system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include <stdint.h>
__global__ void row_contiguous_kernel(float* dst, const uint8_t* src,
int width, int height)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
int c = blockIdx.z;
int channels = gridDim.z;
if(x >= width || y >= height)
return;
dst[(c*height + y)*width + x] = 1.f/255.f * src[(y*width + x)*channels + c];
}
void make_row_contiguous(float* dst, const uint8_t* src,
int width, int height, int channels)
{
int block = 32;
dim3 gridDim((width+block-1)/block, (height+block-1)/block, channels);
dim3 blockDim(block, block, 1);
row_contiguous_kernel<<<gridDim, blockDim>>>(dst, src, width, height);
} | code for sm_80
Function : _Z21row_contiguous_kernelPfPKhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ S2R R7, SR_CTAID.Z ; /* 0x0000000000077919 */
/* 0x000e220000002700 */
/*00b0*/ IMAD R2, R3, c[0x0][0x170], R0 ; /* 0x00005c0003027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R2, R2, c[0x0][0x14], R7 ; /* 0x0000050002027a24 */
/* 0x001fca00078e0207 */
/*00e0*/ IADD3 R4, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0002057a11 */
/* 0x000fca00000f0eff */
/*0100*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0110*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0120*/ IMAD R3, R7, c[0x0][0x174], R3 ; /* 0x00005d0007037a24 */
/* 0x000fc800078e0203 */
/*0130*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fca00078e0200 */
/*0140*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0202 */
/*0150*/ I2F.U16 R6, R4 ; /* 0x0000000400067306 */
/* 0x004e260000101000 */
/*0160*/ FMUL R7, R6, 0.0039215688593685626984 ; /* 0x3b80808106077820 */
/* 0x001fca0000400000 */
/*0170*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include <stdint.h>
__global__ void row_contiguous_kernel(float* dst, const uint8_t* src,
int width, int height)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
int c = blockIdx.z;
int channels = gridDim.z;
if(x >= width || y >= height)
return;
dst[(c*height + y)*width + x] = 1.f/255.f * src[(y*width + x)*channels + c];
}
void make_row_contiguous(float* dst, const uint8_t* src,
int width, int height, int channels)
{
int block = 32;
dim3 gridDim((width+block-1)/block, (height+block-1)/block, channels);
dim3 blockDim(block, block, 1);
row_contiguous_kernel<<<gridDim, blockDim>>>(dst, src, width, height);
} | .file "tmpxft_001804a8_00000000-6_extra_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii
.type _Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii, @function
_Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21row_contiguous_kernelPfPKhii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii, .-_Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii
.globl _Z21row_contiguous_kernelPfPKhii
.type _Z21row_contiguous_kernelPfPKhii, @function
_Z21row_contiguous_kernelPfPKhii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z21row_contiguous_kernelPfPKhii, .-_Z21row_contiguous_kernelPfPKhii
.globl _Z19make_row_contiguousPfPKhiii
.type _Z19make_row_contiguousPfPKhiii, @function
_Z19make_row_contiguousPfPKhiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %esi
leal 62(%rdx), %eax
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 8(%rsp)
leal 62(%rcx), %eax
movl %ecx, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 12(%rsp)
movl $32, 20(%rsp)
movl $32, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z19make_row_contiguousPfPKhiii, .-_Z19make_row_contiguousPfPKhiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21row_contiguous_kernelPfPKhii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21row_contiguous_kernelPfPKhii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include <stdint.h>
__global__ void row_contiguous_kernel(float* dst, const uint8_t* src,
int width, int height)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
int c = blockIdx.z;
int channels = gridDim.z;
if(x >= width || y >= height)
return;
dst[(c*height + y)*width + x] = 1.f/255.f * src[(y*width + x)*channels + c];
}
void make_row_contiguous(float* dst, const uint8_t* src,
int width, int height, int channels)
{
int block = 32;
dim3 gridDim((width+block-1)/block, (height+block-1)/block, channels);
dim3 blockDim(block, block, 1);
row_contiguous_kernel<<<gridDim, blockDim>>>(dst, src, width, height);
} | #include "hip/hip_runtime.h"
#include <stdint.h>
__global__ void row_contiguous_kernel(float* dst, const uint8_t* src,
int width, int height)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
int c = blockIdx.z;
int channels = gridDim.z;
if(x >= width || y >= height)
return;
dst[(c*height + y)*width + x] = 1.f/255.f * src[(y*width + x)*channels + c];
}
void make_row_contiguous(float* dst, const uint8_t* src,
int width, int height, int channels)
{
int block = 32;
dim3 gridDim((width+block-1)/block, (height+block-1)/block, channels);
dim3 blockDim(block, block, 1);
row_contiguous_kernel<<<gridDim, blockDim>>>(dst, src, width, height);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdint.h>
__global__ void row_contiguous_kernel(float* dst, const uint8_t* src,
int width, int height)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
int c = blockIdx.z;
int channels = gridDim.z;
if(x >= width || y >= height)
return;
dst[(c*height + y)*width + x] = 1.f/255.f * src[(y*width + x)*channels + c];
}
void make_row_contiguous(float* dst, const uint8_t* src,
int width, int height, int channels)
{
int block = 32;
dim3 gridDim((width+block-1)/block, (height+block-1)/block, channels);
dim3 blockDim(block, block, 1);
row_contiguous_kernel<<<gridDim, blockDim>>>(dst, src, width, height);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21row_contiguous_kernelPfPKhii
.globl _Z21row_contiguous_kernelPfPKhii
.p2align 8
.type _Z21row_contiguous_kernelPfPKhii,@function
_Z21row_contiguous_kernelPfPKhii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s8, s0, 24
s_addc_u32 s9, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s13, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s2, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b32 s5, s[8:9], 0x8
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s5, v2, s[4:5]
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v2, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
global_load_u8 v5, v[2:3], off
v_mad_u64_u32 v[2:3], null, s4, s7, v[1:2]
v_mad_u64_u32 v[3:4], null, v2, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v2, v5
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, 0x3b808081, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21row_contiguous_kernelPfPKhii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21row_contiguous_kernelPfPKhii, .Lfunc_end0-_Z21row_contiguous_kernelPfPKhii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21row_contiguous_kernelPfPKhii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21row_contiguous_kernelPfPKhii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdint.h>
__global__ void row_contiguous_kernel(float* dst, const uint8_t* src,
int width, int height)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
int c = blockIdx.z;
int channels = gridDim.z;
if(x >= width || y >= height)
return;
dst[(c*height + y)*width + x] = 1.f/255.f * src[(y*width + x)*channels + c];
}
void make_row_contiguous(float* dst, const uint8_t* src,
int width, int height, int channels)
{
int block = 32;
dim3 gridDim((width+block-1)/block, (height+block-1)/block, channels);
dim3 blockDim(block, block, 1);
row_contiguous_kernel<<<gridDim, blockDim>>>(dst, src, width, height);
} | .text
.file "extra_kernels.hip"
.globl _Z36__device_stub__row_contiguous_kernelPfPKhii # -- Begin function _Z36__device_stub__row_contiguous_kernelPfPKhii
.p2align 4, 0x90
.type _Z36__device_stub__row_contiguous_kernelPfPKhii,@function
_Z36__device_stub__row_contiguous_kernelPfPKhii: # @_Z36__device_stub__row_contiguous_kernelPfPKhii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21row_contiguous_kernelPfPKhii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__row_contiguous_kernelPfPKhii, .Lfunc_end0-_Z36__device_stub__row_contiguous_kernelPfPKhii
.cfi_endproc
# -- End function
.globl _Z19make_row_contiguousPfPKhiii # -- Begin function _Z19make_row_contiguousPfPKhiii
.p2align 4, 0x90
.type _Z19make_row_contiguousPfPKhiii,@function
_Z19make_row_contiguousPfPKhiii: # @_Z19make_row_contiguousPfPKhiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movl %edx, %r14d
movq %rsi, %r15
leal 31(%r14), %eax
leal 62(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
leal 31(%rbx), %edx
leal 62(%rbx), %eax
testl %edx, %edx
cmovnsl %edx, %eax
movq %rdi, %r12
sarl $5, %eax
shlq $32, %rax
orq %rcx, %rax
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %rax, %rdi
movl %r8d, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movl %r14d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21row_contiguous_kernelPfPKhii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z19make_row_contiguousPfPKhiii, .Lfunc_end1-_Z19make_row_contiguousPfPKhiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21row_contiguous_kernelPfPKhii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21row_contiguous_kernelPfPKhii,@object # @_Z21row_contiguous_kernelPfPKhii
.section .rodata,"a",@progbits
.globl _Z21row_contiguous_kernelPfPKhii
.p2align 3, 0x0
_Z21row_contiguous_kernelPfPKhii:
.quad _Z36__device_stub__row_contiguous_kernelPfPKhii
.size _Z21row_contiguous_kernelPfPKhii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21row_contiguous_kernelPfPKhii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__row_contiguous_kernelPfPKhii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21row_contiguous_kernelPfPKhii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21row_contiguous_kernelPfPKhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ S2R R7, SR_CTAID.Z ; /* 0x0000000000077919 */
/* 0x000e220000002700 */
/*00b0*/ IMAD R2, R3, c[0x0][0x170], R0 ; /* 0x00005c0003027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R2, R2, c[0x0][0x14], R7 ; /* 0x0000050002027a24 */
/* 0x001fca00078e0207 */
/*00e0*/ IADD3 R4, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0002057a11 */
/* 0x000fca00000f0eff */
/*0100*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0110*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0120*/ IMAD R3, R7, c[0x0][0x174], R3 ; /* 0x00005d0007037a24 */
/* 0x000fc800078e0203 */
/*0130*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fca00078e0200 */
/*0140*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0202 */
/*0150*/ I2F.U16 R6, R4 ; /* 0x0000000400067306 */
/* 0x004e260000101000 */
/*0160*/ FMUL R7, R6, 0.0039215688593685626984 ; /* 0x3b80808106077820 */
/* 0x001fca0000400000 */
/*0170*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21row_contiguous_kernelPfPKhii
.globl _Z21row_contiguous_kernelPfPKhii
.p2align 8
.type _Z21row_contiguous_kernelPfPKhii,@function
_Z21row_contiguous_kernelPfPKhii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s8, s0, 24
s_addc_u32 s9, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s13, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s2, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b32 s5, s[8:9], 0x8
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s5, v2, s[4:5]
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v2, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
global_load_u8 v5, v[2:3], off
v_mad_u64_u32 v[2:3], null, s4, s7, v[1:2]
v_mad_u64_u32 v[3:4], null, v2, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v2, v5
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, 0x3b808081, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21row_contiguous_kernelPfPKhii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21row_contiguous_kernelPfPKhii, .Lfunc_end0-_Z21row_contiguous_kernelPfPKhii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21row_contiguous_kernelPfPKhii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21row_contiguous_kernelPfPKhii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001804a8_00000000-6_extra_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii
.type _Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii, @function
_Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21row_contiguous_kernelPfPKhii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii, .-_Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii
.globl _Z21row_contiguous_kernelPfPKhii
.type _Z21row_contiguous_kernelPfPKhii, @function
_Z21row_contiguous_kernelPfPKhii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z21row_contiguous_kernelPfPKhii, .-_Z21row_contiguous_kernelPfPKhii
.globl _Z19make_row_contiguousPfPKhiii
.type _Z19make_row_contiguousPfPKhiii, @function
_Z19make_row_contiguousPfPKhiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %esi
leal 62(%rdx), %eax
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 8(%rsp)
leal 62(%rcx), %eax
movl %ecx, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 12(%rsp)
movl $32, 20(%rsp)
movl $32, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z46__device_stub__Z21row_contiguous_kernelPfPKhiiPfPKhii
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z19make_row_contiguousPfPKhiii, .-_Z19make_row_contiguousPfPKhiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21row_contiguous_kernelPfPKhii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21row_contiguous_kernelPfPKhii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "extra_kernels.hip"
.globl _Z36__device_stub__row_contiguous_kernelPfPKhii # -- Begin function _Z36__device_stub__row_contiguous_kernelPfPKhii
.p2align 4, 0x90
.type _Z36__device_stub__row_contiguous_kernelPfPKhii,@function
_Z36__device_stub__row_contiguous_kernelPfPKhii: # @_Z36__device_stub__row_contiguous_kernelPfPKhii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21row_contiguous_kernelPfPKhii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__row_contiguous_kernelPfPKhii, .Lfunc_end0-_Z36__device_stub__row_contiguous_kernelPfPKhii
.cfi_endproc
# -- End function
.globl _Z19make_row_contiguousPfPKhiii # -- Begin function _Z19make_row_contiguousPfPKhiii
.p2align 4, 0x90
.type _Z19make_row_contiguousPfPKhiii,@function
_Z19make_row_contiguousPfPKhiii: # @_Z19make_row_contiguousPfPKhiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movl %edx, %r14d
movq %rsi, %r15
leal 31(%r14), %eax
leal 62(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
leal 31(%rbx), %edx
leal 62(%rbx), %eax
testl %edx, %edx
cmovnsl %edx, %eax
movq %rdi, %r12
sarl $5, %eax
shlq $32, %rax
orq %rcx, %rax
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %rax, %rdi
movl %r8d, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movl %r14d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21row_contiguous_kernelPfPKhii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z19make_row_contiguousPfPKhiii, .Lfunc_end1-_Z19make_row_contiguousPfPKhiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21row_contiguous_kernelPfPKhii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21row_contiguous_kernelPfPKhii,@object # @_Z21row_contiguous_kernelPfPKhii
.section .rodata,"a",@progbits
.globl _Z21row_contiguous_kernelPfPKhii
.p2align 3, 0x0
_Z21row_contiguous_kernelPfPKhii:
.quad _Z36__device_stub__row_contiguous_kernelPfPKhii
.size _Z21row_contiguous_kernelPfPKhii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21row_contiguous_kernelPfPKhii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__row_contiguous_kernelPfPKhii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21row_contiguous_kernelPfPKhii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
#include <thrust/transform.h>
#include <iostream>
#define N 64
struct User_Multiple
{
__host__ __device__ int operator()(const int &x, const int &y){
return x * y;
}
};
int main()
{
thrust::device_vector<int> array_X(N);
thrust::device_vector<int> array_Y(N);
thrust::device_vector<int> array_out(N);
thrust::fill(array_X.begin(), array_X.end(),10);
thrust::sequence(array_Y.begin(), array_Y.end());
thrust::transform(array_X.begin(), array_X.end(), array_Y.begin(), array_out.begin(), User_Multiple());
std::cout << "array_out[" << N << "] = ";
for(int i=0; i<N; i++){
if(i < N-1)
std::cout << array_out[i] << ", ";
else
std::cout << array_out[i] << std::endl;
}
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEESF_SF_NS9_14no_stencil_tagE13User_MultipleNS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R6, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R7, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000077a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ IMAD R9, R0, R9, RZ ; /* 0x0000000900097224 */
/* 0x004fca00078e02ff */
/*01f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R6, [R6.64+0x400] ; /* 0x0004000406067981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64+0x400] ; /* 0x0004000404057981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD R9, R6, R5, RZ ; /* 0x0000000506097224 */
/* 0x005fca00078e02ff */
/*0250*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD R9, R0, R9, RZ ; /* 0x0000000900097224 */
/* 0x004fca00078e02ff */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02b0*/ LDG.E R0, [R6.64+0x400] ; /* 0x0004000406007981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R11, [R4.64+0x400] ; /* 0x00040004040b7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ IMAD R11, R0, R11, RZ ; /* 0x0000000b000b7224 */
/* 0x004fca00078e02ff */
/*02e0*/ STG.E [R2.64+0x400], R11 ; /* 0x0004000b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub10__tabulate7functorINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEENS7_6system6detail7generic6detail22compute_sequence_valueIivEElEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R4, R4, 0x200, RZ ; /* 0x0000020004047825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R6, P1, -R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004067a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R7, P2, R4, R9, RZ ; /* 0x0000000904077210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R3, ~R5, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005037a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R0, RZ, RZ, R5, P2 ; /* 0x000000ffff007224 */
/* 0x000fe200010e0605 */
/*00a0*/ LEA R2, P1, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fc40003f04300 */
/*00c0*/ LEA.HI.X R3, R7, c[0x0][0x16c], R0, 0x2, P1 ; /* 0x00005b0007037a11 */
/* 0x000fd600008f1400 */
/*00d0*/ @P0 BRA 0x1d0 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R8, RZ, 0x1f, R6 ; /* 0x0000001fff087819 */
/* 0x000fe40000011406 */
/*0100*/ IADD3 R9, R9, 0x100, RZ ; /* 0x0000010009097810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04300 */
/*0120*/ @P0 IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff000624 */
/* 0x000fc800078e00ff */
/*0130*/ @P0 IMAD R7, R7, R0, c[0x0][0x170] ; /* 0x00005c0007070624 */
/* 0x000fca00078e0200 */
/*0140*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fc80003f04070 */
/*0160*/ ISETP.GT.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04300 */
/*0170*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.IADD R5, R4, 0x1, R9 ; /* 0x0000000104057824 */
/* 0x001fe400078e0209 */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD R5, R5, R0, c[0x0][0x170] ; /* 0x00005c0005057624 */
/* 0x000fca00078e0200 */
/*01b0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R5, R4, 0x100, R9 ; /* 0x0000010004057810 */
/* 0x000fe20007ffe009 */
/*01e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD R7, R7, R0.reuse, c[0x0][0x170] ; /* 0x00005c0007077624 */
/* 0x080fe400078e0200 */
/*0200*/ IMAD R5, R5, R0, c[0x0][0x170] ; /* 0x00005c0005057624 */
/* 0x000fc600078e0200 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0220*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub6__fill7functorINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04300 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
#include <thrust/transform.h>
#include <iostream>
#define N 64
struct User_Multiple
{
__host__ __device__ int operator()(const int &x, const int &y){
return x * y;
}
};
int main()
{
thrust::device_vector<int> array_X(N);
thrust::device_vector<int> array_Y(N);
thrust::device_vector<int> array_out(N);
thrust::fill(array_X.begin(), array_X.end(),10);
thrust::sequence(array_Y.begin(), array_Y.end());
thrust::transform(array_X.begin(), array_X.end(), array_Y.begin(), array_out.begin(), User_Multiple());
std::cout << "array_out[" << N << "] = ";
for(int i=0; i<N; i++){
if(i < N-1)
std::cout << array_out[i] << ", ";
else
std::cout << array_out[i] << std::endl;
}
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
#include <thrust/transform.h>
#include <iostream>
#define N 64
struct User_Multiple
{
__host__ __device__ int operator()(const int &x, const int &y){
return x * y;
}
};
int main()
{
thrust::device_vector<int> array_X(N);
thrust::device_vector<int> array_Y(N);
thrust::device_vector<int> array_out(N);
thrust::fill(array_X.begin(), array_X.end(),10);
thrust::sequence(array_Y.begin(), array_Y.end());
thrust::transform(array_X.begin(), array_X.end(), array_Y.begin(), array_out.begin(), User_Multiple());
std::cout << "array_out[" << N << "] = ";
for(int i=0; i<N; i++){
if(i < N-1)
std::cout << array_out[i] << ", ";
else
std::cout << array_out[i] << std::endl;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
#include <thrust/transform.h>
#include <iostream>
#define N 64
struct User_Multiple
{
__host__ __device__ int operator()(const int &x, const int &y){
return x * y;
}
};
int main()
{
thrust::device_vector<int> array_X(N);
thrust::device_vector<int> array_Y(N);
thrust::device_vector<int> array_out(N);
thrust::fill(array_X.begin(), array_X.end(),10);
thrust::sequence(array_Y.begin(), array_Y.end());
thrust::transform(array_X.begin(), array_X.end(), array_Y.begin(), array_out.begin(), User_Multiple());
std::cout << "array_out[" << N << "] = ";
for(int i=0; i<N; i++){
if(i < N-1)
std::cout << array_out[i] << ", ";
else
std::cout << array_out[i] << std::endl;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s7, v0, s[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo
flat_store_b32 v[0:1], v3
.LBB2_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,comdat
.Lfunc_end2:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_, .Lfunc_end2-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v2, v3, v2
flat_store_b32 v[0:1], v2
.LBB3_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_,comdat
.Lfunc_end3:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_, .Lfunc_end3-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIiEEEES9_S9_NS3_14no_stencil_tagE13User_MultipleNS3_21always_true_predicateEEElLj1EEEvT0_T1_SF_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <sys/time.h>
#include <time.h>
#include <math.h>
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
} }
double w_time()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec + tv.tv_usec * 1E-6;
}
__global__ void init(float *a, float *b)
{
a[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
b[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
}
__global__ void compute(float *a, float *b, float *c)
{
c[threadIdx.x + blockDim.x * blockIdx.x] = a[threadIdx.x + blockDim.x * blockIdx.x] + b[threadIdx.x + blockDim.x * blockIdx.x];
}
int main()
{
int blocks;
int th_p_block;
int N = blocks * th_p_block;
float *a_device;
float *b_device;
float *c_device;
float *buffer_host;
float elapsedTime;
int count = 10;
int start = pow(2, count++);
int end = pow(2, 23); // in the task 2^23
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
cudaEventCreate(&startEvent);
cudaEventCreate(&stopEvent);
while (start < end) {
printf("start = %d\n", start);
blocks = start;
th_p_block = 1;
N = blocks * th_p_block;
while (th_p_block <= 1024) {
// printf("N = %d\tblocks = %d\tth_p_block = %d\n", N, blocks, th_p_block);
// elapsedTime = 0;
buffer_host = (float *)malloc(N * sizeof(float));
CUDA_CHECK_RETURN(cudaMalloc(&a_device, N * sizeof(float)));
CUDA_CHECK_RETURN(cudaMalloc(&b_device, N * sizeof(float)));
CUDA_CHECK_RETURN(cudaMalloc(&c_device, N * sizeof(float)));
init<<<blocks, th_p_block>>>(a_device, b_device);
// elapsedTime -= w_time();
cudaEventRecord(startEvent, 0);
compute<<<blocks, th_p_block>>>(a_device, b_device, c_device);
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// CUDA_CHECK_RETURN(cudaDeviceSynchronize());
CUDA_CHECK_RETURN(cudaGetLastError());
// elapsedTime += w_time();
printf("%f\n", elapsedTime);
CUDA_CHECK_RETURN(cudaMemcpy(buffer_host, c_device, N * sizeof(float), cudaMemcpyDeviceToHost));
free(buffer_host);
cudaFree(a_device);
cudaFree(b_device);
cudaFree(c_device);
blocks /= 2;
th_p_block *= 2;
N = blocks * th_p_block;
}
// start += 32;
start = pow(2, count++);
printf("\n");
}
cudaEventDestroy(startEvent);
cudaEventDestroy(stopEvent);
return 0;
} | code for sm_80
Function : _Z7computePfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4initPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ I2F.U32 R7, R0 ; /* 0x0000000000077306 */
/* 0x000e220000201000 */
/*0070*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0005 */
/*0080*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0005 */
/*0090*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101904 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <sys/time.h>
#include <time.h>
#include <math.h>
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
} }
double w_time()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec + tv.tv_usec * 1E-6;
}
__global__ void init(float *a, float *b)
{
a[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
b[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
}
__global__ void compute(float *a, float *b, float *c)
{
c[threadIdx.x + blockDim.x * blockIdx.x] = a[threadIdx.x + blockDim.x * blockIdx.x] + b[threadIdx.x + blockDim.x * blockIdx.x];
}
int main()
{
int blocks;
int th_p_block;
int N = blocks * th_p_block;
float *a_device;
float *b_device;
float *c_device;
float *buffer_host;
float elapsedTime;
int count = 10;
int start = pow(2, count++);
int end = pow(2, 23); // in the task 2^23
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
cudaEventCreate(&startEvent);
cudaEventCreate(&stopEvent);
while (start < end) {
printf("start = %d\n", start);
blocks = start;
th_p_block = 1;
N = blocks * th_p_block;
while (th_p_block <= 1024) {
// printf("N = %d\tblocks = %d\tth_p_block = %d\n", N, blocks, th_p_block);
// elapsedTime = 0;
buffer_host = (float *)malloc(N * sizeof(float));
CUDA_CHECK_RETURN(cudaMalloc(&a_device, N * sizeof(float)));
CUDA_CHECK_RETURN(cudaMalloc(&b_device, N * sizeof(float)));
CUDA_CHECK_RETURN(cudaMalloc(&c_device, N * sizeof(float)));
init<<<blocks, th_p_block>>>(a_device, b_device);
// elapsedTime -= w_time();
cudaEventRecord(startEvent, 0);
compute<<<blocks, th_p_block>>>(a_device, b_device, c_device);
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// CUDA_CHECK_RETURN(cudaDeviceSynchronize());
CUDA_CHECK_RETURN(cudaGetLastError());
// elapsedTime += w_time();
printf("%f\n", elapsedTime);
CUDA_CHECK_RETURN(cudaMemcpy(buffer_host, c_device, N * sizeof(float), cudaMemcpyDeviceToHost));
free(buffer_host);
cudaFree(a_device);
cudaFree(b_device);
cudaFree(c_device);
blocks /= 2;
th_p_block *= 2;
N = blocks * th_p_block;
}
// start += 32;
start = pow(2, count++);
printf("\n");
}
cudaEventDestroy(startEvent);
cudaEventDestroy(stopEvent);
return 0;
} | .file "tmpxft_00059e54_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6w_timev
.type _Z6w_timev, @function
_Z6w_timev:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6w_timev, .-_Z6w_timev
.globl _Z25__device_stub__Z4initPfS_PfS_
.type _Z25__device_stub__Z4initPfS_PfS_, @function
_Z25__device_stub__Z4initPfS_PfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4initPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z25__device_stub__Z4initPfS_PfS_, .-_Z25__device_stub__Z4initPfS_PfS_
.globl _Z4initPfS_
.type _Z4initPfS_, @function
_Z4initPfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4initPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4initPfS_, .-_Z4initPfS_
.globl _Z30__device_stub__Z7computePfS_S_PfS_S_
.type _Z30__device_stub__Z7computePfS_S_PfS_S_, @function
_Z30__device_stub__Z7computePfS_S_PfS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z30__device_stub__Z7computePfS_S_PfS_S_, .-_Z30__device_stub__Z7computePfS_S_PfS_S_
.globl _Z7computePfS_S_
.type _Z7computePfS_S_, @function
_Z7computePfS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7computePfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7computePfS_S_, .-_Z7computePfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "start = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/hegemonies/PGU/master/2lab/main.cu"
.align 8
.LC3:
.string "Error %s at line %d in file %s\n"
.section .rodata.str1.1
.LC4:
.string "%f\n"
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $1024, %r12d
movl $11, 12(%rsp)
jmp .L32
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %r9
movl $65, %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %r9
movl $66, %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %r9
movl $67, %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z25__device_stub__Z4initPfS_PfS_
jmp .L27
.L44:
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z7computePfS_S_PfS_S_
.L28:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %r12d, %ebx
shrl $31, %ebx
addl %r12d, %ebx
sarl %ebx
movl %ebx, %r12d
addl %ebp, %ebp
imull %ebp, %ebx
cmpl $1024, %ebp
jg .L39
.L31:
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L42
movl %ebp, %r15d
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r12d, %r14d
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L27:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L28
jmp .L44
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %r9
movl $82, %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %r9
movl $87, %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl 12(%rsp), %eax
leal 1(%rax), %ebx
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd .LC5(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r12d
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $8388607, %r12d
jg .L45
movl %ebx, 12(%rsp)
.L32:
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %ebx
movl $1, %ebp
jmp .L31
.L45:
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z7computePfS_S_"
.LC8:
.string "_Z4initPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC5:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <sys/time.h>
#include <time.h>
#include <math.h>
#define CUDA_CHECK_RETURN(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
} }
double w_time()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec + tv.tv_usec * 1E-6;
}
__global__ void init(float *a, float *b)
{
a[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
b[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
}
__global__ void compute(float *a, float *b, float *c)
{
c[threadIdx.x + blockDim.x * blockIdx.x] = a[threadIdx.x + blockDim.x * blockIdx.x] + b[threadIdx.x + blockDim.x * blockIdx.x];
}
int main()
{
int blocks;
int th_p_block;
int N = blocks * th_p_block;
float *a_device;
float *b_device;
float *c_device;
float *buffer_host;
float elapsedTime;
int count = 10;
int start = pow(2, count++);
int end = pow(2, 23); // in the task 2^23
cudaEvent_t startEvent;
cudaEvent_t stopEvent;
cudaEventCreate(&startEvent);
cudaEventCreate(&stopEvent);
while (start < end) {
printf("start = %d\n", start);
blocks = start;
th_p_block = 1;
N = blocks * th_p_block;
while (th_p_block <= 1024) {
// printf("N = %d\tblocks = %d\tth_p_block = %d\n", N, blocks, th_p_block);
// elapsedTime = 0;
buffer_host = (float *)malloc(N * sizeof(float));
CUDA_CHECK_RETURN(cudaMalloc(&a_device, N * sizeof(float)));
CUDA_CHECK_RETURN(cudaMalloc(&b_device, N * sizeof(float)));
CUDA_CHECK_RETURN(cudaMalloc(&c_device, N * sizeof(float)));
init<<<blocks, th_p_block>>>(a_device, b_device);
// elapsedTime -= w_time();
cudaEventRecord(startEvent, 0);
compute<<<blocks, th_p_block>>>(a_device, b_device, c_device);
cudaEventRecord(stopEvent, 0);
cudaEventSynchronize(stopEvent);
cudaEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// CUDA_CHECK_RETURN(cudaDeviceSynchronize());
CUDA_CHECK_RETURN(cudaGetLastError());
// elapsedTime += w_time();
printf("%f\n", elapsedTime);
CUDA_CHECK_RETURN(cudaMemcpy(buffer_host, c_device, N * sizeof(float), cudaMemcpyDeviceToHost));
free(buffer_host);
cudaFree(a_device);
cudaFree(b_device);
cudaFree(c_device);
blocks /= 2;
th_p_block *= 2;
N = blocks * th_p_block;
}
// start += 32;
start = pow(2, count++);
printf("\n");
}
cudaEventDestroy(startEvent);
cudaEventDestroy(stopEvent);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#include <time.h>
#include <math.h>
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
} }
double w_time()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec + tv.tv_usec * 1E-6;
}
__global__ void init(float *a, float *b)
{
a[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
b[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
}
__global__ void compute(float *a, float *b, float *c)
{
c[threadIdx.x + blockDim.x * blockIdx.x] = a[threadIdx.x + blockDim.x * blockIdx.x] + b[threadIdx.x + blockDim.x * blockIdx.x];
}
int main()
{
int blocks;
int th_p_block;
int N = blocks * th_p_block;
float *a_device;
float *b_device;
float *c_device;
float *buffer_host;
float elapsedTime;
int count = 10;
int start = pow(2, count++);
int end = pow(2, 23); // in the task 2^23
hipEvent_t startEvent;
hipEvent_t stopEvent;
hipEventCreate(&startEvent);
hipEventCreate(&stopEvent);
while (start < end) {
printf("start = %d\n", start);
blocks = start;
th_p_block = 1;
N = blocks * th_p_block;
while (th_p_block <= 1024) {
// printf("N = %d\tblocks = %d\tth_p_block = %d\n", N, blocks, th_p_block);
// elapsedTime = 0;
buffer_host = (float *)malloc(N * sizeof(float));
CUDA_CHECK_RETURN(hipMalloc(&a_device, N * sizeof(float)));
CUDA_CHECK_RETURN(hipMalloc(&b_device, N * sizeof(float)));
CUDA_CHECK_RETURN(hipMalloc(&c_device, N * sizeof(float)));
init<<<blocks, th_p_block>>>(a_device, b_device);
// elapsedTime -= w_time();
hipEventRecord(startEvent, 0);
compute<<<blocks, th_p_block>>>(a_device, b_device, c_device);
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// CUDA_CHECK_RETURN(cudaDeviceSynchronize());
CUDA_CHECK_RETURN(hipGetLastError());
// elapsedTime += w_time();
printf("%f\n", elapsedTime);
CUDA_CHECK_RETURN(hipMemcpy(buffer_host, c_device, N * sizeof(float), hipMemcpyDeviceToHost));
free(buffer_host);
hipFree(a_device);
hipFree(b_device);
hipFree(c_device);
blocks /= 2;
th_p_block *= 2;
N = blocks * th_p_block;
}
// start += 32;
start = pow(2, count++);
printf("\n");
}
hipEventDestroy(startEvent);
hipEventDestroy(stopEvent);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#include <time.h>
#include <math.h>
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
} }
double w_time()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec + tv.tv_usec * 1E-6;
}
__global__ void init(float *a, float *b)
{
a[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
b[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
}
__global__ void compute(float *a, float *b, float *c)
{
c[threadIdx.x + blockDim.x * blockIdx.x] = a[threadIdx.x + blockDim.x * blockIdx.x] + b[threadIdx.x + blockDim.x * blockIdx.x];
}
int main()
{
int blocks;
int th_p_block;
int N = blocks * th_p_block;
float *a_device;
float *b_device;
float *c_device;
float *buffer_host;
float elapsedTime;
int count = 10;
int start = pow(2, count++);
int end = pow(2, 23); // in the task 2^23
hipEvent_t startEvent;
hipEvent_t stopEvent;
hipEventCreate(&startEvent);
hipEventCreate(&stopEvent);
while (start < end) {
printf("start = %d\n", start);
blocks = start;
th_p_block = 1;
N = blocks * th_p_block;
while (th_p_block <= 1024) {
// printf("N = %d\tblocks = %d\tth_p_block = %d\n", N, blocks, th_p_block);
// elapsedTime = 0;
buffer_host = (float *)malloc(N * sizeof(float));
CUDA_CHECK_RETURN(hipMalloc(&a_device, N * sizeof(float)));
CUDA_CHECK_RETURN(hipMalloc(&b_device, N * sizeof(float)));
CUDA_CHECK_RETURN(hipMalloc(&c_device, N * sizeof(float)));
init<<<blocks, th_p_block>>>(a_device, b_device);
// elapsedTime -= w_time();
hipEventRecord(startEvent, 0);
compute<<<blocks, th_p_block>>>(a_device, b_device, c_device);
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// CUDA_CHECK_RETURN(cudaDeviceSynchronize());
CUDA_CHECK_RETURN(hipGetLastError());
// elapsedTime += w_time();
printf("%f\n", elapsedTime);
CUDA_CHECK_RETURN(hipMemcpy(buffer_host, c_device, N * sizeof(float), hipMemcpyDeviceToHost));
free(buffer_host);
hipFree(a_device);
hipFree(b_device);
hipFree(c_device);
blocks /= 2;
th_p_block *= 2;
N = blocks * th_p_block;
}
// start += 32;
start = pow(2, count++);
printf("\n");
}
hipEventDestroy(startEvent);
hipEventDestroy(stopEvent);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4initPfS_
.globl _Z4initPfS_
.p2align 8
.type _Z4initPfS_,@function
_Z4initPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_cvt_f32_u32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4initPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4initPfS_, .Lfunc_end0-_Z4initPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7computePfS_S_
.globl _Z7computePfS_S_
.p2align 8
.type _Z7computePfS_S_,@function
_Z7computePfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7computePfS_S_, .Lfunc_end1-_Z7computePfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4initPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4initPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#include <time.h>
#include <math.h>
#define CUDA_CHECK_RETURN(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
fprintf(stderr, "Error %s at line %d in file %s\n",\
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__);\
exit(1);\
} }
double w_time()
{
struct timeval tv;
gettimeofday(&tv, NULL);
return tv.tv_sec + tv.tv_usec * 1E-6;
}
__global__ void init(float *a, float *b)
{
a[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
b[threadIdx.x + blockDim.x * blockIdx.x] = threadIdx.x + blockDim.x * blockIdx.x;
}
__global__ void compute(float *a, float *b, float *c)
{
c[threadIdx.x + blockDim.x * blockIdx.x] = a[threadIdx.x + blockDim.x * blockIdx.x] + b[threadIdx.x + blockDim.x * blockIdx.x];
}
int main()
{
int blocks;
int th_p_block;
int N = blocks * th_p_block;
float *a_device;
float *b_device;
float *c_device;
float *buffer_host;
float elapsedTime;
int count = 10;
int start = pow(2, count++);
int end = pow(2, 23); // in the task 2^23
hipEvent_t startEvent;
hipEvent_t stopEvent;
hipEventCreate(&startEvent);
hipEventCreate(&stopEvent);
while (start < end) {
printf("start = %d\n", start);
blocks = start;
th_p_block = 1;
N = blocks * th_p_block;
while (th_p_block <= 1024) {
// printf("N = %d\tblocks = %d\tth_p_block = %d\n", N, blocks, th_p_block);
// elapsedTime = 0;
buffer_host = (float *)malloc(N * sizeof(float));
CUDA_CHECK_RETURN(hipMalloc(&a_device, N * sizeof(float)));
CUDA_CHECK_RETURN(hipMalloc(&b_device, N * sizeof(float)));
CUDA_CHECK_RETURN(hipMalloc(&c_device, N * sizeof(float)));
init<<<blocks, th_p_block>>>(a_device, b_device);
// elapsedTime -= w_time();
hipEventRecord(startEvent, 0);
compute<<<blocks, th_p_block>>>(a_device, b_device, c_device);
hipEventRecord(stopEvent, 0);
hipEventSynchronize(stopEvent);
hipEventElapsedTime(&elapsedTime, startEvent, stopEvent);
// CUDA_CHECK_RETURN(cudaDeviceSynchronize());
CUDA_CHECK_RETURN(hipGetLastError());
// elapsedTime += w_time();
printf("%f\n", elapsedTime);
CUDA_CHECK_RETURN(hipMemcpy(buffer_host, c_device, N * sizeof(float), hipMemcpyDeviceToHost));
free(buffer_host);
hipFree(a_device);
hipFree(b_device);
hipFree(c_device);
blocks /= 2;
th_p_block *= 2;
N = blocks * th_p_block;
}
// start += 32;
start = pow(2, count++);
printf("\n");
}
hipEventDestroy(startEvent);
hipEventDestroy(stopEvent);
return 0;
} | .text
.file "main.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6w_timev
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z6w_timev
.p2align 4, 0x90
.type _Z6w_timev,@function
_Z6w_timev: # @_Z6w_timev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6w_timev, .Lfunc_end0-_Z6w_timev
.cfi_endproc
# -- End function
.globl _Z19__device_stub__initPfS_ # -- Begin function _Z19__device_stub__initPfS_
.p2align 4, 0x90
.type _Z19__device_stub__initPfS_,@function
_Z19__device_stub__initPfS_: # @_Z19__device_stub__initPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4initPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__initPfS_, .Lfunc_end1-_Z19__device_stub__initPfS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__computePfS_S_ # -- Begin function _Z22__device_stub__computePfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__computePfS_S_,@function
_Z22__device_stub__computePfS_S_: # @_Z22__device_stub__computePfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__computePfS_S_, .Lfunc_end2-_Z22__device_stub__computePfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $11, %eax
movl $1024, %r12d # imm = 0x400
.p2align 4, 0x90
.LBB3_1: # =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movq %rax, 16(%rsp) # 8-byte Spill
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl $1, %r13d
movl %r12d, %eax
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movslq %eax, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.5: # in Loop: Header=BB3_2 Depth=2
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # in Loop: Header=BB3_2 Depth=2
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_8
# %bb.9: # in Loop: Header=BB3_2 Depth=2
movl %r12d, %r14d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
movl %r13d, %r15d
orq %rax, %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_2 Depth=2
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z4initPfS_, %edi
leaq 128(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11: # in Loop: Header=BB3_2 Depth=2
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12: # in Loop: Header=BB3_2 Depth=2
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z7computePfS_S_, %edi
leaq 128(%rsp), %r9
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13: # in Loop: Header=BB3_2 Depth=2
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 124(%rsp), %rdi
callq hipEventElapsedTime
callq hipGetLastError
testl %eax, %eax
jne .LBB3_14
# %bb.15: # in Loop: Header=BB3_2 Depth=2
movss 124(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movq %rbp, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_16
# %bb.17: # in Loop: Header=BB3_2 Depth=2
movq %rbp, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movl %r12d, %eax
shrl $31, %eax
addl %r12d, %eax
sarl %eax
leal (,%r13,2), %ecx
movl %eax, %r12d
imull %ecx, %eax
cmpl $513, %r13d # imm = 0x201
movl %ecx, %r13d
jb .LBB3_2
# %bb.18: # in Loop: Header=BB3_1 Depth=1
movq 16(%rsp), %rdi # 8-byte Reload
leal 1(%rdi), %ebx
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
# kill: def $edi killed $edi killed $rdi
callq ldexp@PLT
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $10, %edi
callq putchar@PLT
cvttsd2si 16(%rsp), %r12d # 8-byte Folded Reload
movl %ebx, %eax
cmpl $8388608, %r12d # imm = 0x800000
jl .LBB3_1
# %bb.19:
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $65, %ecx
jmp .LBB3_4
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $66, %ecx
jmp .LBB3_4
.LBB3_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $67, %ecx
jmp .LBB3_4
.LBB3_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %ecx
jmp .LBB3_4
.LBB3_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $87, %ecx
.LBB3_4:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initPfS_,@object # @_Z4initPfS_
.section .rodata,"a",@progbits
.globl _Z4initPfS_
.p2align 3, 0x0
_Z4initPfS_:
.quad _Z19__device_stub__initPfS_
.size _Z4initPfS_, 8
.type _Z7computePfS_S_,@object # @_Z7computePfS_S_
.globl _Z7computePfS_S_
.p2align 3, 0x0
_Z7computePfS_S_:
.quad _Z22__device_stub__computePfS_S_
.size _Z7computePfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "start = %d\n"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error %s at line %d in file %s\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/hegemonies/PGU/master/2lab/main.hip"
.size .L.str.2, 93
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f\n"
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initPfS_"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7computePfS_S_"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initPfS_
.addrsig_sym _Z22__device_stub__computePfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initPfS_
.addrsig_sym _Z7computePfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7computePfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4initPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ I2F.U32 R7, R0 ; /* 0x0000000000077306 */
/* 0x000e220000201000 */
/*0070*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0005 */
/*0080*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0005 */
/*0090*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101904 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4initPfS_
.globl _Z4initPfS_
.p2align 8
.type _Z4initPfS_,@function
_Z4initPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_cvt_f32_u32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
global_store_b32 v[2:3], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4initPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4initPfS_, .Lfunc_end0-_Z4initPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7computePfS_S_
.globl _Z7computePfS_S_
.p2align 8
.type _Z7computePfS_S_,@function
_Z7computePfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7computePfS_S_, .Lfunc_end1-_Z7computePfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4initPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4initPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00059e54_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6w_timev
.type _Z6w_timev, @function
_Z6w_timev:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6w_timev, .-_Z6w_timev
.globl _Z25__device_stub__Z4initPfS_PfS_
.type _Z25__device_stub__Z4initPfS_PfS_, @function
_Z25__device_stub__Z4initPfS_PfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4initPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z25__device_stub__Z4initPfS_PfS_, .-_Z25__device_stub__Z4initPfS_PfS_
.globl _Z4initPfS_
.type _Z4initPfS_, @function
_Z4initPfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4initPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4initPfS_, .-_Z4initPfS_
.globl _Z30__device_stub__Z7computePfS_S_PfS_S_
.type _Z30__device_stub__Z7computePfS_S_PfS_S_, @function
_Z30__device_stub__Z7computePfS_S_PfS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computePfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z30__device_stub__Z7computePfS_S_PfS_S_, .-_Z30__device_stub__Z7computePfS_S_PfS_S_
.globl _Z7computePfS_S_
.type _Z7computePfS_S_, @function
_Z7computePfS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7computePfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7computePfS_S_, .-_Z7computePfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "start = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/hegemonies/PGU/master/2lab/main.cu"
.align 8
.LC3:
.string "Error %s at line %d in file %s\n"
.section .rodata.str1.1
.LC4:
.string "%f\n"
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $1024, %r12d
movl $11, 12(%rsp)
jmp .L32
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %r9
movl $65, %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %r9
movl $66, %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %r9
movl $67, %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z25__device_stub__Z4initPfS_PfS_
jmp .L27
.L44:
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z7computePfS_S_PfS_S_
.L28:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %r12d, %ebx
shrl $31, %ebx
addl %r12d, %ebx
sarl %ebx
movl %ebx, %r12d
addl %ebp, %ebp
imull %ebp, %ebx
cmpl $1024, %ebp
jg .L39
.L31:
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L42
movl %ebp, %r15d
movl %ebp, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r12d, %r14d
movl %r12d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L27:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %r14d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L28
jmp .L44
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %r9
movl $82, %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %r9
movl $87, %r8d
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl 12(%rsp), %eax
leal 1(%rax), %ebx
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd .LC5(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r12d
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $8388607, %r12d
jg .L45
movl %ebx, 12(%rsp)
.L32:
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %ebx
movl $1, %ebp
jmp .L31
.L45:
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z7computePfS_S_"
.LC8:
.string "_Z4initPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC5:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6w_timev
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z6w_timev
.p2align 4, 0x90
.type _Z6w_timev,@function
_Z6w_timev: # @_Z6w_timev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6w_timev, .Lfunc_end0-_Z6w_timev
.cfi_endproc
# -- End function
.globl _Z19__device_stub__initPfS_ # -- Begin function _Z19__device_stub__initPfS_
.p2align 4, 0x90
.type _Z19__device_stub__initPfS_,@function
_Z19__device_stub__initPfS_: # @_Z19__device_stub__initPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4initPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__initPfS_, .Lfunc_end1-_Z19__device_stub__initPfS_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__computePfS_S_ # -- Begin function _Z22__device_stub__computePfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__computePfS_S_,@function
_Z22__device_stub__computePfS_S_: # @_Z22__device_stub__computePfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__computePfS_S_, .Lfunc_end2-_Z22__device_stub__computePfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $11, %eax
movl $1024, %r12d # imm = 0x400
.p2align 4, 0x90
.LBB3_1: # =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movq %rax, 16(%rsp) # 8-byte Spill
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl $1, %r13d
movl %r12d, %eax
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movslq %eax, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.5: # in Loop: Header=BB3_2 Depth=2
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_6
# %bb.7: # in Loop: Header=BB3_2 Depth=2
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_8
# %bb.9: # in Loop: Header=BB3_2 Depth=2
movl %r12d, %r14d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
movl %r13d, %r15d
orq %rax, %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_2 Depth=2
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z4initPfS_, %edi
leaq 128(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11: # in Loop: Header=BB3_2 Depth=2
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12: # in Loop: Header=BB3_2 Depth=2
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z7computePfS_S_, %edi
leaq 128(%rsp), %r9
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13: # in Loop: Header=BB3_2 Depth=2
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 124(%rsp), %rdi
callq hipEventElapsedTime
callq hipGetLastError
testl %eax, %eax
jne .LBB3_14
# %bb.15: # in Loop: Header=BB3_2 Depth=2
movss 124(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rsi
movq %rbp, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_16
# %bb.17: # in Loop: Header=BB3_2 Depth=2
movq %rbp, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movl %r12d, %eax
shrl $31, %eax
addl %r12d, %eax
sarl %eax
leal (,%r13,2), %ecx
movl %eax, %r12d
imull %ecx, %eax
cmpl $513, %r13d # imm = 0x201
movl %ecx, %r13d
jb .LBB3_2
# %bb.18: # in Loop: Header=BB3_1 Depth=1
movq 16(%rsp), %rdi # 8-byte Reload
leal 1(%rdi), %ebx
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
# kill: def $edi killed $edi killed $rdi
callq ldexp@PLT
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $10, %edi
callq putchar@PLT
cvttsd2si 16(%rsp), %r12d # 8-byte Folded Reload
movl %ebx, %eax
cmpl $8388608, %r12d # imm = 0x800000
jl .LBB3_1
# %bb.19:
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $65, %ecx
jmp .LBB3_4
.LBB3_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $66, %ecx
jmp .LBB3_4
.LBB3_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $67, %ecx
jmp .LBB3_4
.LBB3_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $82, %ecx
jmp .LBB3_4
.LBB3_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str.2, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $87, %ecx
.LBB3_4:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initPfS_,@object # @_Z4initPfS_
.section .rodata,"a",@progbits
.globl _Z4initPfS_
.p2align 3, 0x0
_Z4initPfS_:
.quad _Z19__device_stub__initPfS_
.size _Z4initPfS_, 8
.type _Z7computePfS_S_,@object # @_Z7computePfS_S_
.globl _Z7computePfS_S_
.p2align 3, 0x0
_Z7computePfS_S_:
.quad _Z22__device_stub__computePfS_S_
.size _Z7computePfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "start = %d\n"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error %s at line %d in file %s\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/hegemonies/PGU/master/2lab/main.hip"
.size .L.str.2, 93
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f\n"
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initPfS_"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7computePfS_S_"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initPfS_
.addrsig_sym _Z22__device_stub__computePfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initPfS_
.addrsig_sym _Z7computePfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
result[i] = l[i] + r[i];
} | code for sm_80
Function : _Z6vecAddPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
result[i] = l[i] + r[i];
} | .file "tmpxft_00010719_00000000-6_loop1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
.type _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m, @function
_Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m, .-_Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
.globl _Z6vecAddPfS_S_m
.type _Z6vecAddPfS_S_m, @function
_Z6vecAddPfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPfS_S_m, .-_Z6vecAddPfS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
result[i] = l[i] + r[i];
} | #include <hip/hip_runtime.h>
__global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
result[i] = l[i] + r[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
result[i] = l[i] + r[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_m
.globl _Z6vecAddPfS_S_m
.p2align 8
.type _Z6vecAddPfS_S_m,@function
_Z6vecAddPfS_S_m:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_m, .Lfunc_end0-_Z6vecAddPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__
void vecAdd(float *l, float *r, float *result, size_t N) {
size_t i = threadIdx.x;
result[i] = l[i] + r[i];
} | .text
.file "loop1.hip"
.globl _Z21__device_stub__vecAddPfS_S_m # -- Begin function _Z21__device_stub__vecAddPfS_S_m
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_m,@function
_Z21__device_stub__vecAddPfS_S_m: # @_Z21__device_stub__vecAddPfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_m, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_m,@object # @_Z6vecAddPfS_S_m
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_m
.p2align 3, 0x0
_Z6vecAddPfS_S_m:
.quad _Z21__device_stub__vecAddPfS_S_m
.size _Z6vecAddPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_m"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0007 */
/*0050*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0007 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0007 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_m
.globl _Z6vecAddPfS_S_m
.p2align 8
.type _Z6vecAddPfS_S_m,@function
_Z6vecAddPfS_S_m:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_m, .Lfunc_end0-_Z6vecAddPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00010719_00000000-6_loop1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
.type _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m, @function
_Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m, .-_Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
.globl _Z6vecAddPfS_S_m
.type _Z6vecAddPfS_S_m, @function
_Z6vecAddPfS_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPfS_S_m, .-_Z6vecAddPfS_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPfS_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "loop1.hip"
.globl _Z21__device_stub__vecAddPfS_S_m # -- Begin function _Z21__device_stub__vecAddPfS_S_m
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_m,@function
_Z21__device_stub__vecAddPfS_S_m: # @_Z21__device_stub__vecAddPfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_m, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_m,@object # @_Z6vecAddPfS_S_m
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_m
.p2align 3, 0x0
_Z6vecAddPfS_S_m:
.quad _Z21__device_stub__vecAddPfS_S_m
.size _Z6vecAddPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_m"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void pinv(float *A, int n)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i >= n) {
return;
}
float a = A[4*i + 0];
float b = A[4*i + 1];
float c = A[4*i + 2];
float d = A[4*i + 3];
float e = a*a + c*c;
float f = a*b + c*d;
float g = a*b + c*d;
float h = b*b + d*d;
float scalar = 1/(e*h - f*g);
float e_i = scalar * h;
float f_i = scalar * (-f);
float g_i = scalar * (-g);
float h_i = scalar * e;
A[4*i + 0] = e_i*a + f_i*b;
A[4*i + 1] = e_i*c + f_i*d;
A[4*i + 2] = g_i*a + h_i*b;
A[4*i + 3] = g_i*c + h_i*d;
} | code for sm_80
Function : _Z4pinvPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64+0xc] ; /* 0x00000c0402007981 */
/* 0x000ee8000c1e1900 */
/*00c0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000f28000c1e1900 */
/*00d0*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000f62000c1e1900 */
/*00e0*/ BSSY B0, 0x240 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*00f0*/ FMUL R6, R5, R5 ; /* 0x0000000505067220 */
/* 0x004fc40000400000 */
/*0100*/ FMUL R8, R5, R0.reuse ; /* 0x0000000005087220 */
/* 0x088fe40000400000 */
/*0110*/ FMUL R9, R0, R0 ; /* 0x0000000000097220 */
/* 0x000fe40000400000 */
/*0120*/ FFMA R6, R7.reuse, R7, R6 ; /* 0x0000000707067223 */
/* 0x050fe40000000006 */
/*0130*/ FFMA R8, R7, R4.reuse, R8 ; /* 0x0000000407087223 */
/* 0x0a0fe40000000008 */
/*0140*/ FFMA R9, R4, R4, R9 ; /* 0x0000000404097223 */
/* 0x000fe40000000009 */
/*0150*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0160*/ FFMA R11, R6, R9, -R10 ; /* 0x00000009060b7223 */
/* 0x000fca000000080a */
/*0170*/ IADD3 R10, R11, 0x1800000, RZ ; /* 0x018000000b0a7810 */
/* 0x000fc80007ffe0ff */
/*0180*/ LOP3.LUT R10, R10, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f8000000a0a7812 */
/* 0x000fc800078ec0ff */
/*0190*/ ISETP.GT.U32.AND P0, PT, R10, 0x1ffffff, PT ; /* 0x01ffffff0a00780c */
/* 0x000fda0003f04070 */
/*01a0*/ @P0 BRA 0x1f0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*01b0*/ MOV R10, 0x1d0 ; /* 0x000001d0000a7802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x340 ; /* 0x0000017000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ IMAD.MOV.U32 R13, RZ, RZ, R12 ; /* 0x000000ffff0d7224 */
/* 0x002fe200078e000c */
/*01e0*/ BRA 0x230 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*01f0*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x000e240000001000 */
/*0200*/ FFMA R12, R11, R10, -1 ; /* 0xbf8000000b0c7423 */
/* 0x001fc8000000000a */
/*0210*/ FADD.FTZ R13, -R12, -RZ ; /* 0x800000ff0c0d7221 */
/* 0x000fc80000010100 */
/*0220*/ FFMA R13, R10, R13, R10 ; /* 0x0000000d0a0d7223 */
/* 0x000fe4000000000a */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ FMUL R10, R8, R13.reuse ; /* 0x0000000d080a7220 */
/* 0x080fe40000400000 */
/*0250*/ FMUL R8, R9, R13.reuse ; /* 0x0000000d09087220 */
/* 0x080fe40000400000 */
/*0260*/ FMUL R13, R6, R13 ; /* 0x0000000d060d7220 */
/* 0x000fe40000400000 */
/*0270*/ FMUL R6, R4, R10.reuse ; /* 0x0000000a04067220 */
/* 0x080fe40000400000 */
/*0280*/ FMUL R9, R0, R10.reuse ; /* 0x0000000a00097220 */
/* 0x080fe40000400000 */
/*0290*/ FMUL R11, R7, R10 ; /* 0x0000000a070b7220 */
/* 0x000fc40000400000 */
/*02a0*/ FMUL R10, R5, R10 ; /* 0x0000000a050a7220 */
/* 0x000fe40000400000 */
/*02b0*/ FFMA R11, R4, R13.reuse, -R11 ; /* 0x0000000d040b7223 */
/* 0x080fe4000000080b */
/*02c0*/ FFMA R7, R7, R8.reuse, -R6 ; /* 0x0000000807077223 */
/* 0x080fe40000000806 */
/*02d0*/ FFMA R9, R5, R8, -R9 ; /* 0x0000000805097223 */
/* 0x000fe20000000809 */
/*02e0*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ FFMA R13, R0, R13, -R10 ; /* 0x0000000d000d7223 */
/* 0x000fc6000000080a */
/*0300*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0310*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe8000c101904 */
/*0320*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x000fe2000c101904 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ SHF.L.U32 R12, R11, 0x1, RZ ; /* 0x000000010b0c7819 */
/* 0x000fe200000006ff */
/*0350*/ BSSY B1, 0x660 ; /* 0x0000030000017945 */
/* 0x000fe60003800000 */
/*0360*/ SHF.R.U32.HI R12, RZ, 0x18, R12 ; /* 0x00000018ff0c7819 */
/* 0x000fc8000001160c */
/*0370*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fda0003f05070 */
/*0380*/ @P0 BRA 0x430 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD.SHL.U32 R12, R11, 0x2, RZ ; /* 0x000000020b0c7824 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fda0003f05270 */
/*03b0*/ @P0 FFMA R13, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b0d0823 */
/* 0x000fe200000000ff */
/*03c0*/ @!P0 MUFU.RCP R12, R11 ; /* 0x0000000b000c8308 */
/* 0x000ff00000001000 */
/*03d0*/ @P0 MUFU.RCP R14, R13 ; /* 0x0000000d000e0308 */
/* 0x000e240000001000 */
/*03e0*/ @P0 FFMA R15, R13, R14, -1 ; /* 0xbf8000000d0f0423 */
/* 0x001fc8000000000e */
/*03f0*/ @P0 FADD.FTZ R15, -R15, -RZ ; /* 0x800000ff0f0f0221 */
/* 0x000fc80000010100 */
/*0400*/ @P0 FFMA R15, R14, R15, R14 ; /* 0x0000000f0e0f0223 */
/* 0x000fc8000000000e */
/*0410*/ @P0 FFMA R12, R15, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000f0c0823 */
/* 0x000fe200000000ff */
/*0420*/ BRA 0x650 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0430*/ IADD3 R13, R12, -0xfd, RZ ; /* 0xffffff030c0d7810 */
/* 0x000fc80007ffe0ff */
/*0440*/ ISETP.GT.U32.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f04070 */
/*0450*/ @P0 BRA 0x640 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0460*/ LOP3.LUT R14, R11, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b0e7812 */
/* 0x000fe200078ec0ff */
/*0470*/ HFMA2.MMA R18, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff127435 */
/* 0x000fc600000001ff */
/*0480*/ LOP3.LUT R14, R14, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f8000000e0e7812 */
/* 0x000fc800078efcff */
/*0490*/ MUFU.RCP R15, R14 ; /* 0x0000000e000f7308 */
/* 0x000e260000001000 */
/*04a0*/ SHF.L.U32 R19, R18, R13, RZ ; /* 0x0000000d12137219 */
/* 0x000fe200000006ff */
/*04b0*/ FFMA R16, R14, R15, -1 ; /* 0xbf8000000e107423 */
/* 0x001fc8000000000f */
/*04c0*/ FADD.FTZ R16, -R16, -RZ ; /* 0x800000ff10107221 */
/* 0x000fc80000010100 */
/*04d0*/ FFMA.RM R17, R15.reuse, R16.reuse, R15.reuse ; /* 0x000000100f117223 */
/* 0x1c0fe4000000400f */
/*04e0*/ FFMA.RP R16, R15, R16, R15 ; /* 0x000000100f107223 */
/* 0x000fc6000000800f */
/*04f0*/ LOP3.LUT R15, R17.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff110f7812 */
/* 0x040fe400078ec0ff */
/*0500*/ FSETP.NEU.FTZ.AND P0, PT, R17, R16, PT ; /* 0x000000101100720b */
/* 0x000fe40003f1d000 */
/*0510*/ LOP3.LUT R16, R15, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000f107812 */
/* 0x000fe400078efcff */
/*0520*/ SEL R15, RZ, 0xffffffff, !P0 ; /* 0xffffffffff0f7807 */
/* 0x000fe40004000000 */
/*0530*/ LOP3.LUT R14, R19, R16, RZ, 0xc0, !PT ; /* 0x00000010130e7212 */
/* 0x000fe400078ec0ff */
/*0540*/ IADD3 R15, -R15, RZ, RZ ; /* 0x000000ff0f0f7210 */
/* 0x000fc40007ffe1ff */
/*0550*/ SHF.R.U32.HI R14, RZ, R13.reuse, R14 ; /* 0x0000000dff0e7219 */
/* 0x080fe4000001160e */
/*0560*/ LOP3.LUT P1, RZ, R15, R13, R16, 0xf8, !PT ; /* 0x0000000d0fff7212 */
/* 0x000fe4000782f810 */
/*0570*/ LOP3.LUT P0, RZ, R14.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010eff7812 */
/* 0x040fe4000780c0ff */
/*0580*/ LOP3.LUT P2, RZ, R14, 0x2, RZ, 0xc0, !PT ; /* 0x000000020eff7812 */
/* 0x000fc8000784c0ff */
/*0590*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*05a0*/ LOP3.LUT P1, RZ, R11, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0bff7812 */
/* 0x000fe4000782c0ff */
/*05b0*/ SEL R13, RZ, 0x1, !P0 ; /* 0x00000001ff0d7807 */
/* 0x000fca0004000000 */
/*05c0*/ IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e0a0d */
/*05d0*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f06270 */
/*05e0*/ IADD3 R13, R12, -0xfc, RZ ; /* 0xffffff040c0d7810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ SHF.R.U32.HI R12, RZ, R13, R16 ; /* 0x0000000dff0c7219 */
/* 0x000fce0000011610 */
/*0600*/ @!P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c8810 */
/* 0x000fc80007ffe0ff */
/*0610*/ @!P1 SHF.L.U32 R12, R12, 0x1, RZ ; /* 0x000000010c0c9819 */
/* 0x000fc800000006ff */
/*0620*/ LOP3.LUT R12, R12, 0x80000000, R11, 0xf8, !PT ; /* 0x800000000c0c7812 */
/* 0x000fe200078ef80b */
/*0630*/ BRA 0x650 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0640*/ MUFU.RCP R12, R11 ; /* 0x0000000b000c7308 */
/* 0x0000640000001000 */
/*0650*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0660*/ MOV R11, 0x0 ; /* 0x00000000000b7802 */
/* 0x001fc80000000f00 */
/*0670*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff9800a007950 */
/* 0x000fea0003c3ffff */
/*0680*/ BRA 0x680; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void pinv(float *A, int n)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i >= n) {
return;
}
float a = A[4*i + 0];
float b = A[4*i + 1];
float c = A[4*i + 2];
float d = A[4*i + 3];
float e = a*a + c*c;
float f = a*b + c*d;
float g = a*b + c*d;
float h = b*b + d*d;
float scalar = 1/(e*h - f*g);
float e_i = scalar * h;
float f_i = scalar * (-f);
float g_i = scalar * (-g);
float h_i = scalar * e;
A[4*i + 0] = e_i*a + f_i*b;
A[4*i + 1] = e_i*c + f_i*d;
A[4*i + 2] = g_i*a + h_i*b;
A[4*i + 3] = g_i*c + h_i*d;
} | .file "tmpxft_000670c6_00000000-6_pinv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4pinvPfiPfi
.type _Z24__device_stub__Z4pinvPfiPfi, @function
_Z24__device_stub__Z4pinvPfiPfi:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4pinvPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z24__device_stub__Z4pinvPfiPfi, .-_Z24__device_stub__Z4pinvPfiPfi
.globl _Z4pinvPfi
.type _Z4pinvPfi, @function
_Z4pinvPfi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4pinvPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z4pinvPfi, .-_Z4pinvPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4pinvPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4pinvPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void pinv(float *A, int n)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i >= n) {
return;
}
float a = A[4*i + 0];
float b = A[4*i + 1];
float c = A[4*i + 2];
float d = A[4*i + 3];
float e = a*a + c*c;
float f = a*b + c*d;
float g = a*b + c*d;
float h = b*b + d*d;
float scalar = 1/(e*h - f*g);
float e_i = scalar * h;
float f_i = scalar * (-f);
float g_i = scalar * (-g);
float h_i = scalar * e;
A[4*i + 0] = e_i*a + f_i*b;
A[4*i + 1] = e_i*c + f_i*d;
A[4*i + 2] = g_i*a + h_i*b;
A[4*i + 3] = g_i*c + h_i*d;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void pinv(float *A, int n)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i >= n) {
return;
}
float a = A[4*i + 0];
float b = A[4*i + 1];
float c = A[4*i + 2];
float d = A[4*i + 3];
float e = a*a + c*c;
float f = a*b + c*d;
float g = a*b + c*d;
float h = b*b + d*d;
float scalar = 1/(e*h - f*g);
float e_i = scalar * h;
float f_i = scalar * (-f);
float g_i = scalar * (-g);
float h_i = scalar * e;
A[4*i + 0] = e_i*a + f_i*b;
A[4*i + 1] = e_i*c + f_i*d;
A[4*i + 2] = g_i*a + h_i*b;
A[4*i + 3] = g_i*c + h_i*d;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void pinv(float *A, int n)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i >= n) {
return;
}
float a = A[4*i + 0];
float b = A[4*i + 1];
float c = A[4*i + 2];
float d = A[4*i + 3];
float e = a*a + c*c;
float f = a*b + c*d;
float g = a*b + c*d;
float h = b*b + d*d;
float scalar = 1/(e*h - f*g);
float e_i = scalar * h;
float f_i = scalar * (-f);
float g_i = scalar * (-g);
float h_i = scalar * e;
A[4*i + 0] = e_i*a + f_i*b;
A[4*i + 1] = e_i*c + f_i*d;
A[4*i + 2] = g_i*a + h_i*b;
A[4*i + 3] = g_i*c + h_i*d;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4pinvPfi
.globl _Z4pinvPfi
.p2align 8
.type _Z4pinvPfi,@function
_Z4pinvPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_or_b32_e32 v4, 2, v0
v_ashrrev_i32_e32 v1, 31, v0
v_or_b32_e32 v6, 3, v0
v_or_b32_e32 v2, 1, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x3
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v[6:7], off
global_load_b32 v10, v[0:1], off
global_load_b32 v11, v[2:3], off
s_waitcnt vmcnt(3)
v_mul_f32_e32 v13, v8, v8
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mul_f32 v12, v8, v9 :: v_dual_fmac_f32 v13, v10, v10
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v12, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v14, v9, v9 :: v_dual_mul_f32 v15, v12, v12
v_fmac_f32_e32 v14, v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v15, v13, v14, -v15
v_div_scale_f32 v16, null, v15, v15, 1.0
v_div_scale_f32 v19, vcc_lo, 1.0, v15, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v17, v16
s_waitcnt_depctr 0xfff
v_fma_f32 v18, -v16, v17, 1.0
v_fmac_f32_e32 v17, v18, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v18, v19, v17
v_fma_f32 v20, -v16, v18, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v18, v20, v17
v_fma_f32 v16, -v16, v18, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v16, v16, v17, v18
v_div_fixup_f32 v15, v16, v15, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e64 v12, v15, -v12
v_mul_f32_e32 v13, v13, v15
v_dual_mul_f32 v14, v14, v15 :: v_dual_mul_f32 v15, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_mul_f32 v16, v9, v12 :: v_dual_mul_f32 v11, v11, v13
v_mul_f32_e32 v9, v9, v13
v_fmac_f32_e32 v15, v10, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v16, v8, v14 :: v_dual_fmac_f32 v11, v10, v12
v_fmac_f32_e32 v9, v8, v12
s_clause 0x3
global_store_b32 v[0:1], v15, off
global_store_b32 v[2:3], v16, off
global_store_b32 v[4:5], v11, off
global_store_b32 v[6:7], v9, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4pinvPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4pinvPfi, .Lfunc_end0-_Z4pinvPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4pinvPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4pinvPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void pinv(float *A, int n)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if(i >= n) {
return;
}
float a = A[4*i + 0];
float b = A[4*i + 1];
float c = A[4*i + 2];
float d = A[4*i + 3];
float e = a*a + c*c;
float f = a*b + c*d;
float g = a*b + c*d;
float h = b*b + d*d;
float scalar = 1/(e*h - f*g);
float e_i = scalar * h;
float f_i = scalar * (-f);
float g_i = scalar * (-g);
float h_i = scalar * e;
A[4*i + 0] = e_i*a + f_i*b;
A[4*i + 1] = e_i*c + f_i*d;
A[4*i + 2] = g_i*a + h_i*b;
A[4*i + 3] = g_i*c + h_i*d;
} | .text
.file "pinv.hip"
.globl _Z19__device_stub__pinvPfi # -- Begin function _Z19__device_stub__pinvPfi
.p2align 4, 0x90
.type _Z19__device_stub__pinvPfi,@function
_Z19__device_stub__pinvPfi: # @_Z19__device_stub__pinvPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4pinvPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__pinvPfi, .Lfunc_end0-_Z19__device_stub__pinvPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4pinvPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4pinvPfi,@object # @_Z4pinvPfi
.section .rodata,"a",@progbits
.globl _Z4pinvPfi
.p2align 3, 0x0
_Z4pinvPfi:
.quad _Z19__device_stub__pinvPfi
.size _Z4pinvPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4pinvPfi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__pinvPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4pinvPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4pinvPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64+0xc] ; /* 0x00000c0402007981 */
/* 0x000ee8000c1e1900 */
/*00c0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000f28000c1e1900 */
/*00d0*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000f62000c1e1900 */
/*00e0*/ BSSY B0, 0x240 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*00f0*/ FMUL R6, R5, R5 ; /* 0x0000000505067220 */
/* 0x004fc40000400000 */
/*0100*/ FMUL R8, R5, R0.reuse ; /* 0x0000000005087220 */
/* 0x088fe40000400000 */
/*0110*/ FMUL R9, R0, R0 ; /* 0x0000000000097220 */
/* 0x000fe40000400000 */
/*0120*/ FFMA R6, R7.reuse, R7, R6 ; /* 0x0000000707067223 */
/* 0x050fe40000000006 */
/*0130*/ FFMA R8, R7, R4.reuse, R8 ; /* 0x0000000407087223 */
/* 0x0a0fe40000000008 */
/*0140*/ FFMA R9, R4, R4, R9 ; /* 0x0000000404097223 */
/* 0x000fe40000000009 */
/*0150*/ FMUL R10, R8, R8 ; /* 0x00000008080a7220 */
/* 0x000fc80000400000 */
/*0160*/ FFMA R11, R6, R9, -R10 ; /* 0x00000009060b7223 */
/* 0x000fca000000080a */
/*0170*/ IADD3 R10, R11, 0x1800000, RZ ; /* 0x018000000b0a7810 */
/* 0x000fc80007ffe0ff */
/*0180*/ LOP3.LUT R10, R10, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f8000000a0a7812 */
/* 0x000fc800078ec0ff */
/*0190*/ ISETP.GT.U32.AND P0, PT, R10, 0x1ffffff, PT ; /* 0x01ffffff0a00780c */
/* 0x000fda0003f04070 */
/*01a0*/ @P0 BRA 0x1f0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*01b0*/ MOV R10, 0x1d0 ; /* 0x000001d0000a7802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x340 ; /* 0x0000017000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ IMAD.MOV.U32 R13, RZ, RZ, R12 ; /* 0x000000ffff0d7224 */
/* 0x002fe200078e000c */
/*01e0*/ BRA 0x230 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*01f0*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x000e240000001000 */
/*0200*/ FFMA R12, R11, R10, -1 ; /* 0xbf8000000b0c7423 */
/* 0x001fc8000000000a */
/*0210*/ FADD.FTZ R13, -R12, -RZ ; /* 0x800000ff0c0d7221 */
/* 0x000fc80000010100 */
/*0220*/ FFMA R13, R10, R13, R10 ; /* 0x0000000d0a0d7223 */
/* 0x000fe4000000000a */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ FMUL R10, R8, R13.reuse ; /* 0x0000000d080a7220 */
/* 0x080fe40000400000 */
/*0250*/ FMUL R8, R9, R13.reuse ; /* 0x0000000d09087220 */
/* 0x080fe40000400000 */
/*0260*/ FMUL R13, R6, R13 ; /* 0x0000000d060d7220 */
/* 0x000fe40000400000 */
/*0270*/ FMUL R6, R4, R10.reuse ; /* 0x0000000a04067220 */
/* 0x080fe40000400000 */
/*0280*/ FMUL R9, R0, R10.reuse ; /* 0x0000000a00097220 */
/* 0x080fe40000400000 */
/*0290*/ FMUL R11, R7, R10 ; /* 0x0000000a070b7220 */
/* 0x000fc40000400000 */
/*02a0*/ FMUL R10, R5, R10 ; /* 0x0000000a050a7220 */
/* 0x000fe40000400000 */
/*02b0*/ FFMA R11, R4, R13.reuse, -R11 ; /* 0x0000000d040b7223 */
/* 0x080fe4000000080b */
/*02c0*/ FFMA R7, R7, R8.reuse, -R6 ; /* 0x0000000807077223 */
/* 0x080fe40000000806 */
/*02d0*/ FFMA R9, R5, R8, -R9 ; /* 0x0000000805097223 */
/* 0x000fe20000000809 */
/*02e0*/ STG.E [R2.64+0x8], R11 ; /* 0x0000080b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ FFMA R13, R0, R13, -R10 ; /* 0x0000000d000d7223 */
/* 0x000fc6000000080a */
/*0300*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0310*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe8000c101904 */
/*0320*/ STG.E [R2.64+0xc], R13 ; /* 0x00000c0d02007986 */
/* 0x000fe2000c101904 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ SHF.L.U32 R12, R11, 0x1, RZ ; /* 0x000000010b0c7819 */
/* 0x000fe200000006ff */
/*0350*/ BSSY B1, 0x660 ; /* 0x0000030000017945 */
/* 0x000fe60003800000 */
/*0360*/ SHF.R.U32.HI R12, RZ, 0x18, R12 ; /* 0x00000018ff0c7819 */
/* 0x000fc8000001160c */
/*0370*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fda0003f05070 */
/*0380*/ @P0 BRA 0x430 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD.SHL.U32 R12, R11, 0x2, RZ ; /* 0x000000020b0c7824 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fda0003f05270 */
/*03b0*/ @P0 FFMA R13, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b0d0823 */
/* 0x000fe200000000ff */
/*03c0*/ @!P0 MUFU.RCP R12, R11 ; /* 0x0000000b000c8308 */
/* 0x000ff00000001000 */
/*03d0*/ @P0 MUFU.RCP R14, R13 ; /* 0x0000000d000e0308 */
/* 0x000e240000001000 */
/*03e0*/ @P0 FFMA R15, R13, R14, -1 ; /* 0xbf8000000d0f0423 */
/* 0x001fc8000000000e */
/*03f0*/ @P0 FADD.FTZ R15, -R15, -RZ ; /* 0x800000ff0f0f0221 */
/* 0x000fc80000010100 */
/*0400*/ @P0 FFMA R15, R14, R15, R14 ; /* 0x0000000f0e0f0223 */
/* 0x000fc8000000000e */
/*0410*/ @P0 FFMA R12, R15, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000f0c0823 */
/* 0x000fe200000000ff */
/*0420*/ BRA 0x650 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0430*/ IADD3 R13, R12, -0xfd, RZ ; /* 0xffffff030c0d7810 */
/* 0x000fc80007ffe0ff */
/*0440*/ ISETP.GT.U32.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f04070 */
/*0450*/ @P0 BRA 0x640 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0460*/ LOP3.LUT R14, R11, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b0e7812 */
/* 0x000fe200078ec0ff */
/*0470*/ HFMA2.MMA R18, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff127435 */
/* 0x000fc600000001ff */
/*0480*/ LOP3.LUT R14, R14, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f8000000e0e7812 */
/* 0x000fc800078efcff */
/*0490*/ MUFU.RCP R15, R14 ; /* 0x0000000e000f7308 */
/* 0x000e260000001000 */
/*04a0*/ SHF.L.U32 R19, R18, R13, RZ ; /* 0x0000000d12137219 */
/* 0x000fe200000006ff */
/*04b0*/ FFMA R16, R14, R15, -1 ; /* 0xbf8000000e107423 */
/* 0x001fc8000000000f */
/*04c0*/ FADD.FTZ R16, -R16, -RZ ; /* 0x800000ff10107221 */
/* 0x000fc80000010100 */
/*04d0*/ FFMA.RM R17, R15.reuse, R16.reuse, R15.reuse ; /* 0x000000100f117223 */
/* 0x1c0fe4000000400f */
/*04e0*/ FFMA.RP R16, R15, R16, R15 ; /* 0x000000100f107223 */
/* 0x000fc6000000800f */
/*04f0*/ LOP3.LUT R15, R17.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff110f7812 */
/* 0x040fe400078ec0ff */
/*0500*/ FSETP.NEU.FTZ.AND P0, PT, R17, R16, PT ; /* 0x000000101100720b */
/* 0x000fe40003f1d000 */
/*0510*/ LOP3.LUT R16, R15, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000f107812 */
/* 0x000fe400078efcff */
/*0520*/ SEL R15, RZ, 0xffffffff, !P0 ; /* 0xffffffffff0f7807 */
/* 0x000fe40004000000 */
/*0530*/ LOP3.LUT R14, R19, R16, RZ, 0xc0, !PT ; /* 0x00000010130e7212 */
/* 0x000fe400078ec0ff */
/*0540*/ IADD3 R15, -R15, RZ, RZ ; /* 0x000000ff0f0f7210 */
/* 0x000fc40007ffe1ff */
/*0550*/ SHF.R.U32.HI R14, RZ, R13.reuse, R14 ; /* 0x0000000dff0e7219 */
/* 0x080fe4000001160e */
/*0560*/ LOP3.LUT P1, RZ, R15, R13, R16, 0xf8, !PT ; /* 0x0000000d0fff7212 */
/* 0x000fe4000782f810 */
/*0570*/ LOP3.LUT P0, RZ, R14.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010eff7812 */
/* 0x040fe4000780c0ff */
/*0580*/ LOP3.LUT P2, RZ, R14, 0x2, RZ, 0xc0, !PT ; /* 0x000000020eff7812 */
/* 0x000fc8000784c0ff */
/*0590*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*05a0*/ LOP3.LUT P1, RZ, R11, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0bff7812 */
/* 0x000fe4000782c0ff */
/*05b0*/ SEL R13, RZ, 0x1, !P0 ; /* 0x00000001ff0d7807 */
/* 0x000fca0004000000 */
/*05c0*/ IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e0a0d */
/*05d0*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f06270 */
/*05e0*/ IADD3 R13, R12, -0xfc, RZ ; /* 0xffffff040c0d7810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ SHF.R.U32.HI R12, RZ, R13, R16 ; /* 0x0000000dff0c7219 */
/* 0x000fce0000011610 */
/*0600*/ @!P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c8810 */
/* 0x000fc80007ffe0ff */
/*0610*/ @!P1 SHF.L.U32 R12, R12, 0x1, RZ ; /* 0x000000010c0c9819 */
/* 0x000fc800000006ff */
/*0620*/ LOP3.LUT R12, R12, 0x80000000, R11, 0xf8, !PT ; /* 0x800000000c0c7812 */
/* 0x000fe200078ef80b */
/*0630*/ BRA 0x650 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0640*/ MUFU.RCP R12, R11 ; /* 0x0000000b000c7308 */
/* 0x0000640000001000 */
/*0650*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0660*/ MOV R11, 0x0 ; /* 0x00000000000b7802 */
/* 0x001fc80000000f00 */
/*0670*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff9800a007950 */
/* 0x000fea0003c3ffff */
/*0680*/ BRA 0x680; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4pinvPfi
.globl _Z4pinvPfi
.p2align 8
.type _Z4pinvPfi,@function
_Z4pinvPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_or_b32_e32 v4, 2, v0
v_ashrrev_i32_e32 v1, 31, v0
v_or_b32_e32 v6, 3, v0
v_or_b32_e32 v2, 1, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x3
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v[6:7], off
global_load_b32 v10, v[0:1], off
global_load_b32 v11, v[2:3], off
s_waitcnt vmcnt(3)
v_mul_f32_e32 v13, v8, v8
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mul_f32 v12, v8, v9 :: v_dual_fmac_f32 v13, v10, v10
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v12, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v14, v9, v9 :: v_dual_mul_f32 v15, v12, v12
v_fmac_f32_e32 v14, v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v15, v13, v14, -v15
v_div_scale_f32 v16, null, v15, v15, 1.0
v_div_scale_f32 v19, vcc_lo, 1.0, v15, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v17, v16
s_waitcnt_depctr 0xfff
v_fma_f32 v18, -v16, v17, 1.0
v_fmac_f32_e32 v17, v18, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v18, v19, v17
v_fma_f32 v20, -v16, v18, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v18, v20, v17
v_fma_f32 v16, -v16, v18, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v16, v16, v17, v18
v_div_fixup_f32 v15, v16, v15, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e64 v12, v15, -v12
v_mul_f32_e32 v13, v13, v15
v_dual_mul_f32 v14, v14, v15 :: v_dual_mul_f32 v15, v11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_mul_f32 v16, v9, v12 :: v_dual_mul_f32 v11, v11, v13
v_mul_f32_e32 v9, v9, v13
v_fmac_f32_e32 v15, v10, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v16, v8, v14 :: v_dual_fmac_f32 v11, v10, v12
v_fmac_f32_e32 v9, v8, v12
s_clause 0x3
global_store_b32 v[0:1], v15, off
global_store_b32 v[2:3], v16, off
global_store_b32 v[4:5], v11, off
global_store_b32 v[6:7], v9, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4pinvPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4pinvPfi, .Lfunc_end0-_Z4pinvPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4pinvPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4pinvPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000670c6_00000000-6_pinv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4pinvPfiPfi
.type _Z24__device_stub__Z4pinvPfiPfi, @function
_Z24__device_stub__Z4pinvPfiPfi:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4pinvPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z24__device_stub__Z4pinvPfiPfi, .-_Z24__device_stub__Z4pinvPfiPfi
.globl _Z4pinvPfi
.type _Z4pinvPfi, @function
_Z4pinvPfi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4pinvPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z4pinvPfi, .-_Z4pinvPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4pinvPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4pinvPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pinv.hip"
.globl _Z19__device_stub__pinvPfi # -- Begin function _Z19__device_stub__pinvPfi
.p2align 4, 0x90
.type _Z19__device_stub__pinvPfi,@function
_Z19__device_stub__pinvPfi: # @_Z19__device_stub__pinvPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4pinvPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__pinvPfi, .Lfunc_end0-_Z19__device_stub__pinvPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4pinvPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4pinvPfi,@object # @_Z4pinvPfi
.section .rodata,"a",@progbits
.globl _Z4pinvPfi
.p2align 3, 0x0
_Z4pinvPfi:
.quad _Z19__device_stub__pinvPfi
.size _Z4pinvPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4pinvPfi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__pinvPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4pinvPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK 30000
#define THREAD 1000
#define CHECK 1
void stopwatch(int);
//그냥 글로벌 메모리 사용
__global__ void count( int* cnt)
{
(*cnt)++;
}
//Atomic 함수 사용
__global__ void atomic_count( int* cnt)
{
//Atomic 함수, 더하는 대상을 포인터로 지정해야한다
//한번에 하나의 쓰레드만 작업한다
atomicAdd(cnt,1);
}
//Atonic 함수와 Shared Memory 사용
__global__ void atomic_with_shared_count( int* cnt)
{
__shared__ int s_cnt;
//하나의 쓰레드만 초기화 시켜주면 된다
if(threadIdx.x==0)
s_cnt = 0;
//블록단위 동기화
__syncthreads();
atomicAdd(&s_cnt,1);
//블록단위 동기화
__syncthreads();
//하나의 쓰레드만 글로벌 변수에 더해주면 된다
if(threadIdx.x==0)
atomicAdd(cnt,s_cnt);
}
int main()
{
int * host_cnt;
int * dev_cnt;
dim3 Dg(BLOCK,1,1);
dim3 Db(THREAD,1,1);
printf("BLOCK : %d\nTHREAD : %d\n",BLOCK,THREAD);
host_cnt= (int*)malloc(sizeof(int));
cudaMalloc((void**)&dev_cnt,sizeof(int));
printf("Just cnt++ : ");
stopwatch(0);
cudaMemcpy(dev_cnt, host_cnt,sizeof(int), cudaMemcpyHostToDevice);
count<<<Dg,Db >>>(dev_cnt);
cudaMemcpy(host_cnt,dev_cnt,sizeof(int),cudaMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd : ");
stopwatch(0);
cudaMemcpy(dev_cnt, host_cnt,sizeof(int), cudaMemcpyHostToDevice);
atomic_count<<<Dg,Db >>>(dev_cnt);
cudaMemcpy(host_cnt,dev_cnt,sizeof(int),cudaMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd with Shared Memory : ");
stopwatch(0);
cudaMemcpy(dev_cnt, host_cnt,sizeof(int), cudaMemcpyHostToDevice);
atomic_with_shared_count<<<Dg,Db >>>(dev_cnt);
cudaMemcpy(host_cnt,dev_cnt,sizeof(int),cudaMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
cudaFree(dev_cnt);
free(host_cnt);
return 0;
}
void stopwatch(int flag)
{
enum clock_unit{nano = 0, micro , milli, sec} unit;
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long diff = 0;
/*
여기서 단위 조정
nano, micro, milli, sec
*/
unit = micro;
//start
if(flag == 0)
{
diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
switch(unit)
{
case nano :
printf("% lld nano sec\n",diff);
break;
case micro :
printf("%lld micro sec\n",diff/1000);
break;
case sec :
printf("% lld sec\n",diff/1000000000);
break;
default :
printf("% lld milli sec\n",diff/100000);
break;
}
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
} | code for sm_80
Function : _Z24atomic_with_shared_countPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @!P0 STS [RZ], RZ ; /* 0x000000ffff008388 */
/* 0x000fe80000000800 */
/*0040*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0050*/ ATOMS.POPC.INC.32 RZ, [URZ] ; /* 0x00000000ffff7f8c */
/* 0x000fe8000d00003f */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0090*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12atomic_countPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0020*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0030*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ UFLO.U32 UR5, UR4 ; /* 0x00000004000572bd */
/* 0x000fe200080e0000 */
/*0050*/ POPC R5, UR4 ; /* 0x0000000400057d09 */
/* 0x000e620008000000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fc800078e00ff */
/*0070*/ ISETP.EQ.U32.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x001fe2000bf02070 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0090*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5countPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0050*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK 30000
#define THREAD 1000
#define CHECK 1
void stopwatch(int);
//그냥 글로벌 메모리 사용
__global__ void count( int* cnt)
{
(*cnt)++;
}
//Atomic 함수 사용
__global__ void atomic_count( int* cnt)
{
//Atomic 함수, 더하는 대상을 포인터로 지정해야한다
//한번에 하나의 쓰레드만 작업한다
atomicAdd(cnt,1);
}
//Atonic 함수와 Shared Memory 사용
__global__ void atomic_with_shared_count( int* cnt)
{
__shared__ int s_cnt;
//하나의 쓰레드만 초기화 시켜주면 된다
if(threadIdx.x==0)
s_cnt = 0;
//블록단위 동기화
__syncthreads();
atomicAdd(&s_cnt,1);
//블록단위 동기화
__syncthreads();
//하나의 쓰레드만 글로벌 변수에 더해주면 된다
if(threadIdx.x==0)
atomicAdd(cnt,s_cnt);
}
int main()
{
int * host_cnt;
int * dev_cnt;
dim3 Dg(BLOCK,1,1);
dim3 Db(THREAD,1,1);
printf("BLOCK : %d\nTHREAD : %d\n",BLOCK,THREAD);
host_cnt= (int*)malloc(sizeof(int));
cudaMalloc((void**)&dev_cnt,sizeof(int));
printf("Just cnt++ : ");
stopwatch(0);
cudaMemcpy(dev_cnt, host_cnt,sizeof(int), cudaMemcpyHostToDevice);
count<<<Dg,Db >>>(dev_cnt);
cudaMemcpy(host_cnt,dev_cnt,sizeof(int),cudaMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd : ");
stopwatch(0);
cudaMemcpy(dev_cnt, host_cnt,sizeof(int), cudaMemcpyHostToDevice);
atomic_count<<<Dg,Db >>>(dev_cnt);
cudaMemcpy(host_cnt,dev_cnt,sizeof(int),cudaMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd with Shared Memory : ");
stopwatch(0);
cudaMemcpy(dev_cnt, host_cnt,sizeof(int), cudaMemcpyHostToDevice);
atomic_with_shared_count<<<Dg,Db >>>(dev_cnt);
cudaMemcpy(host_cnt,dev_cnt,sizeof(int),cudaMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
cudaFree(dev_cnt);
free(host_cnt);
return 0;
}
void stopwatch(int flag)
{
enum clock_unit{nano = 0, micro , milli, sec} unit;
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long diff = 0;
/*
여기서 단위 조정
nano, micro, milli, sec
*/
unit = micro;
//start
if(flag == 0)
{
diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
switch(unit)
{
case nano :
printf("% lld nano sec\n",diff);
break;
case micro :
printf("%lld micro sec\n",diff/1000);
break;
case sec :
printf("% lld sec\n",diff/1000000000);
break;
default :
printf("% lld milli sec\n",diff/100000);
break;
}
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
} | .file "tmpxft_00095567_00000000-6_8_atomic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to call clock_gettime\n"
.LC1:
.string "%lld micro sec\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "wrong flag | 0 : start, 1 : end\n"
.text
.globl _Z9stopwatchi
.type _Z9stopwatchi, @function
_Z9stopwatchi:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %edi, %edi
je .L9
cmpl $1, %edi
je .L10
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
leaq _ZZ9stopwatchiE7startTS(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
jne .L3
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L10:
leaq _ZZ9stopwatchiE5endTS(%rip), %rsi
call clock_gettime@PLT
cmpl $-1, %eax
je .L11
.L7:
movq _ZZ9stopwatchiE5endTS(%rip), %rcx
subq _ZZ9stopwatchiE7startTS(%rip), %rcx
imulq $1000000000, %rcx, %rcx
addq 8+_ZZ9stopwatchiE5endTS(%rip), %rcx
subq 8+_ZZ9stopwatchiE7startTS(%rip), %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L11:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z9stopwatchi, .-_Z9stopwatchi
.globl _Z24__device_stub__Z5countPiPi
.type _Z24__device_stub__Z5countPiPi, @function
_Z24__device_stub__Z5countPiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5countPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z24__device_stub__Z5countPiPi, .-_Z24__device_stub__Z5countPiPi
.globl _Z5countPi
.type _Z5countPi, @function
_Z5countPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5countPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z5countPi, .-_Z5countPi
.globl _Z32__device_stub__Z12atomic_countPiPi
.type _Z32__device_stub__Z12atomic_countPiPi, @function
_Z32__device_stub__Z12atomic_countPiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12atomic_countPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z12atomic_countPiPi, .-_Z32__device_stub__Z12atomic_countPiPi
.globl _Z12atomic_countPi
.type _Z12atomic_countPi, @function
_Z12atomic_countPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12atomic_countPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12atomic_countPi, .-_Z12atomic_countPi
.globl _Z44__device_stub__Z24atomic_with_shared_countPiPi
.type _Z44__device_stub__Z24atomic_with_shared_countPiPi, @function
_Z44__device_stub__Z24atomic_with_shared_countPiPi:
.LFB2087:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24atomic_with_shared_countPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z44__device_stub__Z24atomic_with_shared_countPiPi, .-_Z44__device_stub__Z24atomic_with_shared_countPiPi
.globl _Z24atomic_with_shared_countPi
.type _Z24atomic_with_shared_countPi, @function
_Z24atomic_with_shared_countPi:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z24atomic_with_shared_countPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z24atomic_with_shared_countPi, .-_Z24atomic_with_shared_countPi
.section .rodata.str1.1
.LC3:
.string "BLOCK : %d\nTHREAD : %d\n"
.LC4:
.string "Just cnt++ : "
.LC5:
.string "cnt : %d\n"
.LC6:
.string "AtomicAdd : "
.section .rodata.str1.8
.align 8
.LC7:
.string "AtomicAdd with Shared Memory : "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $30000, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1000, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1000, %ecx
movl $30000, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call _Z9stopwatchi
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L37:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %edi
call _Z9stopwatchi
movl (%rbx), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, (%rbx)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call _Z9stopwatchi
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L38:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %edi
call _Z9stopwatchi
movl (%rbx), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, (%rbx)
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call _Z9stopwatchi
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L39:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %edi
call _Z9stopwatchi
movl (%rbx), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z24__device_stub__Z5countPiPi
jmp .L37
.L43:
movq 8(%rsp), %rdi
call _Z32__device_stub__Z12atomic_countPiPi
jmp .L38
.L44:
movq 8(%rsp), %rdi
call _Z44__device_stub__Z24atomic_with_shared_countPiPi
jmp .L39
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z24atomic_with_shared_countPi"
.section .rodata.str1.1
.LC9:
.string "_Z12atomic_countPi"
.LC10:
.string "_Z5countPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z24atomic_with_shared_countPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12atomic_countPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5countPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ9stopwatchiE5endTS
.comm _ZZ9stopwatchiE5endTS,16,16
.local _ZZ9stopwatchiE7startTS
.comm _ZZ9stopwatchiE7startTS,16,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK 30000
#define THREAD 1000
#define CHECK 1
void stopwatch(int);
//그냥 글로벌 메모리 사용
__global__ void count( int* cnt)
{
(*cnt)++;
}
//Atomic 함수 사용
__global__ void atomic_count( int* cnt)
{
//Atomic 함수, 더하는 대상을 포인터로 지정해야한다
//한번에 하나의 쓰레드만 작업한다
atomicAdd(cnt,1);
}
//Atonic 함수와 Shared Memory 사용
__global__ void atomic_with_shared_count( int* cnt)
{
__shared__ int s_cnt;
//하나의 쓰레드만 초기화 시켜주면 된다
if(threadIdx.x==0)
s_cnt = 0;
//블록단위 동기화
__syncthreads();
atomicAdd(&s_cnt,1);
//블록단위 동기화
__syncthreads();
//하나의 쓰레드만 글로벌 변수에 더해주면 된다
if(threadIdx.x==0)
atomicAdd(cnt,s_cnt);
}
int main()
{
int * host_cnt;
int * dev_cnt;
dim3 Dg(BLOCK,1,1);
dim3 Db(THREAD,1,1);
printf("BLOCK : %d\nTHREAD : %d\n",BLOCK,THREAD);
host_cnt= (int*)malloc(sizeof(int));
cudaMalloc((void**)&dev_cnt,sizeof(int));
printf("Just cnt++ : ");
stopwatch(0);
cudaMemcpy(dev_cnt, host_cnt,sizeof(int), cudaMemcpyHostToDevice);
count<<<Dg,Db >>>(dev_cnt);
cudaMemcpy(host_cnt,dev_cnt,sizeof(int),cudaMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd : ");
stopwatch(0);
cudaMemcpy(dev_cnt, host_cnt,sizeof(int), cudaMemcpyHostToDevice);
atomic_count<<<Dg,Db >>>(dev_cnt);
cudaMemcpy(host_cnt,dev_cnt,sizeof(int),cudaMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd with Shared Memory : ");
stopwatch(0);
cudaMemcpy(dev_cnt, host_cnt,sizeof(int), cudaMemcpyHostToDevice);
atomic_with_shared_count<<<Dg,Db >>>(dev_cnt);
cudaMemcpy(host_cnt,dev_cnt,sizeof(int),cudaMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
cudaFree(dev_cnt);
free(host_cnt);
return 0;
}
void stopwatch(int flag)
{
enum clock_unit{nano = 0, micro , milli, sec} unit;
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long diff = 0;
/*
여기서 단위 조정
nano, micro, milli, sec
*/
unit = micro;
//start
if(flag == 0)
{
diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
switch(unit)
{
case nano :
printf("% lld nano sec\n",diff);
break;
case micro :
printf("%lld micro sec\n",diff/1000);
break;
case sec :
printf("% lld sec\n",diff/1000000000);
break;
default :
printf("% lld milli sec\n",diff/100000);
break;
}
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK 30000
#define THREAD 1000
#define CHECK 1
void stopwatch(int);
//그냥 글로벌 메모리 사용
__global__ void count( int* cnt)
{
(*cnt)++;
}
//Atomic 함수 사용
__global__ void atomic_count( int* cnt)
{
//Atomic 함수, 더하는 대상을 포인터로 지정해야한다
//한번에 하나의 쓰레드만 작업한다
atomicAdd(cnt,1);
}
//Atonic 함수와 Shared Memory 사용
__global__ void atomic_with_shared_count( int* cnt)
{
__shared__ int s_cnt;
//하나의 쓰레드만 초기화 시켜주면 된다
if(threadIdx.x==0)
s_cnt = 0;
//블록단위 동기화
__syncthreads();
atomicAdd(&s_cnt,1);
//블록단위 동기화
__syncthreads();
//하나의 쓰레드만 글로벌 변수에 더해주면 된다
if(threadIdx.x==0)
atomicAdd(cnt,s_cnt);
}
int main()
{
int * host_cnt;
int * dev_cnt;
dim3 Dg(BLOCK,1,1);
dim3 Db(THREAD,1,1);
printf("BLOCK : %d\nTHREAD : %d\n",BLOCK,THREAD);
host_cnt= (int*)malloc(sizeof(int));
hipMalloc((void**)&dev_cnt,sizeof(int));
printf("Just cnt++ : ");
stopwatch(0);
hipMemcpy(dev_cnt, host_cnt,sizeof(int), hipMemcpyHostToDevice);
count<<<Dg,Db >>>(dev_cnt);
hipMemcpy(host_cnt,dev_cnt,sizeof(int),hipMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd : ");
stopwatch(0);
hipMemcpy(dev_cnt, host_cnt,sizeof(int), hipMemcpyHostToDevice);
atomic_count<<<Dg,Db >>>(dev_cnt);
hipMemcpy(host_cnt,dev_cnt,sizeof(int),hipMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd with Shared Memory : ");
stopwatch(0);
hipMemcpy(dev_cnt, host_cnt,sizeof(int), hipMemcpyHostToDevice);
atomic_with_shared_count<<<Dg,Db >>>(dev_cnt);
hipMemcpy(host_cnt,dev_cnt,sizeof(int),hipMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
hipFree(dev_cnt);
free(host_cnt);
return 0;
}
void stopwatch(int flag)
{
enum clock_unit{nano = 0, micro , milli, sec} unit;
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long diff = 0;
/*
여기서 단위 조정
nano, micro, milli, sec
*/
unit = micro;
//start
if(flag == 0)
{
diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
switch(unit)
{
case nano :
printf("% lld nano sec\n",diff);
break;
case micro :
printf("%lld micro sec\n",diff/1000);
break;
case sec :
printf("% lld sec\n",diff/1000000000);
break;
default :
printf("% lld milli sec\n",diff/100000);
break;
}
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK 30000
#define THREAD 1000
#define CHECK 1
void stopwatch(int);
//그냥 글로벌 메모리 사용
__global__ void count( int* cnt)
{
(*cnt)++;
}
//Atomic 함수 사용
__global__ void atomic_count( int* cnt)
{
//Atomic 함수, 더하는 대상을 포인터로 지정해야한다
//한번에 하나의 쓰레드만 작업한다
atomicAdd(cnt,1);
}
//Atonic 함수와 Shared Memory 사용
__global__ void atomic_with_shared_count( int* cnt)
{
__shared__ int s_cnt;
//하나의 쓰레드만 초기화 시켜주면 된다
if(threadIdx.x==0)
s_cnt = 0;
//블록단위 동기화
__syncthreads();
atomicAdd(&s_cnt,1);
//블록단위 동기화
__syncthreads();
//하나의 쓰레드만 글로벌 변수에 더해주면 된다
if(threadIdx.x==0)
atomicAdd(cnt,s_cnt);
}
int main()
{
int * host_cnt;
int * dev_cnt;
dim3 Dg(BLOCK,1,1);
dim3 Db(THREAD,1,1);
printf("BLOCK : %d\nTHREAD : %d\n",BLOCK,THREAD);
host_cnt= (int*)malloc(sizeof(int));
hipMalloc((void**)&dev_cnt,sizeof(int));
printf("Just cnt++ : ");
stopwatch(0);
hipMemcpy(dev_cnt, host_cnt,sizeof(int), hipMemcpyHostToDevice);
count<<<Dg,Db >>>(dev_cnt);
hipMemcpy(host_cnt,dev_cnt,sizeof(int),hipMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd : ");
stopwatch(0);
hipMemcpy(dev_cnt, host_cnt,sizeof(int), hipMemcpyHostToDevice);
atomic_count<<<Dg,Db >>>(dev_cnt);
hipMemcpy(host_cnt,dev_cnt,sizeof(int),hipMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd with Shared Memory : ");
stopwatch(0);
hipMemcpy(dev_cnt, host_cnt,sizeof(int), hipMemcpyHostToDevice);
atomic_with_shared_count<<<Dg,Db >>>(dev_cnt);
hipMemcpy(host_cnt,dev_cnt,sizeof(int),hipMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
hipFree(dev_cnt);
free(host_cnt);
return 0;
}
void stopwatch(int flag)
{
enum clock_unit{nano = 0, micro , milli, sec} unit;
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long diff = 0;
/*
여기서 단위 조정
nano, micro, milli, sec
*/
unit = micro;
//start
if(flag == 0)
{
diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
switch(unit)
{
case nano :
printf("% lld nano sec\n",diff);
break;
case micro :
printf("%lld micro sec\n",diff/1000);
break;
case sec :
printf("% lld sec\n",diff/1000000000);
break;
default :
printf("% lld milli sec\n",diff/100000);
break;
}
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5countPi
.globl _Z5countPi
.p2align 8
.type _Z5countPi,@function
_Z5countPi:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5countPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5countPi, .Lfunc_end0-_Z5countPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12atomic_countPi
.globl _Z12atomic_countPi
.p2align 8
.type _Z12atomic_countPi,@function
_Z12atomic_countPi:
s_mov_b32 s2, exec_lo
s_mov_b32 s3, exec_lo
v_mbcnt_lo_u32_b32 v0, s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12atomic_countPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12atomic_countPi, .Lfunc_end1-_Z12atomic_countPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z24atomic_with_shared_countPi
.globl _Z24atomic_with_shared_countPi
.p2align 8
.type _Z24atomic_with_shared_countPi,@function
_Z24atomic_with_shared_countPi:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
v_mov_b32_e32 v0, 0
ds_store_b32 v0, v0
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_mov_b32 s4, exec_lo
v_mbcnt_lo_u32_b32 v0, s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_4
s_bcnt1_i32_b32 s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
ds_add_u32 v0, v1
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_7
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB2_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_bcnt1_i32_b32 s2, s2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s2
global_atomic_add_u32 v0, v1, s[0:1]
.LBB2_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24atomic_with_shared_countPi
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z24atomic_with_shared_countPi, .Lfunc_end2-_Z24atomic_with_shared_countPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5countPi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z5countPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12atomic_countPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z12atomic_countPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24atomic_with_shared_countPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z24atomic_with_shared_countPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define BLOCK 30000
#define THREAD 1000
#define CHECK 1
void stopwatch(int);
//그냥 글로벌 메모리 사용
__global__ void count( int* cnt)
{
(*cnt)++;
}
//Atomic 함수 사용
__global__ void atomic_count( int* cnt)
{
//Atomic 함수, 더하는 대상을 포인터로 지정해야한다
//한번에 하나의 쓰레드만 작업한다
atomicAdd(cnt,1);
}
//Atonic 함수와 Shared Memory 사용
__global__ void atomic_with_shared_count( int* cnt)
{
__shared__ int s_cnt;
//하나의 쓰레드만 초기화 시켜주면 된다
if(threadIdx.x==0)
s_cnt = 0;
//블록단위 동기화
__syncthreads();
atomicAdd(&s_cnt,1);
//블록단위 동기화
__syncthreads();
//하나의 쓰레드만 글로벌 변수에 더해주면 된다
if(threadIdx.x==0)
atomicAdd(cnt,s_cnt);
}
int main()
{
int * host_cnt;
int * dev_cnt;
dim3 Dg(BLOCK,1,1);
dim3 Db(THREAD,1,1);
printf("BLOCK : %d\nTHREAD : %d\n",BLOCK,THREAD);
host_cnt= (int*)malloc(sizeof(int));
hipMalloc((void**)&dev_cnt,sizeof(int));
printf("Just cnt++ : ");
stopwatch(0);
hipMemcpy(dev_cnt, host_cnt,sizeof(int), hipMemcpyHostToDevice);
count<<<Dg,Db >>>(dev_cnt);
hipMemcpy(host_cnt,dev_cnt,sizeof(int),hipMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd : ");
stopwatch(0);
hipMemcpy(dev_cnt, host_cnt,sizeof(int), hipMemcpyHostToDevice);
atomic_count<<<Dg,Db >>>(dev_cnt);
hipMemcpy(host_cnt,dev_cnt,sizeof(int),hipMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
(*host_cnt)=0;
printf("AtomicAdd with Shared Memory : ");
stopwatch(0);
hipMemcpy(dev_cnt, host_cnt,sizeof(int), hipMemcpyHostToDevice);
atomic_with_shared_count<<<Dg,Db >>>(dev_cnt);
hipMemcpy(host_cnt,dev_cnt,sizeof(int),hipMemcpyDeviceToHost);
stopwatch(1);
#if CHECK
printf("cnt : %d\n",*host_cnt);
#endif
hipFree(dev_cnt);
free(host_cnt);
return 0;
}
void stopwatch(int flag)
{
enum clock_unit{nano = 0, micro , milli, sec} unit;
const long long NANOS = 1000000000LL;
static struct timespec startTS,endTS;
static long long diff = 0;
/*
여기서 단위 조정
nano, micro, milli, sec
*/
unit = micro;
//start
if(flag == 0)
{
diff = 0;
if(-1 == clock_gettime(CLOCK_MONOTONIC,&startTS))
printf("Failed to call clock_gettime\n");
}
//end
else if(flag == 1)
{
if(-1 == clock_gettime(CLOCK_MONOTONIC,&endTS))
printf("Failed to call clock_gettime\n");
diff = NANOS * (endTS.tv_sec - startTS.tv_sec) + (endTS.tv_nsec - startTS.tv_nsec);
switch(unit)
{
case nano :
printf("% lld nano sec\n",diff);
break;
case micro :
printf("%lld micro sec\n",diff/1000);
break;
case sec :
printf("% lld sec\n",diff/1000000000);
break;
default :
printf("% lld milli sec\n",diff/100000);
break;
}
}
else
{
printf("wrong flag | 0 : start, 1 : end\n");
}
} | .text
.file "8_atomic.hip"
.globl _Z20__device_stub__countPi # -- Begin function _Z20__device_stub__countPi
.p2align 4, 0x90
.type _Z20__device_stub__countPi,@function
_Z20__device_stub__countPi: # @_Z20__device_stub__countPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5countPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z20__device_stub__countPi, .Lfunc_end0-_Z20__device_stub__countPi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__atomic_countPi # -- Begin function _Z27__device_stub__atomic_countPi
.p2align 4, 0x90
.type _Z27__device_stub__atomic_countPi,@function
_Z27__device_stub__atomic_countPi: # @_Z27__device_stub__atomic_countPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z12atomic_countPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z27__device_stub__atomic_countPi, .Lfunc_end1-_Z27__device_stub__atomic_countPi
.cfi_endproc
# -- End function
.globl _Z39__device_stub__atomic_with_shared_countPi # -- Begin function _Z39__device_stub__atomic_with_shared_countPi
.p2align 4, 0x90
.type _Z39__device_stub__atomic_with_shared_countPi,@function
_Z39__device_stub__atomic_with_shared_countPi: # @_Z39__device_stub__atomic_with_shared_countPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z24atomic_with_shared_countPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z39__device_stub__atomic_with_shared_countPi, .Lfunc_end2-_Z39__device_stub__atomic_with_shared_countPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
movl $30000, %esi # imm = 0x7530
movl $1000, %edx # imm = 0x3E8
xorl %eax, %eax
callq printf
movl $4, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_2
# %bb.1:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_2: # %_Z9stopwatchi.exit
movabsq $4294968296, %r14 # imm = 0x1000003E8
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 29000(%r14), %r15
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z5countPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_6
# %bb.5:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_6: # %_Z9stopwatchi.exit36
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
movabsq $2361183241434822607, %r12 # imm = 0x20C49BA5E353F7CF
imulq %r12
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $0, (%rbx)
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_8
# %bb.7:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_8: # %_Z9stopwatchi.exit38
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12atomic_countPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_12
# %bb.11:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_12: # %_Z9stopwatchi.exit46
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
imulq %r12
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $0, (%rbx)
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_14
# %bb.13:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_14: # %_Z9stopwatchi.exit48
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_16
# %bb.15:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z24atomic_with_shared_countPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_16:
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_18
# %bb.17:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_18: # %_Z9stopwatchi.exit56
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
imulq %r12
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.globl _Z9stopwatchi # -- Begin function _Z9stopwatchi
.p2align 4, 0x90
.type _Z9stopwatchi,@function
_Z9stopwatchi: # @_Z9stopwatchi
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpl $1, %edi
je .LBB4_4
# %bb.1:
testl %edi, %edi
jne .LBB4_7
# %bb.2:
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB4_3
# %bb.8:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB4_4:
.cfi_def_cfa_offset 16
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB4_6
# %bb.5:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB4_6:
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB4_7:
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB4_3:
.cfi_def_cfa_offset 16
movl $.Lstr.2, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z9stopwatchi, .Lfunc_end4-_Z9stopwatchi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5countPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12atomic_countPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24atomic_with_shared_countPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5countPi,@object # @_Z5countPi
.section .rodata,"a",@progbits
.globl _Z5countPi
.p2align 3, 0x0
_Z5countPi:
.quad _Z20__device_stub__countPi
.size _Z5countPi, 8
.type _Z12atomic_countPi,@object # @_Z12atomic_countPi
.globl _Z12atomic_countPi
.p2align 3, 0x0
_Z12atomic_countPi:
.quad _Z27__device_stub__atomic_countPi
.size _Z12atomic_countPi, 8
.type _Z24atomic_with_shared_countPi,@object # @_Z24atomic_with_shared_countPi
.globl _Z24atomic_with_shared_countPi
.p2align 3, 0x0
_Z24atomic_with_shared_countPi:
.quad _Z39__device_stub__atomic_with_shared_countPi
.size _Z24atomic_with_shared_countPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "BLOCK : %d\nTHREAD : %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Just cnt++ : "
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cnt : %d\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "AtomicAdd : "
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "AtomicAdd with Shared Memory : "
.size .L.str.4, 32
.type _ZZ9stopwatchiE7startTS,@object # @_ZZ9stopwatchiE7startTS
.local _ZZ9stopwatchiE7startTS
.comm _ZZ9stopwatchiE7startTS,16,8
.type _ZZ9stopwatchiE5endTS,@object # @_ZZ9stopwatchiE5endTS
.local _ZZ9stopwatchiE5endTS
.comm _ZZ9stopwatchiE5endTS,16,8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%lld micro sec\n"
.size .L.str.7, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5countPi"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12atomic_countPi"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z24atomic_with_shared_countPi"
.size .L__unnamed_3, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "wrong flag | 0 : start, 1 : end"
.size .Lstr, 32
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Failed to call clock_gettime"
.size .Lstr.2, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__countPi
.addrsig_sym _Z27__device_stub__atomic_countPi
.addrsig_sym _Z39__device_stub__atomic_with_shared_countPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5countPi
.addrsig_sym _Z12atomic_countPi
.addrsig_sym _Z24atomic_with_shared_countPi
.addrsig_sym _ZZ9stopwatchiE7startTS
.addrsig_sym _ZZ9stopwatchiE5endTS
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24atomic_with_shared_countPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @!P0 STS [RZ], RZ ; /* 0x000000ffff008388 */
/* 0x000fe80000000800 */
/*0040*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0050*/ ATOMS.POPC.INC.32 RZ, [URZ] ; /* 0x00000000ffff7f8c */
/* 0x000fe8000d00003f */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0090*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12atomic_countPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0020*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0030*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ UFLO.U32 UR5, UR4 ; /* 0x00000004000572bd */
/* 0x000fe200080e0000 */
/*0050*/ POPC R5, UR4 ; /* 0x0000000400057d09 */
/* 0x000e620008000000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fc800078e00ff */
/*0070*/ ISETP.EQ.U32.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x001fe2000bf02070 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0090*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5countPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0050*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5countPi
.globl _Z5countPi
.p2align 8
.type _Z5countPi,@function
_Z5countPi:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5countPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5countPi, .Lfunc_end0-_Z5countPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12atomic_countPi
.globl _Z12atomic_countPi
.p2align 8
.type _Z12atomic_countPi,@function
_Z12atomic_countPi:
s_mov_b32 s2, exec_lo
s_mov_b32 s3, exec_lo
v_mbcnt_lo_u32_b32 v0, s2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12atomic_countPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12atomic_countPi, .Lfunc_end1-_Z12atomic_countPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z24atomic_with_shared_countPi
.globl _Z24atomic_with_shared_countPi
.p2align 8
.type _Z24atomic_with_shared_countPi,@function
_Z24atomic_with_shared_countPi:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
v_mov_b32_e32 v0, 0
ds_store_b32 v0, v0
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
s_mov_b32 s4, exec_lo
v_mbcnt_lo_u32_b32 v0, s3, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_4
s_bcnt1_i32_b32 s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
ds_add_u32 v0, v1
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_7
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB2_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_bcnt1_i32_b32 s2, s2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s2
global_atomic_add_u32 v0, v1, s[0:1]
.LBB2_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24atomic_with_shared_countPi
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z24atomic_with_shared_countPi, .Lfunc_end2-_Z24atomic_with_shared_countPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5countPi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z5countPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12atomic_countPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z12atomic_countPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24atomic_with_shared_countPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z24atomic_with_shared_countPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00095567_00000000-6_8_atomic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Failed to call clock_gettime\n"
.LC1:
.string "%lld micro sec\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "wrong flag | 0 : start, 1 : end\n"
.text
.globl _Z9stopwatchi
.type _Z9stopwatchi, @function
_Z9stopwatchi:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %edi, %edi
je .L9
cmpl $1, %edi
je .L10
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
leaq _ZZ9stopwatchiE7startTS(%rip), %rsi
movl $1, %edi
call clock_gettime@PLT
cmpl $-1, %eax
jne .L3
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L10:
leaq _ZZ9stopwatchiE5endTS(%rip), %rsi
call clock_gettime@PLT
cmpl $-1, %eax
je .L11
.L7:
movq _ZZ9stopwatchiE5endTS(%rip), %rcx
subq _ZZ9stopwatchiE7startTS(%rip), %rcx
imulq $1000000000, %rcx, %rcx
addq 8+_ZZ9stopwatchiE5endTS(%rip), %rcx
subq 8+_ZZ9stopwatchiE7startTS(%rip), %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.L11:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z9stopwatchi, .-_Z9stopwatchi
.globl _Z24__device_stub__Z5countPiPi
.type _Z24__device_stub__Z5countPiPi, @function
_Z24__device_stub__Z5countPiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5countPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z24__device_stub__Z5countPiPi, .-_Z24__device_stub__Z5countPiPi
.globl _Z5countPi
.type _Z5countPi, @function
_Z5countPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z5countPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z5countPi, .-_Z5countPi
.globl _Z32__device_stub__Z12atomic_countPiPi
.type _Z32__device_stub__Z12atomic_countPiPi, @function
_Z32__device_stub__Z12atomic_countPiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12atomic_countPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z12atomic_countPiPi, .-_Z32__device_stub__Z12atomic_countPiPi
.globl _Z12atomic_countPi
.type _Z12atomic_countPi, @function
_Z12atomic_countPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12atomic_countPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12atomic_countPi, .-_Z12atomic_countPi
.globl _Z44__device_stub__Z24atomic_with_shared_countPiPi
.type _Z44__device_stub__Z24atomic_with_shared_countPiPi, @function
_Z44__device_stub__Z24atomic_with_shared_countPiPi:
.LFB2087:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24atomic_with_shared_countPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z44__device_stub__Z24atomic_with_shared_countPiPi, .-_Z44__device_stub__Z24atomic_with_shared_countPiPi
.globl _Z24atomic_with_shared_countPi
.type _Z24atomic_with_shared_countPi, @function
_Z24atomic_with_shared_countPi:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z24atomic_with_shared_countPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z24atomic_with_shared_countPi, .-_Z24atomic_with_shared_countPi
.section .rodata.str1.1
.LC3:
.string "BLOCK : %d\nTHREAD : %d\n"
.LC4:
.string "Just cnt++ : "
.LC5:
.string "cnt : %d\n"
.LC6:
.string "AtomicAdd : "
.section .rodata.str1.8
.align 8
.LC7:
.string "AtomicAdd with Shared Memory : "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $30000, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1000, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1000, %ecx
movl $30000, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call _Z9stopwatchi
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L37:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %edi
call _Z9stopwatchi
movl (%rbx), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, (%rbx)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call _Z9stopwatchi
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L38:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %edi
call _Z9stopwatchi
movl (%rbx), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, (%rbx)
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call _Z9stopwatchi
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L39:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %edi
call _Z9stopwatchi
movl (%rbx), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z24__device_stub__Z5countPiPi
jmp .L37
.L43:
movq 8(%rsp), %rdi
call _Z32__device_stub__Z12atomic_countPiPi
jmp .L38
.L44:
movq 8(%rsp), %rdi
call _Z44__device_stub__Z24atomic_with_shared_countPiPi
jmp .L39
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z24atomic_with_shared_countPi"
.section .rodata.str1.1
.LC9:
.string "_Z12atomic_countPi"
.LC10:
.string "_Z5countPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z24atomic_with_shared_countPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12atomic_countPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5countPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ9stopwatchiE5endTS
.comm _ZZ9stopwatchiE5endTS,16,16
.local _ZZ9stopwatchiE7startTS
.comm _ZZ9stopwatchiE7startTS,16,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "8_atomic.hip"
.globl _Z20__device_stub__countPi # -- Begin function _Z20__device_stub__countPi
.p2align 4, 0x90
.type _Z20__device_stub__countPi,@function
_Z20__device_stub__countPi: # @_Z20__device_stub__countPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z5countPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z20__device_stub__countPi, .Lfunc_end0-_Z20__device_stub__countPi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__atomic_countPi # -- Begin function _Z27__device_stub__atomic_countPi
.p2align 4, 0x90
.type _Z27__device_stub__atomic_countPi,@function
_Z27__device_stub__atomic_countPi: # @_Z27__device_stub__atomic_countPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z12atomic_countPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z27__device_stub__atomic_countPi, .Lfunc_end1-_Z27__device_stub__atomic_countPi
.cfi_endproc
# -- End function
.globl _Z39__device_stub__atomic_with_shared_countPi # -- Begin function _Z39__device_stub__atomic_with_shared_countPi
.p2align 4, 0x90
.type _Z39__device_stub__atomic_with_shared_countPi,@function
_Z39__device_stub__atomic_with_shared_countPi: # @_Z39__device_stub__atomic_with_shared_countPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z24atomic_with_shared_countPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z39__device_stub__atomic_with_shared_countPi, .Lfunc_end2-_Z39__device_stub__atomic_with_shared_countPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
movl $30000, %esi # imm = 0x7530
movl $1000, %edx # imm = 0x3E8
xorl %eax, %eax
callq printf
movl $4, %edi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_2
# %bb.1:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_2: # %_Z9stopwatchi.exit
movabsq $4294968296, %r14 # imm = 0x1000003E8
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 29000(%r14), %r15
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z5countPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_6
# %bb.5:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_6: # %_Z9stopwatchi.exit36
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
movabsq $2361183241434822607, %r12 # imm = 0x20C49BA5E353F7CF
imulq %r12
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $0, (%rbx)
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_8
# %bb.7:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_8: # %_Z9stopwatchi.exit38
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12atomic_countPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_12
# %bb.11:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_12: # %_Z9stopwatchi.exit46
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
imulq %r12
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $0, (%rbx)
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_14
# %bb.13:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_14: # %_Z9stopwatchi.exit48
movq 8(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_16
# %bb.15:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z24atomic_with_shared_countPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_16:
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB3_18
# %bb.17:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB3_18: # %_Z9stopwatchi.exit56
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
imulq %r12
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl (%rbx), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.globl _Z9stopwatchi # -- Begin function _Z9stopwatchi
.p2align 4, 0x90
.type _Z9stopwatchi,@function
_Z9stopwatchi: # @_Z9stopwatchi
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpl $1, %edi
je .LBB4_4
# %bb.1:
testl %edi, %edi
jne .LBB4_7
# %bb.2:
movl $_ZZ9stopwatchiE7startTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
je .LBB4_3
# %bb.8:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB4_4:
.cfi_def_cfa_offset 16
movl $_ZZ9stopwatchiE5endTS, %esi
movl $1, %edi
callq clock_gettime
cmpl $-1, %eax
jne .LBB4_6
# %bb.5:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB4_6:
movq _ZZ9stopwatchiE5endTS(%rip), %rax
subq _ZZ9stopwatchiE7startTS(%rip), %rax
imulq $1000000000, %rax, %rcx # imm = 0x3B9ACA00
movq _ZZ9stopwatchiE5endTS+8(%rip), %rax
subq _ZZ9stopwatchiE7startTS+8(%rip), %rax
addq %rcx, %rax
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB4_7:
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB4_3:
.cfi_def_cfa_offset 16
movl $.Lstr.2, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z9stopwatchi, .Lfunc_end4-_Z9stopwatchi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5countPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12atomic_countPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24atomic_with_shared_countPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5countPi,@object # @_Z5countPi
.section .rodata,"a",@progbits
.globl _Z5countPi
.p2align 3, 0x0
_Z5countPi:
.quad _Z20__device_stub__countPi
.size _Z5countPi, 8
.type _Z12atomic_countPi,@object # @_Z12atomic_countPi
.globl _Z12atomic_countPi
.p2align 3, 0x0
_Z12atomic_countPi:
.quad _Z27__device_stub__atomic_countPi
.size _Z12atomic_countPi, 8
.type _Z24atomic_with_shared_countPi,@object # @_Z24atomic_with_shared_countPi
.globl _Z24atomic_with_shared_countPi
.p2align 3, 0x0
_Z24atomic_with_shared_countPi:
.quad _Z39__device_stub__atomic_with_shared_countPi
.size _Z24atomic_with_shared_countPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "BLOCK : %d\nTHREAD : %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Just cnt++ : "
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cnt : %d\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "AtomicAdd : "
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "AtomicAdd with Shared Memory : "
.size .L.str.4, 32
.type _ZZ9stopwatchiE7startTS,@object # @_ZZ9stopwatchiE7startTS
.local _ZZ9stopwatchiE7startTS
.comm _ZZ9stopwatchiE7startTS,16,8
.type _ZZ9stopwatchiE5endTS,@object # @_ZZ9stopwatchiE5endTS
.local _ZZ9stopwatchiE5endTS
.comm _ZZ9stopwatchiE5endTS,16,8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%lld micro sec\n"
.size .L.str.7, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5countPi"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12atomic_countPi"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z24atomic_with_shared_countPi"
.size .L__unnamed_3, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "wrong flag | 0 : start, 1 : end"
.size .Lstr, 32
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Failed to call clock_gettime"
.size .Lstr.2, 29
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__countPi
.addrsig_sym _Z27__device_stub__atomic_countPi
.addrsig_sym _Z39__device_stub__atomic_with_shared_countPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5countPi
.addrsig_sym _Z12atomic_countPi
.addrsig_sym _Z24atomic_with_shared_countPi
.addrsig_sym _ZZ9stopwatchiE7startTS
.addrsig_sym _ZZ9stopwatchiE5endTS
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Three Dimensional Poisson solver using NVIDIA CUDA
//Author: Arkavo Hait, 2021
#include <stdio.h>
#include <iostream>
#include <cmath>
#include <time.h>
#include <chrono>
#include <string>
#include <limits.h>
#include <fstream>
using namespace std;
//Box struct
struct BOX
{
int X;
int Y;
int Z;
};
//X double derivative
__global__ void DDX(double* R, double* C,int X,int Y,int Z,double dx)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2)))
{
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=1;i<X-1;i++)
{
*(R+index+i) = (*(C+index+1+i) + *(C+index-1+i) - 2* *(C+index+i))/(dx*dx);
}
}
}
//Y double derivative
__global__ void DDY(double* R, double* C,int X,int Y,int Z, double dy)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2))){
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=1;i<Y-1;i++)
{
*(R+index+i*X) = (*(C+index+X*(i+1)) + *(C+index+X*(i-1)) - 2* *(C+index+i*X))/(dy*dy);
}}
}
//Z double derivative
__global__ void DDZ(double* R, double* C,int X,int Y,int Z, double dz)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2))){
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=0;i<Z-1;i++)
{
*(R+index+i*X*Y) = (*(C+index+X*Y*(i+1)) + *(C+index+X*Y*(i-1))- 2* *(C+index+i*X*Y))/(dz*dz);
}}
}
//parallel function to update matrices
__global__ void ASSIGN(double* R, double* C,int X,int Y,int Z)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2))){
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=1;i<X-1;i++)
{
*(R+index+i) = *(C+index+i);
}}
}
//parallel function to add two matrices
__global__ void ADD(double* R,double* C,double dt,int X,int Y,int Z)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2))){
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=0;i<X;i++)
{
*(R+index+i) += (*(C+index+i) * dt);
}}
}
//parallel function to compare two matrices, outputting a maximum difference bteween elements
__global__ void COMPARE(double* R, double* C, double* OUT_H,int X,int Y,int Z)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2))){
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=1;i<X-1;i++)
{
if(abs(*(R+index+i)-*(C+index+i))>= *OUT_H)
{
*OUT_H = abs(*(R+index+i) - *(C+index+i));
}
}}
}
//reset function, use it to reset any pointer
__global__ void RESET_CTR(double* C)
{
*C = 0;
}
//display function, use to disaply any array [deprecated for future use]
void display(double* DATA,int X,int Y,int Z)
{
for(int k=0;k<Z;k++)
{for(int j=0;j<Y;j++)
{for(int i=0;i<X;i++)
{printf("%.2lf ",*(DATA+i+X*j+X*Z*k));}
printf("\n");}printf("\n");}
}
//main fxn, will fix with args after
int main(int argc, char* argv[])
{
std::ofstream file;
file.open("data.csv",ios::app);
//file<<"Threads, X, Y, Z, Total, Time\n";
//DECLARE YOUR VARIABLES HERE
struct BOX grid;
int threads;
//std::cout<<argc<<"\n";
if(argc==2)
{
threads = stoi(argv[1]);
grid.X=10;
grid.Y=10;
grid.Z=10;
}
if(argc>2)
{
threads = stoi(argv[1]);
grid.X = stoi(argv[2]);
grid.Y = stoi(argv[3]);
grid.Z = stoi(argv[4]);
}
std::cout<<"Threads: "<<threads<<"\n";
const int X = grid.X;
const int Y = grid.Y;
const int Z = grid.Z;
int blocks = 1 + (Y-2) * (Z-2) / threads;
std::cout<<"Blocks: "<<blocks<<"\n";
//step for double derivatives
double step = 0.001;
//tolerence
double tol = 0.00001;
std::cout<<"\nX"<<X<<" Y"<<Y<<" Z"<<Z<<" Total Capacity⇒"<<X*Y*Z<<endl;
unsigned long long SIZE_0 = ((int)sizeof(double))*X*Y*Z;
double* DATA_H;
double* DATA_F;
DATA_H = (double*)malloc(SIZE_0);
DATA_F = (double*)malloc(SIZE_0);
//Impose Boundary conditions here
for(int i=0;i<X;i++)
{for(int j=0;j<Y;j++)
{for(int k=0;k<Z;k++)
{
if(i==0||i==(X-1)||j==0||j==(Y-1)||k==0||k==(Z-1))
*(DATA_H+i+j*X+k*X*Y) = 5;
else
*(DATA_H+i+j*X+k*X*Y) = 0;
}}}
//error counters
double* CC;
double CCD = 0;
//DATA pointer for device state 0
double* DATA_ORIGINAL;
//DATA pointer for device state 1
double* DATA_NEXT;
//Derivative results pointers
double* DDX_D;
double* DDY_D;
double* DDZ_D;
//array size for device
//allocating space for arrays
cudaMalloc((void**)&DATA_ORIGINAL,SIZE_0);
cudaMalloc((void**)&DATA_NEXT,SIZE_0);
cudaMalloc((void**)&DDX_D,SIZE_0);
cudaMalloc((void**)&DDY_D,SIZE_0);
cudaMalloc((void**)&DDZ_D,SIZE_0);
cudaMalloc(&CC,(int)sizeof(double));
//token counter
CCD = 10.;
//copy data state0, state1
cudaMemcpy(DATA_ORIGINAL,DATA_H,SIZE_0,cudaMemcpyHostToDevice);
cudaMemcpy(DATA_NEXT,DATA_H,SIZE_0,cudaMemcpyHostToDevice);
//counter
int ct = 0;
auto hst_st = std::chrono::high_resolution_clock::now();
//run while tolerence > differences
while(CCD>tol)
{
//reset difference every loop
RESET_CTR <<<1,1>>> (CC);
//run derivatives
DDY <<<blocks,threads>>> (DDY_D,DATA_ORIGINAL,X,Y,Z,10.);
DDZ <<<blocks,threads>>> (DDZ_D,DATA_ORIGINAL,X,Y,Z,10.);
DDX <<<blocks,threads>>> (DDX_D,DATA_ORIGINAL,X,Y,Z,10.); //add into state 1
ADD <<<blocks,threads>>> (DATA_NEXT,DDX_D,step,X,Y,Z);
ADD <<<blocks,threads>>> (DATA_NEXT,DDY_D,step,X,Y,Z);
ADD <<<blocks,threads>>> (DATA_NEXT,DDZ_D,step,X,Y,Z);
//compare state1 state 0
COMPARE<<<blocks,threads>>>(DATA_ORIGINAL,DATA_NEXT,CC,X,Y,Z);
//copy back max error
cudaMemcpy(&CCD,CC,sizeof(double),cudaMemcpyDeviceToHost);
//make state 1 as state0
ASSIGN <<<blocks,threads>>> (DATA_ORIGINAL,DATA_NEXT,X,Y,Z);
//update counter
ct += 1;
//information every 1000 loops because of visibility
if(ct%1000==0)
{
cudaMemcpy(&CCD,CC,sizeof(double),cudaMemcpyDeviceToHost);
printf("%d loops %0.6lf max error\r",ct,CCD);
}
}
//copy back final array
cudaMemcpy(DATA_F,DATA_ORIGINAL,SIZE_0,cudaMemcpyDeviceToHost);
auto hst_en = std::chrono::high_resolution_clock::now();
std::chrono::duration<float> duration = hst_en-hst_st;
std::cout<<"\nDuration: "<<duration.count()<<"\n";
//final print statement
std::cout<<"\n\nConverged in "<<ct-1<<" loops\n\n";
//file<<"Threads, X, Y, Z, Total, Time\n";
file<<threads<<","<<X<<","<<Y<<","<<Z<<","<<X*Y*Z<<","<<duration.count()<<"\n";
file.close();
//display optional
//display(DATA_F,X,Y,Z);
//free pointers
cudaFree(DATA_ORIGINAL);
cudaFree(DATA_NEXT);
cudaFree(DDX_D);
cudaFree(DDY_D);
cudaFree(DDZ_D);
return 0;
} | //Three Dimensional Poisson solver using NVIDIA CUDA
//Author: Arkavo Hait, 2021
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <cmath>
#include <time.h>
#include <chrono>
#include <string>
#include <limits.h>
#include <fstream>
using namespace std;
//Box struct
struct BOX
{
int X;
int Y;
int Z;
};
//X double derivative
__global__ void DDX(double* R, double* C,int X,int Y,int Z,double dx)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2)))
{
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=1;i<X-1;i++)
{
*(R+index+i) = (*(C+index+1+i) + *(C+index-1+i) - 2* *(C+index+i))/(dx*dx);
}
}
}
//Y double derivative
__global__ void DDY(double* R, double* C,int X,int Y,int Z, double dy)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2))){
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=1;i<Y-1;i++)
{
*(R+index+i*X) = (*(C+index+X*(i+1)) + *(C+index+X*(i-1)) - 2* *(C+index+i*X))/(dy*dy);
}}
}
//Z double derivative
__global__ void DDZ(double* R, double* C,int X,int Y,int Z, double dz)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2))){
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=0;i<Z-1;i++)
{
*(R+index+i*X*Y) = (*(C+index+X*Y*(i+1)) + *(C+index+X*Y*(i-1))- 2* *(C+index+i*X*Y))/(dz*dz);
}}
}
//parallel function to update matrices
__global__ void ASSIGN(double* R, double* C,int X,int Y,int Z)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2))){
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=1;i<X-1;i++)
{
*(R+index+i) = *(C+index+i);
}}
}
//parallel function to add two matrices
__global__ void ADD(double* R,double* C,double dt,int X,int Y,int Z)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2))){
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=0;i<X;i++)
{
*(R+index+i) += (*(C+index+i) * dt);
}}
}
//parallel function to compare two matrices, outputting a maximum difference bteween elements
__global__ void COMPARE(double* R, double* C, double* OUT_H,int X,int Y,int Z)
{
int idx = threadIdx.x + blockIdx.x*blockDim.x;
if(idx<((Y-2)*(Z-2))){
int idy = idx / (Y-2) ;
int idz = idx % (Y-2) ;
int index = idy*X + idz*X*Y + X+X*Y;
for(int i=1;i<X-1;i++)
{
if(abs(*(R+index+i)-*(C+index+i))>= *OUT_H)
{
*OUT_H = abs(*(R+index+i) - *(C+index+i));
}
}}
}
//reset function, use it to reset any pointer
__global__ void RESET_CTR(double* C)
{
*C = 0;
}
//display function, use to disaply any array [deprecated for future use]
void display(double* DATA,int X,int Y,int Z)
{
for(int k=0;k<Z;k++)
{for(int j=0;j<Y;j++)
{for(int i=0;i<X;i++)
{printf("%.2lf ",*(DATA+i+X*j+X*Z*k));}
printf("\n");}printf("\n");}
}
//main fxn, will fix with args after
int main(int argc, char* argv[])
{
std::ofstream file;
file.open("data.csv",ios::app);
//file<<"Threads, X, Y, Z, Total, Time\n";
//DECLARE YOUR VARIABLES HERE
struct BOX grid;
int threads;
//std::cout<<argc<<"\n";
if(argc==2)
{
threads = stoi(argv[1]);
grid.X=10;
grid.Y=10;
grid.Z=10;
}
if(argc>2)
{
threads = stoi(argv[1]);
grid.X = stoi(argv[2]);
grid.Y = stoi(argv[3]);
grid.Z = stoi(argv[4]);
}
std::cout<<"Threads: "<<threads<<"\n";
const int X = grid.X;
const int Y = grid.Y;
const int Z = grid.Z;
int blocks = 1 + (Y-2) * (Z-2) / threads;
std::cout<<"Blocks: "<<blocks<<"\n";
//step for double derivatives
double step = 0.001;
//tolerence
double tol = 0.00001;
std::cout<<"\nX"<<X<<" Y"<<Y<<" Z"<<Z<<" Total Capacity⇒"<<X*Y*Z<<endl;
unsigned long long SIZE_0 = ((int)sizeof(double))*X*Y*Z;
double* DATA_H;
double* DATA_F;
DATA_H = (double*)malloc(SIZE_0);
DATA_F = (double*)malloc(SIZE_0);
//Impose Boundary conditions here
for(int i=0;i<X;i++)
{for(int j=0;j<Y;j++)
{for(int k=0;k<Z;k++)
{
if(i==0||i==(X-1)||j==0||j==(Y-1)||k==0||k==(Z-1))
*(DATA_H+i+j*X+k*X*Y) = 5;
else
*(DATA_H+i+j*X+k*X*Y) = 0;
}}}
//error counters
double* CC;
double CCD = 0;
//DATA pointer for device state 0
double* DATA_ORIGINAL;
//DATA pointer for device state 1
double* DATA_NEXT;
//Derivative results pointers
double* DDX_D;
double* DDY_D;
double* DDZ_D;
//array size for device
//allocating space for arrays
hipMalloc((void**)&DATA_ORIGINAL,SIZE_0);
hipMalloc((void**)&DATA_NEXT,SIZE_0);
hipMalloc((void**)&DDX_D,SIZE_0);
hipMalloc((void**)&DDY_D,SIZE_0);
hipMalloc((void**)&DDZ_D,SIZE_0);
hipMalloc(&CC,(int)sizeof(double));
//token counter
CCD = 10.;
//copy data state0, state1
hipMemcpy(DATA_ORIGINAL,DATA_H,SIZE_0,hipMemcpyHostToDevice);
hipMemcpy(DATA_NEXT,DATA_H,SIZE_0,hipMemcpyHostToDevice);
//counter
int ct = 0;
auto hst_st = std::chrono::high_resolution_clock::now();
//run while tolerence > differences
while(CCD>tol)
{
//reset difference every loop
RESET_CTR <<<1,1>>> (CC);
//run derivatives
DDY <<<blocks,threads>>> (DDY_D,DATA_ORIGINAL,X,Y,Z,10.);
DDZ <<<blocks,threads>>> (DDZ_D,DATA_ORIGINAL,X,Y,Z,10.);
DDX <<<blocks,threads>>> (DDX_D,DATA_ORIGINAL,X,Y,Z,10.); //add into state 1
ADD <<<blocks,threads>>> (DATA_NEXT,DDX_D,step,X,Y,Z);
ADD <<<blocks,threads>>> (DATA_NEXT,DDY_D,step,X,Y,Z);
ADD <<<blocks,threads>>> (DATA_NEXT,DDZ_D,step,X,Y,Z);
//compare state1 state 0
COMPARE<<<blocks,threads>>>(DATA_ORIGINAL,DATA_NEXT,CC,X,Y,Z);
//copy back max error
hipMemcpy(&CCD,CC,sizeof(double),hipMemcpyDeviceToHost);
//make state 1 as state0
ASSIGN <<<blocks,threads>>> (DATA_ORIGINAL,DATA_NEXT,X,Y,Z);
//update counter
ct += 1;
//information every 1000 loops because of visibility
if(ct%1000==0)
{
hipMemcpy(&CCD,CC,sizeof(double),hipMemcpyDeviceToHost);
printf("%d loops %0.6lf max error\r",ct,CCD);
}
}
//copy back final array
hipMemcpy(DATA_F,DATA_ORIGINAL,SIZE_0,hipMemcpyDeviceToHost);
auto hst_en = std::chrono::high_resolution_clock::now();
std::chrono::duration<float> duration = hst_en-hst_st;
std::cout<<"\nDuration: "<<duration.count()<<"\n";
//final print statement
std::cout<<"\n\nConverged in "<<ct-1<<" loops\n\n";
//file<<"Threads, X, Y, Z, Total, Time\n";
file<<threads<<","<<X<<","<<Y<<","<<Z<<","<<X*Y*Z<<","<<duration.count()<<"\n";
file.close();
//display optional
//display(DATA_F,X,Y,Z);
//free pointers
hipFree(DATA_ORIGINAL);
hipFree(DATA_NEXT);
hipFree(DDX_D);
hipFree(DDY_D);
hipFree(DDZ_D);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* EDDL Library - European Distributed Deep Learning Library.
* Version: 1.1
* copyright (c) 2022, Universitat Politècnica de València (UPV), PRHLT Research Centre
* Date: March 2022
* Author: PRHLT Research Centre, UPV, (rparedes@prhlt.upv.es), (jon@prhlt.upv.es)
* All rights reserved
*/
#include <string.h>
#include <cstdio>
#include <cstdlib>
#include <iostream>
#include <cuda.h>
__global__ void gpu_isfinite(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isfinite(A[thread_id_x]);
}
}
__global__ void gpu_isinf(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isinf(A[thread_id_x]);
}
}
__global__ void gpu_isnan(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isnan(A[thread_id_x]);
}
}
__global__ void gpu_isneginf(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isinf(A[thread_id_x]) && A[thread_id_x] < 0.0f;
}
}
__global__ void gpu_isposinf(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isinf(A[thread_id_x]) && A[thread_id_x] > 0.0f;
}
}
__global__ void gpu_logical_and(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = (bool)A[thread_id_x] & (bool)B[thread_id_x];
}
}
__global__ void gpu_logical_or(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = (bool)A[thread_id_x] | (bool)B[thread_id_x];
}
}
__global__ void gpu_logical_not(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = !((bool)A[thread_id_x]);
}
}
__global__ void gpu_logical_xor(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = (bool)A[thread_id_x] ^ (bool)B[thread_id_x];
}
}
__global__ void gpu_allclose(float *A, float *B, float rtol, float atol, bool equal_nan, long int size, bool &allclose){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
// if(!allclose) return; // Abort if there is a result
if (thread_id_x < size && allclose){
bool close = fabsf(A[thread_id_x] - B[thread_id_x]) <= (atol + rtol * fabsf(B[thread_id_x]));
if (!close){
allclose = false;
// return;
}
}
}
__global__ void gpu_isclose(float *A, float *B, float *C, float rtol, float atol, bool equal_nan, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = fabsf(A[thread_id_x] - B[thread_id_x]) <= (atol + rtol * fabsf(B[thread_id_x]));
}
}
__global__ void gpu_greater(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] > v;
}
}
__global__ void gpu_greater(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] > B[thread_id_x];
}
}
__global__ void gpu_greater_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] >= v;
}
}
__global__ void gpu_greater_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] >= B[thread_id_x];
}
}
__global__ void gpu_less(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] < v;
}
}
__global__ void gpu_less(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] < B[thread_id_x];
}
}
__global__ void gpu_less_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] <= v;
}
}
__global__ void gpu_less_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] <= B[thread_id_x];
}
}
__global__ void gpu_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] == v;
}
}
__global__ void gpu_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] == B[thread_id_x];
}
}
__global__ void gpu_not_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] != v;
}
}
__global__ void gpu_not_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] != B[thread_id_x];
}
} | /*
* EDDL Library - European Distributed Deep Learning Library.
* Version: 1.1
* copyright (c) 2022, Universitat Politècnica de València (UPV), PRHLT Research Centre
* Date: March 2022
* Author: PRHLT Research Centre, UPV, (rparedes@prhlt.upv.es), (jon@prhlt.upv.es)
* All rights reserved
*/
#include <string.h>
#include <cstdio>
#include <cstdlib>
#include <iostream>
#include <hip/hip_runtime.h>
__global__ void gpu_isfinite(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isfinite(A[thread_id_x]);
}
}
__global__ void gpu_isinf(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isinf(A[thread_id_x]);
}
}
__global__ void gpu_isnan(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isnan(A[thread_id_x]);
}
}
__global__ void gpu_isneginf(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isinf(A[thread_id_x]) && A[thread_id_x] < 0.0f;
}
}
__global__ void gpu_isposinf(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isinf(A[thread_id_x]) && A[thread_id_x] > 0.0f;
}
}
__global__ void gpu_logical_and(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = (bool)A[thread_id_x] & (bool)B[thread_id_x];
}
}
__global__ void gpu_logical_or(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = (bool)A[thread_id_x] | (bool)B[thread_id_x];
}
}
__global__ void gpu_logical_not(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = !((bool)A[thread_id_x]);
}
}
__global__ void gpu_logical_xor(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = (bool)A[thread_id_x] ^ (bool)B[thread_id_x];
}
}
__global__ void gpu_allclose(float *A, float *B, float rtol, float atol, bool equal_nan, long int size, bool &allclose){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
// if(!allclose) return; // Abort if there is a result
if (thread_id_x < size && allclose){
bool close = fabsf(A[thread_id_x] - B[thread_id_x]) <= (atol + rtol * fabsf(B[thread_id_x]));
if (!close){
allclose = false;
// return;
}
}
}
__global__ void gpu_isclose(float *A, float *B, float *C, float rtol, float atol, bool equal_nan, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = fabsf(A[thread_id_x] - B[thread_id_x]) <= (atol + rtol * fabsf(B[thread_id_x]));
}
}
__global__ void gpu_greater(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] > v;
}
}
__global__ void gpu_greater(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] > B[thread_id_x];
}
}
__global__ void gpu_greater_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] >= v;
}
}
__global__ void gpu_greater_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] >= B[thread_id_x];
}
}
__global__ void gpu_less(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] < v;
}
}
__global__ void gpu_less(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] < B[thread_id_x];
}
}
__global__ void gpu_less_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] <= v;
}
}
__global__ void gpu_less_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] <= B[thread_id_x];
}
}
__global__ void gpu_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] == v;
}
}
__global__ void gpu_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] == B[thread_id_x];
}
}
__global__ void gpu_not_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] != v;
}
}
__global__ void gpu_not_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] != B[thread_id_x];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* EDDL Library - European Distributed Deep Learning Library.
* Version: 1.1
* copyright (c) 2022, Universitat Politècnica de València (UPV), PRHLT Research Centre
* Date: March 2022
* Author: PRHLT Research Centre, UPV, (rparedes@prhlt.upv.es), (jon@prhlt.upv.es)
* All rights reserved
*/
#include <string.h>
#include <cstdio>
#include <cstdlib>
#include <iostream>
#include <hip/hip_runtime.h>
__global__ void gpu_isfinite(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isfinite(A[thread_id_x]);
}
}
__global__ void gpu_isinf(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isinf(A[thread_id_x]);
}
}
__global__ void gpu_isnan(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isnan(A[thread_id_x]);
}
}
__global__ void gpu_isneginf(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isinf(A[thread_id_x]) && A[thread_id_x] < 0.0f;
}
}
__global__ void gpu_isposinf(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = isinf(A[thread_id_x]) && A[thread_id_x] > 0.0f;
}
}
__global__ void gpu_logical_and(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = (bool)A[thread_id_x] & (bool)B[thread_id_x];
}
}
__global__ void gpu_logical_or(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = (bool)A[thread_id_x] | (bool)B[thread_id_x];
}
}
__global__ void gpu_logical_not(float *A, float *B, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = !((bool)A[thread_id_x]);
}
}
__global__ void gpu_logical_xor(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = (bool)A[thread_id_x] ^ (bool)B[thread_id_x];
}
}
__global__ void gpu_allclose(float *A, float *B, float rtol, float atol, bool equal_nan, long int size, bool &allclose){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
// if(!allclose) return; // Abort if there is a result
if (thread_id_x < size && allclose){
bool close = fabsf(A[thread_id_x] - B[thread_id_x]) <= (atol + rtol * fabsf(B[thread_id_x]));
if (!close){
allclose = false;
// return;
}
}
}
__global__ void gpu_isclose(float *A, float *B, float *C, float rtol, float atol, bool equal_nan, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = fabsf(A[thread_id_x] - B[thread_id_x]) <= (atol + rtol * fabsf(B[thread_id_x]));
}
}
__global__ void gpu_greater(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] > v;
}
}
__global__ void gpu_greater(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] > B[thread_id_x];
}
}
__global__ void gpu_greater_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] >= v;
}
}
__global__ void gpu_greater_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] >= B[thread_id_x];
}
}
__global__ void gpu_less(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] < v;
}
}
__global__ void gpu_less(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] < B[thread_id_x];
}
}
__global__ void gpu_less_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] <= v;
}
}
__global__ void gpu_less_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] <= B[thread_id_x];
}
}
__global__ void gpu_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] == v;
}
}
__global__ void gpu_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] == B[thread_id_x];
}
}
__global__ void gpu_not_equal(float *A, float *B, float v, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
B[thread_id_x] = A[thread_id_x] != v;
}
}
__global__ void gpu_not_equal(float *A, float *B, float *C, long int size){
long int thread_id_x = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_id_x < size){
C[thread_id_x] = A[thread_id_x] != B[thread_id_x];
}
} | .text
.file "gpu_comparison_kernels.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__gpu_isfinitePfS_l # -- Begin function _Z27__device_stub__gpu_isfinitePfS_l
.p2align 4, 0x90
.type _Z27__device_stub__gpu_isfinitePfS_l,@function
_Z27__device_stub__gpu_isfinitePfS_l: # @_Z27__device_stub__gpu_isfinitePfS_l
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12gpu_isfinitePfS_l, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__gpu_isfinitePfS_l, .Lfunc_end0-_Z27__device_stub__gpu_isfinitePfS_l
.cfi_endproc
# -- End function
.globl _Z24__device_stub__gpu_isinfPfS_l # -- Begin function _Z24__device_stub__gpu_isinfPfS_l
.p2align 4, 0x90
.type _Z24__device_stub__gpu_isinfPfS_l,@function
_Z24__device_stub__gpu_isinfPfS_l: # @_Z24__device_stub__gpu_isinfPfS_l
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9gpu_isinfPfS_l, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__gpu_isinfPfS_l, .Lfunc_end1-_Z24__device_stub__gpu_isinfPfS_l
.cfi_endproc
# -- End function
.globl _Z24__device_stub__gpu_isnanPfS_l # -- Begin function _Z24__device_stub__gpu_isnanPfS_l
.p2align 4, 0x90
.type _Z24__device_stub__gpu_isnanPfS_l,@function
_Z24__device_stub__gpu_isnanPfS_l: # @_Z24__device_stub__gpu_isnanPfS_l
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9gpu_isnanPfS_l, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z24__device_stub__gpu_isnanPfS_l, .Lfunc_end2-_Z24__device_stub__gpu_isnanPfS_l
.cfi_endproc
# -- End function
.globl _Z27__device_stub__gpu_isneginfPfS_l # -- Begin function _Z27__device_stub__gpu_isneginfPfS_l
.p2align 4, 0x90
.type _Z27__device_stub__gpu_isneginfPfS_l,@function
_Z27__device_stub__gpu_isneginfPfS_l: # @_Z27__device_stub__gpu_isneginfPfS_l
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12gpu_isneginfPfS_l, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z27__device_stub__gpu_isneginfPfS_l, .Lfunc_end3-_Z27__device_stub__gpu_isneginfPfS_l
.cfi_endproc
# -- End function
.globl _Z27__device_stub__gpu_isposinfPfS_l # -- Begin function _Z27__device_stub__gpu_isposinfPfS_l
.p2align 4, 0x90
.type _Z27__device_stub__gpu_isposinfPfS_l,@function
_Z27__device_stub__gpu_isposinfPfS_l: # @_Z27__device_stub__gpu_isposinfPfS_l
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12gpu_isposinfPfS_l, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z27__device_stub__gpu_isposinfPfS_l, .Lfunc_end4-_Z27__device_stub__gpu_isposinfPfS_l
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gpu_logical_andPfS_S_l # -- Begin function _Z30__device_stub__gpu_logical_andPfS_S_l
.p2align 4, 0x90
.type _Z30__device_stub__gpu_logical_andPfS_S_l,@function
_Z30__device_stub__gpu_logical_andPfS_S_l: # @_Z30__device_stub__gpu_logical_andPfS_S_l
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gpu_logical_andPfS_S_l, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z30__device_stub__gpu_logical_andPfS_S_l, .Lfunc_end5-_Z30__device_stub__gpu_logical_andPfS_S_l
.cfi_endproc
# -- End function
.globl _Z29__device_stub__gpu_logical_orPfS_S_l # -- Begin function _Z29__device_stub__gpu_logical_orPfS_S_l
.p2align 4, 0x90
.type _Z29__device_stub__gpu_logical_orPfS_S_l,@function
_Z29__device_stub__gpu_logical_orPfS_S_l: # @_Z29__device_stub__gpu_logical_orPfS_S_l
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14gpu_logical_orPfS_S_l, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z29__device_stub__gpu_logical_orPfS_S_l, .Lfunc_end6-_Z29__device_stub__gpu_logical_orPfS_S_l
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gpu_logical_notPfS_l # -- Begin function _Z30__device_stub__gpu_logical_notPfS_l
.p2align 4, 0x90
.type _Z30__device_stub__gpu_logical_notPfS_l,@function
_Z30__device_stub__gpu_logical_notPfS_l: # @_Z30__device_stub__gpu_logical_notPfS_l
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gpu_logical_notPfS_l, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end7:
.size _Z30__device_stub__gpu_logical_notPfS_l, .Lfunc_end7-_Z30__device_stub__gpu_logical_notPfS_l
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gpu_logical_xorPfS_S_l # -- Begin function _Z30__device_stub__gpu_logical_xorPfS_S_l
.p2align 4, 0x90
.type _Z30__device_stub__gpu_logical_xorPfS_S_l,@function
_Z30__device_stub__gpu_logical_xorPfS_S_l: # @_Z30__device_stub__gpu_logical_xorPfS_S_l
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gpu_logical_xorPfS_S_l, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end8:
.size _Z30__device_stub__gpu_logical_xorPfS_S_l, .Lfunc_end8-_Z30__device_stub__gpu_logical_xorPfS_S_l
.cfi_endproc
# -- End function
.globl _Z27__device_stub__gpu_allclosePfS_ffblRb # -- Begin function _Z27__device_stub__gpu_allclosePfS_ffblRb
.p2align 4, 0x90
.type _Z27__device_stub__gpu_allclosePfS_ffblRb,@function
_Z27__device_stub__gpu_allclosePfS_ffblRb: # @_Z27__device_stub__gpu_allclosePfS_ffblRb
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movb %dl, 7(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 7(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12gpu_allclosePfS_ffblRb, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end9:
.size _Z27__device_stub__gpu_allclosePfS_ffblRb, .Lfunc_end9-_Z27__device_stub__gpu_allclosePfS_ffblRb
.cfi_endproc
# -- End function
.globl _Z26__device_stub__gpu_isclosePfS_S_ffbl # -- Begin function _Z26__device_stub__gpu_isclosePfS_S_ffbl
.p2align 4, 0x90
.type _Z26__device_stub__gpu_isclosePfS_S_ffbl,@function
_Z26__device_stub__gpu_isclosePfS_S_ffbl: # @_Z26__device_stub__gpu_isclosePfS_S_ffbl
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movb %cl, 7(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 7(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11gpu_isclosePfS_S_ffbl, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end10:
.size _Z26__device_stub__gpu_isclosePfS_S_ffbl, .Lfunc_end10-_Z26__device_stub__gpu_isclosePfS_S_ffbl
.cfi_endproc
# -- End function
.globl _Z26__device_stub__gpu_greaterPfS_fl # -- Begin function _Z26__device_stub__gpu_greaterPfS_fl
.p2align 4, 0x90
.type _Z26__device_stub__gpu_greaterPfS_fl,@function
_Z26__device_stub__gpu_greaterPfS_fl: # @_Z26__device_stub__gpu_greaterPfS_fl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11gpu_greaterPfS_fl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end11:
.size _Z26__device_stub__gpu_greaterPfS_fl, .Lfunc_end11-_Z26__device_stub__gpu_greaterPfS_fl
.cfi_endproc
# -- End function
.globl _Z26__device_stub__gpu_greaterPfS_S_l # -- Begin function _Z26__device_stub__gpu_greaterPfS_S_l
.p2align 4, 0x90
.type _Z26__device_stub__gpu_greaterPfS_S_l,@function
_Z26__device_stub__gpu_greaterPfS_S_l: # @_Z26__device_stub__gpu_greaterPfS_S_l
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11gpu_greaterPfS_S_l, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end12:
.size _Z26__device_stub__gpu_greaterPfS_S_l, .Lfunc_end12-_Z26__device_stub__gpu_greaterPfS_S_l
.cfi_endproc
# -- End function
.globl _Z32__device_stub__gpu_greater_equalPfS_fl # -- Begin function _Z32__device_stub__gpu_greater_equalPfS_fl
.p2align 4, 0x90
.type _Z32__device_stub__gpu_greater_equalPfS_fl,@function
_Z32__device_stub__gpu_greater_equalPfS_fl: # @_Z32__device_stub__gpu_greater_equalPfS_fl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17gpu_greater_equalPfS_fl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end13:
.size _Z32__device_stub__gpu_greater_equalPfS_fl, .Lfunc_end13-_Z32__device_stub__gpu_greater_equalPfS_fl
.cfi_endproc
# -- End function
.globl _Z32__device_stub__gpu_greater_equalPfS_S_l # -- Begin function _Z32__device_stub__gpu_greater_equalPfS_S_l
.p2align 4, 0x90
.type _Z32__device_stub__gpu_greater_equalPfS_S_l,@function
_Z32__device_stub__gpu_greater_equalPfS_S_l: # @_Z32__device_stub__gpu_greater_equalPfS_S_l
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17gpu_greater_equalPfS_S_l, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end14:
.size _Z32__device_stub__gpu_greater_equalPfS_S_l, .Lfunc_end14-_Z32__device_stub__gpu_greater_equalPfS_S_l
.cfi_endproc
# -- End function
.globl _Z23__device_stub__gpu_lessPfS_fl # -- Begin function _Z23__device_stub__gpu_lessPfS_fl
.p2align 4, 0x90
.type _Z23__device_stub__gpu_lessPfS_fl,@function
_Z23__device_stub__gpu_lessPfS_fl: # @_Z23__device_stub__gpu_lessPfS_fl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8gpu_lessPfS_fl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end15:
.size _Z23__device_stub__gpu_lessPfS_fl, .Lfunc_end15-_Z23__device_stub__gpu_lessPfS_fl
.cfi_endproc
# -- End function
.globl _Z23__device_stub__gpu_lessPfS_S_l # -- Begin function _Z23__device_stub__gpu_lessPfS_S_l
.p2align 4, 0x90
.type _Z23__device_stub__gpu_lessPfS_S_l,@function
_Z23__device_stub__gpu_lessPfS_S_l: # @_Z23__device_stub__gpu_lessPfS_S_l
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8gpu_lessPfS_S_l, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end16:
.size _Z23__device_stub__gpu_lessPfS_S_l, .Lfunc_end16-_Z23__device_stub__gpu_lessPfS_S_l
.cfi_endproc
# -- End function
.globl _Z29__device_stub__gpu_less_equalPfS_fl # -- Begin function _Z29__device_stub__gpu_less_equalPfS_fl
.p2align 4, 0x90
.type _Z29__device_stub__gpu_less_equalPfS_fl,@function
_Z29__device_stub__gpu_less_equalPfS_fl: # @_Z29__device_stub__gpu_less_equalPfS_fl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14gpu_less_equalPfS_fl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end17:
.size _Z29__device_stub__gpu_less_equalPfS_fl, .Lfunc_end17-_Z29__device_stub__gpu_less_equalPfS_fl
.cfi_endproc
# -- End function
.globl _Z29__device_stub__gpu_less_equalPfS_S_l # -- Begin function _Z29__device_stub__gpu_less_equalPfS_S_l
.p2align 4, 0x90
.type _Z29__device_stub__gpu_less_equalPfS_S_l,@function
_Z29__device_stub__gpu_less_equalPfS_S_l: # @_Z29__device_stub__gpu_less_equalPfS_S_l
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14gpu_less_equalPfS_S_l, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end18:
.size _Z29__device_stub__gpu_less_equalPfS_S_l, .Lfunc_end18-_Z29__device_stub__gpu_less_equalPfS_S_l
.cfi_endproc
# -- End function
.globl _Z24__device_stub__gpu_equalPfS_fl # -- Begin function _Z24__device_stub__gpu_equalPfS_fl
.p2align 4, 0x90
.type _Z24__device_stub__gpu_equalPfS_fl,@function
_Z24__device_stub__gpu_equalPfS_fl: # @_Z24__device_stub__gpu_equalPfS_fl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9gpu_equalPfS_fl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end19:
.size _Z24__device_stub__gpu_equalPfS_fl, .Lfunc_end19-_Z24__device_stub__gpu_equalPfS_fl
.cfi_endproc
# -- End function
.globl _Z24__device_stub__gpu_equalPfS_S_l # -- Begin function _Z24__device_stub__gpu_equalPfS_S_l
.p2align 4, 0x90
.type _Z24__device_stub__gpu_equalPfS_S_l,@function
_Z24__device_stub__gpu_equalPfS_S_l: # @_Z24__device_stub__gpu_equalPfS_S_l
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9gpu_equalPfS_S_l, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end20:
.size _Z24__device_stub__gpu_equalPfS_S_l, .Lfunc_end20-_Z24__device_stub__gpu_equalPfS_S_l
.cfi_endproc
# -- End function
.globl _Z28__device_stub__gpu_not_equalPfS_fl # -- Begin function _Z28__device_stub__gpu_not_equalPfS_fl
.p2align 4, 0x90
.type _Z28__device_stub__gpu_not_equalPfS_fl,@function
_Z28__device_stub__gpu_not_equalPfS_fl: # @_Z28__device_stub__gpu_not_equalPfS_fl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13gpu_not_equalPfS_fl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end21:
.size _Z28__device_stub__gpu_not_equalPfS_fl, .Lfunc_end21-_Z28__device_stub__gpu_not_equalPfS_fl
.cfi_endproc
# -- End function
.globl _Z28__device_stub__gpu_not_equalPfS_S_l # -- Begin function _Z28__device_stub__gpu_not_equalPfS_S_l
.p2align 4, 0x90
.type _Z28__device_stub__gpu_not_equalPfS_S_l,@function
_Z28__device_stub__gpu_not_equalPfS_S_l: # @_Z28__device_stub__gpu_not_equalPfS_S_l
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13gpu_not_equalPfS_S_l, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end22:
.size _Z28__device_stub__gpu_not_equalPfS_S_l, .Lfunc_end22-_Z28__device_stub__gpu_not_equalPfS_S_l
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB23_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB23_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpu_isfinitePfS_l, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpu_isinfPfS_l, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpu_isnanPfS_l, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpu_isneginfPfS_l, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpu_isposinfPfS_l, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gpu_logical_andPfS_S_l, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14gpu_logical_orPfS_S_l, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gpu_logical_notPfS_l, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gpu_logical_xorPfS_S_l, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpu_allclosePfS_ffblRb, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpu_isclosePfS_S_ffbl, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpu_greaterPfS_fl, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11gpu_greaterPfS_S_l, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17gpu_greater_equalPfS_fl, %esi
movl $.L__unnamed_14, %edx
movl $.L__unnamed_14, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17gpu_greater_equalPfS_S_l, %esi
movl $.L__unnamed_15, %edx
movl $.L__unnamed_15, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_lessPfS_fl, %esi
movl $.L__unnamed_16, %edx
movl $.L__unnamed_16, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_lessPfS_S_l, %esi
movl $.L__unnamed_17, %edx
movl $.L__unnamed_17, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14gpu_less_equalPfS_fl, %esi
movl $.L__unnamed_18, %edx
movl $.L__unnamed_18, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14gpu_less_equalPfS_S_l, %esi
movl $.L__unnamed_19, %edx
movl $.L__unnamed_19, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpu_equalPfS_fl, %esi
movl $.L__unnamed_20, %edx
movl $.L__unnamed_20, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpu_equalPfS_S_l, %esi
movl $.L__unnamed_21, %edx
movl $.L__unnamed_21, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_not_equalPfS_fl, %esi
movl $.L__unnamed_22, %edx
movl $.L__unnamed_22, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_not_equalPfS_S_l, %esi
movl $.L__unnamed_23, %edx
movl $.L__unnamed_23, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end23:
.size __hip_module_ctor, .Lfunc_end23-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB24_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB24_2:
retq
.Lfunc_end24:
.size __hip_module_dtor, .Lfunc_end24-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12gpu_isfinitePfS_l,@object # @_Z12gpu_isfinitePfS_l
.section .rodata,"a",@progbits
.globl _Z12gpu_isfinitePfS_l
.p2align 3, 0x0
_Z12gpu_isfinitePfS_l:
.quad _Z27__device_stub__gpu_isfinitePfS_l
.size _Z12gpu_isfinitePfS_l, 8
.type _Z9gpu_isinfPfS_l,@object # @_Z9gpu_isinfPfS_l
.globl _Z9gpu_isinfPfS_l
.p2align 3, 0x0
_Z9gpu_isinfPfS_l:
.quad _Z24__device_stub__gpu_isinfPfS_l
.size _Z9gpu_isinfPfS_l, 8
.type _Z9gpu_isnanPfS_l,@object # @_Z9gpu_isnanPfS_l
.globl _Z9gpu_isnanPfS_l
.p2align 3, 0x0
_Z9gpu_isnanPfS_l:
.quad _Z24__device_stub__gpu_isnanPfS_l
.size _Z9gpu_isnanPfS_l, 8
.type _Z12gpu_isneginfPfS_l,@object # @_Z12gpu_isneginfPfS_l
.globl _Z12gpu_isneginfPfS_l
.p2align 3, 0x0
_Z12gpu_isneginfPfS_l:
.quad _Z27__device_stub__gpu_isneginfPfS_l
.size _Z12gpu_isneginfPfS_l, 8
.type _Z12gpu_isposinfPfS_l,@object # @_Z12gpu_isposinfPfS_l
.globl _Z12gpu_isposinfPfS_l
.p2align 3, 0x0
_Z12gpu_isposinfPfS_l:
.quad _Z27__device_stub__gpu_isposinfPfS_l
.size _Z12gpu_isposinfPfS_l, 8
.type _Z15gpu_logical_andPfS_S_l,@object # @_Z15gpu_logical_andPfS_S_l
.globl _Z15gpu_logical_andPfS_S_l
.p2align 3, 0x0
_Z15gpu_logical_andPfS_S_l:
.quad _Z30__device_stub__gpu_logical_andPfS_S_l
.size _Z15gpu_logical_andPfS_S_l, 8
.type _Z14gpu_logical_orPfS_S_l,@object # @_Z14gpu_logical_orPfS_S_l
.globl _Z14gpu_logical_orPfS_S_l
.p2align 3, 0x0
_Z14gpu_logical_orPfS_S_l:
.quad _Z29__device_stub__gpu_logical_orPfS_S_l
.size _Z14gpu_logical_orPfS_S_l, 8
.type _Z15gpu_logical_notPfS_l,@object # @_Z15gpu_logical_notPfS_l
.globl _Z15gpu_logical_notPfS_l
.p2align 3, 0x0
_Z15gpu_logical_notPfS_l:
.quad _Z30__device_stub__gpu_logical_notPfS_l
.size _Z15gpu_logical_notPfS_l, 8
.type _Z15gpu_logical_xorPfS_S_l,@object # @_Z15gpu_logical_xorPfS_S_l
.globl _Z15gpu_logical_xorPfS_S_l
.p2align 3, 0x0
_Z15gpu_logical_xorPfS_S_l:
.quad _Z30__device_stub__gpu_logical_xorPfS_S_l
.size _Z15gpu_logical_xorPfS_S_l, 8
.type _Z12gpu_allclosePfS_ffblRb,@object # @_Z12gpu_allclosePfS_ffblRb
.globl _Z12gpu_allclosePfS_ffblRb
.p2align 3, 0x0
_Z12gpu_allclosePfS_ffblRb:
.quad _Z27__device_stub__gpu_allclosePfS_ffblRb
.size _Z12gpu_allclosePfS_ffblRb, 8
.type _Z11gpu_isclosePfS_S_ffbl,@object # @_Z11gpu_isclosePfS_S_ffbl
.globl _Z11gpu_isclosePfS_S_ffbl
.p2align 3, 0x0
_Z11gpu_isclosePfS_S_ffbl:
.quad _Z26__device_stub__gpu_isclosePfS_S_ffbl
.size _Z11gpu_isclosePfS_S_ffbl, 8
.type _Z11gpu_greaterPfS_fl,@object # @_Z11gpu_greaterPfS_fl
.globl _Z11gpu_greaterPfS_fl
.p2align 3, 0x0
_Z11gpu_greaterPfS_fl:
.quad _Z26__device_stub__gpu_greaterPfS_fl
.size _Z11gpu_greaterPfS_fl, 8
.type _Z11gpu_greaterPfS_S_l,@object # @_Z11gpu_greaterPfS_S_l
.globl _Z11gpu_greaterPfS_S_l
.p2align 3, 0x0
_Z11gpu_greaterPfS_S_l:
.quad _Z26__device_stub__gpu_greaterPfS_S_l
.size _Z11gpu_greaterPfS_S_l, 8
.type _Z17gpu_greater_equalPfS_fl,@object # @_Z17gpu_greater_equalPfS_fl
.globl _Z17gpu_greater_equalPfS_fl
.p2align 3, 0x0
_Z17gpu_greater_equalPfS_fl:
.quad _Z32__device_stub__gpu_greater_equalPfS_fl
.size _Z17gpu_greater_equalPfS_fl, 8
.type _Z17gpu_greater_equalPfS_S_l,@object # @_Z17gpu_greater_equalPfS_S_l
.globl _Z17gpu_greater_equalPfS_S_l
.p2align 3, 0x0
_Z17gpu_greater_equalPfS_S_l:
.quad _Z32__device_stub__gpu_greater_equalPfS_S_l
.size _Z17gpu_greater_equalPfS_S_l, 8
.type _Z8gpu_lessPfS_fl,@object # @_Z8gpu_lessPfS_fl
.globl _Z8gpu_lessPfS_fl
.p2align 3, 0x0
_Z8gpu_lessPfS_fl:
.quad _Z23__device_stub__gpu_lessPfS_fl
.size _Z8gpu_lessPfS_fl, 8
.type _Z8gpu_lessPfS_S_l,@object # @_Z8gpu_lessPfS_S_l
.globl _Z8gpu_lessPfS_S_l
.p2align 3, 0x0
_Z8gpu_lessPfS_S_l:
.quad _Z23__device_stub__gpu_lessPfS_S_l
.size _Z8gpu_lessPfS_S_l, 8
.type _Z14gpu_less_equalPfS_fl,@object # @_Z14gpu_less_equalPfS_fl
.globl _Z14gpu_less_equalPfS_fl
.p2align 3, 0x0
_Z14gpu_less_equalPfS_fl:
.quad _Z29__device_stub__gpu_less_equalPfS_fl
.size _Z14gpu_less_equalPfS_fl, 8
.type _Z14gpu_less_equalPfS_S_l,@object # @_Z14gpu_less_equalPfS_S_l
.globl _Z14gpu_less_equalPfS_S_l
.p2align 3, 0x0
_Z14gpu_less_equalPfS_S_l:
.quad _Z29__device_stub__gpu_less_equalPfS_S_l
.size _Z14gpu_less_equalPfS_S_l, 8
.type _Z9gpu_equalPfS_fl,@object # @_Z9gpu_equalPfS_fl
.globl _Z9gpu_equalPfS_fl
.p2align 3, 0x0
_Z9gpu_equalPfS_fl:
.quad _Z24__device_stub__gpu_equalPfS_fl
.size _Z9gpu_equalPfS_fl, 8
.type _Z9gpu_equalPfS_S_l,@object # @_Z9gpu_equalPfS_S_l
.globl _Z9gpu_equalPfS_S_l
.p2align 3, 0x0
_Z9gpu_equalPfS_S_l:
.quad _Z24__device_stub__gpu_equalPfS_S_l
.size _Z9gpu_equalPfS_S_l, 8
.type _Z13gpu_not_equalPfS_fl,@object # @_Z13gpu_not_equalPfS_fl
.globl _Z13gpu_not_equalPfS_fl
.p2align 3, 0x0
_Z13gpu_not_equalPfS_fl:
.quad _Z28__device_stub__gpu_not_equalPfS_fl
.size _Z13gpu_not_equalPfS_fl, 8
.type _Z13gpu_not_equalPfS_S_l,@object # @_Z13gpu_not_equalPfS_S_l
.globl _Z13gpu_not_equalPfS_S_l
.p2align 3, 0x0
_Z13gpu_not_equalPfS_S_l:
.quad _Z28__device_stub__gpu_not_equalPfS_S_l
.size _Z13gpu_not_equalPfS_S_l, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12gpu_isfinitePfS_l"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9gpu_isinfPfS_l"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9gpu_isnanPfS_l"
.size .L__unnamed_3, 18
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z12gpu_isneginfPfS_l"
.size .L__unnamed_4, 22
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z12gpu_isposinfPfS_l"
.size .L__unnamed_5, 22
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z15gpu_logical_andPfS_S_l"
.size .L__unnamed_6, 27
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z14gpu_logical_orPfS_S_l"
.size .L__unnamed_7, 26
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_Z15gpu_logical_notPfS_l"
.size .L__unnamed_8, 25
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "_Z15gpu_logical_xorPfS_S_l"
.size .L__unnamed_9, 27
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "_Z12gpu_allclosePfS_ffblRb"
.size .L__unnamed_10, 27
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "_Z11gpu_isclosePfS_S_ffbl"
.size .L__unnamed_11, 26
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "_Z11gpu_greaterPfS_fl"
.size .L__unnamed_12, 22
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "_Z11gpu_greaterPfS_S_l"
.size .L__unnamed_13, 23
.type .L__unnamed_14,@object # @13
.L__unnamed_14:
.asciz "_Z17gpu_greater_equalPfS_fl"
.size .L__unnamed_14, 28
.type .L__unnamed_15,@object # @14
.L__unnamed_15:
.asciz "_Z17gpu_greater_equalPfS_S_l"
.size .L__unnamed_15, 29
.type .L__unnamed_16,@object # @15
.L__unnamed_16:
.asciz "_Z8gpu_lessPfS_fl"
.size .L__unnamed_16, 18
.type .L__unnamed_17,@object # @16
.L__unnamed_17:
.asciz "_Z8gpu_lessPfS_S_l"
.size .L__unnamed_17, 19
.type .L__unnamed_18,@object # @17
.L__unnamed_18:
.asciz "_Z14gpu_less_equalPfS_fl"
.size .L__unnamed_18, 25
.type .L__unnamed_19,@object # @18
.L__unnamed_19:
.asciz "_Z14gpu_less_equalPfS_S_l"
.size .L__unnamed_19, 26
.type .L__unnamed_20,@object # @19
.L__unnamed_20:
.asciz "_Z9gpu_equalPfS_fl"
.size .L__unnamed_20, 19
.type .L__unnamed_21,@object # @20
.L__unnamed_21:
.asciz "_Z9gpu_equalPfS_S_l"
.size .L__unnamed_21, 20
.type .L__unnamed_22,@object # @21
.L__unnamed_22:
.asciz "_Z13gpu_not_equalPfS_fl"
.size .L__unnamed_22, 24
.type .L__unnamed_23,@object # @22
.L__unnamed_23:
.asciz "_Z13gpu_not_equalPfS_S_l"
.size .L__unnamed_23, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__gpu_isfinitePfS_l
.addrsig_sym _Z24__device_stub__gpu_isinfPfS_l
.addrsig_sym _Z24__device_stub__gpu_isnanPfS_l
.addrsig_sym _Z27__device_stub__gpu_isneginfPfS_l
.addrsig_sym _Z27__device_stub__gpu_isposinfPfS_l
.addrsig_sym _Z30__device_stub__gpu_logical_andPfS_S_l
.addrsig_sym _Z29__device_stub__gpu_logical_orPfS_S_l
.addrsig_sym _Z30__device_stub__gpu_logical_notPfS_l
.addrsig_sym _Z30__device_stub__gpu_logical_xorPfS_S_l
.addrsig_sym _Z27__device_stub__gpu_allclosePfS_ffblRb
.addrsig_sym _Z26__device_stub__gpu_isclosePfS_S_ffbl
.addrsig_sym _Z26__device_stub__gpu_greaterPfS_fl
.addrsig_sym _Z26__device_stub__gpu_greaterPfS_S_l
.addrsig_sym _Z32__device_stub__gpu_greater_equalPfS_fl
.addrsig_sym _Z32__device_stub__gpu_greater_equalPfS_S_l
.addrsig_sym _Z23__device_stub__gpu_lessPfS_fl
.addrsig_sym _Z23__device_stub__gpu_lessPfS_S_l
.addrsig_sym _Z29__device_stub__gpu_less_equalPfS_fl
.addrsig_sym _Z29__device_stub__gpu_less_equalPfS_S_l
.addrsig_sym _Z24__device_stub__gpu_equalPfS_fl
.addrsig_sym _Z24__device_stub__gpu_equalPfS_S_l
.addrsig_sym _Z28__device_stub__gpu_not_equalPfS_fl
.addrsig_sym _Z28__device_stub__gpu_not_equalPfS_S_l
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12gpu_isfinitePfS_l
.addrsig_sym _Z9gpu_isinfPfS_l
.addrsig_sym _Z9gpu_isnanPfS_l
.addrsig_sym _Z12gpu_isneginfPfS_l
.addrsig_sym _Z12gpu_isposinfPfS_l
.addrsig_sym _Z15gpu_logical_andPfS_S_l
.addrsig_sym _Z14gpu_logical_orPfS_S_l
.addrsig_sym _Z15gpu_logical_notPfS_l
.addrsig_sym _Z15gpu_logical_xorPfS_S_l
.addrsig_sym _Z12gpu_allclosePfS_ffblRb
.addrsig_sym _Z11gpu_isclosePfS_S_ffbl
.addrsig_sym _Z11gpu_greaterPfS_fl
.addrsig_sym _Z11gpu_greaterPfS_S_l
.addrsig_sym _Z17gpu_greater_equalPfS_fl
.addrsig_sym _Z17gpu_greater_equalPfS_S_l
.addrsig_sym _Z8gpu_lessPfS_fl
.addrsig_sym _Z8gpu_lessPfS_S_l
.addrsig_sym _Z14gpu_less_equalPfS_fl
.addrsig_sym _Z14gpu_less_equalPfS_S_l
.addrsig_sym _Z9gpu_equalPfS_fl
.addrsig_sym _Z9gpu_equalPfS_S_l
.addrsig_sym _Z13gpu_not_equalPfS_fl
.addrsig_sym _Z13gpu_not_equalPfS_S_l
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void init_sssp_data(bool * d_mask, int* d_dists, int* d_update_dists, const int source, const int num_vtx) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_vtx) {
if (source == tid) {
d_mask[tid] = true;
d_dists[tid] = 0;
d_update_dists[tid] = 0;
}
else {
d_mask[tid] = false;
d_dists[tid] = INT_MAX;
d_update_dists[tid] = INT_MAX;
}
}
} | code for sm_80
Function : _Z14init_sssp_dataPbPiS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, R0.reuse, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x040fe20003f05270 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*0090*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*00a0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005037a10 */
/* 0x000fca0000ffe4ff */
/*00b0*/ @!P0 BRA 0x170 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x040fe200078e00ff */
/*00d0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe20000010205 */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff097424 */
/* 0x000fe200078e00ff */
/*00f0*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe4000c101104 */
/*0100*/ IADD3 R4, P0, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006047a10 */
/* 0x040fe40007f1e0ff */
/*0110*/ IADD3 R6, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe40007f3e0ff */
/*0120*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe400007fe4ff */
/*0130*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000077a10 */
/* 0x000fc60000ffe4ff */
/*0140*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.WIDE R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc600078e0205 */
/*01b0*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*01c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc600078e0205 */
/*01d0*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe8000c101904 */
/*01e0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void init_sssp_data(bool * d_mask, int* d_dists, int* d_update_dists, const int source, const int num_vtx) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_vtx) {
if (source == tid) {
d_mask[tid] = true;
d_dists[tid] = 0;
d_update_dists[tid] = 0;
}
else {
d_mask[tid] = false;
d_dists[tid] = INT_MAX;
d_update_dists[tid] = INT_MAX;
}
}
} | .file "tmpxft_000c0622_00000000-6_init_sssp_data.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii
.type _Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii, @function
_Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14init_sssp_dataPbPiS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii, .-_Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii
.globl _Z14init_sssp_dataPbPiS0_ii
.type _Z14init_sssp_dataPbPiS0_ii, @function
_Z14init_sssp_dataPbPiS0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14init_sssp_dataPbPiS0_ii, .-_Z14init_sssp_dataPbPiS0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14init_sssp_dataPbPiS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14init_sssp_dataPbPiS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void init_sssp_data(bool * d_mask, int* d_dists, int* d_update_dists, const int source, const int num_vtx) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_vtx) {
if (source == tid) {
d_mask[tid] = true;
d_dists[tid] = 0;
d_update_dists[tid] = 0;
}
else {
d_mask[tid] = false;
d_dists[tid] = INT_MAX;
d_update_dists[tid] = INT_MAX;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_sssp_data(bool * d_mask, int* d_dists, int* d_update_dists, const int source, const int num_vtx) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_vtx) {
if (source == tid) {
d_mask[tid] = true;
d_dists[tid] = 0;
d_update_dists[tid] = 0;
}
else {
d_mask[tid] = false;
d_dists[tid] = INT_MAX;
d_update_dists[tid] = INT_MAX;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_sssp_data(bool * d_mask, int* d_dists, int* d_update_dists, const int source, const int num_vtx) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_vtx) {
if (source == tid) {
d_mask[tid] = true;
d_dists[tid] = 0;
d_update_dists[tid] = 0;
}
else {
d_mask[tid] = false;
d_dists[tid] = INT_MAX;
d_update_dists[tid] = INT_MAX;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14init_sssp_dataPbPiS0_ii
.globl _Z14init_sssp_dataPbPiS0_ii
.p2align 8
.type _Z14init_sssp_dataPbPiS0_ii,@function
_Z14init_sssp_dataPbPiS0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s8, v1
v_add_co_u32 v0, s0, s4, v1
v_add_co_ci_u32_e64 v1, s0, s5, v2, s0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v5, s0, s6, v3
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
v_cndmask_b32_e64 v8, 0x7fffffff, 0, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v3
v_add_co_ci_u32_e64 v6, s0, s7, v4, s0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
global_store_b8 v[0:1], v7, off
global_store_b32 v[5:6], v8, off
global_store_b32 v[2:3], v8, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14init_sssp_dataPbPiS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14init_sssp_dataPbPiS0_ii, .Lfunc_end0-_Z14init_sssp_dataPbPiS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14init_sssp_dataPbPiS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14init_sssp_dataPbPiS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void init_sssp_data(bool * d_mask, int* d_dists, int* d_update_dists, const int source, const int num_vtx) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < num_vtx) {
if (source == tid) {
d_mask[tid] = true;
d_dists[tid] = 0;
d_update_dists[tid] = 0;
}
else {
d_mask[tid] = false;
d_dists[tid] = INT_MAX;
d_update_dists[tid] = INT_MAX;
}
}
} | .text
.file "init_sssp_data.hip"
.globl _Z29__device_stub__init_sssp_dataPbPiS0_ii # -- Begin function _Z29__device_stub__init_sssp_dataPbPiS0_ii
.p2align 4, 0x90
.type _Z29__device_stub__init_sssp_dataPbPiS0_ii,@function
_Z29__device_stub__init_sssp_dataPbPiS0_ii: # @_Z29__device_stub__init_sssp_dataPbPiS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14init_sssp_dataPbPiS0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__init_sssp_dataPbPiS0_ii, .Lfunc_end0-_Z29__device_stub__init_sssp_dataPbPiS0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14init_sssp_dataPbPiS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14init_sssp_dataPbPiS0_ii,@object # @_Z14init_sssp_dataPbPiS0_ii
.section .rodata,"a",@progbits
.globl _Z14init_sssp_dataPbPiS0_ii
.p2align 3, 0x0
_Z14init_sssp_dataPbPiS0_ii:
.quad _Z29__device_stub__init_sssp_dataPbPiS0_ii
.size _Z14init_sssp_dataPbPiS0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14init_sssp_dataPbPiS0_ii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__init_sssp_dataPbPiS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14init_sssp_dataPbPiS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14init_sssp_dataPbPiS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, R0.reuse, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x040fe20003f05270 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*0090*/ IADD3 R2, P1, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f3e0ff */
/*00a0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005037a10 */
/* 0x000fca0000ffe4ff */
/*00b0*/ @!P0 BRA 0x170 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x040fe200078e00ff */
/*00d0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe20000010205 */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff097424 */
/* 0x000fe200078e00ff */
/*00f0*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe4000c101104 */
/*0100*/ IADD3 R4, P0, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006047a10 */
/* 0x040fe40007f1e0ff */
/*0110*/ IADD3 R6, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe40007f3e0ff */
/*0120*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe400007fe4ff */
/*0130*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000077a10 */
/* 0x000fc60000ffe4ff */
/*0140*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.WIDE R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc600078e0205 */
/*01b0*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*01c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc600078e0205 */
/*01d0*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe8000c101904 */
/*01e0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14init_sssp_dataPbPiS0_ii
.globl _Z14init_sssp_dataPbPiS0_ii
.p2align 8
.type _Z14init_sssp_dataPbPiS0_ii,@function
_Z14init_sssp_dataPbPiS0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s8, v1
v_add_co_u32 v0, s0, s4, v1
v_add_co_ci_u32_e64 v1, s0, s5, v2, s0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v5, s0, s6, v3
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
v_cndmask_b32_e64 v8, 0x7fffffff, 0, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v3
v_add_co_ci_u32_e64 v6, s0, s7, v4, s0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
global_store_b8 v[0:1], v7, off
global_store_b32 v[5:6], v8, off
global_store_b32 v[2:3], v8, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14init_sssp_dataPbPiS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14init_sssp_dataPbPiS0_ii, .Lfunc_end0-_Z14init_sssp_dataPbPiS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14init_sssp_dataPbPiS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14init_sssp_dataPbPiS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c0622_00000000-6_init_sssp_data.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii
.type _Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii, @function
_Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14init_sssp_dataPbPiS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii, .-_Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii
.globl _Z14init_sssp_dataPbPiS0_ii
.type _Z14init_sssp_dataPbPiS0_ii, @function
_Z14init_sssp_dataPbPiS0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14init_sssp_dataPbPiS0_iiPbPiS0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14init_sssp_dataPbPiS0_ii, .-_Z14init_sssp_dataPbPiS0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14init_sssp_dataPbPiS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14init_sssp_dataPbPiS0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "init_sssp_data.hip"
.globl _Z29__device_stub__init_sssp_dataPbPiS0_ii # -- Begin function _Z29__device_stub__init_sssp_dataPbPiS0_ii
.p2align 4, 0x90
.type _Z29__device_stub__init_sssp_dataPbPiS0_ii,@function
_Z29__device_stub__init_sssp_dataPbPiS0_ii: # @_Z29__device_stub__init_sssp_dataPbPiS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14init_sssp_dataPbPiS0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__init_sssp_dataPbPiS0_ii, .Lfunc_end0-_Z29__device_stub__init_sssp_dataPbPiS0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14init_sssp_dataPbPiS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14init_sssp_dataPbPiS0_ii,@object # @_Z14init_sssp_dataPbPiS0_ii
.section .rodata,"a",@progbits
.globl _Z14init_sssp_dataPbPiS0_ii
.p2align 3, 0x0
_Z14init_sssp_dataPbPiS0_ii:
.quad _Z29__device_stub__init_sssp_dataPbPiS0_ii
.size _Z14init_sssp_dataPbPiS0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14init_sssp_dataPbPiS0_ii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__init_sssp_dataPbPiS0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14init_sssp_dataPbPiS0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by sun on 12/9/18.
//
//
//#include "grouping.h"
//
//__host__ __device__ bool sortCorres(const pcl::Correspondence &lhs, const pcl::Correspondence &rhs) {
// return lhs.distance < rhs.distance;
//}
//
//__global__ void kernClusterCorresp(int N, const PointType* model, const PointType* scene, const pcl::Correspondence* corrs,
// const double thres, const int min_size, int* cluster){
//// extern __shared__ bool group_used[]; // N
// __shared__ int num_clustered_curr;
// // keeps whether has been used
//// if (index < N)
//// group_used[index] = false;
//// __syncthreads();
// int index = threadIdx.x + blockIdx.x * blockDim.x;
// if (index < N){
// bool in_dist[N];
//// if (!group_used[index * 2]){
// int scene_self_index = corrs[index].index_match;
// int model_self_index = corrs[index].index_query;
// Eigen::Vector3f scene_self = Eigen::Vector3f(scene[scene_self_index].x, scene[scene_self_index].y,
// scene[scene_self_index].z);
// Eigen::Vector3f model_self = Eigen::Vector3f(model[model_self_index].x, model[model_self_index].y,
// model[model_self_index].z);
// int num_consistent = 0;
// for (int i = 0; i < N; i++){
// if (i == index ) continue;
// int scene_other_index = corrs[i].index_match;
// int model_other_index = corrs[i].index_query;
// Eigen::Vector3f scene_other = Eigen::Vector3f(scene[scene_other_index].x, scene[scene_other_index].y,
// scene[scene_other_index].z);
// Eigen::Vector3f model_other = Eigen::Vector3f(model[model_other_index].x, model[model_other_index].y,
// model[model_other_index].z);
// Eigen::Vector3f dist_scene = scene_other - scene_self;
// Eigen::Vector3f dist_model = model_other - model_self;
// double dist = fabs(dist_scene.norm() - dist_model.norm());
//// if (dist > thres)
//// group_used[i] = false;
// }
//// __syncthreads();
//// if (grouped_used[index])
//// atomicAdd(&num_clustered_curr,1);
//// __syncthreads();
//// if (num_clustered_curr > min_size){
//// // update array for used & dist
//// if (group_used[index]){
//// group_used[index * 2] = true;
//// group_used[index] = false;
//// num_clustered[0] = prev_num_clustered + 1;
//// }
////
//// // run ransac
//// }
//
//// }
// }
//}
//
//
//void Grouping::groupCorrespondence() {
// if (!_input || !_scene || !_corrs){
// std::cerr << "grouping has not been correctly set up " << std::endl;
// exit(1);
// }
//
// pcl::Correspondence* dev_corrs = NULL;
// cudaMalloc((void**)&dev_corrs, _N_corrs * sizeof(pcl::Correspondence));
// checkCUDAError("cudamalloc dev_corr ");
// cudaMemcpy(dev_corrs, &(*_corrs)[0], sizeof(pcl::Correspondence), cudaMemcpyHostToDevice);
// checkCUDAError("cudamemcpy corr error");
//
// PointType *dev_input = NULL;
// cudaMalloc((void**)&dev_input, _N_input * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_input, &_input->points[0], _N_input * sizeof(PointType), cudaMemcpyHostToDevice);
//
// PointType *dev_scene = NULL;
// cudaMalloc((void**)&dev_scene, _N_scene * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_scene, &_scene->points[0], _N_scene * sizeof(PointType), cudaMemcpyHostToDevice);
//
// int *dev_num_clustered = NULL;
// cudaMalloc((void**)&dev_num_clustered, sizeof(int));
// cudaMemset(dev_num_clustered, 0, sizeof(int));
//
// int blocksize = blockSize;
// dim3 fullBlockPerGrid_points;
// if (_N_corrs < blockSize){
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blockSize - 1)/blockSize));
// }else {
// while (blocksize < _N_corrs) blocksize *= 2;
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blocksize - 1) / blocksize));
// }
//
// thrust::sort(thrust::device, dev_corrs, dev_corrs + _N_corrs, sortCorres);
//
// kernClusterCorresp<<< fullBlockPerGrid_points, blocksize>>> (_N_corrs, dev_input, dev_scene, dev_corrs, _thres, dev_num_clustered);
//
//
//} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by sun on 12/9/18.
//
//
//#include "grouping.h"
//
//__host__ __device__ bool sortCorres(const pcl::Correspondence &lhs, const pcl::Correspondence &rhs) {
// return lhs.distance < rhs.distance;
//}
//
//__global__ void kernClusterCorresp(int N, const PointType* model, const PointType* scene, const pcl::Correspondence* corrs,
// const double thres, const int min_size, int* cluster){
//// extern __shared__ bool group_used[]; // N
// __shared__ int num_clustered_curr;
// // keeps whether has been used
//// if (index < N)
//// group_used[index] = false;
//// __syncthreads();
// int index = threadIdx.x + blockIdx.x * blockDim.x;
// if (index < N){
// bool in_dist[N];
//// if (!group_used[index * 2]){
// int scene_self_index = corrs[index].index_match;
// int model_self_index = corrs[index].index_query;
// Eigen::Vector3f scene_self = Eigen::Vector3f(scene[scene_self_index].x, scene[scene_self_index].y,
// scene[scene_self_index].z);
// Eigen::Vector3f model_self = Eigen::Vector3f(model[model_self_index].x, model[model_self_index].y,
// model[model_self_index].z);
// int num_consistent = 0;
// for (int i = 0; i < N; i++){
// if (i == index ) continue;
// int scene_other_index = corrs[i].index_match;
// int model_other_index = corrs[i].index_query;
// Eigen::Vector3f scene_other = Eigen::Vector3f(scene[scene_other_index].x, scene[scene_other_index].y,
// scene[scene_other_index].z);
// Eigen::Vector3f model_other = Eigen::Vector3f(model[model_other_index].x, model[model_other_index].y,
// model[model_other_index].z);
// Eigen::Vector3f dist_scene = scene_other - scene_self;
// Eigen::Vector3f dist_model = model_other - model_self;
// double dist = fabs(dist_scene.norm() - dist_model.norm());
//// if (dist > thres)
//// group_used[i] = false;
// }
//// __syncthreads();
//// if (grouped_used[index])
//// atomicAdd(&num_clustered_curr,1);
//// __syncthreads();
//// if (num_clustered_curr > min_size){
//// // update array for used & dist
//// if (group_used[index]){
//// group_used[index * 2] = true;
//// group_used[index] = false;
//// num_clustered[0] = prev_num_clustered + 1;
//// }
////
//// // run ransac
//// }
//
//// }
// }
//}
//
//
//void Grouping::groupCorrespondence() {
// if (!_input || !_scene || !_corrs){
// std::cerr << "grouping has not been correctly set up " << std::endl;
// exit(1);
// }
//
// pcl::Correspondence* dev_corrs = NULL;
// cudaMalloc((void**)&dev_corrs, _N_corrs * sizeof(pcl::Correspondence));
// checkCUDAError("cudamalloc dev_corr ");
// cudaMemcpy(dev_corrs, &(*_corrs)[0], sizeof(pcl::Correspondence), cudaMemcpyHostToDevice);
// checkCUDAError("cudamemcpy corr error");
//
// PointType *dev_input = NULL;
// cudaMalloc((void**)&dev_input, _N_input * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_input, &_input->points[0], _N_input * sizeof(PointType), cudaMemcpyHostToDevice);
//
// PointType *dev_scene = NULL;
// cudaMalloc((void**)&dev_scene, _N_scene * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_scene, &_scene->points[0], _N_scene * sizeof(PointType), cudaMemcpyHostToDevice);
//
// int *dev_num_clustered = NULL;
// cudaMalloc((void**)&dev_num_clustered, sizeof(int));
// cudaMemset(dev_num_clustered, 0, sizeof(int));
//
// int blocksize = blockSize;
// dim3 fullBlockPerGrid_points;
// if (_N_corrs < blockSize){
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blockSize - 1)/blockSize));
// }else {
// while (blocksize < _N_corrs) blocksize *= 2;
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blocksize - 1) / blocksize));
// }
//
// thrust::sort(thrust::device, dev_corrs, dev_corrs + _N_corrs, sortCorres);
//
// kernClusterCorresp<<< fullBlockPerGrid_points, blocksize>>> (_N_corrs, dev_input, dev_scene, dev_corrs, _thres, dev_num_clustered);
//
//
//} | .file "tmpxft_0006a919_00000000-6_grouping.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by sun on 12/9/18.
//
//
//#include "grouping.h"
//
//__host__ __device__ bool sortCorres(const pcl::Correspondence &lhs, const pcl::Correspondence &rhs) {
// return lhs.distance < rhs.distance;
//}
//
//__global__ void kernClusterCorresp(int N, const PointType* model, const PointType* scene, const pcl::Correspondence* corrs,
// const double thres, const int min_size, int* cluster){
//// extern __shared__ bool group_used[]; // N
// __shared__ int num_clustered_curr;
// // keeps whether has been used
//// if (index < N)
//// group_used[index] = false;
//// __syncthreads();
// int index = threadIdx.x + blockIdx.x * blockDim.x;
// if (index < N){
// bool in_dist[N];
//// if (!group_used[index * 2]){
// int scene_self_index = corrs[index].index_match;
// int model_self_index = corrs[index].index_query;
// Eigen::Vector3f scene_self = Eigen::Vector3f(scene[scene_self_index].x, scene[scene_self_index].y,
// scene[scene_self_index].z);
// Eigen::Vector3f model_self = Eigen::Vector3f(model[model_self_index].x, model[model_self_index].y,
// model[model_self_index].z);
// int num_consistent = 0;
// for (int i = 0; i < N; i++){
// if (i == index ) continue;
// int scene_other_index = corrs[i].index_match;
// int model_other_index = corrs[i].index_query;
// Eigen::Vector3f scene_other = Eigen::Vector3f(scene[scene_other_index].x, scene[scene_other_index].y,
// scene[scene_other_index].z);
// Eigen::Vector3f model_other = Eigen::Vector3f(model[model_other_index].x, model[model_other_index].y,
// model[model_other_index].z);
// Eigen::Vector3f dist_scene = scene_other - scene_self;
// Eigen::Vector3f dist_model = model_other - model_self;
// double dist = fabs(dist_scene.norm() - dist_model.norm());
//// if (dist > thres)
//// group_used[i] = false;
// }
//// __syncthreads();
//// if (grouped_used[index])
//// atomicAdd(&num_clustered_curr,1);
//// __syncthreads();
//// if (num_clustered_curr > min_size){
//// // update array for used & dist
//// if (group_used[index]){
//// group_used[index * 2] = true;
//// group_used[index] = false;
//// num_clustered[0] = prev_num_clustered + 1;
//// }
////
//// // run ransac
//// }
//
//// }
// }
//}
//
//
//void Grouping::groupCorrespondence() {
// if (!_input || !_scene || !_corrs){
// std::cerr << "grouping has not been correctly set up " << std::endl;
// exit(1);
// }
//
// pcl::Correspondence* dev_corrs = NULL;
// cudaMalloc((void**)&dev_corrs, _N_corrs * sizeof(pcl::Correspondence));
// checkCUDAError("cudamalloc dev_corr ");
// cudaMemcpy(dev_corrs, &(*_corrs)[0], sizeof(pcl::Correspondence), cudaMemcpyHostToDevice);
// checkCUDAError("cudamemcpy corr error");
//
// PointType *dev_input = NULL;
// cudaMalloc((void**)&dev_input, _N_input * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_input, &_input->points[0], _N_input * sizeof(PointType), cudaMemcpyHostToDevice);
//
// PointType *dev_scene = NULL;
// cudaMalloc((void**)&dev_scene, _N_scene * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_scene, &_scene->points[0], _N_scene * sizeof(PointType), cudaMemcpyHostToDevice);
//
// int *dev_num_clustered = NULL;
// cudaMalloc((void**)&dev_num_clustered, sizeof(int));
// cudaMemset(dev_num_clustered, 0, sizeof(int));
//
// int blocksize = blockSize;
// dim3 fullBlockPerGrid_points;
// if (_N_corrs < blockSize){
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blockSize - 1)/blockSize));
// }else {
// while (blocksize < _N_corrs) blocksize *= 2;
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blocksize - 1) / blocksize));
// }
//
// thrust::sort(thrust::device, dev_corrs, dev_corrs + _N_corrs, sortCorres);
//
// kernClusterCorresp<<< fullBlockPerGrid_points, blocksize>>> (_N_corrs, dev_input, dev_scene, dev_corrs, _thres, dev_num_clustered);
//
//
//} | #include <hip/hip_runtime.h>
//
// Created by sun on 12/9/18.
//
//
//#include "grouping.h"
//
//__host__ __device__ bool sortCorres(const pcl::Correspondence &lhs, const pcl::Correspondence &rhs) {
// return lhs.distance < rhs.distance;
//}
//
//__global__ void kernClusterCorresp(int N, const PointType* model, const PointType* scene, const pcl::Correspondence* corrs,
// const double thres, const int min_size, int* cluster){
//// extern __shared__ bool group_used[]; // N
// __shared__ int num_clustered_curr;
// // keeps whether has been used
//// if (index < N)
//// group_used[index] = false;
//// __syncthreads();
// int index = threadIdx.x + blockIdx.x * blockDim.x;
// if (index < N){
// bool in_dist[N];
//// if (!group_used[index * 2]){
// int scene_self_index = corrs[index].index_match;
// int model_self_index = corrs[index].index_query;
// Eigen::Vector3f scene_self = Eigen::Vector3f(scene[scene_self_index].x, scene[scene_self_index].y,
// scene[scene_self_index].z);
// Eigen::Vector3f model_self = Eigen::Vector3f(model[model_self_index].x, model[model_self_index].y,
// model[model_self_index].z);
// int num_consistent = 0;
// for (int i = 0; i < N; i++){
// if (i == index ) continue;
// int scene_other_index = corrs[i].index_match;
// int model_other_index = corrs[i].index_query;
// Eigen::Vector3f scene_other = Eigen::Vector3f(scene[scene_other_index].x, scene[scene_other_index].y,
// scene[scene_other_index].z);
// Eigen::Vector3f model_other = Eigen::Vector3f(model[model_other_index].x, model[model_other_index].y,
// model[model_other_index].z);
// Eigen::Vector3f dist_scene = scene_other - scene_self;
// Eigen::Vector3f dist_model = model_other - model_self;
// double dist = fabs(dist_scene.norm() - dist_model.norm());
//// if (dist > thres)
//// group_used[i] = false;
// }
//// __syncthreads();
//// if (grouped_used[index])
//// atomicAdd(&num_clustered_curr,1);
//// __syncthreads();
//// if (num_clustered_curr > min_size){
//// // update array for used & dist
//// if (group_used[index]){
//// group_used[index * 2] = true;
//// group_used[index] = false;
//// num_clustered[0] = prev_num_clustered + 1;
//// }
////
//// // run ransac
//// }
//
//// }
// }
//}
//
//
//void Grouping::groupCorrespondence() {
// if (!_input || !_scene || !_corrs){
// std::cerr << "grouping has not been correctly set up " << std::endl;
// exit(1);
// }
//
// pcl::Correspondence* dev_corrs = NULL;
// cudaMalloc((void**)&dev_corrs, _N_corrs * sizeof(pcl::Correspondence));
// checkCUDAError("cudamalloc dev_corr ");
// cudaMemcpy(dev_corrs, &(*_corrs)[0], sizeof(pcl::Correspondence), cudaMemcpyHostToDevice);
// checkCUDAError("cudamemcpy corr error");
//
// PointType *dev_input = NULL;
// cudaMalloc((void**)&dev_input, _N_input * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_input, &_input->points[0], _N_input * sizeof(PointType), cudaMemcpyHostToDevice);
//
// PointType *dev_scene = NULL;
// cudaMalloc((void**)&dev_scene, _N_scene * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_scene, &_scene->points[0], _N_scene * sizeof(PointType), cudaMemcpyHostToDevice);
//
// int *dev_num_clustered = NULL;
// cudaMalloc((void**)&dev_num_clustered, sizeof(int));
// cudaMemset(dev_num_clustered, 0, sizeof(int));
//
// int blocksize = blockSize;
// dim3 fullBlockPerGrid_points;
// if (_N_corrs < blockSize){
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blockSize - 1)/blockSize));
// }else {
// while (blocksize < _N_corrs) blocksize *= 2;
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blocksize - 1) / blocksize));
// }
//
// thrust::sort(thrust::device, dev_corrs, dev_corrs + _N_corrs, sortCorres);
//
// kernClusterCorresp<<< fullBlockPerGrid_points, blocksize>>> (_N_corrs, dev_input, dev_scene, dev_corrs, _thres, dev_num_clustered);
//
//
//} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//
// Created by sun on 12/9/18.
//
//
//#include "grouping.h"
//
//__host__ __device__ bool sortCorres(const pcl::Correspondence &lhs, const pcl::Correspondence &rhs) {
// return lhs.distance < rhs.distance;
//}
//
//__global__ void kernClusterCorresp(int N, const PointType* model, const PointType* scene, const pcl::Correspondence* corrs,
// const double thres, const int min_size, int* cluster){
//// extern __shared__ bool group_used[]; // N
// __shared__ int num_clustered_curr;
// // keeps whether has been used
//// if (index < N)
//// group_used[index] = false;
//// __syncthreads();
// int index = threadIdx.x + blockIdx.x * blockDim.x;
// if (index < N){
// bool in_dist[N];
//// if (!group_used[index * 2]){
// int scene_self_index = corrs[index].index_match;
// int model_self_index = corrs[index].index_query;
// Eigen::Vector3f scene_self = Eigen::Vector3f(scene[scene_self_index].x, scene[scene_self_index].y,
// scene[scene_self_index].z);
// Eigen::Vector3f model_self = Eigen::Vector3f(model[model_self_index].x, model[model_self_index].y,
// model[model_self_index].z);
// int num_consistent = 0;
// for (int i = 0; i < N; i++){
// if (i == index ) continue;
// int scene_other_index = corrs[i].index_match;
// int model_other_index = corrs[i].index_query;
// Eigen::Vector3f scene_other = Eigen::Vector3f(scene[scene_other_index].x, scene[scene_other_index].y,
// scene[scene_other_index].z);
// Eigen::Vector3f model_other = Eigen::Vector3f(model[model_other_index].x, model[model_other_index].y,
// model[model_other_index].z);
// Eigen::Vector3f dist_scene = scene_other - scene_self;
// Eigen::Vector3f dist_model = model_other - model_self;
// double dist = fabs(dist_scene.norm() - dist_model.norm());
//// if (dist > thres)
//// group_used[i] = false;
// }
//// __syncthreads();
//// if (grouped_used[index])
//// atomicAdd(&num_clustered_curr,1);
//// __syncthreads();
//// if (num_clustered_curr > min_size){
//// // update array for used & dist
//// if (group_used[index]){
//// group_used[index * 2] = true;
//// group_used[index] = false;
//// num_clustered[0] = prev_num_clustered + 1;
//// }
////
//// // run ransac
//// }
//
//// }
// }
//}
//
//
//void Grouping::groupCorrespondence() {
// if (!_input || !_scene || !_corrs){
// std::cerr << "grouping has not been correctly set up " << std::endl;
// exit(1);
// }
//
// pcl::Correspondence* dev_corrs = NULL;
// cudaMalloc((void**)&dev_corrs, _N_corrs * sizeof(pcl::Correspondence));
// checkCUDAError("cudamalloc dev_corr ");
// cudaMemcpy(dev_corrs, &(*_corrs)[0], sizeof(pcl::Correspondence), cudaMemcpyHostToDevice);
// checkCUDAError("cudamemcpy corr error");
//
// PointType *dev_input = NULL;
// cudaMalloc((void**)&dev_input, _N_input * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_input, &_input->points[0], _N_input * sizeof(PointType), cudaMemcpyHostToDevice);
//
// PointType *dev_scene = NULL;
// cudaMalloc((void**)&dev_scene, _N_scene * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_scene, &_scene->points[0], _N_scene * sizeof(PointType), cudaMemcpyHostToDevice);
//
// int *dev_num_clustered = NULL;
// cudaMalloc((void**)&dev_num_clustered, sizeof(int));
// cudaMemset(dev_num_clustered, 0, sizeof(int));
//
// int blocksize = blockSize;
// dim3 fullBlockPerGrid_points;
// if (_N_corrs < blockSize){
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blockSize - 1)/blockSize));
// }else {
// while (blocksize < _N_corrs) blocksize *= 2;
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blocksize - 1) / blocksize));
// }
//
// thrust::sort(thrust::device, dev_corrs, dev_corrs + _N_corrs, sortCorres);
//
// kernClusterCorresp<<< fullBlockPerGrid_points, blocksize>>> (_N_corrs, dev_input, dev_scene, dev_corrs, _thres, dev_num_clustered);
//
//
//} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//
// Created by sun on 12/9/18.
//
//
//#include "grouping.h"
//
//__host__ __device__ bool sortCorres(const pcl::Correspondence &lhs, const pcl::Correspondence &rhs) {
// return lhs.distance < rhs.distance;
//}
//
//__global__ void kernClusterCorresp(int N, const PointType* model, const PointType* scene, const pcl::Correspondence* corrs,
// const double thres, const int min_size, int* cluster){
//// extern __shared__ bool group_used[]; // N
// __shared__ int num_clustered_curr;
// // keeps whether has been used
//// if (index < N)
//// group_used[index] = false;
//// __syncthreads();
// int index = threadIdx.x + blockIdx.x * blockDim.x;
// if (index < N){
// bool in_dist[N];
//// if (!group_used[index * 2]){
// int scene_self_index = corrs[index].index_match;
// int model_self_index = corrs[index].index_query;
// Eigen::Vector3f scene_self = Eigen::Vector3f(scene[scene_self_index].x, scene[scene_self_index].y,
// scene[scene_self_index].z);
// Eigen::Vector3f model_self = Eigen::Vector3f(model[model_self_index].x, model[model_self_index].y,
// model[model_self_index].z);
// int num_consistent = 0;
// for (int i = 0; i < N; i++){
// if (i == index ) continue;
// int scene_other_index = corrs[i].index_match;
// int model_other_index = corrs[i].index_query;
// Eigen::Vector3f scene_other = Eigen::Vector3f(scene[scene_other_index].x, scene[scene_other_index].y,
// scene[scene_other_index].z);
// Eigen::Vector3f model_other = Eigen::Vector3f(model[model_other_index].x, model[model_other_index].y,
// model[model_other_index].z);
// Eigen::Vector3f dist_scene = scene_other - scene_self;
// Eigen::Vector3f dist_model = model_other - model_self;
// double dist = fabs(dist_scene.norm() - dist_model.norm());
//// if (dist > thres)
//// group_used[i] = false;
// }
//// __syncthreads();
//// if (grouped_used[index])
//// atomicAdd(&num_clustered_curr,1);
//// __syncthreads();
//// if (num_clustered_curr > min_size){
//// // update array for used & dist
//// if (group_used[index]){
//// group_used[index * 2] = true;
//// group_used[index] = false;
//// num_clustered[0] = prev_num_clustered + 1;
//// }
////
//// // run ransac
//// }
//
//// }
// }
//}
//
//
//void Grouping::groupCorrespondence() {
// if (!_input || !_scene || !_corrs){
// std::cerr << "grouping has not been correctly set up " << std::endl;
// exit(1);
// }
//
// pcl::Correspondence* dev_corrs = NULL;
// cudaMalloc((void**)&dev_corrs, _N_corrs * sizeof(pcl::Correspondence));
// checkCUDAError("cudamalloc dev_corr ");
// cudaMemcpy(dev_corrs, &(*_corrs)[0], sizeof(pcl::Correspondence), cudaMemcpyHostToDevice);
// checkCUDAError("cudamemcpy corr error");
//
// PointType *dev_input = NULL;
// cudaMalloc((void**)&dev_input, _N_input * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_input, &_input->points[0], _N_input * sizeof(PointType), cudaMemcpyHostToDevice);
//
// PointType *dev_scene = NULL;
// cudaMalloc((void**)&dev_scene, _N_scene * sizeof(PointType));
// checkCUDAError("cudamalloc dev_input");
// cudaMemcpy(dev_scene, &_scene->points[0], _N_scene * sizeof(PointType), cudaMemcpyHostToDevice);
//
// int *dev_num_clustered = NULL;
// cudaMalloc((void**)&dev_num_clustered, sizeof(int));
// cudaMemset(dev_num_clustered, 0, sizeof(int));
//
// int blocksize = blockSize;
// dim3 fullBlockPerGrid_points;
// if (_N_corrs < blockSize){
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blockSize - 1)/blockSize));
// }else {
// while (blocksize < _N_corrs) blocksize *= 2;
// fullBlockPerGrid_points = dim3(static_cast<u_int32_t >((_N_corrs + blocksize - 1) / blocksize));
// }
//
// thrust::sort(thrust::device, dev_corrs, dev_corrs + _N_corrs, sortCorres);
//
// kernClusterCorresp<<< fullBlockPerGrid_points, blocksize>>> (_N_corrs, dev_input, dev_scene, dev_corrs, _thres, dev_num_clustered);
//
//
//} | .text
.file "grouping.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006a919_00000000-6_grouping.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "grouping.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "arguments.hh"
#include <algorithm>
Arguments::Arguments(const std::vector<std::string>& args)
: args_(args)
{}
Arguments::Arguments(int argc, char** argv)
{
for (int i = 0; i < argc; ++i)
args_.push_back(argv[i]);
}
const std::vector<std::string>& Arguments::args_get() const
{
return args_;
}
bool Arguments::has_option(char s) const
{
std::string query = "--";
query[1] = s;
return std::find(args_.begin(), args_.end(), query) != args_.end();
}
bool Arguments::has_option(const std::string& l) const
{
std::string query = "--" + l;
return std::find(args_.begin(), args_.end(), query) != args_.end();
}
bool Arguments::has_option(char s, const std::string& l) const
{
return has_option(s) || has_option(l);
}
std::string Arguments::get_option(char s) const
{
std::string query = "--";
query[1] = s;
auto it = std::find(args_.begin(), args_.end(), query);
if (it == args_.end() || (it + 1) == args_.end())
return "";
return *(it + 1);
}
std::string Arguments::get_option(const std::string& l) const
{
std::string query = "--" + l;
auto it = std::find(args_.begin(), args_.end(), query);
if (it == args_.end() || (it + 1) == args_.end())
return "";
return *(it + 1);
}
std::string Arguments::get_option(char s, const std::string& l) const
{
auto res = get_option(l);
return !res.empty() ? res : get_option(s);
}
std::size_t Arguments::size() const
{
return args_.size();
}
const std::string& Arguments::operator[](std::size_t i) const
{
return args_[i];
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "arguments.hh"
#include <algorithm>
Arguments::Arguments(const std::vector<std::string>& args)
: args_(args)
{}
Arguments::Arguments(int argc, char** argv)
{
for (int i = 0; i < argc; ++i)
args_.push_back(argv[i]);
}
const std::vector<std::string>& Arguments::args_get() const
{
return args_;
}
bool Arguments::has_option(char s) const
{
std::string query = "--";
query[1] = s;
return std::find(args_.begin(), args_.end(), query) != args_.end();
}
bool Arguments::has_option(const std::string& l) const
{
std::string query = "--" + l;
return std::find(args_.begin(), args_.end(), query) != args_.end();
}
bool Arguments::has_option(char s, const std::string& l) const
{
return has_option(s) || has_option(l);
}
std::string Arguments::get_option(char s) const
{
std::string query = "--";
query[1] = s;
auto it = std::find(args_.begin(), args_.end(), query);
if (it == args_.end() || (it + 1) == args_.end())
return "";
return *(it + 1);
}
std::string Arguments::get_option(const std::string& l) const
{
std::string query = "--" + l;
auto it = std::find(args_.begin(), args_.end(), query);
if (it == args_.end() || (it + 1) == args_.end())
return "";
return *(it + 1);
}
std::string Arguments::get_option(char s, const std::string& l) const
{
auto res = get_option(l);
return !res.empty() ? res : get_option(s);
}
std::size_t Arguments::size() const
{
return args_.size();
}
const std::string& Arguments::operator[](std::size_t i) const
{
return args_[i];
} | .file "tmpxft_001aa260_00000000-6_arguments.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZNK9Arguments8args_getB5cxx11Ev
.type _ZNK9Arguments8args_getB5cxx11Ev, @function
_ZNK9Arguments8args_getB5cxx11Ev:
.LFB3690:
.cfi_startproc
endbr64
movq %rdi, %rax
ret
.cfi_endproc
.LFE3690:
.size _ZNK9Arguments8args_getB5cxx11Ev, .-_ZNK9Arguments8args_getB5cxx11Ev
.align 2
.globl _ZNK9Arguments4sizeEv
.type _ZNK9Arguments4sizeEv, @function
_ZNK9Arguments4sizeEv:
.LFB3697:
.cfi_startproc
endbr64
movq 8(%rdi), %rax
subq (%rdi), %rax
sarq $5, %rax
ret
.cfi_endproc
.LFE3697:
.size _ZNK9Arguments4sizeEv, .-_ZNK9Arguments4sizeEv
.align 2
.globl _ZNK9ArgumentsixB5cxx11Em
.type _ZNK9ArgumentsixB5cxx11Em, @function
_ZNK9ArgumentsixB5cxx11Em:
.LFB3698:
.cfi_startproc
endbr64
movq %rsi, %rax
salq $5, %rax
addq (%rdi), %rax
ret
.cfi_endproc
.LFE3698:
.size _ZNK9ArgumentsixB5cxx11Em, .-_ZNK9ArgumentsixB5cxx11Em
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3724:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3724:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag:
.LFB4128:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L15
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L11
movzbl (%rsi), %eax
movb %al, (%rdi)
.L12:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L10:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L12
.L11:
testq %rdx, %rdx
je .L12
jmp .L10
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4128:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag:
.LFB4220:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L24
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L20
movzbl (%rsi), %eax
movb %al, (%rdi)
.L21:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L19:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L21
.L20:
testq %rdx, %rdx
je .L21
jmp .L19
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4220:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.text
.align 2
.globl _ZN9ArgumentsC2ERKSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS6_EE
.type _ZN9ArgumentsC2ERKSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS6_EE, @function
_ZN9ArgumentsC2ERKSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS6_EE:
.LFB3674:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3674
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movq %rsi, %rbp
movq 8(%rsi), %rbx
subq (%rsi), %rbx
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
je .L36
movabsq $9223372036854775776, %rax
cmpq %rbx, %rax
jb .L43
movq %rbx, %rdi
.LEHB0:
call _Znwm@PLT
movq %rax, %r14
.L27:
movq %r14, (%r12)
movq %r14, 8(%r12)
addq %r14, %rbx
movq %rbx, 16(%r12)
movq 8(%rbp), %r13
movq 0(%rbp), %rbx
cmpq %rbx, %r13
je .L37
movq %r14, %rbp
jmp .L30
.L43:
call _ZSt28__throw_bad_array_new_lengthv@PLT
.LEHE0:
.L36:
movl $0, %r14d
jmp .L27
.L44:
addq $32, %rbp
addq $32, %rbx
cmpq %rbx, %r13
je .L29
.L30:
leaq 16(%rbp), %rax
movq %rax, 0(%rbp)
movq (%rbx), %rsi
movq %rsi, %rdx
addq 8(%rbx), %rdx
movq %rbp, %rdi
.LEHB1:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.LEHE1:
jmp .L44
.L37:
movq %r14, %rbp
.L29:
movq %rbp, 8(%r12)
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
.L32:
cmpq %rbp, %r14
jne .L33
.LEHB2:
call __cxa_rethrow@PLT
.LEHE2:
.L38:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq (%r12), %rdi
movq 16(%r12), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L35
call _ZdlPvm@PLT
.L35:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L33:
movq %r14, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
addq $32, %r14
jmp .L32
.cfi_endproc
.LFE3674:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA3674:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3674-.LLSDATTD3674
.LLSDATTD3674:
.byte 0x1
.uleb128 .LLSDACSE3674-.LLSDACSB3674
.LLSDACSB3674:
.uleb128 .LEHB0-.LFB3674
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3674
.uleb128 .LEHE1-.LEHB1
.uleb128 .L39-.LFB3674
.uleb128 0x1
.uleb128 .LEHB2-.LFB3674
.uleb128 .LEHE2-.LEHB2
.uleb128 .L38-.LFB3674
.uleb128 0
.uleb128 .LEHB3-.LFB3674
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3674:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT3674:
.text
.size _ZN9ArgumentsC2ERKSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS6_EE, .-_ZN9ArgumentsC2ERKSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS6_EE
.globl _ZN9ArgumentsC1ERKSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS6_EE
.set _ZN9ArgumentsC1ERKSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS6_EE,_ZN9ArgumentsC2ERKSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS6_EE
.section .rodata._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_.str1.1,"aMS",@progbits,1
.LC0:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.type _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_, @function
_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_:
.LFB4322:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdx, %rbx
movq 8(%rdi), %r14
movq (%rdi), %r12
movq %r14, %rax
subq %r12, %rax
sarq $5, %rax
movabsq $288230376151711743, %rdx
cmpq %rdx, %rax
je .L91
movq %rdi, %r13
movq %rsi, %rbp
cmpq %r12, %r14
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L48
movabsq $288230376151711743, %rdx
cmpq %rdx, %rax
cmovbe %rax, %rdx
movq %rdx, (%rsp)
movq %rsi, %rdi
subq %r12, %rdi
movq %rdi, 8(%rsp)
testq %rax, %rax
jne .L81
movq 8(%rsp), %rdi
movq %rdi, %rax
leaq 16(%rdi), %rsi
movq %rsi, (%rdi)
movq (%rbx), %rcx
leaq 16(%rbx), %rdx
cmpq %rdx, %rcx
je .L80
movl $0, %r15d
jmp .L50
.L91:
leaq .LC0(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L99:
movq 8(%rbx), %rcx
.L51:
addq $1, %rcx
movq %rsi, %r9
cmpl $8, %ecx
jnb .L53
testb $4, %cl
jne .L92
testl %ecx, %ecx
je .L52
movzbl (%rdx), %esi
movb %sil, (%r9)
testb $2, %cl
je .L52
movl %ecx, %ecx
movzwl -2(%rdx,%rcx), %esi
movw %si, -2(%r9,%rcx)
jmp .L52
.L92:
movl (%rdx), %esi
movl %esi, (%r9)
movl %ecx, %ecx
movl -4(%rdx,%rcx), %esi
movl %esi, -4(%r9,%rcx)
jmp .L52
.L53:
movq (%rdx), %rdi
movq %rdi, (%rsi)
movl %ecx, %edi
movq -8(%rdx,%rdi), %r8
movq %r8, -8(%rsi,%rdi)
leaq 8(%rsi), %rdi
andq $-8, %rdi
subq %rdi, %rsi
movq %rdx, %r8
subq %rsi, %r8
addl %esi, %ecx
andl $-8, %ecx
cmpl $8, %ecx
jb .L52
andl $-8, %ecx
movl $0, %esi
.L57:
movl %esi, %r9d
movq (%r8,%r9), %r10
movq %r10, (%rdi,%r9)
addl $8, %esi
cmpl %ecx, %esi
jb .L57
jmp .L52
.L95:
movq -8(%rax), %rbx
leaq 1(%rbx), %rcx
cmpl $8, %ecx
jnb .L61
testb $4, %cl
jne .L93
testl %ecx, %ecx
je .L67
movzbl (%rax), %r9d
movb %r9b, (%rsi)
testb $2, %cl
je .L67
movl %ecx, %ecx
movzwl -2(%rax,%rcx), %r9d
movw %r9w, -2(%rsi,%rcx)
jmp .L67
.L93:
movl (%rax), %r9d
movl %r9d, (%rsi)
movl %ecx, %ecx
movl -4(%rax,%rcx), %r9d
movl %r9d, -4(%rsi,%rcx)
jmp .L67
.L61:
movq (%rax), %r9
movq %r9, (%rsi)
movl %ecx, %r9d
movq -8(%rax,%r9), %r10
movq %r10, -8(%rsi,%r9)
leaq 8(%rsi), %r9
andq $-8, %r9
subq %r9, %rsi
movq %rax, %r10
subq %rsi, %r10
addl %esi, %ecx
andl $-8, %ecx
cmpl $8, %ecx
jb .L67
andl $-8, %ecx
movl $0, %esi
.L65:
movl %esi, %r11d
movq (%r10,%r11), %rbx
movq %rbx, (%r9,%r11)
addl $8, %esi
cmpl %ecx, %esi
jb .L65
.L67:
movq -8(%r8), %rcx
movq %rcx, 8(%rdx)
addq $32, %rdx
addq $32, %rax
cmpq %rdi, %rax
je .L94
.L68:
leaq 16(%rdx), %rsi
movq %rsi, (%rdx)
movq %rax, %r8
movq -16(%rax), %rcx
cmpq %rax, %rcx
je .L95
movq %rcx, (%rdx)
movq (%rax), %rcx
movq %rcx, 16(%rdx)
jmp .L67
.L94:
movq %rbp, %rbx
subq %r12, %rbx
addq %r15, %rbx
.L59:
addq $32, %rbx
cmpq %r14, %rbp
je .L69
leaq 16(%rbp), %rax
leaq 16(%r14), %r8
movq %rbx, %rdx
jmp .L78
.L83:
movq %r15, %rbx
jmp .L59
.L98:
movq -8(%rcx), %rdi
addq $1, %rdi
cmpl $8, %edi
jnb .L71
testb $4, %dil
jne .L96
testl %edi, %edi
je .L77
movzbl (%rcx), %r10d
movb %r10b, (%r9)
testb $2, %dil
je .L77
movl %edi, %edi
movzwl -2(%rcx,%rdi), %ecx
movw %cx, -2(%r9,%rdi)
jmp .L77
.L96:
movl (%rcx), %r10d
movl %r10d, (%r9)
movl %edi, %edi
movl -4(%rcx,%rdi), %ecx
movl %ecx, -4(%r9,%rdi)
jmp .L77
.L71:
movq (%rcx), %r10
movq %r10, (%r9)
movl %edi, %r10d
movq -8(%rcx,%r10), %r11
movq %r11, -8(%r9,%r10)
leaq 8(%r9), %r11
andq $-8, %r11
subq %r11, %r9
subq %r9, %rcx
addl %r9d, %edi
andl $-8, %edi
cmpl $8, %edi
jb .L77
andl $-8, %edi
movl $0, %r9d
movq %rax, 8(%rsp)
.L75:
movl %r9d, %r10d
movq (%rcx,%r10), %rax
movq %rax, (%r11,%r10)
addl $8, %r9d
cmpl %edi, %r9d
jb .L75
movq 8(%rsp), %rax
.L77:
movq -8(%rsi), %rcx
movq %rcx, 8(%rdx)
addq $32, %rdx
addq $32, %rax
cmpq %r8, %rax
je .L97
.L78:
leaq 16(%rdx), %r9
movq %r9, (%rdx)
movq %rax, %rsi
movq -16(%rax), %rcx
cmpq %rcx, %rax
je .L98
movq %rcx, (%rdx)
movq (%rax), %rcx
movq %rcx, 16(%rdx)
jmp .L77
.L97:
subq %rbp, %r14
addq %r14, %rbx
.L69:
testq %r12, %r12
je .L79
movq 16(%r13), %rsi
subq %r12, %rsi
movq %r12, %rdi
call _ZdlPvm@PLT
.L79:
movq %r15, 0(%r13)
movq %rbx, 8(%r13)
movq (%rsp), %rax
salq $5, %rax
addq %r15, %rax
movq %rax, 16(%r13)
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
movq 8(%rbx), %rcx
movl $0, %r15d
jmp .L51
.L48:
movq %rsi, %rax
subq %r12, %rax
movq %rax, 8(%rsp)
movabsq $288230376151711743, %rax
movq %rax, (%rsp)
.L81:
movq (%rsp), %rdi
salq $5, %rdi
call _Znwm@PLT
movq %rax, %r15
movq 8(%rsp), %rax
addq %r15, %rax
leaq 16(%rax), %rsi
movq %rsi, (%rax)
movq (%rbx), %rcx
leaq 16(%rbx), %rdx
cmpq %rdx, %rcx
je .L99
.L50:
movq %rcx, (%rax)
movq 16(%rbx), %rcx
movq %rcx, 16(%rax)
.L52:
movq 8(%rbx), %rcx
movq %rcx, 8(%rax)
movq %rdx, (%rbx)
movq $0, 8(%rbx)
movb $0, 16(%rbx)
cmpq %r12, %rbp
je .L83
leaq 16(%r12), %rax
leaq 16(%rbp), %rdi
movq %r15, %rdx
jmp .L68
.cfi_endproc
.LFE4322:
.size _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_, .-_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "basic_string: construction from null is not valid"
.text
.align 2
.globl _ZN9ArgumentsC2EiPPc
.type _ZN9ArgumentsC2EiPPc, @function
_ZN9ArgumentsC2EiPPc:
.LFB3688:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3688
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testl %esi, %esi
jle .L100
movq %rdi, %rbp
movq %rdx, %r12
movslq %esi, %rsi
leaq (%rdx,%rsi,8), %r14
leaq 16(%rsp), %r13
jmp .L114
.L131:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L128
leaq .LC1(%rip), %rdi
.LEHB4:
call _ZSt19__throw_logic_errorPKc@PLT
.LEHE4:
.L123:
endbr64
movq %rax, %rbx
jmp .L116
.L128:
call __stack_chk_fail@PLT
.L132:
movq 8(%rbp), %rsi
cmpq 16(%rbp), %rsi
je .L104
leaq 16(%rsi), %rdx
movq %rdx, (%rsi)
movq (%rsp), %rax
cmpq %r13, %rax
je .L129
movq %rax, (%rsi)
movq 16(%rsp), %rax
movq %rax, 16(%rsi)
.L112:
movq 8(%rsp), %rax
movq %rax, 8(%rsi)
addq $32, 8(%rbp)
jmp .L113
.L129:
movq 8(%rsp), %rax
addq $1, %rax
cmpl $8, %eax
jnb .L106
testb $4, %al
jne .L130
testl %eax, %eax
je .L112
movzbl 0(%r13), %ecx
movb %cl, 16(%rsi)
testb $2, %al
je .L112
movl %eax, %eax
movzwl -2(%r13,%rax), %ecx
movw %cx, -2(%rdx,%rax)
jmp .L112
.L130:
movl 0(%r13), %ecx
movl %ecx, 16(%rsi)
movl %eax, %eax
movl -4(%r13,%rax), %ecx
movl %ecx, -4(%rdx,%rax)
jmp .L112
.L106:
movq 0(%r13), %rcx
movq %rcx, 16(%rsi)
movl %eax, %ecx
movq -8(%r13,%rcx), %rdi
movq %rdi, -8(%rdx,%rcx)
leaq 8(%rdx), %rdi
andq $-8, %rdi
subq %rdi, %rdx
movq %r13, %r9
subq %rdx, %r9
addl %edx, %eax
andl $-8, %eax
cmpl $8, %eax
jb .L112
andl $-8, %eax
movl $0, %edx
.L110:
movl %edx, %ecx
movq (%r9,%rcx), %r8
movq %r8, (%rdi,%rcx)
addl $8, %edx
cmpl %eax, %edx
jb .L110
jmp .L112
.L104:
movq %rsp, %rdx
movq %rbp, %rdi
.LEHB5:
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.LEHE5:
movq (%rsp), %rdi
cmpq %r13, %rdi
je .L113
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L113:
addq $8, %r12
cmpq %r12, %r14
je .L100
.L114:
movq (%r12), %rbx
movq %r13, (%rsp)
testq %rbx, %rbx
je .L131
movq %rbx, %rdi
call strlen@PLT
leaq (%rbx,%rax), %rdx
movq %rsp, %rdi
movq %rbx, %rsi
.LEHB6:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE6:
jmp .L132
.L124:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L116:
movq 8(%rbp), %r13
movq 0(%rbp), %r12
.L117:
cmpq %r12, %r13
jne .L119
movq 0(%rbp), %rdi
movq 16(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L120
call _ZdlPvm@PLT
.L120:
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L121
call __stack_chk_fail@PLT
.L119:
movq (%r12), %rdi
leaq 16(%r12), %rax
cmpq %rax, %rdi
je .L118
movq 16(%r12), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L118:
addq $32, %r12
jmp .L117
.L121:
movq %rbx, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.LEHE7:
.L100:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L133
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L133:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3688:
.section .gcc_except_table
.LLSDA3688:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3688-.LLSDACSB3688
.LLSDACSB3688:
.uleb128 .LEHB4-.LFB3688
.uleb128 .LEHE4-.LEHB4
.uleb128 .L123-.LFB3688
.uleb128 0
.uleb128 .LEHB5-.LFB3688
.uleb128 .LEHE5-.LEHB5
.uleb128 .L124-.LFB3688
.uleb128 0
.uleb128 .LEHB6-.LFB3688
.uleb128 .LEHE6-.LEHB6
.uleb128 .L123-.LFB3688
.uleb128 0
.uleb128 .LEHB7-.LFB3688
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE3688:
.text
.size _ZN9ArgumentsC2EiPPc, .-_ZN9ArgumentsC2EiPPc
.globl _ZN9ArgumentsC1EiPPc
.set _ZN9ArgumentsC1EiPPc,_ZN9ArgumentsC2EiPPc
.section .text._ZSt9__find_ifIN9__gnu_cxx17__normal_iteratorIPKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt6vectorIS7_SaIS7_EEEENS0_5__ops16_Iter_equals_valIS8_EEET_SH_SH_T0_St26random_access_iterator_tag,"axG",@progbits,_ZSt9__find_ifIN9__gnu_cxx17__normal_iteratorIPKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt6vectorIS7_SaIS7_EEEENS0_5__ops16_Iter_equals_valIS8_EEET_SH_SH_T0_St26random_access_iterator_tag,comdat
.weak _ZSt9__find_ifIN9__gnu_cxx17__normal_iteratorIPKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt6vectorIS7_SaIS7_EEEENS0_5__ops16_Iter_equals_valIS8_EEET_SH_SH_T0_St26random_access_iterator_tag
.type _ZSt9__find_ifIN9__gnu_cxx17__normal_iteratorIPKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt6vectorIS7_SaIS7_EEEENS0_5__ops16_Iter_equals_valIS8_EEET_SH_SH_T0_St26random_access_iterator_tag, @function
_ZSt9__find_ifIN9__gnu_cxx17__normal_iteratorIPKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt6vectorIS7_SaIS7_EEEENS0_5__ops16_Iter_equals_valIS8_EEET_SH_SH_T0_St26random_access_iterator_tag:
.LFB4330:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %r14
movq %rdx, %r13
movq %rsi, %rax
subq %rdi, %rax
sarq $7, %rax
testq %rax, %rax
jle .L156
movq %rdi, %rbx
movq 8(%rdx), %rbp
salq $7, %rax
leaq (%rdi,%rax), %r12
jmp .L147
.L168:
testq %rdx, %rdx
je .L164
movq 0(%r13), %rsi
movq (%rbx), %rdi
call memcmp@PLT
testl %eax, %eax
je .L164
movq 40(%rbx), %rdx
cmpq %rdx, %rbp
jne .L139
jmp .L155
.L169:
testq %rdx, %rdx
je .L140
.L155:
movq 0(%r13), %rsi
movq 32(%rbx), %rdi
call memcmp@PLT
testl %eax, %eax
je .L140
movq 72(%rbx), %rdx
cmpq %rbp, %rdx
jne .L142
jmp .L154
.L140:
addq $32, %rbx
.L164:
movq %rbx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L170:
.cfi_restore_state
testq %rdx, %rdx
je .L143
.L154:
movq 0(%r13), %rsi
movq 64(%rbx), %rdi
call memcmp@PLT
testl %eax, %eax
je .L143
movq 104(%rbx), %rdx
cmpq %rbp, %rdx
jne .L145
.L153:
movq 0(%r13), %rsi
movq 96(%rbx), %rdi
call memcmp@PLT
testl %eax, %eax
je .L146
.L145:
subq $-128, %rbx
cmpq %r12, %rbx
je .L135
.L147:
movq 8(%rbx), %rdx
cmpq %rbp, %rdx
je .L168
movq 40(%rbx), %rdx
cmpq %rdx, %rbp
je .L169
.L139:
movq 72(%rbx), %rdx
cmpq %rdx, %rbp
je .L170
.L142:
movq 104(%rbx), %rdx
cmpq %rdx, %rbp
jne .L145
testq %rdx, %rdx
jne .L153
.L146:
addq $96, %rbx
jmp .L164
.L143:
addq $64, %rbx
jmp .L164
.L156:
movq %rdi, %r12
.L135:
movq %r14, %rax
subq %r12, %rax
cmpq $64, %rax
je .L148
cmpq $96, %rax
je .L149
movq %r14, %rbx
cmpq $32, %rax
jne .L164
.L150:
movq 8(%r12), %rdx
movq %r14, %rbx
cmpq 8(%r13), %rdx
jne .L164
movq %r12, %rbx
testq %rdx, %rdx
je .L164
movq 0(%r13), %rsi
movq (%r12), %rdi
call memcmp@PLT
testl %eax, %eax
movq %r14, %rbx
cmove %r12, %rbx
jmp .L164
.L149:
movq 8(%r12), %rdx
cmpq 8(%r13), %rdx
je .L171
.L151:
addq $32, %r12
.L148:
movq 8(%r12), %rdx
cmpq 8(%r13), %rdx
je .L172
.L152:
addq $32, %r12
jmp .L150
.L171:
movq %r12, %rbx
testq %rdx, %rdx
je .L164
movq 0(%r13), %rsi
movq (%r12), %rdi
call memcmp@PLT
testl %eax, %eax
je .L164
jmp .L151
.L172:
movq %r12, %rbx
testq %rdx, %rdx
je .L164
movq 0(%r13), %rsi
movq (%r12), %rdi
call memcmp@PLT
testl %eax, %eax
je .L164
jmp .L152
.cfi_endproc
.LFE4330:
.size _ZSt9__find_ifIN9__gnu_cxx17__normal_iteratorIPKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt6vectorIS7_SaIS7_EEEENS0_5__ops16_Iter_equals_valIS8_EEET_SH_SH_T0_St26random_access_iterator_tag, .-_ZSt9__find_ifIN9__gnu_cxx17__normal_iteratorIPKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt6vectorIS7_SaIS7_EEEENS0_5__ops16_Iter_equals_valIS8_EEET_SH_SH_T0_St26random_access_iterator_tag
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "basic_string::append"
.LC3:
.string "--"
.LC4:
.string ""
.text
.align 2
.globl _ZNK9Arguments10get_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZNK9Arguments10get_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZNK9Arguments10get_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3695:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3695
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 8(%rdx), %r12
movq (%rdx), %r13
movq %rsp, %rdi
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
leaq 2(%r12), %rsi
.LEHB8:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm@PLT
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq $1, %rax
jbe .L192
movq %rsp, %rdi
movl $2, %edx
leaq .LC3(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L193
.L192:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L194
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L189:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L180
call __stack_chk_fail@PLT
.L194:
call __stack_chk_fail@PLT
.L193:
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq %r12, %rax
jb .L195
movq %rsp, %rdi
movq %r12, %rdx
movq %r13, %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L196
.L195:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L197
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE8:
.L197:
call __stack_chk_fail@PLT
.L180:
movq %rbx, %rdi
.LEHB9:
call _Unwind_Resume@PLT
.LEHE9:
.L196:
movq 8(%rbp), %r12
movq 0(%rbp), %rdi
movq %rsp, %rdx
movq %r12, %rsi
call _ZSt9__find_ifIN9__gnu_cxx17__normal_iteratorIPKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt6vectorIS7_SaIS7_EEEENS0_5__ops16_Iter_equals_valIS8_EEET_SH_SH_T0_St26random_access_iterator_tag
cmpq %rax, %r12
je .L181
leaq 32(%rax), %rdx
cmpq %rdx, %r12
je .L181
leaq 16(%rbx), %rdx
movq %rdx, (%rbx)
movq 32(%rax), %rsi
movq %rsi, %rdx
addq 40(%rax), %rdx
movq %rbx, %rdi
.LEHB10:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
jmp .L183
.L181:
leaq 16(%rbx), %rax
movq %rax, (%rbx)
leaq .LC4(%rip), %rsi
movq %rsi, %rdx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE10:
.L183:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L173
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L173:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L198
movq %rbx, %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L188:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L186
call __stack_chk_fail@PLT
.L186:
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.LEHE11:
.L198:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.section .gcc_except_table
.LLSDA3695:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3695-.LLSDACSB3695
.LLSDACSB3695:
.uleb128 .LEHB8-.LFB3695
.uleb128 .LEHE8-.LEHB8
.uleb128 .L189-.LFB3695
.uleb128 0
.uleb128 .LEHB9-.LFB3695
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.uleb128 .LEHB10-.LFB3695
.uleb128 .LEHE10-.LEHB10
.uleb128 .L188-.LFB3695
.uleb128 0
.uleb128 .LEHB11-.LFB3695
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.LLSDACSE3695:
.text
.size _ZNK9Arguments10get_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZNK9Arguments10get_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.align 2
.globl _ZNK9Arguments10has_optionEc
.type _ZNK9Arguments10has_optionEc, @function
_ZNK9Arguments10has_optionEc:
.LFB3691:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %r13
leaq 16(%rsp), %r12
movq %r12, (%rsp)
leaq 2+.LC3(%rip), %rdx
leaq -2(%rdx), %rsi
movq %r13, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
movq (%rsp), %rax
movb %bpl, 1(%rax)
movq 8(%rbx), %rbp
movq (%rbx), %rdi
movq %r13, %rdx
movq %rbp, %rsi
call _ZSt9__find_ifIN9__gnu_cxx17__normal_iteratorIPKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt6vectorIS7_SaIS7_EEEENS0_5__ops16_Iter_equals_valIS8_EEET_SH_SH_T0_St26random_access_iterator_tag
cmpq %rax, %rbp
setne %bl
movq (%rsp), %rdi
cmpq %r12, %rdi
je .L199
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L199:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L203
movl %ebx, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L203:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3691:
.size _ZNK9Arguments10has_optionEc, .-_ZNK9Arguments10has_optionEc
.align 2
.globl _ZNK9Arguments10get_optionB5cxx11Ec
.type _ZNK9Arguments10get_optionB5cxx11Ec, @function
_ZNK9Arguments10get_optionB5cxx11Ec:
.LFB3694:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3694
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbx
movq %rsi, %rbp
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %r13
leaq 16(%rsp), %rax
movq %rax, (%rsp)
leaq 2+.LC3(%rip), %rdx
leaq -2(%rdx), %rsi
movq %r13, %rdi
.LEHB12:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE12:
movq (%rsp), %rax
movb %r12b, 1(%rax)
movq 8(%rbp), %r12
movq 0(%rbp), %rdi
movq %r13, %rdx
movq %r12, %rsi
call _ZSt9__find_ifIN9__gnu_cxx17__normal_iteratorIPKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt6vectorIS7_SaIS7_EEEENS0_5__ops16_Iter_equals_valIS8_EEET_SH_SH_T0_St26random_access_iterator_tag
cmpq %rax, %r12
je .L205
leaq 32(%rax), %rdx
cmpq %rdx, %r12
je .L205
leaq 16(%rbx), %rdx
movq %rdx, (%rbx)
movq 32(%rax), %rsi
movq %rsi, %rdx
addq 40(%rax), %rdx
movq %rbx, %rdi
.LEHB13:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
jmp .L207
.L205:
leaq 16(%rbx), %rax
movq %rax, (%rbx)
leaq .LC4(%rip), %rsi
movq %rsi, %rdx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE13:
.L207:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L204
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L204:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L214
movq %rbx, %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L212:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L210
call __stack_chk_fail@PLT
.L210:
movq %rbx, %rdi
.LEHB14:
call _Unwind_Resume@PLT
.LEHE14:
.L214:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.section .gcc_except_table
.LLSDA3694:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3694-.LLSDACSB3694
.LLSDACSB3694:
.uleb128 .LEHB12-.LFB3694
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.uleb128 .LEHB13-.LFB3694
.uleb128 .LEHE13-.LEHB13
.uleb128 .L212-.LFB3694
.uleb128 0
.uleb128 .LEHB14-.LFB3694
.uleb128 .LEHE14-.LEHB14
.uleb128 0
.uleb128 0
.LLSDACSE3694:
.text
.size _ZNK9Arguments10get_optionB5cxx11Ec, .-_ZNK9Arguments10get_optionB5cxx11Ec
.align 2
.globl _ZNK9Arguments10get_optionEcRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZNK9Arguments10get_optionEcRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZNK9Arguments10get_optionEcRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3696:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3696
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movl %edx, %r12d
movq %rcx, %rdx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
.LEHB15:
call _ZNK9Arguments10get_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE15:
movq 8(%rsp), %rdx
testq %rdx, %rdx
je .L216
leaq 16(%rbx), %rax
movq %rax, (%rbx)
movq (%rsp), %rsi
addq %rsi, %rdx
movq %rbx, %rdi
.LEHB16:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
jmp .L217
.L216:
movsbl %r12b, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZNK9Arguments10get_optionB5cxx11Ec
.LEHE16:
.L217:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L215
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L215:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L224
movq %rbx, %rax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L222:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L220
call __stack_chk_fail@PLT
.L220:
movq %rbx, %rdi
.LEHB17:
call _Unwind_Resume@PLT
.LEHE17:
.L224:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.section .gcc_except_table
.LLSDA3696:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3696-.LLSDACSB3696
.LLSDACSB3696:
.uleb128 .LEHB15-.LFB3696
.uleb128 .LEHE15-.LEHB15
.uleb128 0
.uleb128 0
.uleb128 .LEHB16-.LFB3696
.uleb128 .LEHE16-.LEHB16
.uleb128 .L222-.LFB3696
.uleb128 0
.uleb128 .LEHB17-.LFB3696
.uleb128 .LEHE17-.LEHB17
.uleb128 0
.uleb128 0
.LLSDACSE3696:
.text
.size _ZNK9Arguments10get_optionEcRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZNK9Arguments10get_optionEcRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.align 2
.globl _ZNK9Arguments10has_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZNK9Arguments10has_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZNK9Arguments10has_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3692:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3692
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rbp
movq (%rsi), %r12
movq %rsp, %rdi
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
leaq 2(%rbp), %rsi
.LEHB18:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm@PLT
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq $1, %rax
jbe .L238
movq %rsp, %rdi
movl $2, %edx
leaq .LC3(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L239
.L238:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L240
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L235:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L232
call __stack_chk_fail@PLT
.L240:
call __stack_chk_fail@PLT
.L239:
movabsq $4611686018427387903, %rax
subq 8(%rsp), %rax
cmpq %rbp, %rax
jb .L241
movq %rsp, %rdi
movq %rbp, %rdx
movq %r12, %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L242
.L241:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L243
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE18:
.L243:
call __stack_chk_fail@PLT
.L232:
movq %rbx, %rdi
.LEHB19:
call _Unwind_Resume@PLT
.LEHE19:
.L242:
movq 8(%rbx), %rbp
movq (%rbx), %rdi
movq %rsp, %rdx
movq %rbp, %rsi
call _ZSt9__find_ifIN9__gnu_cxx17__normal_iteratorIPKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt6vectorIS7_SaIS7_EEEENS0_5__ops16_Iter_equals_valIS8_EEET_SH_SH_T0_St26random_access_iterator_tag
cmpq %rax, %rbp
setne %bl
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L225
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L225:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L244
movl %ebx, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L244:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3692:
.section .gcc_except_table
.LLSDA3692:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3692-.LLSDACSB3692
.LLSDACSB3692:
.uleb128 .LEHB18-.LFB3692
.uleb128 .LEHE18-.LEHB18
.uleb128 .L235-.LFB3692
.uleb128 0
.uleb128 .LEHB19-.LFB3692
.uleb128 .LEHE19-.LEHB19
.uleb128 0
.uleb128 0
.LLSDACSE3692:
.text
.size _ZNK9Arguments10has_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZNK9Arguments10has_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.align 2
.globl _ZNK9Arguments10has_optionEcRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZNK9Arguments10has_optionEcRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZNK9Arguments10has_optionEcRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3693:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %rdx, %rbp
movsbl %sil, %esi
call _ZNK9Arguments10has_optionEc
testb %al, %al
je .L248
.L245:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L248:
.cfi_restore_state
movq %rbp, %rsi
movq %rbx, %rdi
call _ZNK9Arguments10has_optionERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
jmp .L245
.cfi_endproc
.LFE3693:
.size _ZNK9Arguments10has_optionEcRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZNK9Arguments10has_optionEcRKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "arguments.hh"
#include <algorithm>
Arguments::Arguments(const std::vector<std::string>& args)
: args_(args)
{}
Arguments::Arguments(int argc, char** argv)
{
for (int i = 0; i < argc; ++i)
args_.push_back(argv[i]);
}
const std::vector<std::string>& Arguments::args_get() const
{
return args_;
}
bool Arguments::has_option(char s) const
{
std::string query = "--";
query[1] = s;
return std::find(args_.begin(), args_.end(), query) != args_.end();
}
bool Arguments::has_option(const std::string& l) const
{
std::string query = "--" + l;
return std::find(args_.begin(), args_.end(), query) != args_.end();
}
bool Arguments::has_option(char s, const std::string& l) const
{
return has_option(s) || has_option(l);
}
std::string Arguments::get_option(char s) const
{
std::string query = "--";
query[1] = s;
auto it = std::find(args_.begin(), args_.end(), query);
if (it == args_.end() || (it + 1) == args_.end())
return "";
return *(it + 1);
}
std::string Arguments::get_option(const std::string& l) const
{
std::string query = "--" + l;
auto it = std::find(args_.begin(), args_.end(), query);
if (it == args_.end() || (it + 1) == args_.end())
return "";
return *(it + 1);
}
std::string Arguments::get_option(char s, const std::string& l) const
{
auto res = get_option(l);
return !res.empty() ? res : get_option(s);
}
std::size_t Arguments::size() const
{
return args_.size();
}
const std::string& Arguments::operator[](std::size_t i) const
{
return args_[i];
} | #include <hip/hip_runtime.h>
#include "arguments.hh"
#include <algorithm>
Arguments::Arguments(const std::vector<std::string>& args)
: args_(args)
{}
Arguments::Arguments(int argc, char** argv)
{
for (int i = 0; i < argc; ++i)
args_.push_back(argv[i]);
}
const std::vector<std::string>& Arguments::args_get() const
{
return args_;
}
bool Arguments::has_option(char s) const
{
std::string query = "--";
query[1] = s;
return std::find(args_.begin(), args_.end(), query) != args_.end();
}
bool Arguments::has_option(const std::string& l) const
{
std::string query = "--" + l;
return std::find(args_.begin(), args_.end(), query) != args_.end();
}
bool Arguments::has_option(char s, const std::string& l) const
{
return has_option(s) || has_option(l);
}
std::string Arguments::get_option(char s) const
{
std::string query = "--";
query[1] = s;
auto it = std::find(args_.begin(), args_.end(), query);
if (it == args_.end() || (it + 1) == args_.end())
return "";
return *(it + 1);
}
std::string Arguments::get_option(const std::string& l) const
{
std::string query = "--" + l;
auto it = std::find(args_.begin(), args_.end(), query);
if (it == args_.end() || (it + 1) == args_.end())
return "";
return *(it + 1);
}
std::string Arguments::get_option(char s, const std::string& l) const
{
auto res = get_option(l);
return !res.empty() ? res : get_option(s);
}
std::size_t Arguments::size() const
{
return args_.size();
}
const std::string& Arguments::operator[](std::size_t i) const
{
return args_[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "arguments.hh"
#include <algorithm>
Arguments::Arguments(const std::vector<std::string>& args)
: args_(args)
{}
Arguments::Arguments(int argc, char** argv)
{
for (int i = 0; i < argc; ++i)
args_.push_back(argv[i]);
}
const std::vector<std::string>& Arguments::args_get() const
{
return args_;
}
bool Arguments::has_option(char s) const
{
std::string query = "--";
query[1] = s;
return std::find(args_.begin(), args_.end(), query) != args_.end();
}
bool Arguments::has_option(const std::string& l) const
{
std::string query = "--" + l;
return std::find(args_.begin(), args_.end(), query) != args_.end();
}
bool Arguments::has_option(char s, const std::string& l) const
{
return has_option(s) || has_option(l);
}
std::string Arguments::get_option(char s) const
{
std::string query = "--";
query[1] = s;
auto it = std::find(args_.begin(), args_.end(), query);
if (it == args_.end() || (it + 1) == args_.end())
return "";
return *(it + 1);
}
std::string Arguments::get_option(const std::string& l) const
{
std::string query = "--" + l;
auto it = std::find(args_.begin(), args_.end(), query);
if (it == args_.end() || (it + 1) == args_.end())
return "";
return *(it + 1);
}
std::string Arguments::get_option(char s, const std::string& l) const
{
auto res = get_option(l);
return !res.empty() ? res : get_option(s);
}
std::size_t Arguments::size() const
{
return args_.size();
}
const std::string& Arguments::operator[](std::size_t i) const
{
return args_[i];
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void calcCDF(float *cdf, unsigned int *histo, int imageWidth, int imageHeight, int length) {
__shared__ float partialScan[SIZE_CDF];
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < SIZE_CDF && i < 256) {
partialScan[i] = (float) histo[i] / (float) (imageWidth * imageHeight);
}
__syncthreads();
for (unsigned int stride = 1; stride <= SIZE_HISTO; stride *= 2) {
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index < SIZE_CDF && index < length)
partialScan[index] += partialScan[index - stride];
__syncthreads();
}
for (unsigned int stride = SIZE_HISTO / 2; stride > 0; stride /= 2) {
__syncthreads();
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index + stride < SIZE_CDF && index + stride < length) {
partialScan[index + stride] += partialScan[index];
}
}
__syncthreads();
if (i < SIZE_CDF && i < 256) {
cdf[i] += partialScan[threadIdx.x];
}
} | code for sm_80
Function : _Z7calcCDFPfPjiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x1e0 ; /* 0x000001a000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R2 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P2, PT, R0, 0xff, PT ; /* 0x000000ff0000780c */
/* 0x000fda0003f44270 */
/*0070*/ @P2 BRA 0x1d0 ; /* 0x0000015000002947 */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*00d0*/ BSSY B1, 0x1c0 ; /* 0x000000e000017945 */
/* 0x000ff00003800000 */
/*00e0*/ I2F R6, UR4 ; /* 0x0000000400067d06 */
/* 0x000e300008201400 */
/*00f0*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x001e240000001000 */
/*0100*/ FFMA R8, -R6, R7, 1 ; /* 0x3f80000006087423 */
/* 0x001fc80000000107 */
/*0110*/ FFMA R8, R7, R8, R7 ; /* 0x0000000807087223 */
/* 0x000fe40000000007 */
/*0120*/ I2F.U32 R3, R4 ; /* 0x0000000400037306 */
/* 0x004e300000201000 */
/*0130*/ FCHK P0, R3, R6 ; /* 0x0000000603007302 */
/* 0x001e220000000000 */
/*0140*/ FFMA R7, R3, R8, RZ ; /* 0x0000000803077223 */
/* 0x000fc800000000ff */
/*0150*/ FFMA R9, -R6, R7, R3 ; /* 0x0000000706097223 */
/* 0x000fc80000000103 */
/*0160*/ FFMA R7, R8, R9, R7 ; /* 0x0000000908077223 */
/* 0x000fe20000000007 */
/*0170*/ @!P0 BRA 0x1b0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0180*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe40000000f00 */
/*0190*/ CALL.REL.NOINC 0xba0 ; /* 0x00000a0000007944 */
/* 0x000fea0003c00000 */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0003 */
/*01b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01c0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e40000004800 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.SHL.U32 R5, R2, 0x2, RZ ; /* 0x0000000202057824 */
/* 0x000fe200078e00ff */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0200*/ IADD3 R3, R5.reuse, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x040fe40007ffe0ff */
/*0210*/ IADD3 R4, R5, 0x2, RZ ; /* 0x0000000205047810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fc80003f06070 */
/*0230*/ ISETP.GT.U32.OR P1, PT, R3, 0x1ff, P0 ; /* 0x000001ff0300780c */
/* 0x000fe20000724470 */
/*0240*/ IMAD.SHL.U32 R3, R4, 0x2, RZ ; /* 0x0000000204037824 */
/* 0x000fca00078e00ff */
/*0250*/ IADD3 R8, R3, -0x1, RZ ; /* 0xffffffff03087810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fc60003f06070 */
/*0270*/ @!P1 LDS.64 R6, [R2.X8] ; /* 0x0000000002069984 */
/* 0x001e220000008a00 */
/*0280*/ ISETP.GT.U32.OR P0, PT, R8, 0x1ff, P0 ; /* 0x000001ff0800780c */
/* 0x000fe20000704470 */
/*0290*/ @!P1 FADD R7, R6, R7 ; /* 0x0000000706079221 */
/* 0x001fe40000000000 */
/*02a0*/ IMAD.SHL.U32 R6, R2, 0x8, RZ ; /* 0x0000000802067824 */
/* 0x000fc600078e00ff */
/*02b0*/ @!P1 STS [R2.X8+0x4], R7 ; /* 0x0000040702009388 */
/* 0x0001e40000008800 */
/*02c0*/ IADD3 R9, R6.reuse, 0x7, RZ ; /* 0x0000000706097810 */
/* 0x040fe40007ffe0ff */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02e0*/ IADD3 R6, R6, 0xb, RZ ; /* 0x0000000b06067810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.GE.U32.AND P1, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fe20003f26070 */
/*0300*/ IMAD.SHL.U32 R7, R4, 0x8, RZ ; /* 0x0000000804077824 */
/* 0x001fc600078e00ff */
/*0310*/ ISETP.GT.U32.OR P1, PT, R9, 0x1ff, P1 ; /* 0x000001ff0900780c */
/* 0x000fe40000f24470 */
/*0320*/ IADD3 R10, R7, -0x1, RZ ; /* 0xffffffff070a7810 */
/* 0x000fca0007ffe0ff */
/*0330*/ IMAD.IADD R15, R7.reuse, 0x1, R10 ; /* 0x00000001070f7824 */
/* 0x040fe200078e020a */
/*0340*/ IADD3 R7, R7, 0x7, RZ ; /* 0x0000000707077810 */
/* 0x000fe20007ffe0ff */
/*0350*/ @!P0 LDS R8, [R4.X8+-0xc] ; /* 0xfffff40004088984 */
/* 0x000fe80000008800 */
/*0360*/ @!P0 LDS R11, [R4.X8+-0x4] ; /* 0xfffffc00040b8984 */
/* 0x000e240000008800 */
/*0370*/ @!P0 FADD R9, R8, R11 ; /* 0x0000000b08098221 */
/* 0x001fca0000000000 */
/*0380*/ @!P0 STS [R4.X8+-0x4], R9 ; /* 0xfffffc0904008388 */
/* 0x000fe80000008800 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03a0*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */
/* 0x000fc80003f06070 */
/*03b0*/ ISETP.GT.U32.OR P0, PT, R10, 0x1ff, P0 ; /* 0x000001ff0a00780c */
/* 0x000fe20000704470 */
/*03c0*/ IMAD.SHL.U32 R10, R4, 0x10, RZ ; /* 0x00000010040a7824 */
/* 0x000fe200078e00ff */
/*03d0*/ @!P1 LDS R8, [R4.X16+-0x14] ; /* 0xffffec0004089984 */
/* 0x000fe8000000c800 */
/*03e0*/ @!P1 LDS R11, [R4.X16+-0x4] ; /* 0xfffffc00040b9984 */
/* 0x000e24000000c800 */
/*03f0*/ @!P1 FADD R11, R8, R11 ; /* 0x0000000b080b9221 */
/* 0x001fe40000000000 */
/*0400*/ IMAD.SHL.U32 R8, R4, 0x20, RZ ; /* 0x0000002004087824 */
/* 0x000fc600078e00ff */
/*0410*/ @!P1 STS [R4.X16+-0x4], R11 ; /* 0xfffffc0b04009388 */
/* 0x000fe8000000c800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0430*/ ISETP.GE.U32.AND P1, PT, R15, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x000fc80003f26070 */
/*0440*/ ISETP.GT.U32.OR P1, PT, R15, 0x1ff, P1 ; /* 0x000001ff0f00780c */
/* 0x000fe20000f24470 */
/*0450*/ IMAD.IADD R15, R10.reuse, 0x1, R15 ; /* 0x000000010a0f7824 */
/* 0x040fe200078e020f */
/*0460*/ IADD3 R10, R10, 0xf, RZ ; /* 0x0000000f0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0470*/ @!P0 LDS R9, [R8+-0x24] ; /* 0xffffdc0008098984 */
/* 0x000fe80000000800 */
/*0480*/ @!P0 LDS R12, [R8+-0x4] ; /* 0xfffffc00080c8984 */
/* 0x000e240000000800 */
/*0490*/ @!P0 FADD R13, R9, R12 ; /* 0x0000000c090d8221 */
/* 0x001fe40000000000 */
/*04a0*/ IMAD.SHL.U32 R9, R4, 0x40, RZ ; /* 0x0000004004097824 */
/* 0x000fc600078e00ff */
/*04b0*/ @!P0 STS [R8+-0x4], R13 ; /* 0xfffffc0d08008388 */
/* 0x000fe80000000800 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04d0*/ ISETP.GE.U32.AND P0, PT, R15, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x000fc80003f06070 */
/*04e0*/ ISETP.GT.U32.OR P0, PT, R15, 0x1ff, P0 ; /* 0x000001ff0f00780c */
/* 0x000fe20000704470 */
/*04f0*/ IMAD.IADD R15, R8, 0x1, R15 ; /* 0x00000001080f7824 */
/* 0x000fe200078e020f */
/*0500*/ @!P1 LDS R11, [R9+-0x44] ; /* 0xffffbc00090b9984 */
/* 0x000fe80000000800 */
/*0510*/ @!P1 LDS R12, [R9+-0x4] ; /* 0xfffffc00090c9984 */
/* 0x000e240000000800 */
/*0520*/ @!P1 FADD R14, R11, R12 ; /* 0x0000000c0b0e9221 */
/* 0x001fe40000000000 */
/*0530*/ IMAD.SHL.U32 R11, R4, 0x80, RZ ; /* 0x00000080040b7824 */
/* 0x000fc600078e00ff */
/*0540*/ @!P1 STS [R9+-0x4], R14 ; /* 0xfffffc0e09009388 */
/* 0x000fe80000000800 */
/*0550*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0560*/ ISETP.GE.U32.AND P1, PT, R15, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x000fc80003f26070 */
/*0570*/ ISETP.GT.U32.OR P1, PT, R15, 0x1ff, P1 ; /* 0x000001ff0f00780c */
/* 0x000fe40000f24470 */
/*0580*/ IADD3 R15, R11, -0x1, RZ ; /* 0xffffffff0b0f7810 */
/* 0x000fe20007ffe0ff */
/*0590*/ @!P0 LDS R12, [R11+-0x84] ; /* 0xffff7c000b0c8984 */
/* 0x000fe80000000800 */
/*05a0*/ @!P0 LDS R13, [R11+-0x4] ; /* 0xfffffc000b0d8984 */
/* 0x000e240000000800 */
/*05b0*/ @!P0 FADD R16, R12, R13 ; /* 0x0000000d0c108221 */
/* 0x001fe40000000000 */
/*05c0*/ IMAD.SHL.U32 R12, R4, 0x100, RZ ; /* 0x00000100040c7824 */
/* 0x000fc600078e00ff */
/*05d0*/ @!P0 STS [R11+-0x4], R16 ; /* 0xfffffc100b008388 */
/* 0x000fe80000000800 */
/*05e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05f0*/ ISETP.GE.U32.AND P0, PT, R15.reuse, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x040fe40003f06070 */
/*0600*/ IADD3 R17, R12, -0x1, RZ ; /* 0xffffffff0c117810 */
/* 0x000fe40007ffe0ff */
/*0610*/ ISETP.GT.U32.OR P0, PT, R15, 0x1ff, P0 ; /* 0x000001ff0f00780c */
/* 0x000fe20000704470 */
/*0620*/ @!P1 LDS R13, [R12+-0x104] ; /* 0xfffefc000c0d9984 */
/* 0x000fe80000000800 */
/*0630*/ @!P1 LDS R14, [R12+-0x4] ; /* 0xfffffc000c0e9984 */
/* 0x000e240000000800 */
/*0640*/ @!P1 FADD R13, R13, R14 ; /* 0x0000000e0d0d9221 */
/* 0x001fc40000000000 */
/*0650*/ IMAD.SHL.U32 R14, R4, 0x200, RZ ; /* 0x00000200040e7824 */
/* 0x000fc600078e00ff */
/*0660*/ @!P1 STS [R12+-0x4], R13 ; /* 0xfffffc0d0c009388 */
/* 0x0001e80000000800 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0680*/ ISETP.GE.U32.AND P1, PT, R17, c[0x0][0x178], PT ; /* 0x00005e0011007a0c */
/* 0x000fc80003f26070 */
/*0690*/ ISETP.NE.OR P1, PT, R17, 0x1ff, P1 ; /* 0x000001ff1100780c */
/* 0x000fe20000f25670 */
/*06a0*/ IMAD.SHL.U32 R17, R5, 0x400, RZ ; /* 0x0000040005117824 */
/* 0x000fe200078e00ff */
/*06b0*/ IADD3 R13, R11, 0x7f, RZ ; /* 0x0000007f0b0d7810 */
/* 0x001fe20007ffe0ff */
/*06c0*/ @!P0 LDS R15, [R14+-0x204] ; /* 0xfffdfc000e0f8984 */
/* 0x000fe80000000800 */
/*06d0*/ @!P0 LDS R16, [R14+-0x4] ; /* 0xfffffc000e108984 */
/* 0x000e240000000800 */
/*06e0*/ @!P0 FADD R15, R15, R16 ; /* 0x000000100f0f8221 */
/* 0x001fca0000000000 */
/*06f0*/ @!P0 STS [R14+-0x4], R15 ; /* 0xfffffc0f0e008388 */
/* 0x0001e80000000800 */
/*0700*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0710*/ ISETP.GE.U32.AND P0, PT, R13, c[0x0][0x178], PT ; /* 0x00005e000d007a0c */
/* 0x000fc80003f06070 */
/*0720*/ ISETP.GT.U32.OR P0, PT, R13, 0x1ff, P0 ; /* 0x000001ff0d00780c */
/* 0x000fe40000704470 */
/*0730*/ IADD3 R15, R9, 0x3f, RZ ; /* 0x0000003f090f7810 */
/* 0x001fe20007ffe0ff */
/*0740*/ @!P1 LDS R16, [R17+0x3fc] ; /* 0x0003fc0011109984 */
/* 0x000fe80000000800 */
/*0750*/ @!P1 LDS R5, [0x7fc] ; /* 0x0007fc00ff059984 */
/* 0x000e240000000800 */
/*0760*/ @!P1 FADD R5, R5, R16 ; /* 0x0000001005059221 */
/* 0x001fca0000000000 */
/*0770*/ @!P1 STS [0x7fc], R5 ; /* 0x0007fc05ff009388 */
/* 0x000fe80000000800 */
/*0780*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0790*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*07a0*/ ISETP.GE.U32.AND P1, PT, R15, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x000fc80003f26070 */
/*07b0*/ ISETP.GT.U32.OR P1, PT, R15, 0x1ff, P1 ; /* 0x000001ff0f00780c */
/* 0x000fe40000f24470 */
/*07c0*/ IADD3 R15, R8, 0x1f, RZ ; /* 0x0000001f080f7810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ @!P0 LDS R13, [R14+0x1fc] ; /* 0x0001fc000e0d8984 */
/* 0x000fe80000000800 */
/*07e0*/ @!P0 LDS R16, [R14+-0x4] ; /* 0xfffffc000e108984 */
/* 0x000e240000000800 */
/*07f0*/ @!P0 FADD R13, R13, R16 ; /* 0x000000100d0d8221 */
/* 0x001fca0000000000 */
/*0800*/ @!P0 STS [R14+0x1fc], R13 ; /* 0x0001fc0d0e008388 */
/* 0x000fe80000000800 */
/*0810*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0820*/ ISETP.GE.U32.AND P0, PT, R15, c[0x0][0x178], PT ; /* 0x00005e000f007a0c */
/* 0x000fc80003f06070 */
/*0830*/ ISETP.GT.U32.OR P0, PT, R15, 0x1ff, P0 ; /* 0x000001ff0f00780c */
/* 0x000fe20000704470 */
/*0840*/ @!P1 LDS R5, [R12+0xfc] ; /* 0x0000fc000c059984 */
/* 0x000fe80000000800 */
/*0850*/ @!P1 LDS R16, [R12+-0x4] ; /* 0xfffffc000c109984 */
/* 0x000e240000000800 */
/*0860*/ @!P1 FADD R5, R5, R16 ; /* 0x0000001005059221 */
/* 0x001fca0000000000 */
/*0870*/ @!P1 STS [R12+0xfc], R5 ; /* 0x0000fc050c009388 */
/* 0x000fe80000000800 */
/*0880*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0890*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */
/* 0x000fc80003f26070 */
/*08a0*/ ISETP.GT.U32.OR P1, PT, R10, 0x1ff, P1 ; /* 0x000001ff0a00780c */
/* 0x000fe20000f24470 */
/*08b0*/ @!P0 LDS R15, [R11+0x7c] ; /* 0x00007c000b0f8984 */
/* 0x000fe80000000800 */
/*08c0*/ @!P0 LDS R14, [R11+-0x4] ; /* 0xfffffc000b0e8984 */
/* 0x000e240000000800 */
/*08d0*/ @!P0 FADD R14, R15, R14 ; /* 0x0000000e0f0e8221 */
/* 0x001fca0000000000 */
/*08e0*/ @!P0 STS [R11+0x7c], R14 ; /* 0x00007c0e0b008388 */
/* 0x000fe80000000800 */
/*08f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0900*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fc80003f06070 */
/*0910*/ ISETP.GT.U32.OR P0, PT, R7, 0x1ff, P0 ; /* 0x000001ff0700780c */
/* 0x000fe20000704470 */
/*0920*/ @!P1 LDS R10, [R9+0x3c] ; /* 0x00003c00090a9984 */
/* 0x000fe80000000800 */
/*0930*/ @!P1 LDS R5, [R9+-0x4] ; /* 0xfffffc0009059984 */
/* 0x000e240000000800 */
/*0940*/ @!P1 FADD R10, R10, R5 ; /* 0x000000050a0a9221 */
/* 0x001fca0000000000 */
/*0950*/ @!P1 STS [R9+0x3c], R10 ; /* 0x00003c0a09009388 */
/* 0x0001e80000000800 */
/*0960*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0970*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fc80003f26070 */
/*0980*/ ISETP.GT.U32.OR P1, PT, R6, 0x1ff, P1 ; /* 0x000001ff0600780c */
/* 0x000fe40000f24470 */
/*0990*/ IADD3 R9, R3, 0x1, RZ ; /* 0x0000000103097810 */
/* 0x001fe20007ffe0ff */
/*09a0*/ @!P0 LDS R5, [R8+0x1c] ; /* 0x00001c0008058984 */
/* 0x000fe80000000800 */
/*09b0*/ @!P0 LDS R12, [R8+-0x4] ; /* 0xfffffc00080c8984 */
/* 0x000e240000000800 */
/*09c0*/ @!P0 FADD R5, R5, R12 ; /* 0x0000000c05058221 */
/* 0x001fca0000000000 */
/*09d0*/ @!P0 STS [R8+0x1c], R5 ; /* 0x00001c0508008388 */
/* 0x000fe80000000800 */
/*09e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*09f0*/ ISETP.GE.U32.AND P0, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fc80003f06070 */
/*0a00*/ ISETP.GT.U32.OR P0, PT, R9, 0x1ff, P0 ; /* 0x000001ff0900780c */
/* 0x000fe20000704470 */
/*0a10*/ @!P1 LDS R6, [R4.X16+0xc] ; /* 0x00000c0004069984 */
/* 0x000fe8000000c800 */
/*0a20*/ @!P1 LDS R7, [R4.X16+-0x4] ; /* 0xfffffc0004079984 */
/* 0x000e24000000c800 */
/*0a30*/ @!P1 FADD R7, R6, R7 ; /* 0x0000000706079221 */
/* 0x001fca0000000000 */
/*0a40*/ @!P1 STS [R4.X16+0xc], R7 ; /* 0x00000c0704009388 */
/* 0x000fe8000000c800 */
/*0a50*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a60*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc80003f26070 */
/*0a70*/ ISETP.GT.U32.OR P1, PT, R4, 0x1ff, P1 ; /* 0x000001ff0400780c */
/* 0x000fe20000f24470 */
/*0a80*/ @!P0 LDS R6, [R4.X8+0x4] ; /* 0x0000040004068984 */
/* 0x000fe80000008800 */
/*0a90*/ @!P0 LDS R5, [R4.X8+-0x4] ; /* 0xfffffc0004058984 */
/* 0x000e240000008800 */
/*0aa0*/ @!P0 FADD R5, R6, R5 ; /* 0x0000000506058221 */
/* 0x001fca0000000000 */
/*0ab0*/ @!P0 STS [R4.X8+0x4], R5 ; /* 0x0000040504008388 */
/* 0x000fe80000008800 */
/*0ac0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ad0*/ @!P1 LDS R6, [R2.X8+0x8] ; /* 0x0000080002069984 */
/* 0x000fe80000008800 */
/*0ae0*/ @!P1 LDS R9, [R2.X8+0x4] ; /* 0x0000040002099984 */
/* 0x000e240000008800 */
/*0af0*/ @!P1 FADD R9, R6, R9 ; /* 0x0000000906099221 */
/* 0x001fca0000000000 */
/*0b00*/ @!P1 STS [R2.X8+0x8], R9 ; /* 0x0000080902009388 */
/* 0x0001e80000008800 */
/*0b10*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b20*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*0b30*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fe200078e00ff */
/*0b40*/ LDS R3, [R3+-0x4] ; /* 0xfffffc0003037984 */
/* 0x000e260000000800 */
/*0b50*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0205 */
/*0b60*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000e24000c1e1900 */
/*0b70*/ FADD R7, R0, R3 ; /* 0x0000000300077221 */
/* 0x001fca0000000000 */
/*0b80*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101906 */
/*0b90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ba0*/ SHF.R.U32.HI R7, RZ, 0x17, R6.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011606 */
/*0bb0*/ BSSY B2, 0x1200 ; /* 0x0000064000027945 */
/* 0x000fe20003800000 */
/*0bc0*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*0bd0*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0003 */
/*0be0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe200078ec0ff */
/*0bf0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0006 */
/*0c00*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0c10*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fe40007ffe0ff */
/*0c20*/ IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x000fc40007ffe0ff */
/*0c30*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0c40*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0c50*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0c60*/ @!P0 BRA 0xde0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0c70*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1c200 */
/*0c80*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*0c90*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0ca0*/ @P0 BRA 0x11e0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0cb0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0cc0*/ @!P0 BRA 0x11c0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0cd0*/ FSETP.NEU.FTZ.AND P3, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f7d200 */
/*0ce0*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*0cf0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*0d00*/ @!P1 BRA !P3, 0x11c0 ; /* 0x000004b000009947 */
/* 0x000fea0005800000 */
/*0d10*/ LOP3.LUT P3, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000786c0ff */
/*0d20*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*0d30*/ @P1 BRA 0x11a0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0d40*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0d50*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0d60*/ @P0 BRA 0x1170 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0d70*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0d80*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0d90*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0da0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0db0*/ @!P0 FFMA R8, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003088823 */
/* 0x000fe400000000ff */
/*0dc0*/ @!P1 FFMA R9, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006099823 */
/* 0x000fe200000000ff */
/*0dd0*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0de0*/ LEA R6, R7, 0xc0800000, 0x17 ; /* 0xc080000007067811 */
/* 0x000fe200078eb8ff */
/*0df0*/ BSSY B3, 0x1160 ; /* 0x0000036000037945 */
/* 0x000fe20003800000 */
/*0e00*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0e10*/ IMAD.IADD R6, R9, 0x1, -R6 ; /* 0x0000000109067824 */
/* 0x000fe200078e0a06 */
/*0e20*/ IADD3 R7, R5.reuse, 0x7f, -R7 ; /* 0x0000007f05077810 */
/* 0x040fe20007ffe807 */
/*0e30*/ IMAD R8, R5, -0x800000, R8 ; /* 0xff80000005087824 */
/* 0x000fe400078e0208 */
/*0e40*/ MUFU.RCP R3, R6 ; /* 0x0000000600037308 */
/* 0x000e220000001000 */
/*0e50*/ FADD.FTZ R9, -R6, -RZ ; /* 0x800000ff06097221 */
/* 0x000fe40000010100 */
/*0e60*/ IMAD.IADD R10, R7, 0x1, R10 ; /* 0x00000001070a7824 */
/* 0x000fe400078e020a */
/*0e70*/ FFMA R12, R3, R9, 1 ; /* 0x3f800000030c7423 */
/* 0x001fc80000000009 */
/*0e80*/ FFMA R11, R3, R12, R3 ; /* 0x0000000c030b7223 */
/* 0x000fc80000000003 */
/*0e90*/ FFMA R3, R8, R11, RZ ; /* 0x0000000b08037223 */
/* 0x000fc800000000ff */
/*0ea0*/ FFMA R12, R9, R3, R8 ; /* 0x00000003090c7223 */
/* 0x000fc80000000008 */
/*0eb0*/ FFMA R12, R11, R12, R3 ; /* 0x0000000c0b0c7223 */
/* 0x000fc80000000003 */
/*0ec0*/ FFMA R8, R9, R12, R8 ; /* 0x0000000c09087223 */
/* 0x000fc80000000008 */
/*0ed0*/ FFMA R3, R11, R8, R12 ; /* 0x000000080b037223 */
/* 0x000fca000000000c */
/*0ee0*/ SHF.R.U32.HI R5, RZ, 0x17, R3 ; /* 0x00000017ff057819 */
/* 0x000fc80000011603 */
/*0ef0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0f00*/ IMAD.IADD R9, R5, 0x1, R10 ; /* 0x0000000105097824 */
/* 0x000fca00078e020a */
/*0f10*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*0f20*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0f30*/ @!P0 BRA 0x1140 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0f40*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0f50*/ @P0 BRA 0x1110 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0f60*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0f70*/ @P0 BRA 0x1150 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0f80*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0f90*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0fa0*/ @!P0 BRA 0x1150 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0fb0*/ FFMA.RZ R5, R11, R8.reuse, R12.reuse ; /* 0x000000080b057223 */
/* 0x180fe2000000c00c */
/*0fc0*/ ISETP.NE.AND P3, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f65270 */
/*0fd0*/ FFMA.RM R6, R11, R8.reuse, R12.reuse ; /* 0x000000080b067223 */
/* 0x180fe2000000400c */
/*0fe0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0ff0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*1000*/ FFMA.RP R5, R11, R8, R12 ; /* 0x000000080b057223 */
/* 0x000fe2000000800c */
/*1010*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*1020*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*1030*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*1040*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*1050*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*1060*/ SEL R6, R9, RZ, P3 ; /* 0x000000ff09067207 */
/* 0x000fe40001800000 */
/*1070*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*1080*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*1090*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*10a0*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*10b0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*10c0*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*10d0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*10e0*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*10f0*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*1100*/ BRA 0x1150 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*1110*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*1120*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*1130*/ BRA 0x1150 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1140*/ IMAD R3, R10, 0x800000, R3 ; /* 0x008000000a037824 */
/* 0x000fe400078e0203 */
/*1150*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*1160*/ BRA 0x11f0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1170*/ LOP3.LUT R3, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009037812 */
/* 0x000fc800078e4808 */
/*1180*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*1190*/ BRA 0x11f0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*11a0*/ LOP3.LUT R3, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009037812 */
/* 0x000fe200078e4808 */
/*11b0*/ BRA 0x11f0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*11c0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*11d0*/ BRA 0x11f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*11e0*/ FADD.FTZ R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x000fe40000010000 */
/*11f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1200*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*1210*/ RET.REL.NODEC R4 0x0 ; /* 0xffffede004007950 */
/* 0x000fea0003c3ffff */
/*1220*/ BRA 0x1220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void calcCDF(float *cdf, unsigned int *histo, int imageWidth, int imageHeight, int length) {
__shared__ float partialScan[SIZE_CDF];
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < SIZE_CDF && i < 256) {
partialScan[i] = (float) histo[i] / (float) (imageWidth * imageHeight);
}
__syncthreads();
for (unsigned int stride = 1; stride <= SIZE_HISTO; stride *= 2) {
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index < SIZE_CDF && index < length)
partialScan[index] += partialScan[index - stride];
__syncthreads();
}
for (unsigned int stride = SIZE_HISTO / 2; stride > 0; stride /= 2) {
__syncthreads();
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index + stride < SIZE_CDF && index + stride < length) {
partialScan[index + stride] += partialScan[index];
}
}
__syncthreads();
if (i < SIZE_CDF && i < 256) {
cdf[i] += partialScan[threadIdx.x];
}
} | .file "tmpxft_00053062_00000000-6_calcCDF.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii
.type _Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii, @function
_Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7calcCDFPfPjiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii, .-_Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii
.globl _Z7calcCDFPfPjiii
.type _Z7calcCDFPfPjiii, @function
_Z7calcCDFPfPjiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7calcCDFPfPjiii, .-_Z7calcCDFPfPjiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7calcCDFPfPjiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7calcCDFPfPjiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void calcCDF(float *cdf, unsigned int *histo, int imageWidth, int imageHeight, int length) {
__shared__ float partialScan[SIZE_CDF];
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < SIZE_CDF && i < 256) {
partialScan[i] = (float) histo[i] / (float) (imageWidth * imageHeight);
}
__syncthreads();
for (unsigned int stride = 1; stride <= SIZE_HISTO; stride *= 2) {
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index < SIZE_CDF && index < length)
partialScan[index] += partialScan[index - stride];
__syncthreads();
}
for (unsigned int stride = SIZE_HISTO / 2; stride > 0; stride /= 2) {
__syncthreads();
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index + stride < SIZE_CDF && index + stride < length) {
partialScan[index + stride] += partialScan[index];
}
}
__syncthreads();
if (i < SIZE_CDF && i < 256) {
cdf[i] += partialScan[threadIdx.x];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcCDF(float *cdf, unsigned int *histo, int imageWidth, int imageHeight, int length) {
__shared__ float partialScan[SIZE_CDF];
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < SIZE_CDF && i < 256) {
partialScan[i] = (float) histo[i] / (float) (imageWidth * imageHeight);
}
__syncthreads();
for (unsigned int stride = 1; stride <= SIZE_HISTO; stride *= 2) {
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index < SIZE_CDF && index < length)
partialScan[index] += partialScan[index - stride];
__syncthreads();
}
for (unsigned int stride = SIZE_HISTO / 2; stride > 0; stride /= 2) {
__syncthreads();
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index + stride < SIZE_CDF && index + stride < length) {
partialScan[index + stride] += partialScan[index];
}
}
__syncthreads();
if (i < SIZE_CDF && i < 256) {
cdf[i] += partialScan[threadIdx.x];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcCDF(float *cdf, unsigned int *histo, int imageWidth, int imageHeight, int length) {
__shared__ float partialScan[SIZE_CDF];
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < SIZE_CDF && i < 256) {
partialScan[i] = (float) histo[i] / (float) (imageWidth * imageHeight);
}
__syncthreads();
for (unsigned int stride = 1; stride <= SIZE_HISTO; stride *= 2) {
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index < SIZE_CDF && index < length)
partialScan[index] += partialScan[index - stride];
__syncthreads();
}
for (unsigned int stride = SIZE_HISTO / 2; stride > 0; stride /= 2) {
__syncthreads();
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index + stride < SIZE_CDF && index + stride < length) {
partialScan[index + stride] += partialScan[index];
}
}
__syncthreads();
if (i < SIZE_CDF && i < 256) {
cdf[i] += partialScan[threadIdx.x];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7calcCDFPfPjiii
.globl _Z7calcCDFPfPjiii
.p2align 8
.type _Z7calcCDFPfPjiii,@function
_Z7calcCDFPfPjiii:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_i32_e64 s2, 0x100, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_mul_i32 s4, s7, s6
global_load_b32 v3, v[3:4], off
v_cvt_f32_i32_e32 v4, s4
s_waitcnt vmcnt(0)
v_cvt_f32_u32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v5, null, v4, v4, v3
v_div_scale_f32 v8, vcc_lo, v3, v4, v3
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_mul_f32_e32 v7, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v7, v8
v_fmac_f32_e32 v7, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v7, v8
v_div_fmas_f32 v5, v5, v6, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v3, v5, v4, v3
v_lshlrev_b32_e32 v4, 2, v1
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s4, s[0:1], 0x18
v_add_nc_u32_e32 v3, 1, v0
s_mov_b32 s5, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_lshl_b32 s3, s5, 1
s_cmpk_gt_u32 s5, 0x80
s_mov_b32 s5, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
v_mul_lo_u32 v5, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, v5, 1, -1
v_cmp_gt_u32_e32 vcc_lo, 0x101, v5
v_cmp_gt_u32_e64 s3, s4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, vcc_lo, s3
s_and_saveexec_b32 s3, s6
s_cbranch_execz .LBB0_3
v_subrev_nc_u32_e32 v5, s5, v4
v_lshlrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v5, v5
ds_load_b32 v6, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v6
ds_store_b32 v4, v5
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_lshl_add_u32 v3, v0, 1, 2
s_min_u32 s3, s4, 0x200
s_movk_i32 s4, 0x80
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s5
s_lshr_b32 s5, s4, 1
s_cmp_lt_u32 s4, 2
s_mov_b32 s4, s5
s_cbranch_scc1 .LBB0_10
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v5, v3, s4, -1
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v4, s4, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v4
s_cbranch_execz .LBB0_7
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v4, 2, v4
ds_load_b32 v5, v5
ds_load_b32 v6, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v6
ds_store_b32 v4, v5
s_branch .LBB0_7
.LBB0_10:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v3
global_store_b32 v[1:2], v0, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7calcCDFPfPjiii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7calcCDFPfPjiii, .Lfunc_end0-_Z7calcCDFPfPjiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7calcCDFPfPjiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7calcCDFPfPjiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcCDF(float *cdf, unsigned int *histo, int imageWidth, int imageHeight, int length) {
__shared__ float partialScan[SIZE_CDF];
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < SIZE_CDF && i < 256) {
partialScan[i] = (float) histo[i] / (float) (imageWidth * imageHeight);
}
__syncthreads();
for (unsigned int stride = 1; stride <= SIZE_HISTO; stride *= 2) {
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index < SIZE_CDF && index < length)
partialScan[index] += partialScan[index - stride];
__syncthreads();
}
for (unsigned int stride = SIZE_HISTO / 2; stride > 0; stride /= 2) {
__syncthreads();
unsigned int index = (threadIdx.x + 1) * stride * 2 - 1;
if (index + stride < SIZE_CDF && index + stride < length) {
partialScan[index + stride] += partialScan[index];
}
}
__syncthreads();
if (i < SIZE_CDF && i < 256) {
cdf[i] += partialScan[threadIdx.x];
}
} | .text
.file "calcCDF.hip"
.globl _Z22__device_stub__calcCDFPfPjiii # -- Begin function _Z22__device_stub__calcCDFPfPjiii
.p2align 4, 0x90
.type _Z22__device_stub__calcCDFPfPjiii,@function
_Z22__device_stub__calcCDFPfPjiii: # @_Z22__device_stub__calcCDFPfPjiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7calcCDFPfPjiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__calcCDFPfPjiii, .Lfunc_end0-_Z22__device_stub__calcCDFPfPjiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7calcCDFPfPjiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7calcCDFPfPjiii,@object # @_Z7calcCDFPfPjiii
.section .rodata,"a",@progbits
.globl _Z7calcCDFPfPjiii
.p2align 3, 0x0
_Z7calcCDFPfPjiii:
.quad _Z22__device_stub__calcCDFPfPjiii
.size _Z7calcCDFPfPjiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7calcCDFPfPjiii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__calcCDFPfPjiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7calcCDFPfPjiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00053062_00000000-6_calcCDF.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii
.type _Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii, @function
_Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7calcCDFPfPjiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii, .-_Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii
.globl _Z7calcCDFPfPjiii
.type _Z7calcCDFPfPjiii, @function
_Z7calcCDFPfPjiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7calcCDFPfPjiiiPfPjiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7calcCDFPfPjiii, .-_Z7calcCDFPfPjiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7calcCDFPfPjiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7calcCDFPfPjiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calcCDF.hip"
.globl _Z22__device_stub__calcCDFPfPjiii # -- Begin function _Z22__device_stub__calcCDFPfPjiii
.p2align 4, 0x90
.type _Z22__device_stub__calcCDFPfPjiii,@function
_Z22__device_stub__calcCDFPfPjiii: # @_Z22__device_stub__calcCDFPfPjiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7calcCDFPfPjiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__calcCDFPfPjiii, .Lfunc_end0-_Z22__device_stub__calcCDFPfPjiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7calcCDFPfPjiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7calcCDFPfPjiii,@object # @_Z7calcCDFPfPjiii
.section .rodata,"a",@progbits
.globl _Z7calcCDFPfPjiii
.p2align 3, 0x0
_Z7calcCDFPfPjiii:
.quad _Z22__device_stub__calcCDFPfPjiii
.size _Z7calcCDFPfPjiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7calcCDFPfPjiii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__calcCDFPfPjiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7calcCDFPfPjiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <curand_kernel.h>
const int THREADS = 128; //threads per block
const int trial_number = 1024; //trial numbers per thread
const int BLOCKS = 16; //blocks per grid
const float PI = 3.1415926535;
__global__ void pi_estimation(float *pi, curandState *states)
{
unsigned int threadID = threadIdx.x + blockDim.x * blockIdx.x;
int count = 0;
float x,y,z;
curand_init(0, threadID, 1, &states[threadID]); //(seed, sequence number, offset, curandState)
for(int i = 0; i < trial_number; i++)
{
x = curand_uniform(&states[threadID]);//return sequence number of pseudorandom uniformly distributed.
y = curand_uniform(&states[threadID]);
z = (x*x + y*y);
if(z <= 1.0f) //if x,y in unit circle
{
count += 1;
}
}
pi[threadID] = 4.0f * count/(float)trial_number; //estimate PI value 4*count/number of trial
}
int main(int argc, char *argv[])
{
float host[THREADS * BLOCKS];
float *device;
curandState *deviceStates;
cudaMalloc((void **)&device, THREADS * BLOCKS * sizeof(float));
cudaMalloc((void **)&deviceStates, THREADS * BLOCKS * sizeof(curandState));
pi_estimation<<<BLOCKS,THREADS>>>(device,deviceStates); //call kernel
cudaMemcpy(host, device, THREADS * BLOCKS * sizeof(float), cudaMemcpyDeviceToHost); //copy estimated pi value from device to host
float pi = 0.0;
for(int i = 0; i < THREADS * BLOCKS; i++)
{
pi += host[i];
}
pi /= (THREADS * BLOCKS); //get average of each PI value from each thread.
printf("Monte Carlo PI estimation %d times\n", THREADS * BLOCKS * trial_number);
printf("PI estimation: %.10f\n",pi);
printf("Error: %.10\n\n",pi-PI);
cudaFree(device);
cudaFree(deviceStates);
return 0;
} | .file "tmpxft_0007b8dc_00000000-6_lab7.2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW
.type _Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW, @function
_Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13pi_estimationPfP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW, .-_Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW
.globl _Z13pi_estimationPfP17curandStateXORWOW
.type _Z13pi_estimationPfP17curandStateXORWOW, @function
_Z13pi_estimationPfP17curandStateXORWOW:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z13pi_estimationPfP17curandStateXORWOW, .-_Z13pi_estimationPfP17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Monte Carlo PI estimation %d times\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "PI estimation: %.10f\n"
.LC5:
.string "Error: %.10\n\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $4096, %rsp
.cfi_def_cfa_offset 4112
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8208
orq $0, (%rsp)
subq $80, %rsp
.cfi_def_cfa_offset 8288
movq %fs:40, %rax
movq %rax, 8264(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $98304, %esi
call cudaMalloc@PLT
movl $128, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 8256(%rsp), %rdx
pxor %xmm0, %xmm0
.L13:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L13
mulss .LC1(%rip), %xmm0
movss %xmm0, 12(%rsp)
movl $2097152, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
subss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 8264(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $8272, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC6:
.string "_Z13pi_estimationPfP17curandStateXORWOW"
.section .rodata.str1.1
.LC7:
.string "precalc_xorwow_matrix"
.LC8:
.string "precalc_xorwow_offset_matrix"
.LC9:
.string "mrg32k3aM1"
.LC10:
.string "mrg32k3aM2"
.LC11:
.string "mrg32k3aM1SubSeq"
.LC12:
.string "mrg32k3aM2SubSeq"
.LC13:
.string "mrg32k3aM1Seq"
.LC14:
.string "mrg32k3aM2Seq"
.LC15:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13pi_estimationPfP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 973078528
.align 4
.LC4:
.long 1078530011
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <curand_kernel.h>
const int THREADS = 128; //threads per block
const int trial_number = 1024; //trial numbers per thread
const int BLOCKS = 16; //blocks per grid
const float PI = 3.1415926535;
__global__ void pi_estimation(float *pi, curandState *states)
{
unsigned int threadID = threadIdx.x + blockDim.x * blockIdx.x;
int count = 0;
float x,y,z;
curand_init(0, threadID, 1, &states[threadID]); //(seed, sequence number, offset, curandState)
for(int i = 0; i < trial_number; i++)
{
x = curand_uniform(&states[threadID]);//return sequence number of pseudorandom uniformly distributed.
y = curand_uniform(&states[threadID]);
z = (x*x + y*y);
if(z <= 1.0f) //if x,y in unit circle
{
count += 1;
}
}
pi[threadID] = 4.0f * count/(float)trial_number; //estimate PI value 4*count/number of trial
}
int main(int argc, char *argv[])
{
float host[THREADS * BLOCKS];
float *device;
curandState *deviceStates;
cudaMalloc((void **)&device, THREADS * BLOCKS * sizeof(float));
cudaMalloc((void **)&deviceStates, THREADS * BLOCKS * sizeof(curandState));
pi_estimation<<<BLOCKS,THREADS>>>(device,deviceStates); //call kernel
cudaMemcpy(host, device, THREADS * BLOCKS * sizeof(float), cudaMemcpyDeviceToHost); //copy estimated pi value from device to host
float pi = 0.0;
for(int i = 0; i < THREADS * BLOCKS; i++)
{
pi += host[i];
}
pi /= (THREADS * BLOCKS); //get average of each PI value from each thread.
printf("Monte Carlo PI estimation %d times\n", THREADS * BLOCKS * trial_number);
printf("PI estimation: %.10f\n",pi);
printf("Error: %.10\n\n",pi-PI);
cudaFree(device);
cudaFree(deviceStates);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
const int THREADS = 128; //threads per block
const int trial_number = 1024; //trial numbers per thread
const int BLOCKS = 16; //blocks per grid
const float PI = 3.1415926535;
__global__ void pi_estimation(float *pi, hiprandState *states)
{
unsigned int threadID = threadIdx.x + blockDim.x * blockIdx.x;
int count = 0;
float x,y,z;
hiprand_init(0, threadID, 1, &states[threadID]); //(seed, sequence number, offset, curandState)
for(int i = 0; i < trial_number; i++)
{
x = hiprand_uniform(&states[threadID]);//return sequence number of pseudorandom uniformly distributed.
y = hiprand_uniform(&states[threadID]);
z = (x*x + y*y);
if(z <= 1.0f) //if x,y in unit circle
{
count += 1;
}
}
pi[threadID] = 4.0f * count/(float)trial_number; //estimate PI value 4*count/number of trial
}
int main(int argc, char *argv[])
{
float host[THREADS * BLOCKS];
float *device;
hiprandState *deviceStates;
hipMalloc((void **)&device, THREADS * BLOCKS * sizeof(float));
hipMalloc((void **)&deviceStates, THREADS * BLOCKS * sizeof(hiprandState));
pi_estimation<<<BLOCKS,THREADS>>>(device,deviceStates); //call kernel
hipMemcpy(host, device, THREADS * BLOCKS * sizeof(float), hipMemcpyDeviceToHost); //copy estimated pi value from device to host
float pi = 0.0;
for(int i = 0; i < THREADS * BLOCKS; i++)
{
pi += host[i];
}
pi /= (THREADS * BLOCKS); //get average of each PI value from each thread.
printf("Monte Carlo PI estimation %d times\n", THREADS * BLOCKS * trial_number);
printf("PI estimation: %.10f\n",pi);
printf("Error: %.10\n\n",pi-PI);
hipFree(device);
hipFree(deviceStates);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
const int THREADS = 128; //threads per block
const int trial_number = 1024; //trial numbers per thread
const int BLOCKS = 16; //blocks per grid
const float PI = 3.1415926535;
__global__ void pi_estimation(float *pi, hiprandState *states)
{
unsigned int threadID = threadIdx.x + blockDim.x * blockIdx.x;
int count = 0;
float x,y,z;
hiprand_init(0, threadID, 1, &states[threadID]); //(seed, sequence number, offset, curandState)
for(int i = 0; i < trial_number; i++)
{
x = hiprand_uniform(&states[threadID]);//return sequence number of pseudorandom uniformly distributed.
y = hiprand_uniform(&states[threadID]);
z = (x*x + y*y);
if(z <= 1.0f) //if x,y in unit circle
{
count += 1;
}
}
pi[threadID] = 4.0f * count/(float)trial_number; //estimate PI value 4*count/number of trial
}
int main(int argc, char *argv[])
{
float host[THREADS * BLOCKS];
float *device;
hiprandState *deviceStates;
hipMalloc((void **)&device, THREADS * BLOCKS * sizeof(float));
hipMalloc((void **)&deviceStates, THREADS * BLOCKS * sizeof(hiprandState));
pi_estimation<<<BLOCKS,THREADS>>>(device,deviceStates); //call kernel
hipMemcpy(host, device, THREADS * BLOCKS * sizeof(float), hipMemcpyDeviceToHost); //copy estimated pi value from device to host
float pi = 0.0;
for(int i = 0; i < THREADS * BLOCKS; i++)
{
pi += host[i];
}
pi /= (THREADS * BLOCKS); //get average of each PI value from each thread.
printf("Monte Carlo PI estimation %d times\n", THREADS * BLOCKS * trial_number);
printf("PI estimation: %.10f\n",pi);
printf("Error: %.10\n\n",pi-PI);
hipFree(device);
hipFree(deviceStates);
return 0;
} | .text
.file "lab7.2.hip"
.globl _Z28__device_stub__pi_estimationPfP12hiprandState # -- Begin function _Z28__device_stub__pi_estimationPfP12hiprandState
.p2align 4, 0x90
.type _Z28__device_stub__pi_estimationPfP12hiprandState,@function
_Z28__device_stub__pi_estimationPfP12hiprandState: # @_Z28__device_stub__pi_estimationPfP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13pi_estimationPfP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__pi_estimationPfP12hiprandState, .Lfunc_end0-_Z28__device_stub__pi_estimationPfP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3a000000 # float 4.8828125E-4
.LCPI1_1:
.long 0xc0490fdb # float -3.14159274
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $8296, %rsp # imm = 0x2068
.cfi_def_cfa_offset 8304
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $98304, %esi # imm = 0x18000
callq hipMalloc
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 112(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13pi_estimationPfP12hiprandState, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addss 96(%rsp,%rax,4), %xmm0
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB1_3
# %bb.4:
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
movl $.L.str, %edi
movl $2097152, %esi # imm = 0x200000
xorl %eax, %eax
callq printf
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $8296, %rsp # imm = 0x2068
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13pi_estimationPfP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13pi_estimationPfP12hiprandState,@object # @_Z13pi_estimationPfP12hiprandState
.section .rodata,"a",@progbits
.globl _Z13pi_estimationPfP12hiprandState
.p2align 3, 0x0
_Z13pi_estimationPfP12hiprandState:
.quad _Z28__device_stub__pi_estimationPfP12hiprandState
.size _Z13pi_estimationPfP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Monte Carlo PI estimation %d times\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "PI estimation: %.10f\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error: %.10\n\n"
.size .L.str.2, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13pi_estimationPfP12hiprandState"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__pi_estimationPfP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13pi_estimationPfP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007b8dc_00000000-6_lab7.2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW
.type _Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW, @function
_Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13pi_estimationPfP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW, .-_Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW
.globl _Z13pi_estimationPfP17curandStateXORWOW
.type _Z13pi_estimationPfP17curandStateXORWOW, @function
_Z13pi_estimationPfP17curandStateXORWOW:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z13pi_estimationPfP17curandStateXORWOW, .-_Z13pi_estimationPfP17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Monte Carlo PI estimation %d times\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "PI estimation: %.10f\n"
.LC5:
.string "Error: %.10\n\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $4096, %rsp
.cfi_def_cfa_offset 4112
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8208
orq $0, (%rsp)
subq $80, %rsp
.cfi_def_cfa_offset 8288
movq %fs:40, %rax
movq %rax, 8264(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $98304, %esi
call cudaMalloc@PLT
movl $128, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $16, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 8256(%rsp), %rdx
pxor %xmm0, %xmm0
.L13:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L13
mulss .LC1(%rip), %xmm0
movss %xmm0, 12(%rsp)
movl $2097152, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
subss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 8264(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $8272, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z53__device_stub__Z13pi_estimationPfP17curandStateXORWOWPfP17curandStateXORWOW
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC6:
.string "_Z13pi_estimationPfP17curandStateXORWOW"
.section .rodata.str1.1
.LC7:
.string "precalc_xorwow_matrix"
.LC8:
.string "precalc_xorwow_offset_matrix"
.LC9:
.string "mrg32k3aM1"
.LC10:
.string "mrg32k3aM2"
.LC11:
.string "mrg32k3aM1SubSeq"
.LC12:
.string "mrg32k3aM2SubSeq"
.LC13:
.string "mrg32k3aM1Seq"
.LC14:
.string "mrg32k3aM2Seq"
.LC15:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13pi_estimationPfP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 973078528
.align 4
.LC4:
.long 1078530011
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab7.2.hip"
.globl _Z28__device_stub__pi_estimationPfP12hiprandState # -- Begin function _Z28__device_stub__pi_estimationPfP12hiprandState
.p2align 4, 0x90
.type _Z28__device_stub__pi_estimationPfP12hiprandState,@function
_Z28__device_stub__pi_estimationPfP12hiprandState: # @_Z28__device_stub__pi_estimationPfP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13pi_estimationPfP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__pi_estimationPfP12hiprandState, .Lfunc_end0-_Z28__device_stub__pi_estimationPfP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3a000000 # float 4.8828125E-4
.LCPI1_1:
.long 0xc0490fdb # float -3.14159274
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $8296, %rsp # imm = 0x2068
.cfi_def_cfa_offset 8304
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $98304, %esi # imm = 0x18000
callq hipMalloc
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 112(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13pi_estimationPfP12hiprandState, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addss 96(%rsp,%rax,4), %xmm0
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB1_3
# %bb.4:
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
movl $.L.str, %edi
movl $2097152, %esi # imm = 0x200000
xorl %eax, %eax
callq printf
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $8296, %rsp # imm = 0x2068
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13pi_estimationPfP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13pi_estimationPfP12hiprandState,@object # @_Z13pi_estimationPfP12hiprandState
.section .rodata,"a",@progbits
.globl _Z13pi_estimationPfP12hiprandState
.p2align 3, 0x0
_Z13pi_estimationPfP12hiprandState:
.quad _Z28__device_stub__pi_estimationPfP12hiprandState
.size _Z13pi_estimationPfP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Monte Carlo PI estimation %d times\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "PI estimation: %.10f\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error: %.10\n\n"
.size .L.str.2, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13pi_estimationPfP12hiprandState"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__pi_estimationPfP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13pi_estimationPfP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Benchmark that calculate the integral of F(x) over the interval [A,B] */
#include <stdio.h>
#define NUM_INTERVALS 1000000
#define F(x) (x)*(x)
#define A 0
#define B 10
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float arr[1000000],float delta)
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_x_id)
if (thread_x_id <= 1000000) {
float x = ((float )0) + ((float )(1 * thread_x_id + -1)) * delta;
arr[1 * thread_x_id + -1] = x * x + x * delta * (x * delta);
}
}
int main()
{
int i_nom_1;
int i;
/* Array to hold answer */
float arr[1000000];
/* Step size */
float delta = ((float )10) / ((float )1000000);
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_arr;
_narray_arr *d_arr;
cudaMalloc((void **) &d_arr, sizeof(float ) * 1000000);
cudaMemcpy(d_arr, arr, sizeof(float ) * 1000000, cudaMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (1000000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (1 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_arr, delta);
cudaMemcpy(arr, d_arr, sizeof(float ) * 1000000, cudaMemcpyDeviceToHost);
}
/* Add up the heights of the rectangles */
double sum = 0;
for (i_nom_1 = 1; i_nom_1 <= 1000000; i_nom_1 += 1) {
sum += arr[1 * i_nom_1 + -1];
}
/* Multiply by width of rectangle */
sum *= delta / 2.0;
/* Report result */
printf("Result: %f\n",sum);
return 0;
} | code for sm_80
Function : _Z14_auto_kernel_0Pff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xf4240, PT ; /* 0x000f42400000780c */
/* 0x000fc80003f04270 */
/*0050*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e240000201400 */
/*00b0*/ FFMA R4, R2, c[0x0][0x168], RZ ; /* 0x00005a0002047a23 */
/* 0x001fc800000000ff */
/*00c0*/ FMUL R2, R4, c[0x0][0x168] ; /* 0x00005a0004027a20 */
/* 0x000fc80000400000 */
/*00d0*/ FMUL R5, R2, R2 ; /* 0x0000000202057220 */
/* 0x000fe40000400000 */
/*00e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0203 */
/*00f0*/ FFMA R5, R4, R4, R5 ; /* 0x0000000404057223 */
/* 0x000fca0000000005 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Benchmark that calculate the integral of F(x) over the interval [A,B] */
#include <stdio.h>
#define NUM_INTERVALS 1000000
#define F(x) (x)*(x)
#define A 0
#define B 10
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float arr[1000000],float delta)
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_x_id)
if (thread_x_id <= 1000000) {
float x = ((float )0) + ((float )(1 * thread_x_id + -1)) * delta;
arr[1 * thread_x_id + -1] = x * x + x * delta * (x * delta);
}
}
int main()
{
int i_nom_1;
int i;
/* Array to hold answer */
float arr[1000000];
/* Step size */
float delta = ((float )10) / ((float )1000000);
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_arr;
_narray_arr *d_arr;
cudaMalloc((void **) &d_arr, sizeof(float ) * 1000000);
cudaMemcpy(d_arr, arr, sizeof(float ) * 1000000, cudaMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (1000000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (1 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_arr, delta);
cudaMemcpy(arr, d_arr, sizeof(float ) * 1000000, cudaMemcpyDeviceToHost);
}
/* Add up the heights of the rectangles */
double sum = 0;
for (i_nom_1 = 1; i_nom_1 <= 1000000; i_nom_1 += 1) {
sum += arr[1 * i_nom_1 + -1];
}
/* Multiply by width of rectangle */
sum *= delta / 2.0;
/* Report result */
printf("Result: %f\n",sum);
return 0;
} | .file "tmpxft_000a82fe_00000000-6_numerical_integration.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z14_auto_kernel_0PffPff
.type _Z35__device_stub__Z14_auto_kernel_0PffPff, @function
_Z35__device_stub__Z14_auto_kernel_0PffPff:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14_auto_kernel_0Pff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z14_auto_kernel_0PffPff, .-_Z35__device_stub__Z14_auto_kernel_0PffPff
.globl _Z14_auto_kernel_0Pff
.type _Z14_auto_kernel_0Pff, @function
_Z14_auto_kernel_0Pff:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14_auto_kernel_0PffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14_auto_kernel_0Pff, .-_Z14_auto_kernel_0Pff
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Result: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -3997696(%rsp), %r11
.cfi_def_cfa 11, 3997712
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2352, %rsp
.cfi_def_cfa_offset 4000064
movq %fs:40, %rax
movq %rax, 4000040(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $4000000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $7813, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $4000000, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 4000032(%rsp), %rdx
pxor %xmm0, %xmm0
.L13:
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
addsd %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L13
mulsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 4000040(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $4000048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movss .LC1(%rip), %xmm0
movq (%rsp), %rdi
call _Z35__device_stub__Z14_auto_kernel_0PffPff
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14_auto_kernel_0Pff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14_auto_kernel_0Pff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 925353388
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -2147483648
.long 1054144693
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Benchmark that calculate the integral of F(x) over the interval [A,B] */
#include <stdio.h>
#define NUM_INTERVALS 1000000
#define F(x) (x)*(x)
#define A 0
#define B 10
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float arr[1000000],float delta)
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_x_id)
if (thread_x_id <= 1000000) {
float x = ((float )0) + ((float )(1 * thread_x_id + -1)) * delta;
arr[1 * thread_x_id + -1] = x * x + x * delta * (x * delta);
}
}
int main()
{
int i_nom_1;
int i;
/* Array to hold answer */
float arr[1000000];
/* Step size */
float delta = ((float )10) / ((float )1000000);
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_arr;
_narray_arr *d_arr;
cudaMalloc((void **) &d_arr, sizeof(float ) * 1000000);
cudaMemcpy(d_arr, arr, sizeof(float ) * 1000000, cudaMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (1000000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (1 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_arr, delta);
cudaMemcpy(arr, d_arr, sizeof(float ) * 1000000, cudaMemcpyDeviceToHost);
}
/* Add up the heights of the rectangles */
double sum = 0;
for (i_nom_1 = 1; i_nom_1 <= 1000000; i_nom_1 += 1) {
sum += arr[1 * i_nom_1 + -1];
}
/* Multiply by width of rectangle */
sum *= delta / 2.0;
/* Report result */
printf("Result: %f\n",sum);
return 0;
} | /* Benchmark that calculate the integral of F(x) over the interval [A,B] */
#include <hip/hip_runtime.h>
#include <stdio.h>
#define NUM_INTERVALS 1000000
#define F(x) (x)*(x)
#define A 0
#define B 10
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float arr[1000000],float delta)
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_x_id)
if (thread_x_id <= 1000000) {
float x = ((float )0) + ((float )(1 * thread_x_id + -1)) * delta;
arr[1 * thread_x_id + -1] = x * x + x * delta * (x * delta);
}
}
int main()
{
int i_nom_1;
int i;
/* Array to hold answer */
float arr[1000000];
/* Step size */
float delta = ((float )10) / ((float )1000000);
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_arr;
_narray_arr *d_arr;
hipMalloc((void **) &d_arr, sizeof(float ) * 1000000);
hipMemcpy(d_arr, arr, sizeof(float ) * 1000000, hipMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (1000000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (1 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_arr, delta);
hipMemcpy(arr, d_arr, sizeof(float ) * 1000000, hipMemcpyDeviceToHost);
}
/* Add up the heights of the rectangles */
double sum = 0;
for (i_nom_1 = 1; i_nom_1 <= 1000000; i_nom_1 += 1) {
sum += arr[1 * i_nom_1 + -1];
}
/* Multiply by width of rectangle */
sum *= delta / 2.0;
/* Report result */
printf("Result: %f\n",sum);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Benchmark that calculate the integral of F(x) over the interval [A,B] */
#include <hip/hip_runtime.h>
#include <stdio.h>
#define NUM_INTERVALS 1000000
#define F(x) (x)*(x)
#define A 0
#define B 10
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float arr[1000000],float delta)
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_x_id)
if (thread_x_id <= 1000000) {
float x = ((float )0) + ((float )(1 * thread_x_id + -1)) * delta;
arr[1 * thread_x_id + -1] = x * x + x * delta * (x * delta);
}
}
int main()
{
int i_nom_1;
int i;
/* Array to hold answer */
float arr[1000000];
/* Step size */
float delta = ((float )10) / ((float )1000000);
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_arr;
_narray_arr *d_arr;
hipMalloc((void **) &d_arr, sizeof(float ) * 1000000);
hipMemcpy(d_arr, arr, sizeof(float ) * 1000000, hipMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (1000000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (1 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_arr, delta);
hipMemcpy(arr, d_arr, sizeof(float ) * 1000000, hipMemcpyDeviceToHost);
}
/* Add up the heights of the rectangles */
double sum = 0;
for (i_nom_1 = 1; i_nom_1 <= 1000000; i_nom_1 += 1) {
sum += arr[1 * i_nom_1 + -1];
}
/* Multiply by width of rectangle */
sum *= delta / 2.0;
/* Report result */
printf("Result: %f\n",sum);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14_auto_kernel_0Pff
.globl _Z14_auto_kernel_0Pff
.p2align 8
.type _Z14_auto_kernel_0Pff,@function
_Z14_auto_kernel_0Pff:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, 0xf4241, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[0:1], 0x8
v_add_nc_u32_e32 v0, -1, v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v0
s_waitcnt lgkmcnt(0)
v_fma_f32 v2, v1, s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, s2, v2
v_ashrrev_i32_e32 v1, 31, v0
v_mul_f32_e32 v3, v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_fmac_f32_e32 v3, v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14_auto_kernel_0Pff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14_auto_kernel_0Pff, .Lfunc_end0-_Z14_auto_kernel_0Pff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14_auto_kernel_0Pff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14_auto_kernel_0Pff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Benchmark that calculate the integral of F(x) over the interval [A,B] */
#include <hip/hip_runtime.h>
#include <stdio.h>
#define NUM_INTERVALS 1000000
#define F(x) (x)*(x)
#define A 0
#define B 10
#define CUDA_BLOCK_X 128
#define CUDA_BLOCK_Y 1
#define CUDA_BLOCK_Z 1
__global__ void _auto_kernel_0(float arr[1000000],float delta)
{
int thread_x_id;thread_x_id = blockIdx.x * blockDim.x + threadIdx.x;
if (thread_x_id)
if (thread_x_id <= 1000000) {
float x = ((float )0) + ((float )(1 * thread_x_id + -1)) * delta;
arr[1 * thread_x_id + -1] = x * x + x * delta * (x * delta);
}
}
int main()
{
int i_nom_1;
int i;
/* Array to hold answer */
float arr[1000000];
/* Step size */
float delta = ((float )10) / ((float )1000000);
{
/* Auto-generated code for call to _auto_kernel_0 */
typedef float _narray_arr;
_narray_arr *d_arr;
hipMalloc((void **) &d_arr, sizeof(float ) * 1000000);
hipMemcpy(d_arr, arr, sizeof(float ) * 1000000, hipMemcpyHostToDevice);
int CUDA_GRID_X;
CUDA_GRID_X = (1000000 + CUDA_BLOCK_X - 1)/CUDA_BLOCK_X;
int CUDA_GRID_Y;
CUDA_GRID_Y = (1 + CUDA_BLOCK_Y - 1)/CUDA_BLOCK_Y;
int CUDA_GRID_Z;
CUDA_GRID_Z = (1 + CUDA_BLOCK_Z - 1)/CUDA_BLOCK_Z;
const dim3 CUDA_blockSize(CUDA_BLOCK_X, CUDA_BLOCK_Y, CUDA_BLOCK_Z);
const dim3 CUDA_gridSize(CUDA_GRID_X, CUDA_GRID_Y, CUDA_GRID_Z);
_auto_kernel_0<<<CUDA_gridSize,CUDA_blockSize>>>(d_arr, delta);
hipMemcpy(arr, d_arr, sizeof(float ) * 1000000, hipMemcpyDeviceToHost);
}
/* Add up the heights of the rectangles */
double sum = 0;
for (i_nom_1 = 1; i_nom_1 <= 1000000; i_nom_1 += 1) {
sum += arr[1 * i_nom_1 + -1];
}
/* Multiply by width of rectangle */
sum *= delta / 2.0;
/* Report result */
printf("Result: %f\n",sum);
return 0;
} | .text
.file "numerical_integration.hip"
.globl _Z29__device_stub___auto_kernel_0Pff # -- Begin function _Z29__device_stub___auto_kernel_0Pff
.p2align 4, 0x90
.type _Z29__device_stub___auto_kernel_0Pff,@function
_Z29__device_stub___auto_kernel_0Pff: # @_Z29__device_stub___auto_kernel_0Pff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14_auto_kernel_0Pff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub___auto_kernel_0Pff, .Lfunc_end0-_Z29__device_stub___auto_kernel_0Pff
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ed4f8b580000000 # double 4.9999998736893758E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $4000104, %rsp # imm = 0x3D0968
.cfi_def_cfa_offset 4000112
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq 8(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $1, %ecx
callq hipMemcpy
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 7685(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $925353388, 20(%rsp) # imm = 0x3727C5AC
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14_auto_kernel_0Pff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movl $2, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 96(%rsp,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB1_3
# %bb.4:
mulsd .LCPI1_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $4000104, %rsp # imm = 0x3D0968
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14_auto_kernel_0Pff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14_auto_kernel_0Pff,@object # @_Z14_auto_kernel_0Pff
.section .rodata,"a",@progbits
.globl _Z14_auto_kernel_0Pff
.p2align 3, 0x0
_Z14_auto_kernel_0Pff:
.quad _Z29__device_stub___auto_kernel_0Pff
.size _Z14_auto_kernel_0Pff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result: %f\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14_auto_kernel_0Pff"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub___auto_kernel_0Pff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14_auto_kernel_0Pff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14_auto_kernel_0Pff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xf4240, PT ; /* 0x000f42400000780c */
/* 0x000fc80003f04270 */
/*0050*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000702670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x000e240000201400 */
/*00b0*/ FFMA R4, R2, c[0x0][0x168], RZ ; /* 0x00005a0002047a23 */
/* 0x001fc800000000ff */
/*00c0*/ FMUL R2, R4, c[0x0][0x168] ; /* 0x00005a0004027a20 */
/* 0x000fc80000400000 */
/*00d0*/ FMUL R5, R2, R2 ; /* 0x0000000202057220 */
/* 0x000fe40000400000 */
/*00e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0203 */
/*00f0*/ FFMA R5, R4, R4, R5 ; /* 0x0000000404057223 */
/* 0x000fca0000000005 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14_auto_kernel_0Pff
.globl _Z14_auto_kernel_0Pff
.p2align 8
.type _Z14_auto_kernel_0Pff,@function
_Z14_auto_kernel_0Pff:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, 0xf4241, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[0:1], 0x8
v_add_nc_u32_e32 v0, -1, v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v0
s_waitcnt lgkmcnt(0)
v_fma_f32 v2, v1, s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, s2, v2
v_ashrrev_i32_e32 v1, 31, v0
v_mul_f32_e32 v3, v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_fmac_f32_e32 v3, v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14_auto_kernel_0Pff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14_auto_kernel_0Pff, .Lfunc_end0-_Z14_auto_kernel_0Pff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14_auto_kernel_0Pff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14_auto_kernel_0Pff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a82fe_00000000-6_numerical_integration.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z14_auto_kernel_0PffPff
.type _Z35__device_stub__Z14_auto_kernel_0PffPff, @function
_Z35__device_stub__Z14_auto_kernel_0PffPff:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14_auto_kernel_0Pff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z14_auto_kernel_0PffPff, .-_Z35__device_stub__Z14_auto_kernel_0PffPff
.globl _Z14_auto_kernel_0Pff
.type _Z14_auto_kernel_0Pff, @function
_Z14_auto_kernel_0Pff:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14_auto_kernel_0PffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14_auto_kernel_0Pff, .-_Z14_auto_kernel_0Pff
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Result: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -3997696(%rsp), %r11
.cfi_def_cfa 11, 3997712
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2352, %rsp
.cfi_def_cfa_offset 4000064
movq %fs:40, %rax
movq %rax, 4000040(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $4000000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $7813, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $4000000, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 4000032(%rsp), %rdx
pxor %xmm0, %xmm0
.L13:
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
addsd %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L13
mulsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 4000040(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $4000048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movss .LC1(%rip), %xmm0
movq (%rsp), %rdi
call _Z35__device_stub__Z14_auto_kernel_0PffPff
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14_auto_kernel_0Pff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14_auto_kernel_0Pff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 925353388
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -2147483648
.long 1054144693
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "numerical_integration.hip"
.globl _Z29__device_stub___auto_kernel_0Pff # -- Begin function _Z29__device_stub___auto_kernel_0Pff
.p2align 4, 0x90
.type _Z29__device_stub___auto_kernel_0Pff,@function
_Z29__device_stub___auto_kernel_0Pff: # @_Z29__device_stub___auto_kernel_0Pff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14_auto_kernel_0Pff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub___auto_kernel_0Pff, .Lfunc_end0-_Z29__device_stub___auto_kernel_0Pff
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ed4f8b580000000 # double 4.9999998736893758E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $4000104, %rsp # imm = 0x3D0968
.cfi_def_cfa_offset 4000112
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq 8(%rsp), %rdi
leaq 96(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movl $1, %ecx
callq hipMemcpy
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 7685(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $925353388, 20(%rsp) # imm = 0x3727C5AC
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14_auto_kernel_0Pff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movl $2, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 96(%rsp,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB1_3
# %bb.4:
mulsd .LCPI1_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $4000104, %rsp # imm = 0x3D0968
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14_auto_kernel_0Pff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14_auto_kernel_0Pff,@object # @_Z14_auto_kernel_0Pff
.section .rodata,"a",@progbits
.globl _Z14_auto_kernel_0Pff
.p2align 3, 0x0
_Z14_auto_kernel_0Pff:
.quad _Z29__device_stub___auto_kernel_0Pff
.size _Z14_auto_kernel_0Pff, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result: %f\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14_auto_kernel_0Pff"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub___auto_kernel_0Pff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14_auto_kernel_0Pff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void arrayOfPriors ( const int dim, const int nwl, const float *cn, const float *xx, float *pr ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
float sum = 0.;
if ( i < nwl ) {
pr[i] = ( cn[i] == dim ) * sum + ( cn[i] < dim ) * INF;
}
} | code for sm_80
Function : _Z13arrayOfPriorsiiPKfS0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x164], PT ; /* 0x0000590006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ I2F R0, c[0x0][0x160] ; /* 0x0000580000007b06 */
/* 0x000ea20000201400 */
/*00b0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ FSETP.GEU.AND P0, PT, R3, R0, PT ; /* 0x000000000300720b */
/* 0x004fc80003f0e000 */
/*00e0*/ FSEL R5, RZ, 1.875, P0 ; /* 0x3ff00000ff057808 */
/* 0x000fcc0000000000 */
/*00f0*/ DFMA R4, R4, c[0x2][0x0], RZ ; /* 0x0080000004047a2b */
/* 0x000e1400000000ff */
/*0100*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*0110*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x001fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void arrayOfPriors ( const int dim, const int nwl, const float *cn, const float *xx, float *pr ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
float sum = 0.;
if ( i < nwl ) {
pr[i] = ( cn[i] == dim ) * sum + ( cn[i] < dim ) * INF;
}
} | .file "tmpxft_0012a533_00000000-6_arrayOfPriors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf
.type _Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf, @function
_Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13arrayOfPriorsiiPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf, .-_Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf
.globl _Z13arrayOfPriorsiiPKfS0_Pf
.type _Z13arrayOfPriorsiiPKfS0_Pf, @function
_Z13arrayOfPriorsiiPKfS0_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13arrayOfPriorsiiPKfS0_Pf, .-_Z13arrayOfPriorsiiPKfS0_Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13arrayOfPriorsiiPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13arrayOfPriorsiiPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void arrayOfPriors ( const int dim, const int nwl, const float *cn, const float *xx, float *pr ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
float sum = 0.;
if ( i < nwl ) {
pr[i] = ( cn[i] == dim ) * sum + ( cn[i] < dim ) * INF;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void arrayOfPriors ( const int dim, const int nwl, const float *cn, const float *xx, float *pr ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
float sum = 0.;
if ( i < nwl ) {
pr[i] = ( cn[i] == dim ) * sum + ( cn[i] < dim ) * INF;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void arrayOfPriors ( const int dim, const int nwl, const float *cn, const float *xx, float *pr ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
float sum = 0.;
if ( i < nwl ) {
pr[i] = ( cn[i] == dim ) * sum + ( cn[i] < dim ) * INF;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13arrayOfPriorsiiPKfS0_Pf
.globl _Z13arrayOfPriorsiiPKfS0_Pf
.p2align 8
.type _Z13arrayOfPriorsiiPKfS0_Pf,@function
_Z13arrayOfPriorsiiPKfS0_Pf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x0
s_mov_b32 s1, 0x43f158e4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
v_cvt_f32_i32_e32 v3, s0
s_mov_b32 s0, 0x60913d00
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v2, 0
v_cndmask_b32_e64 v3, 0, 0x3ff00000, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], s[0:1], 0
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13arrayOfPriorsiiPKfS0_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13arrayOfPriorsiiPKfS0_Pf, .Lfunc_end0-_Z13arrayOfPriorsiiPKfS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13arrayOfPriorsiiPKfS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13arrayOfPriorsiiPKfS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void arrayOfPriors ( const int dim, const int nwl, const float *cn, const float *xx, float *pr ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
float sum = 0.;
if ( i < nwl ) {
pr[i] = ( cn[i] == dim ) * sum + ( cn[i] < dim ) * INF;
}
} | .text
.file "arrayOfPriors.hip"
.globl _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf # -- Begin function _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf
.p2align 4, 0x90
.type _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf,@function
_Z28__device_stub__arrayOfPriorsiiPKfS0_Pf: # @_Z28__device_stub__arrayOfPriorsiiPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13arrayOfPriorsiiPKfS0_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf, .Lfunc_end0-_Z28__device_stub__arrayOfPriorsiiPKfS0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13arrayOfPriorsiiPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13arrayOfPriorsiiPKfS0_Pf,@object # @_Z13arrayOfPriorsiiPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z13arrayOfPriorsiiPKfS0_Pf
.p2align 3, 0x0
_Z13arrayOfPriorsiiPKfS0_Pf:
.quad _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf
.size _Z13arrayOfPriorsiiPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13arrayOfPriorsiiPKfS0_Pf"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13arrayOfPriorsiiPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13arrayOfPriorsiiPKfS0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x164], PT ; /* 0x0000590006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ I2F R0, c[0x0][0x160] ; /* 0x0000580000007b06 */
/* 0x000ea20000201400 */
/*00b0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ FSETP.GEU.AND P0, PT, R3, R0, PT ; /* 0x000000000300720b */
/* 0x004fc80003f0e000 */
/*00e0*/ FSEL R5, RZ, 1.875, P0 ; /* 0x3ff00000ff057808 */
/* 0x000fcc0000000000 */
/*00f0*/ DFMA R4, R4, c[0x2][0x0], RZ ; /* 0x0080000004047a2b */
/* 0x000e1400000000ff */
/*0100*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*0110*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x001fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13arrayOfPriorsiiPKfS0_Pf
.globl _Z13arrayOfPriorsiiPKfS0_Pf
.p2align 8
.type _Z13arrayOfPriorsiiPKfS0_Pf,@function
_Z13arrayOfPriorsiiPKfS0_Pf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x0
s_mov_b32 s1, 0x43f158e4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
v_cvt_f32_i32_e32 v3, s0
s_mov_b32 s0, 0x60913d00
s_waitcnt vmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v2, 0
v_cndmask_b32_e64 v3, 0, 0x3ff00000, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], s[0:1], 0
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13arrayOfPriorsiiPKfS0_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13arrayOfPriorsiiPKfS0_Pf, .Lfunc_end0-_Z13arrayOfPriorsiiPKfS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13arrayOfPriorsiiPKfS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13arrayOfPriorsiiPKfS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012a533_00000000-6_arrayOfPriors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf
.type _Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf, @function
_Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13arrayOfPriorsiiPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf, .-_Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf
.globl _Z13arrayOfPriorsiiPKfS0_Pf
.type _Z13arrayOfPriorsiiPKfS0_Pf, @function
_Z13arrayOfPriorsiiPKfS0_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z13arrayOfPriorsiiPKfS0_PfiiPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13arrayOfPriorsiiPKfS0_Pf, .-_Z13arrayOfPriorsiiPKfS0_Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13arrayOfPriorsiiPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13arrayOfPriorsiiPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "arrayOfPriors.hip"
.globl _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf # -- Begin function _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf
.p2align 4, 0x90
.type _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf,@function
_Z28__device_stub__arrayOfPriorsiiPKfS0_Pf: # @_Z28__device_stub__arrayOfPriorsiiPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13arrayOfPriorsiiPKfS0_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf, .Lfunc_end0-_Z28__device_stub__arrayOfPriorsiiPKfS0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13arrayOfPriorsiiPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13arrayOfPriorsiiPKfS0_Pf,@object # @_Z13arrayOfPriorsiiPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z13arrayOfPriorsiiPKfS0_Pf
.p2align 3, 0x0
_Z13arrayOfPriorsiiPKfS0_Pf:
.quad _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf
.size _Z13arrayOfPriorsiiPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13arrayOfPriorsiiPKfS0_Pf"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__arrayOfPriorsiiPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13arrayOfPriorsiiPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
* Module to test CUDA module loading and execution.
* To be compiled with:
* nvcc -ptx module_test.cu
*/
#ifdef __cplusplus
extern "C" {
#endif
/// Sets the first N elements of array to value.
#ifdef __cplusplus
}
#endif
__global__ void testMemset(float* array, float value, int N){
int i = ( blockIdx.y*gridDim.x + blockIdx.x ) * blockDim.x + threadIdx.x;
if(i < N){
array[i] = value;
}
} | code for sm_80
Function : _Z10testMemsetPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
* Module to test CUDA module loading and execution.
* To be compiled with:
* nvcc -ptx module_test.cu
*/
#ifdef __cplusplus
extern "C" {
#endif
/// Sets the first N elements of array to value.
#ifdef __cplusplus
}
#endif
__global__ void testMemset(float* array, float value, int N){
int i = ( blockIdx.y*gridDim.x + blockIdx.x ) * blockDim.x + threadIdx.x;
if(i < N){
array[i] = value;
}
} | .file "tmpxft_000f4175_00000000-6_testMemset.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10testMemsetPffiPffi
.type _Z32__device_stub__Z10testMemsetPffiPffi, @function
_Z32__device_stub__Z10testMemsetPffiPffi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10testMemsetPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10testMemsetPffiPffi, .-_Z32__device_stub__Z10testMemsetPffiPffi
.globl _Z10testMemsetPffi
.type _Z10testMemsetPffi, @function
_Z10testMemsetPffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10testMemsetPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10testMemsetPffi, .-_Z10testMemsetPffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10testMemsetPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testMemsetPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
* Module to test CUDA module loading and execution.
* To be compiled with:
* nvcc -ptx module_test.cu
*/
#ifdef __cplusplus
extern "C" {
#endif
/// Sets the first N elements of array to value.
#ifdef __cplusplus
}
#endif
__global__ void testMemset(float* array, float value, int N){
int i = ( blockIdx.y*gridDim.x + blockIdx.x ) * blockDim.x + threadIdx.x;
if(i < N){
array[i] = value;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Module to test CUDA module loading and execution.
* To be compiled with:
* nvcc -ptx module_test.cu
*/
#ifdef __cplusplus
extern "C" {
#endif
/// Sets the first N elements of array to value.
#ifdef __cplusplus
}
#endif
__global__ void testMemset(float* array, float value, int N){
int i = ( blockIdx.y*gridDim.x + blockIdx.x ) * blockDim.x + threadIdx.x;
if(i < N){
array[i] = value;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Module to test CUDA module loading and execution.
* To be compiled with:
* nvcc -ptx module_test.cu
*/
#ifdef __cplusplus
extern "C" {
#endif
/// Sets the first N elements of array to value.
#ifdef __cplusplus
}
#endif
__global__ void testMemset(float* array, float value, int N){
int i = ( blockIdx.y*gridDim.x + blockIdx.x ) * blockDim.x + threadIdx.x;
if(i < N){
array[i] = value;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10testMemsetPffi
.globl _Z10testMemsetPffi
.p2align 8
.type _Z10testMemsetPffi,@function
_Z10testMemsetPffi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10testMemsetPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10testMemsetPffi, .Lfunc_end0-_Z10testMemsetPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10testMemsetPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10testMemsetPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Module to test CUDA module loading and execution.
* To be compiled with:
* nvcc -ptx module_test.cu
*/
#ifdef __cplusplus
extern "C" {
#endif
/// Sets the first N elements of array to value.
#ifdef __cplusplus
}
#endif
__global__ void testMemset(float* array, float value, int N){
int i = ( blockIdx.y*gridDim.x + blockIdx.x ) * blockDim.x + threadIdx.x;
if(i < N){
array[i] = value;
}
} | .text
.file "testMemset.hip"
.globl _Z25__device_stub__testMemsetPffi # -- Begin function _Z25__device_stub__testMemsetPffi
.p2align 4, 0x90
.type _Z25__device_stub__testMemsetPffi,@function
_Z25__device_stub__testMemsetPffi: # @_Z25__device_stub__testMemsetPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10testMemsetPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__testMemsetPffi, .Lfunc_end0-_Z25__device_stub__testMemsetPffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testMemsetPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10testMemsetPffi,@object # @_Z10testMemsetPffi
.section .rodata,"a",@progbits
.globl _Z10testMemsetPffi
.p2align 3, 0x0
_Z10testMemsetPffi:
.quad _Z25__device_stub__testMemsetPffi
.size _Z10testMemsetPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10testMemsetPffi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testMemsetPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testMemsetPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10testMemsetPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10testMemsetPffi
.globl _Z10testMemsetPffi
.p2align 8
.type _Z10testMemsetPffi,@function
_Z10testMemsetPffi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0xc
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10testMemsetPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10testMemsetPffi, .Lfunc_end0-_Z10testMemsetPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10testMemsetPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10testMemsetPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f4175_00000000-6_testMemset.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10testMemsetPffiPffi
.type _Z32__device_stub__Z10testMemsetPffiPffi, @function
_Z32__device_stub__Z10testMemsetPffiPffi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10testMemsetPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10testMemsetPffiPffi, .-_Z32__device_stub__Z10testMemsetPffiPffi
.globl _Z10testMemsetPffi
.type _Z10testMemsetPffi, @function
_Z10testMemsetPffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10testMemsetPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10testMemsetPffi, .-_Z10testMemsetPffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10testMemsetPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testMemsetPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "testMemset.hip"
.globl _Z25__device_stub__testMemsetPffi # -- Begin function _Z25__device_stub__testMemsetPffi
.p2align 4, 0x90
.type _Z25__device_stub__testMemsetPffi,@function
_Z25__device_stub__testMemsetPffi: # @_Z25__device_stub__testMemsetPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10testMemsetPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__testMemsetPffi, .Lfunc_end0-_Z25__device_stub__testMemsetPffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testMemsetPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10testMemsetPffi,@object # @_Z10testMemsetPffi
.section .rodata,"a",@progbits
.globl _Z10testMemsetPffi
.p2align 3, 0x0
_Z10testMemsetPffi:
.quad _Z25__device_stub__testMemsetPffi
.size _Z10testMemsetPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10testMemsetPffi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testMemsetPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testMemsetPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void global_memory_kernel(int *d_go_to_state, unsigned int *d_failure_state, unsigned int *d_output_state, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int num_blocks ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int chars_per_block = n / num_blocks;
int start_block = blockIdx.x * chars_per_block;
int stop_block = start_block + chars_per_block;
int chars_per_thread = ( stop_block - start_block ) / blockDim.x;
int start_thread = start_block + chars_per_thread * threadIdx.x;
int stop_thread;
if( blockIdx.x == num_blocks -1 && threadIdx.x==blockDim.x-1)
stop_thread = n - 1;
else stop_thread = start_thread + chars_per_thread + m-1;
int r = 0, s;
int column;
for ( column = start_thread; ( column < stop_thread && column < n ); column++ ) {
while ( ( s = d_go_to_state[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_failure_state[r];
r = s;
d_out[idx] += d_output_state[r];
}
} | code for sm_80
Function : _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x1a0] ; /* 0x0000680000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC UR4, c[0x0][0x194] ; /* 0x0000650000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IABS R6, c[0x0][0x194] ; /* 0x0000650000067a13 */
/* 0x000fe20000000000 */
/*0040*/ ULDC UR6, c[0x0][0x1a0] ; /* 0x0000680000067ab9 */
/* 0x000fe20000000800 */
/*0050*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*0060*/ ULOP3.LUT UR4, UR4, UR6, URZ, 0x3c, !UPT ; /* 0x0000000604047292 */
/* 0x000fe4000f8e3c3f */
/*0070*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fc80000000000 */
/*0080*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf23270 */
/*0090*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc6000fffe13f */
/*00a0*/ ULDC UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe40000000800 */
/*00b0*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fe2000fffe13f */
/*00c0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00d0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00e0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0100*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*0110*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe400078e02ff */
/*0120*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e240000209000 */
/*0130*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0140*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a00 */
/*0160*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e260000001000 */
/*0170*/ IMAD R2, R5, R3, R6 ; /* 0x0000000305027224 */
/* 0x000fca00078e0206 */
/*0180*/ ISETP.GT.U32.AND P2, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe40003f44070 */
/*0190*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fd60007ffe0ff */
/*01a0*/ @!P2 IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a05 */
/*01b0*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*01d0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x1a0], PT ; /* 0x00006800ff007a0c */
/* 0x000fe40003f45270 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe20003f06070 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd800078e00ff */
/*0200*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x001fc800078e0a03 */
/*0220*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0230*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fe200078e02ff */
/*0240*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0250*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0260*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x1a0], RZ, 0x33, !PT ; /* 0x00006800ff04aa12 */
/* 0x000fe200078e33ff */
/*0270*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe200078e0002 */
/*0280*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fca0003f45070 */
/*0290*/ IMAD.HI.U32 R2, R3, R4, RZ ; /* 0x0000000403027227 */
/* 0x000fe400078e00ff */
/*02a0*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e640000002500 */
/*02b0*/ IMAD.MOV R5, RZ, RZ, -R2 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a02 */
/*02c0*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x000fca00078e0204 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fda0003f06070 */
/*02e0*/ @P0 IADD3 R5, R5, -c[0x0][0x0], RZ ; /* 0x8000000005050a10 */
/* 0x000fe40007ffe0ff */
/*02f0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0300*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fe20003f26070 */
/*0310*/ IMAD R5, R4, R3, RZ ; /* 0x0000000304057224 */
/* 0x002fe200078e02ff */
/*0320*/ ISETP.NE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fc8000bf05270 */
/*0330*/ ISETP.EQ.AND P0, PT, R0, UR5, !P0 ; /* 0x0000000500007c0c */
/* 0x001fce000c702270 */
/*0340*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0350*/ @!P2 LOP3.LUT R2, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff02aa12 */
/* 0x000fca00078e33ff */
/*0360*/ IMAD R5, R2, R0, R5 ; /* 0x0000000002057224 */
/* 0x000fca00078e0205 */
/*0370*/ IADD3 R2, R5, c[0x0][0x190], R2 ; /* 0x0000640005027a10 */
/* 0x000fc80007ffe002 */
/*0380*/ SEL R2, R2, c[0x0][0x194], !P0 ; /* 0x0000650002027a07 */
/* 0x000fe40004000000 */
/*0390*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x194], PT ; /* 0x0000650005007a0c */
/* 0x000fe40003f06270 */
/*03a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*03b0*/ ISETP.GE.OR P0, PT, R5, R2, P0 ; /* 0x000000020500720c */
/* 0x000fda0000706670 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0005 */
/*03e0*/ ULDC.64 UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x000fe20000000a00 */
/*03f0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0400*/ USHF.R.U64 UR4, UR4, 0x2, UR5 ; /* 0x0000000204047899 */
/* 0x000fe40008001205 */
/*0410*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0420*/ IADD3 R8, P0, R10, c[0x0][0x178], RZ ; /* 0x00005e000a087a10 */
/* 0x000fc80007f1e0ff */
/*0430*/ LEA.HI.X.SX32 R9, R10, c[0x0][0x17c], 0x1, P0 ; /* 0x00005f000a097a11 */
/* 0x001fca00000f0eff */
/*0440*/ LDG.E.U8 R14, [R8.64] ; /* 0x00000006080e7981 */
/* 0x000ea2000c1e1100 */
/*0450*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD R4, R11, UR4, R14 ; /* 0x000000040b047c24 */
/* 0x004fca000f8e020e */
/*0470*/ IADD3 R4, R4, -0x41, RZ ; /* 0xffffffbf04047810 */
/* 0x000fca0007ffe0ff */
/*0480*/ IMAD.WIDE R6, R4, R13, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x000fca00078e020d */
/*0490*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IMAD R4, R3, c[0x0][0x0], R0 ; /* 0x0000000003047a24 */
/* 0x000fe200078e0200 */
/*04b0*/ BSSY B0, 0x5a0 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*04c0*/ IMAD.WIDE R4, R4, R13, c[0x0][0x180] ; /* 0x0000600004047625 */
/* 0x000fe200078e020d */
/*04d0*/ ISETP.NE.AND P0, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x004fda0003f05270 */
/*04e0*/ @P0 BRA 0x590 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*04f0*/ BSSY B1, 0x590 ; /* 0x0000009000017945 */
/* 0x000fe40003800000 */
/*0500*/ IMAD.WIDE R6, R11, R13, c[0x0][0x168] ; /* 0x00005a000b067625 */
/* 0x000fca00078e020d */
/*0510*/ LDG.E R11, [R6.64] ; /* 0x00000006060b7981 */
/* 0x000ea4000c1e1900 */
/*0520*/ IMAD R8, R11, UR4, R14 ; /* 0x000000040b087c24 */
/* 0x004fca000f8e020e */
/*0530*/ IADD3 R8, R8, -0x41, RZ ; /* 0xffffffbf08087810 */
/* 0x000fca0007ffe0ff */
/*0540*/ IMAD.WIDE R8, R8, R13, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e020d */
/*0550*/ LDG.E R12, [R8.64] ; /* 0x00000006080c7981 */
/* 0x000ea4000c1e1900 */
/*0560*/ ISETP.NE.AND P0, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x004fda0003f05270 */
/*0570*/ @!P0 BRA 0x500 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0580*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.WIDE R6, R12, R13, c[0x0][0x170] ; /* 0x00005c000c067625 */
/* 0x000fe200078e020d */
/*05b0*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000eaa000c1e1900 */
/*05c0*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*05d0*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ IMAD.MOV.U32 R11, RZ, RZ, R12 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e000c */
/*05f0*/ ISETP.GE.AND P0, PT, R10.reuse, R2, PT ; /* 0x000000020a00720c */
/* 0x040fe40003f06270 */
/*0600*/ ISETP.LT.AND P1, PT, R10, c[0x0][0x194], PT ; /* 0x000065000a007a0c */
/* 0x000fe20003f21270 */
/*0610*/ IMAD.IADD R9, R8, 0x1, R7 ; /* 0x0000000108097824 */
/* 0x004fca00078e0207 */
/*0620*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001ee000c101906 */
/*0630*/ @!P0 BRA P1, 0x420 ; /* 0xfffffde000008947 */
/* 0x000fea000083ffff */
/*0640*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0650*/ BRA 0x650; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void global_memory_kernel(int *d_go_to_state, unsigned int *d_failure_state, unsigned int *d_output_state, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int num_blocks ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int chars_per_block = n / num_blocks;
int start_block = blockIdx.x * chars_per_block;
int stop_block = start_block + chars_per_block;
int chars_per_thread = ( stop_block - start_block ) / blockDim.x;
int start_thread = start_block + chars_per_thread * threadIdx.x;
int stop_thread;
if( blockIdx.x == num_blocks -1 && threadIdx.x==blockDim.x-1)
stop_thread = n - 1;
else stop_thread = start_thread + chars_per_thread + m-1;
int r = 0, s;
int column;
for ( column = start_thread; ( column < stop_thread && column < n ); column++ ) {
while ( ( s = d_go_to_state[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_failure_state[r];
r = s;
d_out[idx] += d_output_state[r];
}
} | .file "tmpxft_0008d596_00000000-6_global_memory_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
.type _Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii, @function
_Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20global_memory_kernelPiPjS0_PhS0_miiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii, .-_Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
.globl _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.type _Z20global_memory_kernelPiPjS0_PhS0_miiiii, @function
_Z20global_memory_kernelPiPjS0_PhS0_miiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20global_memory_kernelPiPjS0_PhS0_miiiii, .-_Z20global_memory_kernelPiPjS0_PhS0_miiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20global_memory_kernelPiPjS0_PhS0_miiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20global_memory_kernelPiPjS0_PhS0_miiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void global_memory_kernel(int *d_go_to_state, unsigned int *d_failure_state, unsigned int *d_output_state, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int num_blocks ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int chars_per_block = n / num_blocks;
int start_block = blockIdx.x * chars_per_block;
int stop_block = start_block + chars_per_block;
int chars_per_thread = ( stop_block - start_block ) / blockDim.x;
int start_thread = start_block + chars_per_thread * threadIdx.x;
int stop_thread;
if( blockIdx.x == num_blocks -1 && threadIdx.x==blockDim.x-1)
stop_thread = n - 1;
else stop_thread = start_thread + chars_per_thread + m-1;
int r = 0, s;
int column;
for ( column = start_thread; ( column < stop_thread && column < n ); column++ ) {
while ( ( s = d_go_to_state[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_failure_state[r];
r = s;
d_out[idx] += d_output_state[r];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void global_memory_kernel(int *d_go_to_state, unsigned int *d_failure_state, unsigned int *d_output_state, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int num_blocks ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int chars_per_block = n / num_blocks;
int start_block = blockIdx.x * chars_per_block;
int stop_block = start_block + chars_per_block;
int chars_per_thread = ( stop_block - start_block ) / blockDim.x;
int start_thread = start_block + chars_per_thread * threadIdx.x;
int stop_thread;
if( blockIdx.x == num_blocks -1 && threadIdx.x==blockDim.x-1)
stop_thread = n - 1;
else stop_thread = start_thread + chars_per_thread + m-1;
int r = 0, s;
int column;
for ( column = start_thread; ( column < stop_thread && column < n ); column++ ) {
while ( ( s = d_go_to_state[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_failure_state[r];
r = s;
d_out[idx] += d_output_state[r];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void global_memory_kernel(int *d_go_to_state, unsigned int *d_failure_state, unsigned int *d_output_state, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int num_blocks ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int chars_per_block = n / num_blocks;
int start_block = blockIdx.x * chars_per_block;
int stop_block = start_block + chars_per_block;
int chars_per_thread = ( stop_block - start_block ) / blockDim.x;
int start_thread = start_block + chars_per_thread * threadIdx.x;
int stop_thread;
if( blockIdx.x == num_blocks -1 && threadIdx.x==blockDim.x-1)
stop_thread = n - 1;
else stop_thread = start_thread + chars_per_thread + m-1;
int r = 0, s;
int column;
for ( column = start_thread; ( column < stop_thread && column < n ); column++ ) {
while ( ( s = d_go_to_state[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_failure_state[r];
r = s;
d_out[idx] += d_output_state[r];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.globl _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.p2align 8
.type _Z20global_memory_kernelPiPjS0_PhS0_miiiii,@function
_Z20global_memory_kernelPiPjS0_PhS0_miiiii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x40
s_load_b32 s2, s[0:1], 0x54
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s3, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s3, s6
v_cvt_f32_u32_e32 v2, s2
s_xor_b32 s7, s4, s6
s_load_b64 s[4:5], s[0:1], 0x30
v_cvt_f32_u32_e32 v1, s7
s_sub_i32 s10, 0, s7
v_rcp_iflag_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s9, s5, 31
v_cvt_u32_f32_e32 v1, v1
s_add_i32 s11, s5, s9
s_xor_b32 s6, s9, s6
s_xor_b32 s11, s11, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s8, v1
v_mul_f32_e32 v1, 0x4f7ffffe, v2
s_mul_i32 s10, s10, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_u32_f32_e32 v1, v1
s_mul_hi_u32 s10, s8, s10
s_add_i32 s8, s8, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readfirstlane_b32 s12, v1
s_mul_hi_u32 s8, s11, s8
s_mul_i32 s9, s8, s7
s_add_i32 s10, s8, 1
s_sub_i32 s9, s11, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s11, s9, s7
s_cmp_ge_u32 s9, s7
s_cselect_b32 s8, s10, s8
s_cselect_b32 s9, s11, s9
s_add_i32 s10, s8, 1
s_cmp_ge_u32 s9, s7
s_cselect_b32 s7, s10, s8
s_sub_i32 s8, 0, s2
s_xor_b32 s7, s7, s6
s_mul_i32 s8, s8, s12
s_sub_i32 s6, s7, s6
s_mul_hi_u32 s8, s12, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s12, s8
s_mul_hi_u32 s7, s6, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s8, s7, s2
s_add_i32 s9, s7, 1
s_sub_i32 s8, s6, s8
s_mul_i32 s6, s6, s15
s_sub_i32 s10, s8, s2
s_cmp_ge_u32 s8, s2
s_cselect_b32 s7, s9, s7
s_cselect_b32 s8, s10, s8
s_add_i32 s9, s7, 1
s_cmp_ge_u32 s8, s2
s_mov_b32 s8, 0
s_cselect_b32 s7, s9, s7
s_add_i32 s3, s3, -1
v_mad_u64_u32 v[1:2], null, s7, v0, s[6:7]
s_cmp_eq_u32 s15, s3
s_cselect_b32 s3, -1, 0
s_add_i32 s6, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, s6, v0
v_add3_u32 v2, s7, s4, v1
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v2, v2, s5, s3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, -1, v2
v_min_i32_e32 v7, s5, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v1, v7
s_cbranch_execz .LBB0_7
s_load_b128 s[16:19], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_load_b256 s[0:7], s[0:1], 0x0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s16, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
v_alignbit_b32 v8, s19, s18, 2
global_load_b32 v0, v[2:3], off
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v4, v[9:10], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v4
v_mov_b32_e32 v4, v5
v_cmp_ge_i32_e32 vcc_lo, v1, v7
global_store_b32 v[2:3], v0, off
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v6, 31, v1
v_add_co_u32 v5, vcc_lo, s6, v1
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_u8 v6, v[5:6], off
v_mul_lo_u32 v5, v4, v8
s_waitcnt vmcnt(0)
v_add3_u32 v9, v5, v6, 0xffffffbf
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 -1, v5
s_cbranch_execz .LBB0_2
s_mov_b32 s10, 0
.p2align 6
.LBB0_5:
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v4, v8
v_add3_u32 v9, v5, v6, 0xffffffbf
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s10
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20global_memory_kernelPiPjS0_PhS0_miiiii, .Lfunc_end0-_Z20global_memory_kernelPiPjS0_PhS0_miiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z20global_memory_kernelPiPjS0_PhS0_miiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void global_memory_kernel(int *d_go_to_state, unsigned int *d_failure_state, unsigned int *d_output_state, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int num_blocks ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int chars_per_block = n / num_blocks;
int start_block = blockIdx.x * chars_per_block;
int stop_block = start_block + chars_per_block;
int chars_per_thread = ( stop_block - start_block ) / blockDim.x;
int start_thread = start_block + chars_per_thread * threadIdx.x;
int stop_thread;
if( blockIdx.x == num_blocks -1 && threadIdx.x==blockDim.x-1)
stop_thread = n - 1;
else stop_thread = start_thread + chars_per_thread + m-1;
int r = 0, s;
int column;
for ( column = start_thread; ( column < stop_thread && column < n ); column++ ) {
while ( ( s = d_go_to_state[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_failure_state[r];
r = s;
d_out[idx] += d_output_state[r];
}
} | .text
.file "global_memory_kernel.hip"
.globl _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii # -- Begin function _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii
.p2align 4, 0x90
.type _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii,@function
_Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii: # @_Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20global_memory_kernelPiPjS0_PhS0_miiiii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii, .Lfunc_end0-_Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20global_memory_kernelPiPjS0_PhS0_miiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20global_memory_kernelPiPjS0_PhS0_miiiii,@object # @_Z20global_memory_kernelPiPjS0_PhS0_miiiii
.section .rodata,"a",@progbits
.globl _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.p2align 3, 0x0
_Z20global_memory_kernelPiPjS0_PhS0_miiiii:
.quad _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii
.size _Z20global_memory_kernelPiPjS0_PhS0_miiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20global_memory_kernelPiPjS0_PhS0_miiiii"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x1a0] ; /* 0x0000680000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC UR4, c[0x0][0x194] ; /* 0x0000650000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IABS R6, c[0x0][0x194] ; /* 0x0000650000067a13 */
/* 0x000fe20000000000 */
/*0040*/ ULDC UR6, c[0x0][0x1a0] ; /* 0x0000680000067ab9 */
/* 0x000fe20000000800 */
/*0050*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*0060*/ ULOP3.LUT UR4, UR4, UR6, URZ, 0x3c, !UPT ; /* 0x0000000604047292 */
/* 0x000fe4000f8e3c3f */
/*0070*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fc80000000000 */
/*0080*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf23270 */
/*0090*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fc6000fffe13f */
/*00a0*/ ULDC UR6, c[0x0][0x0] ; /* 0x0000000000067ab9 */
/* 0x000fe40000000800 */
/*00b0*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fe2000fffe13f */
/*00c0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00d0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00e0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0100*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*0110*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe400078e02ff */
/*0120*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e240000209000 */
/*0130*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0140*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a00 */
/*0160*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e260000001000 */
/*0170*/ IMAD R2, R5, R3, R6 ; /* 0x0000000305027224 */
/* 0x000fca00078e0206 */
/*0180*/ ISETP.GT.U32.AND P2, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe40003f44070 */
/*0190*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fd60007ffe0ff */
/*01a0*/ @!P2 IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a05 */
/*01b0*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*01d0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x1a0], PT ; /* 0x00006800ff007a0c */
/* 0x000fe40003f45270 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe20003f06070 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd800078e00ff */
/*0200*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x001fc800078e0a03 */
/*0220*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0230*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fe200078e02ff */
/*0240*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0250*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*0260*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x1a0], RZ, 0x33, !PT ; /* 0x00006800ff04aa12 */
/* 0x000fe200078e33ff */
/*0270*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe200078e0002 */
/*0280*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fca0003f45070 */
/*0290*/ IMAD.HI.U32 R2, R3, R4, RZ ; /* 0x0000000403027227 */
/* 0x000fe400078e00ff */
/*02a0*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e640000002500 */
/*02b0*/ IMAD.MOV R5, RZ, RZ, -R2 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a02 */
/*02c0*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x000fca00078e0204 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fda0003f06070 */
/*02e0*/ @P0 IADD3 R5, R5, -c[0x0][0x0], RZ ; /* 0x8000000005050a10 */
/* 0x000fe40007ffe0ff */
/*02f0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0300*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fe20003f26070 */
/*0310*/ IMAD R5, R4, R3, RZ ; /* 0x0000000304057224 */
/* 0x002fe200078e02ff */
/*0320*/ ISETP.NE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fc8000bf05270 */
/*0330*/ ISETP.EQ.AND P0, PT, R0, UR5, !P0 ; /* 0x0000000500007c0c */
/* 0x001fce000c702270 */
/*0340*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0350*/ @!P2 LOP3.LUT R2, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff02aa12 */
/* 0x000fca00078e33ff */
/*0360*/ IMAD R5, R2, R0, R5 ; /* 0x0000000002057224 */
/* 0x000fca00078e0205 */
/*0370*/ IADD3 R2, R5, c[0x0][0x190], R2 ; /* 0x0000640005027a10 */
/* 0x000fc80007ffe002 */
/*0380*/ SEL R2, R2, c[0x0][0x194], !P0 ; /* 0x0000650002027a07 */
/* 0x000fe40004000000 */
/*0390*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x194], PT ; /* 0x0000650005007a0c */
/* 0x000fe40003f06270 */
/*03a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*03b0*/ ISETP.GE.OR P0, PT, R5, R2, P0 ; /* 0x000000020500720c */
/* 0x000fda0000706670 */
/*03c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0005 */
/*03e0*/ ULDC.64 UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x000fe20000000a00 */
/*03f0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0400*/ USHF.R.U64 UR4, UR4, 0x2, UR5 ; /* 0x0000000204047899 */
/* 0x000fe40008001205 */
/*0410*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0420*/ IADD3 R8, P0, R10, c[0x0][0x178], RZ ; /* 0x00005e000a087a10 */
/* 0x000fc80007f1e0ff */
/*0430*/ LEA.HI.X.SX32 R9, R10, c[0x0][0x17c], 0x1, P0 ; /* 0x00005f000a097a11 */
/* 0x001fca00000f0eff */
/*0440*/ LDG.E.U8 R14, [R8.64] ; /* 0x00000006080e7981 */
/* 0x000ea2000c1e1100 */
/*0450*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD R4, R11, UR4, R14 ; /* 0x000000040b047c24 */
/* 0x004fca000f8e020e */
/*0470*/ IADD3 R4, R4, -0x41, RZ ; /* 0xffffffbf04047810 */
/* 0x000fca0007ffe0ff */
/*0480*/ IMAD.WIDE R6, R4, R13, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x000fca00078e020d */
/*0490*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IMAD R4, R3, c[0x0][0x0], R0 ; /* 0x0000000003047a24 */
/* 0x000fe200078e0200 */
/*04b0*/ BSSY B0, 0x5a0 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*04c0*/ IMAD.WIDE R4, R4, R13, c[0x0][0x180] ; /* 0x0000600004047625 */
/* 0x000fe200078e020d */
/*04d0*/ ISETP.NE.AND P0, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x004fda0003f05270 */
/*04e0*/ @P0 BRA 0x590 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*04f0*/ BSSY B1, 0x590 ; /* 0x0000009000017945 */
/* 0x000fe40003800000 */
/*0500*/ IMAD.WIDE R6, R11, R13, c[0x0][0x168] ; /* 0x00005a000b067625 */
/* 0x000fca00078e020d */
/*0510*/ LDG.E R11, [R6.64] ; /* 0x00000006060b7981 */
/* 0x000ea4000c1e1900 */
/*0520*/ IMAD R8, R11, UR4, R14 ; /* 0x000000040b087c24 */
/* 0x004fca000f8e020e */
/*0530*/ IADD3 R8, R8, -0x41, RZ ; /* 0xffffffbf08087810 */
/* 0x000fca0007ffe0ff */
/*0540*/ IMAD.WIDE R8, R8, R13, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e020d */
/*0550*/ LDG.E R12, [R8.64] ; /* 0x00000006080c7981 */
/* 0x000ea4000c1e1900 */
/*0560*/ ISETP.NE.AND P0, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x004fda0003f05270 */
/*0570*/ @!P0 BRA 0x500 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0580*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.WIDE R6, R12, R13, c[0x0][0x170] ; /* 0x00005c000c067625 */
/* 0x000fe200078e020d */
/*05b0*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000eaa000c1e1900 */
/*05c0*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*05d0*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ IMAD.MOV.U32 R11, RZ, RZ, R12 ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e000c */
/*05f0*/ ISETP.GE.AND P0, PT, R10.reuse, R2, PT ; /* 0x000000020a00720c */
/* 0x040fe40003f06270 */
/*0600*/ ISETP.LT.AND P1, PT, R10, c[0x0][0x194], PT ; /* 0x000065000a007a0c */
/* 0x000fe20003f21270 */
/*0610*/ IMAD.IADD R9, R8, 0x1, R7 ; /* 0x0000000108097824 */
/* 0x004fca00078e0207 */
/*0620*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001ee000c101906 */
/*0630*/ @!P0 BRA P1, 0x420 ; /* 0xfffffde000008947 */
/* 0x000fea000083ffff */
/*0640*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0650*/ BRA 0x650; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.globl _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.p2align 8
.type _Z20global_memory_kernelPiPjS0_PhS0_miiiii,@function
_Z20global_memory_kernelPiPjS0_PhS0_miiiii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x40
s_load_b32 s2, s[0:1], 0x54
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s3, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s3, s6
v_cvt_f32_u32_e32 v2, s2
s_xor_b32 s7, s4, s6
s_load_b64 s[4:5], s[0:1], 0x30
v_cvt_f32_u32_e32 v1, s7
s_sub_i32 s10, 0, s7
v_rcp_iflag_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s9, s5, 31
v_cvt_u32_f32_e32 v1, v1
s_add_i32 s11, s5, s9
s_xor_b32 s6, s9, s6
s_xor_b32 s11, s11, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s8, v1
v_mul_f32_e32 v1, 0x4f7ffffe, v2
s_mul_i32 s10, s10, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_u32_f32_e32 v1, v1
s_mul_hi_u32 s10, s8, s10
s_add_i32 s8, s8, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readfirstlane_b32 s12, v1
s_mul_hi_u32 s8, s11, s8
s_mul_i32 s9, s8, s7
s_add_i32 s10, s8, 1
s_sub_i32 s9, s11, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s11, s9, s7
s_cmp_ge_u32 s9, s7
s_cselect_b32 s8, s10, s8
s_cselect_b32 s9, s11, s9
s_add_i32 s10, s8, 1
s_cmp_ge_u32 s9, s7
s_cselect_b32 s7, s10, s8
s_sub_i32 s8, 0, s2
s_xor_b32 s7, s7, s6
s_mul_i32 s8, s8, s12
s_sub_i32 s6, s7, s6
s_mul_hi_u32 s8, s12, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s12, s8
s_mul_hi_u32 s7, s6, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s8, s7, s2
s_add_i32 s9, s7, 1
s_sub_i32 s8, s6, s8
s_mul_i32 s6, s6, s15
s_sub_i32 s10, s8, s2
s_cmp_ge_u32 s8, s2
s_cselect_b32 s7, s9, s7
s_cselect_b32 s8, s10, s8
s_add_i32 s9, s7, 1
s_cmp_ge_u32 s8, s2
s_mov_b32 s8, 0
s_cselect_b32 s7, s9, s7
s_add_i32 s3, s3, -1
v_mad_u64_u32 v[1:2], null, s7, v0, s[6:7]
s_cmp_eq_u32 s15, s3
s_cselect_b32 s3, -1, 0
s_add_i32 s6, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, s6, v0
v_add3_u32 v2, s7, s4, v1
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v2, v2, s5, s3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, -1, v2
v_min_i32_e32 v7, s5, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v1, v7
s_cbranch_execz .LBB0_7
s_load_b128 s[16:19], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_load_b256 s[0:7], s[0:1], 0x0
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s16, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
v_alignbit_b32 v8, s19, s18, 2
global_load_b32 v0, v[2:3], off
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v4, v[9:10], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v4
v_mov_b32_e32 v4, v5
v_cmp_ge_i32_e32 vcc_lo, v1, v7
global_store_b32 v[2:3], v0, off
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v6, 31, v1
v_add_co_u32 v5, vcc_lo, s6, v1
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_u8 v6, v[5:6], off
v_mul_lo_u32 v5, v4, v8
s_waitcnt vmcnt(0)
v_add3_u32 v9, v5, v6, 0xffffffbf
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 -1, v5
s_cbranch_execz .LBB0_2
s_mov_b32 s10, 0
.p2align 6
.LBB0_5:
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v5, v4, v8
v_add3_u32 v9, v5, v6, 0xffffffbf
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, -1, v5
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s10
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20global_memory_kernelPiPjS0_PhS0_miiiii, .Lfunc_end0-_Z20global_memory_kernelPiPjS0_PhS0_miiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z20global_memory_kernelPiPjS0_PhS0_miiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008d596_00000000-6_global_memory_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
.type _Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii, @function
_Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20global_memory_kernelPiPjS0_PhS0_miiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii, .-_Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
.globl _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.type _Z20global_memory_kernelPiPjS0_PhS0_miiiii, @function
_Z20global_memory_kernelPiPjS0_PhS0_miiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z56__device_stub__Z20global_memory_kernelPiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20global_memory_kernelPiPjS0_PhS0_miiiii, .-_Z20global_memory_kernelPiPjS0_PhS0_miiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20global_memory_kernelPiPjS0_PhS0_miiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20global_memory_kernelPiPjS0_PhS0_miiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "global_memory_kernel.hip"
.globl _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii # -- Begin function _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii
.p2align 4, 0x90
.type _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii,@function
_Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii: # @_Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20global_memory_kernelPiPjS0_PhS0_miiiii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii, .Lfunc_end0-_Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20global_memory_kernelPiPjS0_PhS0_miiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20global_memory_kernelPiPjS0_PhS0_miiiii,@object # @_Z20global_memory_kernelPiPjS0_PhS0_miiiii
.section .rodata,"a",@progbits
.globl _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.p2align 3, 0x0
_Z20global_memory_kernelPiPjS0_PhS0_miiiii:
.quad _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii
.size _Z20global_memory_kernelPiPjS0_PhS0_miiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20global_memory_kernelPiPjS0_PhS0_miiiii"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__global_memory_kernelPiPjS0_PhS0_miiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20global_memory_kernelPiPjS0_PhS0_miiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdlib.h>
#include <string>
#include <vector>
#include <sstream>
#include <cuda.h>
#include <iterator>
using namespace std;
__global__ void multiply(int *A, int *B, int *C, int N) {
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int i = idx / N, j = idx % N;
int sum = 0;
for (int k = 0; k < N; k++) {
sum += A[i * N + k] * B[k * N + j];
}
C[idx] = sum;
}
int main() {
string line;
int N = -1;
int *A, *B, *C, *cur;
int count = 0;
while(getline(cin, line)) {
if (N == -1) {
N = atoi(line.c_str());
A = new int[N * N];
B = new int[N * N];
C = new int[N * N];
cur = A;
} else {
vector<string> nums;
istringstream iss(line);
copy(istream_iterator<string>(iss),
istream_iterator<string>(),
back_inserter(nums));
for (int i = 0; i < nums.size(); i++) {
cur[count * N + i] = atoi(nums[i].c_str());
}
count++;
if (count == N) {
count = 0;
cur = B;
}
}
}
int *dA, *dB, *dC;
cudaMalloc(&dA, sizeof(int) * N * N);
cudaMalloc(&dB, sizeof(int) * N * N);
cudaMalloc(&dC, sizeof(int) * N * N);
cudaMemcpy(dA, A, sizeof(int) * N * N, cudaMemcpyHostToDevice);
cudaMemcpy(dB, B, sizeof(int) * N * N, cudaMemcpyHostToDevice);
cudaMemcpy(dC, C, sizeof(int) * N * N, cudaMemcpyHostToDevice);
dim3 blockDim(64, 1, 1);
dim3 gridDim(N * N / blockDim.x, 1, 1);
multiply<<<gridDim, blockDim>>>(dA, dB, dC, N);
cudaMemcpy(dA, A, sizeof(int) * N * N, cudaMemcpyDeviceToHost);
cudaMemcpy(dB, B, sizeof(int) * N * N, cudaMemcpyDeviceToHost);
cudaMemcpy(dC, C, sizeof(int) * N * N, cudaMemcpyDeviceToHost);
return 0;
} | code for sm_80
Function : _Z8multiplyPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R8, c[0x0][0x178] ; /* 0x00005e0000087a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*0050*/ I2F.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e620000209400 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e2e0000002100 */
/*0070*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x002e620000001000 */
/*0080*/ IMAD R2, R0, c[0x0][0x0], R3 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f26270 */
/*00a0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x002fe40007ffe0ff */
/*00b0*/ IABS R6, R2 ; /* 0x0000000200067213 */
/* 0x000fe40000000000 */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*00e0*/ IADD3 R7, RZ, -R5, RZ ; /* 0x80000005ff077210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*0110*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fca0000000f00 */
/*0120*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fca00078e00ff */
/*0130*/ IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05057210 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD R5, R8, R5, R6 ; /* 0x0000000508057224 */
/* 0x000fca00078e0206 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f04070 */
/*0160*/ @!P0 IADD3 R5, R5, -R8, RZ ; /* 0x8000000805058210 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f05270 */
/*0180*/ ISETP.GT.U32.AND P2, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f44070 */
/*0190*/ @!P2 IADD3 R5, R5, -R8, RZ ; /* 0x800000080505a210 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.AND P2, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f46270 */
/*01b0*/ @!P1 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05059210 */
/* 0x000fe40007ffe1ff */
/*01c0*/ @!P0 LOP3.LUT R5, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff058a12 */
/* 0x000fd200078e33ff */
/*01d0*/ @!P2 BRA 0xd00 ; /* 0x00000b200000a947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R6, R4.reuse, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x040fe40007ffe0ff */
/*01f0*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe400078ec0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0210*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fd20000000f00 */
/*0230*/ @!P0 BRA 0xbe0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R8, -R7, c[0x0][0x178], RZ ; /* 0x00005e0007087a10 */
/* 0x000fe20007ffe1ff */
/*0250*/ HFMA2.MMA R26, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1a7435 */
/* 0x000fe200000001ff */
/*0260*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0270*/ IADD3 R9, R2, -R5, RZ ; /* 0x8000000502097210 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f04270 */
/*0290*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fc80000000f00 */
/*02a0*/ IMAD.WIDE R26, R5, R26, c[0x0][0x168] ; /* 0x00005a00051a7625 */
/* 0x000fce00078e021a */
/*02b0*/ @!P0 BRA 0xa50 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*02e0*/ @!P1 BRA 0x790 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0310*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0000a2000c1e1900 */
/*0320*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0330*/ IMAD.WIDE R12, R9, 0x4, R12 ; /* 0x00000004090c7825 */
/* 0x000fca00078e020c */
/*0340*/ LDG.E R28, [R12.64] ; /* 0x000000040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.WIDE R16, R4, 0x4, R26 ; /* 0x0000000404107825 */
/* 0x000fc600078e021a */
/*0360*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000ee6000c1e1900 */
/*0370*/ IMAD.WIDE R10, R4.reuse, 0x4, R16 ; /* 0x00000004040a7825 */
/* 0x040fe200078e0210 */
/*0380*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e8000c1e1900 */
/*0390*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000968000c1e1900 */
/*03a0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f68000c1e1900 */
/*03b0*/ LDG.E R14, [R12.64+0xc] ; /* 0x00000c040c0e7981 */
/* 0x000f62000c1e1900 */
/*03c0*/ IMAD.WIDE R10, R4, 0x4, R10 ; /* 0x00000004040a7825 */
/* 0x010fc600078e020a */
/*03d0*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x001f28000c1e1900 */
/*03e0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000122000c1e1900 */
/*03f0*/ IMAD.WIDE R20, R4, 0x4, R10 ; /* 0x0000000404147825 */
/* 0x000fca00078e020a */
/*0400*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000122000c1e1900 */
/*0410*/ IMAD.WIDE R16, R4, 0x4, R20 ; /* 0x0000000404107825 */
/* 0x002fc600078e0214 */
/*0420*/ LDG.E R10, [R12.64+0x18] ; /* 0x000018040c0a7981 */
/* 0x001f28000c1e1900 */
/*0430*/ LDG.E R21, [R12.64+0x1c] ; /* 0x00001c040c157981 */
/* 0x000f22000c1e1900 */
/*0440*/ IMAD R28, R19, R28, R18 ; /* 0x0000001c131c7224 */
/* 0x004fc600078e0212 */
/*0450*/ LDG.E R18, [R12.64+0x14] ; /* 0x000014040c127981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x0000a2000c1e1900 */
/*0470*/ IMAD R28, R22, R23, R28 ; /* 0x00000017161c7224 */
/* 0x008fe400078e021c */
/*0480*/ IMAD.WIDE R16, R4, 0x4, R16 ; /* 0x0000000404107825 */
/* 0x001fca00078e0210 */
/*0490*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000ae2000c1e1900 */
/*04a0*/ IMAD.WIDE R22, R4, 0x4, R16 ; /* 0x0000000404167825 */
/* 0x000fca00078e0210 */
/*04b0*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x0000e2000c1e1900 */
/*04c0*/ IMAD R16, R25, R24, R28 ; /* 0x0000001819107224 */
/* 0x020fe400078e021c */
/*04d0*/ IMAD.WIDE R24, R4.reuse, 0x4, R22 ; /* 0x0000000404187825 */
/* 0x040fe200078e0216 */
/*04e0*/ LDG.E R28, [R12.64+0x20] ; /* 0x000020040c1c7981 */
/* 0x000f68000c1e1900 */
/*04f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000362000c1e1900 */
/*0500*/ IMAD R16, R15, R14, R16 ; /* 0x0000000e0f107224 */
/* 0x010fe400078e0210 */
/*0510*/ IMAD.WIDE R14, R4, 0x4, R24 ; /* 0x00000004040e7825 */
/* 0x000fe200078e0218 */
/*0520*/ LDG.E R23, [R12.64+0x24] ; /* 0x000024040c177981 */
/* 0x001f26000c1e1900 */
/*0530*/ IMAD R26, R27, R26, R16 ; /* 0x0000001a1b1a7224 */
/* 0x000fc400078e0210 */
/*0540*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fe200078e020e */
/*0550*/ LDG.E R27, [R12.64+0x28] ; /* 0x000028040c1b7981 */
/* 0x000f28000c1e1900 */
/*0560*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000128000c1e1900 */
/*0570*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000328000c1e1900 */
/*0580*/ LDG.E R15, [R12.64+0x30] ; /* 0x000030040c0f7981 */
/* 0x001f22000c1e1900 */
/*0590*/ IMAD R26, R19, R18, R26 ; /* 0x00000012131a7224 */
/* 0x004fc400078e021a */
/*05a0*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x000fc800078e0210 */
/*05b0*/ IMAD R26, R11, R10, R26 ; /* 0x0000000a0b1a7224 */
/* 0x008fe400078e021a */
/*05c0*/ IMAD.WIDE R10, R4, 0x4, R18 ; /* 0x00000004040a7825 */
/* 0x000fe400078e0212 */
/*05d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a4000c1e1900 */
/*05e0*/ IMAD R24, R20, R21, R26 ; /* 0x0000001514187224 */
/* 0x002fe400078e021a */
/*05f0*/ IMAD.WIDE R20, R4, 0x4, R10 ; /* 0x0000000404147825 */
/* 0x000fe200078e020a */
/*0600*/ LDG.E R26, [R12.64+0x2c] ; /* 0x00002c040c1a7981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002e2000c1e1900 */
/*0620*/ IMAD R28, R29, R28, R24 ; /* 0x0000001c1d1c7224 */
/* 0x020fc600078e0218 */
/*0630*/ LDG.E R19, [R12.64+0x38] ; /* 0x000038040c137981 */
/* 0x001f62000c1e1900 */
/*0640*/ IMAD.WIDE R24, R4, 0x4, R20 ; /* 0x0000000404187825 */
/* 0x000fc600078e0214 */
/*0650*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*0660*/ LDG.E R11, [R12.64+0x34] ; /* 0x000034040c0b7981 */
/* 0x002f62000c1e1900 */
/*0670*/ IMAD.WIDE R16, R4, 0x4, R24 ; /* 0x0000000404107825 */
/* 0x000fc600078e0218 */
/*0680*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000368000c1e1900 */
/*0690*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x001f68000c1e1900 */
/*06a0*/ LDG.E R24, [R12.64+0x3c] ; /* 0x00003c040c187981 */
/* 0x002f62000c1e1900 */
/*06b0*/ IMAD R14, R14, R23, R28 ; /* 0x000000170e0e7224 */
/* 0x010fe200078e021c */
/*06c0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*06d0*/ IMAD R27, R22, R27, R14 ; /* 0x0000001b161b7224 */
/* 0x000fe200078e020e */
/*06e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*06f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0700*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc60007ffe0ff */
/*0710*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0720*/ IMAD R18, R18, R26, R27 ; /* 0x0000001a12127224 */
/* 0x004fc800078e021b */
/*0730*/ IMAD R10, R10, R15, R18 ; /* 0x0000000f0a0a7224 */
/* 0x008fe400078e0212 */
/*0740*/ IMAD.WIDE R26, R4, 0x4, R16 ; /* 0x00000004041a7825 */
/* 0x000fc800078e0210 */
/*0750*/ IMAD R10, R20, R11, R10 ; /* 0x0000000b140a7224 */
/* 0x020fc800078e020a */
/*0760*/ IMAD R10, R29, R19, R10 ; /* 0x000000131d0a7224 */
/* 0x000fc800078e020a */
/*0770*/ IMAD R18, R21, R24, R10 ; /* 0x0000001815127224 */
/* 0x000fe200078e020a */
/*0780*/ @P1 BRA 0x300 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0790*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*07a0*/ @!P1 BRA 0xa30 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*07b0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*07c0*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*07e0*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fca00078e020a */
/*07f0*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000ea2000c1e1900 */
/*0800*/ IMAD.WIDE R22, R4, 0x4, R26 ; /* 0x0000000404167825 */
/* 0x000fc600078e021a */
/*0810*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0820*/ IMAD.WIDE R14, R4.reuse, 0x4, R22 ; /* 0x00000004040e7825 */
/* 0x040fe200078e0216 */
/*0830*/ LDG.E R29, [R10.64+0x8] ; /* 0x000008040a1d7981 */
/* 0x000f28000c1e1900 */
/*0840*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000e2000c1e1900 */
/*0850*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*0860*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000326000c1e1900 */
/*0870*/ IMAD.WIDE R12, R4.reuse, 0x4, R16 ; /* 0x00000004040c7825 */
/* 0x040fe200078e0210 */
/*0880*/ LDG.E R28, [R10.64+0xc] ; /* 0x00000c040a1c7981 */
/* 0x000f68000c1e1900 */
/*0890*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000362000c1e1900 */
/*08a0*/ IMAD.WIDE R20, R4, 0x4, R12 ; /* 0x0000000404147825 */
/* 0x000fc600078e020c */
/*08b0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000328000c1e1900 */
/*08c0*/ LDG.E R23, [R10.64+0x14] ; /* 0x000014040a177981 */
/* 0x001f68000c1e1900 */
/*08d0*/ LDG.E R16, [R10.64+0x18] ; /* 0x000018040a107981 */
/* 0x002f68000c1e1900 */
/*08e0*/ LDG.E R13, [R10.64+0x10] ; /* 0x000010040a0d7981 */
/* 0x000f62000c1e1900 */
/*08f0*/ IMAD R24, R19, R24, R18 ; /* 0x0000001813187224 */
/* 0x004fc400078e0212 */
/*0900*/ IMAD.WIDE R18, R4.reuse, 0x4, R20 ; /* 0x0000000404127825 */
/* 0x040fe400078e0214 */
/*0910*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1900 */
/*0920*/ IMAD.WIDE R26, R4, 0x4, R18 ; /* 0x00000004041a7825 */
/* 0x000fe200078e0212 */
/*0930*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x0000a8000c1e1900 */
/*0940*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001ea8000c1e1900 */
/*0950*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x0000a2000c1e1900 */
/*0960*/ IMAD R22, R22, R25, R24 ; /* 0x0000001916167224 */
/* 0x008fc800078e0218 */
/*0970*/ IMAD R14, R14, R29, R22 ; /* 0x0000001d0e0e7224 */
/* 0x010fc800078e0216 */
/*0980*/ IMAD R14, R17, R28, R14 ; /* 0x0000001c110e7224 */
/* 0x020fc800078e020e */
/*0990*/ IMAD R12, R12, R13, R14 ; /* 0x0000000d0c0c7224 */
/* 0x000fe200078e020e */
/*09a0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*09b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*09c0*/ IMAD.WIDE R26, R4, 0x4, R26 ; /* 0x00000004041a7825 */
/* 0x001fe200078e021a */
/*09d0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a00*/ IMAD R12, R20, R23, R12 ; /* 0x00000017140c7224 */
/* 0x004fc800078e020c */
/*0a10*/ IMAD R12, R15, R16, R12 ; /* 0x000000100f0c7224 */
/* 0x000fc800078e020c */
/*0a20*/ IMAD R18, R18, R19, R12 ; /* 0x0000001312127224 */
/* 0x000fe400078e020c */
/*0a30*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0a40*/ @!P0 BRA 0xbe0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0a50*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0a60*/ IMAD.WIDE R12, R4, 0x4, R26 ; /* 0x00000004040c7825 */
/* 0x000fe200078e021a */
/*0a70*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0a80*/ LDG.E R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000ea8000c1e1900 */
/*0a90*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fc800078e020a */
/*0aa0*/ IMAD.WIDE R14, R4.reuse, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x040fe200078e020c */
/*0ab0*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000ea8000c1e1900 */
/*0ac0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*0ad0*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*0ae0*/ LDG.E R20, [R10.64+0x4] ; /* 0x000004040a147981 */
/* 0x000ee8000c1e1900 */
/*0af0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f28000c1e1900 */
/*0b00*/ LDG.E R21, [R10.64+0x8] ; /* 0x000008040a157981 */
/* 0x000f28000c1e1900 */
/*0b10*/ LDG.E R23, [R10.64+0xc] ; /* 0x00000c040a177981 */
/* 0x000f68000c1e1900 */
/*0b20*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000f62000c1e1900 */
/*0b30*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0b40*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0b50*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0b60*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0b70*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0b80*/ IMAD R19, R27, R19, R18 ; /* 0x000000131b137224 */
/* 0x004fc800078e0212 */
/*0b90*/ IMAD R19, R12, R20, R19 ; /* 0x000000140c137224 */
/* 0x008fe400078e0213 */
/*0ba0*/ IMAD.WIDE R26, R4, 0x4, R16 ; /* 0x00000004041a7825 */
/* 0x000fc800078e0210 */
/*0bb0*/ IMAD R19, R22, R21, R19 ; /* 0x0000001516137224 */
/* 0x010fc800078e0213 */
/*0bc0*/ IMAD R18, R24, R23, R19 ; /* 0x0000001718127224 */
/* 0x020fe200078e0213 */
/*0bd0*/ @P0 BRA 0xa50 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0be0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0bf0*/ @!P0 BRA 0xd00 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0c00*/ IADD3 R3, R3, R6, RZ ; /* 0x0000000603037210 */
/* 0x000fe20007ffe0ff */
/*0c10*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fc800000001ff */
/*0c20*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x000fca00078e0203 */
/*0c30*/ IADD3 R0, -R5, R0, RZ ; /* 0x0000000005007210 */
/* 0x000fe20007ffe1ff */
/*0c40*/ IMAD R5, R6, c[0x0][0x178], R5 ; /* 0x00005e0006057a24 */
/* 0x000fc800078e0205 */
/*0c50*/ IMAD.WIDE R8, R0, R10, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e020a */
/*0c60*/ IMAD.WIDE R10, R5, R10, c[0x0][0x168] ; /* 0x00005a00050a7625 */
/* 0x000fca00078e020a */
/*0c70*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0000a8000c1e1900 */
/*0c80*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0002a2000c1e1900 */
/*0c90*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*0ca0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0cb0*/ IMAD.WIDE R10, R4, 0x4, R10 ; /* 0x00000004040a7825 */
/* 0x001fe200078e020a */
/*0cc0*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x002fc80007f3e0ff */
/*0cd0*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe20000ffe4ff */
/*0ce0*/ IMAD R18, R3, R0, R18 ; /* 0x0000000003127224 */
/* 0x004fcc00078e0212 */
/*0cf0*/ @P0 BRA 0xc70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0d00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0d10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0d20*/ STG.E [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x000fe2000c101904 */
/*0d30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d40*/ BRA 0xd40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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