system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <fstream>
#include <iostream>
#include <iomanip>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <math.h>
using namespace std;
//Execute 1 thread per pixel of output image.
//Each thread handles all four channels of the output pixels
__global__ void encode_per_pixel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//Get pixel index
//Theres two pixels per byte of data
//Thread 2 would be pixel 2 and working on byte 1 nibble 0
//Thread 3 would be pixel 3 and working on byte 1 nibble 1
//Thread 4 would be pixel 4 and working on byte 2 nibble 0
//Thread 5 would be pixel 5 and working on byte 2 nibble 1
int pixel = threadIdx.x + blockDim.x * blockIdx.x;
if(pixel >= 2 * numBytesData)
return;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy. We only need two global accesses this way.
uchar4 outputPixel = d_destImg[pixel];
//Channel 0 (first bit in the nibble)
int offset = (7 - 4 * nibble);
bool bit = (dataByte >> offset) & 1;
outputPixel.x = outputPixel.x & ~1 | bit;
//Channel 1 (2nd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.y = outputPixel.y & ~1 | bit;
//Channel 2 (3rd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.z = outputPixel.z & ~1 | bit;
//Channel 3 (4th bit) This is the alpha channel
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.w = outputPixel.w & ~1 | bit;
d_destImg[pixel] = outputPixel;
}
//1 channel per bit of data
//8 channels per byte of data
//This calls requires two global memory accesses
__global__ void encode_per_channel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//1 thread per bit of data
//Thread 0 works on pixel 0 channel 0 byte 0 nibble 0 bit 0
//Thread 1 works on pixel 0 channel 1 byte 0 nibble 0 bit 1
//Thread 2 works on pixel 0 channel 2 byte 0 nibble 0 bit 2
//Thread 3 works on pixel 0 channel 3 byte 0 nibble 0 bit 3
//Thread 4 works on pixel 1 channel 0 byte 0 nubble 1 bit 0
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if(idx >= 8 * numBytesData)
return;
//Calculate channel (0-4) and pixel (0 - 2*numBytes - 1)
int channel = idx % 4;
int pixel = idx / 4;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData - 1)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy.
uchar4 outputPixel = d_destImg[pixel];
//Get the bit
//Offset should be 7 for channel 0, nibble 0
//Offset should be 0 for channel 3, nibble 1
int offset = (7 - 4 * nibble) - channel;
bool bit = (dataByte >> offset) & 1;
if(channel == 0) {
outputPixel.x = outputPixel.x & ~1 | bit;
} else if(channel == 1){
outputPixel.y = outputPixel.y & ~1 | bit;
} else if(channel == 2){
outputPixel.z = outputPixel.z & ~1 | bit;
} else if(channel == 3){
outputPixel.w = outputPixel.w & ~1 | bit;
}
d_destImg[pixel] = outputPixel;
}
/**
| 10 11 12 15 ; 11 255 12 0 |
| 15 10 13 5 ; 15 14 19 80 | Original image (each set of 4 is 1 pixel).
| 12 14 16 21 ; 14 18 10 16 |
| 11 11 11 11 ; 10 10 10 10 |
and
[ 1001 0110 1111 0000 1010 0101 0100 1100] Data file
=
| 11 10 12 15 ; 10 255 13 0 |
| 15 11 13 5 ; 14 14 18 80 | Encoded image
| 13 14 17 20 ; 14 19 10 17 |
| 11 10 11 11 ; 11 11 10 10 |
To encode the data, we will use the least significant bit approach by
modifying the LSB of each channel of each pixel of th input image. The
LSB will match the corresponding bit of the input data. The data can be
decoded by reading the LSB from the encoded image.
For example, if the channel byte is 0001 1001 (value of 25) and we want to
encode a 1, the byte would remain the same. If we want to encode a 0, the
byte would become 0001 1000 (value of 24).
If the channel byte is 0010 1110 (value of 46), and we want to encode a 1,
then the byte would become 0010 1111 (value of 47). If we want to encode a
0, then the byte would remain the same.
*/
void encode_parallel(const uchar4* const h_sourceImg,
uchar4* const h_destImg,
const char* const h_binData,
int numBytesData,
const size_t numRowsSource, const size_t numColsSource)
{
//Allocate device memory
uchar4* d_destImg;
char* d_binData;
cudaMalloc(&d_destImg, sizeof(uchar4) * numRowsSource * numColsSource);
cudaMalloc(&d_binData, sizeof(char) * numBytesData);
cudaMemcpy(d_destImg, h_sourceImg, sizeof(uchar4) * numRowsSource * numColsSource, cudaMemcpyHostToDevice);
cudaMemcpy(d_binData, h_binData, numBytesData, cudaMemcpyHostToDevice);
//Each thread handles 1 pixel
//This means 1 thread per 4 bits of data (2 threads per byte)
int numThreads = numBytesData * 2.0;
int threadsPerBlock = 1024;
int numBlocks = ceil((float)numThreads / threadsPerBlock);
encode_per_pixel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
//Each thread handles 1 channel of 1 pixel
//This means 1 thread per bit of data (8 threads per byte)
//int numThreads = numBytesData * 8;
//int threadsPerBlock = 1024;
//int numBlocks = ceil((float)numThreads / threadsPerBlock);
//encode_per_channel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
cudaMemcpy(h_destImg, d_destImg, sizeof(uchar4) * numRowsSource * numColsSource, cudaMemcpyDeviceToHost);
//Free memory
cudaFree(d_destImg);
cudaFree(d_binData);
} | #include <fstream>
#include <iostream>
#include <iomanip>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
using namespace std;
//Execute 1 thread per pixel of output image.
//Each thread handles all four channels of the output pixels
__global__ void encode_per_pixel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//Get pixel index
//Theres two pixels per byte of data
//Thread 2 would be pixel 2 and working on byte 1 nibble 0
//Thread 3 would be pixel 3 and working on byte 1 nibble 1
//Thread 4 would be pixel 4 and working on byte 2 nibble 0
//Thread 5 would be pixel 5 and working on byte 2 nibble 1
int pixel = threadIdx.x + blockDim.x * blockIdx.x;
if(pixel >= 2 * numBytesData)
return;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy. We only need two global accesses this way.
uchar4 outputPixel = d_destImg[pixel];
//Channel 0 (first bit in the nibble)
int offset = (7 - 4 * nibble);
bool bit = (dataByte >> offset) & 1;
outputPixel.x = outputPixel.x & ~1 | bit;
//Channel 1 (2nd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.y = outputPixel.y & ~1 | bit;
//Channel 2 (3rd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.z = outputPixel.z & ~1 | bit;
//Channel 3 (4th bit) This is the alpha channel
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.w = outputPixel.w & ~1 | bit;
d_destImg[pixel] = outputPixel;
}
//1 channel per bit of data
//8 channels per byte of data
//This calls requires two global memory accesses
__global__ void encode_per_channel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//1 thread per bit of data
//Thread 0 works on pixel 0 channel 0 byte 0 nibble 0 bit 0
//Thread 1 works on pixel 0 channel 1 byte 0 nibble 0 bit 1
//Thread 2 works on pixel 0 channel 2 byte 0 nibble 0 bit 2
//Thread 3 works on pixel 0 channel 3 byte 0 nibble 0 bit 3
//Thread 4 works on pixel 1 channel 0 byte 0 nubble 1 bit 0
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if(idx >= 8 * numBytesData)
return;
//Calculate channel (0-4) and pixel (0 - 2*numBytes - 1)
int channel = idx % 4;
int pixel = idx / 4;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData - 1)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy.
uchar4 outputPixel = d_destImg[pixel];
//Get the bit
//Offset should be 7 for channel 0, nibble 0
//Offset should be 0 for channel 3, nibble 1
int offset = (7 - 4 * nibble) - channel;
bool bit = (dataByte >> offset) & 1;
if(channel == 0) {
outputPixel.x = outputPixel.x & ~1 | bit;
} else if(channel == 1){
outputPixel.y = outputPixel.y & ~1 | bit;
} else if(channel == 2){
outputPixel.z = outputPixel.z & ~1 | bit;
} else if(channel == 3){
outputPixel.w = outputPixel.w & ~1 | bit;
}
d_destImg[pixel] = outputPixel;
}
/**
| 10 11 12 15 ; 11 255 12 0 |
| 15 10 13 5 ; 15 14 19 80 | Original image (each set of 4 is 1 pixel).
| 12 14 16 21 ; 14 18 10 16 |
| 11 11 11 11 ; 10 10 10 10 |
and
[ 1001 0110 1111 0000 1010 0101 0100 1100] Data file
=
| 11 10 12 15 ; 10 255 13 0 |
| 15 11 13 5 ; 14 14 18 80 | Encoded image
| 13 14 17 20 ; 14 19 10 17 |
| 11 10 11 11 ; 11 11 10 10 |
To encode the data, we will use the least significant bit approach by
modifying the LSB of each channel of each pixel of th input image. The
LSB will match the corresponding bit of the input data. The data can be
decoded by reading the LSB from the encoded image.
For example, if the channel byte is 0001 1001 (value of 25) and we want to
encode a 1, the byte would remain the same. If we want to encode a 0, the
byte would become 0001 1000 (value of 24).
If the channel byte is 0010 1110 (value of 46), and we want to encode a 1,
then the byte would become 0010 1111 (value of 47). If we want to encode a
0, then the byte would remain the same.
*/
void encode_parallel(const uchar4* const h_sourceImg,
uchar4* const h_destImg,
const char* const h_binData,
int numBytesData,
const size_t numRowsSource, const size_t numColsSource)
{
//Allocate device memory
uchar4* d_destImg;
char* d_binData;
hipMalloc(&d_destImg, sizeof(uchar4) * numRowsSource * numColsSource);
hipMalloc(&d_binData, sizeof(char) * numBytesData);
hipMemcpy(d_destImg, h_sourceImg, sizeof(uchar4) * numRowsSource * numColsSource, hipMemcpyHostToDevice);
hipMemcpy(d_binData, h_binData, numBytesData, hipMemcpyHostToDevice);
//Each thread handles 1 pixel
//This means 1 thread per 4 bits of data (2 threads per byte)
int numThreads = numBytesData * 2.0;
int threadsPerBlock = 1024;
int numBlocks = ceil((float)numThreads / threadsPerBlock);
encode_per_pixel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
//Each thread handles 1 channel of 1 pixel
//This means 1 thread per bit of data (8 threads per byte)
//int numThreads = numBytesData * 8;
//int threadsPerBlock = 1024;
//int numBlocks = ceil((float)numThreads / threadsPerBlock);
//encode_per_channel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
hipMemcpy(h_destImg, d_destImg, sizeof(uchar4) * numRowsSource * numColsSource, hipMemcpyDeviceToHost);
//Free memory
hipFree(d_destImg);
hipFree(d_binData);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <fstream>
#include <iostream>
#include <iomanip>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
using namespace std;
//Execute 1 thread per pixel of output image.
//Each thread handles all four channels of the output pixels
__global__ void encode_per_pixel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//Get pixel index
//Theres two pixels per byte of data
//Thread 2 would be pixel 2 and working on byte 1 nibble 0
//Thread 3 would be pixel 3 and working on byte 1 nibble 1
//Thread 4 would be pixel 4 and working on byte 2 nibble 0
//Thread 5 would be pixel 5 and working on byte 2 nibble 1
int pixel = threadIdx.x + blockDim.x * blockIdx.x;
if(pixel >= 2 * numBytesData)
return;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy. We only need two global accesses this way.
uchar4 outputPixel = d_destImg[pixel];
//Channel 0 (first bit in the nibble)
int offset = (7 - 4 * nibble);
bool bit = (dataByte >> offset) & 1;
outputPixel.x = outputPixel.x & ~1 | bit;
//Channel 1 (2nd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.y = outputPixel.y & ~1 | bit;
//Channel 2 (3rd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.z = outputPixel.z & ~1 | bit;
//Channel 3 (4th bit) This is the alpha channel
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.w = outputPixel.w & ~1 | bit;
d_destImg[pixel] = outputPixel;
}
//1 channel per bit of data
//8 channels per byte of data
//This calls requires two global memory accesses
__global__ void encode_per_channel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//1 thread per bit of data
//Thread 0 works on pixel 0 channel 0 byte 0 nibble 0 bit 0
//Thread 1 works on pixel 0 channel 1 byte 0 nibble 0 bit 1
//Thread 2 works on pixel 0 channel 2 byte 0 nibble 0 bit 2
//Thread 3 works on pixel 0 channel 3 byte 0 nibble 0 bit 3
//Thread 4 works on pixel 1 channel 0 byte 0 nubble 1 bit 0
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if(idx >= 8 * numBytesData)
return;
//Calculate channel (0-4) and pixel (0 - 2*numBytes - 1)
int channel = idx % 4;
int pixel = idx / 4;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData - 1)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy.
uchar4 outputPixel = d_destImg[pixel];
//Get the bit
//Offset should be 7 for channel 0, nibble 0
//Offset should be 0 for channel 3, nibble 1
int offset = (7 - 4 * nibble) - channel;
bool bit = (dataByte >> offset) & 1;
if(channel == 0) {
outputPixel.x = outputPixel.x & ~1 | bit;
} else if(channel == 1){
outputPixel.y = outputPixel.y & ~1 | bit;
} else if(channel == 2){
outputPixel.z = outputPixel.z & ~1 | bit;
} else if(channel == 3){
outputPixel.w = outputPixel.w & ~1 | bit;
}
d_destImg[pixel] = outputPixel;
}
/**
| 10 11 12 15 ; 11 255 12 0 |
| 15 10 13 5 ; 15 14 19 80 | Original image (each set of 4 is 1 pixel).
| 12 14 16 21 ; 14 18 10 16 |
| 11 11 11 11 ; 10 10 10 10 |
and
[ 1001 0110 1111 0000 1010 0101 0100 1100] Data file
=
| 11 10 12 15 ; 10 255 13 0 |
| 15 11 13 5 ; 14 14 18 80 | Encoded image
| 13 14 17 20 ; 14 19 10 17 |
| 11 10 11 11 ; 11 11 10 10 |
To encode the data, we will use the least significant bit approach by
modifying the LSB of each channel of each pixel of th input image. The
LSB will match the corresponding bit of the input data. The data can be
decoded by reading the LSB from the encoded image.
For example, if the channel byte is 0001 1001 (value of 25) and we want to
encode a 1, the byte would remain the same. If we want to encode a 0, the
byte would become 0001 1000 (value of 24).
If the channel byte is 0010 1110 (value of 46), and we want to encode a 1,
then the byte would become 0010 1111 (value of 47). If we want to encode a
0, then the byte would remain the same.
*/
void encode_parallel(const uchar4* const h_sourceImg,
uchar4* const h_destImg,
const char* const h_binData,
int numBytesData,
const size_t numRowsSource, const size_t numColsSource)
{
//Allocate device memory
uchar4* d_destImg;
char* d_binData;
hipMalloc(&d_destImg, sizeof(uchar4) * numRowsSource * numColsSource);
hipMalloc(&d_binData, sizeof(char) * numBytesData);
hipMemcpy(d_destImg, h_sourceImg, sizeof(uchar4) * numRowsSource * numColsSource, hipMemcpyHostToDevice);
hipMemcpy(d_binData, h_binData, numBytesData, hipMemcpyHostToDevice);
//Each thread handles 1 pixel
//This means 1 thread per 4 bits of data (2 threads per byte)
int numThreads = numBytesData * 2.0;
int threadsPerBlock = 1024;
int numBlocks = ceil((float)numThreads / threadsPerBlock);
encode_per_pixel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
//Each thread handles 1 channel of 1 pixel
//This means 1 thread per bit of data (8 threads per byte)
//int numThreads = numBytesData * 8;
//int threadsPerBlock = 1024;
//int numBlocks = ceil((float)numThreads / threadsPerBlock);
//encode_per_channel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
hipMemcpy(h_destImg, d_destImg, sizeof(uchar4) * numRowsSource * numColsSource, hipMemcpyDeviceToHost);
//Free memory
hipFree(d_destImg);
hipFree(d_binData);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.globl _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 8
.type _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci,@function
_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_lshl_b32 s2, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshrrev_b32_e32 v0, 31, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v1, v0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 1, v0
v_and_b32_e32 v0, 0x3ffffffe, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v1, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_lshlrev_b32_e32 v0, 2, v0
global_load_u8 v6, v[2:3], off
global_load_i8 v4, v[4:5], off
s_clause 0x2
global_load_u8 v5, v[2:3], off offset:1
global_load_u8 v7, v[2:3], off offset:2
global_load_u8 v8, v[2:3], off offset:3
v_sub_nc_u32_e32 v1, 7, v0
v_sub_nc_u32_e32 v9, 6, v0
v_sub_nc_u32_e32 v10, 5, v0
v_sub_nc_u32_e32 v0, 4, v0
s_waitcnt vmcnt(4)
v_and_b32_e32 v6, 0xfe, v6
s_waitcnt vmcnt(3)
v_lshrrev_b32_e32 v1, v1, v4
v_lshrrev_b32_e32 v9, v9, v4
v_lshrrev_b32_e32 v10, v10, v4
v_lshrrev_b32_e32 v0, v0, v4
s_waitcnt vmcnt(2)
v_and_b32_e32 v5, 0xfe, v5
v_and_b32_e32 v1, 1, v1
s_waitcnt vmcnt(0)
v_and_b32_e32 v4, 0xfe, v8
v_and_b32_e32 v8, 1, v9
v_and_b32_e32 v7, 0xfe, v7
v_and_b32_e32 v9, 1, v10
v_and_b32_e32 v0, 1, v0
v_or_b32_e32 v1, v1, v6
v_or_b32_e32 v5, v8, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_or_b32_e32 v6, v9, v7
v_or_b32_e32 v0, v4, v0
s_clause 0x3
global_store_b8 v[2:3], v1, off
global_store_b8 v[2:3], v5, off offset:1
global_store_b8 v[2:3], v6, off offset:2
global_store_b8 v[2:3], v0, off offset:3
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end0-_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.globl _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 8
.type _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci,@function
_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_lshl_b32 s2, s3, 3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_18
v_ashrrev_i32_e32 v0, 31, v2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v1, 29, v0
v_lshrrev_b32_e32 v0, 30, v0
v_add_nc_u32_e32 v7, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v2, v0
v_ashrrev_i32_e32 v1, 3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v0, 2, v8
v_and_b32_e32 v7, -8, v7
v_and_b32_e32 v8, -4, v8
v_ashrrev_i32_e32 v4, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
v_ashrrev_i32_e32 v1, 31, v0
v_sub_nc_u32_e32 v7, v7, v2
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_sub_nc_u32_e32 v2, v2, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_nc_u32_e32 v7, 7, v7
global_load_i8 v9, v[3:4], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x3
global_load_u8 v6, v[0:1], off
global_load_u8 v4, v[0:1], off offset:1
global_load_u8 v5, v[0:1], off offset:2
global_load_u8 v3, v[0:1], off offset:3
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(4)
v_lshrrev_b32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v7, 1, v7
v_cmp_eq_u32_e64 s0, 1, v7
v_cmpx_lt_i32_e32 1, v2
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB1_9
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 2, v2
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB1_6
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 3, v2
s_cbranch_execz .LBB1_5
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, -2, v3
v_cndmask_b32_e64 v3, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v3, v2, v3
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s3
.LBB1_6:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB1_8
s_waitcnt vmcnt(1)
v_and_b32_e32 v2, -2, v5
v_cndmask_b32_e64 v5, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v5, v2, v5
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s2
.LBB1_9:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB1_17
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v2
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB1_12
s_waitcnt vmcnt(2)
v_and_b32_e32 v2, -2, v4
v_cndmask_b32_e64 v4, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v4, v2, v4
.LBB1_12:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB1_16
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB1_15
s_waitcnt vmcnt(3)
v_and_b32_e32 v2, -2, v6
v_cndmask_b32_e64 v6, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v6, v2, v6
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s3
.LBB1_16:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
.LBB1_17:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt vmcnt(3)
global_store_b8 v[0:1], v6, off
s_waitcnt vmcnt(2)
global_store_b8 v[0:1], v4, off offset:1
s_waitcnt vmcnt(1)
global_store_b8 v[0:1], v5, off offset:2
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v3, off offset:3
.LBB1_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end1-_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <fstream>
#include <iostream>
#include <iomanip>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <math.h>
using namespace std;
//Execute 1 thread per pixel of output image.
//Each thread handles all four channels of the output pixels
__global__ void encode_per_pixel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//Get pixel index
//Theres two pixels per byte of data
//Thread 2 would be pixel 2 and working on byte 1 nibble 0
//Thread 3 would be pixel 3 and working on byte 1 nibble 1
//Thread 4 would be pixel 4 and working on byte 2 nibble 0
//Thread 5 would be pixel 5 and working on byte 2 nibble 1
int pixel = threadIdx.x + blockDim.x * blockIdx.x;
if(pixel >= 2 * numBytesData)
return;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy. We only need two global accesses this way.
uchar4 outputPixel = d_destImg[pixel];
//Channel 0 (first bit in the nibble)
int offset = (7 - 4 * nibble);
bool bit = (dataByte >> offset) & 1;
outputPixel.x = outputPixel.x & ~1 | bit;
//Channel 1 (2nd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.y = outputPixel.y & ~1 | bit;
//Channel 2 (3rd bit)
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.z = outputPixel.z & ~1 | bit;
//Channel 3 (4th bit) This is the alpha channel
offset -= 1;
bit = (dataByte >> offset) & 1;
outputPixel.w = outputPixel.w & ~1 | bit;
d_destImg[pixel] = outputPixel;
}
//1 channel per bit of data
//8 channels per byte of data
//This calls requires two global memory accesses
__global__ void encode_per_channel_kernel(uchar4* const d_destImg,
const char* const d_binData,
int numBytesData)
{
//1 thread per bit of data
//Thread 0 works on pixel 0 channel 0 byte 0 nibble 0 bit 0
//Thread 1 works on pixel 0 channel 1 byte 0 nibble 0 bit 1
//Thread 2 works on pixel 0 channel 2 byte 0 nibble 0 bit 2
//Thread 3 works on pixel 0 channel 3 byte 0 nibble 0 bit 3
//Thread 4 works on pixel 1 channel 0 byte 0 nubble 1 bit 0
int idx = threadIdx.x + blockDim.x * blockIdx.x;
if(idx >= 8 * numBytesData)
return;
//Calculate channel (0-4) and pixel (0 - 2*numBytes - 1)
int channel = idx % 4;
int pixel = idx / 4;
//Calculate which nibble (0 or 1) in the byte
//and which byte (0 to numBytesData - 1)
int byteIndex = pixel / 2;
int nibble = pixel % 2;
char dataByte = d_binData[byteIndex];
//Let's work with a local copy.
uchar4 outputPixel = d_destImg[pixel];
//Get the bit
//Offset should be 7 for channel 0, nibble 0
//Offset should be 0 for channel 3, nibble 1
int offset = (7 - 4 * nibble) - channel;
bool bit = (dataByte >> offset) & 1;
if(channel == 0) {
outputPixel.x = outputPixel.x & ~1 | bit;
} else if(channel == 1){
outputPixel.y = outputPixel.y & ~1 | bit;
} else if(channel == 2){
outputPixel.z = outputPixel.z & ~1 | bit;
} else if(channel == 3){
outputPixel.w = outputPixel.w & ~1 | bit;
}
d_destImg[pixel] = outputPixel;
}
/**
| 10 11 12 15 ; 11 255 12 0 |
| 15 10 13 5 ; 15 14 19 80 | Original image (each set of 4 is 1 pixel).
| 12 14 16 21 ; 14 18 10 16 |
| 11 11 11 11 ; 10 10 10 10 |
and
[ 1001 0110 1111 0000 1010 0101 0100 1100] Data file
=
| 11 10 12 15 ; 10 255 13 0 |
| 15 11 13 5 ; 14 14 18 80 | Encoded image
| 13 14 17 20 ; 14 19 10 17 |
| 11 10 11 11 ; 11 11 10 10 |
To encode the data, we will use the least significant bit approach by
modifying the LSB of each channel of each pixel of th input image. The
LSB will match the corresponding bit of the input data. The data can be
decoded by reading the LSB from the encoded image.
For example, if the channel byte is 0001 1001 (value of 25) and we want to
encode a 1, the byte would remain the same. If we want to encode a 0, the
byte would become 0001 1000 (value of 24).
If the channel byte is 0010 1110 (value of 46), and we want to encode a 1,
then the byte would become 0010 1111 (value of 47). If we want to encode a
0, then the byte would remain the same.
*/
void encode_parallel(const uchar4* const h_sourceImg,
uchar4* const h_destImg,
const char* const h_binData,
int numBytesData,
const size_t numRowsSource, const size_t numColsSource)
{
//Allocate device memory
uchar4* d_destImg;
char* d_binData;
hipMalloc(&d_destImg, sizeof(uchar4) * numRowsSource * numColsSource);
hipMalloc(&d_binData, sizeof(char) * numBytesData);
hipMemcpy(d_destImg, h_sourceImg, sizeof(uchar4) * numRowsSource * numColsSource, hipMemcpyHostToDevice);
hipMemcpy(d_binData, h_binData, numBytesData, hipMemcpyHostToDevice);
//Each thread handles 1 pixel
//This means 1 thread per 4 bits of data (2 threads per byte)
int numThreads = numBytesData * 2.0;
int threadsPerBlock = 1024;
int numBlocks = ceil((float)numThreads / threadsPerBlock);
encode_per_pixel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
//Each thread handles 1 channel of 1 pixel
//This means 1 thread per bit of data (8 threads per byte)
//int numThreads = numBytesData * 8;
//int threadsPerBlock = 1024;
//int numBlocks = ceil((float)numThreads / threadsPerBlock);
//encode_per_channel_kernel<<<numBlocks, threadsPerBlock>>>(d_destImg, d_binData, numBytesData);
hipMemcpy(h_destImg, d_destImg, sizeof(uchar4) * numRowsSource * numColsSource, hipMemcpyDeviceToHost);
//Free memory
hipFree(d_destImg);
hipFree(d_binData);
} | .text
.file "encode.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci # -- Begin function _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 4, 0x90
.type _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci,@function
_Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci: # @_Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end0-_Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.cfi_endproc
# -- End function
.globl _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci # -- Begin function _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 4, 0x90
.type _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci,@function
_Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci: # @_Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end1-_Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm
.LCPI2_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm
.p2align 4, 0x90
.type _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm,@function
_Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm: # @_Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %r12
imulq %r9, %rbx
shlq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq %ebp, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
addl %r13d, %r13d
cvtsi2ss %r13d, %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm, .Lfunc_end2-_Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci,@object # @_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.section .rodata,"a",@progbits
.globl _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 3, 0x0
_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci:
.quad _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.size _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, 8
.type _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci,@object # @_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.globl _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 3, 0x0
_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci:
.quad _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.size _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci"
.size .L__unnamed_1, 57
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci"
.size .L__unnamed_2, 59
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.addrsig_sym _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.addrsig_sym _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25encode_per_channel_kernelP6uchar4PKci
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.L.U32 UR4, UR4, 0x3, URZ ; /* 0x0000000304047899 */
/* 0x000fe2000800063f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ LEA.HI R2, R3.reuse, R0.reuse, RZ, 0x3 ; /* 0x0000000003027211 */
/* 0x0c0fe400078f18ff */
/*00b0*/ LEA.HI R6, R3, R0, RZ, 0x2 ; /* 0x0000000003067211 */
/* 0x000fe400078f10ff */
/*00c0*/ SHF.R.S32.HI R5, RZ, 0x3, R2 ; /* 0x00000003ff057819 */
/* 0x000fe20000011402 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*00e0*/ SHF.R.S32.HI R7, RZ, 0x2, R6 ; /* 0x00000002ff077819 */
/* 0x000fe40000011406 */
/*00f0*/ IADD3 R4, P0, R5, c[0x0][0x168], RZ ; /* 0x00005a0005047a10 */
/* 0x000fc60007f1e0ff */
/*0100*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fe200078e0202 */
/*0110*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0005057a11 */
/* 0x000fc800000f0eff */
/*0120*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E.S8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0000e2000c1e1300 */
/*0140*/ LEA.HI R8, R6.reuse, R7, RZ, 0x1 ; /* 0x0000000706087211 */
/* 0x040fe200078f08ff */
/*0150*/ BSSY B0, 0x3c0 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*0160*/ LOP3.LUT R9, R6, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc06097812 */
/* 0x000fe400078ec0ff */
/*0170*/ LOP3.LUT R8, R8, 0x3ffffffe, RZ, 0xc0, !PT ; /* 0x3ffffffe08087812 */
/* 0x000fc600078ec0ff */
/*0180*/ IMAD.IADD R9, R0, 0x1, -R9 ; /* 0x0000000100097824 */
/* 0x000fe400078e0a09 */
/*0190*/ IMAD.IADD R8, R7, 0x1, -R8 ; /* 0x0000000107087824 */
/* 0x000fe400078e0a08 */
/*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3 R7, -R9.reuse, 0x7, RZ ; /* 0x0000000709077810 */
/* 0x040fe40007ffe1ff */
/*01c0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f05270 */
/*01d0*/ IMAD R7, R8, -0x4, R7 ; /* 0xfffffffc08077824 */
/* 0x000fca00078e0207 */
/*01e0*/ SHF.L.U32 R7, R0, R7, RZ ; /* 0x0000000700077219 */
/* 0x000fe400000006ff */
/*01f0*/ PRMT R0, R10.reuse, 0x7770, RZ ; /* 0x000077700a007816 */
/* 0x044fe400000000ff */
/*0200*/ PRMT R5, R10.reuse, 0x7772, RZ ; /* 0x000077720a057816 */
/* 0x041fe400000000ff */
/*0210*/ LOP3.LUT R7, R7, R4, RZ, 0xc0, !PT ; /* 0x0000000407077212 */
/* 0x008fe400078ec0ff */
/*0220*/ PRMT R4, R10.reuse, 0x7771, RZ ; /* 0x000077710a047816 */
/* 0x040fe400000000ff */
/*0230*/ PRMT R6, R10, 0x7773, RZ ; /* 0x000077730a067816 */
/* 0x000fc400000000ff */
/*0240*/ PRMT R11, R4, 0x7610, R11 ; /* 0x00007610040b7816 */
/* 0x000fe2000000000b */
/*0250*/ @!P0 BRA 0x380 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f05270 */
/*0270*/ @!P0 BRA 0x340 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0280*/ ISETP.NE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fda0003f05270 */
/*0290*/ @!P0 BRA 0x300 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*02a0*/ ISETP.NE.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fda0003f05270 */
/*02b0*/ @P0 BRA 0x3b0 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*02d0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*02e0*/ LOP3.LUT R6, R7, 0xfffe, R6, 0xf8, !PT ; /* 0x0000fffe07067812 */
/* 0x000fe200078ef806 */
/*02f0*/ BRA 0x3b0 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0300*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*0310*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0320*/ LOP3.LUT R5, R4, 0xfffe, R5, 0xf8, !PT ; /* 0x0000fffe04057812 */
/* 0x000fe200078ef805 */
/*0330*/ BRA 0x3b0 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*0350*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0360*/ LOP3.LUT R11, R4, 0xfffe, R11, 0xf8, !PT ; /* 0x0000fffe040b7812 */
/* 0x000fe200078ef80b */
/*0370*/ BRA 0x3b0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0380*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f05270 */
/*0390*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*03a0*/ LOP3.LUT R0, R7, 0xfffe, R0, 0xf8, !PT ; /* 0x0000fffe07007812 */
/* 0x000fe400078ef800 */
/*03b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03c0*/ PRMT R0, R11, 0x7604, R0 ; /* 0x000076040b007816 */
/* 0x000fc80000000000 */
/*03d0*/ PRMT R5, R5, 0x7054, R0 ; /* 0x0000705405057816 */
/* 0x000fc80000000000 */
/*03e0*/ PRMT R5, R6, 0x654, R5 ; /* 0x0000065406057816 */
/* 0x000fca0000000005 */
/*03f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0400*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0410*/ BRA 0x410; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z23encode_per_pixel_kernelP6uchar4PKci
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LEA.HI R6, R0, R0, RZ, 0x1 ; /* 0x0000000000067211 */
/* 0x000fe200078f08ff */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ SHF.R.S32.HI R2, RZ, 0x1, R6 ; /* 0x00000001ff027819 */
/* 0x000fc80000011406 */
/*00c0*/ IADD3 R4, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R5, R2, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0002057a11 */
/* 0x000fe200000f0eff */
/*00e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0203 */
/*00f0*/ LDG.E.S8 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0000a8000c1e1300 */
/*0100*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ee2000c1e1900 */
/*0110*/ LOP3.LUT R7, R6, 0x3ffffffe, RZ, 0xc0, !PT ; /* 0x3ffffffe06077812 */
/* 0x000fe200078ec0ff */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.IADD R7, R0, 0x1, -R7 ; /* 0x0000000100077824 */
/* 0x000fe400078e0a07 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, -0x4 ; /* 0xfffffffcff007424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD R7, R7, R0, 0x7 ; /* 0x0000000707077424 */
/* 0x000fca00078e0200 */
/*0160*/ IADD3 R0, R7.reuse, -0x1, RZ ; /* 0xffffffff07007810 */
/* 0x040fe40007ffe0ff */
/*0170*/ IADD3 R6, R7.reuse, -0x2, RZ ; /* 0xfffffffe07067810 */
/* 0x040fe40007ffe0ff */
/*0180*/ IADD3 R10, R7, -0x3, RZ ; /* 0xfffffffd070a7810 */
/* 0x000fe40007ffe0ff */
/*0190*/ SHF.L.U32 R7, R11.reuse, R7, RZ ; /* 0x000000070b077219 */
/* 0x040fe400000006ff */
/*01a0*/ SHF.L.U32 R5, R11.reuse, R0, RZ ; /* 0x000000000b057219 */
/* 0x041fe400000006ff */
/*01b0*/ SHF.L.U32 R9, R11, R6, RZ ; /* 0x000000060b097219 */
/* 0x000fc400000006ff */
/*01c0*/ SHF.L.U32 R11, R11, R10, RZ ; /* 0x0000000a0b0b7219 */
/* 0x000fe400000006ff */
/*01d0*/ LOP3.LUT P0, RZ, R7, R8.reuse, RZ, 0xc0, !PT ; /* 0x0000000807ff7212 */
/* 0x084fe4000780c0ff */
/*01e0*/ LOP3.LUT P1, RZ, R5, R8.reuse, RZ, 0xc0, !PT ; /* 0x0000000805ff7212 */
/* 0x080fe4000782c0ff */
/*01f0*/ LOP3.LUT P2, RZ, R9, R8, RZ, 0xc0, !PT ; /* 0x0000000809ff7212 */
/* 0x000fe4000784c0ff */
/*0200*/ PRMT R0, R12.reuse, 0x7770, RZ ; /* 0x000077700c007816 */
/* 0x048fe400000000ff */
/*0210*/ PRMT R4, R12, 0x7771, RZ ; /* 0x000077710c047816 */
/* 0x000fc400000000ff */
/*0220*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fe40004000000 */
/*0230*/ SEL R9, RZ, 0x1, !P1 ; /* 0x00000001ff097807 */
/* 0x000fe40004800000 */
/*0240*/ PRMT R5, R12, 0x7772, RZ ; /* 0x000077720c057816 */
/* 0x000fe400000000ff */
/*0250*/ SEL R6, RZ, 0x1, !P2 ; /* 0x00000001ff067807 */
/* 0x000fe40005000000 */
/*0260*/ LOP3.LUT P0, RZ, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080bff7212 */
/* 0x000fe4000780c0ff */
/*0270*/ LOP3.LUT R7, R7, 0xfffe, R0, 0xf8, !PT ; /* 0x0000fffe07077812 */
/* 0x000fc400078ef800 */
/*0280*/ LOP3.LUT R4, R9, 0xfffe, R4, 0xf8, !PT ; /* 0x0000fffe09047812 */
/* 0x000fe400078ef804 */
/*0290*/ LOP3.LUT R6, R6, 0xfffe, R5, 0xf8, !PT ; /* 0x0000fffe06067812 */
/* 0x000fe400078ef805 */
/*02a0*/ PRMT R0, R12, 0x7773, RZ ; /* 0x000077730c007816 */
/* 0x000fe400000000ff */
/*02b0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fe40004000000 */
/*02c0*/ PRMT R7, R4, 0x7604, R7 ; /* 0x0000760404077816 */
/* 0x000fe40000000007 */
/*02d0*/ LOP3.LUT R0, R5, 0xfffe, R0, 0xf8, !PT ; /* 0x0000fffe05007812 */
/* 0x000fc400078ef800 */
/*02e0*/ PRMT R7, R6, 0x7054, R7 ; /* 0x0000705406077816 */
/* 0x000fc80000000007 */
/*02f0*/ PRMT R7, R0, 0x654, R7 ; /* 0x0000065400077816 */
/* 0x000fca0000000007 */
/*0300*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.globl _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 8
.type _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci,@function
_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_lshl_b32 s2, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshrrev_b32_e32 v0, 31, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v1, v0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 1, v0
v_and_b32_e32 v0, 0x3ffffffe, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v1, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_lshlrev_b32_e32 v0, 2, v0
global_load_u8 v6, v[2:3], off
global_load_i8 v4, v[4:5], off
s_clause 0x2
global_load_u8 v5, v[2:3], off offset:1
global_load_u8 v7, v[2:3], off offset:2
global_load_u8 v8, v[2:3], off offset:3
v_sub_nc_u32_e32 v1, 7, v0
v_sub_nc_u32_e32 v9, 6, v0
v_sub_nc_u32_e32 v10, 5, v0
v_sub_nc_u32_e32 v0, 4, v0
s_waitcnt vmcnt(4)
v_and_b32_e32 v6, 0xfe, v6
s_waitcnt vmcnt(3)
v_lshrrev_b32_e32 v1, v1, v4
v_lshrrev_b32_e32 v9, v9, v4
v_lshrrev_b32_e32 v10, v10, v4
v_lshrrev_b32_e32 v0, v0, v4
s_waitcnt vmcnt(2)
v_and_b32_e32 v5, 0xfe, v5
v_and_b32_e32 v1, 1, v1
s_waitcnt vmcnt(0)
v_and_b32_e32 v4, 0xfe, v8
v_and_b32_e32 v8, 1, v9
v_and_b32_e32 v7, 0xfe, v7
v_and_b32_e32 v9, 1, v10
v_and_b32_e32 v0, 1, v0
v_or_b32_e32 v1, v1, v6
v_or_b32_e32 v5, v8, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_or_b32_e32 v6, v9, v7
v_or_b32_e32 v0, v4, v0
s_clause 0x3
global_store_b8 v[2:3], v1, off
global_store_b8 v[2:3], v5, off offset:1
global_store_b8 v[2:3], v6, off offset:2
global_store_b8 v[2:3], v0, off offset:3
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end0-_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.globl _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 8
.type _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci,@function
_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_lshl_b32 s2, s3, 3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_18
v_ashrrev_i32_e32 v0, 31, v2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v1, 29, v0
v_lshrrev_b32_e32 v0, 30, v0
v_add_nc_u32_e32 v7, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v2, v0
v_ashrrev_i32_e32 v1, 3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v0, 2, v8
v_and_b32_e32 v7, -8, v7
v_and_b32_e32 v8, -4, v8
v_ashrrev_i32_e32 v4, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
v_ashrrev_i32_e32 v1, 31, v0
v_sub_nc_u32_e32 v7, v7, v2
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_sub_nc_u32_e32 v2, v2, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_nc_u32_e32 v7, 7, v7
global_load_i8 v9, v[3:4], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x3
global_load_u8 v6, v[0:1], off
global_load_u8 v4, v[0:1], off offset:1
global_load_u8 v5, v[0:1], off offset:2
global_load_u8 v3, v[0:1], off offset:3
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(4)
v_lshrrev_b32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v7, 1, v7
v_cmp_eq_u32_e64 s0, 1, v7
v_cmpx_lt_i32_e32 1, v2
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB1_9
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 2, v2
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB1_6
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 3, v2
s_cbranch_execz .LBB1_5
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, -2, v3
v_cndmask_b32_e64 v3, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v3, v2, v3
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s3
.LBB1_6:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB1_8
s_waitcnt vmcnt(1)
v_and_b32_e32 v2, -2, v5
v_cndmask_b32_e64 v5, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v5, v2, v5
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s2
.LBB1_9:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB1_17
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v2
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB1_12
s_waitcnt vmcnt(2)
v_and_b32_e32 v2, -2, v4
v_cndmask_b32_e64 v4, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v4, v2, v4
.LBB1_12:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB1_16
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB1_15
s_waitcnt vmcnt(3)
v_and_b32_e32 v2, -2, v6
v_cndmask_b32_e64 v6, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v6, v2, v6
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s3
.LBB1_16:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
.LBB1_17:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt vmcnt(3)
global_store_b8 v[0:1], v6, off
s_waitcnt vmcnt(2)
global_store_b8 v[0:1], v4, off offset:1
s_waitcnt vmcnt(1)
global_store_b8 v[0:1], v5, off offset:2
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v3, off offset:3
.LBB1_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end1-_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a59bf_00000000-6_encode.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4042:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4042:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci
.type _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci, @function
_Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci:
.LFB4064:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23encode_per_pixel_kernelP6uchar4PKci(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4064:
.size _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci, .-_Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci
.globl _Z23encode_per_pixel_kernelP6uchar4PKci
.type _Z23encode_per_pixel_kernelP6uchar4PKci, @function
_Z23encode_per_pixel_kernelP6uchar4PKci:
.LFB4065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4065:
.size _Z23encode_per_pixel_kernelP6uchar4PKci, .-_Z23encode_per_pixel_kernelP6uchar4PKci
.globl _Z15encode_parallelPK6uchar4PS_PKcimm
.type _Z15encode_parallelPK6uchar4PS_PKcimm, @function
_Z15encode_parallelPK6uchar4PS_PKcimm:
.LFB4039:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
imulq %r9, %r8
leaq 0(,%r8,4), %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movslq %ebp, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
addsd %xmm0, %xmm0
cvttsd2sil %xmm0, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z53__device_stub__Z23encode_per_pixel_kernelP6uchar4PKciP6uchar4PKci
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4039:
.size _Z15encode_parallelPK6uchar4PS_PKcimm, .-_Z15encode_parallelPK6uchar4PS_PKcimm
.globl _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci
.type _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci, @function
_Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci:
.LFB4066:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25encode_per_channel_kernelP6uchar4PKci(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4066:
.size _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci, .-_Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci
.globl _Z25encode_per_channel_kernelP6uchar4PKci
.type _Z25encode_per_channel_kernelP6uchar4PKci, @function
_Z25encode_per_channel_kernelP6uchar4PKci:
.LFB4067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z25encode_per_channel_kernelP6uchar4PKciP6uchar4PKci
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4067:
.size _Z25encode_per_channel_kernelP6uchar4PKci, .-_Z25encode_per_channel_kernelP6uchar4PKci
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z25encode_per_channel_kernelP6uchar4PKci"
.align 8
.LC6:
.string "_Z23encode_per_pixel_kernelP6uchar4PKci"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4069:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z25encode_per_channel_kernelP6uchar4PKci(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z23encode_per_pixel_kernelP6uchar4PKci(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4069:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 981467136
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "encode.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci # -- Begin function _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 4, 0x90
.type _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci,@function
_Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci: # @_Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end0-_Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.cfi_endproc
# -- End function
.globl _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci # -- Begin function _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 4, 0x90
.type _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci,@function
_Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci: # @_Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, .Lfunc_end1-_Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm
.LCPI2_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm
.p2align 4, 0x90
.type _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm,@function
_Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm: # @_Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %r12
imulq %r9, %rbx
shlq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq %ebp, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
addl %r13d, %r13d
cvtsi2ss %r13d, %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm, .Lfunc_end2-_Z15encode_parallelPK15HIP_vector_typeIhLj4EEPS0_PKcimm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci,@object # @_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.section .rodata,"a",@progbits
.globl _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 3, 0x0
_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci:
.quad _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.size _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci, 8
.type _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci,@object # @_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.globl _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.p2align 3, 0x0
_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci:
.quad _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.size _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci"
.size .L__unnamed_1, 57
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci"
.size .L__unnamed_2, 59
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.addrsig_sym _Z40__device_stub__encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23encode_per_pixel_kernelP15HIP_vector_typeIhLj4EEPKci
.addrsig_sym _Z25encode_per_channel_kernelP15HIP_vector_typeIhLj4EEPKci
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#define MAX_TESS_POINTS 32
struct BezierLine{
float2 CP[3];//control points for the line
float2 vertexPos[MAX_TESS_POINTS];//Vertex position array to tessellate into
//Number of tessellated vertices
int nVertices;
};
__forceinline__ __device__ float2 operator+(float2 a,float2 b){
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__forceinline__ __device__ float2 operator-(float2 a, float2 b){
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
}
__forceinline__ __device__ float2 operator*(float a, float2 b){
float2 c;
c.x = a * b.x;
c.y = a * b.y;
return c;
}
__forceinline__ __device__ float length(float2 a){
return sqrtf(a.x * a.x + a.y * a.y);
}
__device__ float computeCurvature(BezierLine* bLines){
int bidx = blockIdx.x;
float curvature = length(bLines[bidx].CP[1] - 0.5f * (bLines[bidx].CP[0] + bLines[bidx].CP[2]))/length(bLines[bidx].CP[2] - bLines[bidx].CP[0]);
return curvature;
}
__global__ void computeBezierLines(BezierLine* bLines, int nLines){
int bidx = blockIdx.x;
if(bidx < nLines){
//compute the curvature of the line
float curvature = computeCurvature(bLines);
//From the curvature, compute the number of tessellation points
int nTessPoints = min(max((int)(curvature * 16.0f),4),32);
bLines[bidx].nVertices = nTessPoints;
//Loop through vertices to be tessellated, incrementing by blockDim.x
for(int inc = 0;inc < nTessPoints;inc += blockDim.x){
int idx = inc + threadIdx.x;//Compute a unique index for this point
if(idx < nTessPoints){
float u = (float)idx /(float)(nTessPoints - 1);//compute u from idx
float omu = 1.0f - u;
float B3u[3];
B3u[0] = omu * omu;
B3u[1] = 2.0f * u * omu;
B3u[2] = u * u;
float2 position = {0,0};
for(int i = 0;i<3;i++){
position = position + B3u[i] * bLines[bidx].CP[i];
}
bLines[bidx].vertexPos[idx] = position;
}
}
}
}
#define N_LINES 256
#define BLOCK_DIM 32
void initializeBLines(BezierLine * bLines_h){
float2 last = {0,0};
for(int i = 0;i<N_LINES;i++){
bLines_h[i].CP[0] = last;
for(int j = 1;j<3;j++){
bLines_h[i].CP[j].x = (float)rand()/(float)RAND_MAX;
bLines_h[i].CP[j].y = (float)rand()/(float)RAND_MAX;
}
last = bLines_h[i].CP[2];
bLines_h[i].nVertices = 0;
}
}
int main(){
BezierLine * bLines_h = new BezierLine[N_LINES];
initializeBLines(bLines_h);
BezierLine * bLines_d;
cudaMalloc((void**)&bLines_d,N_LINES*sizeof(BezierLine));
cudaMemcpy(bLines_d,bLines_h,N_LINES*sizeof(BezierLine),cudaMemcpyHostToDevice);
computeBezierLines<<<N_LINES,BLOCK_DIM>>>(bLines_d,N_LINES);
cudaFree(bLines_d);
delete[] bLines_h;
} | code for sm_80
Function : _Z18computeBezierLinesP10BezierLinei
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x120 ; /* 0x00000120ff037424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0080*/ LDG.E.64 R6, [R2.64+0x10] ; /* 0x0000100402067981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000080402087981 */
/* 0x000ee2000c1e1b00 */
/*00a0*/ FADD R0, R5, R7 ; /* 0x0000000705007221 */
/* 0x004fe40000000000 */
/*00b0*/ FADD R11, R4, R6 ; /* 0x00000006040b7221 */
/* 0x000fc40000000000 */
/*00c0*/ FFMA R0, R0, -0.5, R9 ; /* 0xbf00000000007823 */
/* 0x008fe40000000009 */
/*00d0*/ FFMA R8, R11, -0.5, R8 ; /* 0xbf0000000b087823 */
/* 0x000fe40000000008 */
/*00e0*/ FMUL R9, R0, R0 ; /* 0x0000000000097220 */
/* 0x000fc80000400000 */
/*00f0*/ FFMA R9, R8, R8, R9 ; /* 0x0000000808097223 */
/* 0x000fc80000000009 */
/*0100*/ MUFU.RSQ R0, R9 ; /* 0x0000000900007308 */
/* 0x0000620000001400 */
/*0110*/ IADD3 R8, R9, -0xd000000, RZ ; /* 0xf300000009087810 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GT.U32.AND P0, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f04070 */
/*0130*/ @!P0 BRA 0x180 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0140*/ MOV R12, 0x160 ; /* 0x00000160000c7802 */
/* 0x003fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0x6b0 ; /* 0x0000055000007944 */
/* 0x000fea0003c00000 */
/*0160*/ MOV R0, R10 ; /* 0x0000000a00007202 */
/* 0x000fe20000000f00 */
/*0170*/ BRA 0x1c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0180*/ FMUL.FTZ R8, R9, R0 ; /* 0x0000000009087220 */
/* 0x003fe40000410000 */
/*0190*/ FMUL.FTZ R0, R0, 0.5 ; /* 0x3f00000000007820 */
/* 0x000fe40000410000 */
/*01a0*/ FFMA R9, -R8, R8, R9 ; /* 0x0000000808097223 */
/* 0x000fc80000000109 */
/*01b0*/ FFMA R0, R9, R0, R8 ; /* 0x0000000009007223 */
/* 0x000fe40000000008 */
/*01c0*/ FADD R5, -R5, R7 ; /* 0x0000000705057221 */
/* 0x000fe40000000100 */
/*01d0*/ FADD R4, -R4, R6 ; /* 0x0000000604047221 */
/* 0x000fe40000000100 */
/*01e0*/ FMUL R5, R5, R5 ; /* 0x0000000505057220 */
/* 0x000fc80000400000 */
/*01f0*/ FFMA R5, R4, R4, R5 ; /* 0x0000000404057223 */
/* 0x000fc80000000005 */
/*0200*/ MUFU.RSQ R4, R5 ; /* 0x0000000500047308 */
/* 0x0000620000001400 */
/*0210*/ IADD3 R6, R5, -0xd000000, RZ ; /* 0xf300000005067810 */
/* 0x000fc80007ffe0ff */
/*0220*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0230*/ @!P0 BRA 0x290 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x003fe200078e0005 */
/*0250*/ MOV R12, 0x270 ; /* 0x00000270000c7802 */
/* 0x000fe40000000f00 */
/*0260*/ CALL.REL.NOINC 0x6b0 ; /* 0x0000044000007944 */
/* 0x000fea0003c00000 */
/*0270*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0280*/ BRA 0x2d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0290*/ FMUL.FTZ R6, R5, R4 ; /* 0x0000000405067220 */
/* 0x003fe40000410000 */
/*02a0*/ FMUL.FTZ R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000410000 */
/*02b0*/ FFMA R5, -R6, R6, R5 ; /* 0x0000000606057223 */
/* 0x000fc80000000105 */
/*02c0*/ FFMA R5, R5, R4, R6 ; /* 0x0000000405057223 */
/* 0x000fc80000000006 */
/*02d0*/ MUFU.RCP R4, R5 ; /* 0x0000000500047308 */
/* 0x000e300000001000 */
/*02e0*/ FCHK P0, R0, R5 ; /* 0x0000000500007302 */
/* 0x000e620000000000 */
/*02f0*/ FFMA R7, R4, -R5, 1 ; /* 0x3f80000004077423 */
/* 0x001fc80000000805 */
/*0300*/ FFMA R7, R4, R7, R4 ; /* 0x0000000704077223 */
/* 0x000fc80000000004 */
/*0310*/ FFMA R4, R7, R0, RZ ; /* 0x0000000007047223 */
/* 0x000fc800000000ff */
/*0320*/ FFMA R6, R4, -R5, R0 ; /* 0x8000000504067223 */
/* 0x000fc80000000000 */
/*0330*/ FFMA R4, R7, R6, R4 ; /* 0x0000000607047223 */
/* 0x000fe20000000004 */
/*0340*/ @!P0 BRA 0x3a0 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0350*/ MOV R13, R0 ; /* 0x00000000000d7202 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0005 */
/*0370*/ MOV R8, 0x390 ; /* 0x0000039000087802 */
/* 0x000fe40000000f00 */
/*0380*/ CALL.REL.NOINC 0x830 ; /* 0x000004a000007944 */
/* 0x000fea0003c00000 */
/*0390*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fc800078e000e */
/*03a0*/ FMUL R4, R4, 16 ; /* 0x4180000004047820 */
/* 0x000fcc0000400000 */
/*03b0*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e24000020f100 */
/*03c0*/ IMNMX R5, R4, 0x4, !PT ; /* 0x0000000404057817 */
/* 0x001fc80007800200 */
/*03d0*/ ISETP.GE.AND P0, PT, R5.reuse, 0x1, PT ; /* 0x000000010500780c */
/* 0x040fe40003f06270 */
/*03e0*/ IMNMX R5, R5, 0x20, PT ; /* 0x0000002005057817 */
/* 0x000fca0003800200 */
/*03f0*/ STG.E [R2.64+0x118], R5 ; /* 0x0001180502007986 */
/* 0x0001ec000c101904 */
/*0400*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0410*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0420*/ IADD3 R4, R5, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x000fe20007ffe0ff */
/*0430*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fca00000001ff */
/*0440*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000eac0000201400 */
/*0450*/ IMAD.IADD R7, R0, 0x1, R6 ; /* 0x0000000100077824 */
/* 0x002fe200078e0206 */
/*0460*/ IADD3 R6, R6, c[0x0][0x0], RZ ; /* 0x0000000006067a10 */
/* 0x000fe20007ffe0ff */
/*0470*/ BSSY B0, 0x690 ; /* 0x0000021000007945 */
/* 0x000fe60003800000 */
/*0480*/ ISETP.GE.AND P0, PT, R7, R5.reuse, PT ; /* 0x000000050700720c */
/* 0x080fe40003f06270 */
/*0490*/ ISETP.GE.AND P2, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fd60003f46270 */
/*04a0*/ @P0 BRA 0x680 ; /* 0x000001d000000947 */
/* 0x004fea0003800000 */
/*04b0*/ I2F R13, R7 ; /* 0x00000007000d7306 */
/* 0x000e620000201400 */
/*04c0*/ BSSY B1, 0x580 ; /* 0x000000b000017945 */
/* 0x000fee0003800000 */
/*04d0*/ MUFU.RCP R9, R4 ; /* 0x0000000400097308 */
/* 0x004eb00000001000 */
/*04e0*/ FCHK P0, R13, R4 ; /* 0x000000040d007302 */
/* 0x002e620000000000 */
/*04f0*/ FFMA R8, -R4, R9, 1 ; /* 0x3f80000004087423 */
/* 0x004fc80000000109 */
/*0500*/ FFMA R8, R9, R8, R9 ; /* 0x0000000809087223 */
/* 0x000fc80000000009 */
/*0510*/ FFMA R9, R13, R8, RZ ; /* 0x000000080d097223 */
/* 0x000fc800000000ff */
/*0520*/ FFMA R10, -R4, R9, R13 ; /* 0x00000009040a7223 */
/* 0x000fc8000000010d */
/*0530*/ FFMA R14, R8, R10, R9 ; /* 0x0000000a080e7223 */
/* 0x000fe20000000009 */
/*0540*/ @!P0 BRA 0x570 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0550*/ MOV R8, 0x570 ; /* 0x0000057000087802 */
/* 0x000fe40000000f00 */
/*0560*/ CALL.REL.NOINC 0x830 ; /* 0x000002c000007944 */
/* 0x001fea0003c00000 */
/*0570*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0580*/ LDG.E.64 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ee8000c1e1b00 */
/*05a0*/ LDG.E.64 R8, [R2.64+0x10] ; /* 0x0000100402087981 */
/* 0x000f22000c1e1b00 */
/*05b0*/ FADD R15, -R14, 1 ; /* 0x3f8000000e0f7421 */
/* 0x000fc40000000100 */
/*05c0*/ FADD R18, R14.reuse, R14 ; /* 0x0000000e0e127221 */
/* 0x040fe40000000000 */
/*05d0*/ FMUL R16, R15.reuse, R15 ; /* 0x0000000f0f107220 */
/* 0x040fe40000400000 */
/*05e0*/ FMUL R18, R15, R18 ; /* 0x000000120f127220 */
/* 0x000fe40000400000 */
/*05f0*/ FMUL R14, R14, R14 ; /* 0x0000000e0e0e7220 */
/* 0x000fe40000400000 */
/*0600*/ FFMA R15, R16.reuse, R13, RZ ; /* 0x0000000d100f7223 */
/* 0x044fe400000000ff */
/*0610*/ FFMA R13, R16, R12, RZ ; /* 0x0000000c100d7223 */
/* 0x000fc400000000ff */
/*0620*/ FFMA R15, R18.reuse, R11, R15 ; /* 0x0000000b120f7223 */
/* 0x048fe4000000000f */
/*0630*/ FFMA R13, R18, R10, R13 ; /* 0x0000000a120d7223 */
/* 0x000fe4000000000d */
/*0640*/ IMAD.WIDE R10, R7, 0x8, R2 ; /* 0x00000008070a7825 */
/* 0x000fc800078e0202 */
/*0650*/ FFMA R9, R14.reuse, R9, R15 ; /* 0x000000090e097223 */
/* 0x050fe4000000000f */
/*0660*/ FFMA R8, R14, R8, R13 ; /* 0x000000080e087223 */
/* 0x000fca000000000d */
/*0670*/ STG.E.64 [R10.64+0x18], R8 ; /* 0x000018080a007986 */
/* 0x0003e4000c101b04 */
/*0680*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0690*/ @!P2 BRA 0x450 ; /* 0xfffffdb00000a947 */
/* 0x000fea000383ffff */
/*06a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06b0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c0ff */
/*06c0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff088224 */
/* 0x000fe200078e0009 */
/*06d0*/ @!P0 BRA 0x7f0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*06e0*/ FSETP.GEU.FTZ.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fda0003f1e000 */
/*06f0*/ @!P0 MOV R8, 0x7fffffff ; /* 0x7fffffff00088802 */
/* 0x000fe20000000f00 */
/*0700*/ @!P0 BRA 0x7f0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0710*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fda0003f1c200 */
/*0720*/ @P0 FADD.FTZ R8, R9, 1 ; /* 0x3f80000009080421 */
/* 0x000fe20000010000 */
/*0730*/ @P0 BRA 0x7f0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0740*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fda0003f1d200 */
/*0750*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff088224 */
/* 0x000fe200078e0009 */
/*0760*/ @!P0 BRA 0x7f0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0770*/ FFMA R9, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009097823 */
/* 0x000fc800000000ff */
/*0780*/ MUFU.RSQ R8, R9 ; /* 0x0000000900087308 */
/* 0x000e240000001400 */
/*0790*/ FMUL.FTZ R10, R9, R8 ; /* 0x00000008090a7220 */
/* 0x001fe40000410000 */
/*07a0*/ FMUL.FTZ R8, R8, 0.5 ; /* 0x3f00000008087820 */
/* 0x000fe40000410000 */
/*07b0*/ FADD.FTZ R11, -R10, -RZ ; /* 0x800000ff0a0b7221 */
/* 0x000fc80000010100 */
/*07c0*/ FFMA R11, R10, R11, R9 ; /* 0x0000000b0a0b7223 */
/* 0x000fc80000000009 */
/*07d0*/ FFMA R8, R11, R8, R10 ; /* 0x000000080b087223 */
/* 0x000fc8000000000a */
/*07e0*/ FMUL.FTZ R8, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008087820 */
/* 0x000fc80000410000 */
/*07f0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0008 */
/*0800*/ MOV R8, R12 ; /* 0x0000000c00087202 */
/* 0x000fe20000000f00 */
/*0810*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*0820*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff7d008007950 */
/* 0x000fea0003c3ffff */
/*0830*/ SHF.R.U32.HI R11, RZ, 0x17, R4 ; /* 0x00000017ff0b7819 */
/* 0x000fe20000011604 */
/*0840*/ BSSY B2, 0xe90 ; /* 0x0000064000027945 */
/* 0x000fe20003800000 */
/*0850*/ SHF.R.U32.HI R9, RZ, 0x17, R13.reuse ; /* 0x00000017ff097819 */
/* 0x100fe4000001160d */
/*0860*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fe400078ec0ff */
/*0870*/ LOP3.LUT R15, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff090f7812 */
/* 0x000fe200078ec0ff */
/*0880*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*0890*/ IADD3 R16, R11, -0x1, RZ ; /* 0xffffffff0b107810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R14, R15, -0x1, RZ ; /* 0xffffffff0f0e7810 */
/* 0x000fc40007ffe0ff */
/*08b0*/ ISETP.GT.U32.AND P0, PT, R16, 0xfd, PT ; /* 0x000000fd1000780c */
/* 0x000fe40003f04070 */
/*08c0*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x000fe40000000f00 */
/*08d0*/ ISETP.GT.U32.OR P0, PT, R14, 0xfd, P0 ; /* 0x000000fd0e00780c */
/* 0x000fda0000704470 */
/*08e0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*08f0*/ @!P0 BRA 0xa70 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0900*/ FSETP.GTU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f1c200 */
/*0910*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*0920*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0930*/ @P0 BRA 0xe70 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R9, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c809 */
/*0950*/ @!P0 BRA 0xe50 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0960*/ FSETP.NEU.FTZ.AND P3, PT, |R13|.reuse, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x040fe40003f7d200 */
/*0970*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0980*/ FSETP.NEU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fd60003f1d200 */
/*0990*/ @!P1 BRA !P3, 0xe50 ; /* 0x000004b000009947 */
/* 0x000fea0005800000 */
/*09a0*/ LOP3.LUT P3, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000786c0ff */
/*09b0*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*09c0*/ @P1 BRA 0xe30 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*09e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*09f0*/ @P0 BRA 0xe00 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.GE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f06270 */
/*0a10*/ ISETP.GE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd60003f26270 */
/*0a20*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe200078e00ff */
/*0a30*/ @!P0 MOV R10, 0xffffffc0 ; /* 0xffffffc0000a8802 */
/* 0x000fe20000000f00 */
/*0a40*/ @!P0 FFMA R9, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d098823 */
/* 0x000fe400000000ff */
/*0a50*/ @!P1 FFMA R12, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f800000040c9823 */
/* 0x000fe200000000ff */
/*0a60*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ LEA R13, R11, 0xc0800000, 0x17 ; /* 0xc08000000b0d7811 */
/* 0x000fe200078eb8ff */
/*0a80*/ BSSY B3, 0xdf0 ; /* 0x0000036000037945 */
/* 0x000fe80003800000 */
/*0a90*/ IMAD.IADD R13, R12, 0x1, -R13 ; /* 0x000000010c0d7824 */
/* 0x000fe200078e0a0d */
/*0aa0*/ IADD3 R12, R15, -0x7f, RZ ; /* 0xffffff810f0c7810 */
/* 0x000fc60007ffe0ff */
/*0ab0*/ MUFU.RCP R14, R13 ; /* 0x0000000d000e7308 */
/* 0x0000620000001000 */
/*0ac0*/ FADD.FTZ R16, -R13, -RZ ; /* 0x800000ff0d107221 */
/* 0x000fe40000010100 */
/*0ad0*/ IMAD R9, R12.reuse, -0x800000, R9 ; /* 0xff8000000c097824 */
/* 0x040fe200078e0209 */
/*0ae0*/ IADD3 R13, R12, 0x7f, -R11 ; /* 0x0000007f0c0d7810 */
/* 0x001fc80007ffe80b */
/*0af0*/ IADD3 R10, R13, R10, RZ ; /* 0x0000000a0d0a7210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ FFMA R15, R14, R16, 1 ; /* 0x3f8000000e0f7423 */
/* 0x002fc80000000010 */
/*0b10*/ FFMA R18, R14, R15, R14 ; /* 0x0000000f0e127223 */
/* 0x000fc8000000000e */
/*0b20*/ FFMA R14, R9, R18, RZ ; /* 0x00000012090e7223 */
/* 0x000fc800000000ff */
/*0b30*/ FFMA R15, R16, R14, R9 ; /* 0x0000000e100f7223 */
/* 0x000fc80000000009 */
/*0b40*/ FFMA R15, R18, R15, R14 ; /* 0x0000000f120f7223 */
/* 0x000fc8000000000e */
/*0b50*/ FFMA R16, R16, R15, R9 ; /* 0x0000000f10107223 */
/* 0x000fc80000000009 */
/*0b60*/ FFMA R9, R18, R16, R15 ; /* 0x0000001012097223 */
/* 0x000fca000000000f */
/*0b70*/ SHF.R.U32.HI R11, RZ, 0x17, R9 ; /* 0x00000017ff0b7819 */
/* 0x000fc80000011609 */
/*0b80*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fca00078ec0ff */
/*0b90*/ IMAD.IADD R14, R11, 0x1, R10 ; /* 0x000000010b0e7824 */
/* 0x000fca00078e020a */
/*0ba0*/ IADD3 R11, R14, -0x1, RZ ; /* 0xffffffff0e0b7810 */
/* 0x000fc80007ffe0ff */
/*0bb0*/ ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f06070 */
/*0bc0*/ @!P0 BRA 0xdd0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*0be0*/ @P0 BRA 0xda0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0bf0*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0c00*/ @P0 BRA 0xde0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0c10*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*0c20*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fd600078ec0ff */
/*0c30*/ @!P0 BRA 0xde0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0c40*/ FFMA.RZ R10, R18, R16.reuse, R15.reuse ; /* 0x00000010120a7223 */
/* 0x180fe2000000c00f */
/*0c50*/ IADD3 R13, R14, 0x20, RZ ; /* 0x000000200e0d7810 */
/* 0x000fe20007ffe0ff */
/*0c60*/ FFMA.RM R11, R18, R16.reuse, R15.reuse ; /* 0x00000010120b7223 */
/* 0x180fe2000000400f */
/*0c70*/ ISETP.NE.AND P3, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f65270 */
/*0c80*/ LOP3.LUT R12, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a0c7812 */
/* 0x000fe200078ec0ff */
/*0c90*/ FFMA.RP R10, R18, R16, R15 ; /* 0x00000010120a7223 */
/* 0x000fe2000000800f */
/*0ca0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f25270 */
/*0cb0*/ LOP3.LUT R12, R12, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000c0c7812 */
/* 0x000fe400078efcff */
/*0cc0*/ IADD3 R14, -R14, RZ, RZ ; /* 0x000000ff0e0e7210 */
/* 0x000fc40007ffe1ff */
/*0cd0*/ SHF.L.U32 R13, R12, R13, RZ ; /* 0x0000000d0c0d7219 */
/* 0x000fe400000006ff */
/*0ce0*/ FSETP.NEU.FTZ.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720b */
/* 0x000fe40003f1d000 */
/*0cf0*/ SEL R11, R14, RZ, P3 ; /* 0x000000ff0e0b7207 */
/* 0x000fe40001800000 */
/*0d00*/ ISETP.NE.AND P1, PT, R13, RZ, P1 ; /* 0x000000ff0d00720c */
/* 0x000fe40000f25270 */
/*0d10*/ SHF.R.U32.HI R11, RZ, R11, R12 ; /* 0x0000000bff0b7219 */
/* 0x000fe4000001160c */
/*0d20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0d30*/ SHF.R.U32.HI R13, RZ, 0x1, R11 ; /* 0x00000001ff0d7819 */
/* 0x000fe4000001160b */
/*0d40*/ SEL R10, RZ, 0x1, !P0 ; /* 0x00000001ff0a7807 */
/* 0x000fc80004000000 */
/*0d50*/ LOP3.LUT R10, R10, 0x1, R13, 0xf8, !PT ; /* 0x000000010a0a7812 */
/* 0x000fc800078ef80d */
/*0d60*/ LOP3.LUT R10, R10, R11, RZ, 0xc0, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fca00078ec0ff */
/*0d70*/ IMAD.IADD R10, R13, 0x1, R10 ; /* 0x000000010d0a7824 */
/* 0x000fca00078e020a */
/*0d80*/ LOP3.LUT R9, R10, R9, RZ, 0xfc, !PT ; /* 0x000000090a097212 */
/* 0x000fe200078efcff */
/*0d90*/ BRA 0xde0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0da0*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fc800078ec0ff */
/*0db0*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*0dc0*/ BRA 0xde0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0dd0*/ LEA R9, R10, R9, 0x17 ; /* 0x000000090a097211 */
/* 0x000fe400078eb8ff */
/*0de0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0df0*/ BRA 0xe80 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e00*/ LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ; /* 0x800000000c097812 */
/* 0x000fc800078e4809 */
/*0e10*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*0e20*/ BRA 0xe80 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0e30*/ LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ; /* 0x800000000c097812 */
/* 0x000fe200078e4809 */
/*0e40*/ BRA 0xe80 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0e50*/ MUFU.RSQ R9, -QNAN ; /* 0xffc0000000097908 */
/* 0x000e220000001400 */
/*0e60*/ BRA 0xe80 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e70*/ FADD.FTZ R9, R13, R4 ; /* 0x000000040d097221 */
/* 0x000fe40000010000 */
/*0e80*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e90*/ IMAD.MOV.U32 R14, RZ, RZ, R9 ; /* 0x000000ffff0e7224 */
/* 0x001fe200078e0009 */
/*0ea0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fcc00000001ff */
/*0eb0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff14008007950 */
/* 0x000fea0003c3ffff */
/*0ec0*/ BRA 0xec0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#define MAX_TESS_POINTS 32
struct BezierLine{
float2 CP[3];//control points for the line
float2 vertexPos[MAX_TESS_POINTS];//Vertex position array to tessellate into
//Number of tessellated vertices
int nVertices;
};
__forceinline__ __device__ float2 operator+(float2 a,float2 b){
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__forceinline__ __device__ float2 operator-(float2 a, float2 b){
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
}
__forceinline__ __device__ float2 operator*(float a, float2 b){
float2 c;
c.x = a * b.x;
c.y = a * b.y;
return c;
}
__forceinline__ __device__ float length(float2 a){
return sqrtf(a.x * a.x + a.y * a.y);
}
__device__ float computeCurvature(BezierLine* bLines){
int bidx = blockIdx.x;
float curvature = length(bLines[bidx].CP[1] - 0.5f * (bLines[bidx].CP[0] + bLines[bidx].CP[2]))/length(bLines[bidx].CP[2] - bLines[bidx].CP[0]);
return curvature;
}
__global__ void computeBezierLines(BezierLine* bLines, int nLines){
int bidx = blockIdx.x;
if(bidx < nLines){
//compute the curvature of the line
float curvature = computeCurvature(bLines);
//From the curvature, compute the number of tessellation points
int nTessPoints = min(max((int)(curvature * 16.0f),4),32);
bLines[bidx].nVertices = nTessPoints;
//Loop through vertices to be tessellated, incrementing by blockDim.x
for(int inc = 0;inc < nTessPoints;inc += blockDim.x){
int idx = inc + threadIdx.x;//Compute a unique index for this point
if(idx < nTessPoints){
float u = (float)idx /(float)(nTessPoints - 1);//compute u from idx
float omu = 1.0f - u;
float B3u[3];
B3u[0] = omu * omu;
B3u[1] = 2.0f * u * omu;
B3u[2] = u * u;
float2 position = {0,0};
for(int i = 0;i<3;i++){
position = position + B3u[i] * bLines[bidx].CP[i];
}
bLines[bidx].vertexPos[idx] = position;
}
}
}
}
#define N_LINES 256
#define BLOCK_DIM 32
void initializeBLines(BezierLine * bLines_h){
float2 last = {0,0};
for(int i = 0;i<N_LINES;i++){
bLines_h[i].CP[0] = last;
for(int j = 1;j<3;j++){
bLines_h[i].CP[j].x = (float)rand()/(float)RAND_MAX;
bLines_h[i].CP[j].y = (float)rand()/(float)RAND_MAX;
}
last = bLines_h[i].CP[2];
bLines_h[i].nVertices = 0;
}
}
int main(){
BezierLine * bLines_h = new BezierLine[N_LINES];
initializeBLines(bLines_h);
BezierLine * bLines_d;
cudaMalloc((void**)&bLines_d,N_LINES*sizeof(BezierLine));
cudaMemcpy(bLines_d,bLines_h,N_LINES*sizeof(BezierLine),cudaMemcpyHostToDevice);
computeBezierLines<<<N_LINES,BLOCK_DIM>>>(bLines_d,N_LINES);
cudaFree(bLines_d);
delete[] bLines_h;
} | .file "tmpxft_00064377_00000000-6_bezier_curve.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16computeCurvatureP10BezierLine
.type _Z16computeCurvatureP10BezierLine, @function
_Z16computeCurvatureP10BezierLine:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z16computeCurvatureP10BezierLine, .-_Z16computeCurvatureP10BezierLine
.globl _Z16initializeBLinesP10BezierLine
.type _Z16initializeBLinesP10BezierLine, @function
_Z16initializeBLinesP10BezierLine:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq 73728(%rdi), %rbp
pxor %xmm0, %xmm0
movaps %xmm0, %xmm1
.L6:
movss %xmm1, (%rbx)
movss %xmm0, 4(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 12(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 16(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 20(%rbx)
movss 16(%rbx), %xmm1
movl $0, 280(%rbx)
addq $288, %rbx
cmpq %rbp, %rbx
jne .L6
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z16initializeBLinesP10BezierLine, .-_Z16initializeBLinesP10BezierLine
.globl _Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei
.type _Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei, @function
_Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18computeBezierLinesP10BezierLinei(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei, .-_Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei
.globl _Z18computeBezierLinesP10BezierLinei
.type _Z18computeBezierLinesP10BezierLinei, @function
_Z18computeBezierLinesP10BezierLinei:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z18computeBezierLinesP10BezierLinei, .-_Z18computeBezierLinesP10BezierLinei
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $73728, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rax, %rdi
call _Z16initializeBLinesP10BezierLine
leaq 8(%rsp), %rdi
movl $73728, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $73728, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $256, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $256, %esi
movq 8(%rsp), %rdi
call _Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z18computeBezierLinesP10BezierLinei"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z18computeBezierLinesP10BezierLinei(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#define MAX_TESS_POINTS 32
struct BezierLine{
float2 CP[3];//control points for the line
float2 vertexPos[MAX_TESS_POINTS];//Vertex position array to tessellate into
//Number of tessellated vertices
int nVertices;
};
__forceinline__ __device__ float2 operator+(float2 a,float2 b){
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__forceinline__ __device__ float2 operator-(float2 a, float2 b){
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
}
__forceinline__ __device__ float2 operator*(float a, float2 b){
float2 c;
c.x = a * b.x;
c.y = a * b.y;
return c;
}
__forceinline__ __device__ float length(float2 a){
return sqrtf(a.x * a.x + a.y * a.y);
}
__device__ float computeCurvature(BezierLine* bLines){
int bidx = blockIdx.x;
float curvature = length(bLines[bidx].CP[1] - 0.5f * (bLines[bidx].CP[0] + bLines[bidx].CP[2]))/length(bLines[bidx].CP[2] - bLines[bidx].CP[0]);
return curvature;
}
__global__ void computeBezierLines(BezierLine* bLines, int nLines){
int bidx = blockIdx.x;
if(bidx < nLines){
//compute the curvature of the line
float curvature = computeCurvature(bLines);
//From the curvature, compute the number of tessellation points
int nTessPoints = min(max((int)(curvature * 16.0f),4),32);
bLines[bidx].nVertices = nTessPoints;
//Loop through vertices to be tessellated, incrementing by blockDim.x
for(int inc = 0;inc < nTessPoints;inc += blockDim.x){
int idx = inc + threadIdx.x;//Compute a unique index for this point
if(idx < nTessPoints){
float u = (float)idx /(float)(nTessPoints - 1);//compute u from idx
float omu = 1.0f - u;
float B3u[3];
B3u[0] = omu * omu;
B3u[1] = 2.0f * u * omu;
B3u[2] = u * u;
float2 position = {0,0};
for(int i = 0;i<3;i++){
position = position + B3u[i] * bLines[bidx].CP[i];
}
bLines[bidx].vertexPos[idx] = position;
}
}
}
}
#define N_LINES 256
#define BLOCK_DIM 32
void initializeBLines(BezierLine * bLines_h){
float2 last = {0,0};
for(int i = 0;i<N_LINES;i++){
bLines_h[i].CP[0] = last;
for(int j = 1;j<3;j++){
bLines_h[i].CP[j].x = (float)rand()/(float)RAND_MAX;
bLines_h[i].CP[j].y = (float)rand()/(float)RAND_MAX;
}
last = bLines_h[i].CP[2];
bLines_h[i].nVertices = 0;
}
}
int main(){
BezierLine * bLines_h = new BezierLine[N_LINES];
initializeBLines(bLines_h);
BezierLine * bLines_d;
cudaMalloc((void**)&bLines_d,N_LINES*sizeof(BezierLine));
cudaMemcpy(bLines_d,bLines_h,N_LINES*sizeof(BezierLine),cudaMemcpyHostToDevice);
computeBezierLines<<<N_LINES,BLOCK_DIM>>>(bLines_d,N_LINES);
cudaFree(bLines_d);
delete[] bLines_h;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define MAX_TESS_POINTS 32
struct BezierLine{
float2 CP[3];//control points for the line
float2 vertexPos[MAX_TESS_POINTS];//Vertex position array to tessellate into
//Number of tessellated vertices
int nVertices;
};
__forceinline__ __device__ float2 operator+(float2 a,float2 b){
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__forceinline__ __device__ float2 operator-(float2 a, float2 b){
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
}
__forceinline__ __device__ float2 operator*(float a, float2 b){
float2 c;
c.x = a * b.x;
c.y = a * b.y;
return c;
}
__forceinline__ __device__ float length(float2 a){
return sqrtf(a.x * a.x + a.y * a.y);
}
__device__ float computeCurvature(BezierLine* bLines){
int bidx = blockIdx.x;
float curvature = length(bLines[bidx].CP[1] - 0.5f * (bLines[bidx].CP[0] + bLines[bidx].CP[2]))/length(bLines[bidx].CP[2] - bLines[bidx].CP[0]);
return curvature;
}
__global__ void computeBezierLines(BezierLine* bLines, int nLines){
int bidx = blockIdx.x;
if(bidx < nLines){
//compute the curvature of the line
float curvature = computeCurvature(bLines);
//From the curvature, compute the number of tessellation points
int nTessPoints = min(max((int)(curvature * 16.0f),4),32);
bLines[bidx].nVertices = nTessPoints;
//Loop through vertices to be tessellated, incrementing by blockDim.x
for(int inc = 0;inc < nTessPoints;inc += blockDim.x){
int idx = inc + threadIdx.x;//Compute a unique index for this point
if(idx < nTessPoints){
float u = (float)idx /(float)(nTessPoints - 1);//compute u from idx
float omu = 1.0f - u;
float B3u[3];
B3u[0] = omu * omu;
B3u[1] = 2.0f * u * omu;
B3u[2] = u * u;
float2 position = {0,0};
for(int i = 0;i<3;i++){
position = position + B3u[i] * bLines[bidx].CP[i];
}
bLines[bidx].vertexPos[idx] = position;
}
}
}
}
#define N_LINES 256
#define BLOCK_DIM 32
void initializeBLines(BezierLine * bLines_h){
float2 last = {0,0};
for(int i = 0;i<N_LINES;i++){
bLines_h[i].CP[0] = last;
for(int j = 1;j<3;j++){
bLines_h[i].CP[j].x = (float)rand()/(float)RAND_MAX;
bLines_h[i].CP[j].y = (float)rand()/(float)RAND_MAX;
}
last = bLines_h[i].CP[2];
bLines_h[i].nVertices = 0;
}
}
int main(){
BezierLine * bLines_h = new BezierLine[N_LINES];
initializeBLines(bLines_h);
BezierLine * bLines_d;
hipMalloc((void**)&bLines_d,N_LINES*sizeof(BezierLine));
hipMemcpy(bLines_d,bLines_h,N_LINES*sizeof(BezierLine),hipMemcpyHostToDevice);
computeBezierLines<<<N_LINES,BLOCK_DIM>>>(bLines_d,N_LINES);
hipFree(bLines_d);
delete[] bLines_h;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define MAX_TESS_POINTS 32
struct BezierLine{
float2 CP[3];//control points for the line
float2 vertexPos[MAX_TESS_POINTS];//Vertex position array to tessellate into
//Number of tessellated vertices
int nVertices;
};
__forceinline__ __device__ float2 operator+(float2 a,float2 b){
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__forceinline__ __device__ float2 operator-(float2 a, float2 b){
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
}
__forceinline__ __device__ float2 operator*(float a, float2 b){
float2 c;
c.x = a * b.x;
c.y = a * b.y;
return c;
}
__forceinline__ __device__ float length(float2 a){
return sqrtf(a.x * a.x + a.y * a.y);
}
__device__ float computeCurvature(BezierLine* bLines){
int bidx = blockIdx.x;
float curvature = length(bLines[bidx].CP[1] - 0.5f * (bLines[bidx].CP[0] + bLines[bidx].CP[2]))/length(bLines[bidx].CP[2] - bLines[bidx].CP[0]);
return curvature;
}
__global__ void computeBezierLines(BezierLine* bLines, int nLines){
int bidx = blockIdx.x;
if(bidx < nLines){
//compute the curvature of the line
float curvature = computeCurvature(bLines);
//From the curvature, compute the number of tessellation points
int nTessPoints = min(max((int)(curvature * 16.0f),4),32);
bLines[bidx].nVertices = nTessPoints;
//Loop through vertices to be tessellated, incrementing by blockDim.x
for(int inc = 0;inc < nTessPoints;inc += blockDim.x){
int idx = inc + threadIdx.x;//Compute a unique index for this point
if(idx < nTessPoints){
float u = (float)idx /(float)(nTessPoints - 1);//compute u from idx
float omu = 1.0f - u;
float B3u[3];
B3u[0] = omu * omu;
B3u[1] = 2.0f * u * omu;
B3u[2] = u * u;
float2 position = {0,0};
for(int i = 0;i<3;i++){
position = position + B3u[i] * bLines[bidx].CP[i];
}
bLines[bidx].vertexPos[idx] = position;
}
}
}
}
#define N_LINES 256
#define BLOCK_DIM 32
void initializeBLines(BezierLine * bLines_h){
float2 last = {0,0};
for(int i = 0;i<N_LINES;i++){
bLines_h[i].CP[0] = last;
for(int j = 1;j<3;j++){
bLines_h[i].CP[j].x = (float)rand()/(float)RAND_MAX;
bLines_h[i].CP[j].y = (float)rand()/(float)RAND_MAX;
}
last = bLines_h[i].CP[2];
bLines_h[i].nVertices = 0;
}
}
int main(){
BezierLine * bLines_h = new BezierLine[N_LINES];
initializeBLines(bLines_h);
BezierLine * bLines_d;
hipMalloc((void**)&bLines_d,N_LINES*sizeof(BezierLine));
hipMemcpy(bLines_d,bLines_h,N_LINES*sizeof(BezierLine),hipMemcpyHostToDevice);
computeBezierLines<<<N_LINES,BLOCK_DIM>>>(bLines_d,N_LINES);
hipFree(bLines_d);
delete[] bLines_h;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18computeBezierLinesP10BezierLinei
.globl _Z18computeBezierLinesP10BezierLinei
.p2align 8
.type _Z18computeBezierLinesP10BezierLinei,@function
_Z18computeBezierLinesP10BezierLinei:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s2
s_cbranch_scc1 .LBB0_7
s_load_b64 s[4:5], s[0:1], 0x0
s_mul_i32 s2, s15, 0x120
s_mul_hi_i32 s3, s15, 0x120
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s4, s2
s_addc_u32 s7, s5, s3
s_clause 0x1
s_load_b128 s[8:11], s[6:7], 0x0
s_load_b64 s[2:3], s[6:7], 0x10
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v1, s9, s3
v_sub_f32_e64 v2, s3, s9
v_add_f32_e64 v3, s8, s2
v_sub_f32_e64 v4, s2, s8
s_mov_b32 s8, 0
v_fma_f32 v1, v1, -0.5, s11
v_mul_f32_e32 v2, v2, v2
v_fma_f32 v3, v3, -0.5, s10
s_mul_hi_i32 s9, s15, 0x120
s_mul_i32 s11, s15, 0x120
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v1, v1, v1 :: v_dual_fmac_f32 v2, v4, v4
v_fmac_f32_e32 v1, v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_mul_f32_e32 v4, 0x4f800000, v1
v_cmp_gt_f32_e64 s2, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cndmask_b32_e64 v1, v1, v4, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sqrt_f32_e32 v3, v2
v_sqrt_f32_e32 v4, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v3
v_add_nc_u32_e32 v7, 1, v3
v_add_nc_u32_e32 v6, -1, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v9, -v5, v3, v2
v_add_nc_u32_e32 v8, 1, v4
v_fma_f32 v11, -v7, v3, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v10, -v6, v4, v1
v_cmp_ge_f32_e64 s3, 0, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v8, v4, v1
v_cndmask_b32_e64 v3, v3, v5, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s3, 0, v10
v_cndmask_b32_e64 v4, v4, v6, s3
v_cmp_lt_f32_e64 s3, 0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v7, s3
v_cmp_lt_f32_e64 s3, 0, v12
v_mul_f32_e32 v5, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v8, s3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_mul_f32 v6, 0x37800000, v4
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v6, s2
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v4, v1, vcc_lo
v_div_scale_f32 v3, null, v2, v2, v1
v_div_scale_f32 v6, vcc_lo, v1, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v3, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v3, v3, v4, v5
v_mov_b32_e32 v5, 0
v_div_fixup_f32 v1, v3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0x41800000, v1
v_cvt_i32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_med3_i32 v6, v1, 4, 32
global_store_b32 v5, v6, s[6:7] offset:280
s_load_b32 s2, s[0:1], 0x1c
v_add_nc_u32_e32 v1, -1, v6
s_add_u32 s0, s6, 4
s_addc_u32 s1, s7, 0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v7, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s12
s_add_i32 s8, s8, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s8, v6
s_cbranch_vccz .LBB0_7
.LBB0_3:
v_add_nc_u32_e32 v1, s8, v0
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v1, v6
s_cbranch_execz .LBB0_2
v_cvt_f32_i32_e32 v2, v1
s_mov_b64 s[2:3], 0
s_mov_b64 s[6:7], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v7, v7, v2
v_div_scale_f32 v9, vcc_lo, v2, v7, v2
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v8, v4
v_mul_f32_e32 v8, v9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v3, v8, v9
v_fmac_f32_e32 v8, v10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v8, v9
v_div_fmas_f32 v3, v3, v4, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v7, v2
v_dual_mov_b32 v3, 0 :: v_dual_sub_f32 v4, 1.0, v2
v_add_f32_e32 v9, v2, v2
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v8, v4, v4
v_dual_mul_f32 v9, v9, v4 :: v_dual_mov_b32 v4, 0
.p2align 6
.LBB0_5:
s_clause 0x1
global_load_b32 v10, v5, s[6:7] offset:-4
global_load_b32 v11, v5, s[6:7]
s_cmp_eq_u32 s2, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 2
v_cndmask_b32_e32 v12, v8, v9, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_add_u32 s6, s6, 8
v_cndmask_b32_e32 v12, v12, v2, vcc_lo
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 3
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v12, v10
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v12, v11
s_cbranch_scc0 .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_add_u32 s2, s4, s11
s_addc_u32 s3, s5, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b64 v[1:2], v[3:4], off offset:24
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18computeBezierLinesP10BezierLinei
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18computeBezierLinesP10BezierLinei, .Lfunc_end0-_Z18computeBezierLinesP10BezierLinei
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18computeBezierLinesP10BezierLinei
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18computeBezierLinesP10BezierLinei.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define MAX_TESS_POINTS 32
struct BezierLine{
float2 CP[3];//control points for the line
float2 vertexPos[MAX_TESS_POINTS];//Vertex position array to tessellate into
//Number of tessellated vertices
int nVertices;
};
__forceinline__ __device__ float2 operator+(float2 a,float2 b){
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__forceinline__ __device__ float2 operator-(float2 a, float2 b){
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
}
__forceinline__ __device__ float2 operator*(float a, float2 b){
float2 c;
c.x = a * b.x;
c.y = a * b.y;
return c;
}
__forceinline__ __device__ float length(float2 a){
return sqrtf(a.x * a.x + a.y * a.y);
}
__device__ float computeCurvature(BezierLine* bLines){
int bidx = blockIdx.x;
float curvature = length(bLines[bidx].CP[1] - 0.5f * (bLines[bidx].CP[0] + bLines[bidx].CP[2]))/length(bLines[bidx].CP[2] - bLines[bidx].CP[0]);
return curvature;
}
__global__ void computeBezierLines(BezierLine* bLines, int nLines){
int bidx = blockIdx.x;
if(bidx < nLines){
//compute the curvature of the line
float curvature = computeCurvature(bLines);
//From the curvature, compute the number of tessellation points
int nTessPoints = min(max((int)(curvature * 16.0f),4),32);
bLines[bidx].nVertices = nTessPoints;
//Loop through vertices to be tessellated, incrementing by blockDim.x
for(int inc = 0;inc < nTessPoints;inc += blockDim.x){
int idx = inc + threadIdx.x;//Compute a unique index for this point
if(idx < nTessPoints){
float u = (float)idx /(float)(nTessPoints - 1);//compute u from idx
float omu = 1.0f - u;
float B3u[3];
B3u[0] = omu * omu;
B3u[1] = 2.0f * u * omu;
B3u[2] = u * u;
float2 position = {0,0};
for(int i = 0;i<3;i++){
position = position + B3u[i] * bLines[bidx].CP[i];
}
bLines[bidx].vertexPos[idx] = position;
}
}
}
}
#define N_LINES 256
#define BLOCK_DIM 32
void initializeBLines(BezierLine * bLines_h){
float2 last = {0,0};
for(int i = 0;i<N_LINES;i++){
bLines_h[i].CP[0] = last;
for(int j = 1;j<3;j++){
bLines_h[i].CP[j].x = (float)rand()/(float)RAND_MAX;
bLines_h[i].CP[j].y = (float)rand()/(float)RAND_MAX;
}
last = bLines_h[i].CP[2];
bLines_h[i].nVertices = 0;
}
}
int main(){
BezierLine * bLines_h = new BezierLine[N_LINES];
initializeBLines(bLines_h);
BezierLine * bLines_d;
hipMalloc((void**)&bLines_d,N_LINES*sizeof(BezierLine));
hipMemcpy(bLines_d,bLines_h,N_LINES*sizeof(BezierLine),hipMemcpyHostToDevice);
computeBezierLines<<<N_LINES,BLOCK_DIM>>>(bLines_d,N_LINES);
hipFree(bLines_d);
delete[] bLines_h;
} | .text
.file "bezier_curve.hip"
.globl _Z33__device_stub__computeBezierLinesP10BezierLinei # -- Begin function _Z33__device_stub__computeBezierLinesP10BezierLinei
.p2align 4, 0x90
.type _Z33__device_stub__computeBezierLinesP10BezierLinei,@function
_Z33__device_stub__computeBezierLinesP10BezierLinei: # @_Z33__device_stub__computeBezierLinesP10BezierLinei
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18computeBezierLinesP10BezierLinei, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z33__device_stub__computeBezierLinesP10BezierLinei, .Lfunc_end0-_Z33__device_stub__computeBezierLinesP10BezierLinei
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z16initializeBLinesP10BezierLine
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z16initializeBLinesP10BezierLine
.p2align 4, 0x90
.type _Z16initializeBLinesP10BezierLine,@function
_Z16initializeBLinesP10BezierLine: # @_Z16initializeBLinesP10BezierLine
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
leaq 12(%rdi), %r14
xorps %xmm0, %xmm0
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
leaq (%r15,%r15,8), %r12
shlq $5, %r12
leaq (%rbx,%r12), %r13
movlps %xmm0, (%rbx,%r12)
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -4(%r14,%rbp,8)
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%rbp,8)
incq %rbp
cmpq $2, %rbp
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movsd 16(%r13), %xmm0 # xmm0 = mem[0],zero
movl $0, 280(%rbx,%r12)
incq %r15
addq $288, %r14 # imm = 0x120
cmpq $256, %r15 # imm = 0x100
jne .LBB1_1
# %bb.4:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16initializeBLinesP10BezierLine, .Lfunc_end1-_Z16initializeBLinesP10BezierLine
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $73728, %edi # imm = 0x12000
callq _Znam
movq %rax, %rbx
leaq 12(%rax), %r14
xorps %xmm0, %xmm0
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
leaq (%r15,%r15,8), %r12
shlq $5, %r12
leaq (%rbx,%r12), %r13
movlps %xmm0, (%rbx,%r12)
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, -4(%r14,%rbp,8)
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%rbp,8)
incq %rbp
cmpq $2, %rbp
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movsd 16(%r13), %xmm0 # xmm0 = mem[0],zero
movl $0, 280(%rbx,%r12)
incq %r15
addq $288, %r14 # imm = 0x120
cmpq $256, %r15 # imm = 0x100
jne .LBB2_1
# %bb.4: # %_Z16initializeBLinesP10BezierLine.exit
leaq 8(%rsp), %rdi
movl $73728, %esi # imm = 0x12000
callq hipMalloc
movq 8(%rsp), %rdi
movl $73728, %edx # imm = 0x12000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 224(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $256, 20(%rsp) # imm = 0x100
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18computeBezierLinesP10BezierLinei, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18computeBezierLinesP10BezierLinei, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18computeBezierLinesP10BezierLinei,@object # @_Z18computeBezierLinesP10BezierLinei
.section .rodata,"a",@progbits
.globl _Z18computeBezierLinesP10BezierLinei
.p2align 3, 0x0
_Z18computeBezierLinesP10BezierLinei:
.quad _Z33__device_stub__computeBezierLinesP10BezierLinei
.size _Z18computeBezierLinesP10BezierLinei, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18computeBezierLinesP10BezierLinei"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__computeBezierLinesP10BezierLinei
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18computeBezierLinesP10BezierLinei
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18computeBezierLinesP10BezierLinei
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x120 ; /* 0x00000120ff037424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0070*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0080*/ LDG.E.64 R6, [R2.64+0x10] ; /* 0x0000100402067981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000080402087981 */
/* 0x000ee2000c1e1b00 */
/*00a0*/ FADD R0, R5, R7 ; /* 0x0000000705007221 */
/* 0x004fe40000000000 */
/*00b0*/ FADD R11, R4, R6 ; /* 0x00000006040b7221 */
/* 0x000fc40000000000 */
/*00c0*/ FFMA R0, R0, -0.5, R9 ; /* 0xbf00000000007823 */
/* 0x008fe40000000009 */
/*00d0*/ FFMA R8, R11, -0.5, R8 ; /* 0xbf0000000b087823 */
/* 0x000fe40000000008 */
/*00e0*/ FMUL R9, R0, R0 ; /* 0x0000000000097220 */
/* 0x000fc80000400000 */
/*00f0*/ FFMA R9, R8, R8, R9 ; /* 0x0000000808097223 */
/* 0x000fc80000000009 */
/*0100*/ MUFU.RSQ R0, R9 ; /* 0x0000000900007308 */
/* 0x0000620000001400 */
/*0110*/ IADD3 R8, R9, -0xd000000, RZ ; /* 0xf300000009087810 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GT.U32.AND P0, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f04070 */
/*0130*/ @!P0 BRA 0x180 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0140*/ MOV R12, 0x160 ; /* 0x00000160000c7802 */
/* 0x003fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0x6b0 ; /* 0x0000055000007944 */
/* 0x000fea0003c00000 */
/*0160*/ MOV R0, R10 ; /* 0x0000000a00007202 */
/* 0x000fe20000000f00 */
/*0170*/ BRA 0x1c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0180*/ FMUL.FTZ R8, R9, R0 ; /* 0x0000000009087220 */
/* 0x003fe40000410000 */
/*0190*/ FMUL.FTZ R0, R0, 0.5 ; /* 0x3f00000000007820 */
/* 0x000fe40000410000 */
/*01a0*/ FFMA R9, -R8, R8, R9 ; /* 0x0000000808097223 */
/* 0x000fc80000000109 */
/*01b0*/ FFMA R0, R9, R0, R8 ; /* 0x0000000009007223 */
/* 0x000fe40000000008 */
/*01c0*/ FADD R5, -R5, R7 ; /* 0x0000000705057221 */
/* 0x000fe40000000100 */
/*01d0*/ FADD R4, -R4, R6 ; /* 0x0000000604047221 */
/* 0x000fe40000000100 */
/*01e0*/ FMUL R5, R5, R5 ; /* 0x0000000505057220 */
/* 0x000fc80000400000 */
/*01f0*/ FFMA R5, R4, R4, R5 ; /* 0x0000000404057223 */
/* 0x000fc80000000005 */
/*0200*/ MUFU.RSQ R4, R5 ; /* 0x0000000500047308 */
/* 0x0000620000001400 */
/*0210*/ IADD3 R6, R5, -0xd000000, RZ ; /* 0xf300000005067810 */
/* 0x000fc80007ffe0ff */
/*0220*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0230*/ @!P0 BRA 0x290 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x003fe200078e0005 */
/*0250*/ MOV R12, 0x270 ; /* 0x00000270000c7802 */
/* 0x000fe40000000f00 */
/*0260*/ CALL.REL.NOINC 0x6b0 ; /* 0x0000044000007944 */
/* 0x000fea0003c00000 */
/*0270*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0280*/ BRA 0x2d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0290*/ FMUL.FTZ R6, R5, R4 ; /* 0x0000000405067220 */
/* 0x003fe40000410000 */
/*02a0*/ FMUL.FTZ R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000410000 */
/*02b0*/ FFMA R5, -R6, R6, R5 ; /* 0x0000000606057223 */
/* 0x000fc80000000105 */
/*02c0*/ FFMA R5, R5, R4, R6 ; /* 0x0000000405057223 */
/* 0x000fc80000000006 */
/*02d0*/ MUFU.RCP R4, R5 ; /* 0x0000000500047308 */
/* 0x000e300000001000 */
/*02e0*/ FCHK P0, R0, R5 ; /* 0x0000000500007302 */
/* 0x000e620000000000 */
/*02f0*/ FFMA R7, R4, -R5, 1 ; /* 0x3f80000004077423 */
/* 0x001fc80000000805 */
/*0300*/ FFMA R7, R4, R7, R4 ; /* 0x0000000704077223 */
/* 0x000fc80000000004 */
/*0310*/ FFMA R4, R7, R0, RZ ; /* 0x0000000007047223 */
/* 0x000fc800000000ff */
/*0320*/ FFMA R6, R4, -R5, R0 ; /* 0x8000000504067223 */
/* 0x000fc80000000000 */
/*0330*/ FFMA R4, R7, R6, R4 ; /* 0x0000000607047223 */
/* 0x000fe20000000004 */
/*0340*/ @!P0 BRA 0x3a0 ; /* 0x0000005000008947 */
/* 0x002fea0003800000 */
/*0350*/ MOV R13, R0 ; /* 0x00000000000d7202 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0005 */
/*0370*/ MOV R8, 0x390 ; /* 0x0000039000087802 */
/* 0x000fe40000000f00 */
/*0380*/ CALL.REL.NOINC 0x830 ; /* 0x000004a000007944 */
/* 0x000fea0003c00000 */
/*0390*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fc800078e000e */
/*03a0*/ FMUL R4, R4, 16 ; /* 0x4180000004047820 */
/* 0x000fcc0000400000 */
/*03b0*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e24000020f100 */
/*03c0*/ IMNMX R5, R4, 0x4, !PT ; /* 0x0000000404057817 */
/* 0x001fc80007800200 */
/*03d0*/ ISETP.GE.AND P0, PT, R5.reuse, 0x1, PT ; /* 0x000000010500780c */
/* 0x040fe40003f06270 */
/*03e0*/ IMNMX R5, R5, 0x20, PT ; /* 0x0000002005057817 */
/* 0x000fca0003800200 */
/*03f0*/ STG.E [R2.64+0x118], R5 ; /* 0x0001180502007986 */
/* 0x0001ec000c101904 */
/*0400*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0410*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0420*/ IADD3 R4, R5, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x000fe20007ffe0ff */
/*0430*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fca00000001ff */
/*0440*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000eac0000201400 */
/*0450*/ IMAD.IADD R7, R0, 0x1, R6 ; /* 0x0000000100077824 */
/* 0x002fe200078e0206 */
/*0460*/ IADD3 R6, R6, c[0x0][0x0], RZ ; /* 0x0000000006067a10 */
/* 0x000fe20007ffe0ff */
/*0470*/ BSSY B0, 0x690 ; /* 0x0000021000007945 */
/* 0x000fe60003800000 */
/*0480*/ ISETP.GE.AND P0, PT, R7, R5.reuse, PT ; /* 0x000000050700720c */
/* 0x080fe40003f06270 */
/*0490*/ ISETP.GE.AND P2, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fd60003f46270 */
/*04a0*/ @P0 BRA 0x680 ; /* 0x000001d000000947 */
/* 0x004fea0003800000 */
/*04b0*/ I2F R13, R7 ; /* 0x00000007000d7306 */
/* 0x000e620000201400 */
/*04c0*/ BSSY B1, 0x580 ; /* 0x000000b000017945 */
/* 0x000fee0003800000 */
/*04d0*/ MUFU.RCP R9, R4 ; /* 0x0000000400097308 */
/* 0x004eb00000001000 */
/*04e0*/ FCHK P0, R13, R4 ; /* 0x000000040d007302 */
/* 0x002e620000000000 */
/*04f0*/ FFMA R8, -R4, R9, 1 ; /* 0x3f80000004087423 */
/* 0x004fc80000000109 */
/*0500*/ FFMA R8, R9, R8, R9 ; /* 0x0000000809087223 */
/* 0x000fc80000000009 */
/*0510*/ FFMA R9, R13, R8, RZ ; /* 0x000000080d097223 */
/* 0x000fc800000000ff */
/*0520*/ FFMA R10, -R4, R9, R13 ; /* 0x00000009040a7223 */
/* 0x000fc8000000010d */
/*0530*/ FFMA R14, R8, R10, R9 ; /* 0x0000000a080e7223 */
/* 0x000fe20000000009 */
/*0540*/ @!P0 BRA 0x570 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0550*/ MOV R8, 0x570 ; /* 0x0000057000087802 */
/* 0x000fe40000000f00 */
/*0560*/ CALL.REL.NOINC 0x830 ; /* 0x000002c000007944 */
/* 0x001fea0003c00000 */
/*0570*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0580*/ LDG.E.64 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ee8000c1e1b00 */
/*05a0*/ LDG.E.64 R8, [R2.64+0x10] ; /* 0x0000100402087981 */
/* 0x000f22000c1e1b00 */
/*05b0*/ FADD R15, -R14, 1 ; /* 0x3f8000000e0f7421 */
/* 0x000fc40000000100 */
/*05c0*/ FADD R18, R14.reuse, R14 ; /* 0x0000000e0e127221 */
/* 0x040fe40000000000 */
/*05d0*/ FMUL R16, R15.reuse, R15 ; /* 0x0000000f0f107220 */
/* 0x040fe40000400000 */
/*05e0*/ FMUL R18, R15, R18 ; /* 0x000000120f127220 */
/* 0x000fe40000400000 */
/*05f0*/ FMUL R14, R14, R14 ; /* 0x0000000e0e0e7220 */
/* 0x000fe40000400000 */
/*0600*/ FFMA R15, R16.reuse, R13, RZ ; /* 0x0000000d100f7223 */
/* 0x044fe400000000ff */
/*0610*/ FFMA R13, R16, R12, RZ ; /* 0x0000000c100d7223 */
/* 0x000fc400000000ff */
/*0620*/ FFMA R15, R18.reuse, R11, R15 ; /* 0x0000000b120f7223 */
/* 0x048fe4000000000f */
/*0630*/ FFMA R13, R18, R10, R13 ; /* 0x0000000a120d7223 */
/* 0x000fe4000000000d */
/*0640*/ IMAD.WIDE R10, R7, 0x8, R2 ; /* 0x00000008070a7825 */
/* 0x000fc800078e0202 */
/*0650*/ FFMA R9, R14.reuse, R9, R15 ; /* 0x000000090e097223 */
/* 0x050fe4000000000f */
/*0660*/ FFMA R8, R14, R8, R13 ; /* 0x000000080e087223 */
/* 0x000fca000000000d */
/*0670*/ STG.E.64 [R10.64+0x18], R8 ; /* 0x000018080a007986 */
/* 0x0003e4000c101b04 */
/*0680*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0690*/ @!P2 BRA 0x450 ; /* 0xfffffdb00000a947 */
/* 0x000fea000383ffff */
/*06a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06b0*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c0ff */
/*06c0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff088224 */
/* 0x000fe200078e0009 */
/*06d0*/ @!P0 BRA 0x7f0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*06e0*/ FSETP.GEU.FTZ.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fda0003f1e000 */
/*06f0*/ @!P0 MOV R8, 0x7fffffff ; /* 0x7fffffff00088802 */
/* 0x000fe20000000f00 */
/*0700*/ @!P0 BRA 0x7f0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0710*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fda0003f1c200 */
/*0720*/ @P0 FADD.FTZ R8, R9, 1 ; /* 0x3f80000009080421 */
/* 0x000fe20000010000 */
/*0730*/ @P0 BRA 0x7f0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0740*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fda0003f1d200 */
/*0750*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff088224 */
/* 0x000fe200078e0009 */
/*0760*/ @!P0 BRA 0x7f0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0770*/ FFMA R9, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009097823 */
/* 0x000fc800000000ff */
/*0780*/ MUFU.RSQ R8, R9 ; /* 0x0000000900087308 */
/* 0x000e240000001400 */
/*0790*/ FMUL.FTZ R10, R9, R8 ; /* 0x00000008090a7220 */
/* 0x001fe40000410000 */
/*07a0*/ FMUL.FTZ R8, R8, 0.5 ; /* 0x3f00000008087820 */
/* 0x000fe40000410000 */
/*07b0*/ FADD.FTZ R11, -R10, -RZ ; /* 0x800000ff0a0b7221 */
/* 0x000fc80000010100 */
/*07c0*/ FFMA R11, R10, R11, R9 ; /* 0x0000000b0a0b7223 */
/* 0x000fc80000000009 */
/*07d0*/ FFMA R8, R11, R8, R10 ; /* 0x000000080b087223 */
/* 0x000fc8000000000a */
/*07e0*/ FMUL.FTZ R8, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008087820 */
/* 0x000fc80000410000 */
/*07f0*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0008 */
/*0800*/ MOV R8, R12 ; /* 0x0000000c00087202 */
/* 0x000fe20000000f00 */
/*0810*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*0820*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff7d008007950 */
/* 0x000fea0003c3ffff */
/*0830*/ SHF.R.U32.HI R11, RZ, 0x17, R4 ; /* 0x00000017ff0b7819 */
/* 0x000fe20000011604 */
/*0840*/ BSSY B2, 0xe90 ; /* 0x0000064000027945 */
/* 0x000fe20003800000 */
/*0850*/ SHF.R.U32.HI R9, RZ, 0x17, R13.reuse ; /* 0x00000017ff097819 */
/* 0x100fe4000001160d */
/*0860*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fe400078ec0ff */
/*0870*/ LOP3.LUT R15, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff090f7812 */
/* 0x000fe200078ec0ff */
/*0880*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*0890*/ IADD3 R16, R11, -0x1, RZ ; /* 0xffffffff0b107810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R14, R15, -0x1, RZ ; /* 0xffffffff0f0e7810 */
/* 0x000fc40007ffe0ff */
/*08b0*/ ISETP.GT.U32.AND P0, PT, R16, 0xfd, PT ; /* 0x000000fd1000780c */
/* 0x000fe40003f04070 */
/*08c0*/ MOV R12, R4 ; /* 0x00000004000c7202 */
/* 0x000fe40000000f00 */
/*08d0*/ ISETP.GT.U32.OR P0, PT, R14, 0xfd, P0 ; /* 0x000000fd0e00780c */
/* 0x000fda0000704470 */
/*08e0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*08f0*/ @!P0 BRA 0xa70 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0900*/ FSETP.GTU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f1c200 */
/*0910*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*0920*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0930*/ @P0 BRA 0xe70 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R9, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c809 */
/*0950*/ @!P0 BRA 0xe50 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0960*/ FSETP.NEU.FTZ.AND P3, PT, |R13|.reuse, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x040fe40003f7d200 */
/*0970*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0980*/ FSETP.NEU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fd60003f1d200 */
/*0990*/ @!P1 BRA !P3, 0xe50 ; /* 0x000004b000009947 */
/* 0x000fea0005800000 */
/*09a0*/ LOP3.LUT P3, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000786c0ff */
/*09b0*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*09c0*/ @P1 BRA 0xe30 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*09e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*09f0*/ @P0 BRA 0xe00 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0a00*/ ISETP.GE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f06270 */
/*0a10*/ ISETP.GE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd60003f26270 */
/*0a20*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe200078e00ff */
/*0a30*/ @!P0 MOV R10, 0xffffffc0 ; /* 0xffffffc0000a8802 */
/* 0x000fe20000000f00 */
/*0a40*/ @!P0 FFMA R9, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d098823 */
/* 0x000fe400000000ff */
/*0a50*/ @!P1 FFMA R12, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f800000040c9823 */
/* 0x000fe200000000ff */
/*0a60*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ LEA R13, R11, 0xc0800000, 0x17 ; /* 0xc08000000b0d7811 */
/* 0x000fe200078eb8ff */
/*0a80*/ BSSY B3, 0xdf0 ; /* 0x0000036000037945 */
/* 0x000fe80003800000 */
/*0a90*/ IMAD.IADD R13, R12, 0x1, -R13 ; /* 0x000000010c0d7824 */
/* 0x000fe200078e0a0d */
/*0aa0*/ IADD3 R12, R15, -0x7f, RZ ; /* 0xffffff810f0c7810 */
/* 0x000fc60007ffe0ff */
/*0ab0*/ MUFU.RCP R14, R13 ; /* 0x0000000d000e7308 */
/* 0x0000620000001000 */
/*0ac0*/ FADD.FTZ R16, -R13, -RZ ; /* 0x800000ff0d107221 */
/* 0x000fe40000010100 */
/*0ad0*/ IMAD R9, R12.reuse, -0x800000, R9 ; /* 0xff8000000c097824 */
/* 0x040fe200078e0209 */
/*0ae0*/ IADD3 R13, R12, 0x7f, -R11 ; /* 0x0000007f0c0d7810 */
/* 0x001fc80007ffe80b */
/*0af0*/ IADD3 R10, R13, R10, RZ ; /* 0x0000000a0d0a7210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ FFMA R15, R14, R16, 1 ; /* 0x3f8000000e0f7423 */
/* 0x002fc80000000010 */
/*0b10*/ FFMA R18, R14, R15, R14 ; /* 0x0000000f0e127223 */
/* 0x000fc8000000000e */
/*0b20*/ FFMA R14, R9, R18, RZ ; /* 0x00000012090e7223 */
/* 0x000fc800000000ff */
/*0b30*/ FFMA R15, R16, R14, R9 ; /* 0x0000000e100f7223 */
/* 0x000fc80000000009 */
/*0b40*/ FFMA R15, R18, R15, R14 ; /* 0x0000000f120f7223 */
/* 0x000fc8000000000e */
/*0b50*/ FFMA R16, R16, R15, R9 ; /* 0x0000000f10107223 */
/* 0x000fc80000000009 */
/*0b60*/ FFMA R9, R18, R16, R15 ; /* 0x0000001012097223 */
/* 0x000fca000000000f */
/*0b70*/ SHF.R.U32.HI R11, RZ, 0x17, R9 ; /* 0x00000017ff0b7819 */
/* 0x000fc80000011609 */
/*0b80*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fca00078ec0ff */
/*0b90*/ IMAD.IADD R14, R11, 0x1, R10 ; /* 0x000000010b0e7824 */
/* 0x000fca00078e020a */
/*0ba0*/ IADD3 R11, R14, -0x1, RZ ; /* 0xffffffff0e0b7810 */
/* 0x000fc80007ffe0ff */
/*0bb0*/ ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f06070 */
/*0bc0*/ @!P0 BRA 0xdd0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ ISETP.GT.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f04270 */
/*0be0*/ @P0 BRA 0xda0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0bf0*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f06270 */
/*0c00*/ @P0 BRA 0xde0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0c10*/ ISETP.GE.AND P0, PT, R14, -0x18, PT ; /* 0xffffffe80e00780c */
/* 0x000fe40003f06270 */
/*0c20*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fd600078ec0ff */
/*0c30*/ @!P0 BRA 0xde0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0c40*/ FFMA.RZ R10, R18, R16.reuse, R15.reuse ; /* 0x00000010120a7223 */
/* 0x180fe2000000c00f */
/*0c50*/ IADD3 R13, R14, 0x20, RZ ; /* 0x000000200e0d7810 */
/* 0x000fe20007ffe0ff */
/*0c60*/ FFMA.RM R11, R18, R16.reuse, R15.reuse ; /* 0x00000010120b7223 */
/* 0x180fe2000000400f */
/*0c70*/ ISETP.NE.AND P3, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f65270 */
/*0c80*/ LOP3.LUT R12, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a0c7812 */
/* 0x000fe200078ec0ff */
/*0c90*/ FFMA.RP R10, R18, R16, R15 ; /* 0x00000010120a7223 */
/* 0x000fe2000000800f */
/*0ca0*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f25270 */
/*0cb0*/ LOP3.LUT R12, R12, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000c0c7812 */
/* 0x000fe400078efcff */
/*0cc0*/ IADD3 R14, -R14, RZ, RZ ; /* 0x000000ff0e0e7210 */
/* 0x000fc40007ffe1ff */
/*0cd0*/ SHF.L.U32 R13, R12, R13, RZ ; /* 0x0000000d0c0d7219 */
/* 0x000fe400000006ff */
/*0ce0*/ FSETP.NEU.FTZ.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720b */
/* 0x000fe40003f1d000 */
/*0cf0*/ SEL R11, R14, RZ, P3 ; /* 0x000000ff0e0b7207 */
/* 0x000fe40001800000 */
/*0d00*/ ISETP.NE.AND P1, PT, R13, RZ, P1 ; /* 0x000000ff0d00720c */
/* 0x000fe40000f25270 */
/*0d10*/ SHF.R.U32.HI R11, RZ, R11, R12 ; /* 0x0000000bff0b7219 */
/* 0x000fe4000001160c */
/*0d20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0d30*/ SHF.R.U32.HI R13, RZ, 0x1, R11 ; /* 0x00000001ff0d7819 */
/* 0x000fe4000001160b */
/*0d40*/ SEL R10, RZ, 0x1, !P0 ; /* 0x00000001ff0a7807 */
/* 0x000fc80004000000 */
/*0d50*/ LOP3.LUT R10, R10, 0x1, R13, 0xf8, !PT ; /* 0x000000010a0a7812 */
/* 0x000fc800078ef80d */
/*0d60*/ LOP3.LUT R10, R10, R11, RZ, 0xc0, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fca00078ec0ff */
/*0d70*/ IMAD.IADD R10, R13, 0x1, R10 ; /* 0x000000010d0a7824 */
/* 0x000fca00078e020a */
/*0d80*/ LOP3.LUT R9, R10, R9, RZ, 0xfc, !PT ; /* 0x000000090a097212 */
/* 0x000fe200078efcff */
/*0d90*/ BRA 0xde0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0da0*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fc800078ec0ff */
/*0db0*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*0dc0*/ BRA 0xde0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0dd0*/ LEA R9, R10, R9, 0x17 ; /* 0x000000090a097211 */
/* 0x000fe400078eb8ff */
/*0de0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0df0*/ BRA 0xe80 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e00*/ LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ; /* 0x800000000c097812 */
/* 0x000fc800078e4809 */
/*0e10*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*0e20*/ BRA 0xe80 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0e30*/ LOP3.LUT R9, R12, 0x80000000, R9, 0x48, !PT ; /* 0x800000000c097812 */
/* 0x000fe200078e4809 */
/*0e40*/ BRA 0xe80 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0e50*/ MUFU.RSQ R9, -QNAN ; /* 0xffc0000000097908 */
/* 0x000e220000001400 */
/*0e60*/ BRA 0xe80 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e70*/ FADD.FTZ R9, R13, R4 ; /* 0x000000040d097221 */
/* 0x000fe40000010000 */
/*0e80*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e90*/ IMAD.MOV.U32 R14, RZ, RZ, R9 ; /* 0x000000ffff0e7224 */
/* 0x001fe200078e0009 */
/*0ea0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fcc00000001ff */
/*0eb0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff14008007950 */
/* 0x000fea0003c3ffff */
/*0ec0*/ BRA 0xec0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18computeBezierLinesP10BezierLinei
.globl _Z18computeBezierLinesP10BezierLinei
.p2align 8
.type _Z18computeBezierLinesP10BezierLinei,@function
_Z18computeBezierLinesP10BezierLinei:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s2
s_cbranch_scc1 .LBB0_7
s_load_b64 s[4:5], s[0:1], 0x0
s_mul_i32 s2, s15, 0x120
s_mul_hi_i32 s3, s15, 0x120
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s4, s2
s_addc_u32 s7, s5, s3
s_clause 0x1
s_load_b128 s[8:11], s[6:7], 0x0
s_load_b64 s[2:3], s[6:7], 0x10
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v1, s9, s3
v_sub_f32_e64 v2, s3, s9
v_add_f32_e64 v3, s8, s2
v_sub_f32_e64 v4, s2, s8
s_mov_b32 s8, 0
v_fma_f32 v1, v1, -0.5, s11
v_mul_f32_e32 v2, v2, v2
v_fma_f32 v3, v3, -0.5, s10
s_mul_hi_i32 s9, s15, 0x120
s_mul_i32 s11, s15, 0x120
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v1, v1, v1 :: v_dual_fmac_f32 v2, v4, v4
v_fmac_f32_e32 v1, v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_mul_f32_e32 v4, 0x4f800000, v1
v_cmp_gt_f32_e64 s2, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cndmask_b32_e64 v1, v1, v4, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sqrt_f32_e32 v3, v2
v_sqrt_f32_e32 v4, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v3
v_add_nc_u32_e32 v7, 1, v3
v_add_nc_u32_e32 v6, -1, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v9, -v5, v3, v2
v_add_nc_u32_e32 v8, 1, v4
v_fma_f32 v11, -v7, v3, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v10, -v6, v4, v1
v_cmp_ge_f32_e64 s3, 0, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v8, v4, v1
v_cndmask_b32_e64 v3, v3, v5, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s3, 0, v10
v_cndmask_b32_e64 v4, v4, v6, s3
v_cmp_lt_f32_e64 s3, 0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v3, v7, s3
v_cmp_lt_f32_e64 s3, 0, v12
v_mul_f32_e32 v5, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v8, s3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_mul_f32 v6, 0x37800000, v4
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v6, s2
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v4, v1, vcc_lo
v_div_scale_f32 v3, null, v2, v2, v1
v_div_scale_f32 v6, vcc_lo, v1, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v3, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v3, v3, v4, v5
v_mov_b32_e32 v5, 0
v_div_fixup_f32 v1, v3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0x41800000, v1
v_cvt_i32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_med3_i32 v6, v1, 4, 32
global_store_b32 v5, v6, s[6:7] offset:280
s_load_b32 s2, s[0:1], 0x1c
v_add_nc_u32_e32 v1, -1, v6
s_add_u32 s0, s6, 4
s_addc_u32 s1, s7, 0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v7, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s12
s_add_i32 s8, s8, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, s8, v6
s_cbranch_vccz .LBB0_7
.LBB0_3:
v_add_nc_u32_e32 v1, s8, v0
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v1, v6
s_cbranch_execz .LBB0_2
v_cvt_f32_i32_e32 v2, v1
s_mov_b64 s[2:3], 0
s_mov_b64 s[6:7], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v7, v7, v2
v_div_scale_f32 v9, vcc_lo, v2, v7, v2
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v8, v4
v_mul_f32_e32 v8, v9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v3, v8, v9
v_fmac_f32_e32 v8, v10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v8, v9
v_div_fmas_f32 v3, v3, v4, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v7, v2
v_dual_mov_b32 v3, 0 :: v_dual_sub_f32 v4, 1.0, v2
v_add_f32_e32 v9, v2, v2
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v8, v4, v4
v_dual_mul_f32 v9, v9, v4 :: v_dual_mov_b32 v4, 0
.p2align 6
.LBB0_5:
s_clause 0x1
global_load_b32 v10, v5, s[6:7] offset:-4
global_load_b32 v11, v5, s[6:7]
s_cmp_eq_u32 s2, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s2, 2
v_cndmask_b32_e32 v12, v8, v9, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_add_u32 s6, s6, 8
v_cndmask_b32_e32 v12, v12, v2, vcc_lo
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 3
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v12, v10
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v12, v11
s_cbranch_scc0 .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_add_u32 s2, s4, s11
s_addc_u32 s3, s5, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b64 v[1:2], v[3:4], off offset:24
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18computeBezierLinesP10BezierLinei
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18computeBezierLinesP10BezierLinei, .Lfunc_end0-_Z18computeBezierLinesP10BezierLinei
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18computeBezierLinesP10BezierLinei
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18computeBezierLinesP10BezierLinei.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00064377_00000000-6_bezier_curve.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16computeCurvatureP10BezierLine
.type _Z16computeCurvatureP10BezierLine, @function
_Z16computeCurvatureP10BezierLine:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z16computeCurvatureP10BezierLine, .-_Z16computeCurvatureP10BezierLine
.globl _Z16initializeBLinesP10BezierLine
.type _Z16initializeBLinesP10BezierLine, @function
_Z16initializeBLinesP10BezierLine:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq 73728(%rdi), %rbp
pxor %xmm0, %xmm0
movaps %xmm0, %xmm1
.L6:
movss %xmm1, (%rbx)
movss %xmm0, 4(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 12(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 16(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 20(%rbx)
movss 16(%rbx), %xmm1
movl $0, 280(%rbx)
addq $288, %rbx
cmpq %rbp, %rbx
jne .L6
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z16initializeBLinesP10BezierLine, .-_Z16initializeBLinesP10BezierLine
.globl _Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei
.type _Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei, @function
_Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18computeBezierLinesP10BezierLinei(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei, .-_Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei
.globl _Z18computeBezierLinesP10BezierLinei
.type _Z18computeBezierLinesP10BezierLinei, @function
_Z18computeBezierLinesP10BezierLinei:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z18computeBezierLinesP10BezierLinei, .-_Z18computeBezierLinesP10BezierLinei
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $73728, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rax, %rdi
call _Z16initializeBLinesP10BezierLine
leaq 8(%rsp), %rdi
movl $73728, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $73728, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $256, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $256, %esi
movq 8(%rsp), %rdi
call _Z50__device_stub__Z18computeBezierLinesP10BezierLineiP10BezierLinei
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z18computeBezierLinesP10BezierLinei"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z18computeBezierLinesP10BezierLinei(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bezier_curve.hip"
.globl _Z33__device_stub__computeBezierLinesP10BezierLinei # -- Begin function _Z33__device_stub__computeBezierLinesP10BezierLinei
.p2align 4, 0x90
.type _Z33__device_stub__computeBezierLinesP10BezierLinei,@function
_Z33__device_stub__computeBezierLinesP10BezierLinei: # @_Z33__device_stub__computeBezierLinesP10BezierLinei
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18computeBezierLinesP10BezierLinei, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z33__device_stub__computeBezierLinesP10BezierLinei, .Lfunc_end0-_Z33__device_stub__computeBezierLinesP10BezierLinei
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z16initializeBLinesP10BezierLine
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z16initializeBLinesP10BezierLine
.p2align 4, 0x90
.type _Z16initializeBLinesP10BezierLine,@function
_Z16initializeBLinesP10BezierLine: # @_Z16initializeBLinesP10BezierLine
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
leaq 12(%rdi), %r14
xorps %xmm0, %xmm0
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
leaq (%r15,%r15,8), %r12
shlq $5, %r12
leaq (%rbx,%r12), %r13
movlps %xmm0, (%rbx,%r12)
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -4(%r14,%rbp,8)
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%rbp,8)
incq %rbp
cmpq $2, %rbp
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movsd 16(%r13), %xmm0 # xmm0 = mem[0],zero
movl $0, 280(%rbx,%r12)
incq %r15
addq $288, %r14 # imm = 0x120
cmpq $256, %r15 # imm = 0x100
jne .LBB1_1
# %bb.4:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16initializeBLinesP10BezierLine, .Lfunc_end1-_Z16initializeBLinesP10BezierLine
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $73728, %edi # imm = 0x12000
callq _Znam
movq %rax, %rbx
leaq 12(%rax), %r14
xorps %xmm0, %xmm0
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
leaq (%r15,%r15,8), %r12
shlq $5, %r12
leaq (%rbx,%r12), %r13
movlps %xmm0, (%rbx,%r12)
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss %xmm0, -4(%r14,%rbp,8)
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%rbp,8)
incq %rbp
cmpq $2, %rbp
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movsd 16(%r13), %xmm0 # xmm0 = mem[0],zero
movl $0, 280(%rbx,%r12)
incq %r15
addq $288, %r14 # imm = 0x120
cmpq $256, %r15 # imm = 0x100
jne .LBB2_1
# %bb.4: # %_Z16initializeBLinesP10BezierLine.exit
leaq 8(%rsp), %rdi
movl $73728, %esi # imm = 0x12000
callq hipMalloc
movq 8(%rsp), %rdi
movl $73728, %edx # imm = 0x12000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 224(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $256, 20(%rsp) # imm = 0x100
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18computeBezierLinesP10BezierLinei, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18computeBezierLinesP10BezierLinei, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18computeBezierLinesP10BezierLinei,@object # @_Z18computeBezierLinesP10BezierLinei
.section .rodata,"a",@progbits
.globl _Z18computeBezierLinesP10BezierLinei
.p2align 3, 0x0
_Z18computeBezierLinesP10BezierLinei:
.quad _Z33__device_stub__computeBezierLinesP10BezierLinei
.size _Z18computeBezierLinesP10BezierLinei, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18computeBezierLinesP10BezierLinei"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__computeBezierLinesP10BezierLinei
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18computeBezierLinesP10BezierLinei
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <thrust/extrema.h>
#include <thrust/device_vector.h>
struct type {
int key;
int value;
};
struct comparator {
__host__ __device__ bool operator()(type a, type b) {
return a.key < b.key;
}
};
int main() {
srand(time(NULL));
comparator comp;
int i, i_max = -1, n = 100000;
type *arr = (type *)malloc(sizeof(type) * n);
for(i = 0; i < n; i++) {
arr[i].key = 5;
arr[i].value = 5;
if (i_max == -1 || comp(arr[i_max], arr[i]))
i_max = i;
}
type *dev_arr;
cudaMalloc(&dev_arr, sizeof(type) * n);
cudaMemcpy(dev_arr, arr, sizeof(type) * n, cudaMemcpyHostToDevice);
thrust::device_ptr<type> p_arr = thrust::device_pointer_cast(dev_arr);
thrust::device_ptr<type> res = thrust::max_element(p_arr, p_arr + n,comp);
int pos = (int)(res - p_arr);
printf("cpu: %d\ngpu: %d\n", i_max, pos);
printf("%d\n", arr[pos].key);
cudaFree(dev_arr);
free(arr);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <thrust/extrema.h>
#include <thrust/device_vector.h>
struct type {
int key;
int value;
};
struct comparator {
__host__ __device__ bool operator()(type a, type b) {
return a.key < b.key;
}
};
int main() {
srand(time(NULL));
comparator comp;
int i, i_max = -1, n = 100000;
type *arr = (type *)malloc(sizeof(type) * n);
for(i = 0; i < n; i++) {
arr[i].key = 5;
arr[i].value = 5;
if (i_max == -1 || comp(arr[i_max], arr[i]))
i_max = i;
}
type *dev_arr;
hipMalloc(&dev_arr, sizeof(type) * n);
hipMemcpy(dev_arr, arr, sizeof(type) * n, hipMemcpyHostToDevice);
thrust::device_ptr<type> p_arr = thrust::device_pointer_cast(dev_arr);
thrust::device_ptr<type> res = thrust::max_element(p_arr, p_arr + n,comp);
int pos = (int)(res - p_arr);
printf("cpu: %d\ngpu: %d\n", i_max, pos);
printf("%d\n", arr[pos].key);
hipFree(dev_arr);
free(arr);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void LSTMDeltaKernel( float *cellStateErrors, float *outputGateDeltas, float *cellStates, float *outputGateActivations, float *outputGateActivationDerivatives, float *deltas, int cellCount, int cellsPerBlock )
{
int memoryBlockId = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (memoryBlockId < cellCount / cellsPerBlock)
{
float outputGateDeltaSum = 0.0;
for (int cellId = memoryBlockId * cellsPerBlock; cellId < (memoryBlockId + 1) * cellsPerBlock; cellId++)
{
float delta = deltas[cellId];
cellStateErrors[cellId] = outputGateActivations[memoryBlockId] * delta;
outputGateDeltaSum += cellStates[cellId] * delta;
}
outputGateDeltas[memoryBlockId] = outputGateActivationDerivatives[memoryBlockId] * outputGateDeltaSum;
}
} | code for sm_80
Function : _Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R7, c[0x0][0x194] ; /* 0x0000650000077a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC.64 UR4, c[0x0][0x190] ; /* 0x0000640000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fe2000f8e3c3f */
/*0040*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e2a0000209400 */
/*0050*/ ISETP.LE.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf43270 */
/*0060*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00a0*/ IADD3 R4, RZ, -R3, RZ ; /* 0x80000003ff047210 */
/* 0x002fca0007ffe0ff */
/*00b0*/ IMAD R5, R4, R7, RZ ; /* 0x0000000704057224 */
/* 0x000fe200078e02ff */
/*00c0*/ IABS R4, c[0x0][0x190] ; /* 0x0000640000047a13 */
/* 0x000fc60000000000 */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe400078e0002 */
/*00e0*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*00f0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fe200078e00ff */
/*0100*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0110*/ IADD3 R0, -R3, RZ, RZ ; /* 0x000000ff03007210 */
/* 0x000fca0007ffe1ff */
/*0120*/ IMAD R0, R7, R0, R4 ; /* 0x0000000007007224 */
/* 0x000fca00078e0204 */
/*0130*/ ISETP.GT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f24070 */
/*0140*/ @!P1 IADD3 R0, R0, -R7.reuse, RZ ; /* 0x8000000700009210 */
/* 0x080fe40007ffe0ff */
/*0150*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe20003f06070 */
/*0170*/ IMAD R0, R2, c[0x0][0xc], R5 ; /* 0x0000030002007a24 */
/* 0x001fe200078e0205 */
/*0180*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0190*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x194], PT ; /* 0x00006500ff007a0c */
/* 0x000fd40003f25270 */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ @!P2 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff0303a210 */
/* 0x000fe40007ffe1ff */
/*01c0*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x194], RZ, 0x33, !PT ; /* 0x00006500ff039a12 */
/* 0x000fe200078e33ff */
/*01d0*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0207 */
/*01e0*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06270 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ IMAD R11, R0, c[0x0][0x194], RZ ; /* 0x00006500000b7a24 */
/* 0x000fe200078e02ff */
/*0210*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0220*/ BSSY B0, 0x1200 ; /* 0x00000fd000007945 */
/* 0x000fe60003800000 */
/*0230*/ IADD3 R10, R11, c[0x0][0x194], RZ ; /* 0x000065000b0a7a10 */
/* 0x000fc80007ffe0ff */
/*0240*/ ISETP.GE.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fda0003f06270 */
/*0250*/ @P0 MOV R13, RZ ; /* 0x000000ff000d0202 */
/* 0x000fe20000000f00 */
/*0260*/ @P0 BRA 0x11f0 ; /* 0x00000f8000000947 */
/* 0x000fea0003800000 */
/*0270*/ MOV R3, c[0x0][0x194] ; /* 0x0000650000037a02 */
/* 0x000fe40000000f00 */
/*0280*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fe40000000f00 */
/*0290*/ IADD3 R2, R3.reuse, -0x1, RZ ; /* 0xffffffff03027810 */
/* 0x040fe40007ffe0ff */
/*02a0*/ LOP3.LUT P1, R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fe4000782c0ff */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*02c0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*02d0*/ IMAD.WIDE R4, R0, R2, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0202 */
/*02e0*/ @!P1 BRA 0x4d0 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.WIDE R12, R11, R2, c[0x0][0x188] ; /* 0x000062000b0c7625 */
/* 0x000fc800078e0202 */
/*0300*/ IMAD.WIDE R6, R11.reuse, R2, c[0x0][0x160] ; /* 0x000058000b067625 */
/* 0x040fe200078e0202 */
/*0310*/ MOV R17, R13 ; /* 0x0000000d00117202 */
/* 0x000fe40000000f00 */
/*0320*/ MOV R14, R12 ; /* 0x0000000c000e7202 */
/* 0x000fe20000000f00 */
/*0330*/ IMAD.WIDE R8, R11, R2, c[0x0][0x170] ; /* 0x00005c000b087625 */
/* 0x000fe200078e0202 */
/*0340*/ MOV R16, R6 ; /* 0x0000000600107202 */
/* 0x000fe40000000f00 */
/*0350*/ MOV R19, R7 ; /* 0x0000000700137202 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD.MOV.U32 R21, RZ, RZ, R9 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0009 */
/*0370*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fe40000000f00 */
/*0380*/ MOV R6, R14 ; /* 0x0000000e00067202 */
/* 0x000fe20000000f00 */
/*0390*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ MOV R7, R17 ; /* 0x0000001100077202 */
/* 0x000fca0000000f00 */
/*03b0*/ LDG.E R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x0000a4000c1e1900 */
/*03c0*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x001fe200078e0010 */
/*03d0*/ MOV R7, R19 ; /* 0x0000001300077202 */
/* 0x000fe20000000f00 */
/*03e0*/ FMUL R15, R9, R12 ; /* 0x0000000c090f7220 */
/* 0x004fe20000400000 */
/*03f0*/ MOV R9, R21 ; /* 0x0000001500097202 */
/* 0x000fc80000000f00 */
/*0400*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e8000c101904 */
/*0410*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x0002a2000c1e1900 */
/*0420*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0430*/ IADD3 R16, P3, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fe40007f7e0ff */
/*0440*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f25270 */
/*0450*/ IADD3 R14, P4, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc40007f9e0ff */
/*0460*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x002fe40007f5e0ff */
/*0480*/ IADD3.X R19, RZ, R19, RZ, P3, !PT ; /* 0x00000013ff137210 */
/* 0x000fe40001ffe4ff */
/*0490*/ IADD3.X R21, RZ, R21, RZ, P2, !PT ; /* 0x00000015ff157210 */
/* 0x000fe400017fe4ff */
/*04a0*/ IADD3.X R17, RZ, R17, RZ, P4, !PT ; /* 0x00000011ff117210 */
/* 0x000fe200027fe4ff */
/*04b0*/ FFMA R13, R12, R9, R13 ; /* 0x000000090c0d7223 */
/* 0x004fe2000000000d */
/*04c0*/ @P1 BRA 0x380 ; /* 0xfffffeb000001947 */
/* 0x001fea000383ffff */
/*04d0*/ @!P0 BRA 0x11f0 ; /* 0x00000d1000008947 */
/* 0x000fea0003800000 */
/*04e0*/ IADD3 R3, R10, -R11, RZ ; /* 0x8000000b0a037210 */
/* 0x000fe20007ffe0ff */
/*04f0*/ IMAD.WIDE R6, R11, R2, c[0x2][0x0] ; /* 0x008000000b067625 */
/* 0x000fe200078e0202 */
/*0500*/ BSSY B1, 0xc70 ; /* 0x0000076000017945 */
/* 0x000fe40003800000 */
/*0510*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fc40003f24270 */
/*0520*/ IADD3 R2, P0, R6.reuse, c[0x0][0x188], RZ ; /* 0x0000620006027a10 */
/* 0x040fe40007f1e0ff */
/*0530*/ IADD3 R8, P2, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006087a10 */
/* 0x040fe40007f5e0ff */
/*0540*/ IADD3 R6, P3, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe40007f7e0ff */
/*0550*/ IADD3.X R3, R7.reuse, c[0x0][0x18c], RZ, P0, !PT ; /* 0x0000630007037a10 */
/* 0x040fe400007fe4ff */
/*0560*/ IADD3.X R9, R7.reuse, c[0x0][0x164], RZ, P2, !PT ; /* 0x0000590007097a10 */
/* 0x040fe400017fe4ff */
/*0570*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0007077a10 */
/* 0x000fc40001ffe4ff */
/*0580*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*0590*/ @!P1 BRA 0xc60 ; /* 0x000006c000009947 */
/* 0x000fee0003800000 */
/*05a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*05b0*/ IADD3 R12, R10, -0xc, RZ ; /* 0xfffffff40a0c7810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ LDG.E R15, [R4.64] ; /* 0x00000004040f7981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R16, [R2.64+-0x8] ; /* 0xfffff80402107981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ FMUL R17, R15, R16 ; /* 0x000000100f117220 */
/* 0x004fca0000400000 */
/*05f0*/ STG.E [R8.64+-0x8], R17 ; /* 0xfffff81108007986 */
/* 0x0001e8000c101904 */
/*0600*/ LDG.E R15, [R4.64] ; /* 0x00000004040f7981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R14, [R2.64+-0x4] ; /* 0xfffffc04020e7981 */
/* 0x000ea8000c1e1900 */
/*0620*/ LDG.E R18, [R6.64+-0x8] ; /* 0xfffff80406127981 */
/* 0x000ee2000c1e1900 */
/*0630*/ FMUL R21, R15, R14 ; /* 0x0000000e0f157220 */
/* 0x004fca0000400000 */
/*0640*/ STG.E [R8.64+-0x4], R21 ; /* 0xfffffc1508007986 */
/* 0x0003e8000c101904 */
/*0650*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R25, [R6.64+-0x4] ; /* 0xfffffc0406197981 */
/* 0x000f22000c1e1900 */
/*0680*/ FMUL R27, R20, R15 ; /* 0x0000000f141b7220 */
/* 0x004fca0000400000 */
/*0690*/ STG.E [R8.64], R27 ; /* 0x0000001b08007986 */
/* 0x0005e8000c101904 */
/*06a0*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000e28000c1e1900 */
/*06b0*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040402137981 */
/* 0x000e28000c1e1900 */
/*06c0*/ LDG.E R26, [R6.64] ; /* 0x00000004061a7981 */
/* 0x000f62000c1e1900 */
/*06d0*/ FMUL R17, R20, R19 ; /* 0x0000001314117220 */
/* 0x001fca0000400000 */
/*06e0*/ STG.E [R8.64+0x4], R17 ; /* 0x0000041108007986 */
/* 0x0001e8000c101904 */
/*06f0*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080402177981 */
/* 0x000ea4000c1e1900 */
/*0710*/ FMUL R29, R20, R23 ; /* 0x00000017141d7220 */
/* 0x004fc40000400000 */
/*0720*/ LDG.E R20, [R6.64+0x4] ; /* 0x0000040406147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ STG.E [R8.64+0x8], R29 ; /* 0x0000081d08007986 */
/* 0x0001e8000c101904 */
/*0740*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000ea8000c1e1900 */
/*0750*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x002ea8000c1e1900 */
/*0760*/ LDG.E R24, [R6.64+0x8] ; /* 0x0000080406187981 */
/* 0x000ee2000c1e1900 */
/*0770*/ FMUL R27, R22, R21 ; /* 0x00000015161b7220 */
/* 0x004fca0000400000 */
/*0780*/ STG.E [R8.64+0xc], R27 ; /* 0x00000c1b08007986 */
/* 0x0003e8000c101904 */
/*0790*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R17, [R2.64+0x10] ; /* 0x0000100402117981 */
/* 0x001ea2000c1e1900 */
/*07b0*/ FFMA R18, R16, R18, R13 ; /* 0x0000001210127223 */
/* 0x008fe4000000000d */
/*07c0*/ FMUL R13, R22, R17 ; /* 0x00000011160d7220 */
/* 0x004fc40000400000 */
/*07d0*/ LDG.E R22, [R6.64+0xc] ; /* 0x00000c0406167981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ STG.E [R8.64+0x10], R13 ; /* 0x0000100d08007986 */
/* 0x0001e8000c101904 */
/*07f0*/ LDG.E R29, [R4.64] ; /* 0x00000004041d7981 */
/* 0x000ee8000c1e1900 */
/*0800*/ LDG.E R16, [R2.64+0x14] ; /* 0x0000140402107981 */
/* 0x000ee2000c1e1900 */
/*0810*/ FFMA R25, R14, R25, R18 ; /* 0x000000190e197223 */
/* 0x010fc60000000012 */
/*0820*/ LDG.E R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000f22000c1e1900 */
/*0830*/ FMUL R29, R29, R16 ; /* 0x000000101d1d7220 */
/* 0x008fca0000400000 */
/*0840*/ STG.E [R8.64+0x14], R29 ; /* 0x0000141d08007986 */
/* 0x0007e8000c101904 */
/*0850*/ LDG.E R27, [R4.64] ; /* 0x00000004041b7981 */
/* 0x002ea8000c1e1900 */
/*0860*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000ea2000c1e1900 */
/*0870*/ FFMA R25, R15, R26, R25 ; /* 0x0000001a0f197223 */
/* 0x020fc60000000019 */
/*0880*/ LDG.E R13, [R6.64+0x14] ; /* 0x00001404060d7981 */
/* 0x001f62000c1e1900 */
/*0890*/ FMUL R27, R27, R14 ; /* 0x0000000e1b1b7220 */
/* 0x004fca0000400000 */
/*08a0*/ STG.E [R8.64+0x18], R27 ; /* 0x0000181b08007986 */
/* 0x0001e8000c101904 */
/*08b0*/ LDG.E R26, [R4.64] ; /* 0x00000004041a7981 */
/* 0x000ea8000c1e1900 */
/*08c0*/ LDG.E R15, [R2.64+0x1c] ; /* 0x00001c04020f7981 */
/* 0x000ea2000c1e1900 */
/*08d0*/ FFMA R25, R19, R20, R25 ; /* 0x0000001413197223 */
/* 0x000fc60000000019 */
/*08e0*/ LDG.E R19, [R6.64+0x18] ; /* 0x0000180406137981 */
/* 0x000ee2000c1e1900 */
/*08f0*/ FMUL R26, R26, R15 ; /* 0x0000000f1a1a7220 */
/* 0x004fca0000400000 */
/*0900*/ STG.E [R8.64+0x1c], R26 ; /* 0x00001c1a08007986 */
/* 0x0003e8000c101904 */
/*0910*/ LDG.E R29, [R4.64] ; /* 0x00000004041d7981 */
/* 0x008ea8000c1e1900 */
/*0920*/ LDG.E R20, [R2.64+0x20] ; /* 0x0000200402147981 */
/* 0x000ea2000c1e1900 */
/*0930*/ FFMA R25, R23, R24, R25 ; /* 0x0000001817197223 */
/* 0x000fc60000000019 */
/*0940*/ LDG.E R24, [R6.64+0x1c] ; /* 0x00001c0406187981 */
/* 0x000ee2000c1e1900 */
/*0950*/ FMUL R29, R29, R20 ; /* 0x000000141d1d7220 */
/* 0x004fca0000400000 */
/*0960*/ STG.E [R8.64+0x20], R29 ; /* 0x0000201d08007986 */
/* 0x0005e8000c101904 */
/*0970*/ LDG.E R28, [R4.64] ; /* 0x00000004041c7981 */
/* 0x000e28000c1e1900 */
/*0980*/ LDG.E R23, [R2.64+0x24] ; /* 0x0000240402177981 */
/* 0x000e22000c1e1900 */
/*0990*/ FFMA R25, R21, R22, R25 ; /* 0x0000001615197223 */
/* 0x000fc60000000019 */
/*09a0*/ LDG.E R21, [R6.64+0x20] ; /* 0x0000200406157981 */
/* 0x000ea2000c1e1900 */
/*09b0*/ FMUL R27, R28, R23 ; /* 0x000000171c1b7220 */
/* 0x001fca0000400000 */
/*09c0*/ STG.E [R8.64+0x24], R27 ; /* 0x0000241b08007986 */
/* 0x0001e8000c101904 */
/*09d0*/ LDG.E R26, [R4.64] ; /* 0x00000004041a7981 */
/* 0x002ea8000c1e1900 */
/*09e0*/ LDG.E R22, [R2.64+0x28] ; /* 0x0000280402167981 */
/* 0x000ea2000c1e1900 */
/*09f0*/ FFMA R25, R17, R18, R25 ; /* 0x0000001211197223 */
/* 0x010fc60000000019 */
/*0a00*/ LDG.E R18, [R6.64+0x24] ; /* 0x0000240406127981 */
/* 0x000f22000c1e1900 */
/*0a10*/ FMUL R26, R26, R22 ; /* 0x000000161a1a7220 */
/* 0x004fca0000400000 */
/*0a20*/ STG.E [R8.64+0x28], R26 ; /* 0x0000281a08007986 */
/* 0x0003e8000c101904 */
/*0a30*/ LDG.E R28, [R4.64] ; /* 0x00000004041c7981 */
/* 0x000ea8000c1e1900 */
/*0a40*/ LDG.E R17, [R2.64+0x2c] ; /* 0x00002c0402117981 */
/* 0x000ea2000c1e1900 */
/*0a50*/ FFMA R25, R16, R13, R25 ; /* 0x0000000d10197223 */
/* 0x020fc60000000019 */
/*0a60*/ LDG.E R13, [R6.64+0x28] ; /* 0x00002804060d7981 */
/* 0x000f62000c1e1900 */
/*0a70*/ FMUL R29, R28, R17 ; /* 0x000000111c1d7220 */
/* 0x004fca0000400000 */
/*0a80*/ STG.E [R8.64+0x2c], R29 ; /* 0x00002c1d08007986 */
/* 0x000fe8000c101904 */
/*0a90*/ LDG.E R27, [R4.64] ; /* 0x00000004041b7981 */
/* 0x001ea8000c1e1900 */
/*0aa0*/ LDG.E R16, [R2.64+0x30] ; /* 0x0000300402107981 */
/* 0x000ea2000c1e1900 */
/*0ab0*/ FFMA R19, R14, R19, R25 ; /* 0x000000130e137223 */
/* 0x000fc60000000019 */
/*0ac0*/ LDG.E R26, [R6.64+0x2c] ; /* 0x00002c04061a7981 */
/* 0x002ee2000c1e1900 */
/*0ad0*/ FMUL R27, R27, R16 ; /* 0x000000101b1b7220 */
/* 0x004fca0000400000 */
/*0ae0*/ STG.E [R8.64+0x30], R27 ; /* 0x0000301b08007986 */
/* 0x000fe8000c101904 */
/*0af0*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000ea8000c1e1900 */
/*0b00*/ LDG.E R14, [R2.64+0x34] ; /* 0x00003404020e7981 */
/* 0x0000a2000c1e1900 */
/*0b10*/ FFMA R24, R15, R24, R19 ; /* 0x000000180f187223 */
/* 0x008fc60000000013 */
/*0b20*/ LDG.E R15, [R6.64+0x30] ; /* 0x00003004060f7981 */
/* 0x0002e2000c1e1900 */
/*0b30*/ FFMA R21, R20, R21, R24 ; /* 0x0000001514157223 */
/* 0x000fe20000000018 */
/*0b40*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ IADD3 R2, P1, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe20007f3e0ff */
/*0b60*/ FMUL R25, R25, R14 ; /* 0x0000000e19197220 */
/* 0x004fca0000400000 */
/*0b70*/ STG.E [R8.64+0x34], R25 ; /* 0x0000341908007986 */
/* 0x0001e8000c101904 */
/*0b80*/ LDG.E R19, [R6.64+0x34] ; /* 0x0000340406137981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ FFMA R18, R23, R18, R21 ; /* 0x0000001217127223 */
/* 0x010fe20000000015 */
/*0ba0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe40000ffe4ff */
/*0bb0*/ ISETP.GE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe20003f26270 */
/*0bc0*/ FFMA R13, R22, R13, R18 ; /* 0x0000000d160d7223 */
/* 0x020fc80000000012 */
/*0bd0*/ FFMA R13, R17, R26, R13 ; /* 0x0000001a110d7223 */
/* 0x000fe2000000000d */
/*0be0*/ IADD3 R17, P2, R8, 0x40, RZ ; /* 0x0000004008117810 */
/* 0x000fe40007f5e0ff */
/*0bf0*/ IADD3 R6, P3, R6, 0x40, RZ ; /* 0x0000004006067810 */
/* 0x002fe20007f7e0ff */
/*0c00*/ FFMA R13, R16, R15, R13 ; /* 0x0000000f100d7223 */
/* 0x008fe2000000000d */
/*0c10*/ MOV R8, R17 ; /* 0x0000001100087202 */
/* 0x001fe20000000f00 */
/*0c20*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0c30*/ IADD3.X R7, RZ, R7, RZ, P3, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20001ffe4ff */
/*0c40*/ FFMA R13, R14, R19, R13 ; /* 0x000000130e0d7223 */
/* 0x004fe2000000000d */
/*0c50*/ @!P1 BRA 0x5c0 ; /* 0xfffff96000009947 */
/* 0x000fea000383ffff */
/*0c60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c70*/ IADD3 R12, R10, -R11, RZ ; /* 0x8000000b0a0c7210 */
/* 0x000fe20007ffe0ff */
/*0c80*/ BSSY B1, 0x1050 ; /* 0x000003c000017945 */
/* 0x000fe60003800000 */
/*0c90*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*0ca0*/ @!P1 BRA 0x1040 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*0cb0*/ LDG.E R15, [R4.64] ; /* 0x00000004040f7981 */
/* 0x000ea8000c1e1900 */
/*0cc0*/ LDG.E R22, [R2.64+-0x8] ; /* 0xfffff80402167981 */
/* 0x000ea4000c1e1900 */
/*0cd0*/ FMUL R15, R15, R22 ; /* 0x000000160f0f7220 */
/* 0x004fca0000400000 */
/*0ce0*/ STG.E [R8.64+-0x8], R15 ; /* 0xfffff80f08007986 */
/* 0x0001e8000c101904 */
/*0cf0*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea8000c1e1900 */
/*0d00*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc04020c7981 */
/* 0x000ea8000c1e1900 */
/*0d10*/ LDG.E R24, [R6.64+-0x8] ; /* 0xfffff80406187981 */
/* 0x000ee2000c1e1900 */
/*0d20*/ FMUL R17, R17, R12 ; /* 0x0000000c11117220 */
/* 0x004fca0000400000 */
/*0d30*/ STG.E [R8.64+-0x4], R17 ; /* 0xfffffc1108007986 */
/* 0x0003e8000c101904 */
/*0d40*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x000ea8000c1e1900 */
/*0d50*/ LDG.E R20, [R2.64] ; /* 0x0000000402147981 */
/* 0x000ea8000c1e1900 */
/*0d60*/ LDG.E R23, [R6.64+-0x4] ; /* 0xfffffc0406177981 */
/* 0x000f22000c1e1900 */
/*0d70*/ FMUL R25, R19, R20 ; /* 0x0000001413197220 */
/* 0x004fca0000400000 */
/*0d80*/ STG.E [R8.64], R25 ; /* 0x0000001908007986 */
/* 0x0005e8000c101904 */
/*0d90*/ LDG.E R15, [R4.64] ; /* 0x00000004040f7981 */
/* 0x001f68000c1e1900 */
/*0da0*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000f68000c1e1900 */
/*0db0*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000ea2000c1e1900 */
/*0dc0*/ FMUL R27, R15, R18 ; /* 0x000000120f1b7220 */
/* 0x020fca0000400000 */
/*0dd0*/ STG.E [R8.64+0x4], R27 ; /* 0x0000041b08007986 */
/* 0x0001e8000c101904 */
/*0de0*/ LDG.E R15, [R4.64] ; /* 0x00000004040f7981 */
/* 0x000f68000c1e1900 */
/*0df0*/ LDG.E R16, [R2.64+0x8] ; /* 0x0000080402107981 */
/* 0x000f68000c1e1900 */
/*0e00*/ LDG.E R19, [R6.64+0x4] ; /* 0x0000040406137981 */
/* 0x000ea2000c1e1900 */
/*0e10*/ FMUL R29, R15, R16 ; /* 0x000000100f1d7220 */
/* 0x020fca0000400000 */
/*0e20*/ STG.E [R8.64+0x8], R29 ; /* 0x0000081d08007986 */
/* 0x000be8000c101904 */
/*0e30*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*0e40*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f7981 */
/* 0x000ea8000c1e1900 */
/*0e50*/ LDG.E R17, [R6.64+0x8] ; /* 0x0000080406117981 */
/* 0x002ee2000c1e1900 */
/*0e60*/ FMUL R28, R14, R15 ; /* 0x0000000f0e1c7220 */
/* 0x004fca0000400000 */
/*0e70*/ STG.E [R8.64+0xc], R28 ; /* 0x00000c1c08007986 */
/* 0x000fe8000c101904 */
/*0e80*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x000e28000c1e1900 */
/*0e90*/ LDG.E R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000e22000c1e1900 */
/*0ea0*/ FFMA R26, R22, R24, R13 ; /* 0x00000018161a7223 */
/* 0x008fc6000000000d */
/*0eb0*/ LDG.E R24, [R6.64+0xc] ; /* 0x00000c0406187981 */
/* 0x000ea2000c1e1900 */
/*0ec0*/ FMUL R27, R25, R14 ; /* 0x0000000e191b7220 */
/* 0x001fca0000400000 */
/*0ed0*/ STG.E [R8.64+0x10], R27 ; /* 0x0000101b08007986 */
/* 0x000fe8000c101904 */
/*0ee0*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000f68000c1e1900 */
/*0ef0*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140402167981 */
/* 0x000f68000c1e1900 */
/*0f00*/ LDG.E R25, [R6.64+0x10] ; /* 0x0000100406197981 */
/* 0x000ee2000c1e1900 */
/*0f10*/ FFMA R23, R12, R23, R26 ; /* 0x000000170c177223 */
/* 0x010fc8000000001a */
/*0f20*/ FFMA R21, R20, R21, R23 ; /* 0x0000001514157223 */
/* 0x000fe40000000017 */
/*0f30*/ FMUL R29, R13, R22 ; /* 0x000000160d1d7220 */
/* 0x020fca0000400000 */
/*0f40*/ STG.E [R8.64+0x14], R29 ; /* 0x0000141d08007986 */
/* 0x0001e8000c101904 */
/*0f50*/ LDG.E R13, [R6.64+0x14] ; /* 0x00001404060d7981 */
/* 0x000322000c1e1900 */
/*0f60*/ FFMA R19, R18, R19, R21 ; /* 0x0000001312137223 */
/* 0x000fc80000000015 */
/*0f70*/ FFMA R17, R16, R17, R19 ; /* 0x0000001110117223 */
/* 0x000fc80000000013 */
/*0f80*/ FFMA R17, R15, R24, R17 ; /* 0x000000180f117223 */
/* 0x004fe20000000011 */
/*0f90*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x000fe40007f3e0ff */
/*0fa0*/ IADD3 R12, P2, R8, 0x20, RZ ; /* 0x00000020080c7810 */
/* 0x000fe20007f5e0ff */
/*0fb0*/ FFMA R17, R14, R25, R17 ; /* 0x000000190e117223 */
/* 0x008fe20000000011 */
/*0fc0*/ IADD3 R6, P3, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x002fe40007f7e0ff */
/*0fd0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0fe0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe40000ffe4ff */
/*0ff0*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x001fc400017fe4ff */
/*1000*/ IADD3.X R7, RZ, R7, RZ, P3, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40001ffe4ff */
/*1010*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe40007ffe0ff */
/*1020*/ MOV R8, R12 ; /* 0x0000000c00087202 */
/* 0x000fe20000000f00 */
/*1030*/ FFMA R13, R22, R13, R17 ; /* 0x0000000d160d7223 */
/* 0x010fe40000000011 */
/*1040*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1050*/ ISETP.LT.OR P0, PT, R11, R10, P0 ; /* 0x0000000a0b00720c */
/* 0x000fda0000701670 */
/*1060*/ @!P0 BRA 0x11f0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*1070*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*1080*/ LDG.E R11, [R2.64+-0x8] ; /* 0xfffff804020b7981 */
/* 0x000ea4000c1e1900 */
/*1090*/ FMUL R15, R10, R11 ; /* 0x0000000b0a0f7220 */
/* 0x004fca0000400000 */
/*10a0*/ STG.E [R8.64+-0x8], R15 ; /* 0xfffff80f08007986 */
/* 0x0001e8000c101904 */
/*10b0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*10c0*/ LDG.E R17, [R2.64+-0x4] ; /* 0xfffffc0402117981 */
/* 0x000ea4000c1e1900 */
/*10d0*/ FMUL R19, R10, R17 ; /* 0x000000110a137220 */
/* 0x004fc40000400000 */
/*10e0*/ LDG.E R10, [R6.64+-0x8] ; /* 0xfffff804060a7981 */
/* 0x000ea8000c1e1900 */
/*10f0*/ STG.E [R8.64+-0x4], R19 ; /* 0xfffffc1308007986 */
/* 0x0003e8000c101904 */
/*1100*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ee8000c1e1900 */
/*1110*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */
/* 0x000ee4000c1e1900 */
/*1120*/ FMUL R23, R12, R21 ; /* 0x000000150c177220 */
/* 0x008fc40000400000 */
/*1130*/ LDG.E R12, [R6.64+-0x4] ; /* 0xfffffc04060c7981 */
/* 0x000ee8000c1e1900 */
/*1140*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0003e8000c101904 */
/*1150*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000f28000c1e1900 */
/*1160*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x001f22000c1e1900 */
/*1170*/ FFMA R10, R11, R10, R13 ; /* 0x0000000a0b0a7223 */
/* 0x004fc4000000000d */
/*1180*/ FMUL R25, R14, R15 ; /* 0x0000000f0e197220 */
/* 0x010fe40000400000 */
/*1190*/ LDG.E R14, [R6.64] ; /* 0x00000004060e7981 */
/* 0x000ea8000c1e1900 */
/*11a0*/ STG.E [R8.64+0x4], R25 ; /* 0x0000041908007986 */
/* 0x0003e8000c101904 */
/*11b0*/ LDG.E R16, [R6.64+0x4] ; /* 0x0000040406107981 */
/* 0x000f22000c1e1900 */
/*11c0*/ FFMA R10, R17, R12, R10 ; /* 0x0000000c110a7223 */
/* 0x008fc8000000000a */
/*11d0*/ FFMA R10, R21, R14, R10 ; /* 0x0000000e150a7223 */
/* 0x004fc8000000000a */
/*11e0*/ FFMA R13, R15, R16, R10 ; /* 0x000000100f0d7223 */
/* 0x010fe4000000000a */
/*11f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*1200*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*1210*/ IMAD.WIDE R2, R0, R5, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fcc00078e0205 */
/*1220*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*1230*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0205 */
/*1240*/ FMUL R13, R2, R13 ; /* 0x0000000d020d7220 */
/* 0x004fca0000400000 */
/*1250*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe2000c101904 */
/*1260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1270*/ BRA 0x1270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void LSTMDeltaKernel( float *cellStateErrors, float *outputGateDeltas, float *cellStates, float *outputGateActivations, float *outputGateActivationDerivatives, float *deltas, int cellCount, int cellsPerBlock )
{
int memoryBlockId = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (memoryBlockId < cellCount / cellsPerBlock)
{
float outputGateDeltaSum = 0.0;
for (int cellId = memoryBlockId * cellsPerBlock; cellId < (memoryBlockId + 1) * cellsPerBlock; cellId++)
{
float delta = deltas[cellId];
cellStateErrors[cellId] = outputGateActivations[memoryBlockId] * delta;
outputGateDeltaSum += cellStates[cellId] * delta;
}
outputGateDeltas[memoryBlockId] = outputGateActivationDerivatives[memoryBlockId] * outputGateDeltaSum;
}
} | .file "tmpxft_000aba2c_00000000-6_LSTMDeltaKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii
.type _Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii, @function
_Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15LSTMDeltaKernelPfS_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii, .-_Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii
.globl _Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.type _Z15LSTMDeltaKernelPfS_S_S_S_S_ii, @function
_Z15LSTMDeltaKernelPfS_S_S_S_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15LSTMDeltaKernelPfS_S_S_S_S_ii, .-_Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15LSTMDeltaKernelPfS_S_S_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15LSTMDeltaKernelPfS_S_S_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void LSTMDeltaKernel( float *cellStateErrors, float *outputGateDeltas, float *cellStates, float *outputGateActivations, float *outputGateActivationDerivatives, float *deltas, int cellCount, int cellsPerBlock )
{
int memoryBlockId = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (memoryBlockId < cellCount / cellsPerBlock)
{
float outputGateDeltaSum = 0.0;
for (int cellId = memoryBlockId * cellsPerBlock; cellId < (memoryBlockId + 1) * cellsPerBlock; cellId++)
{
float delta = deltas[cellId];
cellStateErrors[cellId] = outputGateActivations[memoryBlockId] * delta;
outputGateDeltaSum += cellStates[cellId] * delta;
}
outputGateDeltas[memoryBlockId] = outputGateActivationDerivatives[memoryBlockId] * outputGateDeltaSum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LSTMDeltaKernel( float *cellStateErrors, float *outputGateDeltas, float *cellStates, float *outputGateActivations, float *outputGateActivationDerivatives, float *deltas, int cellCount, int cellsPerBlock )
{
int memoryBlockId = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (memoryBlockId < cellCount / cellsPerBlock)
{
float outputGateDeltaSum = 0.0;
for (int cellId = memoryBlockId * cellsPerBlock; cellId < (memoryBlockId + 1) * cellsPerBlock; cellId++)
{
float delta = deltas[cellId];
cellStateErrors[cellId] = outputGateActivations[memoryBlockId] * delta;
outputGateDeltaSum += cellStates[cellId] * delta;
}
outputGateDeltas[memoryBlockId] = outputGateActivationDerivatives[memoryBlockId] * outputGateDeltaSum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LSTMDeltaKernel( float *cellStateErrors, float *outputGateDeltas, float *cellStates, float *outputGateActivations, float *outputGateActivationDerivatives, float *deltas, int cellCount, int cellsPerBlock )
{
int memoryBlockId = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (memoryBlockId < cellCount / cellsPerBlock)
{
float outputGateDeltaSum = 0.0;
for (int cellId = memoryBlockId * cellsPerBlock; cellId < (memoryBlockId + 1) * cellsPerBlock; cellId++)
{
float delta = deltas[cellId];
cellStateErrors[cellId] = outputGateActivations[memoryBlockId] * delta;
outputGateDeltaSum += cellStates[cellId] * delta;
}
outputGateDeltas[memoryBlockId] = outputGateActivationDerivatives[memoryBlockId] * outputGateDeltaSum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.globl _Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.p2align 8
.type _Z15LSTMDeltaKernelPfS_S_S_S_S_ii,@function
_Z15LSTMDeltaKernelPfS_S_S_S_S_ii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x30
s_load_b32 s4, s[0:1], 0x38
s_load_b32 s5, s[0:1], 0x44
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s3, 31
s_ashr_i32 s10, s2, 31
s_add_i32 s7, s3, s6
s_add_i32 s2, s2, s10
s_xor_b32 s7, s7, s6
s_xor_b32 s2, s2, s10
v_cvt_f32_u32_e32 v1, s7
s_sub_i32 s9, 0, s7
s_mul_i32 s4, s4, s15
s_and_b32 s5, s5, 0xffff
s_add_i32 s4, s4, s14
v_rcp_iflag_f32_e32 v1, v1
s_xor_b32 s6, s10, s6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s8, v1
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s9, s8
s_mul_hi_u32 s9, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, s9
s_mul_hi_u32 s8, s2, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s8, s7
s_sub_i32 s2, s2, s9
s_add_i32 s9, s8, 1
s_sub_i32 s10, s2, s7
s_cmp_ge_u32 s2, s7
s_cselect_b32 s4, s9, s8
s_cselect_b32 s2, s10, s2
s_add_i32 s5, s4, 1
s_cmp_ge_u32 s2, s7
s_cselect_b32 s2, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s6
s_sub_i32 s2, s2, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_5
v_mul_lo_u32 v3, v1, s3
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s3, v3
v_cmp_lt_i32_e32 vcc_lo, v3, v2
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x28
s_load_b64 s[10:11], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s8, v9
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v10, vcc_lo
v_add_co_u32 v7, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
.p2align 6
.LBB0_3:
global_load_b32 v11, v[5:6], off
global_load_b32 v12, v[3:4], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
v_mul_f32_e32 v12, v11, v12
global_store_b32 v[7:8], v12, off
global_load_b32 v12, v[9:10], off
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v11, v12
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[2:3], s[0:1], 0x20
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v0, v3
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15LSTMDeltaKernelPfS_S_S_S_S_ii, .Lfunc_end0-_Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15LSTMDeltaKernelPfS_S_S_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LSTMDeltaKernel( float *cellStateErrors, float *outputGateDeltas, float *cellStates, float *outputGateActivations, float *outputGateActivationDerivatives, float *deltas, int cellCount, int cellsPerBlock )
{
int memoryBlockId = blockDim.x * blockIdx.y * gridDim.x //rows preceeding current row in grid
+ blockDim.x * blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (memoryBlockId < cellCount / cellsPerBlock)
{
float outputGateDeltaSum = 0.0;
for (int cellId = memoryBlockId * cellsPerBlock; cellId < (memoryBlockId + 1) * cellsPerBlock; cellId++)
{
float delta = deltas[cellId];
cellStateErrors[cellId] = outputGateActivations[memoryBlockId] * delta;
outputGateDeltaSum += cellStates[cellId] * delta;
}
outputGateDeltas[memoryBlockId] = outputGateActivationDerivatives[memoryBlockId] * outputGateDeltaSum;
}
} | .text
.file "LSTMDeltaKernel.hip"
.globl _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii # -- Begin function _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii,@function
_Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii: # @_Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15LSTMDeltaKernelPfS_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii, .Lfunc_end0-_Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15LSTMDeltaKernelPfS_S_S_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15LSTMDeltaKernelPfS_S_S_S_S_ii,@object # @_Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.section .rodata,"a",@progbits
.globl _Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.p2align 3, 0x0
_Z15LSTMDeltaKernelPfS_S_S_S_S_ii:
.quad _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii
.size _Z15LSTMDeltaKernelPfS_S_S_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15LSTMDeltaKernelPfS_S_S_S_S_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aba2c_00000000-6_LSTMDeltaKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii
.type _Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii, @function
_Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15LSTMDeltaKernelPfS_S_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii, .-_Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii
.globl _Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.type _Z15LSTMDeltaKernelPfS_S_S_S_S_ii, @function
_Z15LSTMDeltaKernelPfS_S_S_S_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z15LSTMDeltaKernelPfS_S_S_S_S_iiPfS_S_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15LSTMDeltaKernelPfS_S_S_S_S_ii, .-_Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15LSTMDeltaKernelPfS_S_S_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15LSTMDeltaKernelPfS_S_S_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "LSTMDeltaKernel.hip"
.globl _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii # -- Begin function _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii,@function
_Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii: # @_Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15LSTMDeltaKernelPfS_S_S_S_S_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii, .Lfunc_end0-_Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15LSTMDeltaKernelPfS_S_S_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15LSTMDeltaKernelPfS_S_S_S_S_ii,@object # @_Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.section .rodata,"a",@progbits
.globl _Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.p2align 3, 0x0
_Z15LSTMDeltaKernelPfS_S_S_S_S_ii:
.quad _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii
.size _Z15LSTMDeltaKernelPfS_S_S_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15LSTMDeltaKernelPfS_S_S_S_S_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__LSTMDeltaKernelPfS_S_S_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15LSTMDeltaKernelPfS_S_S_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // **********************************************************************************************************
// PURPOSE : Index calculation for array to access data from kernel. *
// LANGUAGE : CUDA C / CUDA C++ *
// ASSUMPTIONS : This code is part of CUDA fundamentals section. *
// DATE : 24 March 2020 *
// AUTHOR : Vaibhav BENDRE (vaibhav.bendre7520@gmail.com) *
// *
// **********************************************************************************************************
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
#include<stdlib.h>
#include<iostream>
__global__ void uniqueIdxCalcUsingThreadIdx(int* arr) {
unsigned int tidx{ threadIdx.x };
printf("threadIdx : %d, value : %d \n", tidx, arr[tidx]);
}
int main() {
int arrSize{ 16 };
int arrByteSize{ static_cast<int>(sizeof(int))* arrSize };
int arrData[]{ 23,9,4,53,65,12,1,33,87,45,23,12,342,56,44,99 };
for ( int iCounter{ 0 }; iCounter < arrSize; ++iCounter) {
std::cout << arrData[iCounter] << " ";
}
std::cout << "\n\n\n";
int* data;
cudaMalloc((void**)&data, arrByteSize);
cudaMemcpy(data, arrData, arrByteSize, cudaMemcpyHostToDevice);
dim3 block{ 16 };
dim3 grid{ 1 };
uniqueIdxCalcUsingThreadIdx <<< grid, block >>> (data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z27uniqueIdxCalcUsingThreadIdxPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe40007ffe0ff */
/*0050*/ IMAD.WIDE.U32 R2, R10, R3, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x001fca00078e0003 */
/*0060*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000660000000a00 */
/*00c0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00d0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*00e0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fc60000000000 */
/*00f0*/ MOV R11, 0x160 ; /* 0x00000160000b7802 */
/* 0x001fe40000000f00 */
/*0100*/ MOV R20, 0xe0 ; /* 0x000000e000147802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0130*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0140*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0150*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // **********************************************************************************************************
// PURPOSE : Index calculation for array to access data from kernel. *
// LANGUAGE : CUDA C / CUDA C++ *
// ASSUMPTIONS : This code is part of CUDA fundamentals section. *
// DATE : 24 March 2020 *
// AUTHOR : Vaibhav BENDRE (vaibhav.bendre7520@gmail.com) *
// *
// **********************************************************************************************************
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
#include<stdlib.h>
#include<iostream>
__global__ void uniqueIdxCalcUsingThreadIdx(int* arr) {
unsigned int tidx{ threadIdx.x };
printf("threadIdx : %d, value : %d \n", tidx, arr[tidx]);
}
int main() {
int arrSize{ 16 };
int arrByteSize{ static_cast<int>(sizeof(int))* arrSize };
int arrData[]{ 23,9,4,53,65,12,1,33,87,45,23,12,342,56,44,99 };
for ( int iCounter{ 0 }; iCounter < arrSize; ++iCounter) {
std::cout << arrData[iCounter] << " ";
}
std::cout << "\n\n\n";
int* data;
cudaMalloc((void**)&data, arrByteSize);
cudaMemcpy(data, arrData, arrByteSize, cudaMemcpyHostToDevice);
dim3 block{ 16 };
dim3 grid{ 1 };
uniqueIdxCalcUsingThreadIdx <<< grid, block >>> (data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | .file "tmpxft_0002a281_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi
.type _Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi, @function
_Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z27uniqueIdxCalcUsingThreadIdxPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi, .-_Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi
.globl _Z27uniqueIdxCalcUsingThreadIdxPi
.type _Z27uniqueIdxCalcUsingThreadIdxPi, @function
_Z27uniqueIdxCalcUsingThreadIdxPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z27uniqueIdxCalcUsingThreadIdxPi, .-_Z27uniqueIdxCalcUsingThreadIdxPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.LC1:
.string "\n\n\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $120, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $23, 32(%rsp)
movl $9, 36(%rsp)
movl $4, 40(%rsp)
movl $53, 44(%rsp)
movl $65, 48(%rsp)
movl $12, 52(%rsp)
movl $1, 56(%rsp)
movl $33, 60(%rsp)
movl $87, 64(%rsp)
movl $45, 68(%rsp)
movl $23, 72(%rsp)
movl $12, 76(%rsp)
movl $342, 80(%rsp)
movl $56, 84(%rsp)
movl $44, 88(%rsp)
movl $99, 92(%rsp)
leaq 32(%rsp), %rbx
leaq 96(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %rbp
.L12:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $3, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L12
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq (%rsp), %rdi
call _Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z27uniqueIdxCalcUsingThreadIdxPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z27uniqueIdxCalcUsingThreadIdxPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // **********************************************************************************************************
// PURPOSE : Index calculation for array to access data from kernel. *
// LANGUAGE : CUDA C / CUDA C++ *
// ASSUMPTIONS : This code is part of CUDA fundamentals section. *
// DATE : 24 March 2020 *
// AUTHOR : Vaibhav BENDRE (vaibhav.bendre7520@gmail.com) *
// *
// **********************************************************************************************************
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<stdio.h>
#include<stdlib.h>
#include<iostream>
__global__ void uniqueIdxCalcUsingThreadIdx(int* arr) {
unsigned int tidx{ threadIdx.x };
printf("threadIdx : %d, value : %d \n", tidx, arr[tidx]);
}
int main() {
int arrSize{ 16 };
int arrByteSize{ static_cast<int>(sizeof(int))* arrSize };
int arrData[]{ 23,9,4,53,65,12,1,33,87,45,23,12,342,56,44,99 };
for ( int iCounter{ 0 }; iCounter < arrSize; ++iCounter) {
std::cout << arrData[iCounter] << " ";
}
std::cout << "\n\n\n";
int* data;
cudaMalloc((void**)&data, arrByteSize);
cudaMemcpy(data, arrData, arrByteSize, cudaMemcpyHostToDevice);
dim3 block{ 16 };
dim3 grid{ 1 };
uniqueIdxCalcUsingThreadIdx <<< grid, block >>> (data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | // **********************************************************************************************************
// PURPOSE : Index calculation for array to access data from kernel. *
// LANGUAGE : CUDA C / CUDA C++ *
// ASSUMPTIONS : This code is part of CUDA fundamentals section. *
// DATE : 24 March 2020 *
// AUTHOR : Vaibhav BENDRE (vaibhav.bendre7520@gmail.com) *
// *
// **********************************************************************************************************
#include "hip/hip_runtime.h"
#include<stdio.h>
#include<stdlib.h>
#include<iostream>
__global__ void uniqueIdxCalcUsingThreadIdx(int* arr) {
unsigned int tidx{ threadIdx.x };
printf("threadIdx : %d, value : %d \n", tidx, arr[tidx]);
}
int main() {
int arrSize{ 16 };
int arrByteSize{ static_cast<int>(sizeof(int))* arrSize };
int arrData[]{ 23,9,4,53,65,12,1,33,87,45,23,12,342,56,44,99 };
for ( int iCounter{ 0 }; iCounter < arrSize; ++iCounter) {
std::cout << arrData[iCounter] << " ";
}
std::cout << "\n\n\n";
int* data;
hipMalloc((void**)&data, arrByteSize);
hipMemcpy(data, arrData, arrByteSize, hipMemcpyHostToDevice);
dim3 block{ 16 };
dim3 grid{ 1 };
uniqueIdxCalcUsingThreadIdx <<< grid, block >>> (data);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // **********************************************************************************************************
// PURPOSE : Index calculation for array to access data from kernel. *
// LANGUAGE : CUDA C / CUDA C++ *
// ASSUMPTIONS : This code is part of CUDA fundamentals section. *
// DATE : 24 March 2020 *
// AUTHOR : Vaibhav BENDRE (vaibhav.bendre7520@gmail.com) *
// *
// **********************************************************************************************************
#include "hip/hip_runtime.h"
#include<stdio.h>
#include<stdlib.h>
#include<iostream>
__global__ void uniqueIdxCalcUsingThreadIdx(int* arr) {
unsigned int tidx{ threadIdx.x };
printf("threadIdx : %d, value : %d \n", tidx, arr[tidx]);
}
int main() {
int arrSize{ 16 };
int arrByteSize{ static_cast<int>(sizeof(int))* arrSize };
int arrData[]{ 23,9,4,53,65,12,1,33,87,45,23,12,342,56,44,99 };
for ( int iCounter{ 0 }; iCounter < arrSize; ++iCounter) {
std::cout << arrData[iCounter] << " ";
}
std::cout << "\n\n\n";
int* data;
hipMalloc((void**)&data, arrByteSize);
hipMemcpy(data, arrData, arrByteSize, hipMemcpyHostToDevice);
dim3 block{ 16 };
dim3 grid{ 1 };
uniqueIdxCalcUsingThreadIdx <<< grid, block >>> (data);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi # -- Begin function _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi
.p2align 4, 0x90
.type _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi,@function
_Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi: # @_Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z27uniqueIdxCalcUsingThreadIdxPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi, .Lfunc_end0-_Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 23 # 0x17
.long 9 # 0x9
.long 4 # 0x4
.long 53 # 0x35
.LCPI1_1:
.long 65 # 0x41
.long 12 # 0xc
.long 1 # 0x1
.long 33 # 0x21
.LCPI1_2:
.long 87 # 0x57
.long 45 # 0x2d
.long 23 # 0x17
.long 12 # 0xc
.LCPI1_3:
.long 342 # 0x156
.long 56 # 0x38
.long 44 # 0x2c
.long 99 # 0x63
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [23,9,4,53]
movaps %xmm0, 80(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [65,12,1,33]
movaps %xmm0, 96(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [87,45,23,12]
movaps %xmm0, 112(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [342,56,44,99]
movaps %xmm0, 128(%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $16, %rbx
jne .LBB1_1
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z27uniqueIdxCalcUsingThreadIdxPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27uniqueIdxCalcUsingThreadIdxPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27uniqueIdxCalcUsingThreadIdxPi,@object # @_Z27uniqueIdxCalcUsingThreadIdxPi
.section .rodata,"a",@progbits
.globl _Z27uniqueIdxCalcUsingThreadIdxPi
.p2align 3, 0x0
_Z27uniqueIdxCalcUsingThreadIdxPi:
.quad _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi
.size _Z27uniqueIdxCalcUsingThreadIdxPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\n\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27uniqueIdxCalcUsingThreadIdxPi"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27uniqueIdxCalcUsingThreadIdxPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002a281_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi
.type _Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi, @function
_Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z27uniqueIdxCalcUsingThreadIdxPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi, .-_Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi
.globl _Z27uniqueIdxCalcUsingThreadIdxPi
.type _Z27uniqueIdxCalcUsingThreadIdxPi, @function
_Z27uniqueIdxCalcUsingThreadIdxPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z27uniqueIdxCalcUsingThreadIdxPi, .-_Z27uniqueIdxCalcUsingThreadIdxPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.LC1:
.string "\n\n\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $120, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $23, 32(%rsp)
movl $9, 36(%rsp)
movl $4, 40(%rsp)
movl $53, 44(%rsp)
movl $65, 48(%rsp)
movl $12, 52(%rsp)
movl $1, 56(%rsp)
movl $33, 60(%rsp)
movl $87, 64(%rsp)
movl $45, 68(%rsp)
movl $23, 72(%rsp)
movl $12, 76(%rsp)
movl $342, 80(%rsp)
movl $56, 84(%rsp)
movl $44, 88(%rsp)
movl $99, 92(%rsp)
leaq 32(%rsp), %rbx
leaq 96(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC0(%rip), %rbp
.L12:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $3, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L12
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq (%rsp), %rdi
call _Z47__device_stub__Z27uniqueIdxCalcUsingThreadIdxPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z27uniqueIdxCalcUsingThreadIdxPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z27uniqueIdxCalcUsingThreadIdxPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi # -- Begin function _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi
.p2align 4, 0x90
.type _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi,@function
_Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi: # @_Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z27uniqueIdxCalcUsingThreadIdxPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi, .Lfunc_end0-_Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 23 # 0x17
.long 9 # 0x9
.long 4 # 0x4
.long 53 # 0x35
.LCPI1_1:
.long 65 # 0x41
.long 12 # 0xc
.long 1 # 0x1
.long 33 # 0x21
.LCPI1_2:
.long 87 # 0x57
.long 45 # 0x2d
.long 23 # 0x17
.long 12 # 0xc
.LCPI1_3:
.long 342 # 0x156
.long 56 # 0x38
.long 44 # 0x2c
.long 99 # 0x63
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [23,9,4,53]
movaps %xmm0, 80(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [65,12,1,33]
movaps %xmm0, 96(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [87,45,23,12]
movaps %xmm0, 112(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [342,56,44,99]
movaps %xmm0, 128(%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $16, %rbx
jne .LBB1_1
# %bb.2:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z27uniqueIdxCalcUsingThreadIdxPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27uniqueIdxCalcUsingThreadIdxPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27uniqueIdxCalcUsingThreadIdxPi,@object # @_Z27uniqueIdxCalcUsingThreadIdxPi
.section .rodata,"a",@progbits
.globl _Z27uniqueIdxCalcUsingThreadIdxPi
.p2align 3, 0x0
_Z27uniqueIdxCalcUsingThreadIdxPi:
.quad _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi
.size _Z27uniqueIdxCalcUsingThreadIdxPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\n\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27uniqueIdxCalcUsingThreadIdxPi"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__uniqueIdxCalcUsingThreadIdxPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27uniqueIdxCalcUsingThreadIdxPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
int main(int argc, char *argv[])
{
if (argc > 1)
{
std::cout << argv[1] << " " << argv[2];
}
else
{
std::cout << "Nothing entered.";
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
int main(int argc, char *argv[])
{
if (argc > 1)
{
std::cout << argv[1] << " " << argv[2];
}
else
{
std::cout << "Nothing entered.";
}
return 0;
} | .file "tmpxft_0012db84_00000000-6_Calculation.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.LC1:
.string "Nothing entered."
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
cmpl $1, %edi
jle .L4
movq %rsi, %rbx
movq 8(%rsi), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 16(%rbx), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L5:
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L5
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
int main(int argc, char *argv[])
{
if (argc > 1)
{
std::cout << argv[1] << " " << argv[2];
}
else
{
std::cout << "Nothing entered.";
}
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
int main(int argc, char *argv[])
{
if (argc > 1)
{
std::cout << argv[1] << " " << argv[2];
}
else
{
std::cout << "Nothing entered.";
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
int main(int argc, char *argv[])
{
if (argc > 1)
{
std::cout << argv[1] << " " << argv[2];
}
else
{
std::cout << "Nothing entered.";
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
int main(int argc, char *argv[])
{
if (argc > 1)
{
std::cout << argv[1] << " " << argv[2];
}
else
{
std::cout << "Nothing entered.";
}
return 0;
} | .text
.file "Calculation.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
cmpl $2, %edi
jl .LBB0_7
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %r14
testq %r14, %r14
je .LBB0_2
# %bb.3:
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_4
.LBB0_7:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $16, %edx
jmp .LBB0_8
.LBB0_2:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rbx), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.6:
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
.LBB0_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit3
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit3
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 32
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
jmp .LBB0_9
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Nothing entered."
.size .L.str.1, 17
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012db84_00000000-6_Calculation.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.LC1:
.string "Nothing entered."
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
cmpl $1, %edi
jle .L4
movq %rsi, %rbx
movq 8(%rsi), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 16(%rbx), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L5:
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L5
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Calculation.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
cmpl $2, %edi
jl .LBB0_7
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %r14
testq %r14, %r14
je .LBB0_2
# %bb.3:
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_4
.LBB0_7:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $16, %edx
jmp .LBB0_8
.LBB0_2:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB0_4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rbx), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.6:
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
.LBB0_8: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit3
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit3
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 32
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
jmp .LBB0_9
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Nothing entered."
.size .L.str.1, 17
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Below code is based on
https://github.com/NVIDIA-developer-blog/code-samples/tree/master/series/cuda-cpp/transpose.
nvcc transpose_rectangle.cu -o transpose_rectangle
*/
#include <assert.h>
#include <stdio.h>
#define DEBUG
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline cudaError_t checkCuda(cudaError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
const int nx = 1024;
const int ny = 1024;
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float* ref, const float* res, int n, float ms) {
bool passed = true;
for (int i = 0; i < 256; i++) {
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, ref[i], res[i]);
// printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms);
}
// Original coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalescedRectangle_Orig(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
tile[threadIdx.y][threadIdx.x] = idata[y * width + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
if ((x < ny) && (y < nx)) {
odata[y * height + x] = tile[threadIdx.x][threadIdx.y];
}
}
// Naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaiveRectangle(float* odata, const float* idata) {
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
odata[(x)*height + y] = idata[width * y + (x)];
}
}
// Shared
__global__ void transposeCoalescedRectangle(float* odata, const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
__global__ void transposeNoBankConflictsRectangle(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
int main(int argc, char** argv) {
const int mem_size = nx * ny * sizeof(float);
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
int devId = 0;
if (argc > 1)
devId = atoi(argv[1]);
cudaDeviceProp prop;
checkCuda(cudaGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("%d.%d\n", prop.major, prop.minor);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n", nx, ny,
TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n", dimGrid.x, dimGrid.y,
dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda(cudaSetDevice(devId));
float* h_idata = (float*)malloc(mem_size);
float* h_cdata = (float*)malloc(mem_size);
float* h_tdata = (float*)malloc(mem_size);
float* gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda(cudaMalloc(&d_idata, mem_size));
checkCuda(cudaMalloc(&d_cdata, mem_size));
checkCuda(cudaMalloc(&d_tdata, mem_size));
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
h_idata[j * nx + i] = j * nx + i;
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < ny; i++) {
printf("\n");
for (int j = 0; j < nx; j++) {
printf("%d,",(int)h_idata[i*nx+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < nx; j++) {
printf("%d ",(int)h_idata[j]);
}
*/
// correct result for error checking
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
gold[i * ny + j] = h_idata[j * nx + i];
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < nx; i++) {
printf("\n");
for (int j = 0; j < ny; j++) {
printf("%d,",(int)gold[i*ny+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < ny; j++) {
printf("%d ",(int)gold[j]);
}
*/
printf("\nmem_size=%d\n\n", mem_size);
// device
checkCuda(cudaMemcpy(d_idata, h_idata, mem_size, cudaMemcpyHostToDevice));
// events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda(cudaEventCreate(&startEvent));
checkCuda(cudaEventCreate(&stopEvent));
float ms;
// ------------
// time kernels
// ------------
printf("%35s%20s\n", "Routine", "Bandwidth (GB/s)");
{
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, TILE_DIM, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// --------------
// transposeNaiveRectangle
// --------------
printf("%35s", "transposeNaiveRectangle");
checkCuda(cudaMemset(d_tdata, 0, mem_size));
// warmup
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeCoalescedRectangle
// ------------------
printf("%35s", "transposeCoalescedRectangle");
checkCuda(cudaMemset(d_tdata, 0, mem_size));
// warmup
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeNoBankConflictsRectangle
// ------------------
printf("%35s", "transposeNobankConflictsRectangle");
checkCuda(cudaMemset(d_tdata, 0, mem_size));
// warmup
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata,
d_idata);
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
error_exit:
// cleanup
checkCuda(cudaEventDestroy(startEvent));
checkCuda(cudaEventDestroy(stopEvent));
checkCuda(cudaFree(d_tdata));
checkCuda(cudaFree(d_cdata));
checkCuda(cudaFree(d_idata));
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} | code for sm_80
Function : _Z33transposeNoBankConflictsRectanglePfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.L.U32 UR4, UR4, 0x5, URZ ; /* 0x0000000504047899 */
/* 0x000fe2000800063f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0060*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*0070*/ S2R R14, SR_CTAID.Y ; /* 0x00000000000e7919 */
/* 0x000e620000002600 */
/*0080*/ LEA R6, R2, R3, 0x5 ; /* 0x0000000302067211 */
/* 0x001fc800078e28ff */
/*0090*/ ISETP.GT.AND P0, PT, R6, 0x3ff, PT ; /* 0x000003ff0600780c */
/* 0x000fe20003f04270 */
/*00a0*/ IMAD R7, R14, 0x20, R0 ; /* 0x000000200e077824 */
/* 0x002fca00078e0200 */
/*00b0*/ ISETP.GT.OR P2, PT, R7.reuse, 0x3f7, P0 ; /* 0x000003f70700780c */
/* 0x040fe40000744670 */
/*00c0*/ ISETP.GT.OR P4, PT, R7.reuse, 0x3ff, P0 ; /* 0x000003ff0700780c */
/* 0x040fe40000784670 */
/*00d0*/ ISETP.GT.OR P3, PT, R7.reuse, 0x3ef, P0 ; /* 0x000003ef0700780c */
/* 0x040fe40000764670 */
/*00e0*/ ISETP.GT.OR P0, PT, R7, 0x3e7, P0 ; /* 0x000003e70700780c */
/* 0x000fce0000704670 */
/*00f0*/ @!P2 IADD3 R9, R7.reuse, 0x8, RZ ; /* 0x000000080709a810 */
/* 0x040fe20007ffe0ff */
/*0100*/ @!P2 IMAD.MOV.U32 R16, RZ, RZ, 0x4 ; /* 0x00000004ff10a424 */
/* 0x000fe200078e00ff */
/*0110*/ @!P4 MOV R5, 0x4 ; /* 0x000000040005c802 */
/* 0x000fe20000000f00 */
/*0120*/ @!P4 IMAD R4, R7.reuse, UR4, R6.reuse ; /* 0x000000040704cc24 */
/* 0x140fe2000f8e0206 */
/*0130*/ @!P3 IADD3 R11, R7.reuse, 0x10, RZ ; /* 0x00000010070bb810 */
/* 0x040fe40007ffe0ff */
/*0140*/ @!P0 IADD3 R13, R7, 0x18, RZ ; /* 0x00000018070d8810 */
/* 0x000fe20007ffe0ff */
/*0150*/ @!P2 IMAD R7, R9, UR4, R6.reuse ; /* 0x000000040907ac24 */
/* 0x100fe2000f8e0206 */
/*0160*/ @!P3 MOV R15, 0x4 ; /* 0x00000004000fb802 */
/* 0x000fe20000000f00 */
/*0170*/ @!P3 IMAD R8, R11, UR4, R6.reuse ; /* 0x000000040b08bc24 */
/* 0x100fe2000f8e0206 */
/*0180*/ @!P0 MOV R17, 0x4 ; /* 0x0000000400118802 */
/* 0x000fe20000000f00 */
/*0190*/ @!P0 IMAD R10, R13, UR4, R6 ; /* 0x000000040d0a8c24 */
/* 0x000fc4000f8e0206 */
/*01a0*/ @!P4 IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a000404c625 */
/* 0x000fc800078e0205 */
/*01b0*/ @!P2 IMAD.WIDE R6, R7, R16, c[0x0][0x168] ; /* 0x00005a000706a625 */
/* 0x000fe200078e0210 */
/*01c0*/ @!P4 LDG.E R12, [R4.64] ; /* 0x00000006040cc981 */
/* 0x0000a6000c1e1900 */
/*01d0*/ @!P3 IMAD.WIDE R8, R8, R15, c[0x0][0x168] ; /* 0x00005a000808b625 */
/* 0x000fe400078e020f */
/*01e0*/ @!P2 LDG.E R6, [R6.64] ; /* 0x000000060606a981 */
/* 0x0002e4000c1e1900 */
/*01f0*/ @!P0 IMAD.WIDE R10, R10, R17, c[0x0][0x168] ; /* 0x00005a000a0a8625 */
/* 0x000fe400078e0211 */
/*0200*/ @!P3 LDG.E R8, [R8.64] ; /* 0x000000060808b981 */
/* 0x000968000c1e1900 */
/*0210*/ @!P0 LDG.E R10, [R10.64] ; /* 0x000000060a0a8981 */
/* 0x000f62000c1e1900 */
/*0220*/ @!P4 IMAD R13, R0, 0x21, R3 ; /* 0x00000021000dc824 */
/* 0x000fc400078e0203 */
/*0230*/ @!P2 IMAD R7, R0.reuse, 0x21, R3.reuse ; /* 0x000000210007a824 */
/* 0x142fe400078e0203 */
/*0240*/ @!P0 IMAD R17, R0.reuse, 0x21, R3.reuse ; /* 0x0000002100118824 */
/* 0x140fe400078e0203 */
/*0250*/ @!P3 IMAD R9, R0, 0x21, R3.reuse ; /* 0x000000210009b824 */
/* 0x110fe400078e0203 */
/*0260*/ IMAD R4, R14, 0x20, R3 ; /* 0x000000200e047824 */
/* 0x001fe200078e0203 */
/*0270*/ LEA R5, R2, R0, 0x5 ; /* 0x0000000002057211 */
/* 0x000fc800078e28ff */
/*0280*/ ISETP.GT.AND P1, PT, R4, 0x3ff, PT ; /* 0x000003ff0400780c */
/* 0x000fc80003f24270 */
/*0290*/ ISETP.GT.OR P6, PT, R5.reuse, 0x3ff, P1 ; /* 0x000003ff0500780c */
/* 0x040fe40000fc4670 */
/*02a0*/ ISETP.GT.OR P5, PT, R5, 0x3f7, P1 ; /* 0x000003f70500780c */
/* 0x000fe20000fa4670 */
/*02b0*/ IMAD R0, R3, 0x21, R0 ; /* 0x0000002103007824 */
/* 0x000fe200078e0200 */
/*02c0*/ ULDC UR4, c[0x0][0x10] ; /* 0x0000040000047ab9 */
/* 0x000fe40000000800 */
/*02d0*/ USHF.L.U32 UR4, UR4, 0x5, URZ ; /* 0x0000000504047899 */
/* 0x000fd2000800063f */
/*02e0*/ @!P5 IADD3 R3, R5.reuse, 0x8, RZ ; /* 0x000000080503d810 */
/* 0x040fe20007ffe0ff */
/*02f0*/ @!P6 IMAD R2, R5.reuse, UR4, R4 ; /* 0x000000040502ec24 */
/* 0x040fe2000f8e0204 */
/*0300*/ @!P4 STS [R13.X4], R12 ; /* 0x0000000c0d00c388 */
/* 0x004fe80000004800 */
/*0310*/ @!P2 STS [R7.X4+0x420], R6 ; /* 0x000420060700a388 */
/* 0x0081e80000004800 */
/*0320*/ @!P3 STS [R9.X4+0x840], R8 ; /* 0x000840080900b388 */
/* 0x0203e80000004800 */
/*0330*/ @!P0 STS [R17.X4+0xc60], R10 ; /* 0x000c600a11008388 */
/* 0x0005e80000004800 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0350*/ ISETP.GT.OR P4, PT, R5, 0x3ef, P1 ; /* 0x000003ef0500780c */
/* 0x000fca0000f84670 */
/*0360*/ @!P6 LDS R11, [R0.X4] ; /* 0x00000000000be984 */
/* 0x000ee80000004800 */
/*0370*/ @!P5 LDS R13, [R0.X4+0x20] ; /* 0x00002000000dd984 */
/* 0x000f280000004800 */
/*0380*/ @!P4 LDS R15, [R0.X4+0x40] ; /* 0x00004000000fc984 */
/* 0x000f620000004800 */
/*0390*/ @!P4 IADD3 R7, R5, 0x10, RZ ; /* 0x000000100507c810 */
/* 0x001fe40007ffe0ff */
/*03a0*/ @!P6 MOV R9, 0x4 ; /* 0x000000040009e802 */
/* 0x002fc40000000f00 */
/*03b0*/ ISETP.GT.OR P1, PT, R5, 0x3e7, P1 ; /* 0x000003e70500780c */
/* 0x000fe20000f24670 */
/*03c0*/ @!P5 IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff11d424 */
/* 0x004fe200078e00ff */
/*03d0*/ @!P4 MOV R19, 0x4 ; /* 0x000000040013c802 */
/* 0x000fe20000000f00 */
/*03e0*/ @!P5 IMAD R6, R3, UR4, R4.reuse ; /* 0x000000040306dc24 */
/* 0x100fe4000f8e0204 */
/*03f0*/ @!P4 IMAD R8, R7, UR4, R4 ; /* 0x000000040708cc24 */
/* 0x000fe4000f8e0204 */
/*0400*/ @!P6 IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x000058000202e625 */
/* 0x000fc800078e0209 */
/*0410*/ @!P5 IMAD.WIDE R6, R6, R17, c[0x0][0x160] ; /* 0x000058000606d625 */
/* 0x000fc800078e0211 */
/*0420*/ @!P4 IMAD.WIDE R8, R8, R19, c[0x0][0x160] ; /* 0x000058000808c625 */
/* 0x000fe200078e0213 */
/*0430*/ @!P6 STG.E [R2.64], R11 ; /* 0x0000000b0200e986 */
/* 0x0081e8000c101906 */
/*0440*/ @!P5 STG.E [R6.64], R13 ; /* 0x0000000d0600d986 */
/* 0x0101e8000c101906 */
/*0450*/ @!P4 STG.E [R8.64], R15 ; /* 0x0000000f0800c986 */
/* 0x0201e2000c101906 */
/*0460*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0470*/ LDS R7, [R0.X4+0x60] ; /* 0x0000600000077984 */
/* 0x001e220000004800 */
/*0480*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0490*/ IADD3 R5, R5, 0x18, RZ ; /* 0x0000001805057810 */
/* 0x000fca0007ffe0ff */
/*04a0*/ IMAD R2, R5, UR4, R4 ; /* 0x0000000405027c24 */
/* 0x000fc8000f8e0204 */
/*04b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*04c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101906 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z27transposeCoalescedRectanglePfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.L.U32 UR4, UR4, 0x5, URZ ; /* 0x0000000504047899 */
/* 0x000fe2000800063f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0060*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*0070*/ S2R R14, SR_CTAID.Y ; /* 0x00000000000e7919 */
/* 0x000e620000002600 */
/*0080*/ IMAD R6, R2, 0x20, R3 ; /* 0x0000002002067824 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GT.AND P0, PT, R6, 0x3ff, PT ; /* 0x000003ff0600780c */
/* 0x000fe40003f04270 */
/*00a0*/ LEA R7, R14, R0, 0x5 ; /* 0x000000000e077211 */
/* 0x002fc800078e28ff */
/*00b0*/ ISETP.GT.OR P2, PT, R7.reuse, 0x3f7, P0 ; /* 0x000003f70700780c */
/* 0x040fe40000744670 */
/*00c0*/ ISETP.GT.OR P4, PT, R7.reuse, 0x3ff, P0 ; /* 0x000003ff0700780c */
/* 0x040fe40000784670 */
/*00d0*/ ISETP.GT.OR P3, PT, R7.reuse, 0x3ef, P0 ; /* 0x000003ef0700780c */
/* 0x040fe40000764670 */
/*00e0*/ ISETP.GT.OR P0, PT, R7, 0x3e7, P0 ; /* 0x000003e70700780c */
/* 0x000fce0000704670 */
/*00f0*/ @!P2 IADD3 R9, R7.reuse, 0x8, RZ ; /* 0x000000080709a810 */
/* 0x040fe40007ffe0ff */
/*0100*/ @!P4 IMAD R4, R7.reuse, UR4, R6.reuse ; /* 0x000000040704cc24 */
/* 0x140fe4000f8e0206 */
/*0110*/ @!P3 IADD3 R11, R7.reuse, 0x10, RZ ; /* 0x00000010070bb810 */
/* 0x040fe20007ffe0ff */
/*0120*/ @!P4 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff05c424 */
/* 0x000fe200078e00ff */
/*0130*/ @!P0 IADD3 R13, R7, 0x18, RZ ; /* 0x00000018070d8810 */
/* 0x000fe20007ffe0ff */
/*0140*/ @!P2 IMAD R7, R9, UR4, R6.reuse ; /* 0x000000040907ac24 */
/* 0x100fe2000f8e0206 */
/*0150*/ @!P2 MOV R16, 0x4 ; /* 0x000000040010a802 */
/* 0x000fe20000000f00 */
/*0160*/ @!P3 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0fb424 */
/* 0x000fe200078e00ff */
/*0170*/ @!P0 MOV R17, 0x4 ; /* 0x0000000400118802 */
/* 0x000fe20000000f00 */
/*0180*/ @!P3 IMAD R8, R11, UR4, R6 ; /* 0x000000040b08bc24 */
/* 0x000fc4000f8e0206 */
/*0190*/ @!P0 IMAD R10, R13, UR4, R6 ; /* 0x000000040d0a8c24 */
/* 0x000fe4000f8e0206 */
/*01a0*/ @!P4 IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a000404c625 */
/* 0x000fc800078e0205 */
/*01b0*/ @!P2 IMAD.WIDE R6, R7, R16, c[0x0][0x168] ; /* 0x00005a000706a625 */
/* 0x000fe200078e0210 */
/*01c0*/ @!P4 LDG.E R12, [R4.64] ; /* 0x00000006040cc981 */
/* 0x0000a6000c1e1900 */
/*01d0*/ @!P3 IMAD.WIDE R8, R8, R15, c[0x0][0x168] ; /* 0x00005a000808b625 */
/* 0x000fe400078e020f */
/*01e0*/ @!P2 LDG.E R6, [R6.64] ; /* 0x000000060606a981 */
/* 0x0002e4000c1e1900 */
/*01f0*/ @!P0 IMAD.WIDE R10, R10, R17, c[0x0][0x168] ; /* 0x00005a000a0a8625 */
/* 0x000fe400078e0211 */
/*0200*/ @!P3 LDG.E R8, [R8.64] ; /* 0x000000060808b981 */
/* 0x000968000c1e1900 */
/*0210*/ @!P0 LDG.E R10, [R10.64] ; /* 0x000000060a0a8981 */
/* 0x000f62000c1e1900 */
/*0220*/ @!P4 LEA R13, R0, R3, 0x5 ; /* 0x00000003000dc211 */
/* 0x000fc400078e28ff */
/*0230*/ @!P2 LEA R7, R0.reuse, R3.reuse, 0x5 ; /* 0x000000030007a211 */
/* 0x0c2fe400078e28ff */
/*0240*/ @!P0 LEA R17, R0.reuse, R3, 0x5 ; /* 0x0000000300118211 */
/* 0x040fe200078e28ff */
/*0250*/ @!P3 IMAD R9, R0, 0x20, R3.reuse ; /* 0x000000200009b824 */
/* 0x110fe400078e0203 */
/*0260*/ IMAD R4, R14, 0x20, R3 ; /* 0x000000200e047824 */
/* 0x001fe400078e0203 */
/*0270*/ IMAD R5, R2, 0x20, R0 ; /* 0x0000002002057824 */
/* 0x000fc600078e0200 */
/*0280*/ ISETP.GT.AND P1, PT, R4, 0x3ff, PT ; /* 0x000003ff0400780c */
/* 0x000fc80003f24270 */
/*0290*/ ISETP.GT.OR P6, PT, R5.reuse, 0x3ff, P1 ; /* 0x000003ff0500780c */
/* 0x040fe40000fc4670 */
/*02a0*/ ISETP.GT.OR P5, PT, R5, 0x3f7, P1 ; /* 0x000003f70500780c */
/* 0x000fe20000fa4670 */
/*02b0*/ IMAD R0, R3, 0x20, R0 ; /* 0x0000002003007824 */
/* 0x000fe200078e0200 */
/*02c0*/ ULDC UR4, c[0x0][0x10] ; /* 0x0000040000047ab9 */
/* 0x000fe40000000800 */
/*02d0*/ USHF.L.U32 UR4, UR4, 0x5, URZ ; /* 0x0000000504047899 */
/* 0x000fd2000800063f */
/*02e0*/ @!P5 IADD3 R3, R5.reuse, 0x8, RZ ; /* 0x000000080503d810 */
/* 0x040fe20007ffe0ff */
/*02f0*/ @!P6 IMAD R2, R5.reuse, UR4, R4 ; /* 0x000000040502ec24 */
/* 0x040fe2000f8e0204 */
/*0300*/ @!P4 STS [R13.X4], R12 ; /* 0x0000000c0d00c388 */
/* 0x004fe80000004800 */
/*0310*/ @!P2 STS [R7.X4+0x400], R6 ; /* 0x000400060700a388 */
/* 0x0081e80000004800 */
/*0320*/ @!P3 STS [R9.X4+0x800], R8 ; /* 0x000800080900b388 */
/* 0x0203e80000004800 */
/*0330*/ @!P0 STS [R17.X4+0xc00], R10 ; /* 0x000c000a11008388 */
/* 0x0005e80000004800 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0350*/ ISETP.GT.OR P4, PT, R5, 0x3ef, P1 ; /* 0x000003ef0500780c */
/* 0x000fca0000f84670 */
/*0360*/ @!P6 LDS R11, [R0.X4] ; /* 0x00000000000be984 */
/* 0x000ee80000004800 */
/*0370*/ @!P5 LDS R13, [R0.X4+0x20] ; /* 0x00002000000dd984 */
/* 0x000f280000004800 */
/*0380*/ @!P4 LDS R15, [R0.X4+0x40] ; /* 0x00004000000fc984 */
/* 0x000f620000004800 */
/*0390*/ @!P4 IADD3 R7, R5, 0x10, RZ ; /* 0x000000100507c810 */
/* 0x001fe40007ffe0ff */
/*03a0*/ @!P6 MOV R9, 0x4 ; /* 0x000000040009e802 */
/* 0x002fc40000000f00 */
/*03b0*/ ISETP.GT.OR P1, PT, R5, 0x3e7, P1 ; /* 0x000003e70500780c */
/* 0x000fe20000f24670 */
/*03c0*/ @!P5 IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff11d424 */
/* 0x004fe200078e00ff */
/*03d0*/ @!P4 MOV R19, 0x4 ; /* 0x000000040013c802 */
/* 0x000fe20000000f00 */
/*03e0*/ @!P5 IMAD R6, R3, UR4, R4.reuse ; /* 0x000000040306dc24 */
/* 0x100fe4000f8e0204 */
/*03f0*/ @!P4 IMAD R8, R7, UR4, R4 ; /* 0x000000040708cc24 */
/* 0x000fe4000f8e0204 */
/*0400*/ @!P6 IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x000058000202e625 */
/* 0x000fc800078e0209 */
/*0410*/ @!P5 IMAD.WIDE R6, R6, R17, c[0x0][0x160] ; /* 0x000058000606d625 */
/* 0x000fc800078e0211 */
/*0420*/ @!P4 IMAD.WIDE R8, R8, R19, c[0x0][0x160] ; /* 0x000058000808c625 */
/* 0x000fe200078e0213 */
/*0430*/ @!P6 STG.E [R2.64], R11 ; /* 0x0000000b0200e986 */
/* 0x0081e8000c101906 */
/*0440*/ @!P5 STG.E [R6.64], R13 ; /* 0x0000000d0600d986 */
/* 0x0101e8000c101906 */
/*0450*/ @!P4 STG.E [R8.64], R15 ; /* 0x0000000f0800c986 */
/* 0x0201e2000c101906 */
/*0460*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0470*/ LDS R7, [R0.X4+0x60] ; /* 0x0000600000077984 */
/* 0x001e220000004800 */
/*0480*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0490*/ IADD3 R5, R5, 0x18, RZ ; /* 0x0000001805057810 */
/* 0x000fca0007ffe0ff */
/*04a0*/ IMAD R2, R5, UR4, R4 ; /* 0x0000000405027c24 */
/* 0x000fc8000f8e0204 */
/*04b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*04c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101906 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z23transposeNaiveRectanglePfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ LEA R5, R5, R2, 0x5 ; /* 0x0000000205057211 */
/* 0x001fc800078e28ff */
/*0060*/ ISETP.GT.AND P0, PT, R5, 0x3ff, PT ; /* 0x000003ff0500780c */
/* 0x000fe40003f04270 */
/*0070*/ LEA R0, R0, R3, 0x5 ; /* 0x0000000300007211 */
/* 0x002fc800078e28ff */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0x3ff, P0 ; /* 0x000003ff0000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00c0*/ USHF.L.U32 UR4, UR4, 0x5, URZ ; /* 0x0000000504047899 */
/* 0x000fe4000800063f */
/*00d0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*00e0*/ IMAD R2, R5, UR4, R0 ; /* 0x0000000405027c24 */
/* 0x000fc8000f8e0200 */
/*00f0*/ IMAD.WIDE R2, R2, R4, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0204 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ ULDC UR4, c[0x0][0x10] ; /* 0x0000040000047ab9 */
/* 0x000fe40000000800 */
/*0120*/ USHF.L.U32 UR4, UR4, 0x5, URZ ; /* 0x0000000504047899 */
/* 0x000fcc000800063f */
/*0130*/ IMAD R5, R0, UR4, R5 ; /* 0x0000000400057c24 */
/* 0x000fc8000f8e0205 */
/*0140*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fca00078e0204 */
/*0150*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z32transposeCoalescedRectangle_OrigPfPKf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*0060*/ LEA R3, R7, R6, 0x5 ; /* 0x0000000607037211 */
/* 0x001fc800078e28ff */
/*0070*/ ISETP.GT.AND P0, PT, R3, 0x3ff, PT ; /* 0x000003ff0300780c */
/* 0x000fe20003f04270 */
/*0080*/ IMAD R0, R5, 0x20, R4 ; /* 0x0000002005007824 */
/* 0x002fca00078e0204 */
/*0090*/ ISETP.GT.OR P0, PT, R0, 0x3ff, P0 ; /* 0x000003ff0000780c */
/* 0x000fda0000704670 */
/*00a0*/ @!P0 MOV R2, c[0x0][0xc] ; /* 0x0000030000028a02 */
/* 0x000fe40000000f00 */
/*00b0*/ @!P0 MOV R9, 0x4 ; /* 0x0000000400098802 */
/* 0x000fc60000000f00 */
/*00c0*/ @!P0 IMAD.SHL.U32 R2, R2, 0x20, RZ ; /* 0x0000002002028824 */
/* 0x000fc800078e00ff */
/*00d0*/ @!P0 IMAD R2, R3, R2, R0 ; /* 0x0000000203028224 */
/* 0x000fc800078e0200 */
/*00e0*/ @!P0 IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002028625 */
/* 0x000fcc00078e0209 */
/*00f0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000602028981 */
/* 0x000ea2000c1e1900 */
/*0100*/ LEA R0, R7, R4, 0x5 ; /* 0x0000000407007211 */
/* 0x000fe200078e28ff */
/*0110*/ @!P0 IMAD R7, R6, 0x20, R4 ; /* 0x0000002006078824 */
/* 0x000fe400078e0204 */
/*0120*/ IMAD R5, R5, 0x20, R6 ; /* 0x0000002005057824 */
/* 0x000fca00078e0206 */
/*0130*/ ISETP.GT.AND P1, PT, R5, 0x3ff, PT ; /* 0x000003ff0500780c */
/* 0x000fc80003f24270 */
/*0140*/ ISETP.GT.OR P1, PT, R0, 0x3ff, P1 ; /* 0x000003ff0000780c */
/* 0x000fe20000f24670 */
/*0150*/ @!P0 STS [R7.X4], R2 ; /* 0x0000000207008388 */
/* 0x0041e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0170*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0180*/ LEA R7, R4, R6, 0x5 ; /* 0x0000000604077211 */
/* 0x001fe200078e28ff */
/*0190*/ ULDC UR4, c[0x0][0x10] ; /* 0x0000040000047ab9 */
/* 0x000fe20000000800 */
/*01a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*01b0*/ USHF.L.U32 UR4, UR4, 0x5, URZ ; /* 0x0000000504047899 */
/* 0x000fc6000800063f */
/*01c0*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e260000004800 */
/*01d0*/ IMAD R2, R5, UR4, R0 ; /* 0x0000000405027c24 */
/* 0x000fc8000f8e0200 */
/*01e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*01f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Below code is based on
https://github.com/NVIDIA-developer-blog/code-samples/tree/master/series/cuda-cpp/transpose.
nvcc transpose_rectangle.cu -o transpose_rectangle
*/
#include <assert.h>
#include <stdio.h>
#define DEBUG
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline cudaError_t checkCuda(cudaError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
const int nx = 1024;
const int ny = 1024;
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float* ref, const float* res, int n, float ms) {
bool passed = true;
for (int i = 0; i < 256; i++) {
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, ref[i], res[i]);
// printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms);
}
// Original coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalescedRectangle_Orig(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
tile[threadIdx.y][threadIdx.x] = idata[y * width + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
if ((x < ny) && (y < nx)) {
odata[y * height + x] = tile[threadIdx.x][threadIdx.y];
}
}
// Naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaiveRectangle(float* odata, const float* idata) {
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
odata[(x)*height + y] = idata[width * y + (x)];
}
}
// Shared
__global__ void transposeCoalescedRectangle(float* odata, const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
__global__ void transposeNoBankConflictsRectangle(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
int main(int argc, char** argv) {
const int mem_size = nx * ny * sizeof(float);
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
int devId = 0;
if (argc > 1)
devId = atoi(argv[1]);
cudaDeviceProp prop;
checkCuda(cudaGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("%d.%d\n", prop.major, prop.minor);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n", nx, ny,
TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n", dimGrid.x, dimGrid.y,
dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda(cudaSetDevice(devId));
float* h_idata = (float*)malloc(mem_size);
float* h_cdata = (float*)malloc(mem_size);
float* h_tdata = (float*)malloc(mem_size);
float* gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda(cudaMalloc(&d_idata, mem_size));
checkCuda(cudaMalloc(&d_cdata, mem_size));
checkCuda(cudaMalloc(&d_tdata, mem_size));
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
h_idata[j * nx + i] = j * nx + i;
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < ny; i++) {
printf("\n");
for (int j = 0; j < nx; j++) {
printf("%d,",(int)h_idata[i*nx+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < nx; j++) {
printf("%d ",(int)h_idata[j]);
}
*/
// correct result for error checking
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
gold[i * ny + j] = h_idata[j * nx + i];
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < nx; i++) {
printf("\n");
for (int j = 0; j < ny; j++) {
printf("%d,",(int)gold[i*ny+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < ny; j++) {
printf("%d ",(int)gold[j]);
}
*/
printf("\nmem_size=%d\n\n", mem_size);
// device
checkCuda(cudaMemcpy(d_idata, h_idata, mem_size, cudaMemcpyHostToDevice));
// events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda(cudaEventCreate(&startEvent));
checkCuda(cudaEventCreate(&stopEvent));
float ms;
// ------------
// time kernels
// ------------
printf("%35s%20s\n", "Routine", "Bandwidth (GB/s)");
{
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, TILE_DIM, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// --------------
// transposeNaiveRectangle
// --------------
printf("%35s", "transposeNaiveRectangle");
checkCuda(cudaMemset(d_tdata, 0, mem_size));
// warmup
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeCoalescedRectangle
// ------------------
printf("%35s", "transposeCoalescedRectangle");
checkCuda(cudaMemset(d_tdata, 0, mem_size));
// warmup
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeNoBankConflictsRectangle
// ------------------
printf("%35s", "transposeNobankConflictsRectangle");
checkCuda(cudaMemset(d_tdata, 0, mem_size));
// warmup
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata,
d_idata);
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
error_exit:
// cleanup
checkCuda(cudaEventDestroy(startEvent));
checkCuda(cudaEventDestroy(stopEvent));
checkCuda(cudaFree(d_tdata));
checkCuda(cudaFree(d_cdata));
checkCuda(cudaFree(d_idata));
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} | .file "tmpxft_000a4821_00000000-6_transpose_rectangle.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9checkCuda9cudaError.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA Runtime Error: %s\n"
.section .text._Z9checkCuda9cudaError,"axG",@progbits,_Z9checkCuda9cudaError,comdat
.weak _Z9checkCuda9cudaError
.type _Z9checkCuda9cudaError, @function
_Z9checkCuda9cudaError:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
testl %edi, %edi
jne .L6
.L4:
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L4
.cfi_endproc
.LFE2057:
.size _Z9checkCuda9cudaError, .-_Z9checkCuda9cudaError
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d %f %f\n"
.LC4:
.string "%20.2f\n"
.text
.globl _Z11postprocessPKfS0_if
.type _Z11postprocessPKfS0_if, @function
_Z11postprocessPKfS0_if:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %eax
.L11:
movss (%rsi,%rax,4), %xmm1
movss (%rdi,%rax,4), %xmm2
ucomiss %xmm2, %xmm1
jp .L14
jne .L14
addq $1, %rax
cmpq $256, %rax
jne .L11
addl %edx, %edx
movslq %edx, %rax
salq $2, %rax
js .L12
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
.L13:
mulsd .LC2(%rip), %xmm2
mulsd .LC3(%rip), %xmm2
pxor %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movapd %xmm2, %xmm0
divsd %xmm1, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L7
.L14:
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
cvtss2sd %xmm1, %xmm1
movl %eax, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L7:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
shrq %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm2
jmp .L13
.cfi_endproc
.LFE2058:
.size _Z11postprocessPKfS0_if, .-_Z11postprocessPKfS0_if
.globl _Z55__device_stub__Z32transposeCoalescedRectangle_OrigPfPKfPfPKf
.type _Z55__device_stub__Z32transposeCoalescedRectangle_OrigPfPKfPfPKf, @function
_Z55__device_stub__Z32transposeCoalescedRectangle_OrigPfPKfPfPKf:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z32transposeCoalescedRectangle_OrigPfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z55__device_stub__Z32transposeCoalescedRectangle_OrigPfPKfPfPKf, .-_Z55__device_stub__Z32transposeCoalescedRectangle_OrigPfPKfPfPKf
.globl _Z32transposeCoalescedRectangle_OrigPfPKf
.type _Z32transposeCoalescedRectangle_OrigPfPKf, @function
_Z32transposeCoalescedRectangle_OrigPfPKf:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z32transposeCoalescedRectangle_OrigPfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z32transposeCoalescedRectangle_OrigPfPKf, .-_Z32transposeCoalescedRectangle_OrigPfPKf
.globl _Z46__device_stub__Z23transposeNaiveRectanglePfPKfPfPKf
.type _Z46__device_stub__Z23transposeNaiveRectanglePfPKfPfPKf, @function
_Z46__device_stub__Z23transposeNaiveRectanglePfPKfPfPKf:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z23transposeNaiveRectanglePfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z46__device_stub__Z23transposeNaiveRectanglePfPKfPfPKf, .-_Z46__device_stub__Z23transposeNaiveRectanglePfPKfPfPKf
.globl _Z23transposeNaiveRectanglePfPKf
.type _Z23transposeNaiveRectanglePfPKf, @function
_Z23transposeNaiveRectanglePfPKf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z23transposeNaiveRectanglePfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z23transposeNaiveRectanglePfPKf, .-_Z23transposeNaiveRectanglePfPKf
.globl _Z50__device_stub__Z27transposeCoalescedRectanglePfPKfPfPKf
.type _Z50__device_stub__Z27transposeCoalescedRectanglePfPKfPfPKf, @function
_Z50__device_stub__Z27transposeCoalescedRectanglePfPKfPfPKf:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z27transposeCoalescedRectanglePfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z50__device_stub__Z27transposeCoalescedRectanglePfPKfPfPKf, .-_Z50__device_stub__Z27transposeCoalescedRectanglePfPKfPfPKf
.globl _Z27transposeCoalescedRectanglePfPKf
.type _Z27transposeCoalescedRectanglePfPKf, @function
_Z27transposeCoalescedRectanglePfPKf:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z27transposeCoalescedRectanglePfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z27transposeCoalescedRectanglePfPKf, .-_Z27transposeCoalescedRectanglePfPKf
.globl _Z56__device_stub__Z33transposeNoBankConflictsRectanglePfPKfPfPKf
.type _Z56__device_stub__Z33transposeNoBankConflictsRectanglePfPKfPfPKf, @function
_Z56__device_stub__Z33transposeNoBankConflictsRectanglePfPKfPfPKf:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z33transposeNoBankConflictsRectanglePfPKf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z56__device_stub__Z33transposeNoBankConflictsRectanglePfPKfPfPKf, .-_Z56__device_stub__Z33transposeNoBankConflictsRectanglePfPKfPfPKf
.globl _Z33transposeNoBankConflictsRectanglePfPKf
.type _Z33transposeNoBankConflictsRectanglePfPKf, @function
_Z33transposeNoBankConflictsRectanglePfPKf:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z33transposeNoBankConflictsRectanglePfPKfPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z33transposeNoBankConflictsRectanglePfPKf, .-_Z33transposeNoBankConflictsRectanglePfPKf
.section .rodata.str1.1
.LC5:
.string "\nDevice : %s\n"
.LC6:
.string "%d.%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n"
.align 8
.LC8:
.string "dimGrid: %d %d %d. dimBlock: %d %d %d\n"
.section .rodata.str1.1
.LC9:
.string "\nmem_size=%d\n\n"
.LC10:
.string "Bandwidth (GB/s)"
.LC11:
.string "Routine"
.LC12:
.string "%35s%20s\n"
.LC13:
.string "transposeNaiveRectangle"
.LC14:
.string "%35s"
.LC16:
.string " ms=%f\n"
.LC17:
.string "transposeCoalescedRectangle"
.section .rodata.str1.8
.align 8
.LC18:
.string "transposeNobankConflictsRectangle"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1144, %rsp
.cfi_def_cfa_offset 1184
movq %fs:40, %rdx
movq %rdx, 1128(%rsp)
xorl %edx, %edx
movl $0, %ebx
cmpl $1, %edi
jg .L74
.L50:
leaq 96(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq %rbp, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 460(%rsp), %ecx
movl 456(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pushq $32
.cfi_def_cfa_offset 1192
pushq $32
.cfi_def_cfa_offset 1200
movl $8, %r9d
movl $32, %r8d
movl $1024, %ecx
movl $1024, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1184
pushq $1
.cfi_def_cfa_offset 1192
pushq $32
.cfi_def_cfa_offset 1200
movl $32, %r9d
movl $1, %r8d
movl $32, %ecx
movl $32, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1184
movl %ebx, %edi
call cudaSetDevice@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq %r12, %rdi
movq %r12, %rsi
movl $1024, %ecx
.L51:
leal -1024(%rcx), %eax
movq %rsi, %rdx
.L52:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L52
addq $4096, %rsi
addl $1024, %ecx
cmpl $1049600, %ecx
jne .L51
leaq 4194304(%rbp), %rcx
movl $0, %esi
.L53:
leaq -4194304(%rcx), %rax
movq %rdi, %rdx
.L54:
movss (%rdx), %xmm0
movss %xmm0, (%rax)
addq $4, %rdx
addq $4096, %rax
cmpq %rcx, %rax
jne .L54
addl $1, %esi
addq $4096, %rdi
addq $4, %rcx
cmpl $1024, %esi
jne .L53
movl $4194304, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq .LC10(%rip), %rcx
leaq .LC11(%rip), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC13(%rip), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L56:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $100, %r13d
jmp .L58
.L74:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L50
.L75:
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z46__device_stub__Z23transposeNaiveRectanglePfPKfPfPKf
jmp .L56
.L57:
subl $1, %r13d
je .L76
.L58:
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L57
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z46__device_stub__Z23transposeNaiveRectanglePfPKfPfPKf
jmp .L57
.L76:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movss 4(%rsp), %xmm0
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 4(%rsp), %xmm0
movl $1048576, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z11postprocessPKfS0_if
movl $32, 72(%rsp)
movl $32, 76(%rsp)
movl $1, 80(%rsp)
movl $32, 84(%rsp)
movl $8, 88(%rsp)
movl $1, 92(%rsp)
leaq .LC17(%rip), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L59:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $100, %r13d
jmp .L61
.L77:
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z50__device_stub__Z27transposeCoalescedRectanglePfPKfPfPKf
jmp .L59
.L60:
subl $1, %r13d
je .L78
.L61:
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L60
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z50__device_stub__Z27transposeCoalescedRectanglePfPKfPfPKf
jmp .L60
.L78:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movss 4(%rsp), %xmm0
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 4(%rsp), %xmm0
movl $1048576, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z11postprocessPKfS0_if
movl $32, 72(%rsp)
movl $32, 76(%rsp)
movl $1, 80(%rsp)
movl $32, 84(%rsp)
movl $8, 88(%rsp)
movl $1, 92(%rsp)
leaq .LC18(%rip), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L79
.L62:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $100, %r13d
jmp .L64
.L79:
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z56__device_stub__Z33transposeNoBankConflictsRectanglePfPKfPfPKf
jmp .L62
.L63:
subl $1, %r13d
je .L80
.L64:
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L63
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z56__device_stub__Z33transposeNoBankConflictsRectanglePfPKfPfPKf
jmp .L63
.L80:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movss 4(%rsp), %xmm0
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 4(%rsp), %xmm0
movl $1048576, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z11postprocessPKfS0_if
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L81
movl $0, %eax
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC19:
.string "_Z33transposeNoBankConflictsRectanglePfPKf"
.align 8
.LC20:
.string "_Z27transposeCoalescedRectanglePfPKf"
.align 8
.LC21:
.string "_Z23transposeNaiveRectanglePfPKf"
.align 8
.LC22:
.string "_Z32transposeCoalescedRectangle_OrigPfPKf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z33transposeNoBankConflictsRectanglePfPKf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z27transposeCoalescedRectanglePfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z23transposeNaiveRectanglePfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z32transposeCoalescedRectangle_OrigPfPKf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -1598689907
.long 1051772663
.align 8
.LC3:
.long 0
.long 1079574528
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC15:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Below code is based on
https://github.com/NVIDIA-developer-blog/code-samples/tree/master/series/cuda-cpp/transpose.
nvcc transpose_rectangle.cu -o transpose_rectangle
*/
#include <assert.h>
#include <stdio.h>
#define DEBUG
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline cudaError_t checkCuda(cudaError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
const int nx = 1024;
const int ny = 1024;
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float* ref, const float* res, int n, float ms) {
bool passed = true;
for (int i = 0; i < 256; i++) {
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, ref[i], res[i]);
// printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms);
}
// Original coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalescedRectangle_Orig(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
tile[threadIdx.y][threadIdx.x] = idata[y * width + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
if ((x < ny) && (y < nx)) {
odata[y * height + x] = tile[threadIdx.x][threadIdx.y];
}
}
// Naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaiveRectangle(float* odata, const float* idata) {
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
odata[(x)*height + y] = idata[width * y + (x)];
}
}
// Shared
__global__ void transposeCoalescedRectangle(float* odata, const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
__global__ void transposeNoBankConflictsRectangle(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
int main(int argc, char** argv) {
const int mem_size = nx * ny * sizeof(float);
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
int devId = 0;
if (argc > 1)
devId = atoi(argv[1]);
cudaDeviceProp prop;
checkCuda(cudaGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("%d.%d\n", prop.major, prop.minor);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n", nx, ny,
TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n", dimGrid.x, dimGrid.y,
dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda(cudaSetDevice(devId));
float* h_idata = (float*)malloc(mem_size);
float* h_cdata = (float*)malloc(mem_size);
float* h_tdata = (float*)malloc(mem_size);
float* gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda(cudaMalloc(&d_idata, mem_size));
checkCuda(cudaMalloc(&d_cdata, mem_size));
checkCuda(cudaMalloc(&d_tdata, mem_size));
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
h_idata[j * nx + i] = j * nx + i;
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < ny; i++) {
printf("\n");
for (int j = 0; j < nx; j++) {
printf("%d,",(int)h_idata[i*nx+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < nx; j++) {
printf("%d ",(int)h_idata[j]);
}
*/
// correct result for error checking
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
gold[i * ny + j] = h_idata[j * nx + i];
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < nx; i++) {
printf("\n");
for (int j = 0; j < ny; j++) {
printf("%d,",(int)gold[i*ny+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < ny; j++) {
printf("%d ",(int)gold[j]);
}
*/
printf("\nmem_size=%d\n\n", mem_size);
// device
checkCuda(cudaMemcpy(d_idata, h_idata, mem_size, cudaMemcpyHostToDevice));
// events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda(cudaEventCreate(&startEvent));
checkCuda(cudaEventCreate(&stopEvent));
float ms;
// ------------
// time kernels
// ------------
printf("%35s%20s\n", "Routine", "Bandwidth (GB/s)");
{
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, TILE_DIM, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// --------------
// transposeNaiveRectangle
// --------------
printf("%35s", "transposeNaiveRectangle");
checkCuda(cudaMemset(d_tdata, 0, mem_size));
// warmup
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeCoalescedRectangle
// ------------------
printf("%35s", "transposeCoalescedRectangle");
checkCuda(cudaMemset(d_tdata, 0, mem_size));
// warmup
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeNoBankConflictsRectangle
// ------------------
printf("%35s", "transposeNobankConflictsRectangle");
checkCuda(cudaMemset(d_tdata, 0, mem_size));
// warmup
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(cudaEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata,
d_idata);
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(cudaMemcpy(h_tdata, d_tdata, mem_size, cudaMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
error_exit:
// cleanup
checkCuda(cudaEventDestroy(startEvent));
checkCuda(cudaEventDestroy(stopEvent));
checkCuda(cudaFree(d_tdata));
checkCuda(cudaFree(d_cdata));
checkCuda(cudaFree(d_idata));
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} | /*
Below code is based on
https://github.com/NVIDIA-developer-blog/code-samples/tree/master/series/cuda-cpp/transpose.
nvcc transpose_rectangle.cu -o transpose_rectangle
*/
#include <hip/hip_runtime.h>
#include <assert.h>
#include <stdio.h>
#define DEBUG
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline hipError_t checkCuda(hipError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
const int nx = 1024;
const int ny = 1024;
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float* ref, const float* res, int n, float ms) {
bool passed = true;
for (int i = 0; i < 256; i++) {
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, ref[i], res[i]);
// printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms);
}
// Original coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalescedRectangle_Orig(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
tile[threadIdx.y][threadIdx.x] = idata[y * width + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
if ((x < ny) && (y < nx)) {
odata[y * height + x] = tile[threadIdx.x][threadIdx.y];
}
}
// Naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaiveRectangle(float* odata, const float* idata) {
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
odata[(x)*height + y] = idata[width * y + (x)];
}
}
// Shared
__global__ void transposeCoalescedRectangle(float* odata, const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
__global__ void transposeNoBankConflictsRectangle(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
int main(int argc, char** argv) {
const int mem_size = nx * ny * sizeof(float);
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
int devId = 0;
if (argc > 1)
devId = atoi(argv[1]);
hipDeviceProp_t prop;
checkCuda(hipGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("%d.%d\n", prop.major, prop.minor);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n", nx, ny,
TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n", dimGrid.x, dimGrid.y,
dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda(hipSetDevice(devId));
float* h_idata = (float*)malloc(mem_size);
float* h_cdata = (float*)malloc(mem_size);
float* h_tdata = (float*)malloc(mem_size);
float* gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda(hipMalloc(&d_idata, mem_size));
checkCuda(hipMalloc(&d_cdata, mem_size));
checkCuda(hipMalloc(&d_tdata, mem_size));
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
h_idata[j * nx + i] = j * nx + i;
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < ny; i++) {
printf("\n");
for (int j = 0; j < nx; j++) {
printf("%d,",(int)h_idata[i*nx+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < nx; j++) {
printf("%d ",(int)h_idata[j]);
}
*/
// correct result for error checking
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
gold[i * ny + j] = h_idata[j * nx + i];
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < nx; i++) {
printf("\n");
for (int j = 0; j < ny; j++) {
printf("%d,",(int)gold[i*ny+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < ny; j++) {
printf("%d ",(int)gold[j]);
}
*/
printf("\nmem_size=%d\n\n", mem_size);
// device
checkCuda(hipMemcpy(d_idata, h_idata, mem_size, hipMemcpyHostToDevice));
// events for timing
hipEvent_t startEvent, stopEvent;
checkCuda(hipEventCreate(&startEvent));
checkCuda(hipEventCreate(&stopEvent));
float ms;
// ------------
// time kernels
// ------------
printf("%35s%20s\n", "Routine", "Bandwidth (GB/s)");
{
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, TILE_DIM, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// --------------
// transposeNaiveRectangle
// --------------
printf("%35s", "transposeNaiveRectangle");
checkCuda(hipMemset(d_tdata, 0, mem_size));
// warmup
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeCoalescedRectangle
// ------------------
printf("%35s", "transposeCoalescedRectangle");
checkCuda(hipMemset(d_tdata, 0, mem_size));
// warmup
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeNoBankConflictsRectangle
// ------------------
printf("%35s", "transposeNobankConflictsRectangle");
checkCuda(hipMemset(d_tdata, 0, mem_size));
// warmup
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata,
d_idata);
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
error_exit:
// cleanup
checkCuda(hipEventDestroy(startEvent));
checkCuda(hipEventDestroy(stopEvent));
checkCuda(hipFree(d_tdata));
checkCuda(hipFree(d_cdata));
checkCuda(hipFree(d_idata));
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Below code is based on
https://github.com/NVIDIA-developer-blog/code-samples/tree/master/series/cuda-cpp/transpose.
nvcc transpose_rectangle.cu -o transpose_rectangle
*/
#include <hip/hip_runtime.h>
#include <assert.h>
#include <stdio.h>
#define DEBUG
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline hipError_t checkCuda(hipError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
const int nx = 1024;
const int ny = 1024;
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float* ref, const float* res, int n, float ms) {
bool passed = true;
for (int i = 0; i < 256; i++) {
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, ref[i], res[i]);
// printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms);
}
// Original coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalescedRectangle_Orig(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
tile[threadIdx.y][threadIdx.x] = idata[y * width + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
if ((x < ny) && (y < nx)) {
odata[y * height + x] = tile[threadIdx.x][threadIdx.y];
}
}
// Naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaiveRectangle(float* odata, const float* idata) {
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
odata[(x)*height + y] = idata[width * y + (x)];
}
}
// Shared
__global__ void transposeCoalescedRectangle(float* odata, const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
__global__ void transposeNoBankConflictsRectangle(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
int main(int argc, char** argv) {
const int mem_size = nx * ny * sizeof(float);
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
int devId = 0;
if (argc > 1)
devId = atoi(argv[1]);
hipDeviceProp_t prop;
checkCuda(hipGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("%d.%d\n", prop.major, prop.minor);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n", nx, ny,
TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n", dimGrid.x, dimGrid.y,
dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda(hipSetDevice(devId));
float* h_idata = (float*)malloc(mem_size);
float* h_cdata = (float*)malloc(mem_size);
float* h_tdata = (float*)malloc(mem_size);
float* gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda(hipMalloc(&d_idata, mem_size));
checkCuda(hipMalloc(&d_cdata, mem_size));
checkCuda(hipMalloc(&d_tdata, mem_size));
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
h_idata[j * nx + i] = j * nx + i;
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < ny; i++) {
printf("\n");
for (int j = 0; j < nx; j++) {
printf("%d,",(int)h_idata[i*nx+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < nx; j++) {
printf("%d ",(int)h_idata[j]);
}
*/
// correct result for error checking
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
gold[i * ny + j] = h_idata[j * nx + i];
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < nx; i++) {
printf("\n");
for (int j = 0; j < ny; j++) {
printf("%d,",(int)gold[i*ny+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < ny; j++) {
printf("%d ",(int)gold[j]);
}
*/
printf("\nmem_size=%d\n\n", mem_size);
// device
checkCuda(hipMemcpy(d_idata, h_idata, mem_size, hipMemcpyHostToDevice));
// events for timing
hipEvent_t startEvent, stopEvent;
checkCuda(hipEventCreate(&startEvent));
checkCuda(hipEventCreate(&stopEvent));
float ms;
// ------------
// time kernels
// ------------
printf("%35s%20s\n", "Routine", "Bandwidth (GB/s)");
{
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, TILE_DIM, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// --------------
// transposeNaiveRectangle
// --------------
printf("%35s", "transposeNaiveRectangle");
checkCuda(hipMemset(d_tdata, 0, mem_size));
// warmup
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeCoalescedRectangle
// ------------------
printf("%35s", "transposeCoalescedRectangle");
checkCuda(hipMemset(d_tdata, 0, mem_size));
// warmup
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeNoBankConflictsRectangle
// ------------------
printf("%35s", "transposeNobankConflictsRectangle");
checkCuda(hipMemset(d_tdata, 0, mem_size));
// warmup
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata,
d_idata);
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
error_exit:
// cleanup
checkCuda(hipEventDestroy(startEvent));
checkCuda(hipEventDestroy(stopEvent));
checkCuda(hipFree(d_tdata));
checkCuda(hipFree(d_cdata));
checkCuda(hipFree(d_idata));
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32transposeCoalescedRectangle_OrigPfPKf
.globl _Z32transposeCoalescedRectangle_OrigPfPKf
.p2align 8
.type _Z32transposeCoalescedRectangle_OrigPfPKf,@function
_Z32transposeCoalescedRectangle_OrigPfPKf:
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_lshl_b32 s4, s14, 5
s_lshl_b32 s5, s15, 5
s_add_u32 s2, s0, 16
v_add_nc_u32_e32 v2, s4, v1
v_add_nc_u32_e32 v3, s5, v0
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v4, v2, v3
v_cmpx_gt_i32_e32 0x400, v4
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v3, v3, s2
s_load_b64 s[2:3], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v2, v3, 5, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_lshlrev_b32_e32 v3, 2, v1
v_lshl_add_u32 v3, v0, 7, v3
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v2, s5, v1
v_add_nc_u32_e32 v3, s4, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_max_i32_e32 v4, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x400, v4
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 7, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v3, v3, s2
v_lshl_add_u32 v0, v3, 5, v2
ds_load_b32 v2, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32transposeCoalescedRectangle_OrigPfPKf
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32transposeCoalescedRectangle_OrigPfPKf, .Lfunc_end0-_Z32transposeCoalescedRectangle_OrigPfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z23transposeNaiveRectanglePfPKf
.globl _Z23transposeNaiveRectanglePfPKf
.p2align 8
.type _Z23transposeNaiveRectanglePfPKf,@function
_Z23transposeNaiveRectanglePfPKf:
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 5, v1
v_lshl_add_u32 v1, s15, 5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
v_cmpx_gt_i32_e32 0x400, v2
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshl_add_u32 v2, v2, 5, v0
v_mul_lo_u32 v0, v0, s5
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, v0, 5, v1
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[0:1]
global_load_b32 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23transposeNaiveRectanglePfPKf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z23transposeNaiveRectanglePfPKf, .Lfunc_end1-_Z23transposeNaiveRectanglePfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z27transposeCoalescedRectanglePfPKf
.globl _Z27transposeCoalescedRectanglePfPKf
.p2align 8
.type _Z27transposeCoalescedRectanglePfPKf,@function
_Z27transposeCoalescedRectanglePfPKf:
s_load_b128 s[4:7], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s8, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s3, s14, 5
s_mov_b32 s9, -8
v_add_nc_u32_e32 v4, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, s3, v3
v_lshlrev_b32_e32 v5, 2, v3
v_cmp_gt_i32_e32 vcc_lo, 0x400, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshl_add_u32 v5, v2, 7, v5
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s6, v4
s_lshl_b32 s6, s6, 8
v_lshlrev_b32_e32 v1, 5, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v1, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v5, 0x400, v5
v_add_nc_u32_e32 v0, s6, v0
s_add_i32 s9, s9, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s9, 23
s_cbranch_scc1 .LBB2_4
.LBB2_2:
v_add3_u32 v1, v4, s9, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, 0x400, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s10, s2
s_cbranch_execz .LBB2_1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_co_u32 v6, s2, s4, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s2, s5, v7, s2
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
s_branch .LBB2_1
.LBB2_4:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v4, s3, v2
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v1, s8, v3
v_lshlrev_b32_e32 v2, 2, v2
s_lshl_b32 s1, s7, 8
v_mul_lo_u32 v0, s7, v4
s_mov_b32 s4, -8
v_cmp_gt_i32_e32 vcc_lo, 0x400, v1
v_lshl_add_u32 v2, v3, 7, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v0, s8
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_6
.p2align 6
.LBB2_5:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v2, 32, v2
v_add_nc_u32_e32 v0, s1, v0
s_add_i32 s4, s4, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s4, 23
s_cbranch_scc1 .LBB2_8
.LBB2_6:
v_add3_u32 v1, v4, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, 0x400, v1
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s0
s_cbranch_execz .LBB2_5
ds_load_b32 v3, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_co_u32 v5, s0, s2, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_waitcnt lgkmcnt(0)
global_store_b32 v[5:6], v3, off
s_branch .LBB2_5
.LBB2_8:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27transposeCoalescedRectanglePfPKf
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z27transposeCoalescedRectanglePfPKf, .Lfunc_end2-_Z27transposeCoalescedRectanglePfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z33transposeNoBankConflictsRectanglePfPKf
.globl _Z33transposeNoBankConflictsRectanglePfPKf
.p2align 8
.type _Z33transposeNoBankConflictsRectanglePfPKf,@function
_Z33transposeNoBankConflictsRectanglePfPKf:
s_load_b128 s[4:7], s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s8, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s3, s14, 5
s_mov_b32 s9, -8
v_add_nc_u32_e32 v4, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, s3, v3
v_lshlrev_b32_e32 v5, 2, v3
v_cmp_gt_i32_e32 vcc_lo, 0x400, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u32_u24 v5, v2, 0x84, v5
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s6, v4
s_lshl_b32 s6, s6, 8
v_lshlrev_b32_e32 v1, 5, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v1, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB3_2
.p2align 6
.LBB3_1:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v5, 0x420, v5
v_add_nc_u32_e32 v0, s6, v0
s_add_i32 s9, s9, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s9, 23
s_cbranch_scc1 .LBB3_4
.LBB3_2:
v_add3_u32 v1, v4, s9, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, 0x400, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s10, s2
s_cbranch_execz .LBB3_1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_add_co_u32 v6, s2, s4, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s2, s5, v7, s2
global_load_b32 v1, v[6:7], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
s_branch .LBB3_1
.LBB3_4:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v4, s3, v2
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v1, s8, v3
v_lshlrev_b32_e32 v2, 2, v2
s_lshl_b32 s1, s7, 8
v_mul_lo_u32 v0, s7, v4
s_mov_b32 s4, -8
v_cmp_gt_i32_e32 vcc_lo, 0x400, v1
v_mad_u32_u24 v2, v3, 0x84, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshlrev_b32_e32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v0, s8
s_set_inst_prefetch_distance 0x1
s_branch .LBB3_6
.p2align 6
.LBB3_5:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v2, 32, v2
v_add_nc_u32_e32 v0, s1, v0
s_add_i32 s4, s4, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s4, 23
s_cbranch_scc1 .LBB3_8
.LBB3_6:
v_add3_u32 v1, v4, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, 0x400, v1
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s0
s_cbranch_execz .LBB3_5
ds_load_b32 v3, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_co_u32 v5, s0, s2, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
s_waitcnt lgkmcnt(0)
global_store_b32 v[5:6], v3, off
s_branch .LBB3_5
.LBB3_8:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33transposeNoBankConflictsRectanglePfPKf
.amdhsa_group_segment_fixed_size 4224
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z33transposeNoBankConflictsRectanglePfPKf, .Lfunc_end3-_Z33transposeNoBankConflictsRectanglePfPKf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32transposeCoalescedRectangle_OrigPfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32transposeCoalescedRectangle_OrigPfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23transposeNaiveRectanglePfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23transposeNaiveRectanglePfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27transposeCoalescedRectanglePfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27transposeCoalescedRectanglePfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4224
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33transposeNoBankConflictsRectanglePfPKf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z33transposeNoBankConflictsRectanglePfPKf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Below code is based on
https://github.com/NVIDIA-developer-blog/code-samples/tree/master/series/cuda-cpp/transpose.
nvcc transpose_rectangle.cu -o transpose_rectangle
*/
#include <hip/hip_runtime.h>
#include <assert.h>
#include <stdio.h>
#define DEBUG
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline hipError_t checkCuda(hipError_t result) {
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
const int nx = 1024;
const int ny = 1024;
const int TILE_DIM = 32;
const int BLOCK_ROWS = 8;
const int NUM_REPS = 100;
// Check errors and print GB/s
void postprocess(const float* ref, const float* res, int n, float ms) {
bool passed = true;
for (int i = 0; i < 256; i++) {
if (res[i] != ref[i]) {
printf("%d %f %f\n", i, ref[i], res[i]);
// printf("%25s\n", "*** FAILED ***");
passed = false;
break;
}
}
if (passed)
printf("%20.2f\n", 2 * n * sizeof(float) * 1e-6 * NUM_REPS / ms);
}
// Original coalesced transpose
// Uses shared memory to achieve coalesing in both reads and writes
// Tile width == #banks causes shared memory bank conflicts.
__global__ void transposeCoalescedRectangle_Orig(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
tile[threadIdx.y][threadIdx.x] = idata[y * width + x];
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
if ((x < ny) && (y < nx)) {
odata[y * height + x] = tile[threadIdx.x][threadIdx.y];
}
}
// Naive transpose
// Simplest transpose; doesn't use shared memory.
// Global memory reads are coalesced but writes are not.
__global__ void transposeNaiveRectangle(float* odata, const float* idata) {
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
if ((x < nx) && (y < ny)) {
odata[(x)*height + y] = idata[width * y + (x)];
}
}
// Shared
__global__ void transposeCoalescedRectangle(float* odata, const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
__global__ void transposeNoBankConflictsRectangle(float* odata,
const float* idata) {
__shared__ float tile[TILE_DIM][TILE_DIM + 1];
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int width = gridDim.x * TILE_DIM;
int height = gridDim.y * TILE_DIM;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < nx) && ((y + j) < ny)) {
tile[threadIdx.y + j][threadIdx.x] = idata[(y + j) * width + x];
}
}
__syncthreads();
x = blockIdx.y * TILE_DIM + threadIdx.x; // transpose block offset
y = blockIdx.x * TILE_DIM + threadIdx.y;
for (int j = 0; j < TILE_DIM; j += BLOCK_ROWS) {
if ((x < ny) && ((y + j) < nx)) {
odata[(y + j) * height + x] = tile[threadIdx.x][threadIdx.y + j];
}
}
}
int main(int argc, char** argv) {
const int mem_size = nx * ny * sizeof(float);
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
int devId = 0;
if (argc > 1)
devId = atoi(argv[1]);
hipDeviceProp_t prop;
checkCuda(hipGetDeviceProperties(&prop, devId));
printf("\nDevice : %s\n", prop.name);
printf("%d.%d\n", prop.major, prop.minor);
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n", nx, ny,
TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n", dimGrid.x, dimGrid.y,
dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
checkCuda(hipSetDevice(devId));
float* h_idata = (float*)malloc(mem_size);
float* h_cdata = (float*)malloc(mem_size);
float* h_tdata = (float*)malloc(mem_size);
float* gold = (float*)malloc(mem_size);
float *d_idata, *d_cdata, *d_tdata;
checkCuda(hipMalloc(&d_idata, mem_size));
checkCuda(hipMalloc(&d_cdata, mem_size));
checkCuda(hipMalloc(&d_tdata, mem_size));
// check parameters and calculate execution configuration
if (nx % TILE_DIM || ny % TILE_DIM) {
printf("nx and ny must be a multiple of TILE_DIM\n");
goto error_exit;
}
if (TILE_DIM % BLOCK_ROWS) {
printf("TILE_DIM must be a multiple of BLOCK_ROWS\n");
goto error_exit;
}
// host
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
h_idata[j * nx + i] = j * nx + i;
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < ny; i++) {
printf("\n");
for (int j = 0; j < nx; j++) {
printf("%d,",(int)h_idata[i*nx+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < nx; j++) {
printf("%d ",(int)h_idata[j]);
}
*/
// correct result for error checking
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
gold[i * ny + j] = h_idata[j * nx + i];
}
}
/* Print for tfjs sensor
// correct result for error checking
printf("\n[");
for (int i = 0; i < nx; i++) {
printf("\n");
for (int j = 0; j < ny; j++) {
printf("%d,",(int)gold[i*ny+j]);
}
}
printf("\n],[64,64]);");
*/
/*
for (int j = 0; j < ny; j++) {
printf("%d ",(int)gold[j]);
}
*/
printf("\nmem_size=%d\n\n", mem_size);
// device
checkCuda(hipMemcpy(d_idata, h_idata, mem_size, hipMemcpyHostToDevice));
// events for timing
hipEvent_t startEvent, stopEvent;
checkCuda(hipEventCreate(&startEvent));
checkCuda(hipEventCreate(&stopEvent));
float ms;
// ------------
// time kernels
// ------------
printf("%35s%20s\n", "Routine", "Bandwidth (GB/s)");
{
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, TILE_DIM, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// --------------
// transposeNaiveRectangle
// --------------
printf("%35s", "transposeNaiveRectangle");
checkCuda(hipMemset(d_tdata, 0, mem_size));
// warmup
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNaiveRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeCoalescedRectangle
// ------------------
printf("%35s", "transposeCoalescedRectangle");
checkCuda(hipMemset(d_tdata, 0, mem_size));
// warmup
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeCoalescedRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
{
dim3 dimGrid(nx / TILE_DIM, ny / TILE_DIM, 1);
// dim3 dimBlock(TILE_DIM, TILE_DIM, 1);
dim3 dimBlock(TILE_DIM, BLOCK_ROWS, 1);
/*
printf("Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n",
nx, ny, TILE_DIM, BLOCK_ROWS, TILE_DIM, TILE_DIM);
printf("dimGrid: %d %d %d. dimBlock: %d %d %d\n",
dimGrid.x, dimGrid.y, dimGrid.z, dimBlock.x, dimBlock.y, dimBlock.z);
*/
// ------------------
// transposeNoBankConflictsRectangle
// ------------------
printf("%35s", "transposeNobankConflictsRectangle");
checkCuda(hipMemset(d_tdata, 0, mem_size));
// warmup
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata, d_idata);
checkCuda(hipEventRecord(startEvent, 0));
for (int i = 0; i < NUM_REPS; i++)
transposeNoBankConflictsRectangle<<<dimGrid, dimBlock>>>(d_tdata,
d_idata);
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&ms, startEvent, stopEvent));
checkCuda(hipMemcpy(h_tdata, d_tdata, mem_size, hipMemcpyDeviceToHost));
printf(" ms=%f\n", ms / NUM_REPS);
postprocess(gold, h_tdata, nx * ny, ms);
}
error_exit:
// cleanup
checkCuda(hipEventDestroy(startEvent));
checkCuda(hipEventDestroy(stopEvent));
checkCuda(hipFree(d_tdata));
checkCuda(hipFree(d_cdata));
checkCuda(hipFree(d_idata));
free(h_idata);
free(h_tdata);
free(h_cdata);
free(gold);
} | .text
.file "transpose_rectangle.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11postprocessPKfS0_if
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI0_3:
.quad 0x4059000000000000 # double 100
.text
.globl _Z11postprocessPKfS0_if
.p2align 4, 0x90
.type _Z11postprocessPKfS0_if,@function
_Z11postprocessPKfS0_if: # @_Z11postprocessPKfS0_if
.cfi_startproc
# %bb.0:
movq %rsi, %rax
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movss (%rax,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%rdi,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB0_4
jp .LBB0_4
# %bb.2: # in Loop: Header=BB0_1 Depth=1
incq %rsi
cmpq $256, %rsi # imm = 0x100
jne .LBB0_1
# %bb.3: # %.critedge
addl %edx, %edx
movslq %edx, %rax
shlq $2, %rax
movq %rax, %xmm2
punpckldq .LCPI0_0(%rip), %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
subpd .LCPI0_1(%rip), %xmm2
movapd %xmm2, %xmm1
unpckhpd %xmm2, %xmm1 # xmm1 = xmm1[1],xmm2[1]
addsd %xmm2, %xmm1
mulsd .LCPI0_2(%rip), %xmm1
mulsd .LCPI0_3(%rip), %xmm1
cvtss2sd %xmm0, %xmm0
divsd %xmm0, %xmm1
movl $.L.str.1, %edi
movapd %xmm1, %xmm0
movb $1, %al
jmp printf # TAILCALL
.LBB0_4:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
movb $2, %al
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z11postprocessPKfS0_if, .Lfunc_end0-_Z11postprocessPKfS0_if
.cfi_endproc
# -- End function
.globl _Z47__device_stub__transposeCoalescedRectangle_OrigPfPKf # -- Begin function _Z47__device_stub__transposeCoalescedRectangle_OrigPfPKf
.p2align 4, 0x90
.type _Z47__device_stub__transposeCoalescedRectangle_OrigPfPKf,@function
_Z47__device_stub__transposeCoalescedRectangle_OrigPfPKf: # @_Z47__device_stub__transposeCoalescedRectangle_OrigPfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z32transposeCoalescedRectangle_OrigPfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z47__device_stub__transposeCoalescedRectangle_OrigPfPKf, .Lfunc_end1-_Z47__device_stub__transposeCoalescedRectangle_OrigPfPKf
.cfi_endproc
# -- End function
.globl _Z38__device_stub__transposeNaiveRectanglePfPKf # -- Begin function _Z38__device_stub__transposeNaiveRectanglePfPKf
.p2align 4, 0x90
.type _Z38__device_stub__transposeNaiveRectanglePfPKf,@function
_Z38__device_stub__transposeNaiveRectanglePfPKf: # @_Z38__device_stub__transposeNaiveRectanglePfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z23transposeNaiveRectanglePfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z38__device_stub__transposeNaiveRectanglePfPKf, .Lfunc_end2-_Z38__device_stub__transposeNaiveRectanglePfPKf
.cfi_endproc
# -- End function
.globl _Z42__device_stub__transposeCoalescedRectanglePfPKf # -- Begin function _Z42__device_stub__transposeCoalescedRectanglePfPKf
.p2align 4, 0x90
.type _Z42__device_stub__transposeCoalescedRectanglePfPKf,@function
_Z42__device_stub__transposeCoalescedRectanglePfPKf: # @_Z42__device_stub__transposeCoalescedRectanglePfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z27transposeCoalescedRectanglePfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z42__device_stub__transposeCoalescedRectanglePfPKf, .Lfunc_end3-_Z42__device_stub__transposeCoalescedRectanglePfPKf
.cfi_endproc
# -- End function
.globl _Z48__device_stub__transposeNoBankConflictsRectanglePfPKf # -- Begin function _Z48__device_stub__transposeNoBankConflictsRectanglePfPKf
.p2align 4, 0x90
.type _Z48__device_stub__transposeNoBankConflictsRectanglePfPKf,@function
_Z48__device_stub__transposeNoBankConflictsRectanglePfPKf: # @_Z48__device_stub__transposeNoBankConflictsRectanglePfPKf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z33transposeNoBankConflictsRectanglePfPKf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z48__device_stub__transposeNoBankConflictsRectanglePfPKf, .Lfunc_end4-_Z48__device_stub__transposeNoBankConflictsRectanglePfPKf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x42c80000 # float 100
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x408a36e2eb1c432c # double 838.86079999999993
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1624, %rsp # imm = 0x658
.cfi_def_cfa_offset 1680
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
cmpl $2, %edi
jl .LBB5_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB5_2:
leaq 152(%rsp), %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB5_3
.LBB5_4: # %_Z9checkCuda10hipError_t.exit
leaq 152(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 512(%rsp), %esi
movl 516(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.4, %edi
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
movl $32, %ecx
movl $8, %r8d
movl $32, %r9d
xorl %eax, %eax
pushq $32
.cfi_adjust_cfa_offset 8
callq printf
addq $8, %rsp
.cfi_adjust_cfa_offset -8
movl $.L.str.5, %edi
movl $32, %esi
movl $32, %edx
movl $1, %ecx
movl $32, %r8d
movl $32, %r9d
xorl %eax, %eax
pushq $1
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl %ebx, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB5_5
.LBB5_6: # %_Z9checkCuda10hipError_t.exit102
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r12
leaq 112(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB5_7
.LBB5_8: # %_Z9checkCuda10hipError_t.exit104
leaq 144(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB5_9
.LBB5_10: # %_Z9checkCuda10hipError_t.exit106
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
jne .LBB5_11
.LBB5_12: # %.preheader227.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_13: # %.preheader227
# =>This Loop Header: Depth=1
# Child Loop BB5_14 Depth 2
movl $1024, %edx # imm = 0x400
movq %rax, %rsi
.p2align 4, 0x90
.LBB5_14: # Parent Loop BB5_13 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %esi, %xmm0
movss %xmm0, (%rbx,%rsi,4)
incq %rsi
decq %rdx
jne .LBB5_14
# %bb.15: # in Loop: Header=BB5_13 Depth=1
incq %rcx
addq $1024, %rax # imm = 0x400
cmpq $1024, %rcx # imm = 0x400
jne .LBB5_13
# %bb.16: # %.preheader.preheader
xorl %eax, %eax
movq %r12, %rcx
movq %rbx, %rdx
.p2align 4, 0x90
.LBB5_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_18 Depth 2
movq %rcx, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB5_18: # Parent Loop BB5_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi)
incq %rdi
addq $4096, %rsi # imm = 0x1000
cmpq $1024, %rdi # imm = 0x400
jne .LBB5_18
# %bb.19: # in Loop: Header=BB5_17 Depth=1
incq %rax
addq $4096, %rdx # imm = 0x1000
addq $4, %rcx
cmpq $1024, %rax # imm = 0x400
jne .LBB5_17
# %bb.20:
movl $.L.str.6, %edi
movl $4194304, %esi # imm = 0x400000
xorl %eax, %eax
callq printf
movq 112(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_21
.LBB5_22: # %_Z9checkCuda10hipError_t.exit110
leaq 120(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB5_23
.LBB5_24: # %_Z9checkCuda10hipError_t.exit112
leaq 88(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB5_25
.LBB5_26: # %_Z9checkCuda10hipError_t.exit114
movl $.L.str.7, %edi
movl $.L.str.8, %esi
movl $.L.str.9, %edx
xorl %eax, %eax
callq printf
movl $.L.str.10, %edi
movl $.L.str.11, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB5_27
.LBB5_28: # %_Z9checkCuda10hipError_t.exit116
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_30
# %bb.29:
movq 16(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23transposeNaiveRectanglePfPKf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_30:
movq %r12, 128(%rsp) # 8-byte Spill
movq %r15, 136(%rsp) # 8-byte Spill
movq 120(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB5_31
.LBB5_32: # %_Z9checkCuda10hipError_t.exit118
movl $100, %r13d
leaq 40(%rsp), %rbp
leaq 32(%rsp), %r15
leaq 24(%rsp), %r14
leaq 96(%rsp), %r12
jmp .LBB5_33
.p2align 4, 0x90
.LBB5_35: # in Loop: Header=BB5_33 Depth=1
decl %r13d
je .LBB5_36
.LBB5_33: # =>This Inner Loop Header: Depth=1
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_35
# %bb.34: # in Loop: Header=BB5_33 Depth=1
movq 16(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z23transposeNaiveRectanglePfPKf, %edi
movq %r12, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_35
.LBB5_36:
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB5_37
.LBB5_38: # %_Z9checkCuda10hipError_t.exit120
movq 88(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
movq 136(%rsp), %r15 # 8-byte Reload
movq 128(%rsp), %r12 # 8-byte Reload
jne .LBB5_39
.LBB5_40: # %_Z9checkCuda10hipError_t.exit122
movq 120(%rsp), %rsi
movq 88(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB5_41
.LBB5_42: # %_Z9checkCuda10hipError_t.exit124
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_43
.LBB5_44: # %_Z9checkCuda10hipError_t.exit126
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
xorl %esi, %esi
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB5_45: # =>This Inner Loop Header: Depth=1
movss (%r15,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r12,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB5_46
jp .LBB5_46
# %bb.47: # in Loop: Header=BB5_45 Depth=1
incq %rsi
cmpq $256, %rsi # imm = 0x100
jne .LBB5_45
# %bb.48: # %.critedge.i
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LCPI5_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
jmp .LBB5_49
.LBB5_46:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
movb $2, %al
callq printf
.LBB5_49: # %_Z11postprocessPKfS0_if.exit
movl $.L.str.10, %edi
movl $.L.str.13, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB5_50
.LBB5_51: # %_Z9checkCuda10hipError_t.exit128
movabsq $34359738400, %rdx # imm = 0x800000020
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_53
# %bb.52:
movq 16(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27transposeCoalescedRectanglePfPKf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_53:
movq 120(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB5_54
.LBB5_55: # %_Z9checkCuda10hipError_t.exit142
movl $100, %ebp
leaq 40(%rsp), %r15
leaq 32(%rsp), %r14
leaq 24(%rsp), %r13
leaq 96(%rsp), %r12
jmp .LBB5_56
.p2align 4, 0x90
.LBB5_58: # in Loop: Header=BB5_56 Depth=1
decl %ebp
je .LBB5_59
.LBB5_56: # =>This Inner Loop Header: Depth=1
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movabsq $34359738400, %rdx # imm = 0x800000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_58
# %bb.57: # in Loop: Header=BB5_56 Depth=1
movq 16(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z27transposeCoalescedRectanglePfPKf, %edi
movq %r12, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_58
.LBB5_59:
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
movq 128(%rsp), %r12 # 8-byte Reload
jne .LBB5_60
.LBB5_61: # %_Z9checkCuda10hipError_t.exit144
movq 88(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
movq 136(%rsp), %r15 # 8-byte Reload
jne .LBB5_62
.LBB5_63: # %_Z9checkCuda10hipError_t.exit146
movq 120(%rsp), %rsi
movq 88(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB5_64
.LBB5_65: # %_Z9checkCuda10hipError_t.exit148
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_66
.LBB5_67: # %_Z9checkCuda10hipError_t.exit150
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
xorl %esi, %esi
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB5_68: # =>This Inner Loop Header: Depth=1
movss (%r15,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r12,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB5_69
jp .LBB5_69
# %bb.70: # in Loop: Header=BB5_68 Depth=1
incq %rsi
cmpq $256, %rsi # imm = 0x100
jne .LBB5_68
# %bb.71: # %.critedge.i154
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LCPI5_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
jmp .LBB5_72
.LBB5_69:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
movb $2, %al
callq printf
.LBB5_72: # %_Z11postprocessPKfS0_if.exit155
movl $.L.str.10, %edi
movl $.L.str.14, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB5_73
.LBB5_74: # %_Z9checkCuda10hipError_t.exit157
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movabsq $34359738400, %rdx # imm = 0x800000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_76
# %bb.75:
movq 16(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z33transposeNoBankConflictsRectanglePfPKf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_76:
movq 120(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB5_77
.LBB5_78: # %_Z9checkCuda10hipError_t.exit171
movl $100, %ebp
leaq 40(%rsp), %r15
leaq 32(%rsp), %r14
leaq 24(%rsp), %r13
leaq 96(%rsp), %r12
jmp .LBB5_79
.p2align 4, 0x90
.LBB5_81: # in Loop: Header=BB5_79 Depth=1
decl %ebp
je .LBB5_82
.LBB5_79: # =>This Inner Loop Header: Depth=1
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movabsq $34359738400, %rdx # imm = 0x800000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_81
# %bb.80: # in Loop: Header=BB5_79 Depth=1
movq 16(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z33transposeNoBankConflictsRectanglePfPKf, %edi
movq %r12, %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_81
.LBB5_82:
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
movq 128(%rsp), %r12 # 8-byte Reload
jne .LBB5_83
.LBB5_84: # %_Z9checkCuda10hipError_t.exit173
movq 88(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
movq 136(%rsp), %r15 # 8-byte Reload
jne .LBB5_85
.LBB5_86: # %_Z9checkCuda10hipError_t.exit175
movq 120(%rsp), %rsi
movq 88(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB5_87
.LBB5_88: # %_Z9checkCuda10hipError_t.exit177
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_89
.LBB5_90: # %_Z9checkCuda10hipError_t.exit179
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
xorl %esi, %esi
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB5_91: # =>This Inner Loop Header: Depth=1
movss (%r15,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss (%r12,%rsi,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB5_92
jp .LBB5_92
# %bb.93: # in Loop: Header=BB5_91 Depth=1
incq %rsi
cmpq $256, %rsi # imm = 0x100
jne .LBB5_91
# %bb.94: # %.critedge.i183
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LCPI5_1(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
jmp .LBB5_95
.LBB5_92:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
movb $2, %al
callq printf
.LBB5_95: # %_Z11postprocessPKfS0_if.exit184
movq 120(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB5_96
.LBB5_97: # %_Z9checkCuda10hipError_t.exit186
movq 88(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB5_98
.LBB5_99: # %_Z9checkCuda10hipError_t.exit188
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_100
.LBB5_101: # %_Z9checkCuda10hipError_t.exit190
movq 144(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_102
.LBB5_103: # %_Z9checkCuda10hipError_t.exit192
movq 112(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_104
.LBB5_105: # %_Z9checkCuda10hipError_t.exit194
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $1624, %rsp # imm = 0x658
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_3:
.cfi_def_cfa_offset 1680
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_4
.LBB5_5:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_6
.LBB5_7:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_8
.LBB5_9:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_10
.LBB5_11:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_12
.LBB5_21:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_22
.LBB5_23:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_24
.LBB5_25:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_26
.LBB5_27:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_28
.LBB5_31:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_32
.LBB5_37:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_38
.LBB5_39:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_40
.LBB5_41:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_42
.LBB5_43:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_44
.LBB5_50:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_51
.LBB5_54:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_55
.LBB5_60:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_61
.LBB5_62:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_63
.LBB5_64:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_65
.LBB5_66:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_67
.LBB5_73:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_74
.LBB5_77:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_78
.LBB5_83:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_84
.LBB5_85:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_86
.LBB5_87:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_88
.LBB5_89:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_90
.LBB5_96:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_97
.LBB5_98:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_99
.LBB5_100:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_101
.LBB5_102:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_103
.LBB5_104:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_105
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32transposeCoalescedRectangle_OrigPfPKf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23transposeNaiveRectanglePfPKf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27transposeCoalescedRectanglePfPKf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33transposeNoBankConflictsRectanglePfPKf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %f %f\n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%20.2f\n"
.size .L.str.1, 8
.type _Z32transposeCoalescedRectangle_OrigPfPKf,@object # @_Z32transposeCoalescedRectangle_OrigPfPKf
.section .rodata,"a",@progbits
.globl _Z32transposeCoalescedRectangle_OrigPfPKf
.p2align 3, 0x0
_Z32transposeCoalescedRectangle_OrigPfPKf:
.quad _Z47__device_stub__transposeCoalescedRectangle_OrigPfPKf
.size _Z32transposeCoalescedRectangle_OrigPfPKf, 8
.type _Z23transposeNaiveRectanglePfPKf,@object # @_Z23transposeNaiveRectanglePfPKf
.globl _Z23transposeNaiveRectanglePfPKf
.p2align 3, 0x0
_Z23transposeNaiveRectanglePfPKf:
.quad _Z38__device_stub__transposeNaiveRectanglePfPKf
.size _Z23transposeNaiveRectanglePfPKf, 8
.type _Z27transposeCoalescedRectanglePfPKf,@object # @_Z27transposeCoalescedRectanglePfPKf
.globl _Z27transposeCoalescedRectanglePfPKf
.p2align 3, 0x0
_Z27transposeCoalescedRectanglePfPKf:
.quad _Z42__device_stub__transposeCoalescedRectanglePfPKf
.size _Z27transposeCoalescedRectanglePfPKf, 8
.type _Z33transposeNoBankConflictsRectanglePfPKf,@object # @_Z33transposeNoBankConflictsRectanglePfPKf
.globl _Z33transposeNoBankConflictsRectanglePfPKf
.p2align 3, 0x0
_Z33transposeNoBankConflictsRectanglePfPKf:
.quad _Z48__device_stub__transposeNoBankConflictsRectanglePfPKf
.size _Z33transposeNoBankConflictsRectanglePfPKf, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "\nDevice : %s\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d.%d\n"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Matrix size: %d %d, Block size: %d %d, Tile size: %d %d\n"
.size .L.str.4, 57
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "dimGrid: %d %d %d. dimBlock: %d %d %d\n"
.size .L.str.5, 39
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nmem_size=%d\n\n"
.size .L.str.6, 15
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%35s%20s\n"
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Routine"
.size .L.str.8, 8
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Bandwidth (GB/s)"
.size .L.str.9, 17
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%35s"
.size .L.str.10, 5
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "transposeNaiveRectangle"
.size .L.str.11, 24
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " ms=%f\n"
.size .L.str.12, 8
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "transposeCoalescedRectangle"
.size .L.str.13, 28
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "transposeNobankConflictsRectangle"
.size .L.str.14, 34
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "CUDA Runtime Error: %s\n"
.size .L.str.15, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z32transposeCoalescedRectangle_OrigPfPKf"
.size .L__unnamed_1, 42
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z23transposeNaiveRectanglePfPKf"
.size .L__unnamed_2, 33
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z27transposeCoalescedRectanglePfPKf"
.size .L__unnamed_3, 37
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z33transposeNoBankConflictsRectanglePfPKf"
.size .L__unnamed_4, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__transposeCoalescedRectangle_OrigPfPKf
.addrsig_sym _Z38__device_stub__transposeNaiveRectanglePfPKf
.addrsig_sym _Z42__device_stub__transposeCoalescedRectanglePfPKf
.addrsig_sym _Z48__device_stub__transposeNoBankConflictsRectanglePfPKf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32transposeCoalescedRectangle_OrigPfPKf
.addrsig_sym _Z23transposeNaiveRectanglePfPKf
.addrsig_sym _Z27transposeCoalescedRectanglePfPKf
.addrsig_sym _Z33transposeNoBankConflictsRectanglePfPKf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <stdio.h>
#define BLOCK_SIZE 512
#define HIDDEN_SIZE 17
#define ETA 0.3
#define MOMENT 0.3
/*
__device__ float squash(float x ) {
//float m;
//x = -x;
//m = 1 + x + x*x/2 + x*x*x/6 + x*x*x*x/24 + x*x*x*x*x/120;
//return(1.0 / (1.0 + m));
return (1.0 / (1.0 + exp(-x)));
}
*/
/*
__global__ void kernel_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
int threadIdx_x = threadIdx.x;
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < inp) {
float val = 0.0;
for(int i=1; i < hidden ; i++) {
val = input_units[element] * input_weights[(element * hidden) + i] ;
// printf("%d, %d, %f, %f, %f\n", element, i, input_weights[(element * hidden) + i] , input_units[element], val);
atomicAdd(&hidden_units[i], val);
}
}
// nt i=1; i < hidden ; i++) {
//(f(element==0) {
// hidden_units[0] = 0.0;
// }
}
*/
__global__ void kernel_bpnn_layerforward(float *input_units_master, float *hidden_units_master, float *input_weights_master, int inp, int hidden) {
int tx = threadIdx.x;
int element = threadIdx.x + blockDim.x * blockIdx.x;
// Store Input Units, Input Weights in shared memory
__shared__ float input_units[BLOCK_SIZE];
__shared__ float input_weights[18*BLOCK_SIZE];
__shared__ float hidden_units[17];
if(element < inp) {
// Read Data from Global memory to Shared memory
input_units[tx] = input_units_master[element];
// printf("PROBLEM------ %d, %d, %f\n", element, tx, input_units[tx]);
int i;
for(i=0; i<hidden; i++) {
input_weights[(tx*hidden)+i] = input_weights_master[(element * hidden) + i];
hidden_units[i] = 0.0;
hidden_units_master[i] = 0.0;
}
// Sync All Threads
__syncthreads();
// Calculate Intermediate results in Shared memory
for(i=1; i<hidden; i++) {
float result = input_units[tx] * input_weights[(tx*hidden)+i];
//hidden_units[i] += result;
atomicAdd(&(hidden_units[i]), result);
//printf("Intermediate: %d, %d, %f * %f, %f \n", element, i,input_units[tx] , input_weights[(tx*hidden)+i], result);
}
__syncthreads();
// Store final results in Main memory
if(tx ==0) {
for(i=1; i<hidden; i++) {
atomicAdd(&(hidden_units_master[i]), hidden_units[i]);
//hidden_units_master[tx] = hidden_units[tx];
// printf("SUM: %d, %d, %f, %f \n", element, i, hidden_units[i], hidden_units_master[i]);
if(element == 0) {
hidden_units_master[0] = 0.0;
}
}
}
}
}
__global__ void gpu_output_error_kernel_function(float *delta, float *t, float *o, int count, float *err) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element != 0 && element < count) {
delta[element] = o[element] * ( 1.0 - o[element]) * (t[element] - o[element]);
// printf("Output err: %d, %f, %f = %f \n", element, o[element], t[element], delta[element]);
}
}
__global__ void kernel_squash(float *hidden, int count) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element >0 && element < count) {
float orig = hidden[element];
hidden[element] = (1.0 / (1.0 + exp(- orig)));
// printf("Element: %d, Orig: %f, ,squash: %f \n", element, orig, hidden[element]);
}
}
__global__ void gpu_hidden_error_kernel_function (float *hidden_delta_d, int hid, float *output_delta_d, int out, float *hidden_weights_d, float *hidden_units_d) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < hid) {
// for(int i =1; i < out; i++) {
float h = hidden_units_d[element] ;
float sum = output_delta_d[1] * hidden_weights_d[element];
//printf("%d, %f * %f = %f \n", element, output_delta_d[1], hidden_weights_d[element], sum);
hidden_delta_d[element] = h * (1.0 -h) * sum;
//printf("%d => %f * (1.0 - %f) * %f = %f\n", element, h,h, sum, hidden_delta_d[element]);
// }
}
}
__global__ void gpu_weight_adjust_function(float *delta, int out, float *hidden_units, int hid, float *hidden_weights) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < hid) {
float new_dw = ((ETA * delta[1] * hidden_units[element]) + (MOMENT * 0));
hidden_weights[element] += new_dw;
//printf("Element: %d, new val = %f, %f \n", element, new_dw, hidden_weights[element]);
}
}
/// Algorithm using Naive method
/*
void gpu_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
// Place holder to complete input sanity check
//Allocate Blocks
dim3 DimGrid((inp-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE+1, 1, 1);
// Invoke CUDA kernel -----------------------------------------------------
kernel_bpnn_layerforward<<<DimGrid, DimBlock>>>(input_units, hidden_units, input_weights, inp, hidden);
cudaDeviceSynchronize();
dim3 DimGrid2((hidden-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock2(BLOCK_SIZE+1, 1, 1);
// Invoke Squashing kernel
kernel_squash<<<DimGrid2, DimBlock2>>>(hidden_units, hidden);
}
*/
// Algorithm using shared memory
void gpu_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
dim3 DimGrid((inp-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
kernel_bpnn_layerforward<<<DimGrid, DimBlock>>>(input_units, hidden_units, input_weights, inp, hidden);
cudaDeviceSynchronize();
dim3 DimGrid2(1, 1, 1);
dim3 DimBlock2(hidden, 1, 1);
// Invoke Squashing kernel
kernel_squash<<<DimGrid2, DimBlock2>>>(hidden_units, hidden);
}
void gpu_output_error_kernel(float *delta, float *target, float *output, int count, float *err) {
dim3 DimGrid((count-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_output_error_kernel_function<<<DimGrid, DimBlock>>>(delta, target, output, count, err);
}
void gpu_hidden_error_kernel(float *hidden_delta_d , int hid, float *output_delta_d, int out, float *hidden_weights_d, float *hidden_units_d) {
dim3 DimGrid((hid-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_hidden_error_kernel_function<<<DimGrid, DimBlock>>>(hidden_delta_d, hid, output_delta_d, out, hidden_weights_d, hidden_units_d);
}
void gpu_weight_adjust(float *delta, int out, float *hidden_units, int hid, float *hidden_weights) {
dim3 DimGrid((hid-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_weight_adjust_function<<<DimGrid, DimBlock>>>(delta, out, hidden_units, hid, hidden_weights);
} | .file "tmpxft_000de5e1_00000000-6_gpukernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii
.type _Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii, @function
_Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24kernel_bpnn_layerforwardPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii, .-_Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii
.globl _Z24kernel_bpnn_layerforwardPfS_S_ii
.type _Z24kernel_bpnn_layerforwardPfS_S_ii, @function
_Z24kernel_bpnn_layerforwardPfS_S_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z24kernel_bpnn_layerforwardPfS_S_ii, .-_Z24kernel_bpnn_layerforwardPfS_S_ii
.globl _Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_
.type _Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_, @function
_Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_:
.LFB2087:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32gpu_output_error_kernel_functionPfS_S_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_, .-_Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_
.globl _Z32gpu_output_error_kernel_functionPfS_S_iS_
.type _Z32gpu_output_error_kernel_functionPfS_S_iS_, @function
_Z32gpu_output_error_kernel_functionPfS_S_iS_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z32gpu_output_error_kernel_functionPfS_S_iS_, .-_Z32gpu_output_error_kernel_functionPfS_S_iS_
.globl _Z23gpu_output_error_kernelPfS_S_iS_
.type _Z23gpu_output_error_kernelPfS_S_iS_, @function
_Z23gpu_output_error_kernelPfS_S_iS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movq %r8, %r14
leal 510(%rcx), %eax
movl %ecx, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq %r14, %r8
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_
jmp .L19
.cfi_endproc
.LFE2058:
.size _Z23gpu_output_error_kernelPfS_S_iS_, .-_Z23gpu_output_error_kernelPfS_S_iS_
.globl _Z34__device_stub__Z13kernel_squashPfiPfi
.type _Z34__device_stub__Z13kernel_squashPfiPfi, @function
_Z34__device_stub__Z13kernel_squashPfiPfi:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13kernel_squashPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z34__device_stub__Z13kernel_squashPfiPfi, .-_Z34__device_stub__Z13kernel_squashPfiPfi
.globl _Z13kernel_squashPfi
.type _Z13kernel_squashPfi, @function
_Z13kernel_squashPfi:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13kernel_squashPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z13kernel_squashPfi, .-_Z13kernel_squashPfi
.globl _Z21gpu_bpnn_layerforwardPfS_S_ii
.type _Z21gpu_bpnn_layerforwardPfS_S_ii, @function
_Z21gpu_bpnn_layerforwardPfS_S_ii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %r14
movl %ecx, %ebx
movl %r8d, %ebp
leal 510(%rcx), %eax
movl %ecx, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, (%rsp)
movl $1, 4(%rsp)
movl $512, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L32:
call cudaDeviceSynchronize@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L31:
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %ebp, %r8d
movl %ebx, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii
jmp .L32
.L36:
movl %ebp, %esi
movq %r12, %rdi
call _Z34__device_stub__Z13kernel_squashPfiPfi
jmp .L31
.cfi_endproc
.LFE2057:
.size _Z21gpu_bpnn_layerforwardPfS_S_ii, .-_Z21gpu_bpnn_layerforwardPfS_S_ii
.globl _Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_
.type _Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_, @function
_Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_, .-_Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_
.globl _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.type _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, @function
_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, .-_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.globl _Z23gpu_hidden_error_kernelPfiS_iS_S_
.type _Z23gpu_hidden_error_kernelPfiS_iS_S_, @function
_Z23gpu_hidden_error_kernelPfiS_iS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
leal 510(%rsi), %eax
movl %esi, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L45:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_
jmp .L45
.cfi_endproc
.LFE2059:
.size _Z23gpu_hidden_error_kernelPfiS_iS_S_, .-_Z23gpu_hidden_error_kernelPfiS_iS_S_
.globl _Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_
.type _Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_, @function
_Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_:
.LFB2093:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26gpu_weight_adjust_functionPfiS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_, .-_Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_
.globl _Z26gpu_weight_adjust_functionPfiS_iS_
.type _Z26gpu_weight_adjust_functionPfiS_iS_, @function
_Z26gpu_weight_adjust_functionPfiS_iS_:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z26gpu_weight_adjust_functionPfiS_iS_, .-_Z26gpu_weight_adjust_functionPfiS_iS_
.globl _Z17gpu_weight_adjustPfiS_iS_
.type _Z17gpu_weight_adjustPfiS_iS_, @function
_Z17gpu_weight_adjustPfiS_iS_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %r12d
movq %rdx, %r13
movl %ecx, %ebx
movq %r8, %r14
leal 510(%rcx), %eax
movl %ecx, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L57:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
movq %r14, %r8
movl %ebx, %ecx
movq %r13, %rdx
movl %r12d, %esi
movq %rbp, %rdi
call _Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_
jmp .L57
.cfi_endproc
.LFE2060:
.size _Z17gpu_weight_adjustPfiS_iS_, .-_Z17gpu_weight_adjustPfiS_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26gpu_weight_adjust_functionPfiS_iS_"
.align 8
.LC1:
.string "_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z13kernel_squashPfi"
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z32gpu_output_error_kernel_functionPfS_S_iS_"
.align 8
.LC4:
.string "_Z24kernel_bpnn_layerforwardPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26gpu_weight_adjust_functionPfiS_iS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_squashPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z32gpu_output_error_kernel_functionPfS_S_iS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z24kernel_bpnn_layerforwardPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <stdio.h>
#define BLOCK_SIZE 512
#define HIDDEN_SIZE 17
#define ETA 0.3
#define MOMENT 0.3
/*
__device__ float squash(float x ) {
//float m;
//x = -x;
//m = 1 + x + x*x/2 + x*x*x/6 + x*x*x*x/24 + x*x*x*x*x/120;
//return(1.0 / (1.0 + m));
return (1.0 / (1.0 + exp(-x)));
}
*/
/*
__global__ void kernel_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
int threadIdx_x = threadIdx.x;
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < inp) {
float val = 0.0;
for(int i=1; i < hidden ; i++) {
val = input_units[element] * input_weights[(element * hidden) + i] ;
// printf("%d, %d, %f, %f, %f\n", element, i, input_weights[(element * hidden) + i] , input_units[element], val);
atomicAdd(&hidden_units[i], val);
}
}
// nt i=1; i < hidden ; i++) {
//(f(element==0) {
// hidden_units[0] = 0.0;
// }
}
*/
__global__ void kernel_bpnn_layerforward(float *input_units_master, float *hidden_units_master, float *input_weights_master, int inp, int hidden) {
int tx = threadIdx.x;
int element = threadIdx.x + blockDim.x * blockIdx.x;
// Store Input Units, Input Weights in shared memory
__shared__ float input_units[BLOCK_SIZE];
__shared__ float input_weights[18*BLOCK_SIZE];
__shared__ float hidden_units[17];
if(element < inp) {
// Read Data from Global memory to Shared memory
input_units[tx] = input_units_master[element];
// printf("PROBLEM------ %d, %d, %f\n", element, tx, input_units[tx]);
int i;
for(i=0; i<hidden; i++) {
input_weights[(tx*hidden)+i] = input_weights_master[(element * hidden) + i];
hidden_units[i] = 0.0;
hidden_units_master[i] = 0.0;
}
// Sync All Threads
__syncthreads();
// Calculate Intermediate results in Shared memory
for(i=1; i<hidden; i++) {
float result = input_units[tx] * input_weights[(tx*hidden)+i];
//hidden_units[i] += result;
atomicAdd(&(hidden_units[i]), result);
//printf("Intermediate: %d, %d, %f * %f, %f \n", element, i,input_units[tx] , input_weights[(tx*hidden)+i], result);
}
__syncthreads();
// Store final results in Main memory
if(tx ==0) {
for(i=1; i<hidden; i++) {
atomicAdd(&(hidden_units_master[i]), hidden_units[i]);
//hidden_units_master[tx] = hidden_units[tx];
// printf("SUM: %d, %d, %f, %f \n", element, i, hidden_units[i], hidden_units_master[i]);
if(element == 0) {
hidden_units_master[0] = 0.0;
}
}
}
}
}
__global__ void gpu_output_error_kernel_function(float *delta, float *t, float *o, int count, float *err) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element != 0 && element < count) {
delta[element] = o[element] * ( 1.0 - o[element]) * (t[element] - o[element]);
// printf("Output err: %d, %f, %f = %f \n", element, o[element], t[element], delta[element]);
}
}
__global__ void kernel_squash(float *hidden, int count) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element >0 && element < count) {
float orig = hidden[element];
hidden[element] = (1.0 / (1.0 + exp(- orig)));
// printf("Element: %d, Orig: %f, ,squash: %f \n", element, orig, hidden[element]);
}
}
__global__ void gpu_hidden_error_kernel_function (float *hidden_delta_d, int hid, float *output_delta_d, int out, float *hidden_weights_d, float *hidden_units_d) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < hid) {
// for(int i =1; i < out; i++) {
float h = hidden_units_d[element] ;
float sum = output_delta_d[1] * hidden_weights_d[element];
//printf("%d, %f * %f = %f \n", element, output_delta_d[1], hidden_weights_d[element], sum);
hidden_delta_d[element] = h * (1.0 -h) * sum;
//printf("%d => %f * (1.0 - %f) * %f = %f\n", element, h,h, sum, hidden_delta_d[element]);
// }
}
}
__global__ void gpu_weight_adjust_function(float *delta, int out, float *hidden_units, int hid, float *hidden_weights) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < hid) {
float new_dw = ((ETA * delta[1] * hidden_units[element]) + (MOMENT * 0));
hidden_weights[element] += new_dw;
//printf("Element: %d, new val = %f, %f \n", element, new_dw, hidden_weights[element]);
}
}
/// Algorithm using Naive method
/*
void gpu_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
// Place holder to complete input sanity check
//Allocate Blocks
dim3 DimGrid((inp-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE+1, 1, 1);
// Invoke CUDA kernel -----------------------------------------------------
kernel_bpnn_layerforward<<<DimGrid, DimBlock>>>(input_units, hidden_units, input_weights, inp, hidden);
cudaDeviceSynchronize();
dim3 DimGrid2((hidden-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock2(BLOCK_SIZE+1, 1, 1);
// Invoke Squashing kernel
kernel_squash<<<DimGrid2, DimBlock2>>>(hidden_units, hidden);
}
*/
// Algorithm using shared memory
void gpu_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
dim3 DimGrid((inp-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
kernel_bpnn_layerforward<<<DimGrid, DimBlock>>>(input_units, hidden_units, input_weights, inp, hidden);
cudaDeviceSynchronize();
dim3 DimGrid2(1, 1, 1);
dim3 DimBlock2(hidden, 1, 1);
// Invoke Squashing kernel
kernel_squash<<<DimGrid2, DimBlock2>>>(hidden_units, hidden);
}
void gpu_output_error_kernel(float *delta, float *target, float *output, int count, float *err) {
dim3 DimGrid((count-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_output_error_kernel_function<<<DimGrid, DimBlock>>>(delta, target, output, count, err);
}
void gpu_hidden_error_kernel(float *hidden_delta_d , int hid, float *output_delta_d, int out, float *hidden_weights_d, float *hidden_units_d) {
dim3 DimGrid((hid-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_hidden_error_kernel_function<<<DimGrid, DimBlock>>>(hidden_delta_d, hid, output_delta_d, out, hidden_weights_d, hidden_units_d);
}
void gpu_weight_adjust(float *delta, int out, float *hidden_units, int hid, float *hidden_weights) {
dim3 DimGrid((hid-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_weight_adjust_function<<<DimGrid, DimBlock>>>(delta, out, hidden_units, hid, hidden_weights);
} | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 512
#define HIDDEN_SIZE 17
#define ETA 0.3
#define MOMENT 0.3
/*
__device__ float squash(float x ) {
//float m;
//x = -x;
//m = 1 + x + x*x/2 + x*x*x/6 + x*x*x*x/24 + x*x*x*x*x/120;
//return(1.0 / (1.0 + m));
return (1.0 / (1.0 + exp(-x)));
}
*/
/*
__global__ void kernel_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
int threadIdx_x = threadIdx.x;
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < inp) {
float val = 0.0;
for(int i=1; i < hidden ; i++) {
val = input_units[element] * input_weights[(element * hidden) + i] ;
// printf("%d, %d, %f, %f, %f\n", element, i, input_weights[(element * hidden) + i] , input_units[element], val);
atomicAdd(&hidden_units[i], val);
}
}
// nt i=1; i < hidden ; i++) {
//(f(element==0) {
// hidden_units[0] = 0.0;
// }
}
*/
__global__ void kernel_bpnn_layerforward(float *input_units_master, float *hidden_units_master, float *input_weights_master, int inp, int hidden) {
int tx = threadIdx.x;
int element = threadIdx.x + blockDim.x * blockIdx.x;
// Store Input Units, Input Weights in shared memory
__shared__ float input_units[BLOCK_SIZE];
__shared__ float input_weights[18*BLOCK_SIZE];
__shared__ float hidden_units[17];
if(element < inp) {
// Read Data from Global memory to Shared memory
input_units[tx] = input_units_master[element];
// printf("PROBLEM------ %d, %d, %f\n", element, tx, input_units[tx]);
int i;
for(i=0; i<hidden; i++) {
input_weights[(tx*hidden)+i] = input_weights_master[(element * hidden) + i];
hidden_units[i] = 0.0;
hidden_units_master[i] = 0.0;
}
// Sync All Threads
__syncthreads();
// Calculate Intermediate results in Shared memory
for(i=1; i<hidden; i++) {
float result = input_units[tx] * input_weights[(tx*hidden)+i];
//hidden_units[i] += result;
atomicAdd(&(hidden_units[i]), result);
//printf("Intermediate: %d, %d, %f * %f, %f \n", element, i,input_units[tx] , input_weights[(tx*hidden)+i], result);
}
__syncthreads();
// Store final results in Main memory
if(tx ==0) {
for(i=1; i<hidden; i++) {
atomicAdd(&(hidden_units_master[i]), hidden_units[i]);
//hidden_units_master[tx] = hidden_units[tx];
// printf("SUM: %d, %d, %f, %f \n", element, i, hidden_units[i], hidden_units_master[i]);
if(element == 0) {
hidden_units_master[0] = 0.0;
}
}
}
}
}
__global__ void gpu_output_error_kernel_function(float *delta, float *t, float *o, int count, float *err) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element != 0 && element < count) {
delta[element] = o[element] * ( 1.0 - o[element]) * (t[element] - o[element]);
// printf("Output err: %d, %f, %f = %f \n", element, o[element], t[element], delta[element]);
}
}
__global__ void kernel_squash(float *hidden, int count) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element >0 && element < count) {
float orig = hidden[element];
hidden[element] = (1.0 / (1.0 + exp(- orig)));
// printf("Element: %d, Orig: %f, ,squash: %f \n", element, orig, hidden[element]);
}
}
__global__ void gpu_hidden_error_kernel_function (float *hidden_delta_d, int hid, float *output_delta_d, int out, float *hidden_weights_d, float *hidden_units_d) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < hid) {
// for(int i =1; i < out; i++) {
float h = hidden_units_d[element] ;
float sum = output_delta_d[1] * hidden_weights_d[element];
//printf("%d, %f * %f = %f \n", element, output_delta_d[1], hidden_weights_d[element], sum);
hidden_delta_d[element] = h * (1.0 -h) * sum;
//printf("%d => %f * (1.0 - %f) * %f = %f\n", element, h,h, sum, hidden_delta_d[element]);
// }
}
}
__global__ void gpu_weight_adjust_function(float *delta, int out, float *hidden_units, int hid, float *hidden_weights) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < hid) {
float new_dw = ((ETA * delta[1] * hidden_units[element]) + (MOMENT * 0));
hidden_weights[element] += new_dw;
//printf("Element: %d, new val = %f, %f \n", element, new_dw, hidden_weights[element]);
}
}
/// Algorithm using Naive method
/*
void gpu_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
// Place holder to complete input sanity check
//Allocate Blocks
dim3 DimGrid((inp-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE+1, 1, 1);
// Invoke CUDA kernel -----------------------------------------------------
kernel_bpnn_layerforward<<<DimGrid, DimBlock>>>(input_units, hidden_units, input_weights, inp, hidden);
cudaDeviceSynchronize();
dim3 DimGrid2((hidden-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock2(BLOCK_SIZE+1, 1, 1);
// Invoke Squashing kernel
kernel_squash<<<DimGrid2, DimBlock2>>>(hidden_units, hidden);
}
*/
// Algorithm using shared memory
void gpu_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
dim3 DimGrid((inp-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
kernel_bpnn_layerforward<<<DimGrid, DimBlock>>>(input_units, hidden_units, input_weights, inp, hidden);
hipDeviceSynchronize();
dim3 DimGrid2(1, 1, 1);
dim3 DimBlock2(hidden, 1, 1);
// Invoke Squashing kernel
kernel_squash<<<DimGrid2, DimBlock2>>>(hidden_units, hidden);
}
void gpu_output_error_kernel(float *delta, float *target, float *output, int count, float *err) {
dim3 DimGrid((count-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_output_error_kernel_function<<<DimGrid, DimBlock>>>(delta, target, output, count, err);
}
void gpu_hidden_error_kernel(float *hidden_delta_d , int hid, float *output_delta_d, int out, float *hidden_weights_d, float *hidden_units_d) {
dim3 DimGrid((hid-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_hidden_error_kernel_function<<<DimGrid, DimBlock>>>(hidden_delta_d, hid, output_delta_d, out, hidden_weights_d, hidden_units_d);
}
void gpu_weight_adjust(float *delta, int out, float *hidden_units, int hid, float *hidden_weights) {
dim3 DimGrid((hid-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_weight_adjust_function<<<DimGrid, DimBlock>>>(delta, out, hidden_units, hid, hidden_weights);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 512
#define HIDDEN_SIZE 17
#define ETA 0.3
#define MOMENT 0.3
/*
__device__ float squash(float x ) {
//float m;
//x = -x;
//m = 1 + x + x*x/2 + x*x*x/6 + x*x*x*x/24 + x*x*x*x*x/120;
//return(1.0 / (1.0 + m));
return (1.0 / (1.0 + exp(-x)));
}
*/
/*
__global__ void kernel_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
int threadIdx_x = threadIdx.x;
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < inp) {
float val = 0.0;
for(int i=1; i < hidden ; i++) {
val = input_units[element] * input_weights[(element * hidden) + i] ;
// printf("%d, %d, %f, %f, %f\n", element, i, input_weights[(element * hidden) + i] , input_units[element], val);
atomicAdd(&hidden_units[i], val);
}
}
// nt i=1; i < hidden ; i++) {
//(f(element==0) {
// hidden_units[0] = 0.0;
// }
}
*/
__global__ void kernel_bpnn_layerforward(float *input_units_master, float *hidden_units_master, float *input_weights_master, int inp, int hidden) {
int tx = threadIdx.x;
int element = threadIdx.x + blockDim.x * blockIdx.x;
// Store Input Units, Input Weights in shared memory
__shared__ float input_units[BLOCK_SIZE];
__shared__ float input_weights[18*BLOCK_SIZE];
__shared__ float hidden_units[17];
if(element < inp) {
// Read Data from Global memory to Shared memory
input_units[tx] = input_units_master[element];
// printf("PROBLEM------ %d, %d, %f\n", element, tx, input_units[tx]);
int i;
for(i=0; i<hidden; i++) {
input_weights[(tx*hidden)+i] = input_weights_master[(element * hidden) + i];
hidden_units[i] = 0.0;
hidden_units_master[i] = 0.0;
}
// Sync All Threads
__syncthreads();
// Calculate Intermediate results in Shared memory
for(i=1; i<hidden; i++) {
float result = input_units[tx] * input_weights[(tx*hidden)+i];
//hidden_units[i] += result;
atomicAdd(&(hidden_units[i]), result);
//printf("Intermediate: %d, %d, %f * %f, %f \n", element, i,input_units[tx] , input_weights[(tx*hidden)+i], result);
}
__syncthreads();
// Store final results in Main memory
if(tx ==0) {
for(i=1; i<hidden; i++) {
atomicAdd(&(hidden_units_master[i]), hidden_units[i]);
//hidden_units_master[tx] = hidden_units[tx];
// printf("SUM: %d, %d, %f, %f \n", element, i, hidden_units[i], hidden_units_master[i]);
if(element == 0) {
hidden_units_master[0] = 0.0;
}
}
}
}
}
__global__ void gpu_output_error_kernel_function(float *delta, float *t, float *o, int count, float *err) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element != 0 && element < count) {
delta[element] = o[element] * ( 1.0 - o[element]) * (t[element] - o[element]);
// printf("Output err: %d, %f, %f = %f \n", element, o[element], t[element], delta[element]);
}
}
__global__ void kernel_squash(float *hidden, int count) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element >0 && element < count) {
float orig = hidden[element];
hidden[element] = (1.0 / (1.0 + exp(- orig)));
// printf("Element: %d, Orig: %f, ,squash: %f \n", element, orig, hidden[element]);
}
}
__global__ void gpu_hidden_error_kernel_function (float *hidden_delta_d, int hid, float *output_delta_d, int out, float *hidden_weights_d, float *hidden_units_d) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < hid) {
// for(int i =1; i < out; i++) {
float h = hidden_units_d[element] ;
float sum = output_delta_d[1] * hidden_weights_d[element];
//printf("%d, %f * %f = %f \n", element, output_delta_d[1], hidden_weights_d[element], sum);
hidden_delta_d[element] = h * (1.0 -h) * sum;
//printf("%d => %f * (1.0 - %f) * %f = %f\n", element, h,h, sum, hidden_delta_d[element]);
// }
}
}
__global__ void gpu_weight_adjust_function(float *delta, int out, float *hidden_units, int hid, float *hidden_weights) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < hid) {
float new_dw = ((ETA * delta[1] * hidden_units[element]) + (MOMENT * 0));
hidden_weights[element] += new_dw;
//printf("Element: %d, new val = %f, %f \n", element, new_dw, hidden_weights[element]);
}
}
/// Algorithm using Naive method
/*
void gpu_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
// Place holder to complete input sanity check
//Allocate Blocks
dim3 DimGrid((inp-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE+1, 1, 1);
// Invoke CUDA kernel -----------------------------------------------------
kernel_bpnn_layerforward<<<DimGrid, DimBlock>>>(input_units, hidden_units, input_weights, inp, hidden);
cudaDeviceSynchronize();
dim3 DimGrid2((hidden-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock2(BLOCK_SIZE+1, 1, 1);
// Invoke Squashing kernel
kernel_squash<<<DimGrid2, DimBlock2>>>(hidden_units, hidden);
}
*/
// Algorithm using shared memory
void gpu_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
dim3 DimGrid((inp-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
kernel_bpnn_layerforward<<<DimGrid, DimBlock>>>(input_units, hidden_units, input_weights, inp, hidden);
hipDeviceSynchronize();
dim3 DimGrid2(1, 1, 1);
dim3 DimBlock2(hidden, 1, 1);
// Invoke Squashing kernel
kernel_squash<<<DimGrid2, DimBlock2>>>(hidden_units, hidden);
}
void gpu_output_error_kernel(float *delta, float *target, float *output, int count, float *err) {
dim3 DimGrid((count-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_output_error_kernel_function<<<DimGrid, DimBlock>>>(delta, target, output, count, err);
}
void gpu_hidden_error_kernel(float *hidden_delta_d , int hid, float *output_delta_d, int out, float *hidden_weights_d, float *hidden_units_d) {
dim3 DimGrid((hid-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_hidden_error_kernel_function<<<DimGrid, DimBlock>>>(hidden_delta_d, hid, output_delta_d, out, hidden_weights_d, hidden_units_d);
}
void gpu_weight_adjust(float *delta, int out, float *hidden_units, int hid, float *hidden_weights) {
dim3 DimGrid((hid-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_weight_adjust_function<<<DimGrid, DimBlock>>>(delta, out, hidden_units, hid, hidden_weights);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24kernel_bpnn_layerforwardPfS_S_ii
.globl _Z24kernel_bpnn_layerforwardPfS_S_ii
.p2align 8
.type _Z24kernel_bpnn_layerforwardPfS_S_ii,@function
_Z24kernel_bpnn_layerforwardPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_19
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x1c
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mul_lo_u32 v4, v0, s8
s_cmp_lt_i32 s8, 1
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v2 offset:36864
s_cbranch_scc1 .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v2, v1, s8
v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v6, 2, v4
s_mov_b32 s2, 0
s_mov_b32 s3, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mov_b64 s[0:1], s[6:7]
.p2align 6
.LBB0_3:
global_load_b32 v8, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_dual_mov_b32 v10, s2 :: v_dual_add_nc_u32 v9, s2, v6
s_add_i32 s3, s3, -1
s_add_i32 s2, s2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
global_store_b32 v7, v7, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s3, 0
ds_store_b32 v10, v7 offset:38912
s_waitcnt vmcnt(0)
ds_store_b32 v9, v8
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_cmp_lt_i32 s8, 2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_11
v_or_b32_e32 v2, 0x9000, v5
s_mov_b32 s0, 1
ds_load_b32 v2, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, s8
s_cbranch_scc0 .LBB0_11
.LBB0_7:
v_add_lshl_u32 v3, s0, v4, 2
s_mov_b32 s1, exec_lo
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v5, v2, v3
v_bfrev_b32_e32 v3, 1
.LBB0_8:
s_ctz_i32_b32 s2, s1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_readlane_b32 s3, v5, s2
s_lshl_b32 s2, 1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s1, s1, s2
s_cmp_lg_u32 s1, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, s3, v3
s_cbranch_scc1 .LBB0_8
v_mbcnt_lo_u32_b32 v5, exec_lo, 0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v5
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_6
s_lshl_b32 s2, s0, 2
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s2
ds_add_f32 v5, v3 offset:38912
s_branch .LBB0_6
.LBB0_11:
s_set_inst_prefetch_distance 0x2
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_cmp_gt_i32 s8, 1
s_mov_b32 s3, 0
s_cselect_b32 s0, -1, 0
s_mov_b32 s2, 1
s_and_b32 s0, vcc_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_19
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_mov_b32_e32 v2, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_14
.p2align 6
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, s8
s_cbranch_scc0 .LBB0_19
.LBB0_14:
s_mov_b32 s9, exec_lo
s_mov_b32 s1, exec_lo
v_mbcnt_lo_u32_b32 v0, s9, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_17
s_lshl_b64 s[4:5], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s4, s6, s4
s_addc_u32 s5, s7, s5
s_lshl_b32 s0, s2, 2
global_load_b32 v1, v2, s[4:5]
v_mov_b32_e32 v0, s0
s_bcnt1_i32_b32 s0, s9
s_mov_b32 s9, 0
v_cvt_f32_ubyte0_e32 v3, s0
ds_load_b32 v0, v0 offset:38912
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v3, v0, v3
.LBB0_16:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v0, v1, v3
global_atomic_cmpswap_b32 v0, v2, v[0:1], s[4:5] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s9, s0, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_16
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_13
global_store_b32 v2, v2, s[6:7]
s_branch .LBB0_13
.LBB0_19:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24kernel_bpnn_layerforwardPfS_S_ii
.amdhsa_group_segment_fixed_size 38980
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24kernel_bpnn_layerforwardPfS_S_ii, .Lfunc_end0-_Z24kernel_bpnn_layerforwardPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z32gpu_output_error_kernel_functionPfS_S_iS_
.globl _Z32gpu_output_error_kernel_functionPfS_S_iS_
.p2align 8
.type _Z32gpu_output_error_kernel_functionPfS_S_iS_,@function
_Z32gpu_output_error_kernel_functionPfS_S_iS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v6, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v7, v[2:3], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[2:3], v6
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], -v[2:3], 1.0
v_mul_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v6
v_mul_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32gpu_output_error_kernel_functionPfS_S_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z32gpu_output_error_kernel_functionPfS_S_iS_, .Lfunc_end1-_Z32gpu_output_error_kernel_functionPfS_S_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13kernel_squashPfi
.globl _Z13kernel_squashPfi
.p2align 8
.type _Z13kernel_squashPfi,@function
_Z13kernel_squashPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0xbfb8aa3b, v2
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v2
v_fma_f32 v4, v2, 0xbfb8aa3b, -v3
v_rndne_f32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v4, v2, 0xb2a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], 1.0
v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[8:9], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernel_squashPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13kernel_squashPfi, .Lfunc_end2-_Z13kernel_squashPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.globl _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.p2align 8
.type _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_,@function
_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB3_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_load_b32 s2, s[2:3], 0x4
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[2:3], v4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], -v[2:3], 1.0
v_mul_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v6
v_mul_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, .Lfunc_end3-_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z26gpu_weight_adjust_functionPfiS_iS_
.globl _Z26gpu_weight_adjust_functionPfiS_iS_
.p2align 8
.type _Z26gpu_weight_adjust_functionPfiS_iS_,@function
_Z26gpu_weight_adjust_functionPfiS_iS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB4_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[2:3], off
s_load_b32 s0, s[0:1], 0x4
s_mov_b32 s1, 0x3fd33333
global_load_b32 v6, v[0:1], off
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[2:3], s0
s_mov_b32 s0, 0x33333333
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_f64 v[2:3], v[2:3], s[0:1]
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], v[4:5], 0
v_cvt_f32_f64_e32 v2, v[2:3]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, v6, v2
global_store_b32 v[0:1], v2, off
.LBB4_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26gpu_weight_adjust_functionPfiS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z26gpu_weight_adjust_functionPfiS_iS_, .Lfunc_end4-_Z26gpu_weight_adjust_functionPfiS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 38980
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24kernel_bpnn_layerforwardPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24kernel_bpnn_layerforwardPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32gpu_output_error_kernel_functionPfS_S_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32gpu_output_error_kernel_functionPfS_S_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernel_squashPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernel_squashPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26gpu_weight_adjust_functionPfiS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26gpu_weight_adjust_functionPfiS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 512
#define HIDDEN_SIZE 17
#define ETA 0.3
#define MOMENT 0.3
/*
__device__ float squash(float x ) {
//float m;
//x = -x;
//m = 1 + x + x*x/2 + x*x*x/6 + x*x*x*x/24 + x*x*x*x*x/120;
//return(1.0 / (1.0 + m));
return (1.0 / (1.0 + exp(-x)));
}
*/
/*
__global__ void kernel_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
int threadIdx_x = threadIdx.x;
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < inp) {
float val = 0.0;
for(int i=1; i < hidden ; i++) {
val = input_units[element] * input_weights[(element * hidden) + i] ;
// printf("%d, %d, %f, %f, %f\n", element, i, input_weights[(element * hidden) + i] , input_units[element], val);
atomicAdd(&hidden_units[i], val);
}
}
// nt i=1; i < hidden ; i++) {
//(f(element==0) {
// hidden_units[0] = 0.0;
// }
}
*/
__global__ void kernel_bpnn_layerforward(float *input_units_master, float *hidden_units_master, float *input_weights_master, int inp, int hidden) {
int tx = threadIdx.x;
int element = threadIdx.x + blockDim.x * blockIdx.x;
// Store Input Units, Input Weights in shared memory
__shared__ float input_units[BLOCK_SIZE];
__shared__ float input_weights[18*BLOCK_SIZE];
__shared__ float hidden_units[17];
if(element < inp) {
// Read Data from Global memory to Shared memory
input_units[tx] = input_units_master[element];
// printf("PROBLEM------ %d, %d, %f\n", element, tx, input_units[tx]);
int i;
for(i=0; i<hidden; i++) {
input_weights[(tx*hidden)+i] = input_weights_master[(element * hidden) + i];
hidden_units[i] = 0.0;
hidden_units_master[i] = 0.0;
}
// Sync All Threads
__syncthreads();
// Calculate Intermediate results in Shared memory
for(i=1; i<hidden; i++) {
float result = input_units[tx] * input_weights[(tx*hidden)+i];
//hidden_units[i] += result;
atomicAdd(&(hidden_units[i]), result);
//printf("Intermediate: %d, %d, %f * %f, %f \n", element, i,input_units[tx] , input_weights[(tx*hidden)+i], result);
}
__syncthreads();
// Store final results in Main memory
if(tx ==0) {
for(i=1; i<hidden; i++) {
atomicAdd(&(hidden_units_master[i]), hidden_units[i]);
//hidden_units_master[tx] = hidden_units[tx];
// printf("SUM: %d, %d, %f, %f \n", element, i, hidden_units[i], hidden_units_master[i]);
if(element == 0) {
hidden_units_master[0] = 0.0;
}
}
}
}
}
__global__ void gpu_output_error_kernel_function(float *delta, float *t, float *o, int count, float *err) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element != 0 && element < count) {
delta[element] = o[element] * ( 1.0 - o[element]) * (t[element] - o[element]);
// printf("Output err: %d, %f, %f = %f \n", element, o[element], t[element], delta[element]);
}
}
__global__ void kernel_squash(float *hidden, int count) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element >0 && element < count) {
float orig = hidden[element];
hidden[element] = (1.0 / (1.0 + exp(- orig)));
// printf("Element: %d, Orig: %f, ,squash: %f \n", element, orig, hidden[element]);
}
}
__global__ void gpu_hidden_error_kernel_function (float *hidden_delta_d, int hid, float *output_delta_d, int out, float *hidden_weights_d, float *hidden_units_d) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < hid) {
// for(int i =1; i < out; i++) {
float h = hidden_units_d[element] ;
float sum = output_delta_d[1] * hidden_weights_d[element];
//printf("%d, %f * %f = %f \n", element, output_delta_d[1], hidden_weights_d[element], sum);
hidden_delta_d[element] = h * (1.0 -h) * sum;
//printf("%d => %f * (1.0 - %f) * %f = %f\n", element, h,h, sum, hidden_delta_d[element]);
// }
}
}
__global__ void gpu_weight_adjust_function(float *delta, int out, float *hidden_units, int hid, float *hidden_weights) {
int element = threadIdx.x + blockDim.x * blockIdx.x;
if(element < hid) {
float new_dw = ((ETA * delta[1] * hidden_units[element]) + (MOMENT * 0));
hidden_weights[element] += new_dw;
//printf("Element: %d, new val = %f, %f \n", element, new_dw, hidden_weights[element]);
}
}
/// Algorithm using Naive method
/*
void gpu_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
// Place holder to complete input sanity check
//Allocate Blocks
dim3 DimGrid((inp-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE+1, 1, 1);
// Invoke CUDA kernel -----------------------------------------------------
kernel_bpnn_layerforward<<<DimGrid, DimBlock>>>(input_units, hidden_units, input_weights, inp, hidden);
cudaDeviceSynchronize();
dim3 DimGrid2((hidden-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock2(BLOCK_SIZE+1, 1, 1);
// Invoke Squashing kernel
kernel_squash<<<DimGrid2, DimBlock2>>>(hidden_units, hidden);
}
*/
// Algorithm using shared memory
void gpu_bpnn_layerforward(float *input_units, float *hidden_units, float *input_weights, int inp, int hidden) {
dim3 DimGrid((inp-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
kernel_bpnn_layerforward<<<DimGrid, DimBlock>>>(input_units, hidden_units, input_weights, inp, hidden);
hipDeviceSynchronize();
dim3 DimGrid2(1, 1, 1);
dim3 DimBlock2(hidden, 1, 1);
// Invoke Squashing kernel
kernel_squash<<<DimGrid2, DimBlock2>>>(hidden_units, hidden);
}
void gpu_output_error_kernel(float *delta, float *target, float *output, int count, float *err) {
dim3 DimGrid((count-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_output_error_kernel_function<<<DimGrid, DimBlock>>>(delta, target, output, count, err);
}
void gpu_hidden_error_kernel(float *hidden_delta_d , int hid, float *output_delta_d, int out, float *hidden_weights_d, float *hidden_units_d) {
dim3 DimGrid((hid-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_hidden_error_kernel_function<<<DimGrid, DimBlock>>>(hidden_delta_d, hid, output_delta_d, out, hidden_weights_d, hidden_units_d);
}
void gpu_weight_adjust(float *delta, int out, float *hidden_units, int hid, float *hidden_weights) {
dim3 DimGrid((hid-1)/BLOCK_SIZE +1, 1, 1);
dim3 DimBlock(BLOCK_SIZE, 1, 1);
gpu_weight_adjust_function<<<DimGrid, DimBlock>>>(delta, out, hidden_units, hid, hidden_weights);
} | .text
.file "gpukernel.hip"
.globl _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii # -- Begin function _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii
.p2align 4, 0x90
.type _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii,@function
_Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii: # @_Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24kernel_bpnn_layerforwardPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii, .Lfunc_end0-_Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_ # -- Begin function _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_
.p2align 4, 0x90
.type _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_,@function
_Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_: # @_Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32gpu_output_error_kernel_functionPfS_S_iS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_, .Lfunc_end1-_Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__kernel_squashPfi # -- Begin function _Z28__device_stub__kernel_squashPfi
.p2align 4, 0x90
.type _Z28__device_stub__kernel_squashPfi,@function
_Z28__device_stub__kernel_squashPfi: # @_Z28__device_stub__kernel_squashPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13kernel_squashPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z28__device_stub__kernel_squashPfi, .Lfunc_end2-_Z28__device_stub__kernel_squashPfi
.cfi_endproc
# -- End function
.globl _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_ # -- Begin function _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_
.p2align 4, 0x90
.type _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_,@function
_Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_: # @_Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_, .Lfunc_end3-_Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_
.cfi_endproc
# -- End function
.globl _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_ # -- Begin function _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_
.p2align 4, 0x90
.type _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_,@function
_Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_: # @_Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26gpu_weight_adjust_functionPfiS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_, .Lfunc_end4-_Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_
.cfi_endproc
# -- End function
.globl _Z21gpu_bpnn_layerforwardPfS_S_ii # -- Begin function _Z21gpu_bpnn_layerforwardPfS_S_ii
.p2align 4, 0x90
.type _Z21gpu_bpnn_layerforwardPfS_S_ii,@function
_Z21gpu_bpnn_layerforwardPfS_S_ii: # @_Z21gpu_bpnn_layerforwardPfS_S_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebx
movl %ecx, %r12d
movq %rdx, %r13
movq %rsi, %r14
movq %rdi, %rbp
movabsq $4294967296, %r15 # imm = 0x100000000
leal -1(%r12), %eax
leal 510(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
incl %edi
orq %r15, %rdi
leaq 512(%r15), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq %rbp, 56(%rsp)
movq %r14, 16(%rsp)
movq %r13, 8(%rsp)
movl %r12d, 68(%rsp)
movl %ebx, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 68(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
movq %rsp, %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24kernel_bpnn_layerforwardPfS_S_ii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
callq hipDeviceSynchronize
movl %ebx, %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq %r14, 56(%rsp)
movl %ebx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_squashPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z21gpu_bpnn_layerforwardPfS_S_ii, .Lfunc_end5-_Z21gpu_bpnn_layerforwardPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z23gpu_output_error_kernelPfS_S_iS_ # -- Begin function _Z23gpu_output_error_kernelPfS_S_iS_
.p2align 4, 0x90
.type _Z23gpu_output_error_kernelPfS_S_iS_,@function
_Z23gpu_output_error_kernelPfS_S_iS_: # @_Z23gpu_output_error_kernelPfS_S_iS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
movl %ecx, %r14d
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
leal -1(%r14), %eax
leal 510(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq %r13, 88(%rsp)
movq %r12, 80(%rsp)
movq %r15, 72(%rsp)
movl %r14d, 12(%rsp)
movq %rbx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32gpu_output_error_kernel_functionPfS_S_iS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z23gpu_output_error_kernelPfS_S_iS_, .Lfunc_end6-_Z23gpu_output_error_kernelPfS_S_iS_
.cfi_endproc
# -- End function
.globl _Z23gpu_hidden_error_kernelPfiS_iS_S_ # -- Begin function _Z23gpu_hidden_error_kernelPfiS_iS_S_
.p2align 4, 0x90
.type _Z23gpu_hidden_error_kernelPfiS_iS_S_,@function
_Z23gpu_hidden_error_kernelPfiS_iS_S_: # @_Z23gpu_hidden_error_kernelPfiS_iS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movq %rdx, %r15
movl %esi, %r12d
movq %rdi, %r13
leal -1(%r12), %eax
leal 510(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq %r13, 88(%rsp)
movl %r12d, 12(%rsp)
movq %r15, 80(%rsp)
movl %ebp, 8(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z23gpu_hidden_error_kernelPfiS_iS_S_, .Lfunc_end7-_Z23gpu_hidden_error_kernelPfiS_iS_S_
.cfi_endproc
# -- End function
.globl _Z17gpu_weight_adjustPfiS_iS_ # -- Begin function _Z17gpu_weight_adjustPfiS_iS_
.p2align 4, 0x90
.type _Z17gpu_weight_adjustPfiS_iS_,@function
_Z17gpu_weight_adjustPfiS_iS_: # @_Z17gpu_weight_adjustPfiS_iS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movl %ecx, %r14d
movq %rdx, %r15
movl %esi, %ebp
movq %rdi, %r12
leal -1(%r14), %eax
leal 510(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_2
# %bb.1:
movq %r12, 72(%rsp)
movl %ebp, 4(%rsp)
movq %r15, 64(%rsp)
movl %r14d, (%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26gpu_weight_adjust_functionPfiS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_2:
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z17gpu_weight_adjustPfiS_iS_, .Lfunc_end8-_Z17gpu_weight_adjustPfiS_iS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24kernel_bpnn_layerforwardPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32gpu_output_error_kernel_functionPfS_S_iS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_squashPfi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26gpu_weight_adjust_functionPfiS_iS_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24kernel_bpnn_layerforwardPfS_S_ii,@object # @_Z24kernel_bpnn_layerforwardPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z24kernel_bpnn_layerforwardPfS_S_ii
.p2align 3, 0x0
_Z24kernel_bpnn_layerforwardPfS_S_ii:
.quad _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii
.size _Z24kernel_bpnn_layerforwardPfS_S_ii, 8
.type _Z32gpu_output_error_kernel_functionPfS_S_iS_,@object # @_Z32gpu_output_error_kernel_functionPfS_S_iS_
.globl _Z32gpu_output_error_kernel_functionPfS_S_iS_
.p2align 3, 0x0
_Z32gpu_output_error_kernel_functionPfS_S_iS_:
.quad _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_
.size _Z32gpu_output_error_kernel_functionPfS_S_iS_, 8
.type _Z13kernel_squashPfi,@object # @_Z13kernel_squashPfi
.globl _Z13kernel_squashPfi
.p2align 3, 0x0
_Z13kernel_squashPfi:
.quad _Z28__device_stub__kernel_squashPfi
.size _Z13kernel_squashPfi, 8
.type _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_,@object # @_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.globl _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.p2align 3, 0x0
_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_:
.quad _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_
.size _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, 8
.type _Z26gpu_weight_adjust_functionPfiS_iS_,@object # @_Z26gpu_weight_adjust_functionPfiS_iS_
.globl _Z26gpu_weight_adjust_functionPfiS_iS_
.p2align 3, 0x0
_Z26gpu_weight_adjust_functionPfiS_iS_:
.quad _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_
.size _Z26gpu_weight_adjust_functionPfiS_iS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24kernel_bpnn_layerforwardPfS_S_ii"
.size .L__unnamed_1, 37
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z32gpu_output_error_kernel_functionPfS_S_iS_"
.size .L__unnamed_2, 46
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13kernel_squashPfi"
.size .L__unnamed_3, 21
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_"
.size .L__unnamed_4, 47
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z26gpu_weight_adjust_functionPfiS_iS_"
.size .L__unnamed_5, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii
.addrsig_sym _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_
.addrsig_sym _Z28__device_stub__kernel_squashPfi
.addrsig_sym _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_
.addrsig_sym _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24kernel_bpnn_layerforwardPfS_S_ii
.addrsig_sym _Z32gpu_output_error_kernel_functionPfS_S_iS_
.addrsig_sym _Z13kernel_squashPfi
.addrsig_sym _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.addrsig_sym _Z26gpu_weight_adjust_functionPfiS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000de5e1_00000000-6_gpukernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii
.type _Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii, @function
_Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24kernel_bpnn_layerforwardPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii, .-_Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii
.globl _Z24kernel_bpnn_layerforwardPfS_S_ii
.type _Z24kernel_bpnn_layerforwardPfS_S_ii, @function
_Z24kernel_bpnn_layerforwardPfS_S_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z24kernel_bpnn_layerforwardPfS_S_ii, .-_Z24kernel_bpnn_layerforwardPfS_S_ii
.globl _Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_
.type _Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_, @function
_Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_:
.LFB2087:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32gpu_output_error_kernel_functionPfS_S_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_, .-_Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_
.globl _Z32gpu_output_error_kernel_functionPfS_S_iS_
.type _Z32gpu_output_error_kernel_functionPfS_S_iS_, @function
_Z32gpu_output_error_kernel_functionPfS_S_iS_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z32gpu_output_error_kernel_functionPfS_S_iS_, .-_Z32gpu_output_error_kernel_functionPfS_S_iS_
.globl _Z23gpu_output_error_kernelPfS_S_iS_
.type _Z23gpu_output_error_kernelPfS_S_iS_, @function
_Z23gpu_output_error_kernelPfS_S_iS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movq %r8, %r14
leal 510(%rcx), %eax
movl %ecx, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L19:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq %r14, %r8
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z59__device_stub__Z32gpu_output_error_kernel_functionPfS_S_iS_PfS_S_iS_
jmp .L19
.cfi_endproc
.LFE2058:
.size _Z23gpu_output_error_kernelPfS_S_iS_, .-_Z23gpu_output_error_kernelPfS_S_iS_
.globl _Z34__device_stub__Z13kernel_squashPfiPfi
.type _Z34__device_stub__Z13kernel_squashPfiPfi, @function
_Z34__device_stub__Z13kernel_squashPfiPfi:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13kernel_squashPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z34__device_stub__Z13kernel_squashPfiPfi, .-_Z34__device_stub__Z13kernel_squashPfiPfi
.globl _Z13kernel_squashPfi
.type _Z13kernel_squashPfi, @function
_Z13kernel_squashPfi:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13kernel_squashPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z13kernel_squashPfi, .-_Z13kernel_squashPfi
.globl _Z21gpu_bpnn_layerforwardPfS_S_ii
.type _Z21gpu_bpnn_layerforwardPfS_S_ii, @function
_Z21gpu_bpnn_layerforwardPfS_S_ii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %r14
movl %ecx, %ebx
movl %r8d, %ebp
leal 510(%rcx), %eax
movl %ecx, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, (%rsp)
movl $1, 4(%rsp)
movl $512, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L32:
call cudaDeviceSynchronize@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L31:
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %ebp, %r8d
movl %ebx, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z50__device_stub__Z24kernel_bpnn_layerforwardPfS_S_iiPfS_S_ii
jmp .L32
.L36:
movl %ebp, %esi
movq %r12, %rdi
call _Z34__device_stub__Z13kernel_squashPfiPfi
jmp .L31
.cfi_endproc
.LFE2057:
.size _Z21gpu_bpnn_layerforwardPfS_S_ii, .-_Z21gpu_bpnn_layerforwardPfS_S_ii
.globl _Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_
.type _Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_, @function
_Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_:
.LFB2091:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_, .-_Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_
.globl _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.type _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, @function
_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, .-_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.globl _Z23gpu_hidden_error_kernelPfiS_iS_S_
.type _Z23gpu_hidden_error_kernelPfiS_iS_S_, @function
_Z23gpu_hidden_error_kernelPfiS_iS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
leal 510(%rsi), %eax
movl %esi, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L45:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movq %r12, %rdx
movl %ebx, %esi
movq %rbp, %rdi
call _Z60__device_stub__Z32gpu_hidden_error_kernel_functionPfiS_iS_S_PfiS_iS_S_
jmp .L45
.cfi_endproc
.LFE2059:
.size _Z23gpu_hidden_error_kernelPfiS_iS_S_, .-_Z23gpu_hidden_error_kernelPfiS_iS_S_
.globl _Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_
.type _Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_, @function
_Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_:
.LFB2093:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26gpu_weight_adjust_functionPfiS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_, .-_Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_
.globl _Z26gpu_weight_adjust_functionPfiS_iS_
.type _Z26gpu_weight_adjust_functionPfiS_iS_, @function
_Z26gpu_weight_adjust_functionPfiS_iS_:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z26gpu_weight_adjust_functionPfiS_iS_, .-_Z26gpu_weight_adjust_functionPfiS_iS_
.globl _Z17gpu_weight_adjustPfiS_iS_
.type _Z17gpu_weight_adjustPfiS_iS_, @function
_Z17gpu_weight_adjustPfiS_iS_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %r12d
movq %rdx, %r13
movl %ecx, %ebx
movq %r8, %r14
leal 510(%rcx), %eax
movl %ecx, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L57:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
movq %r14, %r8
movl %ebx, %ecx
movq %r13, %rdx
movl %r12d, %esi
movq %rbp, %rdi
call _Z52__device_stub__Z26gpu_weight_adjust_functionPfiS_iS_PfiS_iS_
jmp .L57
.cfi_endproc
.LFE2060:
.size _Z17gpu_weight_adjustPfiS_iS_, .-_Z17gpu_weight_adjustPfiS_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26gpu_weight_adjust_functionPfiS_iS_"
.align 8
.LC1:
.string "_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z13kernel_squashPfi"
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z32gpu_output_error_kernel_functionPfS_S_iS_"
.align 8
.LC4:
.string "_Z24kernel_bpnn_layerforwardPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26gpu_weight_adjust_functionPfiS_iS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_squashPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z32gpu_output_error_kernel_functionPfS_S_iS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z24kernel_bpnn_layerforwardPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpukernel.hip"
.globl _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii # -- Begin function _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii
.p2align 4, 0x90
.type _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii,@function
_Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii: # @_Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24kernel_bpnn_layerforwardPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii, .Lfunc_end0-_Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_ # -- Begin function _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_
.p2align 4, 0x90
.type _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_,@function
_Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_: # @_Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32gpu_output_error_kernel_functionPfS_S_iS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_, .Lfunc_end1-_Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__kernel_squashPfi # -- Begin function _Z28__device_stub__kernel_squashPfi
.p2align 4, 0x90
.type _Z28__device_stub__kernel_squashPfi,@function
_Z28__device_stub__kernel_squashPfi: # @_Z28__device_stub__kernel_squashPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13kernel_squashPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z28__device_stub__kernel_squashPfi, .Lfunc_end2-_Z28__device_stub__kernel_squashPfi
.cfi_endproc
# -- End function
.globl _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_ # -- Begin function _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_
.p2align 4, 0x90
.type _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_,@function
_Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_: # @_Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_, .Lfunc_end3-_Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_
.cfi_endproc
# -- End function
.globl _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_ # -- Begin function _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_
.p2align 4, 0x90
.type _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_,@function
_Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_: # @_Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26gpu_weight_adjust_functionPfiS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_, .Lfunc_end4-_Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_
.cfi_endproc
# -- End function
.globl _Z21gpu_bpnn_layerforwardPfS_S_ii # -- Begin function _Z21gpu_bpnn_layerforwardPfS_S_ii
.p2align 4, 0x90
.type _Z21gpu_bpnn_layerforwardPfS_S_ii,@function
_Z21gpu_bpnn_layerforwardPfS_S_ii: # @_Z21gpu_bpnn_layerforwardPfS_S_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebx
movl %ecx, %r12d
movq %rdx, %r13
movq %rsi, %r14
movq %rdi, %rbp
movabsq $4294967296, %r15 # imm = 0x100000000
leal -1(%r12), %eax
leal 510(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
incl %edi
orq %r15, %rdi
leaq 512(%r15), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq %rbp, 56(%rsp)
movq %r14, 16(%rsp)
movq %r13, 8(%rsp)
movl %r12d, 68(%rsp)
movl %ebx, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 68(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
movq %rsp, %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24kernel_bpnn_layerforwardPfS_S_ii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
callq hipDeviceSynchronize
movl %ebx, %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq %r14, 56(%rsp)
movl %ebx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_squashPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z21gpu_bpnn_layerforwardPfS_S_ii, .Lfunc_end5-_Z21gpu_bpnn_layerforwardPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z23gpu_output_error_kernelPfS_S_iS_ # -- Begin function _Z23gpu_output_error_kernelPfS_S_iS_
.p2align 4, 0x90
.type _Z23gpu_output_error_kernelPfS_S_iS_,@function
_Z23gpu_output_error_kernelPfS_S_iS_: # @_Z23gpu_output_error_kernelPfS_S_iS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
movl %ecx, %r14d
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
leal -1(%r14), %eax
leal 510(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq %r13, 88(%rsp)
movq %r12, 80(%rsp)
movq %r15, 72(%rsp)
movl %r14d, 12(%rsp)
movq %rbx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32gpu_output_error_kernel_functionPfS_S_iS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z23gpu_output_error_kernelPfS_S_iS_, .Lfunc_end6-_Z23gpu_output_error_kernelPfS_S_iS_
.cfi_endproc
# -- End function
.globl _Z23gpu_hidden_error_kernelPfiS_iS_S_ # -- Begin function _Z23gpu_hidden_error_kernelPfiS_iS_S_
.p2align 4, 0x90
.type _Z23gpu_hidden_error_kernelPfiS_iS_S_,@function
_Z23gpu_hidden_error_kernelPfiS_iS_S_: # @_Z23gpu_hidden_error_kernelPfiS_iS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movq %rdx, %r15
movl %esi, %r12d
movq %rdi, %r13
leal -1(%r12), %eax
leal 510(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq %r13, 88(%rsp)
movl %r12d, 12(%rsp)
movq %r15, 80(%rsp)
movl %ebp, 8(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z23gpu_hidden_error_kernelPfiS_iS_S_, .Lfunc_end7-_Z23gpu_hidden_error_kernelPfiS_iS_S_
.cfi_endproc
# -- End function
.globl _Z17gpu_weight_adjustPfiS_iS_ # -- Begin function _Z17gpu_weight_adjustPfiS_iS_
.p2align 4, 0x90
.type _Z17gpu_weight_adjustPfiS_iS_,@function
_Z17gpu_weight_adjustPfiS_iS_: # @_Z17gpu_weight_adjustPfiS_iS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movl %ecx, %r14d
movq %rdx, %r15
movl %esi, %ebp
movq %rdi, %r12
leal -1(%r14), %eax
leal 510(%r14), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_2
# %bb.1:
movq %r12, 72(%rsp)
movl %ebp, 4(%rsp)
movq %r15, 64(%rsp)
movl %r14d, (%rsp)
movq %rbx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26gpu_weight_adjust_functionPfiS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_2:
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z17gpu_weight_adjustPfiS_iS_, .Lfunc_end8-_Z17gpu_weight_adjustPfiS_iS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24kernel_bpnn_layerforwardPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32gpu_output_error_kernel_functionPfS_S_iS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_squashPfi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26gpu_weight_adjust_functionPfiS_iS_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24kernel_bpnn_layerforwardPfS_S_ii,@object # @_Z24kernel_bpnn_layerforwardPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z24kernel_bpnn_layerforwardPfS_S_ii
.p2align 3, 0x0
_Z24kernel_bpnn_layerforwardPfS_S_ii:
.quad _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii
.size _Z24kernel_bpnn_layerforwardPfS_S_ii, 8
.type _Z32gpu_output_error_kernel_functionPfS_S_iS_,@object # @_Z32gpu_output_error_kernel_functionPfS_S_iS_
.globl _Z32gpu_output_error_kernel_functionPfS_S_iS_
.p2align 3, 0x0
_Z32gpu_output_error_kernel_functionPfS_S_iS_:
.quad _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_
.size _Z32gpu_output_error_kernel_functionPfS_S_iS_, 8
.type _Z13kernel_squashPfi,@object # @_Z13kernel_squashPfi
.globl _Z13kernel_squashPfi
.p2align 3, 0x0
_Z13kernel_squashPfi:
.quad _Z28__device_stub__kernel_squashPfi
.size _Z13kernel_squashPfi, 8
.type _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_,@object # @_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.globl _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.p2align 3, 0x0
_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_:
.quad _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_
.size _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_, 8
.type _Z26gpu_weight_adjust_functionPfiS_iS_,@object # @_Z26gpu_weight_adjust_functionPfiS_iS_
.globl _Z26gpu_weight_adjust_functionPfiS_iS_
.p2align 3, 0x0
_Z26gpu_weight_adjust_functionPfiS_iS_:
.quad _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_
.size _Z26gpu_weight_adjust_functionPfiS_iS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24kernel_bpnn_layerforwardPfS_S_ii"
.size .L__unnamed_1, 37
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z32gpu_output_error_kernel_functionPfS_S_iS_"
.size .L__unnamed_2, 46
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13kernel_squashPfi"
.size .L__unnamed_3, 21
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z32gpu_hidden_error_kernel_functionPfiS_iS_S_"
.size .L__unnamed_4, 47
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z26gpu_weight_adjust_functionPfiS_iS_"
.size .L__unnamed_5, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__kernel_bpnn_layerforwardPfS_S_ii
.addrsig_sym _Z47__device_stub__gpu_output_error_kernel_functionPfS_S_iS_
.addrsig_sym _Z28__device_stub__kernel_squashPfi
.addrsig_sym _Z47__device_stub__gpu_hidden_error_kernel_functionPfiS_iS_S_
.addrsig_sym _Z41__device_stub__gpu_weight_adjust_functionPfiS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24kernel_bpnn_layerforwardPfS_S_ii
.addrsig_sym _Z32gpu_output_error_kernel_functionPfS_S_iS_
.addrsig_sym _Z13kernel_squashPfi
.addrsig_sym _Z32gpu_hidden_error_kernel_functionPfiS_iS_S_
.addrsig_sym _Z26gpu_weight_adjust_functionPfiS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// simple_conv.cu
// Conv
//
// Created by DB on 12/27/18.
// Copyright © 2018 D Blalock. All rights reserved.
//
#include <stdio.h> | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// simple_conv.cu
// Conv
//
// Created by DB on 12/27/18.
// Copyright © 2018 D Blalock. All rights reserved.
//
#include <stdio.h> | .file "tmpxft_0003351f_00000000-6_simple_conv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// simple_conv.cu
// Conv
//
// Created by DB on 12/27/18.
// Copyright © 2018 D Blalock. All rights reserved.
//
#include <stdio.h> | //
// simple_conv.cu
// Conv
//
// Created by DB on 12/27/18.
// Copyright © 2018 D Blalock. All rights reserved.
//
#include <hip/hip_runtime.h>
#include <stdio.h> |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// simple_conv.cu
// Conv
//
// Created by DB on 12/27/18.
// Copyright © 2018 D Blalock. All rights reserved.
//
#include <hip/hip_runtime.h>
#include <stdio.h> | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// simple_conv.cu
// Conv
//
// Created by DB on 12/27/18.
// Copyright © 2018 D Blalock. All rights reserved.
//
#include <hip/hip_runtime.h>
#include <stdio.h> | .text
.file "simple_conv.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003351f_00000000-6_simple_conv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple_conv.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0xfffff, PT ; /* 0x000fffff0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
} | .file "tmpxft_0001d877_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 0xfffff
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add( int *a, int *b, int *c ) {
int tid = blockIdx.x; // this thread handles the data at its thread id
if (tid < N)
c[tid] = a[tid] + b[tid];
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0xfffff, PT ; /* 0x000fffff0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 0xfffff
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001d877_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wcpp"
#include <thrust/device_vector.h>
__global__ void
_cu_vertdegree(int numpts, int colsize, float eps, float* d_data, int* d_Va)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= numpts)
return;
d_Va[i] = 0;
for (int j = 0; j < numpts; ++j) {
float accum = 0.0;
for (int cs = 0; cs < colsize; ++cs) {
accum += (d_data[i * colsize + cs] - d_data[j * colsize + cs]) *
(d_data[i * colsize + cs] - d_data[j * colsize + cs]);
}
accum = sqrtf(accum);
if (accum < eps) {
d_Va[i] += 1;
}
}
}
__global__ void
_cu_asmadjlist(int numpts, int colsize, float eps, float* d_data, int* d_Va1, int* d_Ea)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= numpts)
return;
int basei = d_Va1[i];
for (int j = 0; j < numpts; ++j) {
float accum = 0.0;
for (int cs = 0; cs < colsize; ++cs) {
accum += (d_data[i * colsize + cs] - d_data[j * colsize + cs]) *
(d_data[i * colsize + cs] - d_data[j * colsize + cs]);
}
accum = sqrtf(accum);
if (accum < eps) {
d_Ea[basei] = j;
++basei;
}
}
}
__global__ void
_cu_breadth_first_search_kern(int numpts, int* d_Ea, int* d_Va0, int* d_Va1, int* d_Fa, int* d_Xa)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= numpts)
return;
if (d_Fa[tid])
{
d_Fa[tid] = 0;
d_Xa[tid] = 1;
int nmax_idx = d_Va1[tid] + d_Va0[tid];
for (int i = d_Va1[tid]; i < nmax_idx; ++i )
{
int nid = d_Ea[i];
if (!d_Xa[nid])
{
d_Fa[nid] = 1;
}
}
}
}
namespace clustering {
void vertdegree(int N, int colsize, float eps, float* d_data, int* d_Va)
{
_cu_vertdegree<<<(N + 255) / 256, 256>>>(N, colsize, eps, d_data, d_Va);
cudaDeviceSynchronize();
}
void adjlistsind(int N, int* Va0, int* Va1)
{
thrust::device_ptr<int> va0_ptr(Va0);
thrust::device_ptr<int> va1_ptr(Va1);
thrust::exclusive_scan(va0_ptr, va0_ptr+N, va1_ptr);
cudaDeviceSynchronize();
}
void asmadjlist(int N, int colsize, float eps, float* d_data, int* d_Va1, int* d_Ea)
{
_cu_asmadjlist<<<(N + 255) / 256, 256>>>(N, colsize, eps, d_data, d_Va1, d_Ea);
cudaDeviceSynchronize();
}
void breadth_first_search_kern(int N, int* d_Ea, int* d_Va0, int* d_Va1, int* d_Fa, int* d_Xa)
{
_cu_breadth_first_search_kern<<<(N + 255) / 256, 256>>>(N, d_Ea, d_Va0, d_Va1, d_Fa, d_Xa);
cudaDeviceSynchronize();
}
}
#pragma GCC diagnostic pop | #pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wcpp"
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
__global__ void
_cu_vertdegree(int numpts, int colsize, float eps, float* d_data, int* d_Va)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= numpts)
return;
d_Va[i] = 0;
for (int j = 0; j < numpts; ++j) {
float accum = 0.0;
for (int cs = 0; cs < colsize; ++cs) {
accum += (d_data[i * colsize + cs] - d_data[j * colsize + cs]) *
(d_data[i * colsize + cs] - d_data[j * colsize + cs]);
}
accum = sqrtf(accum);
if (accum < eps) {
d_Va[i] += 1;
}
}
}
__global__ void
_cu_asmadjlist(int numpts, int colsize, float eps, float* d_data, int* d_Va1, int* d_Ea)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= numpts)
return;
int basei = d_Va1[i];
for (int j = 0; j < numpts; ++j) {
float accum = 0.0;
for (int cs = 0; cs < colsize; ++cs) {
accum += (d_data[i * colsize + cs] - d_data[j * colsize + cs]) *
(d_data[i * colsize + cs] - d_data[j * colsize + cs]);
}
accum = sqrtf(accum);
if (accum < eps) {
d_Ea[basei] = j;
++basei;
}
}
}
__global__ void
_cu_breadth_first_search_kern(int numpts, int* d_Ea, int* d_Va0, int* d_Va1, int* d_Fa, int* d_Xa)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid >= numpts)
return;
if (d_Fa[tid])
{
d_Fa[tid] = 0;
d_Xa[tid] = 1;
int nmax_idx = d_Va1[tid] + d_Va0[tid];
for (int i = d_Va1[tid]; i < nmax_idx; ++i )
{
int nid = d_Ea[i];
if (!d_Xa[nid])
{
d_Fa[nid] = 1;
}
}
}
}
namespace clustering {
void vertdegree(int N, int colsize, float eps, float* d_data, int* d_Va)
{
_cu_vertdegree<<<(N + 255) / 256, 256>>>(N, colsize, eps, d_data, d_Va);
hipDeviceSynchronize();
}
void adjlistsind(int N, int* Va0, int* Va1)
{
thrust::device_ptr<int> va0_ptr(Va0);
thrust::device_ptr<int> va1_ptr(Va1);
thrust::exclusive_scan(va0_ptr, va0_ptr+N, va1_ptr);
hipDeviceSynchronize();
}
void asmadjlist(int N, int colsize, float eps, float* d_data, int* d_Va1, int* d_Ea)
{
_cu_asmadjlist<<<(N + 255) / 256, 256>>>(N, colsize, eps, d_data, d_Va1, d_Ea);
hipDeviceSynchronize();
}
void breadth_first_search_kern(int N, int* d_Ea, int* d_Va0, int* d_Va1, int* d_Fa, int* d_Xa)
{
_cu_breadth_first_search_kern<<<(N + 255) / 256, 256>>>(N, d_Ea, d_Va0, d_Va1, d_Fa, d_Xa);
hipDeviceSynchronize();
}
}
#pragma GCC diagnostic pop |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void K(int *x) {
*x = 0;
printf("%d\n", *x);
}
int main() {
int *x = NULL;
K<<<2, 10>>>(x);
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z1KPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fca00078e00ff */
/*0010*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ STL [R1], RZ ; /* 0x000000ff01007387 */
/* 0x0001e20000100800 */
/*0070*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*0080*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00a0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc400078e00ff */
/*00c0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*00d0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fcc0000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0130*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0140*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void K(int *x) {
*x = 0;
printf("%d\n", *x);
}
int main() {
int *x = NULL;
K<<<2, 10>>>(x);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00168e11_00000000-6_gdb.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z1KPiPi
.type _Z20__device_stub__Z1KPiPi, @function
_Z20__device_stub__Z1KPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z1KPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z20__device_stub__Z1KPiPi, .-_Z20__device_stub__Z1KPiPi
.globl _Z1KPi
.type _Z1KPi, @function
_Z1KPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z1KPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z1KPi, .-_Z1KPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl $0, %edi
call _Z20__device_stub__Z1KPiPi
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1KPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1KPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
__global__ void K(int *x) {
*x = 0;
printf("%d\n", *x);
}
int main() {
int *x = NULL;
K<<<2, 10>>>(x);
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void K(int *x) {
*x = 0;
printf("%d\n", *x);
}
int main() {
int *x = NULL;
K<<<2, 10>>>(x);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void K(int *x) {
*x = 0;
printf("%d\n", *x);
}
int main() {
int *x = NULL;
K<<<2, 10>>>(x);
hipDeviceSynchronize();
return 0;
} | .text
.file "gdb.hip"
.globl _Z16__device_stub__KPi # -- Begin function _Z16__device_stub__KPi
.p2align 4, 0x90
.type _Z16__device_stub__KPi,@function
_Z16__device_stub__KPi: # @_Z16__device_stub__KPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1KPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z16__device_stub__KPi, .Lfunc_end0-_Z16__device_stub__KPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 8(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq $0, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1KPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1KPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1KPi,@object # @_Z1KPi
.section .rodata,"a",@progbits
.globl _Z1KPi
.p2align 3, 0x0
_Z1KPi:
.quad _Z16__device_stub__KPi
.size _Z1KPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1KPi"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__KPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1KPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00168e11_00000000-6_gdb.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z1KPiPi
.type _Z20__device_stub__Z1KPiPi, @function
_Z20__device_stub__Z1KPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z1KPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z20__device_stub__Z1KPiPi, .-_Z20__device_stub__Z1KPiPi
.globl _Z1KPi
.type _Z1KPi, @function
_Z1KPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z1KPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z1KPi, .-_Z1KPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl $0, %edi
call _Z20__device_stub__Z1KPiPi
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1KPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1KPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gdb.hip"
.globl _Z16__device_stub__KPi # -- Begin function _Z16__device_stub__KPi
.p2align 4, 0x90
.type _Z16__device_stub__KPi,@function
_Z16__device_stub__KPi: # @_Z16__device_stub__KPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1KPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z16__device_stub__KPi, .Lfunc_end0-_Z16__device_stub__KPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 8(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq $0, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1KPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1KPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1KPi,@object # @_Z1KPi
.section .rodata,"a",@progbits
.globl _Z1KPi
.p2align 3, 0x0
_Z1KPi:
.quad _Z16__device_stub__KPi
.size _Z1KPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1KPi"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__KPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1KPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* jegood Joshua Good */
/**
* @file p3.cu
* Calculates the minimum distance for a set of file-specified points using GPU
* multi-threading. This program requires access to a CUDA-enabled GPU (i.e. NVIDIA
* graphics card).
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <limits.h>
#include <math.h>
#include <time.h>
/** Maximum number of threads per block */
#define MAX_THRDS 1024
// Point struct
struct point{
int x;
int y;
int index;
double minDistance;
}typedef Point;
/**
* Calculates the minimum distance for this point from each point
* in the points array.
* @param points the point array
* @param numPoints number of points in the point array
*/
__global__ void calcMinDist(Point *points, int numPoints)
{
// Compute the minimum distance for each point in the point array
for(int i = 0; i < numPoints; i++){
// Ensure we don't calculate the distance to a point from itself
if(i != points[blockIdx.x].index){
double distance = sqrt(pow((double)(points[i].x - points[blockIdx.x].x), 2) + pow((double)(points[i].y - points[blockIdx.x].y), 2));
// Check if distance is a new minimum distance for this point
if(distance < points[blockIdx.x].minDistance){
points[blockIdx.x].minDistance = distance;
}
}
}
}
/**
* Calculates the minimum distance for a set of file-specified points using a CUDA
* kernel function. Reports this information and its associated minimum distance points
* alongside the time taken to complete this process.
* @param argc number of command line arguments
* @param argv list of command of line arguments
*/
int main(int argc, char *argv[])
{
FILE *fp;
// Ensure a valid file is given
if(!(fp = fopen(argv[1], "r"))){
printf("Usage: ./p3 <input file>\n");
exit(EXIT_FAILURE);
}
/** Start time for a process */
clock_t start;
/** End time for a process */
clock_t finish;
// Start process clock
start = clock();
// Initially loop through and calculate the number of points in the file
Point p;
/** Number of points in the file */
int numPoints = 0;
while(fscanf(fp, "%d%d", &p.x, &p.y) == 2){ // read, but don't store(*)
numPoints++;
}
// Rewind the file and assign points in the array of points
rewind(fp);
/** Index of point in points array */
int index = 0;
Point points[numPoints];
for(int i = 0; i < numPoints; i++){
// Scan in next point
fscanf(fp, "%d %d", &p.x, &p.y);
p.index = index;
p.minDistance = INFINITY;
points[i] = p;
index++;
}
// Allocate memory for kernel threads
double minDist = INFINITY;
Point *arr_p;
int size = numPoints * sizeof(Point);
cudaMalloc((void**)&arr_p, size);
cudaMemcpy(arr_p, points, size, cudaMemcpyHostToDevice);
// Launch the kernel to do work
// Runs numPoints blocks with one thread each
calcMinDist<<<numPoints, 1>>>(arr_p, numPoints);
// Use result on host
cudaMemcpy(points, arr_p, size, cudaMemcpyDeviceToHost);
// Determine minDist for these points
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance < minDist){
minDist = points[i].minDistance;
}
}
// Determine which points have minimum distance
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance == minDist){
printf("(%d,%d)", points[i].x, points[i].y);
}
}
// Print the minimum distance for the set of points
printf("%lf\n", minDist);
// End process time
finish = clock();
// Print the process time
printf("Time : %lf seconds\n", (double) (finish - start) / CLOCKS_PER_SEC);
// Free memory
cudaFree(arr_p);
// Return EXIT_SUCCESS
return 0;
} | code for sm_80
Function : _Z11calcMinDistP5pointi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, 0x18 ; /* 0x00000018ff057424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x001fca00078e0005 */
/*0080*/ LDG.E R0, [R4.64+0x8] ; /* 0x0000080404007981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x004fca00078e0a00 */
/*00d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*00e0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fce0003f26270 */
/*0100*/ @!P0 BRA 0x640 ; /* 0x0000053000008947 */
/* 0x003fea0003800000 */
/*0110*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x000ea2000c1e1900 */
/*0130*/ MOV R28, 0x190 ; /* 0x00000190001c7802 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.IADD R10, R3, 0x1, -R10 ; /* 0x00000001030a7824 */
/* 0x004fc800078e0a0a */
/*0150*/ I2F.F64 R8, R10 ; /* 0x0000000a00087312 */
/* 0x000e240000201c00 */
/*0160*/ DADD R12, -RZ, |R8| ; /* 0x00000000ff0c7229 */
/* 0x001e140000000508 */
/*0170*/ IMAD.MOV.U32 R18, RZ, RZ, R12 ; /* 0x000000ffff127224 */
/* 0x001fe400078e000c */
/*0180*/ CALL.REL.NOINC 0x930 ; /* 0x000007a000007944 */
/* 0x000fea0003c00000 */
/*0190*/ DADD R12, R8, 2 ; /* 0x40000000080c7429 */
/* 0x002e620000000000 */
/*01a0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd20003f05270 */
/*01b0*/ LOP3.LUT R12, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d0c7812 */
/* 0x002fe200078ec0ff */
/*01c0*/ IMAD.MOV.U32 R13, RZ, RZ, R19 ; /* 0x000000ffff0d7224 */
/* 0x004fc600078e0013 */
/*01d0*/ ISETP.NE.AND P2, PT, R12, 0x7ff00000, PT ; /* 0x7ff000000c00780c */
/* 0x000fe20003f45270 */
/*01e0*/ IMAD.MOV.U32 R12, RZ, RZ, R18 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0012 */
/*01f0*/ @!P0 CS2R R12, SRZ ; /* 0x00000000000c8805 */
/* 0x000fd6000001ff00 */
/*0200*/ @P2 BRA 0x2b0 ; /* 0x000000a000002947 */
/* 0x000fea0003800000 */
/*0210*/ DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; /* 0x7ff000000800742a */
/* 0x000e5c0003f0c200 */
/*0220*/ @P0 BRA 0x2a0 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*0230*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0240*/ LOP3.LUT R8, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09087812 */
/* 0x000fc800078ec0ff */
/*0250*/ ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; /* 0x7ff000000800780c */
/* 0x000fda0000705670 */
/*0260*/ @P0 BRA 0x2b0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R13, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff0d7424 */
/* 0x000fe200078e00ff */
/*0290*/ BRA 0x2b0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*02a0*/ DADD R12, R8, 2 ; /* 0x40000000080c7429 */
/* 0x0002880000000000 */
/*02b0*/ LDG.E R3, [R4.64+0x4] ; /* 0x0000040404037981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R8, [R6.64+0x4] ; /* 0x0000040406087981 */
/* 0x002ee2000c1e1900 */
/*02d0*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003f05270 */
/*02e0*/ MOV R28, 0x370 ; /* 0x00000370001c7802 */
/* 0x000fc40000000f00 */
/*02f0*/ FSEL R11, R13, 1.875, P0 ; /* 0x3ff000000d0b7808 */
/* 0x004fe40000000000 */
/*0300*/ FSEL R10, R12, RZ, P0 ; /* 0x000000ff0c0a7208 */
/* 0x000fe20000000000 */
/*0310*/ IMAD.IADD R3, R8, 0x1, -R3 ; /* 0x0000000108037824 */
/* 0x008fc800078e0a03 */
/*0320*/ I2F.F64 R8, R3 ; /* 0x0000000300087312 */
/* 0x000e640000201c00 */
/*0330*/ DADD R14, -RZ, |R8| ; /* 0x00000000ff0e7229 */
/* 0x002e540000000508 */
/*0340*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x002fe400078e000e */
/*0350*/ IMAD.MOV.U32 R13, RZ, RZ, R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e000f */
/*0360*/ CALL.REL.NOINC 0x930 ; /* 0x000005c000007944 */
/* 0x001fea0003c00000 */
/*0370*/ DADD R12, R8, 2 ; /* 0x40000000080c7429 */
/* 0x002e620000000000 */
/*0380*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fd20003f05270 */
/*0390*/ LOP3.LUT R12, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d0c7812 */
/* 0x002fe200078ec0ff */
/*03a0*/ IMAD.MOV.U32 R13, RZ, RZ, R19 ; /* 0x000000ffff0d7224 */
/* 0x004fc600078e0013 */
/*03b0*/ ISETP.NE.AND P2, PT, R12, 0x7ff00000, PT ; /* 0x7ff000000c00780c */
/* 0x000fe20003f45270 */
/*03c0*/ IMAD.MOV.U32 R12, RZ, RZ, R18 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0012 */
/*03d0*/ @!P0 CS2R R12, SRZ ; /* 0x00000000000c8805 */
/* 0x000fd6000001ff00 */
/*03e0*/ @P2 BRA 0x490 ; /* 0x000000a000002947 */
/* 0x000fea0003800000 */
/*03f0*/ DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; /* 0x7ff000000800742a */
/* 0x000e5c0003f0c200 */
/*0400*/ @P0 BRA 0x480 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*0410*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0420*/ LOP3.LUT R8, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09087812 */
/* 0x000fc800078ec0ff */
/*0430*/ ISETP.NE.OR P0, PT, R8, 0x7ff00000, P0 ; /* 0x7ff000000800780c */
/* 0x000fda0000705670 */
/*0440*/ @P0 BRA 0x490 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD.MOV.U32 R13, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff0d7424 */
/* 0x000fe200078e00ff */
/*0470*/ BRA 0x490 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0480*/ DADD R12, R8, 2 ; /* 0x40000000080c7429 */
/* 0x00028c0000000000 */
/*0490*/ ISETP.NE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f05270 */
/*04a0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0f7424 */
/* 0x000fe200078e00ff */
/*04c0*/ FSEL R8, R12, RZ, P0 ; /* 0x000000ff0c087208 */
/* 0x006fe40000000000 */
/*04d0*/ FSEL R9, R13, 1.875, P0 ; /* 0x3ff000000d097808 */
/* 0x000fcc0000000000 */
/*04e0*/ DADD R10, R10, R8 ; /* 0x000000000a0a7229 */
/* 0x000e4c0000000008 */
/*04f0*/ MUFU.RSQ64H R13, R11 ; /* 0x0000000b000d7308 */
/* 0x002e680000001c00 */
/*0500*/ IADD3 R12, R11, -0x3500000, RZ ; /* 0xfcb000000b0c7810 */
/* 0x000fc80007ffe0ff */
/*0510*/ ISETP.GE.U32.AND P0, PT, R12, 0x7ca00000, PT ; /* 0x7ca000000c00780c */
/* 0x000fe40003f06070 */
/*0520*/ DMUL R8, R12, R12 ; /* 0x0000000c0c087228 */
/* 0x002e4c0000000000 */
/*0530*/ DFMA R8, R10, -R8, 1 ; /* 0x3ff000000a08742b */
/* 0x002e4c0000000808 */
/*0540*/ DFMA R14, R8, R14, 0.5 ; /* 0x3fe00000080e742b */
/* 0x002fc8000000000e */
/*0550*/ DMUL R8, R12, R8 ; /* 0x000000080c087228 */
/* 0x000e4c0000000000 */
/*0560*/ DFMA R18, R14, R8, R12 ; /* 0x000000080e12722b */
/* 0x002e4c000000000c */
/*0570*/ DMUL R14, R10, R18 ; /* 0x000000120a0e7228 */
/* 0x002e480000000000 */
/*0580*/ IADD3 R17, R19, -0x100000, RZ ; /* 0xfff0000013117810 */
/* 0x001fe20007ffe0ff */
/*0590*/ IMAD.MOV.U32 R16, RZ, RZ, R18 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0012 */
/*05a0*/ DFMA R20, R14, -R14, R10 ; /* 0x8000000e0e14722b */
/* 0x002e0c000000000a */
/*05b0*/ DFMA R8, R20, R16, R14 ; /* 0x000000101408722b */
/* 0x001062000000000e */
/*05c0*/ @!P0 BRA 0x610 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*05d0*/ MOV R8, 0x5f0 ; /* 0x000005f000087802 */
/* 0x002fca0000000f00 */
/*05e0*/ CALL.REL.NOINC 0x690 ; /* 0x000000a000007944 */
/* 0x001fea0003c00000 */
/*05f0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x002fe400078e000a */
/*0600*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fc800078e000b */
/*0610*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000ea4000c1e1b00 */
/*0620*/ DSETP.GEU.AND P0, PT, R8, R10, PT ; /* 0x0000000a0800722a */
/* 0x006e5c0003f0e000 */
/*0630*/ @!P0 STG.E.64 [R4.64+0x10], R8 ; /* 0x0000100804008986 */
/* 0x0023e4000c101b04 */
/*0640*/ IADD3 R6, P0, R6, 0x18, RZ ; /* 0x0000001806067810 */
/* 0x000fe40007f1e0ff */
/*0650*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc60007ffe0ff */
/*0660*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe200000e0607 */
/*0670*/ @!P1 BRA 0xd0 ; /* 0xfffffa5000009947 */
/* 0x000fea000383ffff */
/*0680*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0690*/ ISETP.GE.U32.AND P0, PT, R12, -0x3400000, PT ; /* 0xfcc000000c00780c */
/* 0x000fe20003f06070 */
/*06a0*/ IMAD.MOV.U32 R12, RZ, RZ, R10 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e000a */
/*06b0*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e000b */
/*06c0*/ IMAD.MOV.U32 R16, RZ, RZ, R18 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0012 */
/*06d0*/ IMAD.MOV.U32 R10, RZ, RZ, R20 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0014 */
/*06e0*/ IMAD.MOV.U32 R11, RZ, RZ, R21 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0015 */
/*06f0*/ @!P0 BRA 0x780 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0700*/ DFMA.RM R10, R10, R16, R14 ; /* 0x000000100a0a722b */
/* 0x000e14000000400e */
/*0710*/ IADD3 R14, P0, R10, 0x1, RZ ; /* 0x000000010a0e7810 */
/* 0x001fca0007f1e0ff */
/*0720*/ IMAD.X R15, RZ, RZ, R11, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fcc00000e060b */
/*0730*/ DFMA.RP R12, -R10, R14, R12 ; /* 0x0000000e0a0c722b */
/* 0x000e0c000000810c */
/*0740*/ DSETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00722a */
/* 0x001e0c0003f04000 */
/*0750*/ FSEL R10, R14, R10, P0 ; /* 0x0000000a0e0a7208 */
/* 0x001fe40000000000 */
/*0760*/ FSEL R11, R15, R11, P0 ; /* 0x0000000b0f0b7208 */
/* 0x000fe20000000000 */
/*0770*/ BRA 0x910 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*0780*/ DSETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00722a */
/* 0x000e1c0003f05000 */
/*0790*/ @!P0 BRA 0x900 ; /* 0x0000016000008947 */
/* 0x001fea0003800000 */
/*07a0*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fda0003f06270 */
/*07b0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a8424 */
/* 0x000fe400078e00ff */
/*07c0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, -0x80000 ; /* 0xfff80000ff0b8424 */
/* 0x000fe200078e00ff */
/*07d0*/ @!P0 BRA 0x910 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.GT.AND P0, PT, R13, 0x7fefffff, PT ; /* 0x7fefffff0d00780c */
/* 0x000fda0003f04270 */
/*07f0*/ @P0 BRA 0x900 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0800*/ DMUL R10, R12, 8.11296384146066816958e+31 ; /* 0x469000000c0a7828 */
/* 0x0000620000000000 */
/*0810*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x000fe400078e00ff */
/*0820*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x001fe400078e00ff */
/*0830*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff117424 */
/* 0x000fe200078e00ff */
/*0840*/ MUFU.RSQ64H R13, R11 ; /* 0x0000000b000d7308 */
/* 0x002e260000001c00 */
/*0850*/ DMUL R14, R12, R12 ; /* 0x0000000c0c0e7228 */
/* 0x001e0c0000000000 */
/*0860*/ DFMA R14, R10, -R14, 1 ; /* 0x3ff000000a0e742b */
/* 0x001e0c000000080e */
/*0870*/ DFMA R16, R14, R16, 0.5 ; /* 0x3fe000000e10742b */
/* 0x001fc80000000010 */
/*0880*/ DMUL R14, R12, R14 ; /* 0x0000000e0c0e7228 */
/* 0x000e0c0000000000 */
/*0890*/ DFMA R14, R16, R14, R12 ; /* 0x0000000e100e722b */
/* 0x001e0c000000000c */
/*08a0*/ DMUL R12, R10, R14 ; /* 0x0000000e0a0c7228 */
/* 0x0010480000000000 */
/*08b0*/ IADD3 R15, R15, -0x100000, RZ ; /* 0xfff000000f0f7810 */
/* 0x001fe40007ffe0ff */
/*08c0*/ DFMA R16, R12, -R12, R10 ; /* 0x8000000c0c10722b */
/* 0x002e0c000000000a */
/*08d0*/ DFMA R10, R14, R16, R12 ; /* 0x000000100e0a722b */
/* 0x001e14000000000c */
/*08e0*/ IADD3 R11, R11, -0x3500000, RZ ; /* 0xfcb000000b0b7810 */
/* 0x001fe20007ffe0ff */
/*08f0*/ BRA 0x910 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0900*/ DADD R10, R12, R12 ; /* 0x000000000c0a7229 */
/* 0x000048000000000c */
/*0910*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*0920*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff6d008007950 */
/* 0x000fea0003c3ffff */
/*0930*/ SHF.R.U32.HI R29, RZ, 0x14, R13 ; /* 0x00000014ff1d7819 */
/* 0x000fe2000001160d */
/*0940*/ IMAD.MOV.U32 R12, RZ, RZ, R18 ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e0012 */
/*0950*/ ISETP.NE.AND P0, PT, R29, RZ, PT ; /* 0x000000ff1d00720c */
/* 0x000fda0003f05270 */
/*0960*/ @!P0 DMUL R22, R12, 1.80143985094819840000e+16 ; /* 0x435000000c168828 */
/* 0x0000640000000000 */
/*0970*/ IMAD.MOV.U32 R12, RZ, RZ, R13 ; /* 0x000000ffff0c7224 */
/* 0x001fd000078e000d */
/*0980*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, R23 ; /* 0x000000ffff0c8224 */
/* 0x002fe200078e0017 */
/*0990*/ @!P0 LEA.HI R29, R23, 0xffffffca, RZ, 0xc ; /* 0xffffffca171d8811 */
/* 0x000fe200078f60ff */
/*09a0*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, R22 ; /* 0x000000ffff128224 */
/* 0x000fc600078e0016 */
/*09b0*/ LOP3.LUT R12, R12, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0c0c7812 */
/* 0x000fc800078ec0ff */
/*09c0*/ LOP3.LUT R19, R12, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000c137812 */
/* 0x000fe200078efcff */
/*09d0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e00ff */
/*09e0*/ ISETP.GE.U32.AND P2, PT, R19, 0x3ff6a09f, PT ; /* 0x3ff6a09f1300780c */
/* 0x000fda0003f46070 */
/*09f0*/ @P2 IADD3 R13, R19, -0x100000, RZ ; /* 0xfff00000130d2810 */
/* 0x000fca0007ffe0ff */
/*0a00*/ @P2 IMAD.MOV.U32 R19, RZ, RZ, R13 ; /* 0x000000ffff132224 */
/* 0x000fcc00078e000d */
/*0a10*/ DADD R20, R18, 1 ; /* 0x3ff0000012147429 */
/* 0x000e080000000000 */
/*0a20*/ DADD R18, R18, -1 ; /* 0xbff0000012127429 */
/* 0x000fe40000000000 */
/*0a30*/ MUFU.RCP64H R13, R21 ; /* 0x00000015000d7308 */
/* 0x001e240000001800 */
/*0a40*/ DFMA R16, -R20, R12, 1 ; /* 0x3ff000001410742b */
/* 0x001e0c000000010c */
/*0a50*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0a60*/ DFMA R16, R12, R16, R12 ; /* 0x000000100c10722b */
/* 0x001e0c000000000c */
/*0a70*/ DMUL R12, R16, R18 ; /* 0x00000012100c7228 */
/* 0x001e0c0000000000 */
/*0a80*/ DFMA R12, R16, R18, R12 ; /* 0x00000012100c722b */
/* 0x001e0c000000000c */
/*0a90*/ DADD R14, R18, -R12 ; /* 0x00000000120e7229 */
/* 0x001e08000000080c */
/*0aa0*/ DMUL R24, R12, R12 ; /* 0x0000000c0c187228 */
/* 0x000fc80000000000 */
/*0ab0*/ DADD R14, R14, R14 ; /* 0x000000000e0e7229 */
/* 0x001e0c000000000e */
/*0ac0*/ DFMA R14, R18, -R12, R14 ; /* 0x8000000c120e722b */
/* 0x001064000000000e */
/*0ad0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff127424 */
/* 0x001fe400078e00ff */
/*0ae0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff137424 */
/* 0x000fe400078e00ff */
/*0af0*/ DMUL R14, R16, R14 ; /* 0x0000000e100e7228 */
/* 0x002fc80000000000 */
/*0b00*/ DFMA R18, R24, R18, c[0x2][0x0] ; /* 0x008000001812762b */
/* 0x000e0c0000000012 */
/*0b10*/ DFMA R20, R24, R18, c[0x2][0x8] ; /* 0x008002001814762b */
/* 0x001e220000000012 */
/*0b20*/ IADD3 R23, R15, 0x100000, RZ ; /* 0x001000000f177810 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD.MOV.U32 R22, RZ, RZ, R14 ; /* 0x000000ffff167224 */
/* 0x000fc800078e000e */
/*0b40*/ DFMA R20, R24, R20, c[0x2][0x10] ; /* 0x008004001814762b */
/* 0x001e0c0000000014 */
/*0b50*/ DFMA R20, R24, R20, c[0x2][0x18] ; /* 0x008006001814762b */
/* 0x001e0c0000000014 */
/*0b60*/ DFMA R20, R24, R20, c[0x2][0x20] ; /* 0x008008001814762b */
/* 0x001e0c0000000014 */
/*0b70*/ DFMA R20, R24, R20, c[0x2][0x28] ; /* 0x00800a001814762b */
/* 0x001e0c0000000014 */
/*0b80*/ DFMA R16, R24, R20, c[0x2][0x30] ; /* 0x00800c001810762b */
/* 0x001e0c0000000014 */
/*0b90*/ DADD R18, -R16, c[0x2][0x30] ; /* 0x00800c0010127629 */
/* 0x001e0c0000000100 */
/*0ba0*/ DFMA R18, R24, R20, R18 ; /* 0x000000141812722b */
/* 0x001e080000000012 */
/*0bb0*/ DMUL R20, R12, R12 ; /* 0x0000000c0c147228 */
/* 0x000e480000000000 */
/*0bc0*/ DADD R18, RZ, R18 ; /* 0x00000000ff127229 */
/* 0x001fc80000000012 */
/*0bd0*/ DFMA R24, R12, R12, -R20 ; /* 0x0000000c0c18722b */
/* 0x002e0c0000000814 */
/*0be0*/ DFMA R22, R12, R22, R24 ; /* 0x000000160c16722b */
/* 0x001fc80000000018 */
/*0bf0*/ DMUL R24, R12, R20 ; /* 0x000000140c187228 */
/* 0x000e0c0000000000 */
/*0c00*/ DFMA R26, R12, R20, -R24 ; /* 0x000000140c1a722b */
/* 0x001e0c0000000818 */
/*0c10*/ DFMA R26, R14, R20, R26 ; /* 0x000000140e1a722b */
/* 0x001e0c000000001a */
/*0c20*/ DFMA R22, R12, R22, R26 ; /* 0x000000160c16722b */
/* 0x001fc8000000001a */
/*0c30*/ DADD R26, R18, c[0x2][0x38] ; /* 0x00800e00121a7629 */
/* 0x000e0c0000000000 */
/*0c40*/ DADD R18, R16, R26 ; /* 0x0000000010127229 */
/* 0x001e0c000000001a */
/*0c50*/ DADD R16, R16, -R18 ; /* 0x0000000010107229 */
/* 0x001e080000000812 */
/*0c60*/ DMUL R20, R18, R24 ; /* 0x0000001812147228 */
/* 0x000e480000000000 */
/*0c70*/ DADD R26, R26, R16 ; /* 0x000000001a1a7229 */
/* 0x001fc80000000010 */
/*0c80*/ DFMA R16, R18, R24, -R20 ; /* 0x000000181210722b */
/* 0x002e0c0000000814 */
/*0c90*/ DFMA R16, R18, R22, R16 ; /* 0x000000161210722b */
/* 0x001e0c0000000010 */
/*0ca0*/ DFMA R26, R26, R24, R16 ; /* 0x000000181a1a722b */
/* 0x001e0c0000000010 */
/*0cb0*/ DADD R18, R20, R26 ; /* 0x0000000014127229 */
/* 0x001e0c000000001a */
/*0cc0*/ DADD R16, R12, R18 ; /* 0x000000000c107229 */
/* 0x001e080000000012 */
/*0cd0*/ DADD R20, R20, -R18 ; /* 0x0000000014147229 */
/* 0x000e480000000812 */
/*0ce0*/ DADD R12, R12, -R16 ; /* 0x000000000c0c7229 */
/* 0x001e080000000810 */
/*0cf0*/ DADD R20, R26, R20 ; /* 0x000000001a147229 */
/* 0x002fc80000000014 */
/*0d00*/ DADD R12, R18, R12 ; /* 0x00000000120c7229 */
/* 0x001064000000000c */
/*0d10*/ IADD3 R18, R29.reuse, -0x3ff, RZ ; /* 0xfffffc011d127810 */
/* 0x041fe40007ffe0ff */
/*0d20*/ @P2 IADD3 R18, R29, -0x3fe, RZ ; /* 0xfffffc021d122810 */
/* 0x000fe40007ffe0ff */
/*0d30*/ DADD R20, R20, R12 ; /* 0x0000000014147229 */
/* 0x002064000000000c */
/*0d40*/ LOP3.LUT R12, R18, 0x80000000, RZ, 0x3c, !PT ; /* 0x80000000120c7812 */
/* 0x001fe200078e3cff */
/*0d50*/ IMAD.MOV.U32 R13, RZ, RZ, 0x43300000 ; /* 0x43300000ff0d7424 */
/* 0x000fc600078e00ff */
/*0d60*/ DADD R20, R14, R20 ; /* 0x000000000e147229 */
/* 0x002e080000000014 */
/*0d70*/ DADD R12, R12, c[0x2][0x40] ; /* 0x008010000c0c7629 */
/* 0x000fc80000000000 */
/*0d80*/ DADD R14, R16, R20 ; /* 0x00000000100e7229 */
/* 0x001e0c0000000014 */
/*0d90*/ DFMA R18, R12, c[0x2][0x48], R14 ; /* 0x008012000c127a2b */
/* 0x001e08000000000e */
/*0da0*/ DADD R22, R16, -R14 ; /* 0x0000000010167229 */
/* 0x000e48000000080e */
/*0db0*/ DFMA R16, -R12, c[0x2][0x48], R18 ; /* 0x008012000c107a2b */
/* 0x001e080000000112 */
/*0dc0*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x002fc80000000016 */
/*0dd0*/ DADD R16, -R14, R16 ; /* 0x000000000e107229 */
/* 0x001e0c0000000110 */
/*0de0*/ DADD R14, R22, -R16 ; /* 0x00000000160e7229 */
/* 0x001e0c0000000810 */
/*0df0*/ DFMA R14, R12, c[0x2][0x50], R14 ; /* 0x008014000c0e7a2b */
/* 0x001e0c000000000e */
/*0e00*/ DADD R12, R18, R14 ; /* 0x00000000120c7229 */
/* 0x001e0c000000000e */
/*0e10*/ DADD R18, R18, -R12 ; /* 0x0000000012127229 */
/* 0x001e08000000080c */
/*0e20*/ DMUL R22, R12, 2 ; /* 0x400000000c167828 */
/* 0x000e480000000000 */
/*0e30*/ DADD R18, R14, R18 ; /* 0x000000000e127229 */
/* 0x0011e40000000012 */
/*0e40*/ IMAD.MOV.U32 R14, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0e7424 */
/* 0x001fe400078e00ff */
/*0e50*/ DFMA R20, R12, 2, -R22 ; /* 0x400000000c14782b */
/* 0x002e220000000816 */
/*0e60*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0f7424 */
/* 0x000fca00078e00ff */
/*0e70*/ DFMA R20, R18, 2, R20 ; /* 0x400000001214782b */
/* 0x001e0c0000000014 */
/*0e80*/ DADD R12, R22, R20 ; /* 0x00000000160c7229 */
/* 0x001e0c0000000014 */
/*0e90*/ DFMA R14, R12, R14, 6.75539944105574400000e+15 ; /* 0x433800000c0e742b */
/* 0x001e08000000000e */
/*0ea0*/ FSETP.GEU.AND P0, PT, |R13|, 4.1917929649353027344, PT ; /* 0x4086232b0d00780b */
/* 0x000fe40003f0e200 */
/*0eb0*/ DADD R16, R14, -6.75539944105574400000e+15 ; /* 0xc33800000e107429 */
/* 0x001e0c0000000000 */
/*0ec0*/ DFMA R18, R16, c[0x2][0x58], R12 ; /* 0x0080160010127a2b */
/* 0x001e0c000000000c */
/*0ed0*/ DFMA R18, R16, c[0x2][0x60], R18 ; /* 0x0080180010127a2b */
/* 0x0010640000000012 */
/*0ee0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff107424 */
/* 0x001fe400078e00ff */
/*0ef0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff117424 */
/* 0x000fcc00078e00ff */
/*0f00*/ DFMA R16, R18, R16, c[0x2][0x68] ; /* 0x00801a001210762b */
/* 0x002e0c0000000010 */
/*0f10*/ DFMA R16, R18, R16, c[0x2][0x70] ; /* 0x00801c001210762b */
/* 0x001e0c0000000010 */
/*0f20*/ DFMA R16, R18, R16, c[0x2][0x78] ; /* 0x00801e001210762b */
/* 0x001e0c0000000010 */
/*0f30*/ DFMA R16, R18, R16, c[0x2][0x80] ; /* 0x008020001210762b */
/* 0x001e0c0000000010 */
/*0f40*/ DFMA R16, R18, R16, c[0x2][0x88] ; /* 0x008022001210762b */
/* 0x001e0c0000000010 */
/*0f50*/ DFMA R16, R18, R16, c[0x2][0x90] ; /* 0x008024001210762b */
/* 0x001e0c0000000010 */
/*0f60*/ DFMA R16, R18, R16, c[0x2][0x98] ; /* 0x008026001210762b */
/* 0x001e0c0000000010 */
/*0f70*/ DFMA R16, R18, R16, c[0x2][0xa0] ; /* 0x008028001210762b */
/* 0x001e0c0000000010 */
/*0f80*/ DFMA R16, R18, R16, c[0x2][0xa8] ; /* 0x00802a001210762b */
/* 0x001e0c0000000010 */
/*0f90*/ DFMA R16, R18, R16, 1 ; /* 0x3ff000001210742b */
/* 0x001e0c0000000010 */
/*0fa0*/ DFMA R16, R18, R16, 1 ; /* 0x3ff000001210742b */
/* 0x001e140000000010 */
/*0fb0*/ IMAD R19, R14, 0x100000, R17 ; /* 0x001000000e137824 */
/* 0x001fe400078e0211 */
/*0fc0*/ IMAD.MOV.U32 R18, RZ, RZ, R16 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0010 */
/*0fd0*/ @!P0 BRA 0x10b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0fe0*/ FSETP.GEU.AND P2, PT, |R13|, 4.2275390625, PT ; /* 0x408748000d00780b */
/* 0x000fe20003f4e200 */
/*0ff0*/ DADD R18, R12, +INF ; /* 0x7ff000000c127429 */
/* 0x000fc80000000000 */
/*1000*/ DSETP.GEU.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00722a */
/* 0x000e0c0003f0e000 */
/*1010*/ FSEL R18, R18, RZ, P0 ; /* 0x000000ff12127208 */
/* 0x001fe40000000000 */
/*1020*/ FSEL R19, R19, RZ, P0 ; /* 0x000000ff13137208 */
/* 0x000fe20000000000 */
/*1030*/ @P2 BRA 0x10b0 ; /* 0x0000007000002947 */
/* 0x000fea0003800000 */
/*1040*/ LEA.HI R15, R14, R14, RZ, 0x1 ; /* 0x0000000e0e0f7211 */
/* 0x000fe200078f08ff */
/*1050*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc600078e00ff */
/*1060*/ SHF.R.S32.HI R15, RZ, 0x1, R15 ; /* 0x00000001ff0f7819 */
/* 0x000fca000001140f */
/*1070*/ IMAD.IADD R14, R14, 0x1, -R15 ; /* 0x000000010e0e7824 */
/* 0x000fe400078e0a0f */
/*1080*/ IMAD R17, R15, 0x100000, R17 ; /* 0x001000000f117824 */
/* 0x000fc600078e0211 */
/*1090*/ LEA R19, R14, 0x3ff00000, 0x14 ; /* 0x3ff000000e137811 */
/* 0x000fcc00078ea0ff */
/*10a0*/ DMUL R18, R16, R18 ; /* 0x0000001210127228 */
/* 0x0000540000000000 */
/*10b0*/ LOP3.LUT R14, R19, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff130e7812 */
/* 0x002fe200078ec0ff */
/*10c0*/ DADD R12, R22, -R12 ; /* 0x00000000160c7229 */
/* 0x000e62000000080c */
/*10d0*/ IMAD.MOV.U32 R29, RZ, RZ, 0x0 ; /* 0x00000000ff1d7424 */
/* 0x000fe400078e00ff */
/*10e0*/ ISETP.NE.AND P0, PT, R14, 0x7ff00000, PT ; /* 0x7ff000000e00780c */
/* 0x000fc60003f05270 */
/*10f0*/ DADD R12, R20, R12 ; /* 0x00000000140c7229 */
/* 0x002e62000000000c */
/*1100*/ ISETP.EQ.AND P0, PT, R18, RZ, !P0 ; /* 0x000000ff1200720c */
/* 0x000fda0004702270 */
/*1110*/ @!P0 DFMA R18, R12, R18, R18 ; /* 0x000000120c12822b */
/* 0x0022a20000000012 */
/*1120*/ RET.REL.NODEC R28 0x0 ; /* 0xffffeed01c007950 */
/* 0x000ff40003c3ffff */
/*1130*/ BRA 0x1130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* jegood Joshua Good */
/**
* @file p3.cu
* Calculates the minimum distance for a set of file-specified points using GPU
* multi-threading. This program requires access to a CUDA-enabled GPU (i.e. NVIDIA
* graphics card).
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <limits.h>
#include <math.h>
#include <time.h>
/** Maximum number of threads per block */
#define MAX_THRDS 1024
// Point struct
struct point{
int x;
int y;
int index;
double minDistance;
}typedef Point;
/**
* Calculates the minimum distance for this point from each point
* in the points array.
* @param points the point array
* @param numPoints number of points in the point array
*/
__global__ void calcMinDist(Point *points, int numPoints)
{
// Compute the minimum distance for each point in the point array
for(int i = 0; i < numPoints; i++){
// Ensure we don't calculate the distance to a point from itself
if(i != points[blockIdx.x].index){
double distance = sqrt(pow((double)(points[i].x - points[blockIdx.x].x), 2) + pow((double)(points[i].y - points[blockIdx.x].y), 2));
// Check if distance is a new minimum distance for this point
if(distance < points[blockIdx.x].minDistance){
points[blockIdx.x].minDistance = distance;
}
}
}
}
/**
* Calculates the minimum distance for a set of file-specified points using a CUDA
* kernel function. Reports this information and its associated minimum distance points
* alongside the time taken to complete this process.
* @param argc number of command line arguments
* @param argv list of command of line arguments
*/
int main(int argc, char *argv[])
{
FILE *fp;
// Ensure a valid file is given
if(!(fp = fopen(argv[1], "r"))){
printf("Usage: ./p3 <input file>\n");
exit(EXIT_FAILURE);
}
/** Start time for a process */
clock_t start;
/** End time for a process */
clock_t finish;
// Start process clock
start = clock();
// Initially loop through and calculate the number of points in the file
Point p;
/** Number of points in the file */
int numPoints = 0;
while(fscanf(fp, "%d%d", &p.x, &p.y) == 2){ // read, but don't store(*)
numPoints++;
}
// Rewind the file and assign points in the array of points
rewind(fp);
/** Index of point in points array */
int index = 0;
Point points[numPoints];
for(int i = 0; i < numPoints; i++){
// Scan in next point
fscanf(fp, "%d %d", &p.x, &p.y);
p.index = index;
p.minDistance = INFINITY;
points[i] = p;
index++;
}
// Allocate memory for kernel threads
double minDist = INFINITY;
Point *arr_p;
int size = numPoints * sizeof(Point);
cudaMalloc((void**)&arr_p, size);
cudaMemcpy(arr_p, points, size, cudaMemcpyHostToDevice);
// Launch the kernel to do work
// Runs numPoints blocks with one thread each
calcMinDist<<<numPoints, 1>>>(arr_p, numPoints);
// Use result on host
cudaMemcpy(points, arr_p, size, cudaMemcpyDeviceToHost);
// Determine minDist for these points
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance < minDist){
minDist = points[i].minDistance;
}
}
// Determine which points have minimum distance
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance == minDist){
printf("(%d,%d)", points[i].x, points[i].y);
}
}
// Print the minimum distance for the set of points
printf("%lf\n", minDist);
// End process time
finish = clock();
// Print the process time
printf("Time : %lf seconds\n", (double) (finish - start) / CLOCKS_PER_SEC);
// Free memory
cudaFree(arr_p);
// Return EXIT_SUCCESS
return 0;
} | .file "tmpxft_0017bcb6_00000000-6_p3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11calcMinDistP5pointiP5pointi
.type _Z37__device_stub__Z11calcMinDistP5pointiP5pointi, @function
_Z37__device_stub__Z11calcMinDistP5pointiP5pointi:
.LFB2095:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11calcMinDistP5pointi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z37__device_stub__Z11calcMinDistP5pointiP5pointi, .-_Z37__device_stub__Z11calcMinDistP5pointiP5pointi
.globl _Z11calcMinDistP5pointi
.type _Z11calcMinDistP5pointi, @function
_Z11calcMinDistP5pointi:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11calcMinDistP5pointiP5pointi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z11calcMinDistP5pointi, .-_Z11calcMinDistP5pointi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "Usage: ./p3 <input file>\n"
.LC3:
.string "%d%d"
.LC4:
.string "%d %d"
.LC5:
.string "(%d,%d)"
.LC6:
.string "%lf\n"
.LC8:
.string "Time : %lf seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq 8(%rsi), %rdi
leaq .LC1(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L35
movq %rax, %r14
call clock@PLT
movq %rax, -144(%rbp)
movl $0, %r13d
leaq .LC3(%rip), %rbx
jmp .L13
.L35:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L14:
addl $1, %r13d
.L13:
leaq -80(%rbp), %rdx
leaq -76(%rbp), %rcx
movq %rbx, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
je .L14
movq %r14, %rdi
call rewind@PLT
movslq %r13d, %rax
leaq (%rax,%rax,2), %rdx
leaq 0(,%rdx,8), %rsi
movq %rsi, -136(%rbp)
leaq 15(%rsi), %rdx
movq %rdx, %rsi
andq $-16, %rsi
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L15:
cmpq %rcx, %rsp
je .L16
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L15
.L16:
movq %rsi, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L17
orq $0, -8(%rsp,%rdx)
.L17:
movq %rsp, %r12
movq %r12, -128(%rbp)
testl %r13d, %r13d
jle .L18
movl $0, %ebx
leaq -80(%rbp), %r15
leaq -76(%rbp), %rdi
movq %rdi, -120(%rbp)
movq %rax, -152(%rbp)
.L19:
movq -120(%rbp), %rcx
movq %r15, %rdx
leaq .LC4(%rip), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %ebx, -72(%rbp)
movq .LC0(%rip), %rax
movq %rax, -64(%rbp)
movdqa -80(%rbp), %xmm2
movups %xmm2, (%r12)
movabsq $9218868437227405312, %rax
movq %rax, 16(%r12)
addl $1, %ebx
addq $24, %r12
cmpl %ebx, %r13d
jne .L19
movq -152(%rbp), %rax
.L18:
leal (%rax,%rax,2), %ebx
sall $3, %ebx
movslq %ebx, %rbx
leaq -112(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -128(%rbp), %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, -92(%rbp)
movl $1, -88(%rbp)
movl $1, -84(%rbp)
movl %r13d, -104(%rbp)
movl $1, -100(%rbp)
movl $1, -96(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -92(%rbp), %rdx
movl $1, %ecx
movq -104(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L20:
movl $2, %ecx
movq %rbx, %rdx
movq -112(%rbp), %rsi
movq -128(%rbp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L28
leaq 16(%rbx), %rax
movq -136(%rbp), %rsi
leaq 16(%rbx,%rsi), %rdx
movsd .LC0(%rip), %xmm4
movsd %xmm4, -120(%rbp)
.L23:
movsd (%rax), %xmm0
minsd -120(%rbp), %xmm0
movsd %xmm0, -120(%rbp)
addq $24, %rax
cmpq %rdx, %rax
jne .L23
movq -128(%rbp), %r12
movq -136(%rbp), %rax
addq %rax, %r12
leaq .LC5(%rip), %r13
jmp .L26
.L36:
movl %r13d, %esi
movq -112(%rbp), %rdi
call _Z37__device_stub__Z11calcMinDistP5pointiP5pointi
jmp .L20
.L37:
movl 4(%rbx), %ecx
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L24:
addq $24, %rbx
cmpq %r12, %rbx
je .L21
.L26:
movsd -120(%rbp), %xmm1
ucomisd 16(%rbx), %xmm1
jp .L24
jne .L24
jmp .L37
.L28:
movsd .LC0(%rip), %xmm5
movsd %xmm5, -120(%rbp)
.L21:
movsd -120(%rbp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq -144(%rbp), %rdi
subq %rdi, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z11calcMinDistP5pointi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calcMinDistP5pointi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 2146435072
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* jegood Joshua Good */
/**
* @file p3.cu
* Calculates the minimum distance for a set of file-specified points using GPU
* multi-threading. This program requires access to a CUDA-enabled GPU (i.e. NVIDIA
* graphics card).
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <limits.h>
#include <math.h>
#include <time.h>
/** Maximum number of threads per block */
#define MAX_THRDS 1024
// Point struct
struct point{
int x;
int y;
int index;
double minDistance;
}typedef Point;
/**
* Calculates the minimum distance for this point from each point
* in the points array.
* @param points the point array
* @param numPoints number of points in the point array
*/
__global__ void calcMinDist(Point *points, int numPoints)
{
// Compute the minimum distance for each point in the point array
for(int i = 0; i < numPoints; i++){
// Ensure we don't calculate the distance to a point from itself
if(i != points[blockIdx.x].index){
double distance = sqrt(pow((double)(points[i].x - points[blockIdx.x].x), 2) + pow((double)(points[i].y - points[blockIdx.x].y), 2));
// Check if distance is a new minimum distance for this point
if(distance < points[blockIdx.x].minDistance){
points[blockIdx.x].minDistance = distance;
}
}
}
}
/**
* Calculates the minimum distance for a set of file-specified points using a CUDA
* kernel function. Reports this information and its associated minimum distance points
* alongside the time taken to complete this process.
* @param argc number of command line arguments
* @param argv list of command of line arguments
*/
int main(int argc, char *argv[])
{
FILE *fp;
// Ensure a valid file is given
if(!(fp = fopen(argv[1], "r"))){
printf("Usage: ./p3 <input file>\n");
exit(EXIT_FAILURE);
}
/** Start time for a process */
clock_t start;
/** End time for a process */
clock_t finish;
// Start process clock
start = clock();
// Initially loop through and calculate the number of points in the file
Point p;
/** Number of points in the file */
int numPoints = 0;
while(fscanf(fp, "%d%d", &p.x, &p.y) == 2){ // read, but don't store(*)
numPoints++;
}
// Rewind the file and assign points in the array of points
rewind(fp);
/** Index of point in points array */
int index = 0;
Point points[numPoints];
for(int i = 0; i < numPoints; i++){
// Scan in next point
fscanf(fp, "%d %d", &p.x, &p.y);
p.index = index;
p.minDistance = INFINITY;
points[i] = p;
index++;
}
// Allocate memory for kernel threads
double minDist = INFINITY;
Point *arr_p;
int size = numPoints * sizeof(Point);
cudaMalloc((void**)&arr_p, size);
cudaMemcpy(arr_p, points, size, cudaMemcpyHostToDevice);
// Launch the kernel to do work
// Runs numPoints blocks with one thread each
calcMinDist<<<numPoints, 1>>>(arr_p, numPoints);
// Use result on host
cudaMemcpy(points, arr_p, size, cudaMemcpyDeviceToHost);
// Determine minDist for these points
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance < minDist){
minDist = points[i].minDistance;
}
}
// Determine which points have minimum distance
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance == minDist){
printf("(%d,%d)", points[i].x, points[i].y);
}
}
// Print the minimum distance for the set of points
printf("%lf\n", minDist);
// End process time
finish = clock();
// Print the process time
printf("Time : %lf seconds\n", (double) (finish - start) / CLOCKS_PER_SEC);
// Free memory
cudaFree(arr_p);
// Return EXIT_SUCCESS
return 0;
} | /* jegood Joshua Good */
/**
* @file p3.cu
* Calculates the minimum distance for a set of file-specified points using GPU
* multi-threading. This program requires access to a CUDA-enabled GPU (i.e. NVIDIA
* graphics card).
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <limits.h>
#include <math.h>
#include <time.h>
/** Maximum number of threads per block */
#define MAX_THRDS 1024
// Point struct
struct point{
int x;
int y;
int index;
double minDistance;
}typedef Point;
/**
* Calculates the minimum distance for this point from each point
* in the points array.
* @param points the point array
* @param numPoints number of points in the point array
*/
__global__ void calcMinDist(Point *points, int numPoints)
{
// Compute the minimum distance for each point in the point array
for(int i = 0; i < numPoints; i++){
// Ensure we don't calculate the distance to a point from itself
if(i != points[blockIdx.x].index){
double distance = sqrt(pow((double)(points[i].x - points[blockIdx.x].x), 2) + pow((double)(points[i].y - points[blockIdx.x].y), 2));
// Check if distance is a new minimum distance for this point
if(distance < points[blockIdx.x].minDistance){
points[blockIdx.x].minDistance = distance;
}
}
}
}
/**
* Calculates the minimum distance for a set of file-specified points using a CUDA
* kernel function. Reports this information and its associated minimum distance points
* alongside the time taken to complete this process.
* @param argc number of command line arguments
* @param argv list of command of line arguments
*/
int main(int argc, char *argv[])
{
FILE *fp;
// Ensure a valid file is given
if(!(fp = fopen(argv[1], "r"))){
printf("Usage: ./p3 <input file>\n");
exit(EXIT_FAILURE);
}
/** Start time for a process */
clock_t start;
/** End time for a process */
clock_t finish;
// Start process clock
start = clock();
// Initially loop through and calculate the number of points in the file
Point p;
/** Number of points in the file */
int numPoints = 0;
while(fscanf(fp, "%d%d", &p.x, &p.y) == 2){ // read, but don't store(*)
numPoints++;
}
// Rewind the file and assign points in the array of points
rewind(fp);
/** Index of point in points array */
int index = 0;
Point points[numPoints];
for(int i = 0; i < numPoints; i++){
// Scan in next point
fscanf(fp, "%d %d", &p.x, &p.y);
p.index = index;
p.minDistance = INFINITY;
points[i] = p;
index++;
}
// Allocate memory for kernel threads
double minDist = INFINITY;
Point *arr_p;
int size = numPoints * sizeof(Point);
hipMalloc((void**)&arr_p, size);
hipMemcpy(arr_p, points, size, hipMemcpyHostToDevice);
// Launch the kernel to do work
// Runs numPoints blocks with one thread each
calcMinDist<<<numPoints, 1>>>(arr_p, numPoints);
// Use result on host
hipMemcpy(points, arr_p, size, hipMemcpyDeviceToHost);
// Determine minDist for these points
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance < minDist){
minDist = points[i].minDistance;
}
}
// Determine which points have minimum distance
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance == minDist){
printf("(%d,%d)", points[i].x, points[i].y);
}
}
// Print the minimum distance for the set of points
printf("%lf\n", minDist);
// End process time
finish = clock();
// Print the process time
printf("Time : %lf seconds\n", (double) (finish - start) / CLOCKS_PER_SEC);
// Free memory
hipFree(arr_p);
// Return EXIT_SUCCESS
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* jegood Joshua Good */
/**
* @file p3.cu
* Calculates the minimum distance for a set of file-specified points using GPU
* multi-threading. This program requires access to a CUDA-enabled GPU (i.e. NVIDIA
* graphics card).
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <limits.h>
#include <math.h>
#include <time.h>
/** Maximum number of threads per block */
#define MAX_THRDS 1024
// Point struct
struct point{
int x;
int y;
int index;
double minDistance;
}typedef Point;
/**
* Calculates the minimum distance for this point from each point
* in the points array.
* @param points the point array
* @param numPoints number of points in the point array
*/
__global__ void calcMinDist(Point *points, int numPoints)
{
// Compute the minimum distance for each point in the point array
for(int i = 0; i < numPoints; i++){
// Ensure we don't calculate the distance to a point from itself
if(i != points[blockIdx.x].index){
double distance = sqrt(pow((double)(points[i].x - points[blockIdx.x].x), 2) + pow((double)(points[i].y - points[blockIdx.x].y), 2));
// Check if distance is a new minimum distance for this point
if(distance < points[blockIdx.x].minDistance){
points[blockIdx.x].minDistance = distance;
}
}
}
}
/**
* Calculates the minimum distance for a set of file-specified points using a CUDA
* kernel function. Reports this information and its associated minimum distance points
* alongside the time taken to complete this process.
* @param argc number of command line arguments
* @param argv list of command of line arguments
*/
int main(int argc, char *argv[])
{
FILE *fp;
// Ensure a valid file is given
if(!(fp = fopen(argv[1], "r"))){
printf("Usage: ./p3 <input file>\n");
exit(EXIT_FAILURE);
}
/** Start time for a process */
clock_t start;
/** End time for a process */
clock_t finish;
// Start process clock
start = clock();
// Initially loop through and calculate the number of points in the file
Point p;
/** Number of points in the file */
int numPoints = 0;
while(fscanf(fp, "%d%d", &p.x, &p.y) == 2){ // read, but don't store(*)
numPoints++;
}
// Rewind the file and assign points in the array of points
rewind(fp);
/** Index of point in points array */
int index = 0;
Point points[numPoints];
for(int i = 0; i < numPoints; i++){
// Scan in next point
fscanf(fp, "%d %d", &p.x, &p.y);
p.index = index;
p.minDistance = INFINITY;
points[i] = p;
index++;
}
// Allocate memory for kernel threads
double minDist = INFINITY;
Point *arr_p;
int size = numPoints * sizeof(Point);
hipMalloc((void**)&arr_p, size);
hipMemcpy(arr_p, points, size, hipMemcpyHostToDevice);
// Launch the kernel to do work
// Runs numPoints blocks with one thread each
calcMinDist<<<numPoints, 1>>>(arr_p, numPoints);
// Use result on host
hipMemcpy(points, arr_p, size, hipMemcpyDeviceToHost);
// Determine minDist for these points
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance < minDist){
minDist = points[i].minDistance;
}
}
// Determine which points have minimum distance
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance == minDist){
printf("(%d,%d)", points[i].x, points[i].y);
}
}
// Print the minimum distance for the set of points
printf("%lf\n", minDist);
// End process time
finish = clock();
// Print the process time
printf("Time : %lf seconds\n", (double) (finish - start) / CLOCKS_PER_SEC);
// Free memory
hipFree(arr_p);
// Return EXIT_SUCCESS
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11calcMinDistP5pointi
.globl _Z11calcMinDistP5pointi
.p2align 8
.type _Z11calcMinDistP5pointi,@function
_Z11calcMinDistP5pointi:
s_load_b32 s33, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s33, 1
s_cbranch_scc1 .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
s_mul_i32 s3, s15, 24
s_mul_hi_u32 s2, s15, 24
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0x3fe55555
s_mov_b32 s4, 0x55555555
s_mov_b32 s7, 0x3fba6564
s_mov_b32 s6, 0x968915a9
s_mov_b32 s9, 0x3fbdee67
s_mov_b32 s8, 0x4222de17
s_mov_b32 s11, 0x3fbe25e4
s_mov_b32 s10, 0x3abe935a
s_mov_b32 s13, 0x3fc110ef
s_mov_b32 s12, 0x47e6c9c2
s_mov_b32 s15, 0x3fc3b13b
s_mov_b32 s14, 0xcfa74449
s_mov_b32 s17, 0x3fc745d1
s_mov_b32 s16, 0x71bf3c30
s_mov_b32 s19, 0x3fcc71c7
s_mov_b32 s18, 0x1c7792ce
s_waitcnt lgkmcnt(0)
s_add_u32 s20, s0, s3
s_addc_u32 s21, s1, s2
s_add_u32 s22, s20, 4
s_load_b32 s66, s[20:21], 0x8
s_addc_u32 s23, s21, 0
s_add_u32 s24, s20, 16
s_addc_u32 s25, s21, 0
s_add_u32 s26, s0, 4
s_addc_u32 s27, s1, 0
s_mov_b32 s29, 0x3fd24924
s_mov_b32 s28, 0x924920da
s_mov_b32 s31, 0x3fd99999
s_mov_b32 s30, 0x9999999c
s_mov_b32 s35, 0x3fe62e42
s_mov_b32 s34, 0xfefa39ef
s_mov_b32 s37, 0x3c7abc9e
s_mov_b32 s36, 0x3b39803f
s_mov_b32 s3, 0xbfe55555
s_mov_b32 s39, 0x3c8543b0
s_mov_b32 s38, 0xd5df274d
s_mov_b32 s41, 0x3ff71547
s_mov_b32 s40, 0x652b82fe
s_mov_b32 s43, 0xbfe62e42
s_mov_b32 s45, 0xbc7abc9e
s_mov_b32 s47, 0x3e928af3
s_mov_b32 s46, 0xfca7ab0c
s_mov_b32 s49, 0x3e5ade15
s_mov_b32 s48, 0x6a5dcb37
s_mov_b32 s51, 0x3ec71dee
s_mov_b32 s50, 0x623fde64
s_mov_b32 s53, 0x3efa0199
s_mov_b32 s52, 0x7c89e6b0
s_mov_b32 s55, 0x3f2a01a0
s_mov_b32 s54, 0x14761f6e
s_mov_b32 s57, 0x3f56c16c
s_mov_b32 s56, 0x1852b7b0
s_mov_b32 s59, 0x3f811111
s_mov_b32 s58, 0x11122322
s_mov_b32 s61, 0x3fa55555
s_mov_b32 s60, 0x555502a1
s_mov_b32 s63, 0x3fc55555
s_mov_b32 s62, 0x55555511
s_mov_b32 s65, 0x3fe00000
s_mov_b32 s64, 11
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s33, s33, -1
s_add_i32 s66, s66, -1
s_add_u32 s26, s26, 24
s_addc_u32 s27, s27, 0
s_cmp_eq_u32 s33, 0
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s66, 0
s_cbranch_scc1 .LBB0_2
s_add_u32 s0, s26, -4
s_addc_u32 s1, s27, -1
s_mov_b32 s2, s4
s_load_b32 s67, s[0:1], 0x0
s_clause 0x1
s_load_b32 s68, s[20:21], 0x0
s_load_b32 s69, s[22:23], 0x0
s_mov_b32 s42, s34
s_mov_b32 s44, s36
s_load_b32 s70, s[26:27], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s0, s67, s68
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[0:1], s0
v_frexp_mant_f64_e64 v[3:4], |v[0:1]|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[3:4]
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
v_ldexp_f64 v[3:4], v[3:4], v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[3:4], 1.0
v_add_f64 v[11:12], v[3:4], -1.0
v_rcp_f64_e32 v[7:8], v[5:6]
v_add_f64 v[13:14], v[5:6], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], -v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[11:12], v[7:8]
v_mul_f64 v[15:16], v[5:6], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[9:10], v[5:6], -v[15:16]
v_fma_f64 v[3:4], v[9:10], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[15:16], v[3:4]
v_add_f64 v[13:14], v[11:12], -v[5:6]
v_add_f64 v[15:16], v[5:6], -v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[11:12], -v[13:14]
v_add_f64 v[3:4], v[15:16], -v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[11:12], -v[5:6]
v_add_f64 v[3:4], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[13:14], v[3:4]
v_mul_f64 v[3:4], v[7:8], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[9:10], v[3:4]
v_add_f64 v[7:8], v[5:6], -v[9:10]
v_mul_f64 v[9:10], v[5:6], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[3:4], -v[7:8]
v_fma_f64 v[7:8], v[5:6], v[5:6], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[11:12], v[3:4], v[3:4]
v_fma_f64 v[7:8], v[5:6], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[11:12], v[9:10], v[7:8]
v_fma_f64 v[13:14], v[11:12], s[8:9], s[6:7]
v_add_f64 v[9:10], v[11:12], -v[9:10]
v_mul_f64 v[19:20], v[5:6], v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[10:11]
v_add_f64 v[7:8], v[7:8], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[12:13]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[16:17]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[28:29]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[30:31]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[11:12], v[13:14]
v_fma_f64 v[9:10], v[11:12], v[13:14], -v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[7:8], v[13:14], v[9:10]
v_add_f64 v[13:14], v[15:16], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[17:18], v[13:14], s[4:5]
v_add_f64 v[15:16], v[13:14], -v[15:16]
v_add_f64 v[21:22], v[17:18], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[9:10], -v[15:16]
v_fma_f64 v[15:16], v[11:12], v[5:6], -v[19:20]
v_add_f64 v[13:14], v[13:14], -v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[9:10], s[38:39]
v_fma_f64 v[11:12], v[11:12], v[3:4], v[15:16]
v_ldexp_f64 v[3:4], v[3:4], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[9:10], v[13:14]
v_fma_f64 v[7:8], v[7:8], v[5:6], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[17:18], v[9:10]
v_add_f64 v[13:14], v[19:20], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[15:16], v[17:18], -v[11:12]
v_mul_f64 v[17:18], v[13:14], v[11:12]
v_add_f64 v[19:20], v[13:14], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[9:10], v[15:16]
v_fma_f64 v[15:16], v[13:14], v[11:12], -v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[7:8], -v[19:20]
v_fma_f64 v[9:10], v[13:14], v[9:10], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[7:8], v[7:8], v[11:12], v[9:10]
v_frexp_exp_i32_f64_e32 v9, v[0:1]
v_ldexp_f64 v[0:1], v[5:6], 1
v_add_f64 v[5:6], v[17:18], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
v_cvt_f64_i32_e32 v[9:10], v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[0:1], v[5:6]
v_add_f64 v[13:14], v[5:6], -v[17:18]
v_mul_f64 v[15:16], v[9:10], s[34:35]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[0:1], v[11:12], -v[0:1]
v_add_f64 v[7:8], v[7:8], -v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[13:14], v[9:10], s[34:35], -v[15:16]
v_add_f64 v[0:1], v[5:6], -v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[3:4], v[3:4], v[7:8]
v_fma_f64 v[5:6], v[9:10], s[36:37], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[3:4], v[0:1]
v_add_f64 v[3:4], v[15:16], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[11:12], v[0:1]
v_add_f64 v[15:16], v[3:4], -v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[3:4], v[7:8]
v_add_f64 v[11:12], v[7:8], -v[11:12]
v_add_f64 v[5:6], v[5:6], -v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[13:14], v[9:10], -v[3:4]
v_add_f64 v[0:1], v[0:1], -v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[17:18], v[9:10], -v[13:14]
v_add_f64 v[7:8], v[7:8], -v[13:14]
v_add_f64 v[11:12], v[5:6], v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], -v[17:18]
v_add_f64 v[3:4], v[7:8], v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[11:12], -v[5:6]
v_add_f64 v[3:4], v[11:12], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], -v[7:8]
v_add_f64 v[0:1], v[0:1], -v[7:8]
v_add_f64 v[13:14], v[9:10], v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[11:12]
v_add_f64 v[7:8], v[13:14], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[0:1], v[5:6]
v_add_f64 v[3:4], v[3:4], -v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[3:4]
v_add_f64 v[3:4], v[13:14], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[3:4], -v[13:14]
v_add_f64 v[7:8], v[3:4], v[3:4]
v_add_f64 v[0:1], v[0:1], -v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[3:4], v[3:4], 2.0, -v[7:8]
v_cmp_class_f64_e64 vcc_lo, v[7:8], 0x204
v_fma_f64 v[0:1], v[0:1], 2.0, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[7:8], v[0:1]
v_dual_cndmask_b32 v6, v4, v8 :: v_dual_cndmask_b32 v5, v3, v7
v_add_f64 v[3:4], v[3:4], -v[7:8]
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[9:10], v[5:6], s[40:41]
v_cmp_nlt_f64_e64 s0, 0x40900000, v[5:6]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[5:6]|
v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[5:6]
v_add_f64 v[0:1], v[0:1], -v[3:4]
v_rndne_f64_e32 v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
s_and_b32 vcc_lo, s1, s0
s_cmp_lg_u32 s67, s68
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[11:12], v[9:10], s[42:43], v[5:6]
v_cvt_i32_f64_e32 v15, v[9:10]
v_fma_f64 v[11:12], v[9:10], s[44:45], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], s[48:49], s[46:47]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[50:51]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[52:53]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[54:55]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[56:57]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[58:59]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[60:61]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[62:63]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[64:65]
v_fma_f64 v[13:14], v[11:12], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[11:12], v[13:14], 1.0
v_ldexp_f64 v[7:8], v[9:10], v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, 0x7ff00000, v8, s0
v_cndmask_b32_e64 v4, 0, v3, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, 0, v7, vcc_lo
v_fma_f64 v[0:1], v[3:4], v[0:1], v[3:4]
v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_dual_cndmask_b32 v24, v1, v4 :: v_dual_cndmask_b32 v23, v0, v3
s_cselect_b32 vcc_lo, -1, 0
s_sub_i32 s0, s70, s69
v_cvt_f64_i32_e32 v[0:1], s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e64 v[3:4], |v[0:1]|
v_cmp_gt_f64_e64 s0, s[4:5], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0, 1, s0
v_ldexp_f64 v[3:4], v[3:4], v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[3:4], 1.0
v_add_f64 v[11:12], v[3:4], -1.0
v_rcp_f64_e32 v[7:8], v[5:6]
v_add_f64 v[13:14], v[5:6], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], -v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[11:12], v[7:8]
v_mul_f64 v[15:16], v[5:6], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[9:10], v[5:6], -v[15:16]
v_fma_f64 v[3:4], v[9:10], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[15:16], v[3:4]
v_add_f64 v[13:14], v[11:12], -v[5:6]
v_add_f64 v[15:16], v[5:6], -v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[11:12], -v[13:14]
v_add_f64 v[3:4], v[15:16], -v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[11:12], -v[5:6]
v_add_f64 v[3:4], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[13:14], v[3:4]
v_mul_f64 v[3:4], v[7:8], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[9:10], v[3:4]
v_add_f64 v[7:8], v[5:6], -v[9:10]
v_mul_f64 v[9:10], v[5:6], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[3:4], -v[7:8]
v_fma_f64 v[7:8], v[5:6], v[5:6], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[11:12], v[3:4], v[3:4]
v_fma_f64 v[7:8], v[5:6], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[11:12], v[9:10], v[7:8]
v_fma_f64 v[13:14], v[11:12], s[8:9], s[6:7]
v_add_f64 v[9:10], v[11:12], -v[9:10]
v_mul_f64 v[19:20], v[5:6], v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[10:11]
v_add_f64 v[7:8], v[7:8], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[12:13]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[16:17]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[28:29]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[30:31]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[11:12], v[13:14]
v_fma_f64 v[9:10], v[11:12], v[13:14], -v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[7:8], v[13:14], v[9:10]
v_add_f64 v[13:14], v[15:16], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[17:18], v[13:14], s[4:5]
v_add_f64 v[15:16], v[13:14], -v[15:16]
v_add_f64 v[21:22], v[17:18], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[9:10], -v[15:16]
v_fma_f64 v[15:16], v[11:12], v[5:6], -v[19:20]
v_add_f64 v[13:14], v[13:14], -v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[9:10], s[38:39]
v_fma_f64 v[11:12], v[11:12], v[3:4], v[15:16]
v_ldexp_f64 v[3:4], v[3:4], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[9:10], v[13:14]
v_fma_f64 v[7:8], v[7:8], v[5:6], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[17:18], v[9:10]
v_add_f64 v[13:14], v[19:20], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[15:16], v[17:18], -v[11:12]
v_mul_f64 v[17:18], v[13:14], v[11:12]
v_add_f64 v[19:20], v[13:14], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[9:10], v[15:16]
v_fma_f64 v[15:16], v[13:14], v[11:12], -v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[7:8], -v[19:20]
v_fma_f64 v[9:10], v[13:14], v[9:10], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[7:8], v[7:8], v[11:12], v[9:10]
v_frexp_exp_i32_f64_e32 v9, v[0:1]
v_ldexp_f64 v[0:1], v[5:6], 1
v_add_f64 v[5:6], v[17:18], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e64 v9, s0, 0, v9, s0
v_cvt_f64_i32_e32 v[9:10], v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[0:1], v[5:6]
v_add_f64 v[13:14], v[5:6], -v[17:18]
v_mul_f64 v[15:16], v[9:10], s[34:35]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[0:1], v[11:12], -v[0:1]
v_add_f64 v[7:8], v[7:8], -v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[13:14], v[9:10], s[34:35], -v[15:16]
v_add_f64 v[0:1], v[5:6], -v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[3:4], v[3:4], v[7:8]
v_fma_f64 v[5:6], v[9:10], s[36:37], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[3:4], v[0:1]
v_add_f64 v[3:4], v[15:16], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[11:12], v[0:1]
v_add_f64 v[15:16], v[3:4], -v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[3:4], v[7:8]
v_add_f64 v[11:12], v[7:8], -v[11:12]
v_add_f64 v[5:6], v[5:6], -v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[13:14], v[9:10], -v[3:4]
v_add_f64 v[0:1], v[0:1], -v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[17:18], v[9:10], -v[13:14]
v_add_f64 v[7:8], v[7:8], -v[13:14]
v_add_f64 v[11:12], v[5:6], v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], -v[17:18]
v_add_f64 v[3:4], v[7:8], v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[11:12], -v[5:6]
v_add_f64 v[3:4], v[11:12], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], -v[7:8]
v_add_f64 v[0:1], v[0:1], -v[7:8]
v_add_f64 v[13:14], v[9:10], v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[11:12]
v_add_f64 v[7:8], v[13:14], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[0:1], v[5:6]
v_add_f64 v[3:4], v[3:4], -v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[3:4]
v_add_f64 v[3:4], v[13:14], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[3:4], -v[13:14]
v_add_f64 v[7:8], v[3:4], v[3:4]
v_add_f64 v[0:1], v[0:1], -v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[3:4], v[3:4], 2.0, -v[7:8]
v_cmp_class_f64_e64 s0, v[7:8], 0x204
v_fma_f64 v[0:1], v[0:1], 2.0, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[7:8], v[0:1]
v_cndmask_b32_e64 v6, v4, v8, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, v3, v7, s0
v_add_f64 v[3:4], v[3:4], -v[7:8]
v_mul_f64 v[9:10], v[5:6], s[40:41]
v_cmp_nlt_f64_e64 s1, 0x40900000, v[5:6]
v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[5:6]|
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[5:6]
v_add_f64 v[0:1], v[0:1], -v[3:4]
v_rndne_f64_e32 v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, 0, v1, s0
v_cndmask_b32_e64 v0, 0, v0, s0
s_and_b32 s0, s2, s1
s_cmp_lg_u32 s70, s69
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[9:10], s[42:43], v[5:6]
v_cvt_i32_f64_e32 v15, v[9:10]
global_load_b64 v[5:6], v2, s[24:25]
v_fma_f64 v[11:12], v[9:10], s[44:45], v[11:12]
v_fma_f64 v[13:14], v[11:12], s[48:49], s[46:47]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[50:51]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[52:53]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[54:55]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[56:57]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[58:59]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[60:61]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], s[62:63]
v_fma_f64 v[13:14], v[11:12], v[13:14], s[64:65]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[11:12], v[13:14], 1.0
v_fma_f64 v[9:10], v[11:12], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[7:8], v[9:10], v15
v_cndmask_b32_e64 v3, 0x7ff00000, v8, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, 0, v3, s2
v_cndmask_b32_e64 v3, 0, v7, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[3:4], v[0:1], v[3:4]
v_cmp_class_f64_e64 s0, v[3:4], 0x204
v_cndmask_b32_e64 v3, v0, v3, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v1, v4, s0
v_dual_cndmask_b32 v1, 0, v24 :: v_dual_cndmask_b32 v0, 0, v23
s_cselect_b32 vcc_lo, -1, 0
v_dual_cndmask_b32 v4, 0, v4 :: v_dual_cndmask_b32 v3, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], |v[0:1]|, |v[3:4]|
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_and_b32 s0, vcc_lo, exec_lo
s_cselect_b32 s0, 0xffffff80, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 8, v3
v_ldexp_f64 v[0:1], v[0:1], v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[3:4], v[0:1]
v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[7:8], v[0:1], v[3:4]
v_mul_f64 v[3:4], v[3:4], 0.5
v_fma_f64 v[9:10], -v[3:4], v[7:8], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_fma_f64 v[3:4], v[3:4], v[9:10], v[3:4]
v_fma_f64 v[9:10], -v[7:8], v[7:8], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[9:10], v[3:4], v[7:8]
v_fma_f64 v[9:10], -v[7:8], v[7:8], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[9:10], v[3:4], v[7:8]
v_ldexp_f64 v[3:4], v[3:4], s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v4, v1 :: v_dual_cndmask_b32 v0, v3, v0
s_waitcnt vmcnt(0)
v_cmp_nlt_f64_e32 vcc_lo, v[0:1], v[5:6]
s_cbranch_vccnz .LBB0_2
global_store_b64 v2, v[0:1], s[24:25]
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11calcMinDistP5pointi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 71
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11calcMinDistP5pointi, .Lfunc_end0-_Z11calcMinDistP5pointi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11calcMinDistP5pointi
.private_segment_fixed_size: 0
.sgpr_count: 73
.sgpr_spill_count: 0
.symbol: _Z11calcMinDistP5pointi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* jegood Joshua Good */
/**
* @file p3.cu
* Calculates the minimum distance for a set of file-specified points using GPU
* multi-threading. This program requires access to a CUDA-enabled GPU (i.e. NVIDIA
* graphics card).
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <limits.h>
#include <math.h>
#include <time.h>
/** Maximum number of threads per block */
#define MAX_THRDS 1024
// Point struct
struct point{
int x;
int y;
int index;
double minDistance;
}typedef Point;
/**
* Calculates the minimum distance for this point from each point
* in the points array.
* @param points the point array
* @param numPoints number of points in the point array
*/
__global__ void calcMinDist(Point *points, int numPoints)
{
// Compute the minimum distance for each point in the point array
for(int i = 0; i < numPoints; i++){
// Ensure we don't calculate the distance to a point from itself
if(i != points[blockIdx.x].index){
double distance = sqrt(pow((double)(points[i].x - points[blockIdx.x].x), 2) + pow((double)(points[i].y - points[blockIdx.x].y), 2));
// Check if distance is a new minimum distance for this point
if(distance < points[blockIdx.x].minDistance){
points[blockIdx.x].minDistance = distance;
}
}
}
}
/**
* Calculates the minimum distance for a set of file-specified points using a CUDA
* kernel function. Reports this information and its associated minimum distance points
* alongside the time taken to complete this process.
* @param argc number of command line arguments
* @param argv list of command of line arguments
*/
int main(int argc, char *argv[])
{
FILE *fp;
// Ensure a valid file is given
if(!(fp = fopen(argv[1], "r"))){
printf("Usage: ./p3 <input file>\n");
exit(EXIT_FAILURE);
}
/** Start time for a process */
clock_t start;
/** End time for a process */
clock_t finish;
// Start process clock
start = clock();
// Initially loop through and calculate the number of points in the file
Point p;
/** Number of points in the file */
int numPoints = 0;
while(fscanf(fp, "%d%d", &p.x, &p.y) == 2){ // read, but don't store(*)
numPoints++;
}
// Rewind the file and assign points in the array of points
rewind(fp);
/** Index of point in points array */
int index = 0;
Point points[numPoints];
for(int i = 0; i < numPoints; i++){
// Scan in next point
fscanf(fp, "%d %d", &p.x, &p.y);
p.index = index;
p.minDistance = INFINITY;
points[i] = p;
index++;
}
// Allocate memory for kernel threads
double minDist = INFINITY;
Point *arr_p;
int size = numPoints * sizeof(Point);
hipMalloc((void**)&arr_p, size);
hipMemcpy(arr_p, points, size, hipMemcpyHostToDevice);
// Launch the kernel to do work
// Runs numPoints blocks with one thread each
calcMinDist<<<numPoints, 1>>>(arr_p, numPoints);
// Use result on host
hipMemcpy(points, arr_p, size, hipMemcpyDeviceToHost);
// Determine minDist for these points
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance < minDist){
minDist = points[i].minDistance;
}
}
// Determine which points have minimum distance
for(int i = 0; i < numPoints; i++){
if(points[i].minDistance == minDist){
printf("(%d,%d)", points[i].x, points[i].y);
}
}
// Print the minimum distance for the set of points
printf("%lf\n", minDist);
// End process time
finish = clock();
// Print the process time
printf("Time : %lf seconds\n", (double) (finish - start) / CLOCKS_PER_SEC);
// Free memory
hipFree(arr_p);
// Return EXIT_SUCCESS
return 0;
} | .text
.file "p3.hip"
.globl _Z26__device_stub__calcMinDistP5pointi # -- Begin function _Z26__device_stub__calcMinDistP5pointi
.p2align 4, 0x90
.type _Z26__device_stub__calcMinDistP5pointi,@function
_Z26__device_stub__calcMinDistP5pointi: # @_Z26__device_stub__calcMinDistP5pointi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11calcMinDistP5pointi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__calcMinDistP5pointi, .Lfunc_end0-_Z26__device_stub__calcMinDistP5pointi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x7ff0000000000000 # double +Inf
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $168, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq 8(%rsi), %rdi
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_18
# %bb.1:
movq %rax, %rbx
callq clock
movq %rax, -120(%rbp) # 8-byte Spill
movl $1, %r15d
movl $-24, %r13d
leaq -96(%rbp), %r14
movl $4294967295, %r12d # imm = 0xFFFFFFFF
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %r14, %rdx
leaq -92(%rbp), %rcx
xorl %eax, %eax
callq __isoc23_fscanf
decq %r15
addl $24, %r13d
incq %r12
cmpl $2, %eax
je .LBB1_2
# %bb.3:
movq %rbx, %rdi
callq rewind
movq %rsp, -112(%rbp) # 8-byte Spill
movq %r15, %rax
negq %rax
movq %rax, -72(%rbp) # 8-byte Spill
leaq (,%r15,8), %rax
leaq (%rax,%rax,2), %rax
movl $15, %ecx
subq %rax, %rcx
andq $-16, %rcx
movq %rsp, %rax
subq %rcx, %rax
movq %rax, -64(%rbp) # 8-byte Spill
movq %rax, %rsp
movq %r15, -104(%rbp) # 8-byte Spill
testl %r15d, %r15d
je .LBB1_6
# %bb.4: # %.lr.ph
movq %rbx, %r15
movq -64(%rbp), %r14 # 8-byte Reload
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r15, %rdi
leaq -96(%rbp), %rdx
leaq -92(%rbp), %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movl %ebx, -88(%rbp)
movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
movq %rax, -80(%rbp)
movq %rax, 16(%r14)
movq -96(%rbp), %rax
movq %rax, (%r14)
movl -88(%rbp), %eax
movl %eax, 8(%r14)
movl -84(%rbp), %eax
movl %eax, 12(%r14)
incq %rbx
addq $24, %r14
cmpq %rbx, -72(%rbp) # 8-byte Folded Reload
jne .LBB1_5
.LBB1_6: # %._crit_edge
movslq %r13d, %r13
leaq -48(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
movq -48(%rbp), %rdi
movq -64(%rbp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl $4294967295, %edx # imm = 0xFFFFFFFF
addq $2, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq -72(%rbp), %rbx # 8-byte Reload
jne .LBB1_8
# %bb.7:
movq -48(%rbp), %rax
movq %rax, -184(%rbp)
movl %ebx, -52(%rbp)
leaq -184(%rbp), %rax
movq %rax, -208(%rbp)
leaq -52(%rbp), %rax
movq %rax, -200(%rbp)
leaq -176(%rbp), %rdi
leaq -160(%rbp), %rsi
leaq -144(%rbp), %rdx
leaq -136(%rbp), %rcx
callq __hipPopCallConfiguration
movq -176(%rbp), %rsi
movl -168(%rbp), %edx
movq -160(%rbp), %rcx
movl -152(%rbp), %r8d
leaq -208(%rbp), %r9
movl $_Z11calcMinDistP5pointi, %edi
pushq -136(%rbp)
pushq -144(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_8:
movq -48(%rbp), %rsi
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq -104(%rbp), %rdx # 8-byte Reload
testl %edx, %edx
je .LBB1_9
# %bb.16: # %.lr.ph53.preheader
leaq 16(%r14), %rax
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
movq %rbx, %rcx
.p2align 4, 0x90
.LBB1_17: # %.lr.ph53
# =>This Inner Loop Header: Depth=1
movsd (%rax), %xmm0 # xmm0 = mem[0],zero
minsd %xmm1, %xmm0
addq $24, %rax
movapd %xmm0, %xmm1
decq %rcx
jne .LBB1_17
# %bb.10: # %.preheader
testl %edx, %edx
jne .LBB1_11
jmp .LBB1_15
.LBB1_9:
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
testl %edx, %edx
je .LBB1_15
.LBB1_11:
movsd %xmm0, -128(%rbp) # 8-byte Spill
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_12 Depth=1
addq $24, %r14
decq %rbx
je .LBB1_15
.LBB1_12: # %.lr.ph55
# =>This Inner Loop Header: Depth=1
movsd 16(%r14), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jne .LBB1_14
jp .LBB1_14
# %bb.13: # in Loop: Header=BB1_12 Depth=1
movl (%r14), %esi
movl 4(%r14), %edx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movsd -128(%rbp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jmp .LBB1_14
.LBB1_15: # %._crit_edge56
movl $.L.str.5, %edi
movb $1, %al
callq printf
callq clock
subq -120(%rbp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq -48(%rbp), %rdi
callq hipFree
movq -112(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_18:
.cfi_def_cfa %rbp, 16
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11calcMinDistP5pointi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11calcMinDistP5pointi,@object # @_Z11calcMinDistP5pointi
.section .rodata,"a",@progbits
.globl _Z11calcMinDistP5pointi
.p2align 3, 0x0
_Z11calcMinDistP5pointi:
.quad _Z26__device_stub__calcMinDistP5pointi
.size _Z11calcMinDistP5pointi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d%d"
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "(%d,%d)"
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%lf\n"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time : %lf seconds\n"
.size .L.str.6, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11calcMinDistP5pointi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: ./p3 <input file>"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__calcMinDistP5pointi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11calcMinDistP5pointi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017bcb6_00000000-6_p3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11calcMinDistP5pointiP5pointi
.type _Z37__device_stub__Z11calcMinDistP5pointiP5pointi, @function
_Z37__device_stub__Z11calcMinDistP5pointiP5pointi:
.LFB2095:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11calcMinDistP5pointi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z37__device_stub__Z11calcMinDistP5pointiP5pointi, .-_Z37__device_stub__Z11calcMinDistP5pointiP5pointi
.globl _Z11calcMinDistP5pointi
.type _Z11calcMinDistP5pointi, @function
_Z11calcMinDistP5pointi:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11calcMinDistP5pointiP5pointi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z11calcMinDistP5pointi, .-_Z11calcMinDistP5pointi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "Usage: ./p3 <input file>\n"
.LC3:
.string "%d%d"
.LC4:
.string "%d %d"
.LC5:
.string "(%d,%d)"
.LC6:
.string "%lf\n"
.LC8:
.string "Time : %lf seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq 8(%rsi), %rdi
leaq .LC1(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L35
movq %rax, %r14
call clock@PLT
movq %rax, -144(%rbp)
movl $0, %r13d
leaq .LC3(%rip), %rbx
jmp .L13
.L35:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L14:
addl $1, %r13d
.L13:
leaq -80(%rbp), %rdx
leaq -76(%rbp), %rcx
movq %rbx, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
je .L14
movq %r14, %rdi
call rewind@PLT
movslq %r13d, %rax
leaq (%rax,%rax,2), %rdx
leaq 0(,%rdx,8), %rsi
movq %rsi, -136(%rbp)
leaq 15(%rsi), %rdx
movq %rdx, %rsi
andq $-16, %rsi
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L15:
cmpq %rcx, %rsp
je .L16
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L15
.L16:
movq %rsi, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L17
orq $0, -8(%rsp,%rdx)
.L17:
movq %rsp, %r12
movq %r12, -128(%rbp)
testl %r13d, %r13d
jle .L18
movl $0, %ebx
leaq -80(%rbp), %r15
leaq -76(%rbp), %rdi
movq %rdi, -120(%rbp)
movq %rax, -152(%rbp)
.L19:
movq -120(%rbp), %rcx
movq %r15, %rdx
leaq .LC4(%rip), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %ebx, -72(%rbp)
movq .LC0(%rip), %rax
movq %rax, -64(%rbp)
movdqa -80(%rbp), %xmm2
movups %xmm2, (%r12)
movabsq $9218868437227405312, %rax
movq %rax, 16(%r12)
addl $1, %ebx
addq $24, %r12
cmpl %ebx, %r13d
jne .L19
movq -152(%rbp), %rax
.L18:
leal (%rax,%rax,2), %ebx
sall $3, %ebx
movslq %ebx, %rbx
leaq -112(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -128(%rbp), %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, -92(%rbp)
movl $1, -88(%rbp)
movl $1, -84(%rbp)
movl %r13d, -104(%rbp)
movl $1, -100(%rbp)
movl $1, -96(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -92(%rbp), %rdx
movl $1, %ecx
movq -104(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L20:
movl $2, %ecx
movq %rbx, %rdx
movq -112(%rbp), %rsi
movq -128(%rbp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L28
leaq 16(%rbx), %rax
movq -136(%rbp), %rsi
leaq 16(%rbx,%rsi), %rdx
movsd .LC0(%rip), %xmm4
movsd %xmm4, -120(%rbp)
.L23:
movsd (%rax), %xmm0
minsd -120(%rbp), %xmm0
movsd %xmm0, -120(%rbp)
addq $24, %rax
cmpq %rdx, %rax
jne .L23
movq -128(%rbp), %r12
movq -136(%rbp), %rax
addq %rax, %r12
leaq .LC5(%rip), %r13
jmp .L26
.L36:
movl %r13d, %esi
movq -112(%rbp), %rdi
call _Z37__device_stub__Z11calcMinDistP5pointiP5pointi
jmp .L20
.L37:
movl 4(%rbx), %ecx
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L24:
addq $24, %rbx
cmpq %r12, %rbx
je .L21
.L26:
movsd -120(%rbp), %xmm1
ucomisd 16(%rbx), %xmm1
jp .L24
jne .L24
jmp .L37
.L28:
movsd .LC0(%rip), %xmm5
movsd %xmm5, -120(%rbp)
.L21:
movsd -120(%rbp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq -144(%rbp), %rdi
subq %rdi, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z11calcMinDistP5pointi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calcMinDistP5pointi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 2146435072
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "p3.hip"
.globl _Z26__device_stub__calcMinDistP5pointi # -- Begin function _Z26__device_stub__calcMinDistP5pointi
.p2align 4, 0x90
.type _Z26__device_stub__calcMinDistP5pointi,@function
_Z26__device_stub__calcMinDistP5pointi: # @_Z26__device_stub__calcMinDistP5pointi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11calcMinDistP5pointi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__calcMinDistP5pointi, .Lfunc_end0-_Z26__device_stub__calcMinDistP5pointi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x7ff0000000000000 # double +Inf
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $168, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq 8(%rsi), %rdi
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_18
# %bb.1:
movq %rax, %rbx
callq clock
movq %rax, -120(%rbp) # 8-byte Spill
movl $1, %r15d
movl $-24, %r13d
leaq -96(%rbp), %r14
movl $4294967295, %r12d # imm = 0xFFFFFFFF
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %r14, %rdx
leaq -92(%rbp), %rcx
xorl %eax, %eax
callq __isoc23_fscanf
decq %r15
addl $24, %r13d
incq %r12
cmpl $2, %eax
je .LBB1_2
# %bb.3:
movq %rbx, %rdi
callq rewind
movq %rsp, -112(%rbp) # 8-byte Spill
movq %r15, %rax
negq %rax
movq %rax, -72(%rbp) # 8-byte Spill
leaq (,%r15,8), %rax
leaq (%rax,%rax,2), %rax
movl $15, %ecx
subq %rax, %rcx
andq $-16, %rcx
movq %rsp, %rax
subq %rcx, %rax
movq %rax, -64(%rbp) # 8-byte Spill
movq %rax, %rsp
movq %r15, -104(%rbp) # 8-byte Spill
testl %r15d, %r15d
je .LBB1_6
# %bb.4: # %.lr.ph
movq %rbx, %r15
movq -64(%rbp), %r14 # 8-byte Reload
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r15, %rdi
leaq -96(%rbp), %rdx
leaq -92(%rbp), %rcx
xorl %eax, %eax
callq __isoc23_fscanf
movl %ebx, -88(%rbp)
movabsq $9218868437227405312, %rax # imm = 0x7FF0000000000000
movq %rax, -80(%rbp)
movq %rax, 16(%r14)
movq -96(%rbp), %rax
movq %rax, (%r14)
movl -88(%rbp), %eax
movl %eax, 8(%r14)
movl -84(%rbp), %eax
movl %eax, 12(%r14)
incq %rbx
addq $24, %r14
cmpq %rbx, -72(%rbp) # 8-byte Folded Reload
jne .LBB1_5
.LBB1_6: # %._crit_edge
movslq %r13d, %r13
leaq -48(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
movq -48(%rbp), %rdi
movq -64(%rbp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movl $4294967295, %edx # imm = 0xFFFFFFFF
addq $2, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq -72(%rbp), %rbx # 8-byte Reload
jne .LBB1_8
# %bb.7:
movq -48(%rbp), %rax
movq %rax, -184(%rbp)
movl %ebx, -52(%rbp)
leaq -184(%rbp), %rax
movq %rax, -208(%rbp)
leaq -52(%rbp), %rax
movq %rax, -200(%rbp)
leaq -176(%rbp), %rdi
leaq -160(%rbp), %rsi
leaq -144(%rbp), %rdx
leaq -136(%rbp), %rcx
callq __hipPopCallConfiguration
movq -176(%rbp), %rsi
movl -168(%rbp), %edx
movq -160(%rbp), %rcx
movl -152(%rbp), %r8d
leaq -208(%rbp), %r9
movl $_Z11calcMinDistP5pointi, %edi
pushq -136(%rbp)
pushq -144(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_8:
movq -48(%rbp), %rsi
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq -104(%rbp), %rdx # 8-byte Reload
testl %edx, %edx
je .LBB1_9
# %bb.16: # %.lr.ph53.preheader
leaq 16(%r14), %rax
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
movq %rbx, %rcx
.p2align 4, 0x90
.LBB1_17: # %.lr.ph53
# =>This Inner Loop Header: Depth=1
movsd (%rax), %xmm0 # xmm0 = mem[0],zero
minsd %xmm1, %xmm0
addq $24, %rax
movapd %xmm0, %xmm1
decq %rcx
jne .LBB1_17
# %bb.10: # %.preheader
testl %edx, %edx
jne .LBB1_11
jmp .LBB1_15
.LBB1_9:
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
testl %edx, %edx
je .LBB1_15
.LBB1_11:
movsd %xmm0, -128(%rbp) # 8-byte Spill
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_12 Depth=1
addq $24, %r14
decq %rbx
je .LBB1_15
.LBB1_12: # %.lr.ph55
# =>This Inner Loop Header: Depth=1
movsd 16(%r14), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jne .LBB1_14
jp .LBB1_14
# %bb.13: # in Loop: Header=BB1_12 Depth=1
movl (%r14), %esi
movl 4(%r14), %edx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movsd -128(%rbp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jmp .LBB1_14
.LBB1_15: # %._crit_edge56
movl $.L.str.5, %edi
movb $1, %al
callq printf
callq clock
subq -120(%rbp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_1(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq -48(%rbp), %rdi
callq hipFree
movq -112(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_18:
.cfi_def_cfa %rbp, 16
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11calcMinDistP5pointi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11calcMinDistP5pointi,@object # @_Z11calcMinDistP5pointi
.section .rodata,"a",@progbits
.globl _Z11calcMinDistP5pointi
.p2align 3, 0x0
_Z11calcMinDistP5pointi:
.quad _Z26__device_stub__calcMinDistP5pointi
.size _Z11calcMinDistP5pointi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d%d"
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "(%d,%d)"
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%lf\n"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Time : %lf seconds\n"
.size .L.str.6, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11calcMinDistP5pointi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: ./p3 <input file>"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__calcMinDistP5pointi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11calcMinDistP5pointi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void Ring_kernel( float *A, float *BP, int *corrAB, float *M, int ring, int c, int h, int w )
{
int id1 = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
int ringSize = 2*ring + 1;
int ringPatch = ringSize * ringSize;
if (id1 < size) {
int y1 = id1 / w, x1 = id1 % w;
int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0];
// int id2 = y2 * w + x2;
for (int dx = -ring; dx <= ring; dx++)
for (int dy = -ring; dy <= ring; dy++)
{
int pIdx = (dy + ring) * ringSize + (dx + ring);
int _x2 = x2 + dx, _y2 = y2 + dy;
if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h)
{
for (int dc = 0; dc < c; dc++) {
// M[(dc * size + y1 * w + x1) * ringPatch + pIdx] =
M[(dc * size + y1 * w) * ringPatch + pIdx * w + x1] =
BP[dc * size + _y2 * w + _x2];
}
}
}
}
return ;
} | code for sm_80
Function : _Z11Ring_kernelPfS_PiS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC UR5, c[0x0][0x180] ; /* 0x0000600000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x188], RZ ; /* 0x0000620000007a24 */
/* 0x000fe200078e02ff */
/*0060*/ ULEA UR5, UR5, 0x1, 0x1 ; /* 0x0000000105057891 */
/* 0x000fe2000f8e083f */
/*0070*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R2, RZ, -c[0x0][0x180], RZ ; /* 0x80006000ff027a10 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fda0003f04270 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fca00078e00ff */
/*00e0*/ ISETP.LE.AND P0, PT, R3, c[0x0][0x184], PT ; /* 0x0000610003007a0c */
/* 0x000fda0003f03270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IABS R12, c[0x0][0x18c] ; /* 0x00006300000c7a13 */
/* 0x000fe20000000000 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0120*/ SHF.L.U32 R6, R8, 0x1, RZ ; /* 0x0000000108067819 */
/* 0x000fe200000006ff */
/*0130*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0140*/ I2F.RP R5, R12 ; /* 0x0000000c00057306 */
/* 0x000e260000209400 */
/*0150*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0207 */
/*0160*/ LDG.E R3, [R6.64+0x4] ; /* 0x0000040606037981 */
/* 0x000368000c1e1900 */
/*0170*/ LDG.E R4, [R6.64] ; /* 0x0000000606047981 */
/* 0x000362000c1e1900 */
/*0180*/ ISETP.GE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f46270 */
/*0190*/ UIMAD UR8, UR5, UR5, URZ ; /* 0x00000005050872a4 */
/* 0x000fe2000f8e023f */
/*01a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e220000001000 */
/*01b0*/ IABS R6, R8 ; /* 0x0000000800067213 */
/* 0x002fe20000000000 */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff077624 */
/* 0x000fe200078e00ff */
/*01d0*/ IADD3 R10, R5, 0xffffffe, RZ ; /* 0x0ffffffe050a7810 */
/* 0x001fca0007ffe0ff */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000064000021f000 */
/*01f0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fe200078e00ff */
/*0200*/ IADD3 R9, RZ, -R11, RZ ; /* 0x8000000bff097210 */
/* 0x002fca0007ffe0ff */
/*0210*/ IMAD R9, R9, R12, RZ ; /* 0x0000000c09097224 */
/* 0x000fc800078e02ff */
/*0220*/ IMAD.HI.U32 R11, R11, R9, R10 ; /* 0x000000090b0b7227 */
/* 0x000fc800078e000a */
/*0230*/ IMAD R9, R0, UR8, RZ ; /* 0x0000000800097c24 */
/* 0x000fe4000f8e02ff */
/*0240*/ IMAD.HI.U32 R11, R11, R6, RZ ; /* 0x000000060b0b7227 */
/* 0x000fca00078e00ff */
/*0250*/ IADD3 R11, -R11, RZ, RZ ; /* 0x000000ff0b0b7210 */
/* 0x000fca0007ffe1ff */
/*0260*/ IMAD R5, R12, R11, R6 ; /* 0x0000000b0c057224 */
/* 0x000fe400078e0206 */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc600078e00ff */
/*0280*/ ISETP.GT.U32.AND P0, PT, R12, R5, PT ; /* 0x000000050c00720c */
/* 0x000fe40003f04070 */
/*0290*/ IADD3 R6, -R6, c[0x0][0x184], RZ ; /* 0x0000610006067a10 */
/* 0x000fd60007ffe1ff */
/*02a0*/ @!P0 IMAD.IADD R5, R5, 0x1, -R12 ; /* 0x0000000105058824 */
/* 0x000fe200078e0a0c */
/*02b0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fc80003f05270 */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R12, R5, PT ; /* 0x000000050c00720c */
/* 0x000fda0003f24070 */
/*02d0*/ @!P1 IADD3 R5, R5, -R12, RZ ; /* 0x8000000c05059210 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*02f0*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*0300*/ @!P0 LOP3.LUT R5, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff058a12 */
/* 0x000fe400078e33ff */
/*0310*/ LOP3.LUT R6, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307067812 */
/* 0x000fe200078ec0ff */
/*0320*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0330*/ IADD3 R8, R8, -R5, RZ ; /* 0x8000000508087210 */
/* 0x000fc40007ffe0ff */
/*0340*/ IADD3 R10, R6, -c[0x0][0x184], RZ ; /* 0x80006100060a7a10 */
/* 0x000fc60007ffe0ff */
/*0350*/ IMAD R11, R8, UR8, R5 ; /* 0x00000008080b7c24 */
/* 0x000fe4000f8e0205 */
/*0360*/ ISETP.GE.AND P2, PT, R7.reuse, c[0x0][0x180], PT ; /* 0x0000600007007a0c */
/* 0x040fe20003f46270 */
/*0370*/ IMAD.MOV.U32 R24, RZ, RZ, R2 ; /* 0x000000ffff187224 */
/* 0x000fe200078e0002 */
/*0380*/ IADD3 R12, R7.reuse, c[0x0][0x180], RZ ; /* 0x00006000070c7a10 */
/* 0x040fe40007ffe0ff */
/*0390*/ IADD3 R13, R4, R7, RZ ; /* 0x00000007040d7210 */
/* 0x020fe40007ffe0ff */
/*03a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fe40007ffe0ff */
/*03b0*/ IADD3 R14, R3, R24, RZ ; /* 0x00000018030e7210 */
/* 0x001fe20007ffe0ff */
/*03c0*/ BSSY B0, 0x820 ; /* 0x0000045000007945 */
/* 0x000fe60003800000 */
/*03d0*/ LOP3.LUT R15, R14, R13, RZ, 0xfc, !PT ; /* 0x0000000d0e0f7212 */
/* 0x000fc800078efcff */
/*03e0*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*03f0*/ ISETP.GE.OR P0, PT, R13, c[0x0][0x18c], !P0 ; /* 0x000063000d007a0c */
/* 0x000fc80004706670 */
/*0400*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x188], P0 ; /* 0x000062000e007a0c */
/* 0x000fda0000706670 */
/*0410*/ @P0 BRA 0x810 ; /* 0x000003f000000947 */
/* 0x000fea0003800000 */
/*0420*/ IADD3 R15, R24, c[0x0][0x180], RZ ; /* 0x00006000180f7a10 */
/* 0x000fe20007ffe0ff */
/*0430*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0440*/ ISETP.NE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f65270 */
/*0450*/ IMAD R25, R14, c[0x0][0x18c], R13 ; /* 0x000063000e197a24 */
/* 0x000fe400078e020d */
/*0460*/ IMAD R26, R15, UR5, R12 ; /* 0x000000050f1a7c24 */
/* 0x000fe2000f8e020c */
/*0470*/ @!P1 BRA 0x620 ; /* 0x000001a000009947 */
/* 0x000ff00003800000 */
/*0480*/ IMAD R28, R26, c[0x0][0x18c], R11 ; /* 0x000063001a1c7a24 */
/* 0x000fe200078e020b */
/*0490*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*04a0*/ IMAD.MOV.U32 R27, RZ, RZ, R25 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e0019 */
/*04b0*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fd400000001ff */
/*04c0*/ IMAD.WIDE R20, R27, R16, c[0x0][0x168] ; /* 0x00005a001b147625 */
/* 0x000fca00078e0210 */
/*04d0*/ LDG.E R29, [R20.64] ; /* 0x00000006141d7981 */
/* 0x0010a2000c1e1900 */
/*04e0*/ IMAD.WIDE R16, R28, R16, c[0x0][0x178] ; /* 0x00005e001c107625 */
/* 0x000fc800078e0210 */
/*04f0*/ IMAD.WIDE R20, R0.reuse, 0x4, R20 ; /* 0x0000000400147825 */
/* 0x041fe200078e0214 */
/*0500*/ STG.E [R16.64], R29 ; /* 0x0000001d10007986 */
/* 0x0041e8000c101906 */
/*0510*/ LDG.E R19, [R20.64] ; /* 0x0000000614137981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0214 */
/*0530*/ IMAD.WIDE R16, R9, 0x4, R16 ; /* 0x0000000409107825 */
/* 0x001fca00078e0210 */
/*0540*/ STG.E [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0041e8000c101906 */
/*0550*/ LDG.E R29, [R14.64] ; /* 0x000000060e1d7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R22, R0, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x000fc800078e020e */
/*0570*/ IMAD.WIDE R18, R9, 0x4, R16 ; /* 0x0000000409127825 */
/* 0x001fca00078e0210 */
/*0580*/ STG.E [R18.64], R29 ; /* 0x0000001d12007986 */
/* 0x0041e8000c101906 */
/*0590*/ LDG.E R23, [R22.64] ; /* 0x0000000616177981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R14, R9.reuse, 0x4, R18 ; /* 0x00000004090e7825 */
/* 0x040fe200078e0212 */
/*05b0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*05c0*/ LEA R28, R9, R28, 0x2 ; /* 0x0000001c091c7211 */
/* 0x000fe400078e10ff */
/*05d0*/ IMAD R27, R0, 0x4, R27 ; /* 0x00000004001b7824 */
/* 0x000fc600078e021b */
/*05e0*/ IADD3 R20, R10, UR4, RZ ; /* 0x000000040a147c10 */
/* 0x000fc8000fffe0ff */
/*05f0*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f05270 */
/*0600*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0041d8000c101906 */
/*0610*/ @P0 BRA 0x4b0 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*0620*/ IMAD R26, R26, c[0x0][0x18c], R5 ; /* 0x000063001a1a7a24 */
/* 0x000fe200078e0205 */
/*0630*/ @!P3 BRA 0x810 ; /* 0x000001d00000b947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD R19, R0, UR4, RZ ; /* 0x0000000400137c24 */
/* 0x001fe4000f8e02ff */
/*0650*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fc600078e00ff */
/*0660*/ IADD3 R17, R25, R19, RZ ; /* 0x0000001319117210 */
/* 0x000fca0007ffe0ff */
/*0670*/ IMAD.WIDE R16, R17, R18, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fcc00078e0212 */
/*0680*/ LDG.E R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000ea2000c1e1900 */
/*0690*/ IMAD.IADD R15, R8, 0x1, R19 ; /* 0x00000001080f7824 */
/* 0x000fe200078e0213 */
/*06a0*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f05270 */
/*06b0*/ IMAD R15, R15, UR8, R26 ; /* 0x000000080f0f7c24 */
/* 0x000fc8000f8e021a */
/*06c0*/ IMAD.WIDE R14, R15, R18, c[0x0][0x178] ; /* 0x00005e000f0e7625 */
/* 0x000fca00078e0212 */
/*06d0*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0041e2000c101906 */
/*06e0*/ @!P0 BRA 0x810 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*06f0*/ IADD3 R19, R0, R19, RZ ; /* 0x0000001300137210 */
/* 0x000fca0007ffe0ff */
/*0700*/ IMAD.IADD R17, R25, 0x1, R19 ; /* 0x0000000119117824 */
/* 0x001fc800078e0213 */
/*0710*/ IMAD.WIDE R16, R17, R18, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fcc00078e0212 */
/*0720*/ LDG.E R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IADD3 R15, R8, R19, RZ ; /* 0x00000013080f7210 */
/* 0x000fe40007ffe0ff */
/*0740*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fc60003f05270 */
/*0750*/ IMAD R15, R15, UR8, R26 ; /* 0x000000080f0f7c24 */
/* 0x000fc8000f8e021a */
/*0760*/ IMAD.WIDE R14, R15, R18, c[0x0][0x178] ; /* 0x00005e000f0e7625 */
/* 0x000fca00078e0212 */
/*0770*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0041e2000c101906 */
/*0780*/ @!P0 BRA 0x810 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0790*/ IMAD.IADD R14, R0, 0x1, R19 ; /* 0x00000001000e7824 */
/* 0x001fca00078e0213 */
/*07a0*/ IADD3 R17, R25, R14, RZ ; /* 0x0000000e19117210 */
/* 0x000fca0007ffe0ff */
/*07b0*/ IMAD.WIDE R16, R17, R18, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fcc00078e0212 */
/*07c0*/ LDG.E R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ IADD3 R15, R8, R14, RZ ; /* 0x0000000e080f7210 */
/* 0x000fca0007ffe0ff */
/*07e0*/ IMAD R15, R15, UR8, R26 ; /* 0x000000080f0f7c24 */
/* 0x000fc8000f8e021a */
/*07f0*/ IMAD.WIDE R14, R15, R18, c[0x0][0x178] ; /* 0x00005e000f0e7625 */
/* 0x000fca00078e0212 */
/*0800*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0041e4000c101906 */
/*0810*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0820*/ ISETP.GE.AND P0, PT, R24.reuse, c[0x0][0x180], PT ; /* 0x0000600018007a0c */
/* 0x040fe40003f06270 */
/*0830*/ IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fd60007ffe0ff */
/*0840*/ @!P0 BRA 0x3b0 ; /* 0xfffffb6000008947 */
/* 0x000fea000383ffff */
/*0850*/ @!P2 BRA 0x360 ; /* 0xfffffb000000a947 */
/* 0x000fea000383ffff */
/*0860*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void Ring_kernel( float *A, float *BP, int *corrAB, float *M, int ring, int c, int h, int w )
{
int id1 = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
int ringSize = 2*ring + 1;
int ringPatch = ringSize * ringSize;
if (id1 < size) {
int y1 = id1 / w, x1 = id1 % w;
int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0];
// int id2 = y2 * w + x2;
for (int dx = -ring; dx <= ring; dx++)
for (int dy = -ring; dy <= ring; dy++)
{
int pIdx = (dy + ring) * ringSize + (dx + ring);
int _x2 = x2 + dx, _y2 = y2 + dy;
if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h)
{
for (int dc = 0; dc < c; dc++) {
// M[(dc * size + y1 * w + x1) * ringPatch + pIdx] =
M[(dc * size + y1 * w) * ringPatch + pIdx * w + x1] =
BP[dc * size + _y2 * w + _x2];
}
}
}
}
return ;
} | .file "tmpxft_0001698b_00000000-6_Ring_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii
.type _Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii, @function
_Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11Ring_kernelPfS_PiS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii, .-_Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii
.globl _Z11Ring_kernelPfS_PiS_iiii
.type _Z11Ring_kernelPfS_PiS_iiii, @function
_Z11Ring_kernelPfS_PiS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11Ring_kernelPfS_PiS_iiii, .-_Z11Ring_kernelPfS_PiS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11Ring_kernelPfS_PiS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Ring_kernelPfS_PiS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void Ring_kernel( float *A, float *BP, int *corrAB, float *M, int ring, int c, int h, int w )
{
int id1 = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
int ringSize = 2*ring + 1;
int ringPatch = ringSize * ringSize;
if (id1 < size) {
int y1 = id1 / w, x1 = id1 % w;
int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0];
// int id2 = y2 * w + x2;
for (int dx = -ring; dx <= ring; dx++)
for (int dy = -ring; dy <= ring; dy++)
{
int pIdx = (dy + ring) * ringSize + (dx + ring);
int _x2 = x2 + dx, _y2 = y2 + dy;
if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h)
{
for (int dc = 0; dc < c; dc++) {
// M[(dc * size + y1 * w + x1) * ringPatch + pIdx] =
M[(dc * size + y1 * w) * ringPatch + pIdx * w + x1] =
BP[dc * size + _y2 * w + _x2];
}
}
}
}
return ;
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void Ring_kernel( float *A, float *BP, int *corrAB, float *M, int ring, int c, int h, int w )
{
int id1 = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
int ringSize = 2*ring + 1;
int ringPatch = ringSize * ringSize;
if (id1 < size) {
int y1 = id1 / w, x1 = id1 % w;
int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0];
// int id2 = y2 * w + x2;
for (int dx = -ring; dx <= ring; dx++)
for (int dy = -ring; dy <= ring; dy++)
{
int pIdx = (dy + ring) * ringSize + (dx + ring);
int _x2 = x2 + dx, _y2 = y2 + dy;
if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h)
{
for (int dc = 0; dc < c; dc++) {
// M[(dc * size + y1 * w + x1) * ringPatch + pIdx] =
M[(dc * size + y1 * w) * ringPatch + pIdx * w + x1] =
BP[dc * size + _y2 * w + _x2];
}
}
}
}
return ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void Ring_kernel( float *A, float *BP, int *corrAB, float *M, int ring, int c, int h, int w )
{
int id1 = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
int ringSize = 2*ring + 1;
int ringPatch = ringSize * ringSize;
if (id1 < size) {
int y1 = id1 / w, x1 = id1 % w;
int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0];
// int id2 = y2 * w + x2;
for (int dx = -ring; dx <= ring; dx++)
for (int dy = -ring; dy <= ring; dy++)
{
int pIdx = (dy + ring) * ringSize + (dx + ring);
int _x2 = x2 + dx, _y2 = y2 + dy;
if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h)
{
for (int dc = 0; dc < c; dc++) {
// M[(dc * size + y1 * w + x1) * ringPatch + pIdx] =
M[(dc * size + y1 * w) * ringPatch + pIdx * w + x1] =
BP[dc * size + _y2 * w + _x2];
}
}
}
}
return ;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11Ring_kernelPfS_PiS_iiii
.globl _Z11Ring_kernelPfS_PiS_iiii
.p2align 8
.type _Z11Ring_kernelPfS_PiS_iiii,@function
_Z11Ring_kernelPfS_PiS_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s3, s9, s8
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_10
s_load_b32 s12, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 0
s_cbranch_scc1 .LBB0_10
v_lshlrev_b32_e32 v2, 1, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[10:11], s[0:1], 0x18
s_ashr_i32 s2, s9, 31
v_ashrrev_i32_e32 v9, 31, v1
v_or_b32_e32 v4, 1, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_add_i32 s6, s9, s2
s_clause 0x1
global_load_b32 v5, v[4:5], off
global_load_b32 v0, v[2:3], off
s_xor_b32 s2, s6, s2
v_add_nc_u32_e32 v4, v1, v9
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s6, 0, s2
s_sub_i32 s7, 0, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v9
v_rcp_iflag_f32_e32 v2, v2
s_mov_b32 s16, s7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v3, s6, v2
s_load_b32 s6, s[0:1], 0x24
s_lshl_b32 s0, s12, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, 1
s_mul_i32 s1, s0, s0
s_mul_i32 s14, s9, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
s_mul_i32 s15, s3, s1
v_add_nc_u32_e32 v6, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, v6, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cselect_b32 s13, -1, 0
v_mul_lo_u32 v2, v3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v4, v2
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_xor_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v9, v2
v_add_nc_u32_e32 v1, v1, v3
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v6, s12, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s9, v6, v[0:1]
v_mad_u64_u32 v[7:8], null, v1, s1, v[2:3]
v_subrev_nc_u32_e32 v6, s12, v3
s_delay_alu instid0(VALU_DEP_2)
v_sub_nc_u32_e32 v7, v7, v9
s_branch .LBB0_4
.LBB0_3:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v6, 1, v6
v_add_nc_u32_e32 v7, s9, v7
s_add_i32 s0, s16, 1
s_cmp_eq_u32 s16, s12
s_mov_b32 s16, s0
s_cbranch_scc1 .LBB0_10
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v8, v7 :: v_dual_add_nc_u32 v1, s16, v0
v_mov_b32_e32 v9, v6
s_mov_b32 s17, s7
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, -1, v1
v_cmp_le_i32_e64 s0, s9, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s18
v_add_nc_u32_e32 v9, s9, v9
v_add_nc_u32_e32 v8, s14, v8
s_add_i32 s1, s17, 1
s_cmp_eq_u32 s17, s12
s_mov_b32 s17, s1
s_cbranch_scc1 .LBB0_3
.LBB0_6:
s_and_saveexec_b32 s18, vcc_lo
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v1, s17, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s1, 0, v1
v_cmp_le_i32_e64 s2, s8, v1
s_or_b32 s1, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s1, s13
s_xor_b32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, v8
v_mov_b32_e32 v3, v9
s_mov_b32 s2, s6
.p2align 6
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s2, 0
v_lshlrev_b64 v[10:11], 2, v[3:4]
v_add_nc_u32_e32 v3, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s1, s4, v10
v_add_co_ci_u32_e64 v11, s1, s5, v11, s1
global_load_b32 v4, v[10:11], off
v_lshlrev_b64 v[10:11], 2, v[1:2]
v_add_nc_u32_e32 v1, s15, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s1, s10, v10
v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
s_waitcnt vmcnt(0)
global_store_b32 v[10:11], v4, off
s_cbranch_scc1 .LBB0_9
s_branch .LBB0_5
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Ring_kernelPfS_PiS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11Ring_kernelPfS_PiS_iiii, .Lfunc_end0-_Z11Ring_kernelPfS_PiS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Ring_kernelPfS_PiS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z11Ring_kernelPfS_PiS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void Ring_kernel( float *A, float *BP, int *corrAB, float *M, int ring, int c, int h, int w )
{
int id1 = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
int ringSize = 2*ring + 1;
int ringPatch = ringSize * ringSize;
if (id1 < size) {
int y1 = id1 / w, x1 = id1 % w;
int y2 = corrAB[2 * id1 + 1], x2 = corrAB[2 * id1 + 0];
// int id2 = y2 * w + x2;
for (int dx = -ring; dx <= ring; dx++)
for (int dy = -ring; dy <= ring; dy++)
{
int pIdx = (dy + ring) * ringSize + (dx + ring);
int _x2 = x2 + dx, _y2 = y2 + dy;
if (_x2 >= 0 && _x2 < w && _y2 >= 0 && _y2 < h)
{
for (int dc = 0; dc < c; dc++) {
// M[(dc * size + y1 * w + x1) * ringPatch + pIdx] =
M[(dc * size + y1 * w) * ringPatch + pIdx * w + x1] =
BP[dc * size + _y2 * w + _x2];
}
}
}
}
return ;
} | .text
.file "Ring_kernel.hip"
.globl _Z26__device_stub__Ring_kernelPfS_PiS_iiii # -- Begin function _Z26__device_stub__Ring_kernelPfS_PiS_iiii
.p2align 4, 0x90
.type _Z26__device_stub__Ring_kernelPfS_PiS_iiii,@function
_Z26__device_stub__Ring_kernelPfS_PiS_iiii: # @_Z26__device_stub__Ring_kernelPfS_PiS_iiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11Ring_kernelPfS_PiS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z26__device_stub__Ring_kernelPfS_PiS_iiii, .Lfunc_end0-_Z26__device_stub__Ring_kernelPfS_PiS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Ring_kernelPfS_PiS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11Ring_kernelPfS_PiS_iiii,@object # @_Z11Ring_kernelPfS_PiS_iiii
.section .rodata,"a",@progbits
.globl _Z11Ring_kernelPfS_PiS_iiii
.p2align 3, 0x0
_Z11Ring_kernelPfS_PiS_iiii:
.quad _Z26__device_stub__Ring_kernelPfS_PiS_iiii
.size _Z11Ring_kernelPfS_PiS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11Ring_kernelPfS_PiS_iiii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__Ring_kernelPfS_PiS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11Ring_kernelPfS_PiS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11Ring_kernelPfS_PiS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC UR5, c[0x0][0x180] ; /* 0x0000600000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x188], RZ ; /* 0x0000620000007a24 */
/* 0x000fe200078e02ff */
/*0060*/ ULEA UR5, UR5, 0x1, 0x1 ; /* 0x0000000105057891 */
/* 0x000fe2000f8e083f */
/*0070*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R2, RZ, -c[0x0][0x180], RZ ; /* 0x80006000ff027a10 */
/* 0x000fc80007ffe0ff */
/*00b0*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fda0003f04270 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fca00078e00ff */
/*00e0*/ ISETP.LE.AND P0, PT, R3, c[0x0][0x184], PT ; /* 0x0000610003007a0c */
/* 0x000fda0003f03270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IABS R12, c[0x0][0x18c] ; /* 0x00006300000c7a13 */
/* 0x000fe20000000000 */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0120*/ SHF.L.U32 R6, R8, 0x1, RZ ; /* 0x0000000108067819 */
/* 0x000fe200000006ff */
/*0130*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0140*/ I2F.RP R5, R12 ; /* 0x0000000c00057306 */
/* 0x000e260000209400 */
/*0150*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fca00078e0207 */
/*0160*/ LDG.E R3, [R6.64+0x4] ; /* 0x0000040606037981 */
/* 0x000368000c1e1900 */
/*0170*/ LDG.E R4, [R6.64] ; /* 0x0000000606047981 */
/* 0x000362000c1e1900 */
/*0180*/ ISETP.GE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f46270 */
/*0190*/ UIMAD UR8, UR5, UR5, URZ ; /* 0x00000005050872a4 */
/* 0x000fe2000f8e023f */
/*01a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e220000001000 */
/*01b0*/ IABS R6, R8 ; /* 0x0000000800067213 */
/* 0x002fe20000000000 */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff077624 */
/* 0x000fe200078e00ff */
/*01d0*/ IADD3 R10, R5, 0xffffffe, RZ ; /* 0x0ffffffe050a7810 */
/* 0x001fca0007ffe0ff */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000064000021f000 */
/*01f0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fe200078e00ff */
/*0200*/ IADD3 R9, RZ, -R11, RZ ; /* 0x8000000bff097210 */
/* 0x002fca0007ffe0ff */
/*0210*/ IMAD R9, R9, R12, RZ ; /* 0x0000000c09097224 */
/* 0x000fc800078e02ff */
/*0220*/ IMAD.HI.U32 R11, R11, R9, R10 ; /* 0x000000090b0b7227 */
/* 0x000fc800078e000a */
/*0230*/ IMAD R9, R0, UR8, RZ ; /* 0x0000000800097c24 */
/* 0x000fe4000f8e02ff */
/*0240*/ IMAD.HI.U32 R11, R11, R6, RZ ; /* 0x000000060b0b7227 */
/* 0x000fca00078e00ff */
/*0250*/ IADD3 R11, -R11, RZ, RZ ; /* 0x000000ff0b0b7210 */
/* 0x000fca0007ffe1ff */
/*0260*/ IMAD R5, R12, R11, R6 ; /* 0x0000000b0c057224 */
/* 0x000fe400078e0206 */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc600078e00ff */
/*0280*/ ISETP.GT.U32.AND P0, PT, R12, R5, PT ; /* 0x000000050c00720c */
/* 0x000fe40003f04070 */
/*0290*/ IADD3 R6, -R6, c[0x0][0x184], RZ ; /* 0x0000610006067a10 */
/* 0x000fd60007ffe1ff */
/*02a0*/ @!P0 IMAD.IADD R5, R5, 0x1, -R12 ; /* 0x0000000105058824 */
/* 0x000fe200078e0a0c */
/*02b0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fc80003f05270 */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R12, R5, PT ; /* 0x000000050c00720c */
/* 0x000fda0003f24070 */
/*02d0*/ @!P1 IADD3 R5, R5, -R12, RZ ; /* 0x8000000c05059210 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*02f0*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*0300*/ @!P0 LOP3.LUT R5, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff058a12 */
/* 0x000fe400078e33ff */
/*0310*/ LOP3.LUT R6, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307067812 */
/* 0x000fe200078ec0ff */
/*0320*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0330*/ IADD3 R8, R8, -R5, RZ ; /* 0x8000000508087210 */
/* 0x000fc40007ffe0ff */
/*0340*/ IADD3 R10, R6, -c[0x0][0x184], RZ ; /* 0x80006100060a7a10 */
/* 0x000fc60007ffe0ff */
/*0350*/ IMAD R11, R8, UR8, R5 ; /* 0x00000008080b7c24 */
/* 0x000fe4000f8e0205 */
/*0360*/ ISETP.GE.AND P2, PT, R7.reuse, c[0x0][0x180], PT ; /* 0x0000600007007a0c */
/* 0x040fe20003f46270 */
/*0370*/ IMAD.MOV.U32 R24, RZ, RZ, R2 ; /* 0x000000ffff187224 */
/* 0x000fe200078e0002 */
/*0380*/ IADD3 R12, R7.reuse, c[0x0][0x180], RZ ; /* 0x00006000070c7a10 */
/* 0x040fe40007ffe0ff */
/*0390*/ IADD3 R13, R4, R7, RZ ; /* 0x00000007040d7210 */
/* 0x020fe40007ffe0ff */
/*03a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fe40007ffe0ff */
/*03b0*/ IADD3 R14, R3, R24, RZ ; /* 0x00000018030e7210 */
/* 0x001fe20007ffe0ff */
/*03c0*/ BSSY B0, 0x820 ; /* 0x0000045000007945 */
/* 0x000fe60003800000 */
/*03d0*/ LOP3.LUT R15, R14, R13, RZ, 0xfc, !PT ; /* 0x0000000d0e0f7212 */
/* 0x000fc800078efcff */
/*03e0*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*03f0*/ ISETP.GE.OR P0, PT, R13, c[0x0][0x18c], !P0 ; /* 0x000063000d007a0c */
/* 0x000fc80004706670 */
/*0400*/ ISETP.GE.OR P0, PT, R14, c[0x0][0x188], P0 ; /* 0x000062000e007a0c */
/* 0x000fda0000706670 */
/*0410*/ @P0 BRA 0x810 ; /* 0x000003f000000947 */
/* 0x000fea0003800000 */
/*0420*/ IADD3 R15, R24, c[0x0][0x180], RZ ; /* 0x00006000180f7a10 */
/* 0x000fe20007ffe0ff */
/*0430*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0440*/ ISETP.NE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f65270 */
/*0450*/ IMAD R25, R14, c[0x0][0x18c], R13 ; /* 0x000063000e197a24 */
/* 0x000fe400078e020d */
/*0460*/ IMAD R26, R15, UR5, R12 ; /* 0x000000050f1a7c24 */
/* 0x000fe2000f8e020c */
/*0470*/ @!P1 BRA 0x620 ; /* 0x000001a000009947 */
/* 0x000ff00003800000 */
/*0480*/ IMAD R28, R26, c[0x0][0x18c], R11 ; /* 0x000063001a1c7a24 */
/* 0x000fe200078e020b */
/*0490*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*04a0*/ IMAD.MOV.U32 R27, RZ, RZ, R25 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e0019 */
/*04b0*/ HFMA2.MMA R16, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff107435 */
/* 0x000fd400000001ff */
/*04c0*/ IMAD.WIDE R20, R27, R16, c[0x0][0x168] ; /* 0x00005a001b147625 */
/* 0x000fca00078e0210 */
/*04d0*/ LDG.E R29, [R20.64] ; /* 0x00000006141d7981 */
/* 0x0010a2000c1e1900 */
/*04e0*/ IMAD.WIDE R16, R28, R16, c[0x0][0x178] ; /* 0x00005e001c107625 */
/* 0x000fc800078e0210 */
/*04f0*/ IMAD.WIDE R20, R0.reuse, 0x4, R20 ; /* 0x0000000400147825 */
/* 0x041fe200078e0214 */
/*0500*/ STG.E [R16.64], R29 ; /* 0x0000001d10007986 */
/* 0x0041e8000c101906 */
/*0510*/ LDG.E R19, [R20.64] ; /* 0x0000000614137981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0214 */
/*0530*/ IMAD.WIDE R16, R9, 0x4, R16 ; /* 0x0000000409107825 */
/* 0x001fca00078e0210 */
/*0540*/ STG.E [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0041e8000c101906 */
/*0550*/ LDG.E R29, [R14.64] ; /* 0x000000060e1d7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R22, R0, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x000fc800078e020e */
/*0570*/ IMAD.WIDE R18, R9, 0x4, R16 ; /* 0x0000000409127825 */
/* 0x001fca00078e0210 */
/*0580*/ STG.E [R18.64], R29 ; /* 0x0000001d12007986 */
/* 0x0041e8000c101906 */
/*0590*/ LDG.E R23, [R22.64] ; /* 0x0000000616177981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R14, R9.reuse, 0x4, R18 ; /* 0x00000004090e7825 */
/* 0x040fe200078e0212 */
/*05b0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*05c0*/ LEA R28, R9, R28, 0x2 ; /* 0x0000001c091c7211 */
/* 0x000fe400078e10ff */
/*05d0*/ IMAD R27, R0, 0x4, R27 ; /* 0x00000004001b7824 */
/* 0x000fc600078e021b */
/*05e0*/ IADD3 R20, R10, UR4, RZ ; /* 0x000000040a147c10 */
/* 0x000fc8000fffe0ff */
/*05f0*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f05270 */
/*0600*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0041d8000c101906 */
/*0610*/ @P0 BRA 0x4b0 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*0620*/ IMAD R26, R26, c[0x0][0x18c], R5 ; /* 0x000063001a1a7a24 */
/* 0x000fe200078e0205 */
/*0630*/ @!P3 BRA 0x810 ; /* 0x000001d00000b947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD R19, R0, UR4, RZ ; /* 0x0000000400137c24 */
/* 0x001fe4000f8e02ff */
/*0650*/ IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff127424 */
/* 0x000fc600078e00ff */
/*0660*/ IADD3 R17, R25, R19, RZ ; /* 0x0000001319117210 */
/* 0x000fca0007ffe0ff */
/*0670*/ IMAD.WIDE R16, R17, R18, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fcc00078e0212 */
/*0680*/ LDG.E R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000ea2000c1e1900 */
/*0690*/ IMAD.IADD R15, R8, 0x1, R19 ; /* 0x00000001080f7824 */
/* 0x000fe200078e0213 */
/*06a0*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f05270 */
/*06b0*/ IMAD R15, R15, UR8, R26 ; /* 0x000000080f0f7c24 */
/* 0x000fc8000f8e021a */
/*06c0*/ IMAD.WIDE R14, R15, R18, c[0x0][0x178] ; /* 0x00005e000f0e7625 */
/* 0x000fca00078e0212 */
/*06d0*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0041e2000c101906 */
/*06e0*/ @!P0 BRA 0x810 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*06f0*/ IADD3 R19, R0, R19, RZ ; /* 0x0000001300137210 */
/* 0x000fca0007ffe0ff */
/*0700*/ IMAD.IADD R17, R25, 0x1, R19 ; /* 0x0000000119117824 */
/* 0x001fc800078e0213 */
/*0710*/ IMAD.WIDE R16, R17, R18, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fcc00078e0212 */
/*0720*/ LDG.E R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IADD3 R15, R8, R19, RZ ; /* 0x00000013080f7210 */
/* 0x000fe40007ffe0ff */
/*0740*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fc60003f05270 */
/*0750*/ IMAD R15, R15, UR8, R26 ; /* 0x000000080f0f7c24 */
/* 0x000fc8000f8e021a */
/*0760*/ IMAD.WIDE R14, R15, R18, c[0x0][0x178] ; /* 0x00005e000f0e7625 */
/* 0x000fca00078e0212 */
/*0770*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0041e2000c101906 */
/*0780*/ @!P0 BRA 0x810 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0790*/ IMAD.IADD R14, R0, 0x1, R19 ; /* 0x00000001000e7824 */
/* 0x001fca00078e0213 */
/*07a0*/ IADD3 R17, R25, R14, RZ ; /* 0x0000000e19117210 */
/* 0x000fca0007ffe0ff */
/*07b0*/ IMAD.WIDE R16, R17, R18, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fcc00078e0212 */
/*07c0*/ LDG.E R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ IADD3 R15, R8, R14, RZ ; /* 0x0000000e080f7210 */
/* 0x000fca0007ffe0ff */
/*07e0*/ IMAD R15, R15, UR8, R26 ; /* 0x000000080f0f7c24 */
/* 0x000fc8000f8e021a */
/*07f0*/ IMAD.WIDE R14, R15, R18, c[0x0][0x178] ; /* 0x00005e000f0e7625 */
/* 0x000fca00078e0212 */
/*0800*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0041e4000c101906 */
/*0810*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0820*/ ISETP.GE.AND P0, PT, R24.reuse, c[0x0][0x180], PT ; /* 0x0000600018007a0c */
/* 0x040fe40003f06270 */
/*0830*/ IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fd60007ffe0ff */
/*0840*/ @!P0 BRA 0x3b0 ; /* 0xfffffb6000008947 */
/* 0x000fea000383ffff */
/*0850*/ @!P2 BRA 0x360 ; /* 0xfffffb000000a947 */
/* 0x000fea000383ffff */
/*0860*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11Ring_kernelPfS_PiS_iiii
.globl _Z11Ring_kernelPfS_PiS_iiii
.p2align 8
.type _Z11Ring_kernelPfS_PiS_iiii,@function
_Z11Ring_kernelPfS_PiS_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s3, s9, s8
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_10
s_load_b32 s12, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 0
s_cbranch_scc1 .LBB0_10
v_lshlrev_b32_e32 v2, 1, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[10:11], s[0:1], 0x18
s_ashr_i32 s2, s9, 31
v_ashrrev_i32_e32 v9, 31, v1
v_or_b32_e32 v4, 1, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_add_i32 s6, s9, s2
s_clause 0x1
global_load_b32 v5, v[4:5], off
global_load_b32 v0, v[2:3], off
s_xor_b32 s2, s6, s2
v_add_nc_u32_e32 v4, v1, v9
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s6, 0, s2
s_sub_i32 s7, 0, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v9
v_rcp_iflag_f32_e32 v2, v2
s_mov_b32 s16, s7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v3, s6, v2
s_load_b32 s6, s[0:1], 0x24
s_lshl_b32 s0, s12, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, 1
s_mul_i32 s1, s0, s0
s_mul_i32 s14, s9, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
s_mul_i32 s15, s3, s1
v_add_nc_u32_e32 v6, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, v6, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cselect_b32 s13, -1, 0
v_mul_lo_u32 v2, v3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v4, v2
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_xor_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v9, v2
v_add_nc_u32_e32 v1, v1, v3
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v6, s12, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s9, v6, v[0:1]
v_mad_u64_u32 v[7:8], null, v1, s1, v[2:3]
v_subrev_nc_u32_e32 v6, s12, v3
s_delay_alu instid0(VALU_DEP_2)
v_sub_nc_u32_e32 v7, v7, v9
s_branch .LBB0_4
.LBB0_3:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v6, 1, v6
v_add_nc_u32_e32 v7, s9, v7
s_add_i32 s0, s16, 1
s_cmp_eq_u32 s16, s12
s_mov_b32 s16, s0
s_cbranch_scc1 .LBB0_10
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v8, v7 :: v_dual_add_nc_u32 v1, s16, v0
v_mov_b32_e32 v9, v6
s_mov_b32 s17, s7
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, -1, v1
v_cmp_le_i32_e64 s0, s9, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s18
v_add_nc_u32_e32 v9, s9, v9
v_add_nc_u32_e32 v8, s14, v8
s_add_i32 s1, s17, 1
s_cmp_eq_u32 s17, s12
s_mov_b32 s17, s1
s_cbranch_scc1 .LBB0_3
.LBB0_6:
s_and_saveexec_b32 s18, vcc_lo
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v1, s17, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s1, 0, v1
v_cmp_le_i32_e64 s2, s8, v1
s_or_b32 s1, s0, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s1, s13
s_xor_b32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, v8
v_mov_b32_e32 v3, v9
s_mov_b32 s2, s6
.p2align 6
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s2, 0
v_lshlrev_b64 v[10:11], 2, v[3:4]
v_add_nc_u32_e32 v3, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s1, s4, v10
v_add_co_ci_u32_e64 v11, s1, s5, v11, s1
global_load_b32 v4, v[10:11], off
v_lshlrev_b64 v[10:11], 2, v[1:2]
v_add_nc_u32_e32 v1, s15, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s1, s10, v10
v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
s_waitcnt vmcnt(0)
global_store_b32 v[10:11], v4, off
s_cbranch_scc1 .LBB0_9
s_branch .LBB0_5
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11Ring_kernelPfS_PiS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11Ring_kernelPfS_PiS_iiii, .Lfunc_end0-_Z11Ring_kernelPfS_PiS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11Ring_kernelPfS_PiS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z11Ring_kernelPfS_PiS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001698b_00000000-6_Ring_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii
.type _Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii, @function
_Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11Ring_kernelPfS_PiS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii, .-_Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii
.globl _Z11Ring_kernelPfS_PiS_iiii
.type _Z11Ring_kernelPfS_PiS_iiii, @function
_Z11Ring_kernelPfS_PiS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z11Ring_kernelPfS_PiS_iiiiPfS_PiS_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11Ring_kernelPfS_PiS_iiii, .-_Z11Ring_kernelPfS_PiS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11Ring_kernelPfS_PiS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11Ring_kernelPfS_PiS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Ring_kernel.hip"
.globl _Z26__device_stub__Ring_kernelPfS_PiS_iiii # -- Begin function _Z26__device_stub__Ring_kernelPfS_PiS_iiii
.p2align 4, 0x90
.type _Z26__device_stub__Ring_kernelPfS_PiS_iiii,@function
_Z26__device_stub__Ring_kernelPfS_PiS_iiii: # @_Z26__device_stub__Ring_kernelPfS_PiS_iiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11Ring_kernelPfS_PiS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z26__device_stub__Ring_kernelPfS_PiS_iiii, .Lfunc_end0-_Z26__device_stub__Ring_kernelPfS_PiS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11Ring_kernelPfS_PiS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11Ring_kernelPfS_PiS_iiii,@object # @_Z11Ring_kernelPfS_PiS_iiii
.section .rodata,"a",@progbits
.globl _Z11Ring_kernelPfS_PiS_iiii
.p2align 3, 0x0
_Z11Ring_kernelPfS_PiS_iiii:
.quad _Z26__device_stub__Ring_kernelPfS_PiS_iiii
.size _Z11Ring_kernelPfS_PiS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11Ring_kernelPfS_PiS_iiii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__Ring_kernelPfS_PiS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11Ring_kernelPfS_PiS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "file_reader.cuh"
#include "reader.cuh"
template<class T>
FileReader<T>::FileReader(std::string &filename, Probe &probe)
: Reader<T>(probe), filename_(filename), file_size_(0) {
set_filename(filename);
}
/**
* @brief Acquire samples_ from the file, so many frames at a time.
* @tparam T The type of samples_ stored in the underlying file.
* @param frame_offset Number of frames after the beginning to start acquiring.
* @param n_frames Number of frames to acquire.
* @param buf Buffer where the acquired samples_ will be stored.
* @return The number of frames read.
*/
template<class T>
uint32_t
FileReader<T>::AcquireFrames(std::vector<T> &buf,
uint64_t frame_offset,
uint32_t n_frames) {
if (n_frames == 0) {
return 0;
}
Open(); // no-op if already Open
auto n_channels = this->probe_.n_total();
auto n_samples = n_frames * n_channels;
if (buf.size() != n_samples) {
buf.resize(n_samples);
}
auto nb = sizeof(T);
auto fpos = frame_offset * n_channels * nb;
auto n_bytes = nb * n_samples < file_size_ - fpos ? nb * n_samples : file_size_ - fpos;
fp.seekg(fpos, std::ios::beg);
fp.read((char *) buf.data(), n_bytes);
return n_bytes / (nb * this->probe_.n_total());
}
/**
* @brief Open the underlying file for reading.
* @tparam T The type of samples_ stored in the underlying file.
*/
template<class T>
void FileReader<T>::Open() {
if (!fp.is_open())
fp.open(filename_, std::ios::in | std::ios::binary);
}
/**
* @brief Close the underlying file.
* @tparam T The type of samples_ stored in the underlying file.
*/
template<class T>
void FileReader<T>::Close() {
if (fp.is_open())
fp.close();
}
/**
* @brief Compute and return the number of frames in the underlying data file.
* @tparam T The type of data stored in the underlying file.
* @return The number of frames in the underlying data file.
*/
template<class T>
uint64_t FileReader<T>::n_frames() const {
return file_size_ / (Reader<T>::probe_.n_total() * sizeof(T));
}
/**
* @brief Set the path for the underlying file.
* @tparam T The type of data stored in the underlying file.
* @param filename
*/
template<class T>
void FileReader<T>::set_filename(std::string &filename) {
filename_ = filename;
ComputeFileSize();
}
template<class T>
void FileReader<T>::ComputeFileSize() {
FileReader<T>::Open();
// seek to the end to get the size in bytes
fp.seekg(0, std::ios::end);
file_size_ = fp.tellg();
FileReader<T>::Close();
}
template
class FileReader<short>; | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "file_reader.cuh"
#include "reader.cuh"
template<class T>
FileReader<T>::FileReader(std::string &filename, Probe &probe)
: Reader<T>(probe), filename_(filename), file_size_(0) {
set_filename(filename);
}
/**
* @brief Acquire samples_ from the file, so many frames at a time.
* @tparam T The type of samples_ stored in the underlying file.
* @param frame_offset Number of frames after the beginning to start acquiring.
* @param n_frames Number of frames to acquire.
* @param buf Buffer where the acquired samples_ will be stored.
* @return The number of frames read.
*/
template<class T>
uint32_t
FileReader<T>::AcquireFrames(std::vector<T> &buf,
uint64_t frame_offset,
uint32_t n_frames) {
if (n_frames == 0) {
return 0;
}
Open(); // no-op if already Open
auto n_channels = this->probe_.n_total();
auto n_samples = n_frames * n_channels;
if (buf.size() != n_samples) {
buf.resize(n_samples);
}
auto nb = sizeof(T);
auto fpos = frame_offset * n_channels * nb;
auto n_bytes = nb * n_samples < file_size_ - fpos ? nb * n_samples : file_size_ - fpos;
fp.seekg(fpos, std::ios::beg);
fp.read((char *) buf.data(), n_bytes);
return n_bytes / (nb * this->probe_.n_total());
}
/**
* @brief Open the underlying file for reading.
* @tparam T The type of samples_ stored in the underlying file.
*/
template<class T>
void FileReader<T>::Open() {
if (!fp.is_open())
fp.open(filename_, std::ios::in | std::ios::binary);
}
/**
* @brief Close the underlying file.
* @tparam T The type of samples_ stored in the underlying file.
*/
template<class T>
void FileReader<T>::Close() {
if (fp.is_open())
fp.close();
}
/**
* @brief Compute and return the number of frames in the underlying data file.
* @tparam T The type of data stored in the underlying file.
* @return The number of frames in the underlying data file.
*/
template<class T>
uint64_t FileReader<T>::n_frames() const {
return file_size_ / (Reader<T>::probe_.n_total() * sizeof(T));
}
/**
* @brief Set the path for the underlying file.
* @tparam T The type of data stored in the underlying file.
* @param filename
*/
template<class T>
void FileReader<T>::set_filename(std::string &filename) {
filename_ = filename;
ComputeFileSize();
}
template<class T>
void FileReader<T>::ComputeFileSize() {
FileReader<T>::Open();
// seek to the end to get the size in bytes
fp.seekg(0, std::ios::end);
file_size_ = fp.tellg();
FileReader<T>::Close();
}
template
class FileReader<short>; | #include <hip/hip_runtime.h>
#include "file_reader.cuh"
#include "reader.cuh"
template<class T>
FileReader<T>::FileReader(std::string &filename, Probe &probe)
: Reader<T>(probe), filename_(filename), file_size_(0) {
set_filename(filename);
}
/**
* @brief Acquire samples_ from the file, so many frames at a time.
* @tparam T The type of samples_ stored in the underlying file.
* @param frame_offset Number of frames after the beginning to start acquiring.
* @param n_frames Number of frames to acquire.
* @param buf Buffer where the acquired samples_ will be stored.
* @return The number of frames read.
*/
template<class T>
uint32_t
FileReader<T>::AcquireFrames(std::vector<T> &buf,
uint64_t frame_offset,
uint32_t n_frames) {
if (n_frames == 0) {
return 0;
}
Open(); // no-op if already Open
auto n_channels = this->probe_.n_total();
auto n_samples = n_frames * n_channels;
if (buf.size() != n_samples) {
buf.resize(n_samples);
}
auto nb = sizeof(T);
auto fpos = frame_offset * n_channels * nb;
auto n_bytes = nb * n_samples < file_size_ - fpos ? nb * n_samples : file_size_ - fpos;
fp.seekg(fpos, std::ios::beg);
fp.read((char *) buf.data(), n_bytes);
return n_bytes / (nb * this->probe_.n_total());
}
/**
* @brief Open the underlying file for reading.
* @tparam T The type of samples_ stored in the underlying file.
*/
template<class T>
void FileReader<T>::Open() {
if (!fp.is_open())
fp.open(filename_, std::ios::in | std::ios::binary);
}
/**
* @brief Close the underlying file.
* @tparam T The type of samples_ stored in the underlying file.
*/
template<class T>
void FileReader<T>::Close() {
if (fp.is_open())
fp.close();
}
/**
* @brief Compute and return the number of frames in the underlying data file.
* @tparam T The type of data stored in the underlying file.
* @return The number of frames in the underlying data file.
*/
template<class T>
uint64_t FileReader<T>::n_frames() const {
return file_size_ / (Reader<T>::probe_.n_total() * sizeof(T));
}
/**
* @brief Set the path for the underlying file.
* @tparam T The type of data stored in the underlying file.
* @param filename
*/
template<class T>
void FileReader<T>::set_filename(std::string &filename) {
filename_ = filename;
ComputeFileSize();
}
template<class T>
void FileReader<T>::ComputeFileSize() {
FileReader<T>::Open();
// seek to the end to get the size in bytes
fp.seekg(0, std::ios::end);
file_size_ = fp.tellg();
FileReader<T>::Close();
}
template
class FileReader<short>; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "file_reader.cuh"
#include "reader.cuh"
template<class T>
FileReader<T>::FileReader(std::string &filename, Probe &probe)
: Reader<T>(probe), filename_(filename), file_size_(0) {
set_filename(filename);
}
/**
* @brief Acquire samples_ from the file, so many frames at a time.
* @tparam T The type of samples_ stored in the underlying file.
* @param frame_offset Number of frames after the beginning to start acquiring.
* @param n_frames Number of frames to acquire.
* @param buf Buffer where the acquired samples_ will be stored.
* @return The number of frames read.
*/
template<class T>
uint32_t
FileReader<T>::AcquireFrames(std::vector<T> &buf,
uint64_t frame_offset,
uint32_t n_frames) {
if (n_frames == 0) {
return 0;
}
Open(); // no-op if already Open
auto n_channels = this->probe_.n_total();
auto n_samples = n_frames * n_channels;
if (buf.size() != n_samples) {
buf.resize(n_samples);
}
auto nb = sizeof(T);
auto fpos = frame_offset * n_channels * nb;
auto n_bytes = nb * n_samples < file_size_ - fpos ? nb * n_samples : file_size_ - fpos;
fp.seekg(fpos, std::ios::beg);
fp.read((char *) buf.data(), n_bytes);
return n_bytes / (nb * this->probe_.n_total());
}
/**
* @brief Open the underlying file for reading.
* @tparam T The type of samples_ stored in the underlying file.
*/
template<class T>
void FileReader<T>::Open() {
if (!fp.is_open())
fp.open(filename_, std::ios::in | std::ios::binary);
}
/**
* @brief Close the underlying file.
* @tparam T The type of samples_ stored in the underlying file.
*/
template<class T>
void FileReader<T>::Close() {
if (fp.is_open())
fp.close();
}
/**
* @brief Compute and return the number of frames in the underlying data file.
* @tparam T The type of data stored in the underlying file.
* @return The number of frames in the underlying data file.
*/
template<class T>
uint64_t FileReader<T>::n_frames() const {
return file_size_ / (Reader<T>::probe_.n_total() * sizeof(T));
}
/**
* @brief Set the path for the underlying file.
* @tparam T The type of data stored in the underlying file.
* @param filename
*/
template<class T>
void FileReader<T>::set_filename(std::string &filename) {
filename_ = filename;
ComputeFileSize();
}
template<class T>
void FileReader<T>::ComputeFileSize() {
FileReader<T>::Open();
// seek to the end to get the size in bytes
fp.seekg(0, std::ios::end);
file_size_ = fp.tellg();
FileReader<T>::Close();
}
template
class FileReader<short>; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <assert.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <stdarg.h>
struct settings
{
unsigned int iterations;
unsigned int x;
unsigned int y;
unsigned int z;
unsigned int n;
bool dim_3d;
unsigned int threads;
unsigned long read_only;
};
bool read(char *token, const char *delim, int argc, ...)
{
va_list argv;
va_start(argv, argc);
unsigned int *temp_int;
float *temp_float;
unsigned int i;
for (i = 0; i < argc; i++)
{
token = strtok(NULL, delim);
if (i == argc - 1)
{
temp_float = (float *) va_arg(argv, float *);
if (token != NULL) { *temp_float = atof(token); }
else { return false; }
}
else
{
temp_int = (unsigned int *) va_arg(argv, unsigned int*);
if (token != NULL) { *temp_int = atoi(token); }
else { return false; }
}
}
return true;
}
unsigned int next_pow(unsigned int x)
{
unsigned int n = 1;
while (n < x) { n <<= 1; }
return n;
}
unsigned int __max(unsigned int a, unsigned int b)
{
if (a > b) { return a; }
return b;
}
__global__ void iterate2d(float *from, float *to, bool *read_only, unsigned int yshift, unsigned int N)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
if (read_only[x+(y<<yshift)] == false && x != 0 && y != 0 && x != (N - 1) && y != (N - 1))
{
to[x+(y<<yshift)] = (from[(x+1)+((y+1)<<yshift)] + from[(x+1)+((y-1))] + from[(x-1)+((y+1)<<yshift)] + from[(x-1)+((y-1)<<yshift)]) / 4;
}
else
{
to[x+(y<<yshift)] = from[x+(y<<yshift)];
}
}
__global__ void iterate3d(float *from, float *to, bool *read_only, unsigned int yshift, unsigned int zshift, unsigned int N, unsigned int NN)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int z = blockIdx.z * blockDim.z + threadIdx.z;
if (read_only[x+(y<<yshift)+(z<<zshift)] == false && x != 0 && y != 0 && z != 0 && x != (N - 1) && y != (N - 1) && z != (N - 1))
{
to[x+(y<<yshift)+(z<<zshift)] = (from[(x+1)+((y+1)<<yshift)+((z+1)<<zshift)] + from[(x+1)+((y+1)<<yshift)+((z-1)<<zshift)] + from[(x+1)+((y-1)<<yshift)+((z+1)<<zshift)] + from[(x+1)+((y-1)<<yshift)+((z-1)<<zshift)] + from[(x-1)+((y+1)<<yshift)+((z+1)<<zshift)] + from[(x-1)+((y+1)<<yshift)+((z-1)<<zshift)] + from[(x-1)+((y-1)<<yshift)+((z+1)<<zshift)] + from[(x-1)+((y-1)<<yshift)+((z-1)<<zshift)]) / 8;
}
else
{
to[x+(y<<yshift)+(z<<zshift)] = from[x+(y<<yshift)+(z<<zshift)];
}
}
void read_config(char *settings_file, settings &config)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
memset(buf, 0, size + 1);
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
while (token != NULL)
{
if (strcmp(token, "iterations") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.iterations = atoi(token); }
}
else if (strcmp(token, "x") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.x = atoi(token); }
}
else if (strcmp(token, "y") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.y = atoi(token); }
}
else if (strcmp(token, "z") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.z = atoi(token); }
}
else if (strcmp(token, "threads") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.threads = atoi(token); }
}
else if (strcmp(token, "2d") == 0)
{
config.dim_3d = false;
}
else if (strcmp(token, "3d") == 0)
{
config.dim_3d = true;
}
token = strtok(NULL, delimiter);
}
free(buf);
fclose(handle);
}
void init2d(char *settings_file, settings &config, float *data, bool *read_only)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
for(unsigned long i = 0; i < config.n * config.n; i++)
{
data[i] = 0.0f;
read_only[i] = false;
}
config.read_only = 0;
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
unsigned int x0;
unsigned int x1;
unsigned int y0;
unsigned int y1;
float f;
unsigned int x;
unsigned int y;
while (token != NULL)
{
if (strcmp(token, "point") == 0) //point located at (x,y), syntax: point [x] [y] [value]
{
assert(read(token, delimiter, 3, &x, &y, &f));
assert(x < config.n);
assert(y < config.n);
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
if (strcmp(token, "yline") == 0) //line in y direction, syntax: yline [xpos] [ystart] [yend] [value]
{
assert(read(token, delimiter, 4, &x, &y0, &y1, &f));
assert(y0 < y1);
assert(x < config.n);
assert(y1 < config.n);
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
else if (strcmp(token, "xline") == 0) //line in x direction, syntax: xline [ypos] [xstart] [xend] [value]
{
assert(read(token, delimiter, 4, &y, &x0, &x1, &f));
assert(x0 < x1);
assert(y < config.n);
assert(x1 < config.n);
for (x = x0; x <= x1; x++)
{
assert(x < config.n);
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
else if (strcmp(token, "rectangle") == 0) //rectangle from (x0, y0) to (x1, y1), syntax: square [x0] [y0] [x1] [y1] [value]
{
assert(read(token, delimiter, 5, &x0, &y0, &x1, &y1, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(x1 < config.n);
assert(y1 < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
}
token = strtok(NULL, delimiter);
}
for (x = config.x; x < config.n; x++)
{
for (y = config.y; y < config.n; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
}
}
free(buf);
fclose(handle);
}
void init3d(char *settings_file, settings &config, float *data, bool *read_only)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
for(unsigned long i = 0; i < config.n * config.n * config.n; i++)
{
data[i] = 0.0f;
read_only[i] = false;
}
config.read_only = 0;
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
unsigned int x0;
unsigned int x1;
unsigned int y0;
unsigned int y1;
unsigned int z0;
unsigned int z1;
float f;
unsigned int x;
unsigned int y;
unsigned int z;
while (token != NULL)
{
if (strcmp(token, "point") == 0) //point located at (x,y,z), syntax: point [x] [y] [z] [value]
{
assert(read(token, delimiter, 4, &x, &y, &z, &f));
assert(x < config.n);
assert(y < config.n);
assert(z < config.n);
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
if (strcmp(token, "zline") == 0) //line in z direction, syntax: zline [xpos] [ypos] [zstart] [zend] [value]
{
assert(read(token, delimiter, 5, &x, &y, &z0, &z1, &f));
assert(z0 < z1);
assert(x < config.n);
assert(y < config.n);
assert(z1 < config.n);
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "yline") == 0) //line in y direction, syntax: yline [xpos] [zpos] [ystart] [yend] [value]
{
assert(read(token, delimiter, 5, &x, &z, &y0, &y1, &f));
assert(y0 < y1);
assert(x < config.n);
assert(y1 < config.n);
assert(z < config.n);
for (y = y0; y <= y1; y++)
{
assert(y < config.n);
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "xline") == 0) //line in x direction, syntax: xline [ypos] [zpos] [xstart] [xend] [value]
{
assert(read(token, delimiter, 5, &y, &z, &x0, &x1, &f));
assert(x0 < x1);
assert(x1 < config.n);
assert(y < config.n);
assert(z < config.n);
for (x = x0; x <= x1; x++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "zrectangle") == 0) //rectangle from (x0, y0) to (x1, y1) in z plane, syntax: zrectangle [x0] [y0] [x1] [y1] [z] [value]
{
assert(read(token, delimiter, 6, &x0, &y0, &x1, &y1, &z, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(x1 < config.n);
assert(y1 < config.n);
assert(z < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "yrectangle") == 0) //rectangle from (x0, z0) to (x1, z1) in y plane, syntax yrectangle [x0] [z0] [x1] [z1] [y] [value]
{
assert(read(token, delimiter, 6, &x0, &z0, &x1, &z1, &y, &f));
assert(x0 < x1);
assert(z0 < z1);
assert(x1 < config.n);
assert(y < config.n);
assert(z1 < config.n);
for (x = x0; x <= x1; x++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "xrectangle") == 0) ////rectangle from (y0, z0) to (y1, z1) in x plane, syntax xrectangle [y0] [z0] [y1] [z1] [x] [value]
{
assert(read(token, delimiter, 6, &y0, &z0, &y1, &z1, &x, &f));
assert(y0 < y1);
assert(z0 < z1);
assert(x < config.n);
assert(y1 < config.n);
assert(z1 < config.n);
for (y = y0; y <= y1; y++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "prism") == 0) //prism from (x0, y0, z0) to (x1, y1, z1), syntax prism [x0] [y0] [z0] [x1] [y1] [z1] [value]
{
assert(read(token, delimiter, 7, &x0, &y0, &z0, &x1, &y1, &z1, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(z0 < z1);
assert(x1 < config.n);
assert(y1 < config.n);
assert(z1 < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
}
token = strtok(NULL, delimiter);
}
for (x = config.x; x < config.n; x++)
{
for (y = config.y; y < config.n; y++)
{
for (z = config.z; z < config.n; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
config.read_only ++;
}
}
}
}
free(buf);
fclose(handle);
}
int main(int argc, char **argv)
{
if (argc != 3)
{
printf("Usage: %s [config file] [output]\n", argv[0]);
exit(1);
}
settings config;
dim3 block(1,1,1);
dim3 grid(1,1,1);
unsigned long float_mem;
unsigned long bool_mem;
config.iterations = 0;
config.n = 0;
config.threads = 512;
config.x = 0;
config.y = 0;
config.z = 0;
config.dim_3d = false;
char *settings_file = argv[1];
read_config(settings_file, config);
switch (config.threads)
{
case 2048:
block.x = 32; block.y = 32; block.z = 2;
break;
case 1024:
block.x = 32; block.y = 32; block.z = 1;
break;
case 512:
block.x = 16; block.y = 16; block.z = 2;
break;
case 256:
block.x = 16; block.y = 16; block.z = 1;
break;
case 128:
block.x = 8; block.y = 8; block.z = 2;
break;
case 64:
block.x = 8; block.y = 8; block.z = 1;
break;
case 32:
block.x = 4; block.y = 4; block.z = 2;
break;
}
if (!config.dim_3d)
{
block.z = 1;
}
assert(config.n % block.x == 0);
assert(config.n % block.y == 0);
assert(config.n % block.z == 0);
if (config.dim_3d)
{
config.n = next_pow(__max(__max(config.x, config.y), config.z));
grid.x = config.n / block.x;
grid.y = config.n / block.y;
grid.z = config.n / block.z;
float_mem = config.n * config.n * config.n * sizeof(float);
bool_mem = config.n * config.n * config.n * sizeof(bool);
}
else
{
config.n = next_pow(__max(config.x, config.y));
grid.x = config.n / block.x;
grid.y = config.n / block.y;
float_mem = config.n * config.n * sizeof(float);
bool_mem = config.n * config.n * sizeof(bool);
}
float *data = (float *)malloc(float_mem);
bool *read_only = (bool *)malloc(bool_mem);
if (config.dim_3d) { init3d(settings_file, config, data, read_only); }
else { init2d(settings_file, config, data, read_only); }
float *d_z_1;
float *d_z_2;
bool *d_read_only;
cudaEvent_t start;
cudaEvent_t stop;
float compute_time;
double gflops;
unsigned int yshift = (unsigned int) log2((double) config.n);
unsigned int zshift = (unsigned int) log2((double) config.n * config.n);
assert(cudaSuccess == cudaEventCreate(&start));
assert(cudaSuccess == cudaEventCreate(&stop));
assert(cudaSuccess == cudaMalloc((void**) &d_z_1, float_mem));
assert(cudaSuccess == cudaMalloc((void**) &d_z_2, float_mem));
assert(cudaSuccess == cudaMalloc((void**) &d_read_only, bool_mem));
assert(cudaSuccess == cudaMemcpy(d_z_1, data, float_mem, cudaMemcpyHostToDevice));
assert(cudaSuccess == cudaMemcpy(d_read_only, read_only, bool_mem, cudaMemcpyHostToDevice));
assert(cudaSuccess == cudaEventRecord(start, 0));
for (unsigned int i = 0; i < config.iterations; i++)
{
if (config.dim_3d)
{
iterate3d<<<grid, block>>>(d_z_1, d_z_2, d_read_only, yshift, zshift, config.n, config.n * config.n);
cudaThreadSynchronize();
iterate3d<<<grid, block>>>(d_z_2, d_z_1, d_read_only, yshift, zshift, config.n, config.n * config.n);
cudaThreadSynchronize();
if (i % 50 == 0) { printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\bIterations: %u", i); }
}
else
{
iterate2d<<<grid, block>>>(d_z_1, d_z_2, d_read_only, yshift, config.n);
cudaThreadSynchronize();
iterate2d<<<grid, block>>>(d_z_2, d_z_1, d_read_only, yshift, config.n);
cudaThreadSynchronize();
if (i % 500 == 0) { printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\bIterations: %u", i); }
}
}
assert(cudaSuccess == cudaEventRecord(stop, 0));
assert(cudaSuccess == cudaEventSynchronize(stop));
assert(cudaSuccess == cudaEventElapsedTime(&compute_time, start, stop));
printf("\n");
printf("Compute time: %fms\n", compute_time);
if (config.dim_3d) { gflops = ((config.n * config.n * config.n) - config.read_only) * 16.0 * config.iterations / (compute_time * 1000000.0); }
else { gflops = ((config.n * config.n) - config.read_only) * 8.0 * config.iterations / (compute_time * 1000000.0); }
printf("Compute speed: %f GFLOPS\n", gflops);
assert(cudaSuccess == cudaMemcpy(data, d_z_1, float_mem, cudaMemcpyDeviceToHost));
FILE *handle = fopen(argv[2], "w");
assert(handle != NULL);
if (config.dim_3d)
{
for (unsigned int x = 0; x < config.x; x++)
{
for (unsigned int y = 0; y < config.y; y++)
{
for (unsigned int z = 0; z < config.z; z++)
{
fprintf(handle, "%u, %u, %u, %f\n", x, y, z, data[x+(y*config.n)+(z*config.n*config.n)]);
}
}
}
}
else
{
for (unsigned int y = 0; y < config.n; y++)
{
for (unsigned int x = 0; x < config.n; x++)
{
fprintf(handle, "%06.2f", data[x+(y*config.n)]);
if (x == config.n - 1) { fprintf(handle, "\n"); }
else { fprintf(handle, ", "); }
}
}
}
fclose(handle);
assert(cudaSuccess == cudaFree(d_z_1));
assert(cudaSuccess == cudaFree(d_z_2));
assert(cudaSuccess == cudaFree(d_read_only));
free(data);
free(read_only);
return 0;
} | code for sm_80
Function : _Z9iterate3dPfS_Pbjjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0040*/ S2R R7, SR_CTAID.Z ; /* 0x0000000000077919 */
/* 0x000e680000002700 */
/*0050*/ S2R R2, SR_TID.Z ; /* 0x0000000000027919 */
/* 0x000e680000002300 */
/*0060*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000ea80000002500 */
/*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0205 */
/*0090*/ IMAD R7, R7, c[0x0][0x8], R2 ; /* 0x0000020007077a24 */
/* 0x002fca00078e0202 */
/*00a0*/ SHF.L.U32 R2, R7, c[0x0][0x17c], RZ ; /* 0x00005f0007027a19 */
/* 0x000fe200000006ff */
/*00b0*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x004fe200078e0203 */
/*00c0*/ SHF.L.U32 R3, R0, c[0x0][0x178], RZ ; /* 0x00005e0000037a19 */
/* 0x000fc800000006ff */
/*00d0*/ IADD3 R8, R2, R3, R6 ; /* 0x0000000302087210 */
/* 0x000fc80007ffe006 */
/*00e0*/ IADD3 R2, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008027a10 */
/* 0x000fca0007f1e0ff */
/*00f0*/ IMAD.X R3, RZ, RZ, c[0x0][0x174], P0 ; /* 0x00005d00ff037624 */
/* 0x000fca00000e06ff */
/*0100*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1100 */
/*0110*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0120*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0130*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fc80003f05270 */
/*0140*/ ISETP.NE.AND P0, PT, R6, RZ, !P0 ; /* 0x000000ff0600720c */
/* 0x000fc80004705270 */
/*0150*/ ISETP.NE.AND P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80000705270 */
/*0160*/ ISETP.NE.AND P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fc80000705270 */
/*0170*/ ISETP.NE.AND P0, PT, R6, UR4, P0 ; /* 0x0000000406007c0c */
/* 0x000fc80008705270 */
/*0180*/ ISETP.NE.AND P0, PT, R0, UR4, P0 ; /* 0x0000000400007c0c */
/* 0x000fc80008705270 */
/*0190*/ ISETP.NE.AND P0, PT, R7, UR4, P0 ; /* 0x0000000407007c0c */
/* 0x000fda0008705270 */
/*01a0*/ @!P0 LEA R4, P1, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008048a11 */
/* 0x000fc800078210ff */
/*01b0*/ @!P0 LEA.HI.X R5, R8, c[0x0][0x164], RZ, 0x2, P1 ; /* 0x0000590008058a11 */
/* 0x000fca00008f14ff */
/*01c0*/ @!P0 LDG.E R9, [R4.64] ; /* 0x0000000604098981 */
/* 0x000162000c1e1900 */
/*01d0*/ LEA R2, P1, R8.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0008027a11 */
/* 0x040fe200078210ff */
/*01e0*/ BSSY B0, 0x510 ; /* 0x0000032000007945 */
/* 0x000fe60003800000 */
/*01f0*/ LEA.HI.X R3, R8, c[0x0][0x16c], RZ, 0x2, P1 ; /* 0x00005b0008037a11 */
/* 0x000fe200008f14ff */
/*0200*/ @!P0 BRA 0x500 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0210*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x001fe40007ffe0ff */
/*0220*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x000fc40007ffe0ff */
/*0240*/ SHF.L.U32 R11, R4, c[0x0][0x178], RZ ; /* 0x00005e00040b7a19 */
/* 0x000fe400000006ff */
/*0250*/ IADD3 R12, R0, -0x1, RZ ; /* 0xffffffff000c7810 */
/* 0x000fe20007ffe0ff */
/*0260*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0270*/ IADD3 R10, R7, -0x1, RZ ; /* 0xffffffff070a7810 */
/* 0x000fe40007ffe0ff */
/*0280*/ SHF.L.U32 R4, R5, c[0x0][0x17c], RZ ; /* 0x00005f0005047a19 */
/* 0x000fe400000006ff */
/*0290*/ IADD3 R9, R8, R11, RZ ; /* 0x0000000b08097210 */
/* 0x020fe40007ffe0ff */
/*02a0*/ SHF.L.U32 R7, R12, c[0x0][0x178], RZ ; /* 0x00005e000c077a19 */
/* 0x000fc400000006ff */
/*02b0*/ SHF.L.U32 R5, R10, c[0x0][0x17c], RZ ; /* 0x00005f000a057a19 */
/* 0x000fe200000006ff */
/*02c0*/ IMAD.IADD R15, R9.reuse, 0x1, R4 ; /* 0x00000001090f7824 */
/* 0x040fe200078e0204 */
/*02d0*/ IADD3 R10, R8, R7, RZ ; /* 0x00000007080a7210 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R16, R6, -0x1, RZ ; /* 0xffffffff06107810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.IADD R9, R9, 0x1, R5 ; /* 0x0000000109097824 */
/* 0x000fe400078e0205 */
/*0300*/ IMAD.IADD R13, R4, 0x1, R10 ; /* 0x00000001040d7824 */
/* 0x000fe400078e020a */
/*0310*/ IMAD.WIDE.U32 R8, R9, R0, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fe200078e0000 */
/*0320*/ IADD3 R17, R11, R16, RZ ; /* 0x000000100b117210 */
/* 0x000fc60007ffe0ff */
/*0330*/ IMAD.WIDE.U32 R14, R15, R0.reuse, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x080fe200078e0000 */
/*0340*/ IADD3 R19, R4, R17, RZ ; /* 0x0000001104137210 */
/* 0x000fe20007ffe0ff */
/*0350*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ea4000c1e1900 */
/*0360*/ IMAD.IADD R11, R5, 0x1, R10 ; /* 0x00000001050b7824 */
/* 0x000fe400078e020a */
/*0370*/ IMAD.WIDE.U32 R12, R13, R0.reuse, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x080fe200078e0000 */
/*0380*/ LDG.E R6, [R14.64] ; /* 0x000000060e067981 */
/* 0x0000a6000c1e1900 */
/*0390*/ IMAD.WIDE.U32 R10, R11, R0, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fc400078e0000 */
/*03a0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ee4000c1e1900 */
/*03b0*/ IMAD.IADD R18, R7, 0x1, R16 ; /* 0x0000000107127824 */
/* 0x000fe200078e0210 */
/*03c0*/ IADD3 R7, R5, R17, RZ ; /* 0x0000001105077210 */
/* 0x000fe20007ffe0ff */
/*03d0*/ IMAD.WIDE.U32 R16, R19, R0.reuse, c[0x0][0x160] ; /* 0x0000580013107625 */
/* 0x080fe200078e0000 */
/*03e0*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000f26000c1e1900 */
/*03f0*/ IMAD.IADD R19, R4, 0x1, R18 ; /* 0x0000000104137824 */
/* 0x000fe400078e0212 */
/*0400*/ IMAD.WIDE.U32 R14, R7, R0, c[0x0][0x160] ; /* 0x00005800070e7625 */
/* 0x001fe200078e0000 */
/*0410*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000f22000c1e1900 */
/*0420*/ IADD3 R7, R5, R18, RZ ; /* 0x0000001205077210 */
/* 0x000fc40007ffe0ff */
/*0430*/ IMAD.WIDE.U32 R4, R19, R0.reuse, c[0x0][0x160] ; /* 0x0000580013047625 */
/* 0x080fe400078e0000 */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f24000c1e1900 */
/*0450*/ IMAD.WIDE.U32 R18, R7, R0, c[0x0][0x160] ; /* 0x0000580007127625 */
/* 0x000fe400078e0000 */
/*0460*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000f22000c1e1900 */
/*0480*/ FADD R9, R9, R6 ; /* 0x0000000609097221 */
/* 0x004fc80000000000 */
/*0490*/ FADD R9, R9, R12 ; /* 0x0000000c09097221 */
/* 0x008fc80000000000 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fc80000000000 */
/*04b0*/ FADD R9, R9, R16 ; /* 0x0000001009097221 */
/* 0x000fc80000000000 */
/*04c0*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x000fc80000000000 */
/*04d0*/ FADD R9, R9, R4 ; /* 0x0000000409097221 */
/* 0x000fc80000000000 */
/*04e0*/ FADD R9, R9, R18 ; /* 0x0000001209097221 */
/* 0x000fc80000000000 */
/*04f0*/ FMUL R9, R9, 0.125 ; /* 0x3e00000009097820 */
/* 0x000fe40000400000 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x020fe2000c101906 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9iterate2dPfS_Pbjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x001fe400078e0202 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0203 */
/*0080*/ SHF.L.U32 R3, R7, c[0x0][0x178], RZ ; /* 0x00005e0007037a19 */
/* 0x000fca00000006ff */
/*0090*/ IMAD.IADD R6, R0, 0x1, R3 ; /* 0x0000000100067824 */
/* 0x000fca00078e0203 */
/*00a0*/ IADD3 R4, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006047a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R5, RZ, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00ff057a10 */
/* 0x000fca00007fe4ff */
/*00c0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1100 */
/*00d0*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe20000000800 */
/*00e0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*00f0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fc6000fffe03f */
/*0100*/ IMAD.WIDE.U32 R2, R6, R13, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc600078e000d */
/*0110*/ ISETP.NE.AND P1, PT, R7, UR4, PT ; /* 0x0000000407007c0c */
/* 0x000fc8000bf25270 */
/*0120*/ ISETP.NE.AND P1, PT, R0, UR4, P1 ; /* 0x0000000400007c0c */
/* 0x000fe40008f25270 */
/*0130*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fc80003f05270 */
/*0140*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80000702670 */
/*0150*/ ISETP.EQ.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000702670 */
/*0160*/ @P1 BRA !P0, 0x1c0 ; /* 0x0000005000001947 */
/* 0x000fea0004000000 */
/*0170*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x000fc800078010ff */
/*0180*/ LEA.HI.X R5, R6, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fcc00000f14ff */
/*0190*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101906 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R4, R7.reuse, 0x1, RZ ; /* 0x0000000107047810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ IADD3 R9, R7, -0x1, RZ ; /* 0xffffffff07097810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ SHF.L.U32 R5, R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a19 */
/* 0x000fe400000006ff */
/*01f0*/ IADD3 R8, R0, -0x1, RZ ; /* 0xffffffff00087810 */
/* 0x000fc40007ffe0ff */
/*0200*/ IADD3 R6, R0.reuse, R7, RZ ; /* 0x0000000700067210 */
/* 0x040fe40007ffe0ff */
/*0210*/ IADD3 R4, R0, 0x1, R5 ; /* 0x0000000100047810 */
/* 0x000fe40007ffe005 */
/*0220*/ SHF.L.U32 R11, R9, c[0x0][0x178], RZ ; /* 0x00005e00090b7a19 */
/* 0x000fe200000006ff */
/*0230*/ IMAD.IADD R9, R5, 0x1, R8 ; /* 0x0000000105097824 */
/* 0x000fe400078e0208 */
/*0240*/ IMAD.WIDE.U32 R6, R6, R13, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e000d */
/*0250*/ IADD3 R11, R8, R11, RZ ; /* 0x0000000b080b7210 */
/* 0x000fc60007ffe0ff */
/*0260*/ IMAD.WIDE.U32 R4, R4, R13.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e000d */
/*0270*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R8, R9, R13.reuse, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x080fe400078e000d */
/*0290*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R10, R11, R13, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fe400078e000d */
/*02b0*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000f22000c1e1900 */
/*02d0*/ FADD R0, R6, R5 ; /* 0x0000000506007221 */
/* 0x004fc80000000000 */
/*02e0*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x008fc80000000000 */
/*02f0*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x010fc80000000000 */
/*0300*/ FMUL R13, R0, 0.25 ; /* 0x3e800000000d7820 */
/* 0x000fca0000400000 */
/*0310*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101906 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <assert.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <stdarg.h>
struct settings
{
unsigned int iterations;
unsigned int x;
unsigned int y;
unsigned int z;
unsigned int n;
bool dim_3d;
unsigned int threads;
unsigned long read_only;
};
bool read(char *token, const char *delim, int argc, ...)
{
va_list argv;
va_start(argv, argc);
unsigned int *temp_int;
float *temp_float;
unsigned int i;
for (i = 0; i < argc; i++)
{
token = strtok(NULL, delim);
if (i == argc - 1)
{
temp_float = (float *) va_arg(argv, float *);
if (token != NULL) { *temp_float = atof(token); }
else { return false; }
}
else
{
temp_int = (unsigned int *) va_arg(argv, unsigned int*);
if (token != NULL) { *temp_int = atoi(token); }
else { return false; }
}
}
return true;
}
unsigned int next_pow(unsigned int x)
{
unsigned int n = 1;
while (n < x) { n <<= 1; }
return n;
}
unsigned int __max(unsigned int a, unsigned int b)
{
if (a > b) { return a; }
return b;
}
__global__ void iterate2d(float *from, float *to, bool *read_only, unsigned int yshift, unsigned int N)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
if (read_only[x+(y<<yshift)] == false && x != 0 && y != 0 && x != (N - 1) && y != (N - 1))
{
to[x+(y<<yshift)] = (from[(x+1)+((y+1)<<yshift)] + from[(x+1)+((y-1))] + from[(x-1)+((y+1)<<yshift)] + from[(x-1)+((y-1)<<yshift)]) / 4;
}
else
{
to[x+(y<<yshift)] = from[x+(y<<yshift)];
}
}
__global__ void iterate3d(float *from, float *to, bool *read_only, unsigned int yshift, unsigned int zshift, unsigned int N, unsigned int NN)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int z = blockIdx.z * blockDim.z + threadIdx.z;
if (read_only[x+(y<<yshift)+(z<<zshift)] == false && x != 0 && y != 0 && z != 0 && x != (N - 1) && y != (N - 1) && z != (N - 1))
{
to[x+(y<<yshift)+(z<<zshift)] = (from[(x+1)+((y+1)<<yshift)+((z+1)<<zshift)] + from[(x+1)+((y+1)<<yshift)+((z-1)<<zshift)] + from[(x+1)+((y-1)<<yshift)+((z+1)<<zshift)] + from[(x+1)+((y-1)<<yshift)+((z-1)<<zshift)] + from[(x-1)+((y+1)<<yshift)+((z+1)<<zshift)] + from[(x-1)+((y+1)<<yshift)+((z-1)<<zshift)] + from[(x-1)+((y-1)<<yshift)+((z+1)<<zshift)] + from[(x-1)+((y-1)<<yshift)+((z-1)<<zshift)]) / 8;
}
else
{
to[x+(y<<yshift)+(z<<zshift)] = from[x+(y<<yshift)+(z<<zshift)];
}
}
void read_config(char *settings_file, settings &config)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
memset(buf, 0, size + 1);
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
while (token != NULL)
{
if (strcmp(token, "iterations") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.iterations = atoi(token); }
}
else if (strcmp(token, "x") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.x = atoi(token); }
}
else if (strcmp(token, "y") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.y = atoi(token); }
}
else if (strcmp(token, "z") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.z = atoi(token); }
}
else if (strcmp(token, "threads") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.threads = atoi(token); }
}
else if (strcmp(token, "2d") == 0)
{
config.dim_3d = false;
}
else if (strcmp(token, "3d") == 0)
{
config.dim_3d = true;
}
token = strtok(NULL, delimiter);
}
free(buf);
fclose(handle);
}
void init2d(char *settings_file, settings &config, float *data, bool *read_only)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
for(unsigned long i = 0; i < config.n * config.n; i++)
{
data[i] = 0.0f;
read_only[i] = false;
}
config.read_only = 0;
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
unsigned int x0;
unsigned int x1;
unsigned int y0;
unsigned int y1;
float f;
unsigned int x;
unsigned int y;
while (token != NULL)
{
if (strcmp(token, "point") == 0) //point located at (x,y), syntax: point [x] [y] [value]
{
assert(read(token, delimiter, 3, &x, &y, &f));
assert(x < config.n);
assert(y < config.n);
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
if (strcmp(token, "yline") == 0) //line in y direction, syntax: yline [xpos] [ystart] [yend] [value]
{
assert(read(token, delimiter, 4, &x, &y0, &y1, &f));
assert(y0 < y1);
assert(x < config.n);
assert(y1 < config.n);
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
else if (strcmp(token, "xline") == 0) //line in x direction, syntax: xline [ypos] [xstart] [xend] [value]
{
assert(read(token, delimiter, 4, &y, &x0, &x1, &f));
assert(x0 < x1);
assert(y < config.n);
assert(x1 < config.n);
for (x = x0; x <= x1; x++)
{
assert(x < config.n);
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
else if (strcmp(token, "rectangle") == 0) //rectangle from (x0, y0) to (x1, y1), syntax: square [x0] [y0] [x1] [y1] [value]
{
assert(read(token, delimiter, 5, &x0, &y0, &x1, &y1, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(x1 < config.n);
assert(y1 < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
}
token = strtok(NULL, delimiter);
}
for (x = config.x; x < config.n; x++)
{
for (y = config.y; y < config.n; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
}
}
free(buf);
fclose(handle);
}
void init3d(char *settings_file, settings &config, float *data, bool *read_only)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
for(unsigned long i = 0; i < config.n * config.n * config.n; i++)
{
data[i] = 0.0f;
read_only[i] = false;
}
config.read_only = 0;
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
unsigned int x0;
unsigned int x1;
unsigned int y0;
unsigned int y1;
unsigned int z0;
unsigned int z1;
float f;
unsigned int x;
unsigned int y;
unsigned int z;
while (token != NULL)
{
if (strcmp(token, "point") == 0) //point located at (x,y,z), syntax: point [x] [y] [z] [value]
{
assert(read(token, delimiter, 4, &x, &y, &z, &f));
assert(x < config.n);
assert(y < config.n);
assert(z < config.n);
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
if (strcmp(token, "zline") == 0) //line in z direction, syntax: zline [xpos] [ypos] [zstart] [zend] [value]
{
assert(read(token, delimiter, 5, &x, &y, &z0, &z1, &f));
assert(z0 < z1);
assert(x < config.n);
assert(y < config.n);
assert(z1 < config.n);
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "yline") == 0) //line in y direction, syntax: yline [xpos] [zpos] [ystart] [yend] [value]
{
assert(read(token, delimiter, 5, &x, &z, &y0, &y1, &f));
assert(y0 < y1);
assert(x < config.n);
assert(y1 < config.n);
assert(z < config.n);
for (y = y0; y <= y1; y++)
{
assert(y < config.n);
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "xline") == 0) //line in x direction, syntax: xline [ypos] [zpos] [xstart] [xend] [value]
{
assert(read(token, delimiter, 5, &y, &z, &x0, &x1, &f));
assert(x0 < x1);
assert(x1 < config.n);
assert(y < config.n);
assert(z < config.n);
for (x = x0; x <= x1; x++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "zrectangle") == 0) //rectangle from (x0, y0) to (x1, y1) in z plane, syntax: zrectangle [x0] [y0] [x1] [y1] [z] [value]
{
assert(read(token, delimiter, 6, &x0, &y0, &x1, &y1, &z, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(x1 < config.n);
assert(y1 < config.n);
assert(z < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "yrectangle") == 0) //rectangle from (x0, z0) to (x1, z1) in y plane, syntax yrectangle [x0] [z0] [x1] [z1] [y] [value]
{
assert(read(token, delimiter, 6, &x0, &z0, &x1, &z1, &y, &f));
assert(x0 < x1);
assert(z0 < z1);
assert(x1 < config.n);
assert(y < config.n);
assert(z1 < config.n);
for (x = x0; x <= x1; x++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "xrectangle") == 0) ////rectangle from (y0, z0) to (y1, z1) in x plane, syntax xrectangle [y0] [z0] [y1] [z1] [x] [value]
{
assert(read(token, delimiter, 6, &y0, &z0, &y1, &z1, &x, &f));
assert(y0 < y1);
assert(z0 < z1);
assert(x < config.n);
assert(y1 < config.n);
assert(z1 < config.n);
for (y = y0; y <= y1; y++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "prism") == 0) //prism from (x0, y0, z0) to (x1, y1, z1), syntax prism [x0] [y0] [z0] [x1] [y1] [z1] [value]
{
assert(read(token, delimiter, 7, &x0, &y0, &z0, &x1, &y1, &z1, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(z0 < z1);
assert(x1 < config.n);
assert(y1 < config.n);
assert(z1 < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
}
token = strtok(NULL, delimiter);
}
for (x = config.x; x < config.n; x++)
{
for (y = config.y; y < config.n; y++)
{
for (z = config.z; z < config.n; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
config.read_only ++;
}
}
}
}
free(buf);
fclose(handle);
}
int main(int argc, char **argv)
{
if (argc != 3)
{
printf("Usage: %s [config file] [output]\n", argv[0]);
exit(1);
}
settings config;
dim3 block(1,1,1);
dim3 grid(1,1,1);
unsigned long float_mem;
unsigned long bool_mem;
config.iterations = 0;
config.n = 0;
config.threads = 512;
config.x = 0;
config.y = 0;
config.z = 0;
config.dim_3d = false;
char *settings_file = argv[1];
read_config(settings_file, config);
switch (config.threads)
{
case 2048:
block.x = 32; block.y = 32; block.z = 2;
break;
case 1024:
block.x = 32; block.y = 32; block.z = 1;
break;
case 512:
block.x = 16; block.y = 16; block.z = 2;
break;
case 256:
block.x = 16; block.y = 16; block.z = 1;
break;
case 128:
block.x = 8; block.y = 8; block.z = 2;
break;
case 64:
block.x = 8; block.y = 8; block.z = 1;
break;
case 32:
block.x = 4; block.y = 4; block.z = 2;
break;
}
if (!config.dim_3d)
{
block.z = 1;
}
assert(config.n % block.x == 0);
assert(config.n % block.y == 0);
assert(config.n % block.z == 0);
if (config.dim_3d)
{
config.n = next_pow(__max(__max(config.x, config.y), config.z));
grid.x = config.n / block.x;
grid.y = config.n / block.y;
grid.z = config.n / block.z;
float_mem = config.n * config.n * config.n * sizeof(float);
bool_mem = config.n * config.n * config.n * sizeof(bool);
}
else
{
config.n = next_pow(__max(config.x, config.y));
grid.x = config.n / block.x;
grid.y = config.n / block.y;
float_mem = config.n * config.n * sizeof(float);
bool_mem = config.n * config.n * sizeof(bool);
}
float *data = (float *)malloc(float_mem);
bool *read_only = (bool *)malloc(bool_mem);
if (config.dim_3d) { init3d(settings_file, config, data, read_only); }
else { init2d(settings_file, config, data, read_only); }
float *d_z_1;
float *d_z_2;
bool *d_read_only;
cudaEvent_t start;
cudaEvent_t stop;
float compute_time;
double gflops;
unsigned int yshift = (unsigned int) log2((double) config.n);
unsigned int zshift = (unsigned int) log2((double) config.n * config.n);
assert(cudaSuccess == cudaEventCreate(&start));
assert(cudaSuccess == cudaEventCreate(&stop));
assert(cudaSuccess == cudaMalloc((void**) &d_z_1, float_mem));
assert(cudaSuccess == cudaMalloc((void**) &d_z_2, float_mem));
assert(cudaSuccess == cudaMalloc((void**) &d_read_only, bool_mem));
assert(cudaSuccess == cudaMemcpy(d_z_1, data, float_mem, cudaMemcpyHostToDevice));
assert(cudaSuccess == cudaMemcpy(d_read_only, read_only, bool_mem, cudaMemcpyHostToDevice));
assert(cudaSuccess == cudaEventRecord(start, 0));
for (unsigned int i = 0; i < config.iterations; i++)
{
if (config.dim_3d)
{
iterate3d<<<grid, block>>>(d_z_1, d_z_2, d_read_only, yshift, zshift, config.n, config.n * config.n);
cudaThreadSynchronize();
iterate3d<<<grid, block>>>(d_z_2, d_z_1, d_read_only, yshift, zshift, config.n, config.n * config.n);
cudaThreadSynchronize();
if (i % 50 == 0) { printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\bIterations: %u", i); }
}
else
{
iterate2d<<<grid, block>>>(d_z_1, d_z_2, d_read_only, yshift, config.n);
cudaThreadSynchronize();
iterate2d<<<grid, block>>>(d_z_2, d_z_1, d_read_only, yshift, config.n);
cudaThreadSynchronize();
if (i % 500 == 0) { printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\bIterations: %u", i); }
}
}
assert(cudaSuccess == cudaEventRecord(stop, 0));
assert(cudaSuccess == cudaEventSynchronize(stop));
assert(cudaSuccess == cudaEventElapsedTime(&compute_time, start, stop));
printf("\n");
printf("Compute time: %fms\n", compute_time);
if (config.dim_3d) { gflops = ((config.n * config.n * config.n) - config.read_only) * 16.0 * config.iterations / (compute_time * 1000000.0); }
else { gflops = ((config.n * config.n) - config.read_only) * 8.0 * config.iterations / (compute_time * 1000000.0); }
printf("Compute speed: %f GFLOPS\n", gflops);
assert(cudaSuccess == cudaMemcpy(data, d_z_1, float_mem, cudaMemcpyDeviceToHost));
FILE *handle = fopen(argv[2], "w");
assert(handle != NULL);
if (config.dim_3d)
{
for (unsigned int x = 0; x < config.x; x++)
{
for (unsigned int y = 0; y < config.y; y++)
{
for (unsigned int z = 0; z < config.z; z++)
{
fprintf(handle, "%u, %u, %u, %f\n", x, y, z, data[x+(y*config.n)+(z*config.n*config.n)]);
}
}
}
}
else
{
for (unsigned int y = 0; y < config.n; y++)
{
for (unsigned int x = 0; x < config.n; x++)
{
fprintf(handle, "%06.2f", data[x+(y*config.n)]);
if (x == config.n - 1) { fprintf(handle, "\n"); }
else { fprintf(handle, ", "); }
}
}
}
fclose(handle);
assert(cudaSuccess == cudaFree(d_z_1));
assert(cudaSuccess == cudaFree(d_z_2));
assert(cudaSuccess == cudaFree(d_read_only));
free(data);
free(read_only);
return 0;
} | #include <hip/hip_runtime.h>
#include <assert.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <stdarg.h>
struct settings
{
unsigned int iterations;
unsigned int x;
unsigned int y;
unsigned int z;
unsigned int n;
bool dim_3d;
unsigned int threads;
unsigned long read_only;
};
bool read(char *token, const char *delim, int argc, ...)
{
va_list argv;
va_start(argv, argc);
unsigned int *temp_int;
float *temp_float;
unsigned int i;
for (i = 0; i < argc; i++)
{
token = strtok(NULL, delim);
if (i == argc - 1)
{
temp_float = (float *) va_arg(argv, float *);
if (token != NULL) { *temp_float = atof(token); }
else { return false; }
}
else
{
temp_int = (unsigned int *) va_arg(argv, unsigned int*);
if (token != NULL) { *temp_int = atoi(token); }
else { return false; }
}
}
return true;
}
unsigned int next_pow(unsigned int x)
{
unsigned int n = 1;
while (n < x) { n <<= 1; }
return n;
}
unsigned int __max(unsigned int a, unsigned int b)
{
if (a > b) { return a; }
return b;
}
__global__ void iterate2d(float *from, float *to, bool *read_only, unsigned int yshift, unsigned int N)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
if (read_only[x+(y<<yshift)] == false && x != 0 && y != 0 && x != (N - 1) && y != (N - 1))
{
to[x+(y<<yshift)] = (from[(x+1)+((y+1)<<yshift)] + from[(x+1)+((y-1))] + from[(x-1)+((y+1)<<yshift)] + from[(x-1)+((y-1)<<yshift)]) / 4;
}
else
{
to[x+(y<<yshift)] = from[x+(y<<yshift)];
}
}
__global__ void iterate3d(float *from, float *to, bool *read_only, unsigned int yshift, unsigned int zshift, unsigned int N, unsigned int NN)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int z = blockIdx.z * blockDim.z + threadIdx.z;
if (read_only[x+(y<<yshift)+(z<<zshift)] == false && x != 0 && y != 0 && z != 0 && x != (N - 1) && y != (N - 1) && z != (N - 1))
{
to[x+(y<<yshift)+(z<<zshift)] = (from[(x+1)+((y+1)<<yshift)+((z+1)<<zshift)] + from[(x+1)+((y+1)<<yshift)+((z-1)<<zshift)] + from[(x+1)+((y-1)<<yshift)+((z+1)<<zshift)] + from[(x+1)+((y-1)<<yshift)+((z-1)<<zshift)] + from[(x-1)+((y+1)<<yshift)+((z+1)<<zshift)] + from[(x-1)+((y+1)<<yshift)+((z-1)<<zshift)] + from[(x-1)+((y-1)<<yshift)+((z+1)<<zshift)] + from[(x-1)+((y-1)<<yshift)+((z-1)<<zshift)]) / 8;
}
else
{
to[x+(y<<yshift)+(z<<zshift)] = from[x+(y<<yshift)+(z<<zshift)];
}
}
void read_config(char *settings_file, settings &config)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
memset(buf, 0, size + 1);
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
while (token != NULL)
{
if (strcmp(token, "iterations") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.iterations = atoi(token); }
}
else if (strcmp(token, "x") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.x = atoi(token); }
}
else if (strcmp(token, "y") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.y = atoi(token); }
}
else if (strcmp(token, "z") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.z = atoi(token); }
}
else if (strcmp(token, "threads") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.threads = atoi(token); }
}
else if (strcmp(token, "2d") == 0)
{
config.dim_3d = false;
}
else if (strcmp(token, "3d") == 0)
{
config.dim_3d = true;
}
token = strtok(NULL, delimiter);
}
free(buf);
fclose(handle);
}
void init2d(char *settings_file, settings &config, float *data, bool *read_only)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
for(unsigned long i = 0; i < config.n * config.n; i++)
{
data[i] = 0.0f;
read_only[i] = false;
}
config.read_only = 0;
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
unsigned int x0;
unsigned int x1;
unsigned int y0;
unsigned int y1;
float f;
unsigned int x;
unsigned int y;
while (token != NULL)
{
if (strcmp(token, "point") == 0) //point located at (x,y), syntax: point [x] [y] [value]
{
assert(read(token, delimiter, 3, &x, &y, &f));
assert(x < config.n);
assert(y < config.n);
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
if (strcmp(token, "yline") == 0) //line in y direction, syntax: yline [xpos] [ystart] [yend] [value]
{
assert(read(token, delimiter, 4, &x, &y0, &y1, &f));
assert(y0 < y1);
assert(x < config.n);
assert(y1 < config.n);
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
else if (strcmp(token, "xline") == 0) //line in x direction, syntax: xline [ypos] [xstart] [xend] [value]
{
assert(read(token, delimiter, 4, &y, &x0, &x1, &f));
assert(x0 < x1);
assert(y < config.n);
assert(x1 < config.n);
for (x = x0; x <= x1; x++)
{
assert(x < config.n);
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
else if (strcmp(token, "rectangle") == 0) //rectangle from (x0, y0) to (x1, y1), syntax: square [x0] [y0] [x1] [y1] [value]
{
assert(read(token, delimiter, 5, &x0, &y0, &x1, &y1, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(x1 < config.n);
assert(y1 < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
}
token = strtok(NULL, delimiter);
}
for (x = config.x; x < config.n; x++)
{
for (y = config.y; y < config.n; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
}
}
free(buf);
fclose(handle);
}
void init3d(char *settings_file, settings &config, float *data, bool *read_only)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
for(unsigned long i = 0; i < config.n * config.n * config.n; i++)
{
data[i] = 0.0f;
read_only[i] = false;
}
config.read_only = 0;
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
unsigned int x0;
unsigned int x1;
unsigned int y0;
unsigned int y1;
unsigned int z0;
unsigned int z1;
float f;
unsigned int x;
unsigned int y;
unsigned int z;
while (token != NULL)
{
if (strcmp(token, "point") == 0) //point located at (x,y,z), syntax: point [x] [y] [z] [value]
{
assert(read(token, delimiter, 4, &x, &y, &z, &f));
assert(x < config.n);
assert(y < config.n);
assert(z < config.n);
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
if (strcmp(token, "zline") == 0) //line in z direction, syntax: zline [xpos] [ypos] [zstart] [zend] [value]
{
assert(read(token, delimiter, 5, &x, &y, &z0, &z1, &f));
assert(z0 < z1);
assert(x < config.n);
assert(y < config.n);
assert(z1 < config.n);
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "yline") == 0) //line in y direction, syntax: yline [xpos] [zpos] [ystart] [yend] [value]
{
assert(read(token, delimiter, 5, &x, &z, &y0, &y1, &f));
assert(y0 < y1);
assert(x < config.n);
assert(y1 < config.n);
assert(z < config.n);
for (y = y0; y <= y1; y++)
{
assert(y < config.n);
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "xline") == 0) //line in x direction, syntax: xline [ypos] [zpos] [xstart] [xend] [value]
{
assert(read(token, delimiter, 5, &y, &z, &x0, &x1, &f));
assert(x0 < x1);
assert(x1 < config.n);
assert(y < config.n);
assert(z < config.n);
for (x = x0; x <= x1; x++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "zrectangle") == 0) //rectangle from (x0, y0) to (x1, y1) in z plane, syntax: zrectangle [x0] [y0] [x1] [y1] [z] [value]
{
assert(read(token, delimiter, 6, &x0, &y0, &x1, &y1, &z, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(x1 < config.n);
assert(y1 < config.n);
assert(z < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "yrectangle") == 0) //rectangle from (x0, z0) to (x1, z1) in y plane, syntax yrectangle [x0] [z0] [x1] [z1] [y] [value]
{
assert(read(token, delimiter, 6, &x0, &z0, &x1, &z1, &y, &f));
assert(x0 < x1);
assert(z0 < z1);
assert(x1 < config.n);
assert(y < config.n);
assert(z1 < config.n);
for (x = x0; x <= x1; x++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "xrectangle") == 0) ////rectangle from (y0, z0) to (y1, z1) in x plane, syntax xrectangle [y0] [z0] [y1] [z1] [x] [value]
{
assert(read(token, delimiter, 6, &y0, &z0, &y1, &z1, &x, &f));
assert(y0 < y1);
assert(z0 < z1);
assert(x < config.n);
assert(y1 < config.n);
assert(z1 < config.n);
for (y = y0; y <= y1; y++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "prism") == 0) //prism from (x0, y0, z0) to (x1, y1, z1), syntax prism [x0] [y0] [z0] [x1] [y1] [z1] [value]
{
assert(read(token, delimiter, 7, &x0, &y0, &z0, &x1, &y1, &z1, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(z0 < z1);
assert(x1 < config.n);
assert(y1 < config.n);
assert(z1 < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
}
token = strtok(NULL, delimiter);
}
for (x = config.x; x < config.n; x++)
{
for (y = config.y; y < config.n; y++)
{
for (z = config.z; z < config.n; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
config.read_only ++;
}
}
}
}
free(buf);
fclose(handle);
}
int main(int argc, char **argv)
{
if (argc != 3)
{
printf("Usage: %s [config file] [output]\n", argv[0]);
exit(1);
}
settings config;
dim3 block(1,1,1);
dim3 grid(1,1,1);
unsigned long float_mem;
unsigned long bool_mem;
config.iterations = 0;
config.n = 0;
config.threads = 512;
config.x = 0;
config.y = 0;
config.z = 0;
config.dim_3d = false;
char *settings_file = argv[1];
read_config(settings_file, config);
switch (config.threads)
{
case 2048:
block.x = 32; block.y = 32; block.z = 2;
break;
case 1024:
block.x = 32; block.y = 32; block.z = 1;
break;
case 512:
block.x = 16; block.y = 16; block.z = 2;
break;
case 256:
block.x = 16; block.y = 16; block.z = 1;
break;
case 128:
block.x = 8; block.y = 8; block.z = 2;
break;
case 64:
block.x = 8; block.y = 8; block.z = 1;
break;
case 32:
block.x = 4; block.y = 4; block.z = 2;
break;
}
if (!config.dim_3d)
{
block.z = 1;
}
assert(config.n % block.x == 0);
assert(config.n % block.y == 0);
assert(config.n % block.z == 0);
if (config.dim_3d)
{
config.n = next_pow(__max(__max(config.x, config.y), config.z));
grid.x = config.n / block.x;
grid.y = config.n / block.y;
grid.z = config.n / block.z;
float_mem = config.n * config.n * config.n * sizeof(float);
bool_mem = config.n * config.n * config.n * sizeof(bool);
}
else
{
config.n = next_pow(__max(config.x, config.y));
grid.x = config.n / block.x;
grid.y = config.n / block.y;
float_mem = config.n * config.n * sizeof(float);
bool_mem = config.n * config.n * sizeof(bool);
}
float *data = (float *)malloc(float_mem);
bool *read_only = (bool *)malloc(bool_mem);
if (config.dim_3d) { init3d(settings_file, config, data, read_only); }
else { init2d(settings_file, config, data, read_only); }
float *d_z_1;
float *d_z_2;
bool *d_read_only;
hipEvent_t start;
hipEvent_t stop;
float compute_time;
double gflops;
unsigned int yshift = (unsigned int) log2((double) config.n);
unsigned int zshift = (unsigned int) log2((double) config.n * config.n);
assert(hipSuccess == hipEventCreate(&start));
assert(hipSuccess == hipEventCreate(&stop));
assert(hipSuccess == hipMalloc((void**) &d_z_1, float_mem));
assert(hipSuccess == hipMalloc((void**) &d_z_2, float_mem));
assert(hipSuccess == hipMalloc((void**) &d_read_only, bool_mem));
assert(hipSuccess == hipMemcpy(d_z_1, data, float_mem, hipMemcpyHostToDevice));
assert(hipSuccess == hipMemcpy(d_read_only, read_only, bool_mem, hipMemcpyHostToDevice));
assert(hipSuccess == hipEventRecord(start, 0));
for (unsigned int i = 0; i < config.iterations; i++)
{
if (config.dim_3d)
{
iterate3d<<<grid, block>>>(d_z_1, d_z_2, d_read_only, yshift, zshift, config.n, config.n * config.n);
hipDeviceSynchronize();
iterate3d<<<grid, block>>>(d_z_2, d_z_1, d_read_only, yshift, zshift, config.n, config.n * config.n);
hipDeviceSynchronize();
if (i % 50 == 0) { printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\bIterations: %u", i); }
}
else
{
iterate2d<<<grid, block>>>(d_z_1, d_z_2, d_read_only, yshift, config.n);
hipDeviceSynchronize();
iterate2d<<<grid, block>>>(d_z_2, d_z_1, d_read_only, yshift, config.n);
hipDeviceSynchronize();
if (i % 500 == 0) { printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\bIterations: %u", i); }
}
}
assert(hipSuccess == hipEventRecord(stop, 0));
assert(hipSuccess == hipEventSynchronize(stop));
assert(hipSuccess == hipEventElapsedTime(&compute_time, start, stop));
printf("\n");
printf("Compute time: %fms\n", compute_time);
if (config.dim_3d) { gflops = ((config.n * config.n * config.n) - config.read_only) * 16.0 * config.iterations / (compute_time * 1000000.0); }
else { gflops = ((config.n * config.n) - config.read_only) * 8.0 * config.iterations / (compute_time * 1000000.0); }
printf("Compute speed: %f GFLOPS\n", gflops);
assert(hipSuccess == hipMemcpy(data, d_z_1, float_mem, hipMemcpyDeviceToHost));
FILE *handle = fopen(argv[2], "w");
assert(handle != NULL);
if (config.dim_3d)
{
for (unsigned int x = 0; x < config.x; x++)
{
for (unsigned int y = 0; y < config.y; y++)
{
for (unsigned int z = 0; z < config.z; z++)
{
fprintf(handle, "%u, %u, %u, %f\n", x, y, z, data[x+(y*config.n)+(z*config.n*config.n)]);
}
}
}
}
else
{
for (unsigned int y = 0; y < config.n; y++)
{
for (unsigned int x = 0; x < config.n; x++)
{
fprintf(handle, "%06.2f", data[x+(y*config.n)]);
if (x == config.n - 1) { fprintf(handle, "\n"); }
else { fprintf(handle, ", "); }
}
}
}
fclose(handle);
assert(hipSuccess == hipFree(d_z_1));
assert(hipSuccess == hipFree(d_z_2));
assert(hipSuccess == hipFree(d_read_only));
free(data);
free(read_only);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <assert.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <stdarg.h>
struct settings
{
unsigned int iterations;
unsigned int x;
unsigned int y;
unsigned int z;
unsigned int n;
bool dim_3d;
unsigned int threads;
unsigned long read_only;
};
bool read(char *token, const char *delim, int argc, ...)
{
va_list argv;
va_start(argv, argc);
unsigned int *temp_int;
float *temp_float;
unsigned int i;
for (i = 0; i < argc; i++)
{
token = strtok(NULL, delim);
if (i == argc - 1)
{
temp_float = (float *) va_arg(argv, float *);
if (token != NULL) { *temp_float = atof(token); }
else { return false; }
}
else
{
temp_int = (unsigned int *) va_arg(argv, unsigned int*);
if (token != NULL) { *temp_int = atoi(token); }
else { return false; }
}
}
return true;
}
unsigned int next_pow(unsigned int x)
{
unsigned int n = 1;
while (n < x) { n <<= 1; }
return n;
}
unsigned int __max(unsigned int a, unsigned int b)
{
if (a > b) { return a; }
return b;
}
__global__ void iterate2d(float *from, float *to, bool *read_only, unsigned int yshift, unsigned int N)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
if (read_only[x+(y<<yshift)] == false && x != 0 && y != 0 && x != (N - 1) && y != (N - 1))
{
to[x+(y<<yshift)] = (from[(x+1)+((y+1)<<yshift)] + from[(x+1)+((y-1))] + from[(x-1)+((y+1)<<yshift)] + from[(x-1)+((y-1)<<yshift)]) / 4;
}
else
{
to[x+(y<<yshift)] = from[x+(y<<yshift)];
}
}
__global__ void iterate3d(float *from, float *to, bool *read_only, unsigned int yshift, unsigned int zshift, unsigned int N, unsigned int NN)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int z = blockIdx.z * blockDim.z + threadIdx.z;
if (read_only[x+(y<<yshift)+(z<<zshift)] == false && x != 0 && y != 0 && z != 0 && x != (N - 1) && y != (N - 1) && z != (N - 1))
{
to[x+(y<<yshift)+(z<<zshift)] = (from[(x+1)+((y+1)<<yshift)+((z+1)<<zshift)] + from[(x+1)+((y+1)<<yshift)+((z-1)<<zshift)] + from[(x+1)+((y-1)<<yshift)+((z+1)<<zshift)] + from[(x+1)+((y-1)<<yshift)+((z-1)<<zshift)] + from[(x-1)+((y+1)<<yshift)+((z+1)<<zshift)] + from[(x-1)+((y+1)<<yshift)+((z-1)<<zshift)] + from[(x-1)+((y-1)<<yshift)+((z+1)<<zshift)] + from[(x-1)+((y-1)<<yshift)+((z-1)<<zshift)]) / 8;
}
else
{
to[x+(y<<yshift)+(z<<zshift)] = from[x+(y<<yshift)+(z<<zshift)];
}
}
void read_config(char *settings_file, settings &config)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
memset(buf, 0, size + 1);
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
while (token != NULL)
{
if (strcmp(token, "iterations") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.iterations = atoi(token); }
}
else if (strcmp(token, "x") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.x = atoi(token); }
}
else if (strcmp(token, "y") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.y = atoi(token); }
}
else if (strcmp(token, "z") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.z = atoi(token); }
}
else if (strcmp(token, "threads") == 0)
{
token = strtok(NULL, delimiter);
if (token == NULL) { break; }
else { config.threads = atoi(token); }
}
else if (strcmp(token, "2d") == 0)
{
config.dim_3d = false;
}
else if (strcmp(token, "3d") == 0)
{
config.dim_3d = true;
}
token = strtok(NULL, delimiter);
}
free(buf);
fclose(handle);
}
void init2d(char *settings_file, settings &config, float *data, bool *read_only)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
for(unsigned long i = 0; i < config.n * config.n; i++)
{
data[i] = 0.0f;
read_only[i] = false;
}
config.read_only = 0;
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
unsigned int x0;
unsigned int x1;
unsigned int y0;
unsigned int y1;
float f;
unsigned int x;
unsigned int y;
while (token != NULL)
{
if (strcmp(token, "point") == 0) //point located at (x,y), syntax: point [x] [y] [value]
{
assert(read(token, delimiter, 3, &x, &y, &f));
assert(x < config.n);
assert(y < config.n);
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
if (strcmp(token, "yline") == 0) //line in y direction, syntax: yline [xpos] [ystart] [yend] [value]
{
assert(read(token, delimiter, 4, &x, &y0, &y1, &f));
assert(y0 < y1);
assert(x < config.n);
assert(y1 < config.n);
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
else if (strcmp(token, "xline") == 0) //line in x direction, syntax: xline [ypos] [xstart] [xend] [value]
{
assert(read(token, delimiter, 4, &y, &x0, &x1, &f));
assert(x0 < x1);
assert(y < config.n);
assert(x1 < config.n);
for (x = x0; x <= x1; x++)
{
assert(x < config.n);
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
else if (strcmp(token, "rectangle") == 0) //rectangle from (x0, y0) to (x1, y1), syntax: square [x0] [y0] [x1] [y1] [value]
{
assert(read(token, delimiter, 5, &x0, &y0, &x1, &y1, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(x1 < config.n);
assert(y1 < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
data[x+(y*config.n)] = f;
}
}
}
token = strtok(NULL, delimiter);
}
for (x = config.x; x < config.n; x++)
{
for (y = config.y; y < config.n; y++)
{
if (read_only[x+(y*config.n)] == false)
{
read_only[x+(y*config.n)] = true;
config.read_only ++;
}
}
}
free(buf);
fclose(handle);
}
void init3d(char *settings_file, settings &config, float *data, bool *read_only)
{
FILE *handle = fopen(settings_file, "r");
fseek(handle, 0L, SEEK_END);
unsigned long size = ftell(handle);
fseek(handle, 0L, SEEK_SET);
char *buf = (char*) malloc((size + 1) * sizeof(char));
for(unsigned long i = 0; i < config.n * config.n * config.n; i++)
{
data[i] = 0.0f;
read_only[i] = false;
}
config.read_only = 0;
fread(buf, size, 1, handle);
const char *delimiter = " \n";
char *token = strtok(buf, delimiter);
unsigned int x0;
unsigned int x1;
unsigned int y0;
unsigned int y1;
unsigned int z0;
unsigned int z1;
float f;
unsigned int x;
unsigned int y;
unsigned int z;
while (token != NULL)
{
if (strcmp(token, "point") == 0) //point located at (x,y,z), syntax: point [x] [y] [z] [value]
{
assert(read(token, delimiter, 4, &x, &y, &z, &f));
assert(x < config.n);
assert(y < config.n);
assert(z < config.n);
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
if (strcmp(token, "zline") == 0) //line in z direction, syntax: zline [xpos] [ypos] [zstart] [zend] [value]
{
assert(read(token, delimiter, 5, &x, &y, &z0, &z1, &f));
assert(z0 < z1);
assert(x < config.n);
assert(y < config.n);
assert(z1 < config.n);
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "yline") == 0) //line in y direction, syntax: yline [xpos] [zpos] [ystart] [yend] [value]
{
assert(read(token, delimiter, 5, &x, &z, &y0, &y1, &f));
assert(y0 < y1);
assert(x < config.n);
assert(y1 < config.n);
assert(z < config.n);
for (y = y0; y <= y1; y++)
{
assert(y < config.n);
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "xline") == 0) //line in x direction, syntax: xline [ypos] [zpos] [xstart] [xend] [value]
{
assert(read(token, delimiter, 5, &y, &z, &x0, &x1, &f));
assert(x0 < x1);
assert(x1 < config.n);
assert(y < config.n);
assert(z < config.n);
for (x = x0; x <= x1; x++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
else if (strcmp(token, "zrectangle") == 0) //rectangle from (x0, y0) to (x1, y1) in z plane, syntax: zrectangle [x0] [y0] [x1] [y1] [z] [value]
{
assert(read(token, delimiter, 6, &x0, &y0, &x1, &y1, &z, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(x1 < config.n);
assert(y1 < config.n);
assert(z < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "yrectangle") == 0) //rectangle from (x0, z0) to (x1, z1) in y plane, syntax yrectangle [x0] [z0] [x1] [z1] [y] [value]
{
assert(read(token, delimiter, 6, &x0, &z0, &x1, &z1, &y, &f));
assert(x0 < x1);
assert(z0 < z1);
assert(x1 < config.n);
assert(y < config.n);
assert(z1 < config.n);
for (x = x0; x <= x1; x++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "xrectangle") == 0) ////rectangle from (y0, z0) to (y1, z1) in x plane, syntax xrectangle [y0] [z0] [y1] [z1] [x] [value]
{
assert(read(token, delimiter, 6, &y0, &z0, &y1, &z1, &x, &f));
assert(y0 < y1);
assert(z0 < z1);
assert(x < config.n);
assert(y1 < config.n);
assert(z1 < config.n);
for (y = y0; y <= y1; y++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
else if (strcmp(token, "prism") == 0) //prism from (x0, y0, z0) to (x1, y1, z1), syntax prism [x0] [y0] [z0] [x1] [y1] [z1] [value]
{
assert(read(token, delimiter, 7, &x0, &y0, &z0, &x1, &y1, &z1, &f));
assert(x0 < x1);
assert(y0 < y1);
assert(z0 < z1);
assert(x1 < config.n);
assert(y1 < config.n);
assert(z1 < config.n);
for (x = x0; x <= x1; x++)
{
for (y = y0; y <= y1; y++)
{
for (z = z0; z <= z1; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
config.read_only ++;
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
}
data[x+(y*config.n)+(z*config.n*config.n)] = f;
}
}
}
}
token = strtok(NULL, delimiter);
}
for (x = config.x; x < config.n; x++)
{
for (y = config.y; y < config.n; y++)
{
for (z = config.z; z < config.n; z++)
{
if (read_only[x+(y*config.n)+(z*config.n*config.n)] == false)
{
read_only[x+(y*config.n)+(z*config.n*config.n)] = true;
config.read_only ++;
}
}
}
}
free(buf);
fclose(handle);
}
int main(int argc, char **argv)
{
if (argc != 3)
{
printf("Usage: %s [config file] [output]\n", argv[0]);
exit(1);
}
settings config;
dim3 block(1,1,1);
dim3 grid(1,1,1);
unsigned long float_mem;
unsigned long bool_mem;
config.iterations = 0;
config.n = 0;
config.threads = 512;
config.x = 0;
config.y = 0;
config.z = 0;
config.dim_3d = false;
char *settings_file = argv[1];
read_config(settings_file, config);
switch (config.threads)
{
case 2048:
block.x = 32; block.y = 32; block.z = 2;
break;
case 1024:
block.x = 32; block.y = 32; block.z = 1;
break;
case 512:
block.x = 16; block.y = 16; block.z = 2;
break;
case 256:
block.x = 16; block.y = 16; block.z = 1;
break;
case 128:
block.x = 8; block.y = 8; block.z = 2;
break;
case 64:
block.x = 8; block.y = 8; block.z = 1;
break;
case 32:
block.x = 4; block.y = 4; block.z = 2;
break;
}
if (!config.dim_3d)
{
block.z = 1;
}
assert(config.n % block.x == 0);
assert(config.n % block.y == 0);
assert(config.n % block.z == 0);
if (config.dim_3d)
{
config.n = next_pow(__max(__max(config.x, config.y), config.z));
grid.x = config.n / block.x;
grid.y = config.n / block.y;
grid.z = config.n / block.z;
float_mem = config.n * config.n * config.n * sizeof(float);
bool_mem = config.n * config.n * config.n * sizeof(bool);
}
else
{
config.n = next_pow(__max(config.x, config.y));
grid.x = config.n / block.x;
grid.y = config.n / block.y;
float_mem = config.n * config.n * sizeof(float);
bool_mem = config.n * config.n * sizeof(bool);
}
float *data = (float *)malloc(float_mem);
bool *read_only = (bool *)malloc(bool_mem);
if (config.dim_3d) { init3d(settings_file, config, data, read_only); }
else { init2d(settings_file, config, data, read_only); }
float *d_z_1;
float *d_z_2;
bool *d_read_only;
hipEvent_t start;
hipEvent_t stop;
float compute_time;
double gflops;
unsigned int yshift = (unsigned int) log2((double) config.n);
unsigned int zshift = (unsigned int) log2((double) config.n * config.n);
assert(hipSuccess == hipEventCreate(&start));
assert(hipSuccess == hipEventCreate(&stop));
assert(hipSuccess == hipMalloc((void**) &d_z_1, float_mem));
assert(hipSuccess == hipMalloc((void**) &d_z_2, float_mem));
assert(hipSuccess == hipMalloc((void**) &d_read_only, bool_mem));
assert(hipSuccess == hipMemcpy(d_z_1, data, float_mem, hipMemcpyHostToDevice));
assert(hipSuccess == hipMemcpy(d_read_only, read_only, bool_mem, hipMemcpyHostToDevice));
assert(hipSuccess == hipEventRecord(start, 0));
for (unsigned int i = 0; i < config.iterations; i++)
{
if (config.dim_3d)
{
iterate3d<<<grid, block>>>(d_z_1, d_z_2, d_read_only, yshift, zshift, config.n, config.n * config.n);
hipDeviceSynchronize();
iterate3d<<<grid, block>>>(d_z_2, d_z_1, d_read_only, yshift, zshift, config.n, config.n * config.n);
hipDeviceSynchronize();
if (i % 50 == 0) { printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\bIterations: %u", i); }
}
else
{
iterate2d<<<grid, block>>>(d_z_1, d_z_2, d_read_only, yshift, config.n);
hipDeviceSynchronize();
iterate2d<<<grid, block>>>(d_z_2, d_z_1, d_read_only, yshift, config.n);
hipDeviceSynchronize();
if (i % 500 == 0) { printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\bIterations: %u", i); }
}
}
assert(hipSuccess == hipEventRecord(stop, 0));
assert(hipSuccess == hipEventSynchronize(stop));
assert(hipSuccess == hipEventElapsedTime(&compute_time, start, stop));
printf("\n");
printf("Compute time: %fms\n", compute_time);
if (config.dim_3d) { gflops = ((config.n * config.n * config.n) - config.read_only) * 16.0 * config.iterations / (compute_time * 1000000.0); }
else { gflops = ((config.n * config.n) - config.read_only) * 8.0 * config.iterations / (compute_time * 1000000.0); }
printf("Compute speed: %f GFLOPS\n", gflops);
assert(hipSuccess == hipMemcpy(data, d_z_1, float_mem, hipMemcpyDeviceToHost));
FILE *handle = fopen(argv[2], "w");
assert(handle != NULL);
if (config.dim_3d)
{
for (unsigned int x = 0; x < config.x; x++)
{
for (unsigned int y = 0; y < config.y; y++)
{
for (unsigned int z = 0; z < config.z; z++)
{
fprintf(handle, "%u, %u, %u, %f\n", x, y, z, data[x+(y*config.n)+(z*config.n*config.n)]);
}
}
}
}
else
{
for (unsigned int y = 0; y < config.n; y++)
{
for (unsigned int x = 0; x < config.n; x++)
{
fprintf(handle, "%06.2f", data[x+(y*config.n)]);
if (x == config.n - 1) { fprintf(handle, "\n"); }
else { fprintf(handle, ", "); }
}
}
}
fclose(handle);
assert(hipSuccess == hipFree(d_z_1));
assert(hipSuccess == hipFree(d_z_2));
assert(hipSuccess == hipFree(d_read_only));
free(data);
free(read_only);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9iterate2dPfS_Pbjj
.globl _Z9iterate2dPfS_Pbjj
.p2align 8
.type _Z9iterate2dPfS_Pbjj,@function
_Z9iterate2dPfS_Pbjj:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s7, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s8, -1
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_lshl_add_u32 v0, v3, s7, v2
global_load_u8 v1, v0, s[2:3]
v_cmp_ne_u32_e64 s2, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s3, 0, v1
v_mov_b32_e32 v1, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, s2, -1
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, s2, v2
v_cmp_ne_u32_e64 s2, s2, v3
s_and_b32 s9, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_3
v_add_lshl_u32 v8, v3, 1, s7
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v10, -1, v2
v_add_nc_u32_e32 v11, -1, v3
s_xor_b32 s8, exec_lo, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, v2, v8, 1
v_lshlrev_b64 v[6:7], 2, v[4:5]
v_add_nc_u32_e32 v4, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_nc_u32_e32 v4, v8, v10
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[4:5]
v_lshl_add_u32 v4, v11, s7, v10
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_clause 0x1
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(2)
v_add_f32_e32 v4, v6, v7
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v4, v2
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v4, 0x3e800000, v2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s3, exec_lo
s_and_b32 s3, s8, exec_lo
s_or_b32 s3, s2, s3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9iterate2dPfS_Pbjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9iterate2dPfS_Pbjj, .Lfunc_end0-_Z9iterate2dPfS_Pbjj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9iterate3dPfS_Pbjjjj
.globl _Z9iterate3dPfS_Pbjjjj
.p2align 8
.type _Z9iterate3dPfS_Pbjjjj,@function
_Z9iterate3dPfS_Pbjjjj:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
s_mov_b32 s10, -1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s2, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[4:5], null, s14, s8, v[2:3]
v_mad_u64_u32 v[5:6], null, s15, s3, v[0:1]
s_and_b32 s2, s2, 0xffff
s_load_b64 s[8:9], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, s13, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b32_e32 v0, s6, v4
v_cmp_ne_u32_e64 s2, 0, v4
v_lshlrev_b32_e32 v1, s7, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_add3_u32 v0, v0, v2, v1
s_delay_alu instid0(VALU_DEP_4)
s_and_b32 s2, vcc_lo, s2
global_load_u8 v1, v0, s[4:5]
v_cmp_ne_u32_e64 s4, 0, v5
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s3, 0, v1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, s2, -1
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB1_4
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, s3, v2
v_cmp_ne_u32_e64 s2, s3, v4
v_cmp_ne_u32_e64 s3, s3, v5
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB1_3
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v8, 1, v2
v_add_lshl_u32 v9, v4, 1, s6
v_add_lshl_u32 v14, v5, 1, s7
v_add_lshl_u32 v15, v5, -1, s7
v_add_lshl_u32 v16, v4, -1, s6
v_add_nc_u32_e32 v17, -1, v2
v_add_nc_u32_e32 v10, v9, v8
s_xor_b32 s10, exec_lo, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v18, v9, v17
v_add_nc_u32_e32 v6, v10, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[6:7]
v_add_nc_u32_e32 v6, v10, v15
v_add_nc_u32_e32 v10, v16, v8
v_add_nc_u32_e32 v16, v16, v17
v_lshlrev_b64 v[4:5], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, v10, v14
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[8:9], 2, v[6:7]
v_add_nc_u32_e32 v6, v10, v15
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_add_nc_u32_e32 v6, v18, v14
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
v_lshlrev_b64 v[12:13], 2, v[6:7]
v_add_nc_u32_e32 v6, v18, v15
s_clause 0x2
global_load_b32 v18, v[2:3], off
global_load_b32 v19, v[4:5], off
global_load_b32 v20, v[8:9], off
v_add_co_u32 v2, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[6:7]
v_add_nc_u32_e32 v6, v16, v14
v_add_co_u32 v8, vcc_lo, s8, v12
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_add_nc_u32_e32 v6, v16, v15
v_add_co_u32 v4, vcc_lo, s8, v4
global_load_b32 v12, v[2:3], off
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_clause 0x1
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[4:5], off
v_add_co_u32 v4, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v11, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(6)
v_add_f32_e32 v3, v18, v19
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v20
s_waitcnt vmcnt(4)
v_add_f32_e32 v3, v3, v12
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v8
s_waitcnt vmcnt(2)
v_add_f32_e32 v3, v3, v9
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v3, 0x3e000000, v2
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s4, exec_lo
s_and_b32 s3, s10, exec_lo
s_or_b32 s4, s2, s3
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s5
s_and_saveexec_b32 s2, s4
s_cbranch_execz .LBB1_6
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9iterate3dPfS_Pbjjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9iterate3dPfS_Pbjjjj, .Lfunc_end1-_Z9iterate3dPfS_Pbjjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9iterate2dPfS_Pbjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9iterate2dPfS_Pbjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9iterate3dPfS_Pbjjjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9iterate3dPfS_Pbjjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9iterate3dPfS_Pbjjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0040*/ S2R R7, SR_CTAID.Z ; /* 0x0000000000077919 */
/* 0x000e680000002700 */
/*0050*/ S2R R2, SR_TID.Z ; /* 0x0000000000027919 */
/* 0x000e680000002300 */
/*0060*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000ea80000002500 */
/*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fc400078e0205 */
/*0090*/ IMAD R7, R7, c[0x0][0x8], R2 ; /* 0x0000020007077a24 */
/* 0x002fca00078e0202 */
/*00a0*/ SHF.L.U32 R2, R7, c[0x0][0x17c], RZ ; /* 0x00005f0007027a19 */
/* 0x000fe200000006ff */
/*00b0*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x004fe200078e0203 */
/*00c0*/ SHF.L.U32 R3, R0, c[0x0][0x178], RZ ; /* 0x00005e0000037a19 */
/* 0x000fc800000006ff */
/*00d0*/ IADD3 R8, R2, R3, R6 ; /* 0x0000000302087210 */
/* 0x000fc80007ffe006 */
/*00e0*/ IADD3 R2, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008027a10 */
/* 0x000fca0007f1e0ff */
/*00f0*/ IMAD.X R3, RZ, RZ, c[0x0][0x174], P0 ; /* 0x00005d00ff037624 */
/* 0x000fca00000e06ff */
/*0100*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1100 */
/*0110*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000800 */
/*0120*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0130*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fc80003f05270 */
/*0140*/ ISETP.NE.AND P0, PT, R6, RZ, !P0 ; /* 0x000000ff0600720c */
/* 0x000fc80004705270 */
/*0150*/ ISETP.NE.AND P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80000705270 */
/*0160*/ ISETP.NE.AND P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fc80000705270 */
/*0170*/ ISETP.NE.AND P0, PT, R6, UR4, P0 ; /* 0x0000000406007c0c */
/* 0x000fc80008705270 */
/*0180*/ ISETP.NE.AND P0, PT, R0, UR4, P0 ; /* 0x0000000400007c0c */
/* 0x000fc80008705270 */
/*0190*/ ISETP.NE.AND P0, PT, R7, UR4, P0 ; /* 0x0000000407007c0c */
/* 0x000fda0008705270 */
/*01a0*/ @!P0 LEA R4, P1, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008048a11 */
/* 0x000fc800078210ff */
/*01b0*/ @!P0 LEA.HI.X R5, R8, c[0x0][0x164], RZ, 0x2, P1 ; /* 0x0000590008058a11 */
/* 0x000fca00008f14ff */
/*01c0*/ @!P0 LDG.E R9, [R4.64] ; /* 0x0000000604098981 */
/* 0x000162000c1e1900 */
/*01d0*/ LEA R2, P1, R8.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0008027a11 */
/* 0x040fe200078210ff */
/*01e0*/ BSSY B0, 0x510 ; /* 0x0000032000007945 */
/* 0x000fe60003800000 */
/*01f0*/ LEA.HI.X R3, R8, c[0x0][0x16c], RZ, 0x2, P1 ; /* 0x00005b0008037a11 */
/* 0x000fe200008f14ff */
/*0200*/ @!P0 BRA 0x500 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0210*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x001fe40007ffe0ff */
/*0220*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x000fc40007ffe0ff */
/*0240*/ SHF.L.U32 R11, R4, c[0x0][0x178], RZ ; /* 0x00005e00040b7a19 */
/* 0x000fe400000006ff */
/*0250*/ IADD3 R12, R0, -0x1, RZ ; /* 0xffffffff000c7810 */
/* 0x000fe20007ffe0ff */
/*0260*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0270*/ IADD3 R10, R7, -0x1, RZ ; /* 0xffffffff070a7810 */
/* 0x000fe40007ffe0ff */
/*0280*/ SHF.L.U32 R4, R5, c[0x0][0x17c], RZ ; /* 0x00005f0005047a19 */
/* 0x000fe400000006ff */
/*0290*/ IADD3 R9, R8, R11, RZ ; /* 0x0000000b08097210 */
/* 0x020fe40007ffe0ff */
/*02a0*/ SHF.L.U32 R7, R12, c[0x0][0x178], RZ ; /* 0x00005e000c077a19 */
/* 0x000fc400000006ff */
/*02b0*/ SHF.L.U32 R5, R10, c[0x0][0x17c], RZ ; /* 0x00005f000a057a19 */
/* 0x000fe200000006ff */
/*02c0*/ IMAD.IADD R15, R9.reuse, 0x1, R4 ; /* 0x00000001090f7824 */
/* 0x040fe200078e0204 */
/*02d0*/ IADD3 R10, R8, R7, RZ ; /* 0x00000007080a7210 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R16, R6, -0x1, RZ ; /* 0xffffffff06107810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.IADD R9, R9, 0x1, R5 ; /* 0x0000000109097824 */
/* 0x000fe400078e0205 */
/*0300*/ IMAD.IADD R13, R4, 0x1, R10 ; /* 0x00000001040d7824 */
/* 0x000fe400078e020a */
/*0310*/ IMAD.WIDE.U32 R8, R9, R0, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fe200078e0000 */
/*0320*/ IADD3 R17, R11, R16, RZ ; /* 0x000000100b117210 */
/* 0x000fc60007ffe0ff */
/*0330*/ IMAD.WIDE.U32 R14, R15, R0.reuse, c[0x0][0x160] ; /* 0x000058000f0e7625 */
/* 0x080fe200078e0000 */
/*0340*/ IADD3 R19, R4, R17, RZ ; /* 0x0000001104137210 */
/* 0x000fe20007ffe0ff */
/*0350*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ea4000c1e1900 */
/*0360*/ IMAD.IADD R11, R5, 0x1, R10 ; /* 0x00000001050b7824 */
/* 0x000fe400078e020a */
/*0370*/ IMAD.WIDE.U32 R12, R13, R0.reuse, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x080fe200078e0000 */
/*0380*/ LDG.E R6, [R14.64] ; /* 0x000000060e067981 */
/* 0x0000a6000c1e1900 */
/*0390*/ IMAD.WIDE.U32 R10, R11, R0, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fc400078e0000 */
/*03a0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ee4000c1e1900 */
/*03b0*/ IMAD.IADD R18, R7, 0x1, R16 ; /* 0x0000000107127824 */
/* 0x000fe200078e0210 */
/*03c0*/ IADD3 R7, R5, R17, RZ ; /* 0x0000001105077210 */
/* 0x000fe20007ffe0ff */
/*03d0*/ IMAD.WIDE.U32 R16, R19, R0.reuse, c[0x0][0x160] ; /* 0x0000580013107625 */
/* 0x080fe200078e0000 */
/*03e0*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000f26000c1e1900 */
/*03f0*/ IMAD.IADD R19, R4, 0x1, R18 ; /* 0x0000000104137824 */
/* 0x000fe400078e0212 */
/*0400*/ IMAD.WIDE.U32 R14, R7, R0, c[0x0][0x160] ; /* 0x00005800070e7625 */
/* 0x001fe200078e0000 */
/*0410*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000f22000c1e1900 */
/*0420*/ IADD3 R7, R5, R18, RZ ; /* 0x0000001205077210 */
/* 0x000fc40007ffe0ff */
/*0430*/ IMAD.WIDE.U32 R4, R19, R0.reuse, c[0x0][0x160] ; /* 0x0000580013047625 */
/* 0x080fe400078e0000 */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f24000c1e1900 */
/*0450*/ IMAD.WIDE.U32 R18, R7, R0, c[0x0][0x160] ; /* 0x0000580007127625 */
/* 0x000fe400078e0000 */
/*0460*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000f22000c1e1900 */
/*0480*/ FADD R9, R9, R6 ; /* 0x0000000609097221 */
/* 0x004fc80000000000 */
/*0490*/ FADD R9, R9, R12 ; /* 0x0000000c09097221 */
/* 0x008fc80000000000 */
/*04a0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x010fc80000000000 */
/*04b0*/ FADD R9, R9, R16 ; /* 0x0000001009097221 */
/* 0x000fc80000000000 */
/*04c0*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x000fc80000000000 */
/*04d0*/ FADD R9, R9, R4 ; /* 0x0000000409097221 */
/* 0x000fc80000000000 */
/*04e0*/ FADD R9, R9, R18 ; /* 0x0000001209097221 */
/* 0x000fc80000000000 */
/*04f0*/ FMUL R9, R9, 0.125 ; /* 0x3e00000009097820 */
/* 0x000fe40000400000 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x020fe2000c101906 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9iterate2dPfS_Pbjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x001fe400078e0202 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0203 */
/*0080*/ SHF.L.U32 R3, R7, c[0x0][0x178], RZ ; /* 0x00005e0007037a19 */
/* 0x000fca00000006ff */
/*0090*/ IMAD.IADD R6, R0, 0x1, R3 ; /* 0x0000000100067824 */
/* 0x000fca00078e0203 */
/*00a0*/ IADD3 R4, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006047a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R5, RZ, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00ff057a10 */
/* 0x000fca00007fe4ff */
/*00c0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1100 */
/*00d0*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe20000000800 */
/*00e0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*00f0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fc6000fffe03f */
/*0100*/ IMAD.WIDE.U32 R2, R6, R13, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc600078e000d */
/*0110*/ ISETP.NE.AND P1, PT, R7, UR4, PT ; /* 0x0000000407007c0c */
/* 0x000fc8000bf25270 */
/*0120*/ ISETP.NE.AND P1, PT, R0, UR4, P1 ; /* 0x0000000400007c0c */
/* 0x000fe40008f25270 */
/*0130*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fc80003f05270 */
/*0140*/ ISETP.EQ.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fc80000702670 */
/*0150*/ ISETP.EQ.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000702670 */
/*0160*/ @P1 BRA !P0, 0x1c0 ; /* 0x0000005000001947 */
/* 0x000fea0004000000 */
/*0170*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x000fc800078010ff */
/*0180*/ LEA.HI.X R5, R6, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fcc00000f14ff */
/*0190*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101906 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R4, R7.reuse, 0x1, RZ ; /* 0x0000000107047810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ IADD3 R9, R7, -0x1, RZ ; /* 0xffffffff07097810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ SHF.L.U32 R5, R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a19 */
/* 0x000fe400000006ff */
/*01f0*/ IADD3 R8, R0, -0x1, RZ ; /* 0xffffffff00087810 */
/* 0x000fc40007ffe0ff */
/*0200*/ IADD3 R6, R0.reuse, R7, RZ ; /* 0x0000000700067210 */
/* 0x040fe40007ffe0ff */
/*0210*/ IADD3 R4, R0, 0x1, R5 ; /* 0x0000000100047810 */
/* 0x000fe40007ffe005 */
/*0220*/ SHF.L.U32 R11, R9, c[0x0][0x178], RZ ; /* 0x00005e00090b7a19 */
/* 0x000fe200000006ff */
/*0230*/ IMAD.IADD R9, R5, 0x1, R8 ; /* 0x0000000105097824 */
/* 0x000fe400078e0208 */
/*0240*/ IMAD.WIDE.U32 R6, R6, R13, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e000d */
/*0250*/ IADD3 R11, R8, R11, RZ ; /* 0x0000000b080b7210 */
/* 0x000fc60007ffe0ff */
/*0260*/ IMAD.WIDE.U32 R4, R4, R13.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e000d */
/*0270*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD.WIDE.U32 R8, R9, R13.reuse, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x080fe400078e000d */
/*0290*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ IMAD.WIDE.U32 R10, R11, R13, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fe400078e000d */
/*02b0*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000f22000c1e1900 */
/*02d0*/ FADD R0, R6, R5 ; /* 0x0000000506007221 */
/* 0x004fc80000000000 */
/*02e0*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x008fc80000000000 */
/*02f0*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x010fc80000000000 */
/*0300*/ FMUL R13, R0, 0.25 ; /* 0x3e800000000d7820 */
/* 0x000fca0000400000 */
/*0310*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101906 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9iterate2dPfS_Pbjj
.globl _Z9iterate2dPfS_Pbjj
.p2align 8
.type _Z9iterate2dPfS_Pbjj,@function
_Z9iterate2dPfS_Pbjj:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s7, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s8, -1
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_lshl_add_u32 v0, v3, s7, v2
global_load_u8 v1, v0, s[2:3]
v_cmp_ne_u32_e64 s2, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s3, 0, v1
v_mov_b32_e32 v1, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, s2, -1
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, s2, v2
v_cmp_ne_u32_e64 s2, s2, v3
s_and_b32 s9, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_3
v_add_lshl_u32 v8, v3, 1, s7
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v10, -1, v2
v_add_nc_u32_e32 v11, -1, v3
s_xor_b32 s8, exec_lo, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, v2, v8, 1
v_lshlrev_b64 v[6:7], 2, v[4:5]
v_add_nc_u32_e32 v4, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_nc_u32_e32 v4, v8, v10
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 2, v[4:5]
v_lshl_add_u32 v4, v11, s7, v10
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_clause 0x1
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(2)
v_add_f32_e32 v4, v6, v7
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v4, v2
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v4, 0x3e800000, v2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s3, exec_lo
s_and_b32 s3, s8, exec_lo
s_or_b32 s3, s2, s3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9iterate2dPfS_Pbjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9iterate2dPfS_Pbjj, .Lfunc_end0-_Z9iterate2dPfS_Pbjj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9iterate3dPfS_Pbjjjj
.globl _Z9iterate3dPfS_Pbjjjj
.p2align 8
.type _Z9iterate3dPfS_Pbjjjj,@function
_Z9iterate3dPfS_Pbjjjj:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
s_mov_b32 s10, -1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s8, s2, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[4:5], null, s14, s8, v[2:3]
v_mad_u64_u32 v[5:6], null, s15, s3, v[0:1]
s_and_b32 s2, s2, 0xffff
s_load_b64 s[8:9], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, s13, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b32_e32 v0, s6, v4
v_cmp_ne_u32_e64 s2, 0, v4
v_lshlrev_b32_e32 v1, s7, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_add3_u32 v0, v0, v2, v1
s_delay_alu instid0(VALU_DEP_4)
s_and_b32 s2, vcc_lo, s2
global_load_u8 v1, v0, s[4:5]
v_cmp_ne_u32_e64 s4, 0, v5
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s3, 0, v1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, s2, -1
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB1_4
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, s3, v2
v_cmp_ne_u32_e64 s2, s3, v4
v_cmp_ne_u32_e64 s3, s3, v5
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB1_3
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v8, 1, v2
v_add_lshl_u32 v9, v4, 1, s6
v_add_lshl_u32 v14, v5, 1, s7
v_add_lshl_u32 v15, v5, -1, s7
v_add_lshl_u32 v16, v4, -1, s6
v_add_nc_u32_e32 v17, -1, v2
v_add_nc_u32_e32 v10, v9, v8
s_xor_b32 s10, exec_lo, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v18, v9, v17
v_add_nc_u32_e32 v6, v10, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[6:7]
v_add_nc_u32_e32 v6, v10, v15
v_add_nc_u32_e32 v10, v16, v8
v_add_nc_u32_e32 v16, v16, v17
v_lshlrev_b64 v[4:5], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, v10, v14
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[8:9], 2, v[6:7]
v_add_nc_u32_e32 v6, v10, v15
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_add_nc_u32_e32 v6, v18, v14
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
v_lshlrev_b64 v[12:13], 2, v[6:7]
v_add_nc_u32_e32 v6, v18, v15
s_clause 0x2
global_load_b32 v18, v[2:3], off
global_load_b32 v19, v[4:5], off
global_load_b32 v20, v[8:9], off
v_add_co_u32 v2, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v11, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[6:7]
v_add_nc_u32_e32 v6, v16, v14
v_add_co_u32 v8, vcc_lo, s8, v12
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_add_nc_u32_e32 v6, v16, v15
v_add_co_u32 v4, vcc_lo, s8, v4
global_load_b32 v12, v[2:3], off
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[6:7]
s_clause 0x1
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[4:5], off
v_add_co_u32 v4, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v11, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(6)
v_add_f32_e32 v3, v18, v19
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v20
s_waitcnt vmcnt(4)
v_add_f32_e32 v3, v3, v12
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v8
s_waitcnt vmcnt(2)
v_add_f32_e32 v3, v3, v9
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v3, v4
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v3, 0x3e000000, v2
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s4, exec_lo
s_and_b32 s3, s10, exec_lo
s_or_b32 s4, s2, s3
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s5
s_and_saveexec_b32 s2, s4
s_cbranch_execz .LBB1_6
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9iterate3dPfS_Pbjjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9iterate3dPfS_Pbjjjj, .Lfunc_end1-_Z9iterate3dPfS_Pbjjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9iterate2dPfS_Pbjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9iterate2dPfS_Pbjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9iterate3dPfS_Pbjjjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9iterate3dPfS_Pbjjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
__global__ void hello_world() {
printf("Hello, World\n");
}
int main() {
hello_world<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z11hello_worldv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
__global__ void hello_world() {
printf("Hello, World\n");
}
int main() {
hello_world<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000dc603_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11hello_worldvv
.type _Z30__device_stub__Z11hello_worldvv, @function
_Z30__device_stub__Z11hello_worldvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11hello_worldv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z11hello_worldvv, .-_Z30__device_stub__Z11hello_worldvv
.globl _Z11hello_worldv
.type _Z11hello_worldv, @function
_Z11hello_worldv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11hello_worldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11hello_worldv, .-_Z11hello_worldv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11hello_worldvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11hello_worldv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11hello_worldv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
__global__ void hello_world() {
printf("Hello, World\n");
}
int main() {
hello_world<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void hello_world() {
printf("Hello, World\n");
}
int main() {
hello_world<<<1,1>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void hello_world() {
printf("Hello, World\n");
}
int main() {
hello_world<<<1,1>>>();
hipDeviceSynchronize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11hello_worldv
.globl _Z11hello_worldv
.p2align 8
.type _Z11hello_worldv,@function
_Z11hello_worldv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 14
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11hello_worldv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11hello_worldv, .Lfunc_end0-_Z11hello_worldv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello, World\n"
.size .str, 14
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11hello_worldv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z11hello_worldv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void hello_world() {
printf("Hello, World\n");
}
int main() {
hello_world<<<1,1>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "hello_world.hip"
.globl _Z26__device_stub__hello_worldv # -- Begin function _Z26__device_stub__hello_worldv
.p2align 4, 0x90
.type _Z26__device_stub__hello_worldv,@function
_Z26__device_stub__hello_worldv: # @_Z26__device_stub__hello_worldv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11hello_worldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__hello_worldv, .Lfunc_end0-_Z26__device_stub__hello_worldv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11hello_worldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11hello_worldv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11hello_worldv,@object # @_Z11hello_worldv
.section .rodata,"a",@progbits
.globl _Z11hello_worldv
.p2align 3, 0x0
_Z11hello_worldv:
.quad _Z26__device_stub__hello_worldv
.size _Z11hello_worldv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11hello_worldv"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__hello_worldv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11hello_worldv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11hello_worldv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11hello_worldv
.globl _Z11hello_worldv
.p2align 8
.type _Z11hello_worldv,@function
_Z11hello_worldv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 14
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11hello_worldv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11hello_worldv, .Lfunc_end0-_Z11hello_worldv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello, World\n"
.size .str, 14
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11hello_worldv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z11hello_worldv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dc603_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11hello_worldvv
.type _Z30__device_stub__Z11hello_worldvv, @function
_Z30__device_stub__Z11hello_worldvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11hello_worldv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z11hello_worldvv, .-_Z30__device_stub__Z11hello_worldvv
.globl _Z11hello_worldv
.type _Z11hello_worldv, @function
_Z11hello_worldv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11hello_worldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11hello_worldv, .-_Z11hello_worldv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11hello_worldvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11hello_worldv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11hello_worldv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_world.hip"
.globl _Z26__device_stub__hello_worldv # -- Begin function _Z26__device_stub__hello_worldv
.p2align 4, 0x90
.type _Z26__device_stub__hello_worldv,@function
_Z26__device_stub__hello_worldv: # @_Z26__device_stub__hello_worldv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11hello_worldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__hello_worldv, .Lfunc_end0-_Z26__device_stub__hello_worldv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11hello_worldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11hello_worldv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11hello_worldv,@object # @_Z11hello_worldv
.section .rodata,"a",@progbits
.globl _Z11hello_worldv
.p2align 3, 0x0
_Z11hello_worldv:
.quad _Z26__device_stub__hello_worldv
.size _Z11hello_worldv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11hello_worldv"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__hello_worldv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11hello_worldv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // add two numbers
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand_kernel.h>
const int NBLOCK = 1;
const int NTHREAD = 1;
__global__ void add(int a,int b,int *c){
*c = a + b;
}
int main(void){
int a = 2;
int b = 7;
int c;
int *c_dev;
cudaMalloc( (void**)&c_dev,sizeof(int) );
add<<<NBLOCK,NTHREAD>>>(a,b,c_dev);
cudaMemcpy(&c,c_dev,sizeof(int),cudaMemcpyDeviceToHost);
printf("%d + %d = %d \n",a,b,c);
cudaFree(c_dev);
return 0;
} | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // add two numbers
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand_kernel.h>
const int NBLOCK = 1;
const int NTHREAD = 1;
__global__ void add(int a,int b,int *c){
*c = a + b;
}
int main(void){
int a = 2;
int b = 7;
int c;
int *c_dev;
cudaMalloc( (void**)&c_dev,sizeof(int) );
add<<<NBLOCK,NTHREAD>>>(a,b,c_dev);
cudaMemcpy(&c,c_dev,sizeof(int),cudaMemcpyDeviceToHost);
printf("%d + %d = %d \n",a,b,c);
cudaFree(c_dev);
return 0;
} | .file "tmpxft_0009dec8_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d \n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %r8d
movl $7, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addiiPi"
.LC2:
.string "precalc_xorwow_matrix"
.LC3:
.string "precalc_xorwow_offset_matrix"
.LC4:
.string "mrg32k3aM1"
.LC5:
.string "mrg32k3aM2"
.LC6:
.string "mrg32k3aM1SubSeq"
.LC7:
.string "mrg32k3aM2SubSeq"
.LC8:
.string "mrg32k3aM1Seq"
.LC9:
.string "mrg32k3aM2Seq"
.LC10:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // add two numbers
#include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand_kernel.h>
const int NBLOCK = 1;
const int NTHREAD = 1;
__global__ void add(int a,int b,int *c){
*c = a + b;
}
int main(void){
int a = 2;
int b = 7;
int c;
int *c_dev;
cudaMalloc( (void**)&c_dev,sizeof(int) );
add<<<NBLOCK,NTHREAD>>>(a,b,c_dev);
cudaMemcpy(&c,c_dev,sizeof(int),cudaMemcpyDeviceToHost);
printf("%d + %d = %d \n",a,b,c);
cudaFree(c_dev);
return 0;
} | // add two numbers
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
const int NBLOCK = 1;
const int NTHREAD = 1;
__global__ void add(int a,int b,int *c){
*c = a + b;
}
int main(void){
int a = 2;
int b = 7;
int c;
int *c_dev;
hipMalloc( (void**)&c_dev,sizeof(int) );
add<<<NBLOCK,NTHREAD>>>(a,b,c_dev);
hipMemcpy(&c,c_dev,sizeof(int),hipMemcpyDeviceToHost);
printf("%d + %d = %d \n",a,b,c);
hipFree(c_dev);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // add two numbers
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
const int NBLOCK = 1;
const int NTHREAD = 1;
__global__ void add(int a,int b,int *c){
*c = a + b;
}
int main(void){
int a = 2;
int b = 7;
int c;
int *c_dev;
hipMalloc( (void**)&c_dev,sizeof(int) );
add<<<NBLOCK,NTHREAD>>>(a,b,c_dev);
hipMemcpy(&c,c_dev,sizeof(int),hipMemcpyDeviceToHost);
printf("%d + %d = %d \n",a,b,c);
hipFree(c_dev);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // add two numbers
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
const int NBLOCK = 1;
const int NTHREAD = 1;
__global__ void add(int a,int b,int *c){
*c = a + b;
}
int main(void){
int a = 2;
int b = 7;
int c;
int *c_dev;
hipMalloc( (void**)&c_dev,sizeof(int) );
add<<<NBLOCK,NTHREAD>>>(a,b,c_dev);
hipMemcpy(&c,c_dev,sizeof(int),hipMemcpyDeviceToHost);
printf("%d + %d = %d \n",a,b,c);
hipFree(c_dev);
return 0;
} | .text
.file "add.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %ecx
movl $.L.str, %edi
movl $2, %esi
movl $7, %edx
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d \n"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009dec8_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d \n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %r8d
movl $7, %ecx
movl $2, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addiiPi"
.LC2:
.string "precalc_xorwow_matrix"
.LC3:
.string "precalc_xorwow_offset_matrix"
.LC4:
.string "mrg32k3aM1"
.LC5:
.string "mrg32k3aM2"
.LC6:
.string "mrg32k3aM1SubSeq"
.LC7:
.string "mrg32k3aM2SubSeq"
.LC8:
.string "mrg32k3aM1Seq"
.LC9:
.string "mrg32k3aM2Seq"
.LC10:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %ecx
movl $.L.str, %edi
movl $2, %esi
movl $7, %edx
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d \n"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <numeric>
#include <random>
#include <vector>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 1
constexpr int num_elements = 1 << 18;
constexpr uint num_blocks = num_elements >> 10; // div by 1024
constexpr uint block_size = num_elements / num_blocks;
// constexpr uint num_blocks = 1 << 8; //num_elements >> 10; // div by 1024
// constexpr uint block_size = 1 << 10; // num_elements / num_blocks;
// Part 1 of 6: implement the kernel
__global__ void block_sum(const int* input, int* per_block_results,
const size_t n, const int block_sizeee)
{
// fill me
// shared memory : chunk of size block_size from the input
__shared__ int sdata[block_size];
uint block_id = blockIdx.x;
uint thread_id = threadIdx.x;
// fill the shared memory :
// each thread of a block fills its cell
sdata[thread_id] = input[block_size * block_id + thread_id];
// Wait for the shared memory to be full
__syncthreads();
// One single thread sums all the elements of the block
if (thread_id == 0) {
int psum = 0;
for (uint i = 0; i < block_size; ++i) {
psum += 1;//sdata[i];
}
per_block_results[block_id] = psum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(void)
{
std::random_device
rd; // Will be used to obtain a seed for the random number engine
std::mt19937 gen(rd()); // Standard mersenne_twister_engine seeded with rd()
std::uniform_int_distribution<> distrib(-10, 10);
// create array of 256ki elements
const int num_elements = 1 << 18;
// generate random input on the host
std::vector<int> h_input(num_elements);
for (auto& elt : h_input) {
elt = distrib(gen);
}
const int host_result = std::accumulate(h_input.begin(), h_input.end(), 0);
std::cerr << "Host sum: " << host_result << std::endl;
// //Part 1 of 6: move input to device memory
int* d_input;
// all the elements to sum
uint in_size = num_elements * sizeof(int);
// partial sums
uint num_blocks = num_elements >> 10; // div by 1024
const uint block_size = num_elements / num_blocks;
// partial sum array
const uint out_psm_size = num_blocks * sizeof(int);
// Alloc and copy input data
cudaMalloc(&d_input, in_size);
cudaMemcpy(d_input, h_input.data(), in_size, cudaMemcpyHostToDevice);
// // Part 1 of 6: allocate the partial sums: How much space does it need?
int* d_partial_sums_and_total;
cudaMalloc(&d_partial_sums_and_total, out_psm_size);
int* d_result;
cudaMalloc(&d_result, sizeof(int));
// // Part 1 of 6: launch one kernel to compute, per-block, a partial sum. How
// much shared memory does it need?
block_sum<<<num_blocks, block_size>>>(d_input, d_partial_sums_and_total,
num_elements, block_size);
int h_partial_sums_and_total[num_blocks];
cudaMemcpy(&h_partial_sums_and_total, d_partial_sums_and_total, out_psm_size, cudaMemcpyDeviceToHost);
for (uint ib = 0; ib < num_blocks; ++ib) {
std::cout << "b(" << ib << ") = " << h_partial_sums_and_total[ib] << std::endl;
}
// // Part 1 of 6: compute the sum of the partial sums
block_sum<<<1, num_blocks>>>(d_partial_sums_and_total, d_result, 0, num_blocks);
// // Part 1 of 6: copy the result back to the host
int device_result = 0;
cudaMemcpy(&device_result, d_result, sizeof(int), cudaMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// // Part 1 of 6: deallocate device memory
return 0;
} | code for sm_80
Function : _Z9block_sumPKiPimi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0030*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0x400 ; /* 0x0000040000057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x001fca00078e0003 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <numeric>
#include <random>
#include <vector>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 1
constexpr int num_elements = 1 << 18;
constexpr uint num_blocks = num_elements >> 10; // div by 1024
constexpr uint block_size = num_elements / num_blocks;
// constexpr uint num_blocks = 1 << 8; //num_elements >> 10; // div by 1024
// constexpr uint block_size = 1 << 10; // num_elements / num_blocks;
// Part 1 of 6: implement the kernel
__global__ void block_sum(const int* input, int* per_block_results,
const size_t n, const int block_sizeee)
{
// fill me
// shared memory : chunk of size block_size from the input
__shared__ int sdata[block_size];
uint block_id = blockIdx.x;
uint thread_id = threadIdx.x;
// fill the shared memory :
// each thread of a block fills its cell
sdata[thread_id] = input[block_size * block_id + thread_id];
// Wait for the shared memory to be full
__syncthreads();
// One single thread sums all the elements of the block
if (thread_id == 0) {
int psum = 0;
for (uint i = 0; i < block_size; ++i) {
psum += 1;//sdata[i];
}
per_block_results[block_id] = psum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(void)
{
std::random_device
rd; // Will be used to obtain a seed for the random number engine
std::mt19937 gen(rd()); // Standard mersenne_twister_engine seeded with rd()
std::uniform_int_distribution<> distrib(-10, 10);
// create array of 256ki elements
const int num_elements = 1 << 18;
// generate random input on the host
std::vector<int> h_input(num_elements);
for (auto& elt : h_input) {
elt = distrib(gen);
}
const int host_result = std::accumulate(h_input.begin(), h_input.end(), 0);
std::cerr << "Host sum: " << host_result << std::endl;
// //Part 1 of 6: move input to device memory
int* d_input;
// all the elements to sum
uint in_size = num_elements * sizeof(int);
// partial sums
uint num_blocks = num_elements >> 10; // div by 1024
const uint block_size = num_elements / num_blocks;
// partial sum array
const uint out_psm_size = num_blocks * sizeof(int);
// Alloc and copy input data
cudaMalloc(&d_input, in_size);
cudaMemcpy(d_input, h_input.data(), in_size, cudaMemcpyHostToDevice);
// // Part 1 of 6: allocate the partial sums: How much space does it need?
int* d_partial_sums_and_total;
cudaMalloc(&d_partial_sums_and_total, out_psm_size);
int* d_result;
cudaMalloc(&d_result, sizeof(int));
// // Part 1 of 6: launch one kernel to compute, per-block, a partial sum. How
// much shared memory does it need?
block_sum<<<num_blocks, block_size>>>(d_input, d_partial_sums_and_total,
num_elements, block_size);
int h_partial_sums_and_total[num_blocks];
cudaMemcpy(&h_partial_sums_and_total, d_partial_sums_and_total, out_psm_size, cudaMemcpyDeviceToHost);
for (uint ib = 0; ib < num_blocks; ++ib) {
std::cout << "b(" << ib << ") = " << h_partial_sums_and_total[ib] << std::endl;
}
// // Part 1 of 6: compute the sum of the partial sums
block_sum<<<1, num_blocks>>>(d_partial_sums_and_total, d_result, 0, num_blocks);
// // Part 1 of 6: copy the result back to the host
int device_result = 0;
cudaMemcpy(&device_result, d_result, sizeof(int), cudaMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// // Part 1 of 6: deallocate device memory
return 0;
} | .file "tmpxft_00070264_00000000-6_reduction_test_brouillon.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4756:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4756:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9block_sumPKiPimiPKiPimi
.type _Z33__device_stub__Z9block_sumPKiPimiPKiPimi, @function
_Z33__device_stub__Z9block_sumPKiPimiPKiPimi:
.LFB4778:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9block_sumPKiPimi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4778:
.size _Z33__device_stub__Z9block_sumPKiPimiPKiPimi, .-_Z33__device_stub__Z9block_sumPKiPimiPKiPimi
.globl _Z9block_sumPKiPimi
.type _Z9block_sumPKiPimi, @function
_Z9block_sumPKiPimi:
.LFB4779:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9block_sumPKiPimiPKiPimi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4779:
.size _Z9block_sumPKiPimi, .-_Z9block_sumPKiPimi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9block_sumPKiPimi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4781:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9block_sumPKiPimi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4781:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB5113:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE5113:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv:
.LFB5502:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1816(%rdi), %r9
movq %rdi, %rcx
movl $2567483615, %r8d
.L21:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 3176(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L21
leaq 3168(%rdi), %r8
movl $2567483615, %esi
.L23:
movq 1816(%rdx), %rax
andq $-2147483648, %rax
movq 1824(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1816(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L23
movq 4984(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 3168(%rdi), %rdx
andl $1, %eax
movl $2567483615, %ecx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 4984(%rdi)
movq $0, 4992(%rdi)
ret
.cfi_endproc
.LFE5502:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv:
.LFB5426:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $623, 4992(%rdi)
ja .L30
.L28:
movq 4992(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 4992(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $11, %rdx
movl %edx, %edx
xorq %rax, %rdx
movq %rdx, %rax
salq $7, %rax
andl $2636928640, %eax
xorq %rdx, %rax
movq %rax, %rdx
salq $15, %rdx
andl $4022730752, %edx
xorq %rax, %rdx
movq %rdx, %rax
shrq $18, %rax
xorq %rdx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
jmp .L28
.cfi_endproc
.LFE5426:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE:
.LFB5307:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq 4(%rdx), %rbx
movslq (%rdx), %rax
subq %rax, %rbx
movl $4294967294, %eax
cmpq %rbx, %rax
jnb .L42
movq %rdi, %r14
movq %rbx, %rax
shrq $32, %rax
je .L36
movq %rsp, %r15
.L40:
movl $0, (%rsp)
movl $-1, 4(%rsp)
movq %r15, %rdx
movq %rbp, %rsi
movq %r14, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movq %rax, %r13
salq $32, %r13
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %r13, %rax
cmpq %rax, %rbx
jb .L40
cmpq %r13, %rax
jb .L40
jmp .L35
.L42:
addq $1, %rbx
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %ebx, %eax
jnb .L33
movl %ebx, %eax
negl %eax
movl $0, %edx
divl %ebx
movl %edx, %r13d
cmpl %edx, %ecx
jnb .L33
.L34:
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %r13d, %eax
jb .L34
.L33:
movq %rcx, %rax
shrq $32, %rax
.L35:
addl (%r12), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L43
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .L35
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5307:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.section .rodata.str1.1
.LC1:
.string "Host sum: "
.LC2:
.string "b("
.LC3:
.string ") = "
.LC4:
.string "Device sum: "
.text
.globl main
.type main, @function
main:
.LFB4753:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4753
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $4096, %rsp
orq $0, (%rsp)
subq $4096, %rsp
orq $0, (%rsp)
subq $1928, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -5056(%rbp), %rsi
leaq -5040(%rbp), %rax
movq %rax, -5056(%rbp)
movl $1634100580, -5040(%rbp)
movl $1953264993, -5037(%rbp)
movq $7, -5048(%rbp)
movb $0, -5033(%rbp)
leaq -10064(%rbp), %rdi
.LEHB0:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE0:
movq -5056(%rbp), %rdi
leaq -5040(%rbp), %rax
cmpq %rax, %rdi
je .L45
movq -5040(%rbp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L45:
leaq -10064(%rbp), %rdi
.LEHB1:
call _ZNSt13random_device9_M_getvalEv@PLT
movl %eax, %eax
movq %rax, -5056(%rbp)
movl $1, %ecx
movabsq $945986875574848801, %rdi
.L49:
movq -5064(%rbp,%rcx,8), %rax
movq %rax, %rdx
shrq $30, %rdx
xorq %rdx, %rax
imulq $1812433253, %rax, %rsi
movq %rcx, %rdx
shrq $4, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $624, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addl %esi, %eax
movq %rax, -5056(%rbp,%rcx,8)
addq $1, %rcx
cmpq $624, %rcx
jne .L49
movq $624, -64(%rbp)
movl $-10, -10128(%rbp)
movl $10, -10124(%rbp)
movq $0, -10088(%rbp)
movq $0, -10080(%rbp)
movl $1048576, %edi
call _Znwm@PLT
.LEHE1:
jmp .L77
.L69:
endbr64
movq %rax, %rbx
leaq -5056(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L48:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L77:
movq %rax, %r13
movq %rax, -10096(%rbp)
leaq 1048576(%rax), %rdx
movq %rdx, -10080(%rbp)
movl $0, (%rax)
leaq 4(%rax), %rax
.L50:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L50
movq %rdx, -10088(%rbp)
movq %r13, %rbx
leaq 1048576(%r13), %r14
movq %r13, %r12
leaq -10128(%rbp), %r15
.L51:
leaq -5056(%rbp), %rsi
movq %r15, %rdx
movq %r15, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, (%r12)
addq $4, %r12
cmpq %r14, %r12
jne .L51
movl $0, %eax
.L52:
addl (%rbx), %eax
movl %eax, %r12d
addq $4, %rbx
cmpq %rbx, %r14
jne .L52
leaq .LC1(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB3:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq -10152(%rbp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1048576, %edx
movq %r13, %rsi
movq -10152(%rbp), %rdi
call cudaMemcpy@PLT
leaq -10144(%rbp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq -10136(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1024, -10108(%rbp)
movl $1, -10104(%rbp)
movl $1, -10100(%rbp)
movl $256, -10120(%rbp)
movl $1, -10116(%rbp)
movl $1, -10112(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -10108(%rbp), %rdx
movl $1, %ecx
movq -10120(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L53
movl $1024, %ecx
movl $262144, %edx
movq -10144(%rbp), %rsi
movq -10152(%rbp), %rdi
call _Z33__device_stub__Z9block_sumPKiPimiPKiPimi
.L53:
movq %rsp, %rax
.L54:
cmpq %rax, %rsp
je .L55
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L54
.L55:
subq $1024, %rsp
orq $0, 1016(%rsp)
movq %rsp, %r15
movl $2, %ecx
movl $1024, %edx
movq -10144(%rbp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
jmp .L61
.L82:
movq %r12, %rsi
movq %r14, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movl $4, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r15,%r12,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L78
cmpb $0, 56(%r13)
je .L59
movzbl 67(%r13), %esi
.L60:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L79
.L78:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L80
call _ZSt16__throw_bad_castv@PLT
.LEHE3:
.L68:
endbr64
movq %rax, %rbx
leaq -10096(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L64:
leaq -10064(%rbp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L65
call __stack_chk_fail@PLT
.L80:
call __stack_chk_fail@PLT
.L59:
movq %r13, %rdi
.LEHB4:
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L60
.L79:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %r12
cmpq $256, %r12
je .L81
.L61:
movl $2, %edx
leaq .LC2(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L82
.L81:
movl $256, -10108(%rbp)
movl $1, -10104(%rbp)
movl $1, -10100(%rbp)
movl $1, -10120(%rbp)
movl $1, -10116(%rbp)
movl $1, -10112(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -10108(%rbp), %rdx
movl $1, %ecx
movq -10120(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L62
movl $256, %ecx
movl $0, %edx
movq -10136(%rbp), %rsi
movq -10144(%rbp), %rdi
call _Z33__device_stub__Z9block_sumPKiPimiPKiPimi
.L62:
movl $0, -10108(%rbp)
leaq -10108(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -10136(%rbp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -10108(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE4:
leaq -10096(%rbp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq -10064(%rbp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L83
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L67:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L64
.L65:
movq %rbx, %rdi
.LEHB5:
call _Unwind_Resume@PLT
.LEHE5:
.L83:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4753:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4753:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4753-.LLSDACSB4753
.LLSDACSB4753:
.uleb128 .LEHB0-.LFB4753
.uleb128 .LEHE0-.LEHB0
.uleb128 .L69-.LFB4753
.uleb128 0
.uleb128 .LEHB1-.LFB4753
.uleb128 .LEHE1-.LEHB1
.uleb128 .L67-.LFB4753
.uleb128 0
.uleb128 .LEHB2-.LFB4753
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4753
.uleb128 .LEHE3-.LEHB3
.uleb128 .L68-.LFB4753
.uleb128 0
.uleb128 .LEHB4-.LFB4753
.uleb128 .LEHE4-.LEHB4
.uleb128 .L68-.LFB4753
.uleb128 0
.uleb128 .LEHB5-.LFB4753
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.LLSDACSE4753:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <numeric>
#include <random>
#include <vector>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 1
constexpr int num_elements = 1 << 18;
constexpr uint num_blocks = num_elements >> 10; // div by 1024
constexpr uint block_size = num_elements / num_blocks;
// constexpr uint num_blocks = 1 << 8; //num_elements >> 10; // div by 1024
// constexpr uint block_size = 1 << 10; // num_elements / num_blocks;
// Part 1 of 6: implement the kernel
__global__ void block_sum(const int* input, int* per_block_results,
const size_t n, const int block_sizeee)
{
// fill me
// shared memory : chunk of size block_size from the input
__shared__ int sdata[block_size];
uint block_id = blockIdx.x;
uint thread_id = threadIdx.x;
// fill the shared memory :
// each thread of a block fills its cell
sdata[thread_id] = input[block_size * block_id + thread_id];
// Wait for the shared memory to be full
__syncthreads();
// One single thread sums all the elements of the block
if (thread_id == 0) {
int psum = 0;
for (uint i = 0; i < block_size; ++i) {
psum += 1;//sdata[i];
}
per_block_results[block_id] = psum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(void)
{
std::random_device
rd; // Will be used to obtain a seed for the random number engine
std::mt19937 gen(rd()); // Standard mersenne_twister_engine seeded with rd()
std::uniform_int_distribution<> distrib(-10, 10);
// create array of 256ki elements
const int num_elements = 1 << 18;
// generate random input on the host
std::vector<int> h_input(num_elements);
for (auto& elt : h_input) {
elt = distrib(gen);
}
const int host_result = std::accumulate(h_input.begin(), h_input.end(), 0);
std::cerr << "Host sum: " << host_result << std::endl;
// //Part 1 of 6: move input to device memory
int* d_input;
// all the elements to sum
uint in_size = num_elements * sizeof(int);
// partial sums
uint num_blocks = num_elements >> 10; // div by 1024
const uint block_size = num_elements / num_blocks;
// partial sum array
const uint out_psm_size = num_blocks * sizeof(int);
// Alloc and copy input data
cudaMalloc(&d_input, in_size);
cudaMemcpy(d_input, h_input.data(), in_size, cudaMemcpyHostToDevice);
// // Part 1 of 6: allocate the partial sums: How much space does it need?
int* d_partial_sums_and_total;
cudaMalloc(&d_partial_sums_and_total, out_psm_size);
int* d_result;
cudaMalloc(&d_result, sizeof(int));
// // Part 1 of 6: launch one kernel to compute, per-block, a partial sum. How
// much shared memory does it need?
block_sum<<<num_blocks, block_size>>>(d_input, d_partial_sums_and_total,
num_elements, block_size);
int h_partial_sums_and_total[num_blocks];
cudaMemcpy(&h_partial_sums_and_total, d_partial_sums_and_total, out_psm_size, cudaMemcpyDeviceToHost);
for (uint ib = 0; ib < num_blocks; ++ib) {
std::cout << "b(" << ib << ") = " << h_partial_sums_and_total[ib] << std::endl;
}
// // Part 1 of 6: compute the sum of the partial sums
block_sum<<<1, num_blocks>>>(d_partial_sums_and_total, d_result, 0, num_blocks);
// // Part 1 of 6: copy the result back to the host
int device_result = 0;
cudaMemcpy(&device_result, d_result, sizeof(int), cudaMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// // Part 1 of 6: deallocate device memory
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <random>
#include <vector>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 1
constexpr int num_elements = 1 << 18;
constexpr uint num_blocks = num_elements >> 10; // div by 1024
constexpr uint block_size = num_elements / num_blocks;
// constexpr uint num_blocks = 1 << 8; //num_elements >> 10; // div by 1024
// constexpr uint block_size = 1 << 10; // num_elements / num_blocks;
// Part 1 of 6: implement the kernel
__global__ void block_sum(const int* input, int* per_block_results,
const size_t n, const int block_sizeee)
{
// fill me
// shared memory : chunk of size block_size from the input
__shared__ int sdata[block_size];
uint block_id = blockIdx.x;
uint thread_id = threadIdx.x;
// fill the shared memory :
// each thread of a block fills its cell
sdata[thread_id] = input[block_size * block_id + thread_id];
// Wait for the shared memory to be full
__syncthreads();
// One single thread sums all the elements of the block
if (thread_id == 0) {
int psum = 0;
for (uint i = 0; i < block_size; ++i) {
psum += 1;//sdata[i];
}
per_block_results[block_id] = psum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(void)
{
std::random_device
rd; // Will be used to obtain a seed for the random number engine
std::mt19937 gen(rd()); // Standard mersenne_twister_engine seeded with rd()
std::uniform_int_distribution<> distrib(-10, 10);
// create array of 256ki elements
const int num_elements = 1 << 18;
// generate random input on the host
std::vector<int> h_input(num_elements);
for (auto& elt : h_input) {
elt = distrib(gen);
}
const int host_result = std::accumulate(h_input.begin(), h_input.end(), 0);
std::cerr << "Host sum: " << host_result << std::endl;
// //Part 1 of 6: move input to device memory
int* d_input;
// all the elements to sum
uint in_size = num_elements * sizeof(int);
// partial sums
uint num_blocks = num_elements >> 10; // div by 1024
const uint block_size = num_elements / num_blocks;
// partial sum array
const uint out_psm_size = num_blocks * sizeof(int);
// Alloc and copy input data
hipMalloc(&d_input, in_size);
hipMemcpy(d_input, h_input.data(), in_size, hipMemcpyHostToDevice);
// // Part 1 of 6: allocate the partial sums: How much space does it need?
int* d_partial_sums_and_total;
hipMalloc(&d_partial_sums_and_total, out_psm_size);
int* d_result;
hipMalloc(&d_result, sizeof(int));
// // Part 1 of 6: launch one kernel to compute, per-block, a partial sum. How
// much shared memory does it need?
block_sum<<<num_blocks, block_size>>>(d_input, d_partial_sums_and_total,
num_elements, block_size);
int h_partial_sums_and_total[num_blocks];
hipMemcpy(&h_partial_sums_and_total, d_partial_sums_and_total, out_psm_size, hipMemcpyDeviceToHost);
for (uint ib = 0; ib < num_blocks; ++ib) {
std::cout << "b(" << ib << ") = " << h_partial_sums_and_total[ib] << std::endl;
}
// // Part 1 of 6: compute the sum of the partial sums
block_sum<<<1, num_blocks>>>(d_partial_sums_and_total, d_result, 0, num_blocks);
// // Part 1 of 6: copy the result back to the host
int device_result = 0;
hipMemcpy(&device_result, d_result, sizeof(int), hipMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// // Part 1 of 6: deallocate device memory
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <random>
#include <vector>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 1
constexpr int num_elements = 1 << 18;
constexpr uint num_blocks = num_elements >> 10; // div by 1024
constexpr uint block_size = num_elements / num_blocks;
// constexpr uint num_blocks = 1 << 8; //num_elements >> 10; // div by 1024
// constexpr uint block_size = 1 << 10; // num_elements / num_blocks;
// Part 1 of 6: implement the kernel
__global__ void block_sum(const int* input, int* per_block_results,
const size_t n, const int block_sizeee)
{
// fill me
// shared memory : chunk of size block_size from the input
__shared__ int sdata[block_size];
uint block_id = blockIdx.x;
uint thread_id = threadIdx.x;
// fill the shared memory :
// each thread of a block fills its cell
sdata[thread_id] = input[block_size * block_id + thread_id];
// Wait for the shared memory to be full
__syncthreads();
// One single thread sums all the elements of the block
if (thread_id == 0) {
int psum = 0;
for (uint i = 0; i < block_size; ++i) {
psum += 1;//sdata[i];
}
per_block_results[block_id] = psum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(void)
{
std::random_device
rd; // Will be used to obtain a seed for the random number engine
std::mt19937 gen(rd()); // Standard mersenne_twister_engine seeded with rd()
std::uniform_int_distribution<> distrib(-10, 10);
// create array of 256ki elements
const int num_elements = 1 << 18;
// generate random input on the host
std::vector<int> h_input(num_elements);
for (auto& elt : h_input) {
elt = distrib(gen);
}
const int host_result = std::accumulate(h_input.begin(), h_input.end(), 0);
std::cerr << "Host sum: " << host_result << std::endl;
// //Part 1 of 6: move input to device memory
int* d_input;
// all the elements to sum
uint in_size = num_elements * sizeof(int);
// partial sums
uint num_blocks = num_elements >> 10; // div by 1024
const uint block_size = num_elements / num_blocks;
// partial sum array
const uint out_psm_size = num_blocks * sizeof(int);
// Alloc and copy input data
hipMalloc(&d_input, in_size);
hipMemcpy(d_input, h_input.data(), in_size, hipMemcpyHostToDevice);
// // Part 1 of 6: allocate the partial sums: How much space does it need?
int* d_partial_sums_and_total;
hipMalloc(&d_partial_sums_and_total, out_psm_size);
int* d_result;
hipMalloc(&d_result, sizeof(int));
// // Part 1 of 6: launch one kernel to compute, per-block, a partial sum. How
// much shared memory does it need?
block_sum<<<num_blocks, block_size>>>(d_input, d_partial_sums_and_total,
num_elements, block_size);
int h_partial_sums_and_total[num_blocks];
hipMemcpy(&h_partial_sums_and_total, d_partial_sums_and_total, out_psm_size, hipMemcpyDeviceToHost);
for (uint ib = 0; ib < num_blocks; ++ib) {
std::cout << "b(" << ib << ") = " << h_partial_sums_and_total[ib] << std::endl;
}
// // Part 1 of 6: compute the sum of the partial sums
block_sum<<<1, num_blocks>>>(d_partial_sums_and_total, d_result, 0, num_blocks);
// // Part 1 of 6: copy the result back to the host
int device_result = 0;
hipMemcpy(&device_result, d_result, sizeof(int), hipMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// // Part 1 of 6: deallocate device memory
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9block_sumPKiPimi
.globl _Z9block_sumPKiPimi
.p2align 8
.type _Z9block_sumPKiPimi,@function
_Z9block_sumPKiPimi:
s_mov_b32 s3, 0
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s2, s15
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x400
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9block_sumPKiPimi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9block_sumPKiPimi, .Lfunc_end0-_Z9block_sumPKiPimi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9block_sumPKiPimi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z9block_sumPKiPimi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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