system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <random>
#include <vector>
// Here you can set the device ID that was assigned to you
#define MYDEVICE 1
constexpr int num_elements = 1 << 18;
constexpr uint num_blocks = num_elements >> 10; // div by 1024
constexpr uint block_size = num_elements / num_blocks;
// constexpr uint num_blocks = 1 << 8; //num_elements >> 10; // div by 1024
// constexpr uint block_size = 1 << 10; // num_elements / num_blocks;
// Part 1 of 6: implement the kernel
__global__ void block_sum(const int* input, int* per_block_results,
const size_t n, const int block_sizeee)
{
// fill me
// shared memory : chunk of size block_size from the input
__shared__ int sdata[block_size];
uint block_id = blockIdx.x;
uint thread_id = threadIdx.x;
// fill the shared memory :
// each thread of a block fills its cell
sdata[thread_id] = input[block_size * block_id + thread_id];
// Wait for the shared memory to be full
__syncthreads();
// One single thread sums all the elements of the block
if (thread_id == 0) {
int psum = 0;
for (uint i = 0; i < block_size; ++i) {
psum += 1;//sdata[i];
}
per_block_results[block_id] = psum;
}
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(void)
{
std::random_device
rd; // Will be used to obtain a seed for the random number engine
std::mt19937 gen(rd()); // Standard mersenne_twister_engine seeded with rd()
std::uniform_int_distribution<> distrib(-10, 10);
// create array of 256ki elements
const int num_elements = 1 << 18;
// generate random input on the host
std::vector<int> h_input(num_elements);
for (auto& elt : h_input) {
elt = distrib(gen);
}
const int host_result = std::accumulate(h_input.begin(), h_input.end(), 0);
std::cerr << "Host sum: " << host_result << std::endl;
// //Part 1 of 6: move input to device memory
int* d_input;
// all the elements to sum
uint in_size = num_elements * sizeof(int);
// partial sums
uint num_blocks = num_elements >> 10; // div by 1024
const uint block_size = num_elements / num_blocks;
// partial sum array
const uint out_psm_size = num_blocks * sizeof(int);
// Alloc and copy input data
hipMalloc(&d_input, in_size);
hipMemcpy(d_input, h_input.data(), in_size, hipMemcpyHostToDevice);
// // Part 1 of 6: allocate the partial sums: How much space does it need?
int* d_partial_sums_and_total;
hipMalloc(&d_partial_sums_and_total, out_psm_size);
int* d_result;
hipMalloc(&d_result, sizeof(int));
// // Part 1 of 6: launch one kernel to compute, per-block, a partial sum. How
// much shared memory does it need?
block_sum<<<num_blocks, block_size>>>(d_input, d_partial_sums_and_total,
num_elements, block_size);
int h_partial_sums_and_total[num_blocks];
hipMemcpy(&h_partial_sums_and_total, d_partial_sums_and_total, out_psm_size, hipMemcpyDeviceToHost);
for (uint ib = 0; ib < num_blocks; ++ib) {
std::cout << "b(" << ib << ") = " << h_partial_sums_and_total[ib] << std::endl;
}
// // Part 1 of 6: compute the sum of the partial sums
block_sum<<<1, num_blocks>>>(d_partial_sums_and_total, d_result, 0, num_blocks);
// // Part 1 of 6: copy the result back to the host
int device_result = 0;
hipMemcpy(&device_result, d_result, sizeof(int), hipMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// // Part 1 of 6: deallocate device memory
return 0;
} | .text
.file "reduction_test_brouillon.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__block_sumPKiPimi # -- Begin function _Z24__device_stub__block_sumPKiPimi
.p2align 4, 0x90
.type _Z24__device_stub__block_sumPKiPimi,@function
_Z24__device_stub__block_sumPKiPimi: # @_Z24__device_stub__block_sumPKiPimi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9block_sumPKiPimi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__block_sumPKiPimi, .Lfunc_end0-_Z24__device_stub__block_sumPKiPimi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $10152, %rsp # imm = 0x27A8
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
leaq -5176(%rbp), %rbx
movq %rbx, -5192(%rbp)
movl $1634100580, -5176(%rbp) # imm = 0x61666564
movl $1953264993, -5173(%rbp) # imm = 0x746C7561
movq $7, -5184(%rbp)
movb $0, -5169(%rbp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq -10192(%rbp), %rdi
leaq -5192(%rbp), %rsi
callq _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq -5192(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB1_3
# %bb.2: # %.critedge.i.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_3: # %_ZNSt13random_deviceC2Ev.exit
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq -10192(%rbp), %rdi
callq _ZNSt13random_device9_M_getvalEv
.Ltmp4:
# %bb.4: # %_ZNSt13random_deviceclEv.exit
movl %eax, %eax
movq %rax, -5192(%rbp)
movl $1, %ecx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %rax, %rdx
shrq $30, %rdx
xorl %eax, %edx
imull $1812433253, %edx, %eax # imm = 0x6C078965
addl %ecx, %eax
movq %rax, -5192(%rbp,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB1_5
# %bb.6: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit
movq $624, -200(%rbp) # imm = 0x270
movabsq $47244640246, %rax # imm = 0xAFFFFFFF6
movq %rax, -192(%rbp)
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $1048576, %edi # imm = 0x100000
callq _Znwm
.Ltmp7:
# %bb.7: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
xorl %r12d, %r12d
movl $1048576, %edx # imm = 0x100000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq -5192(%rbp), %r14
leaq -192(%rbp), %r15
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
.Ltmp9:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.Ltmp10:
# %bb.9: # %_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_.exit
# in Loop: Header=BB1_8 Depth=1
movl %eax, (%rbx,%r12)
addq $4, %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_8
# %bb.10: # %.lr.ph.i.preheader
xorl %r14d, %r14d
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rax), %r14d
addq $4, %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_11
# %bb.12: # %_ZSt10accumulateIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEiET0_T_S8_S7_.exit
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl %r14d, %esi
callq _ZNSolsEi
.Ltmp15:
# %bb.14:
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_15
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_25
# %bb.24:
movzbl 67(%r15), %eax
jmp .LBB1_27
.LBB1_25:
.Ltmp16:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp17:
# %bb.26: # %.noexc79
movq (%r15), %rax
.Ltmp18:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp19:
.LBB1_27: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp20:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp21:
# %bb.28: # %.noexc81
.Ltmp22:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp23:
# %bb.29: # %_ZNSolsEPFRSoS_E.exit
.Ltmp24:
.cfi_escape 0x2e, 0x00
leaq -176(%rbp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
.Ltmp25:
# %bb.30: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
movq -176(%rbp), %rdi
.Ltmp26:
.cfi_escape 0x2e, 0x00
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp27:
# %bb.31:
.Ltmp29:
.cfi_escape 0x2e, 0x00
leaq -56(%rbp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
.Ltmp30:
# %bb.32: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit51
.Ltmp32:
.cfi_escape 0x2e, 0x00
leaq -168(%rbp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp33:
# %bb.33: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit52
.Ltmp34:
.cfi_escape 0x2e, 0x00
movabsq $4294967552, %rdi # imm = 0x100000100
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp35:
# %bb.34:
testl %eax, %eax
jne .LBB1_37
# %bb.35:
movq -176(%rbp), %rax
movq -56(%rbp), %rcx
movq %rax, -128(%rbp)
movq %rcx, -120(%rbp)
movq $262144, -112(%rbp) # imm = 0x40000
movl $1024, -44(%rbp) # imm = 0x400
leaq -128(%rbp), %rax
movq %rax, -160(%rbp)
leaq -120(%rbp), %rax
movq %rax, -152(%rbp)
leaq -112(%rbp), %rax
movq %rax, -144(%rbp)
leaq -44(%rbp), %rax
movq %rax, -136(%rbp)
.Ltmp36:
.cfi_escape 0x2e, 0x00
leaq -104(%rbp), %rdi
leaq -88(%rbp), %rsi
leaq -72(%rbp), %rdx
leaq -64(%rbp), %rcx
callq __hipPopCallConfiguration
.Ltmp37:
# %bb.36: # %.noexc
movq -104(%rbp), %rsi
movl -96(%rbp), %edx
movq -88(%rbp), %rcx
movl -80(%rbp), %r8d
.Ltmp38:
.cfi_escape 0x2e, 0x10
leaq -160(%rbp), %r9
movl $_Z9block_sumPKiPimi, %edi
pushq -64(%rbp)
pushq -72(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.Ltmp39:
.LBB1_37:
movq %rsp, -184(%rbp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movq %rsp, %r14
addq $-1024, %r14 # imm = 0xFC00
movq %r14, %rsp
movq -56(%rbp), %rsi
.Ltmp40:
.cfi_escape 0x2e, 0x00
movl $1024, %edx # imm = 0x400
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp41:
# %bb.38: # %.preheader.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_39: # %.preheader
# =>This Inner Loop Header: Depth=1
.Ltmp42:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp43:
# %bb.40: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit55
# in Loop: Header=BB1_39 Depth=1
.Ltmp44:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertImEERSoT_
.Ltmp45:
# %bb.41: # %_ZNSolsEj.exit
# in Loop: Header=BB1_39 Depth=1
.Ltmp46:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp47:
# %bb.42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit58
# in Loop: Header=BB1_39 Depth=1
movl (%r14,%r15,4), %esi
.Ltmp48:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSolsEi
.Ltmp49:
# %bb.43: # in Loop: Header=BB1_39 Depth=1
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_44
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i84
# in Loop: Header=BB1_39 Depth=1
cmpb $0, 56(%r13)
je .LBB1_52
# %bb.51: # in Loop: Header=BB1_39 Depth=1
movzbl 67(%r13), %eax
jmp .LBB1_54
.p2align 4, 0x90
.LBB1_52: # in Loop: Header=BB1_39 Depth=1
.Ltmp50:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp51:
# %bb.53: # %.noexc89
# in Loop: Header=BB1_39 Depth=1
movq (%r13), %rax
.Ltmp52:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp53:
.LBB1_54: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i86
# in Loop: Header=BB1_39 Depth=1
.Ltmp54:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp55:
# %bb.55: # %.noexc91
# in Loop: Header=BB1_39 Depth=1
.Ltmp56:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp57:
# %bb.56: # %_ZNSolsEPFRSoS_E.exit60
# in Loop: Header=BB1_39 Depth=1
incq %r15
cmpq $256, %r15 # imm = 0x100
jne .LBB1_39
# %bb.57:
.Ltmp59:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp60:
# %bb.58:
testl %eax, %eax
jne .LBB1_61
# %bb.59:
movq -56(%rbp), %rax
movq -168(%rbp), %rcx
movq %rax, -128(%rbp)
movq %rcx, -120(%rbp)
movq $0, -112(%rbp)
movl $256, -44(%rbp) # imm = 0x100
leaq -128(%rbp), %rax
movq %rax, -160(%rbp)
leaq -120(%rbp), %rax
movq %rax, -152(%rbp)
leaq -112(%rbp), %rax
movq %rax, -144(%rbp)
leaq -44(%rbp), %rax
movq %rax, -136(%rbp)
.Ltmp61:
.cfi_escape 0x2e, 0x00
leaq -104(%rbp), %rdi
leaq -88(%rbp), %rsi
leaq -72(%rbp), %rdx
leaq -64(%rbp), %rcx
callq __hipPopCallConfiguration
.Ltmp62:
# %bb.60: # %.noexc67
movq -104(%rbp), %rsi
movl -96(%rbp), %edx
movq -88(%rbp), %rcx
movl -80(%rbp), %r8d
.Ltmp63:
.cfi_escape 0x2e, 0x10
leaq -160(%rbp), %r9
movl $_Z9block_sumPKiPimi, %edi
pushq -64(%rbp)
pushq -72(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.Ltmp64:
.LBB1_61:
movl $0, -160(%rbp)
movq -168(%rbp), %rsi
.Ltmp66:
.cfi_escape 0x2e, 0x00
leaq -160(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp67:
# %bb.62:
.Ltmp68:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp69:
# %bb.63: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit71
movl -160(%rbp), %esi
.Ltmp70:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp71:
# %bb.64:
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_65
# %bb.69: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i95
cmpb $0, 56(%r15)
je .LBB1_71
# %bb.70:
movzbl 67(%r15), %eax
jmp .LBB1_73
.LBB1_71:
.Ltmp72:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp73:
# %bb.72: # %.noexc100
movq (%r15), %rax
.Ltmp74:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp75:
.LBB1_73: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i97
.Ltmp76:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp77:
# %bb.74: # %.noexc102
.Ltmp78:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp79:
# %bb.75: # %_ZNSolsEPFRSoS_E.exit73
movq -184(%rbp), %rsp # 8-byte Reload
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.Ltmp80:
.cfi_escape 0x2e, 0x00
leaq -10192(%rbp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp81:
# %bb.76: # %_ZNSt13random_deviceD2Ev.exit
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_44:
.cfi_def_cfa %rbp, 16
.Ltmp86:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp87:
# %bb.49: # %.noexc88
.LBB1_15:
.Ltmp89:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp90:
# %bb.22: # %.noexc78
.LBB1_65:
.Ltmp83:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp84:
# %bb.68: # %.noexc99
.LBB1_80:
.Ltmp82:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.LBB1_47:
.Ltmp31:
jmp .LBB1_78
.LBB1_20:
.Ltmp8:
movq %rax, %r14
jmp .LBB1_79
.LBB1_19:
.Ltmp5:
movq %rax, %r14
jmp .LBB1_79
.LBB1_16:
.Ltmp2:
movq %rax, %r14
movq -5192(%rbp), %rdi
cmpq %rbx, %rdi
je .LBB1_18
# %bb.17: # %.critedge.i.i6.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.LBB1_46:
.Ltmp28:
jmp .LBB1_78
.LBB1_48:
.Ltmp65:
jmp .LBB1_78
.LBB1_45:
.Ltmp91:
jmp .LBB1_78
.LBB1_77:
.Ltmp85:
jmp .LBB1_78
.LBB1_67: # %.loopexit.split-lp
.Ltmp88:
jmp .LBB1_78
.LBB1_21:
.Ltmp11:
jmp .LBB1_78
.LBB1_66: # %.loopexit
.Ltmp58:
.LBB1_78:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB1_79:
.Ltmp92:
.cfi_escape 0x2e, 0x00
leaq -10192(%rbp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp93:
.LBB1_18: # %common.resume
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.LBB1_81:
.Ltmp94:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp23-.Ltmp12 # Call between .Ltmp12 and .Ltmp23
.uleb128 .Ltmp91-.Lfunc_begin0 # jumps to .Ltmp91
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp27-.Ltmp24 # Call between .Ltmp24 and .Ltmp27
.uleb128 .Ltmp28-.Lfunc_begin0 # jumps to .Ltmp28
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp30-.Ltmp29 # Call between .Ltmp29 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp41-.Ltmp32 # Call between .Ltmp32 and .Ltmp41
.uleb128 .Ltmp65-.Lfunc_begin0 # jumps to .Ltmp65
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp57-.Ltmp42 # Call between .Ltmp42 and .Ltmp57
.uleb128 .Ltmp58-.Lfunc_begin0 # jumps to .Ltmp58
.byte 0 # On action: cleanup
.uleb128 .Ltmp59-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp64-.Ltmp59 # Call between .Ltmp59 and .Ltmp64
.uleb128 .Ltmp65-.Lfunc_begin0 # jumps to .Ltmp65
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp79-.Ltmp66 # Call between .Ltmp66 and .Ltmp79
.uleb128 .Ltmp85-.Lfunc_begin0 # jumps to .Ltmp85
.byte 0 # On action: cleanup
.uleb128 .Ltmp80-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp81-.Ltmp80 # Call between .Ltmp80 and .Ltmp81
.uleb128 .Ltmp82-.Lfunc_begin0 # jumps to .Ltmp82
.byte 1 # On action: 1
.uleb128 .Ltmp86-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp87-.Ltmp86 # Call between .Ltmp86 and .Ltmp87
.uleb128 .Ltmp88-.Lfunc_begin0 # jumps to .Ltmp88
.byte 0 # On action: cleanup
.uleb128 .Ltmp89-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp90-.Ltmp89 # Call between .Ltmp89 and .Ltmp90
.uleb128 .Ltmp91-.Lfunc_begin0 # jumps to .Ltmp91
.byte 0 # On action: cleanup
.uleb128 .Ltmp83-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp84-.Ltmp83 # Call between .Ltmp83 and .Ltmp84
.uleb128 .Ltmp85-.Lfunc_begin0 # jumps to .Ltmp85
.byte 0 # On action: cleanup
.uleb128 .Ltmp84-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp92-.Ltmp84 # Call between .Ltmp84 and .Ltmp92
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp92-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp93-.Ltmp92 # Call between .Ltmp92 and .Ltmp93
.uleb128 .Ltmp94-.Lfunc_begin0 # jumps to .Ltmp94
.byte 1 # On action: 1
.uleb128 .Ltmp93-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Lfunc_end1-.Ltmp93 # Call between .Ltmp93 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end2:
.size __clang_call_terminate, .Lfunc_end2-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE # -- Begin function _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.p2align 4, 0x90
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,@function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE: # @_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movslq 4(%rdx), %r15
movq %rdx, 8(%rsp) # 8-byte Spill
movslq (%rdx), %rax
subq %rax, %r15
movl $4294967294, %eax # imm = 0xFFFFFFFE
cmpq %rax, %r15
ja .LBB3_6
# %bb.1:
leal 1(%r15), %r12d
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %r12d
jbe .LBB3_5
# %bb.2:
notl %r15d
movq %rax, %rcx
movl %r15d, %eax
xorl %edx, %edx
divl %r12d
movq %rcx, %rax
cmpl %eax, %edx
jbe .LBB3_5
# %bb.3: # %.lr.ph.i.preheader
movl %edx, %ebp
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %ebp
ja .LBB3_4
.LBB3_5: # %_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_.exit
shrq $32, %rax
jmp .LBB3_11
.LBB3_6:
movl $4294967295, %eax # imm = 0xFFFFFFFF
cmpq %rax, %r15
jne .LBB3_7
# %bb.10:
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .LBB3_11
.LBB3_7: # %.preheader
movq %rdi, %r12
movabsq $-4294967296, %rbx # imm = 0xFFFFFFFF00000000
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB3_8: # =>This Inner Loop Header: Depth=1
movq %rbx, 16(%rsp)
movq %r12, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebp
shlq $32, %rbp
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %rbp, %rax
setb %cl
cmpq %r15, %rax
ja .LBB3_8
# %bb.9: # in Loop: Header=BB3_8 Depth=1
testb %cl, %cl
jne .LBB3_8
.LBB3_11: # %.loopexit
movq 8(%rsp), %rcx # 8-byte Reload
addl (%rcx), %eax
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .Lfunc_end3-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_startproc
# %bb.0:
cmpq $624, 4992(%rdi) # imm = 0x270
jb .LBB4_6
# %bb.1: # %.preheader.preheader
movl $2567483615, %eax # imm = 0x9908B0DF
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 3176(%rdi,%rdx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $227, %rsi
jne .LBB4_2
# %bb.3: # %.preheader.i.preheader
movl $228, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1824(%rdi,%rcx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB4_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 4984(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 3168(%rdi), %rsi
andl $1, %edx
negl %edx
andl %eax, %edx
xorq %rsi, %rdx
movq %rdx, 4984(%rdi)
movq $0, 4992(%rdi)
.LBB4_6:
movq 4992(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 4992(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $11, %rcx
movl %ecx, %ecx
xorq %rax, %rcx
movl %ecx, %eax
shll $7, %eax
andl $-1658038656, %eax # imm = 0x9D2C5680
xorq %rcx, %rax
movl %eax, %ecx
shll $15, %ecx
andl $-272236544, %ecx # imm = 0xEFC60000
xorq %rax, %rcx
movq %rcx, %rax
shrq $18, %rax
xorq %rcx, %rax
retq
.Lfunc_end4:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end4-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9block_sumPKiPimi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9block_sumPKiPimi,@object # @_Z9block_sumPKiPimi
.section .rodata,"a",@progbits
.globl _Z9block_sumPKiPimi
.p2align 3, 0x0
_Z9block_sumPKiPimi:
.quad _Z24__device_stub__block_sumPKiPimi
.size _Z9block_sumPKiPimi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Host sum: "
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "b("
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ") = "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device sum: "
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "default"
.size .L.str.4, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9block_sumPKiPimi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__block_sumPKiPimi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9block_sumPKiPimi
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9block_sumPKiPimi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0030*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, 0x400 ; /* 0x0000040000057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x001fca00078e0003 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9block_sumPKiPimi
.globl _Z9block_sumPKiPimi
.p2align 8
.type _Z9block_sumPKiPimi,@function
_Z9block_sumPKiPimi:
s_mov_b32 s3, 0
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s2, s15
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x400
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9block_sumPKiPimi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9block_sumPKiPimi, .Lfunc_end0-_Z9block_sumPKiPimi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9block_sumPKiPimi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z9block_sumPKiPimi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ static void solveFull ( double* data, double* inv1, double* inv2, const int nx, const int nBatch )
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set values to last two entries in array
double oldNx2 = data[(nx - 2) * nBatch + globalIdx]; // Two points from end
double oldNx1 = data[(nx - 1) * nBatch + globalIdx]; // One point from end
// Set index being computed
int index = globalIdy * nBatch + globalIdx;
if (globalIdy < nx - 2)
{
data[index] = data[index] - (inv1[index] * oldNx2 + inv2[index] * oldNx1);
}
} | code for sm_80
Function : _Z9solveFullPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0040*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe200078e0203 */
/*0050*/ IADD3 R3, R2, -0x2, RZ ; /* 0xfffffffe02037810 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0090*/ HFMA2.MMA R13, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0d7435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*00c0*/ IMAD R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a24 */
/* 0x001fc800078e0202 */
/*00d0*/ IMAD R3, R3, c[0x0][0x17c], R2.reuse ; /* 0x00005f0003037a24 */
/* 0x100fe400078e0202 */
/*00e0*/ IMAD R2, R0, c[0x0][0x17c], R2 ; /* 0x00005f0000027a24 */
/* 0x000fc600078e0202 */
/*00f0*/ IADD3 R10, R3, c[0x0][0x17c], RZ ; /* 0x00005f00030a7a10 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.WIDE R8, R2, R13, c[0x0][0x170] ; /* 0x00005c0002087625 */
/* 0x000fc800078e020d */
/*0110*/ IMAD.WIDE R10, R10, R13.reuse, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x080fe400078e020d */
/*0120*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1b00 */
/*0130*/ IMAD.WIDE R4, R2.reuse, R13.reuse, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x0c0fe400078e020d */
/*0140*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1b00 */
/*0150*/ IMAD.WIDE R6, R3, R13.reuse, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x080fe400078e020d */
/*0160*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1b00 */
/*0170*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc400078e020d */
/*0180*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1b00 */
/*0190*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000f22000c1e1b00 */
/*01a0*/ DMUL R12, R8, R10 ; /* 0x0000000a080c7228 */
/* 0x004ecc0000000000 */
/*01b0*/ DFMA R12, R4, R6, R12 ; /* 0x00000006040c722b */
/* 0x008f0c000000000c */
/*01c0*/ DADD R12, -R12, R14 ; /* 0x000000000c0c7229 */
/* 0x010e0e000000010e */
/*01d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x001fe2000c101b04 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ static void solveFull ( double* data, double* inv1, double* inv2, const int nx, const int nBatch )
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set values to last two entries in array
double oldNx2 = data[(nx - 2) * nBatch + globalIdx]; // Two points from end
double oldNx1 = data[(nx - 1) * nBatch + globalIdx]; // One point from end
// Set index being computed
int index = globalIdy * nBatch + globalIdx;
if (globalIdy < nx - 2)
{
data[index] = data[index] - (inv1[index] * oldNx2 + inv2[index] * oldNx1);
}
} | .file "tmpxft_000c3f80_00000000-6_solveFull.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL9solveFullPdS_S_ii, @function
_ZL9solveFullPdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, (%rsp)
movl %r8d, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL9solveFullPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL9solveFullPdS_S_ii, .-_ZL9solveFullPdS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9solveFullPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9solveFullPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ static void solveFull ( double* data, double* inv1, double* inv2, const int nx, const int nBatch )
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set values to last two entries in array
double oldNx2 = data[(nx - 2) * nBatch + globalIdx]; // Two points from end
double oldNx1 = data[(nx - 1) * nBatch + globalIdx]; // One point from end
// Set index being computed
int index = globalIdy * nBatch + globalIdx;
if (globalIdy < nx - 2)
{
data[index] = data[index] - (inv1[index] * oldNx2 + inv2[index] * oldNx1);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void solveFull ( double* data, double* inv1, double* inv2, const int nx, const int nBatch )
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set values to last two entries in array
double oldNx2 = data[(nx - 2) * nBatch + globalIdx]; // Two points from end
double oldNx1 = data[(nx - 1) * nBatch + globalIdx]; // One point from end
// Set index being computed
int index = globalIdy * nBatch + globalIdx;
if (globalIdy < nx - 2)
{
data[index] = data[index] - (inv1[index] * oldNx2 + inv2[index] * oldNx1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void solveFull ( double* data, double* inv1, double* inv2, const int nx, const int nBatch )
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set values to last two entries in array
double oldNx2 = data[(nx - 2) * nBatch + globalIdx]; // Two points from end
double oldNx1 = data[(nx - 1) * nBatch + globalIdx]; // One point from end
// Set index being computed
int index = globalIdy * nBatch + globalIdx;
if (globalIdy < nx - 2)
{
data[index] = data[index] - (inv1[index] * oldNx2 + inv2[index] * oldNx1);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL9solveFullPdS_S_ii,"axG",@progbits,_ZL9solveFullPdS_S_ii,comdat
.globl _ZL9solveFullPdS_S_ii
.p2align 8
.type _ZL9solveFullPdS_S_ii,@function
_ZL9solveFullPdS_S_ii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s5, 16
s_add_i32 s8, s4, -2
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[2:3], 0xc
s_load_b32 s3, s[0:1], 0x1c
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
s_add_i32 s2, s4, -1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s2, s3, v[2:3]
v_mad_u64_u32 v[5:6], null, v1, s3, v[2:3]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 3, v[3:4]
v_ashrrev_i32_e32 v6, 31, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_lshlrev_b64 v[3:4], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[5:6], v[5:6], off
v_mad_u64_u32 v[7:8], null, s8, s3, v[2:3]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v4, vcc_lo
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[9:10], v[9:10], off
v_add_co_u32 v2, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[11:12], v[2:3], off
s_waitcnt vmcnt(3)
v_mul_f64 v[0:1], v[0:1], v[5:6]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[7:8], v[9:10], v[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[11:12], -v[0:1]
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL9solveFullPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL9solveFullPdS_S_ii,"axG",@progbits,_ZL9solveFullPdS_S_ii,comdat
.Lfunc_end0:
.size _ZL9solveFullPdS_S_ii, .Lfunc_end0-_ZL9solveFullPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL9solveFullPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL9solveFullPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void solveFull ( double* data, double* inv1, double* inv2, const int nx, const int nBatch )
{
// Matrix index
int globalIdx = blockDim.x * blockIdx.x + threadIdx.x;
int globalIdy = blockDim.y * blockIdx.y + threadIdx.y;
// Set values to last two entries in array
double oldNx2 = data[(nx - 2) * nBatch + globalIdx]; // Two points from end
double oldNx1 = data[(nx - 1) * nBatch + globalIdx]; // One point from end
// Set index being computed
int index = globalIdy * nBatch + globalIdx;
if (globalIdy < nx - 2)
{
data[index] = data[index] - (inv1[index] * oldNx2 + inv2[index] * oldNx1);
}
} | .text
.file "solveFull.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9solveFullPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0040*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe200078e0203 */
/*0050*/ IADD3 R3, R2, -0x2, RZ ; /* 0xfffffffe02037810 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0090*/ HFMA2.MMA R13, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0d7435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*00c0*/ IMAD R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a24 */
/* 0x001fc800078e0202 */
/*00d0*/ IMAD R3, R3, c[0x0][0x17c], R2.reuse ; /* 0x00005f0003037a24 */
/* 0x100fe400078e0202 */
/*00e0*/ IMAD R2, R0, c[0x0][0x17c], R2 ; /* 0x00005f0000027a24 */
/* 0x000fc600078e0202 */
/*00f0*/ IADD3 R10, R3, c[0x0][0x17c], RZ ; /* 0x00005f00030a7a10 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.WIDE R8, R2, R13, c[0x0][0x170] ; /* 0x00005c0002087625 */
/* 0x000fc800078e020d */
/*0110*/ IMAD.WIDE R10, R10, R13.reuse, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x080fe400078e020d */
/*0120*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1b00 */
/*0130*/ IMAD.WIDE R4, R2.reuse, R13.reuse, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x0c0fe400078e020d */
/*0140*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1b00 */
/*0150*/ IMAD.WIDE R6, R3, R13.reuse, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x080fe400078e020d */
/*0160*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1b00 */
/*0170*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc400078e020d */
/*0180*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1b00 */
/*0190*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000f22000c1e1b00 */
/*01a0*/ DMUL R12, R8, R10 ; /* 0x0000000a080c7228 */
/* 0x004ecc0000000000 */
/*01b0*/ DFMA R12, R4, R6, R12 ; /* 0x00000006040c722b */
/* 0x008f0c000000000c */
/*01c0*/ DADD R12, -R12, R14 ; /* 0x000000000c0c7229 */
/* 0x010e0e000000010e */
/*01d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x001fe2000c101b04 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL9solveFullPdS_S_ii,"axG",@progbits,_ZL9solveFullPdS_S_ii,comdat
.globl _ZL9solveFullPdS_S_ii
.p2align 8
.type _ZL9solveFullPdS_S_ii,@function
_ZL9solveFullPdS_S_ii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s5, 16
s_add_i32 s8, s4, -2
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[2:3], 0xc
s_load_b32 s3, s[0:1], 0x1c
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
s_add_i32 s2, s4, -1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s2, s3, v[2:3]
v_mad_u64_u32 v[5:6], null, v1, s3, v[2:3]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 3, v[3:4]
v_ashrrev_i32_e32 v6, 31, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_lshlrev_b64 v[3:4], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[5:6], v[5:6], off
v_mad_u64_u32 v[7:8], null, s8, s3, v[2:3]
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v4, vcc_lo
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[9:10], v[9:10], off
v_add_co_u32 v2, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[11:12], v[2:3], off
s_waitcnt vmcnt(3)
v_mul_f64 v[0:1], v[0:1], v[5:6]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[7:8], v[9:10], v[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[11:12], -v[0:1]
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL9solveFullPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL9solveFullPdS_S_ii,"axG",@progbits,_ZL9solveFullPdS_S_ii,comdat
.Lfunc_end0:
.size _ZL9solveFullPdS_S_ii, .Lfunc_end0-_ZL9solveFullPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL9solveFullPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL9solveFullPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c3f80_00000000-6_solveFull.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL9solveFullPdS_S_ii, @function
_ZL9solveFullPdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, (%rsp)
movl %r8d, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL9solveFullPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL9solveFullPdS_S_ii, .-_ZL9solveFullPdS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9solveFullPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9solveFullPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "solveFull.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define NUM_THREADS 32
__global__ void euclidean_kernel(const float * vg_a, size_t pitch_a, size_t n_a, const float * vg_b, size_t pitch_b, size_t n_b, size_t k, float * d, size_t pitch_d, float p)
{
size_t x = blockIdx.x;
size_t y = blockIdx.y;
// If an element is to be computed
if(x < n_a && y < n_b) {
__shared__ float temp[NUM_THREADS];
temp[threadIdx.x] = 0.0;
for(size_t offset = threadIdx.x; offset < k; offset += blockDim.x) {
float t = vg_a[x * pitch_a + offset] - vg_b[y * pitch_b + offset];
temp[threadIdx.x] += (t * t);
}
// Sync with other threads
__syncthreads();
// Reduce
for(size_t stride = blockDim.x >> 1; stride > 0; stride >>= 1) {
if(threadIdx.x < stride) {
temp[threadIdx.x] += temp[threadIdx.x + stride];
}
__syncthreads();
}
// Write to global memory
if(threadIdx.x == 0) {
d[y * pitch_d + x] = sqrt(temp[0]);
}
}
} | code for sm_80
Function : _Z16euclidean_kernelPKfmmS0_mmmPfmf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*0030*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x188], PT ; /* 0x0000620005007a0c */
/* 0x001fe40003f26070 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x002fe40003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P1, PT, RZ, c[0x0][0x18c], PT, P1 ; /* 0x00006300ff007a0c */
/* 0x000fc80003f26110 */
/*0060*/ ISETP.GE.U32.OR.EX P0, PT, RZ, c[0x0][0x174], P1, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0000f06500 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e220000002100 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ BSSY B0, 0x2a0 ; /* 0x000001f000007945 */
/* 0x000fe40003800000 */
/*00b0*/ STS [R15.X4], RZ ; /* 0x000000ff0f007388 */
/* 0x0011e20000004800 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R15.reuse, c[0x0][0x190], PT ; /* 0x000064000f007a0c */
/* 0x040fe20003f06070 */
/*00d0*/ IMAD.SHL.U32 R0, R15, 0x4, RZ ; /* 0x000000040f007824 */
/* 0x000fc600078e00ff */
/*00e0*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x194], PT, P0 ; /* 0x00006500ff007a0c */
/* 0x000fda0003f06100 */
/*00f0*/ @P0 BRA 0x290 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*0100*/ BSSY B1, 0x280 ; /* 0x0000017000017945 */
/* 0x001fe20003800000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R14, R15 ; /* 0x0000000f000e7202 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fca00078e00ff */
/*0140*/ MOV R9, R17 ; /* 0x0000001100097202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fc800078e000e */
/*0160*/ IMAD.WIDE.U32 R6, R2, c[0x0][0x168], R8 ; /* 0x00005a0002067a25 */
/* 0x000fc800078e0008 */
/*0170*/ IMAD.WIDE.U32 R8, R5, c[0x0][0x180], R8 ; /* 0x0000600005087a25 */
/* 0x000fe200078e0008 */
/*0180*/ LEA R12, P0, R6, c[0x0][0x160], 0x2 ; /* 0x00005800060c7a11 */
/* 0x000fc600078010ff */
/*0190*/ IMAD R11, R2, c[0x0][0x16c], R7 ; /* 0x00005b00020b7a24 */
/* 0x000fe200078e0207 */
/*01a0*/ LEA R10, P1, R8, c[0x0][0x178], 0x2 ; /* 0x00005e00080a7a11 */
/* 0x000fe200078210ff */
/*01b0*/ IMAD R7, R5, c[0x0][0x184], R9 ; /* 0x0000610005077a24 */
/* 0x000fc600078e0209 */
/*01c0*/ LEA.HI.X R13, R6, c[0x0][0x164], R11, 0x2, P0 ; /* 0x00005900060d7a11 */
/* 0x000fe400000f140b */
/*01d0*/ LEA.HI.X R11, R8, c[0x0][0x17c], R7, 0x2, P1 ; /* 0x00005f00080b7a11 */
/* 0x000fc800008f1407 */
/*01e0*/ LDG.E R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R14, P0, R14, c[0x0][0x0], RZ ; /* 0x000000000e0e7a10 */
/* 0x000fca0007f1e0ff */
/*0210*/ IMAD.X R17, RZ, RZ, R17, P0 ; /* 0x000000ffff117224 */
/* 0x000fe200000e0611 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R14, c[0x0][0x190], PT ; /* 0x000064000e007a0c */
/* 0x000fc80003f06070 */
/*0230*/ ISETP.GE.U32.AND.EX P0, PT, R17, c[0x0][0x194], PT, P0 ; /* 0x0000650011007a0c */
/* 0x000fe20003f06100 */
/*0240*/ FADD R7, -R10, R13 ; /* 0x0000000d0a077221 */
/* 0x004fc80000000100 */
/*0250*/ FFMA R4, R7, R7, R4 ; /* 0x0000000707047223 */
/* 0x000fd00000000004 */
/*0260*/ @!P0 BRA 0x140 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*0270*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0280*/ STS [R15.X4], R4 ; /* 0x000000040f007388 */
/* 0x0001e40000004800 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*02d0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fca0003f25270 */
/*02e0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*02f0*/ @!P0 BRA 0x3f0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0300*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0310*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fca000f8e00ff */
/*0320*/ ISETP.GT.U32.AND P0, PT, R8, R15, PT ; /* 0x0000000f0800720c */
/* 0x000fc80003f04070 */
/*0330*/ ISETP.GT.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f04100 */
/*0340*/ @P0 IMAD R4, R8.reuse, 0x4, R0 ; /* 0x0000000408040824 */
/* 0x040fe200078e0200 */
/*0350*/ @P0 LDS R6, [R15.X4] ; /* 0x000000000f060984 */
/* 0x000fe20000004800 */
/*0360*/ SHF.R.U64 R8, R8, 0x1, R9.reuse ; /* 0x0000000108087819 */
/* 0x100fe40000001209 */
/*0370*/ SHF.R.U32.HI R9, RZ, 0x1, R9 ; /* 0x00000001ff097819 */
/* 0x000fe20000011609 */
/*0380*/ @P0 LDS R7, [R4] ; /* 0x0000000004070984 */
/* 0x000e240000000800 */
/*0390*/ @P0 FADD R6, R6, R7 ; /* 0x0000000706060221 */
/* 0x001fca0000000000 */
/*03a0*/ @P0 STS [R15.X4], R6 ; /* 0x000000060f000388 */
/* 0x0001e80000004800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03c0*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*03d0*/ ISETP.NE.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f05300 */
/*03e0*/ @P0 BRA 0x320 ; /* 0xffffff3000000947 */
/* 0x001fea000383ffff */
/*03f0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0400*/ LDS R0, [RZ] ; /* 0x00000000ff007984 */
/* 0x000e240000000800 */
/*0410*/ IADD3 R4, R0, -0xd000000, RZ ; /* 0xf300000000047810 */
/* 0x001fe20007ffe0ff */
/*0420*/ MUFU.RSQ R7, R0 ; /* 0x0000000000077308 */
/* 0x0000660000001400 */
/*0430*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0440*/ @!P0 BRA 0x490 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0450*/ MOV R6, 0x470 ; /* 0x0000047000067802 */
/* 0x003fe40000000f00 */
/*0460*/ CALL.REL.NOINC 0x540 ; /* 0x000000d000007944 */
/* 0x000fea0003c00000 */
/*0470*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0004 */
/*0480*/ BRA 0x4d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0490*/ FMUL.FTZ R9, R0, R7 ; /* 0x0000000700097220 */
/* 0x003fe40000410000 */
/*04a0*/ FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007077820 */
/* 0x000fe40000410000 */
/*04b0*/ FFMA R0, -R9, R9, R0 ; /* 0x0000000909007223 */
/* 0x000fc80000000100 */
/*04c0*/ FFMA R7, R0, R7, R9 ; /* 0x0000000700077223 */
/* 0x000fe40000000009 */
/*04d0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fca0000000f00 */
/*04e0*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x1a0], R2 ; /* 0x0000680005027a25 */
/* 0x000fc800078e0002 */
/*04f0*/ IMAD R5, R5, c[0x0][0x1a4], R3 ; /* 0x0000690005057a24 */
/* 0x000fe200078e0203 */
/*0500*/ LEA R4, P0, R2, c[0x0][0x198], 0x2 ; /* 0x0000660002047a11 */
/* 0x000fc800078010ff */
/*0510*/ LEA.HI.X R5, R2, c[0x0][0x19c], R5, 0x2, P0 ; /* 0x0000670002057a11 */
/* 0x000fca00000f1405 */
/*0520*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101906 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00ff7812 */
/* 0x000fda000780c0ff */
/*0550*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0000 */
/*0560*/ @!P0 BRA 0x680 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0570*/ FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f1e000 */
/*0580*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff048424 */
/* 0x000fe200078e00ff */
/*0590*/ @!P0 BRA 0x680 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1c200 */
/*05b0*/ @P0 FADD.FTZ R4, R0, 1 ; /* 0x3f80000000040421 */
/* 0x000fe20000010000 */
/*05c0*/ @P0 BRA 0x680 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*05d0*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1d200 */
/*05e0*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*05f0*/ @!P0 BRA 0x680 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0600*/ FFMA R0, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000007823 */
/* 0x000fc800000000ff */
/*0610*/ MUFU.RSQ R7, R0 ; /* 0x0000000000077308 */
/* 0x000e240000001400 */
/*0620*/ FMUL.FTZ R9, R0, R7 ; /* 0x0000000700097220 */
/* 0x001fe40000410000 */
/*0630*/ FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007077820 */
/* 0x000fe40000410000 */
/*0640*/ FADD.FTZ R4, -R9, -RZ ; /* 0x800000ff09047221 */
/* 0x000fc80000010100 */
/*0650*/ FFMA R4, R9, R4, R0 ; /* 0x0000000409047223 */
/* 0x000fc80000000000 */
/*0660*/ FFMA R4, R4, R7, R9 ; /* 0x0000000704047223 */
/* 0x000fc80000000009 */
/*0670*/ FMUL.FTZ R4, R4, 2.3283064365386962891e-10 ; /* 0x2f80000004047820 */
/* 0x000fe40000410000 */
/*0680*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0690*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff96006007950 */
/* 0x000fea0003c3ffff */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define NUM_THREADS 32
__global__ void euclidean_kernel(const float * vg_a, size_t pitch_a, size_t n_a, const float * vg_b, size_t pitch_b, size_t n_b, size_t k, float * d, size_t pitch_d, float p)
{
size_t x = blockIdx.x;
size_t y = blockIdx.y;
// If an element is to be computed
if(x < n_a && y < n_b) {
__shared__ float temp[NUM_THREADS];
temp[threadIdx.x] = 0.0;
for(size_t offset = threadIdx.x; offset < k; offset += blockDim.x) {
float t = vg_a[x * pitch_a + offset] - vg_b[y * pitch_b + offset];
temp[threadIdx.x] += (t * t);
}
// Sync with other threads
__syncthreads();
// Reduce
for(size_t stride = blockDim.x >> 1; stride > 0; stride >>= 1) {
if(threadIdx.x < stride) {
temp[threadIdx.x] += temp[threadIdx.x + stride];
}
__syncthreads();
}
// Write to global memory
if(threadIdx.x == 0) {
d[y * pitch_d + x] = sqrt(temp[0]);
}
}
} | .file "tmpxft_0009f1ec_00000000-6_euclidean_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf
.type _Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf, @function
_Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 4(%rsp)
movq 248(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z16euclidean_kernelPKfmmS0_mmmPfmf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf, .-_Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf
.globl _Z16euclidean_kernelPKfmmS0_mmmPfmf
.type _Z16euclidean_kernelPKfmmS0_mmmPfmf, @function
_Z16euclidean_kernelPKfmmS0_mmmPfmf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16euclidean_kernelPKfmmS0_mmmPfmf, .-_Z16euclidean_kernelPKfmmS0_mmmPfmf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16euclidean_kernelPKfmmS0_mmmPfmf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16euclidean_kernelPKfmmS0_mmmPfmf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define NUM_THREADS 32
__global__ void euclidean_kernel(const float * vg_a, size_t pitch_a, size_t n_a, const float * vg_b, size_t pitch_b, size_t n_b, size_t k, float * d, size_t pitch_d, float p)
{
size_t x = blockIdx.x;
size_t y = blockIdx.y;
// If an element is to be computed
if(x < n_a && y < n_b) {
__shared__ float temp[NUM_THREADS];
temp[threadIdx.x] = 0.0;
for(size_t offset = threadIdx.x; offset < k; offset += blockDim.x) {
float t = vg_a[x * pitch_a + offset] - vg_b[y * pitch_b + offset];
temp[threadIdx.x] += (t * t);
}
// Sync with other threads
__syncthreads();
// Reduce
for(size_t stride = blockDim.x >> 1; stride > 0; stride >>= 1) {
if(threadIdx.x < stride) {
temp[threadIdx.x] += temp[threadIdx.x + stride];
}
__syncthreads();
}
// Write to global memory
if(threadIdx.x == 0) {
d[y * pitch_d + x] = sqrt(temp[0]);
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUM_THREADS 32
__global__ void euclidean_kernel(const float * vg_a, size_t pitch_a, size_t n_a, const float * vg_b, size_t pitch_b, size_t n_b, size_t k, float * d, size_t pitch_d, float p)
{
size_t x = blockIdx.x;
size_t y = blockIdx.y;
// If an element is to be computed
if(x < n_a && y < n_b) {
__shared__ float temp[NUM_THREADS];
temp[threadIdx.x] = 0.0;
for(size_t offset = threadIdx.x; offset < k; offset += blockDim.x) {
float t = vg_a[x * pitch_a + offset] - vg_b[y * pitch_b + offset];
temp[threadIdx.x] += (t * t);
}
// Sync with other threads
__syncthreads();
// Reduce
for(size_t stride = blockDim.x >> 1; stride > 0; stride >>= 1) {
if(threadIdx.x < stride) {
temp[threadIdx.x] += temp[threadIdx.x + stride];
}
__syncthreads();
}
// Write to global memory
if(threadIdx.x == 0) {
d[y * pitch_d + x] = sqrt(temp[0]);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUM_THREADS 32
__global__ void euclidean_kernel(const float * vg_a, size_t pitch_a, size_t n_a, const float * vg_b, size_t pitch_b, size_t n_b, size_t k, float * d, size_t pitch_d, float p)
{
size_t x = blockIdx.x;
size_t y = blockIdx.y;
// If an element is to be computed
if(x < n_a && y < n_b) {
__shared__ float temp[NUM_THREADS];
temp[threadIdx.x] = 0.0;
for(size_t offset = threadIdx.x; offset < k; offset += blockDim.x) {
float t = vg_a[x * pitch_a + offset] - vg_b[y * pitch_b + offset];
temp[threadIdx.x] += (t * t);
}
// Sync with other threads
__syncthreads();
// Reduce
for(size_t stride = blockDim.x >> 1; stride > 0; stride >>= 1) {
if(threadIdx.x < stride) {
temp[threadIdx.x] += temp[threadIdx.x + stride];
}
__syncthreads();
}
// Write to global memory
if(threadIdx.x == 0) {
d[y * pitch_d + x] = sqrt(temp[0]);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16euclidean_kernelPKfmmS0_mmmPfmf
.globl _Z16euclidean_kernelPKfmmS0_mmmPfmf
.p2align 8
.type _Z16euclidean_kernelPKfmmS0_mmmPfmf,@function
_Z16euclidean_kernelPKfmmS0_mmmPfmf:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x28
s_mov_b32 s8, s15
s_mov_b32 s15, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mov_b32 s9, s15
s_waitcnt lgkmcnt(0)
v_cmp_ge_u64_e64 s2, s[14:15], s[2:3]
v_cmp_ge_u64_e64 s3, s[8:9], s[4:5]
s_or_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_12
s_load_b64 s[10:11], s[0:1], 0x30
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 2, v0
s_mov_b32 s3, exec_lo
ds_store_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[10:11], v[0:1]
s_cbranch_execz .LBB0_5
s_clause 0x2
s_load_b128 s[16:19], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x5c
ds_load_b32 v5, v4
v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v6, 2, v0
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s14, s19
s_mul_hi_u32 s19, s14, s18
s_mul_i32 s12, s14, s18
s_add_i32 s13, s19, s13
s_mul_i32 s20, s8, s7
s_lshl_b64 s[12:13], s[12:13], 2
s_mul_hi_u32 s19, s8, s6
s_mul_i32 s18, s8, s6
s_add_u32 s6, s16, s12
s_addc_u32 s7, s17, s13
s_add_i32 s19, s19, s20
s_mov_b32 s16, s9
s_lshl_b64 s[12:13], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s4, s4, s12
s_addc_u32 s5, s5, s13
s_and_b32 s12, s2, 0xffff
s_mov_b32 s13, s9
s_lshl_b32 s17, s12, 2
.p2align 6
.LBB0_3:
v_add_co_u32 v8, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s12
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[10:11], off
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v6, s2, v6, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s2, s13, v7, s2
v_cmp_le_u64_e32 vcc_lo, s[10:11], v[2:3]
s_or_b32 s16, vcc_lo, s16
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, v8, v8
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s16
ds_store_b32 v4, v5
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s2, s[0:1], 0x5c
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s3, s2, 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_10
s_and_b32 s2, 0xffff, s2
s_mov_b32 s3, 0
s_lshr_b32 s2, s2, 1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_lt_u64_e64 s4, s[2:3], 2
s_lshr_b64 s[2:3], s[2:3], 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_10
.LBB0_8:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u64_e64 s[2:3], v[0:1]
s_cbranch_execz .LBB0_7
v_add_lshl_u32 v2, v0, s2, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v4, v2
s_branch .LBB0_7
.LBB0_10:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v0, 0
s_load_b128 s[4:7], s[0:1], 0x38
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s8, s7
s_mul_hi_u32 s2, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_add_i32 s1, s2, s1
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
v_fma_f32 v5, -v3, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v2, v1
v_cmp_ge_f32_e64 s0, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v3, s0
v_cmp_lt_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v2, v2, v4, s0
s_mul_i32 s0, s8, s6
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_lshl_b64 s[0:1], s[14:15], 2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
global_store_b32 v0, v1, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16euclidean_kernelPKfmmS0_mmmPfmf
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16euclidean_kernelPKfmmS0_mmmPfmf, .Lfunc_end0-_Z16euclidean_kernelPKfmmS0_mmmPfmf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 8
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16euclidean_kernelPKfmmS0_mmmPfmf
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z16euclidean_kernelPKfmmS0_mmmPfmf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUM_THREADS 32
__global__ void euclidean_kernel(const float * vg_a, size_t pitch_a, size_t n_a, const float * vg_b, size_t pitch_b, size_t n_b, size_t k, float * d, size_t pitch_d, float p)
{
size_t x = blockIdx.x;
size_t y = blockIdx.y;
// If an element is to be computed
if(x < n_a && y < n_b) {
__shared__ float temp[NUM_THREADS];
temp[threadIdx.x] = 0.0;
for(size_t offset = threadIdx.x; offset < k; offset += blockDim.x) {
float t = vg_a[x * pitch_a + offset] - vg_b[y * pitch_b + offset];
temp[threadIdx.x] += (t * t);
}
// Sync with other threads
__syncthreads();
// Reduce
for(size_t stride = blockDim.x >> 1; stride > 0; stride >>= 1) {
if(threadIdx.x < stride) {
temp[threadIdx.x] += temp[threadIdx.x + stride];
}
__syncthreads();
}
// Write to global memory
if(threadIdx.x == 0) {
d[y * pitch_d + x] = sqrt(temp[0]);
}
}
} | .text
.file "euclidean_kernel.hip"
.globl _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf # -- Begin function _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf
.p2align 4, 0x90
.type _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf,@function
_Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf: # @_Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16euclidean_kernelPKfmmS0_mmmPfmf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf, .Lfunc_end0-_Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16euclidean_kernelPKfmmS0_mmmPfmf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16euclidean_kernelPKfmmS0_mmmPfmf,@object # @_Z16euclidean_kernelPKfmmS0_mmmPfmf
.section .rodata,"a",@progbits
.globl _Z16euclidean_kernelPKfmmS0_mmmPfmf
.p2align 3, 0x0
_Z16euclidean_kernelPKfmmS0_mmmPfmf:
.quad _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf
.size _Z16euclidean_kernelPKfmmS0_mmmPfmf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16euclidean_kernelPKfmmS0_mmmPfmf"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16euclidean_kernelPKfmmS0_mmmPfmf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16euclidean_kernelPKfmmS0_mmmPfmf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*0030*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x188], PT ; /* 0x0000620005007a0c */
/* 0x001fe40003f26070 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x002fe40003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P1, PT, RZ, c[0x0][0x18c], PT, P1 ; /* 0x00006300ff007a0c */
/* 0x000fc80003f26110 */
/*0060*/ ISETP.GE.U32.OR.EX P0, PT, RZ, c[0x0][0x174], P1, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0000f06500 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e220000002100 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ BSSY B0, 0x2a0 ; /* 0x000001f000007945 */
/* 0x000fe40003800000 */
/*00b0*/ STS [R15.X4], RZ ; /* 0x000000ff0f007388 */
/* 0x0011e20000004800 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R15.reuse, c[0x0][0x190], PT ; /* 0x000064000f007a0c */
/* 0x040fe20003f06070 */
/*00d0*/ IMAD.SHL.U32 R0, R15, 0x4, RZ ; /* 0x000000040f007824 */
/* 0x000fc600078e00ff */
/*00e0*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x194], PT, P0 ; /* 0x00006500ff007a0c */
/* 0x000fda0003f06100 */
/*00f0*/ @P0 BRA 0x290 ; /* 0x0000019000000947 */
/* 0x000fea0003800000 */
/*0100*/ BSSY B1, 0x280 ; /* 0x0000017000017945 */
/* 0x001fe20003800000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0120*/ MOV R14, R15 ; /* 0x0000000f000e7202 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fca00078e00ff */
/*0140*/ MOV R9, R17 ; /* 0x0000001100097202 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fc800078e000e */
/*0160*/ IMAD.WIDE.U32 R6, R2, c[0x0][0x168], R8 ; /* 0x00005a0002067a25 */
/* 0x000fc800078e0008 */
/*0170*/ IMAD.WIDE.U32 R8, R5, c[0x0][0x180], R8 ; /* 0x0000600005087a25 */
/* 0x000fe200078e0008 */
/*0180*/ LEA R12, P0, R6, c[0x0][0x160], 0x2 ; /* 0x00005800060c7a11 */
/* 0x000fc600078010ff */
/*0190*/ IMAD R11, R2, c[0x0][0x16c], R7 ; /* 0x00005b00020b7a24 */
/* 0x000fe200078e0207 */
/*01a0*/ LEA R10, P1, R8, c[0x0][0x178], 0x2 ; /* 0x00005e00080a7a11 */
/* 0x000fe200078210ff */
/*01b0*/ IMAD R7, R5, c[0x0][0x184], R9 ; /* 0x0000610005077a24 */
/* 0x000fc600078e0209 */
/*01c0*/ LEA.HI.X R13, R6, c[0x0][0x164], R11, 0x2, P0 ; /* 0x00005900060d7a11 */
/* 0x000fe400000f140b */
/*01d0*/ LEA.HI.X R11, R8, c[0x0][0x17c], R7, 0x2, P1 ; /* 0x00005f00080b7a11 */
/* 0x000fc800008f1407 */
/*01e0*/ LDG.E R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R14, P0, R14, c[0x0][0x0], RZ ; /* 0x000000000e0e7a10 */
/* 0x000fca0007f1e0ff */
/*0210*/ IMAD.X R17, RZ, RZ, R17, P0 ; /* 0x000000ffff117224 */
/* 0x000fe200000e0611 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R14, c[0x0][0x190], PT ; /* 0x000064000e007a0c */
/* 0x000fc80003f06070 */
/*0230*/ ISETP.GE.U32.AND.EX P0, PT, R17, c[0x0][0x194], PT, P0 ; /* 0x0000650011007a0c */
/* 0x000fe20003f06100 */
/*0240*/ FADD R7, -R10, R13 ; /* 0x0000000d0a077221 */
/* 0x004fc80000000100 */
/*0250*/ FFMA R4, R7, R7, R4 ; /* 0x0000000707047223 */
/* 0x000fd00000000004 */
/*0260*/ @!P0 BRA 0x140 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*0270*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0280*/ STS [R15.X4], R4 ; /* 0x000000040f007388 */
/* 0x0001e40000004800 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*02d0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fca0003f25270 */
/*02e0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*02f0*/ @!P0 BRA 0x3f0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0300*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0310*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fca000f8e00ff */
/*0320*/ ISETP.GT.U32.AND P0, PT, R8, R15, PT ; /* 0x0000000f0800720c */
/* 0x000fc80003f04070 */
/*0330*/ ISETP.GT.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f04100 */
/*0340*/ @P0 IMAD R4, R8.reuse, 0x4, R0 ; /* 0x0000000408040824 */
/* 0x040fe200078e0200 */
/*0350*/ @P0 LDS R6, [R15.X4] ; /* 0x000000000f060984 */
/* 0x000fe20000004800 */
/*0360*/ SHF.R.U64 R8, R8, 0x1, R9.reuse ; /* 0x0000000108087819 */
/* 0x100fe40000001209 */
/*0370*/ SHF.R.U32.HI R9, RZ, 0x1, R9 ; /* 0x00000001ff097819 */
/* 0x000fe20000011609 */
/*0380*/ @P0 LDS R7, [R4] ; /* 0x0000000004070984 */
/* 0x000e240000000800 */
/*0390*/ @P0 FADD R6, R6, R7 ; /* 0x0000000706060221 */
/* 0x001fca0000000000 */
/*03a0*/ @P0 STS [R15.X4], R6 ; /* 0x000000060f000388 */
/* 0x0001e80000004800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03c0*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05070 */
/*03d0*/ ISETP.NE.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f05300 */
/*03e0*/ @P0 BRA 0x320 ; /* 0xffffff3000000947 */
/* 0x001fea000383ffff */
/*03f0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0400*/ LDS R0, [RZ] ; /* 0x00000000ff007984 */
/* 0x000e240000000800 */
/*0410*/ IADD3 R4, R0, -0xd000000, RZ ; /* 0xf300000000047810 */
/* 0x001fe20007ffe0ff */
/*0420*/ MUFU.RSQ R7, R0 ; /* 0x0000000000077308 */
/* 0x0000660000001400 */
/*0430*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0440*/ @!P0 BRA 0x490 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0450*/ MOV R6, 0x470 ; /* 0x0000047000067802 */
/* 0x003fe40000000f00 */
/*0460*/ CALL.REL.NOINC 0x540 ; /* 0x000000d000007944 */
/* 0x000fea0003c00000 */
/*0470*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0004 */
/*0480*/ BRA 0x4d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0490*/ FMUL.FTZ R9, R0, R7 ; /* 0x0000000700097220 */
/* 0x003fe40000410000 */
/*04a0*/ FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007077820 */
/* 0x000fe40000410000 */
/*04b0*/ FFMA R0, -R9, R9, R0 ; /* 0x0000000909007223 */
/* 0x000fc80000000100 */
/*04c0*/ FFMA R7, R0, R7, R9 ; /* 0x0000000700077223 */
/* 0x000fe40000000009 */
/*04d0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fca0000000f00 */
/*04e0*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x1a0], R2 ; /* 0x0000680005027a25 */
/* 0x000fc800078e0002 */
/*04f0*/ IMAD R5, R5, c[0x0][0x1a4], R3 ; /* 0x0000690005057a24 */
/* 0x000fe200078e0203 */
/*0500*/ LEA R4, P0, R2, c[0x0][0x198], 0x2 ; /* 0x0000660002047a11 */
/* 0x000fc800078010ff */
/*0510*/ LEA.HI.X R5, R2, c[0x0][0x19c], R5, 0x2, P0 ; /* 0x0000670002057a11 */
/* 0x000fca00000f1405 */
/*0520*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101906 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00ff7812 */
/* 0x000fda000780c0ff */
/*0550*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0000 */
/*0560*/ @!P0 BRA 0x680 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0570*/ FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f1e000 */
/*0580*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff048424 */
/* 0x000fe200078e00ff */
/*0590*/ @!P0 BRA 0x680 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1c200 */
/*05b0*/ @P0 FADD.FTZ R4, R0, 1 ; /* 0x3f80000000040421 */
/* 0x000fe20000010000 */
/*05c0*/ @P0 BRA 0x680 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*05d0*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1d200 */
/*05e0*/ @!P0 MOV R4, R0 ; /* 0x0000000000048202 */
/* 0x000fe20000000f00 */
/*05f0*/ @!P0 BRA 0x680 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0600*/ FFMA R0, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000007823 */
/* 0x000fc800000000ff */
/*0610*/ MUFU.RSQ R7, R0 ; /* 0x0000000000077308 */
/* 0x000e240000001400 */
/*0620*/ FMUL.FTZ R9, R0, R7 ; /* 0x0000000700097220 */
/* 0x001fe40000410000 */
/*0630*/ FMUL.FTZ R7, R7, 0.5 ; /* 0x3f00000007077820 */
/* 0x000fe40000410000 */
/*0640*/ FADD.FTZ R4, -R9, -RZ ; /* 0x800000ff09047221 */
/* 0x000fc80000010100 */
/*0650*/ FFMA R4, R9, R4, R0 ; /* 0x0000000409047223 */
/* 0x000fc80000000000 */
/*0660*/ FFMA R4, R4, R7, R9 ; /* 0x0000000704047223 */
/* 0x000fc80000000009 */
/*0670*/ FMUL.FTZ R4, R4, 2.3283064365386962891e-10 ; /* 0x2f80000004047820 */
/* 0x000fe40000410000 */
/*0680*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0690*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff96006007950 */
/* 0x000fea0003c3ffff */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16euclidean_kernelPKfmmS0_mmmPfmf
.globl _Z16euclidean_kernelPKfmmS0_mmmPfmf
.p2align 8
.type _Z16euclidean_kernelPKfmmS0_mmmPfmf,@function
_Z16euclidean_kernelPKfmmS0_mmmPfmf:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x28
s_mov_b32 s8, s15
s_mov_b32 s15, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mov_b32 s9, s15
s_waitcnt lgkmcnt(0)
v_cmp_ge_u64_e64 s2, s[14:15], s[2:3]
v_cmp_ge_u64_e64 s3, s[8:9], s[4:5]
s_or_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_12
s_load_b64 s[10:11], s[0:1], 0x30
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 2, v0
s_mov_b32 s3, exec_lo
ds_store_b32 v4, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[10:11], v[0:1]
s_cbranch_execz .LBB0_5
s_clause 0x2
s_load_b128 s[16:19], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x5c
ds_load_b32 v5, v4
v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v6, 2, v0
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s14, s19
s_mul_hi_u32 s19, s14, s18
s_mul_i32 s12, s14, s18
s_add_i32 s13, s19, s13
s_mul_i32 s20, s8, s7
s_lshl_b64 s[12:13], s[12:13], 2
s_mul_hi_u32 s19, s8, s6
s_mul_i32 s18, s8, s6
s_add_u32 s6, s16, s12
s_addc_u32 s7, s17, s13
s_add_i32 s19, s19, s20
s_mov_b32 s16, s9
s_lshl_b64 s[12:13], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s4, s4, s12
s_addc_u32 s5, s5, s13
s_and_b32 s12, s2, 0xffff
s_mov_b32 s13, s9
s_lshl_b32 s17, s12, 2
.p2align 6
.LBB0_3:
v_add_co_u32 v8, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s12
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[10:11], off
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v6, s2, v6, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s2, s13, v7, s2
v_cmp_le_u64_e32 vcc_lo, s[10:11], v[2:3]
s_or_b32 s16, vcc_lo, s16
s_waitcnt vmcnt(0)
v_sub_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, v8, v8
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s16
ds_store_b32 v4, v5
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s2, s[0:1], 0x5c
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s3, s2, 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_10
s_and_b32 s2, 0xffff, s2
s_mov_b32 s3, 0
s_lshr_b32 s2, s2, 1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_lt_u64_e64 s4, s[2:3], 2
s_lshr_b64 s[2:3], s[2:3], 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_10
.LBB0_8:
s_mov_b32 s4, exec_lo
v_cmpx_gt_u64_e64 s[2:3], v[0:1]
s_cbranch_execz .LBB0_7
v_add_lshl_u32 v2, v0, s2, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v4, v2
s_branch .LBB0_7
.LBB0_10:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v0, 0
s_load_b128 s[4:7], s[0:1], 0x38
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s8, s7
s_mul_hi_u32 s2, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_add_i32 s1, s2, s1
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
v_fma_f32 v5, -v3, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v2, v1
v_cmp_ge_f32_e64 s0, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v3, s0
v_cmp_lt_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v2, v2, v4, s0
s_mul_i32 s0, s8, s6
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_lshl_b64 s[0:1], s[14:15], 2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
global_store_b32 v0, v1, s[0:1]
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16euclidean_kernelPKfmmS0_mmmPfmf
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16euclidean_kernelPKfmmS0_mmmPfmf, .Lfunc_end0-_Z16euclidean_kernelPKfmmS0_mmmPfmf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 8
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16euclidean_kernelPKfmmS0_mmmPfmf
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z16euclidean_kernelPKfmmS0_mmmPfmf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009f1ec_00000000-6_euclidean_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf
.type _Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf, @function
_Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 4(%rsp)
movq 248(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z16euclidean_kernelPKfmmS0_mmmPfmf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf, .-_Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf
.globl _Z16euclidean_kernelPKfmmS0_mmmPfmf
.type _Z16euclidean_kernelPKfmmS0_mmmPfmf, @function
_Z16euclidean_kernelPKfmmS0_mmmPfmf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z49__device_stub__Z16euclidean_kernelPKfmmS0_mmmPfmfPKfmmS0_mmmPfmf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16euclidean_kernelPKfmmS0_mmmPfmf, .-_Z16euclidean_kernelPKfmmS0_mmmPfmf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16euclidean_kernelPKfmmS0_mmmPfmf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16euclidean_kernelPKfmmS0_mmmPfmf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "euclidean_kernel.hip"
.globl _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf # -- Begin function _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf
.p2align 4, 0x90
.type _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf,@function
_Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf: # @_Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z16euclidean_kernelPKfmmS0_mmmPfmf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf, .Lfunc_end0-_Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16euclidean_kernelPKfmmS0_mmmPfmf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16euclidean_kernelPKfmmS0_mmmPfmf,@object # @_Z16euclidean_kernelPKfmmS0_mmmPfmf
.section .rodata,"a",@progbits
.globl _Z16euclidean_kernelPKfmmS0_mmmPfmf
.p2align 3, 0x0
_Z16euclidean_kernelPKfmmS0_mmmPfmf:
.quad _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf
.size _Z16euclidean_kernelPKfmmS0_mmmPfmf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16euclidean_kernelPKfmmS0_mmmPfmf"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__euclidean_kernelPKfmmS0_mmmPfmf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16euclidean_kernelPKfmmS0_mmmPfmf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cmath>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
static void HandleError(cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
#define HANDLE_NULL(a) \
{ \
if (a == NULL) { \
printf("Host memory failed in %s at line %d\n", __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void saxpy(int *x, int *y, int alpha, size_t N) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N) {
y[i] = alpha * y[i] + x[i];
}
}
void initialize_list(int *x, int N) {
for (int i = 0; i < N; i++) {
x[i] = rand();
}
}
int main(void) {
int N = std::pow(10, 7);
int alpha = 2;
int *x, *y;
x = (int *)(malloc(N * sizeof(int)));
y = (int *)(malloc(N * sizeof(int)));
srand(time(NULL));
initialize_list(x, N);
initialize_list(y, N);
int *d_x, *d_y;
HANDLE_ERROR( cudaMalloc((void **)&d_x, N * sizeof(int)) );
cudaMalloc((void **)&d_y, N * sizeof(int));
cudaMemcpy(d_x, x, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, N * sizeof(int), cudaMemcpyHostToDevice);
saxpy<<<(N + 255) / 256, 256>>>(d_x, d_y, alpha, N);
int *c;
c = (int *)(malloc(N * sizeof(int)));
cudaMemcpy(c, d_y, N * sizeof(int), cudaMemcpyDeviceToHost);
printf("[");
for (int i = 0; i < N; i++) {
if (i < 10) {
printf("%d ", c[i]);
}
if (y[i] * alpha + x[i] != c[i]) {
printf("YOU SCREWED UP!");
}
}
printf(" ... ]");
cudaFree(d_x);
return 0;
} | code for sm_80
Function : _Z5saxpyPiS_im
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x2, R3 ; /* 0x0000000200007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x168], RZ ; /* 0x00005a0004027a10 */
/* 0x040fe40007f1e0ff */
/*00c0*/ IADD3 R4, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fe40007f3e0ff */
/*00d0*/ IADD3.X R3, R0.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000037a10 */
/* 0x040fe400007fe4ff */
/*00e0*/ IADD3.X R5, R0, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590000057a10 */
/* 0x000fc60000ffe4ff */
/*00f0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0110*/ IMAD R7, R0, c[0x0][0x170], R5 ; /* 0x00005c0000077a24 */
/* 0x004fca00078e0205 */
/*0120*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
static void HandleError(cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
#define HANDLE_NULL(a) \
{ \
if (a == NULL) { \
printf("Host memory failed in %s at line %d\n", __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void saxpy(int *x, int *y, int alpha, size_t N) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N) {
y[i] = alpha * y[i] + x[i];
}
}
void initialize_list(int *x, int N) {
for (int i = 0; i < N; i++) {
x[i] = rand();
}
}
int main(void) {
int N = std::pow(10, 7);
int alpha = 2;
int *x, *y;
x = (int *)(malloc(N * sizeof(int)));
y = (int *)(malloc(N * sizeof(int)));
srand(time(NULL));
initialize_list(x, N);
initialize_list(y, N);
int *d_x, *d_y;
HANDLE_ERROR( cudaMalloc((void **)&d_x, N * sizeof(int)) );
cudaMalloc((void **)&d_y, N * sizeof(int));
cudaMemcpy(d_x, x, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, N * sizeof(int), cudaMemcpyHostToDevice);
saxpy<<<(N + 255) / 256, 256>>>(d_x, d_y, alpha, N);
int *c;
c = (int *)(malloc(N * sizeof(int)));
cudaMemcpy(c, d_y, N * sizeof(int), cudaMemcpyDeviceToHost);
printf("[");
for (int i = 0; i < N; i++) {
if (i < 10) {
printf("%d ", c[i]);
}
if (y[i] * alpha + x[i] != c[i]) {
printf("YOU SCREWED UP!");
}
}
printf(" ... ]");
cudaFree(d_x);
return 0;
} | .file "tmpxft_00089545_00000000-6_saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15initialize_listPii
.type _Z15initialize_listPii, @function
_Z15initialize_listPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z15initialize_listPii, .-_Z15initialize_listPii
.globl _Z28__device_stub__Z5saxpyPiS_imPiS_im
.type _Z28__device_stub__Z5saxpyPiS_imPiS_im, @function
_Z28__device_stub__Z5saxpyPiS_imPiS_im:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPiS_im(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z28__device_stub__Z5saxpyPiS_imPiS_im, .-_Z28__device_stub__Z5saxpyPiS_imPiS_im
.globl _Z5saxpyPiS_im
.type _Z5saxpyPiS_im, @function
_Z5saxpyPiS_im:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyPiS_imPiS_im
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z5saxpyPiS_im, .-_Z5saxpyPiS_im
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/adhithadias/matrix-multiply/main/cuda-mat-mul/saxpy.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.LC2:
.string "["
.LC3:
.string "%d "
.LC4:
.string "YOU SCREWED UP!"
.LC5:
.string " ... ]"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $10000000, %esi
movq %rbp, %rdi
call _Z15initialize_listPii
movl $10000000, %esi
movq %r12, %rdi
call _Z15initialize_listPii
movq %rsp, %rdi
movl $40000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
leaq 8(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000000, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $39063, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L21:
movl $40000000, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movl $40000000, %edx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC4(%rip), %r14
jmp .L27
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $48, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl $10000000, %ecx
movl $2, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z5saxpyPiS_imPiS_im
jmp .L21
.L36:
movl 0(%r13,%rbx,4), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%r12,%rbx,4), %edx
movl 0(%rbp,%rbx,4), %eax
leal (%rax,%rdx,2), %eax
cmpl 0(%r13,%rbx,4), %eax
jne .L23
addq $1, %rbx
jmp .L27
.L25:
addq $1, %rbx
cmpq $10000000, %rbx
je .L35
.L27:
cmpl $9, %ebx
jle .L36
movl (%r12,%rbx,4), %edx
movl 0(%rbp,%rbx,4), %eax
leal (%rax,%rdx,2), %eax
cmpl 0(%r13,%rbx,4), %eax
je .L25
.L23:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L35:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z5saxpyPiS_im"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPiS_im(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
static void HandleError(cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
#define HANDLE_NULL(a) \
{ \
if (a == NULL) { \
printf("Host memory failed in %s at line %d\n", __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void saxpy(int *x, int *y, int alpha, size_t N) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N) {
y[i] = alpha * y[i] + x[i];
}
}
void initialize_list(int *x, int N) {
for (int i = 0; i < N; i++) {
x[i] = rand();
}
}
int main(void) {
int N = std::pow(10, 7);
int alpha = 2;
int *x, *y;
x = (int *)(malloc(N * sizeof(int)));
y = (int *)(malloc(N * sizeof(int)));
srand(time(NULL));
initialize_list(x, N);
initialize_list(y, N);
int *d_x, *d_y;
HANDLE_ERROR( cudaMalloc((void **)&d_x, N * sizeof(int)) );
cudaMalloc((void **)&d_y, N * sizeof(int));
cudaMemcpy(d_x, x, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, N * sizeof(int), cudaMemcpyHostToDevice);
saxpy<<<(N + 255) / 256, 256>>>(d_x, d_y, alpha, N);
int *c;
c = (int *)(malloc(N * sizeof(int)));
cudaMemcpy(c, d_y, N * sizeof(int), cudaMemcpyDeviceToHost);
printf("[");
for (int i = 0; i < N; i++) {
if (i < 10) {
printf("%d ", c[i]);
}
if (y[i] * alpha + x[i] != c[i]) {
printf("YOU SCREWED UP!");
}
}
printf(" ... ]");
cudaFree(d_x);
return 0;
} | #include <hip/hip_runtime.h>
#include <cmath>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
static void HandleError(hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
#define HANDLE_NULL(a) \
{ \
if (a == NULL) { \
printf("Host memory failed in %s at line %d\n", __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void saxpy(int *x, int *y, int alpha, size_t N) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N) {
y[i] = alpha * y[i] + x[i];
}
}
void initialize_list(int *x, int N) {
for (int i = 0; i < N; i++) {
x[i] = rand();
}
}
int main(void) {
int N = std::pow(10, 7);
int alpha = 2;
int *x, *y;
x = (int *)(malloc(N * sizeof(int)));
y = (int *)(malloc(N * sizeof(int)));
srand(time(NULL));
initialize_list(x, N);
initialize_list(y, N);
int *d_x, *d_y;
HANDLE_ERROR( hipMalloc((void **)&d_x, N * sizeof(int)) );
hipMalloc((void **)&d_y, N * sizeof(int));
hipMemcpy(d_x, x, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, N * sizeof(int), hipMemcpyHostToDevice);
saxpy<<<(N + 255) / 256, 256>>>(d_x, d_y, alpha, N);
int *c;
c = (int *)(malloc(N * sizeof(int)));
hipMemcpy(c, d_y, N * sizeof(int), hipMemcpyDeviceToHost);
printf("[");
for (int i = 0; i < N; i++) {
if (i < 10) {
printf("%d ", c[i]);
}
if (y[i] * alpha + x[i] != c[i]) {
printf("YOU SCREWED UP!");
}
}
printf(" ... ]");
hipFree(d_x);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
static void HandleError(hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
#define HANDLE_NULL(a) \
{ \
if (a == NULL) { \
printf("Host memory failed in %s at line %d\n", __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void saxpy(int *x, int *y, int alpha, size_t N) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N) {
y[i] = alpha * y[i] + x[i];
}
}
void initialize_list(int *x, int N) {
for (int i = 0; i < N; i++) {
x[i] = rand();
}
}
int main(void) {
int N = std::pow(10, 7);
int alpha = 2;
int *x, *y;
x = (int *)(malloc(N * sizeof(int)));
y = (int *)(malloc(N * sizeof(int)));
srand(time(NULL));
initialize_list(x, N);
initialize_list(y, N);
int *d_x, *d_y;
HANDLE_ERROR( hipMalloc((void **)&d_x, N * sizeof(int)) );
hipMalloc((void **)&d_y, N * sizeof(int));
hipMemcpy(d_x, x, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, N * sizeof(int), hipMemcpyHostToDevice);
saxpy<<<(N + 255) / 256, 256>>>(d_x, d_y, alpha, N);
int *c;
c = (int *)(malloc(N * sizeof(int)));
hipMemcpy(c, d_y, N * sizeof(int), hipMemcpyDeviceToHost);
printf("[");
for (int i = 0; i < N; i++) {
if (i < 10) {
printf("%d ", c[i]);
}
if (y[i] * alpha + x[i] != c[i]) {
printf("YOU SCREWED UP!");
}
}
printf(" ... ]");
hipFree(d_x);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPiS_im
.globl _Z5saxpyPiS_im
.p2align 8
.type _Z5saxpyPiS_im,@function
_Z5saxpyPiS_im:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v6, s0, v[0:1]
global_store_b32 v[2:3], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPiS_im
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPiS_im, .Lfunc_end0-_Z5saxpyPiS_im
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPiS_im
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPiS_im.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
static void HandleError(hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
#define HANDLE_NULL(a) \
{ \
if (a == NULL) { \
printf("Host memory failed in %s at line %d\n", __FILE__, __LINE__); \
exit(EXIT_FAILURE); \
} \
}
__global__ void saxpy(int *x, int *y, int alpha, size_t N) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N) {
y[i] = alpha * y[i] + x[i];
}
}
void initialize_list(int *x, int N) {
for (int i = 0; i < N; i++) {
x[i] = rand();
}
}
int main(void) {
int N = std::pow(10, 7);
int alpha = 2;
int *x, *y;
x = (int *)(malloc(N * sizeof(int)));
y = (int *)(malloc(N * sizeof(int)));
srand(time(NULL));
initialize_list(x, N);
initialize_list(y, N);
int *d_x, *d_y;
HANDLE_ERROR( hipMalloc((void **)&d_x, N * sizeof(int)) );
hipMalloc((void **)&d_y, N * sizeof(int));
hipMemcpy(d_x, x, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, N * sizeof(int), hipMemcpyHostToDevice);
saxpy<<<(N + 255) / 256, 256>>>(d_x, d_y, alpha, N);
int *c;
c = (int *)(malloc(N * sizeof(int)));
hipMemcpy(c, d_y, N * sizeof(int), hipMemcpyDeviceToHost);
printf("[");
for (int i = 0; i < N; i++) {
if (i < 10) {
printf("%d ", c[i]);
}
if (y[i] * alpha + x[i] != c[i]) {
printf("YOU SCREWED UP!");
}
}
printf(" ... ]");
hipFree(d_x);
return 0;
} | .text
.file "saxpy.hip"
.globl _Z20__device_stub__saxpyPiS_im # -- Begin function _Z20__device_stub__saxpyPiS_im
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPiS_im,@function
_Z20__device_stub__saxpyPiS_im: # @_Z20__device_stub__saxpyPiS_im
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPiS_im, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPiS_im, .Lfunc_end0-_Z20__device_stub__saxpyPiS_im
.cfi_endproc
# -- End function
.globl _Z15initialize_listPii # -- Begin function _Z15initialize_listPii
.p2align 4, 0x90
.type _Z15initialize_listPii,@function
_Z15initialize_listPii: # @_Z15initialize_listPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z15initialize_listPii, .Lfunc_end1-_Z15initialize_listPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.lr.ph.preheader.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $10000000, %r15 # imm = 0x989680
jne .LBB2_1
# %bb.2: # %.lr.ph.i35.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i35
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $10000000, %r15 # imm = 0x989680
jne .LBB2_3
# %bb.4: # %_Z15initialize_listPii.exit39
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
testl %eax, %eax
jne .LBB2_14
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit
movq %rsp, %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq 8(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 38807(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $2, 20(%rsp)
movq $10000000, 72(%rsp) # imm = 0x989680
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5saxpyPiS_im, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r15
movq (%rsp), %rsi
movl $40000000, %edx # imm = 0x2625A00
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movl $91, %edi
callq putchar@PLT
xorl %r12d, %r12d
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_8 Depth=1
incq %r12
cmpq $10000000, %r12 # imm = 0x989680
je .LBB2_13
.LBB2_8: # =>This Inner Loop Header: Depth=1
cmpq $9, %r12
ja .LBB2_10
# %bb.9: # in Loop: Header=BB2_8 Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB2_10: # in Loop: Header=BB2_8 Depth=1
movl (%r14,%r12,4), %eax
addl %eax, %eax
addl (%rbx,%r12,4), %eax
cmpl (%r15,%r12,4), %eax
je .LBB2_12
# %bb.11: # in Loop: Header=BB2_8 Depth=1
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_12
.LBB2_13:
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_14:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $50, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPiS_im, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPiS_im,@object # @_Z5saxpyPiS_im
.section .rodata,"a",@progbits
.globl _Z5saxpyPiS_im
.p2align 3, 0x0
_Z5saxpyPiS_im:
.quad _Z20__device_stub__saxpyPiS_im
.size _Z5saxpyPiS_im, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/adhithadias/matrix-multiply/main/cuda-mat-mul/saxpy.hip"
.size .L.str, 113
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "YOU SCREWED UP!"
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " ... ]"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s in %s at line %d\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyPiS_im"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPiS_im
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPiS_im
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyPiS_im
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R4, R0.reuse, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x2, R3 ; /* 0x0000000200007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x168], RZ ; /* 0x00005a0004027a10 */
/* 0x040fe40007f1e0ff */
/*00c0*/ IADD3 R4, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fe40007f3e0ff */
/*00d0*/ IADD3.X R3, R0.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000037a10 */
/* 0x040fe400007fe4ff */
/*00e0*/ IADD3.X R5, R0, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590000057a10 */
/* 0x000fc60000ffe4ff */
/*00f0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0110*/ IMAD R7, R0, c[0x0][0x170], R5 ; /* 0x00005c0000077a24 */
/* 0x004fca00078e0205 */
/*0120*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPiS_im
.globl _Z5saxpyPiS_im
.p2align 8
.type _Z5saxpyPiS_im,@function
_Z5saxpyPiS_im:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v6, s0, v[0:1]
global_store_b32 v[2:3], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPiS_im
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPiS_im, .Lfunc_end0-_Z5saxpyPiS_im
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPiS_im
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPiS_im.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00089545_00000000-6_saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15initialize_listPii
.type _Z15initialize_listPii, @function
_Z15initialize_listPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z15initialize_listPii, .-_Z15initialize_listPii
.globl _Z28__device_stub__Z5saxpyPiS_imPiS_im
.type _Z28__device_stub__Z5saxpyPiS_imPiS_im, @function
_Z28__device_stub__Z5saxpyPiS_imPiS_im:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPiS_im(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z28__device_stub__Z5saxpyPiS_imPiS_im, .-_Z28__device_stub__Z5saxpyPiS_imPiS_im
.globl _Z5saxpyPiS_im
.type _Z5saxpyPiS_im, @function
_Z5saxpyPiS_im:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyPiS_imPiS_im
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z5saxpyPiS_im, .-_Z5saxpyPiS_im
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/adhithadias/matrix-multiply/main/cuda-mat-mul/saxpy.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.LC2:
.string "["
.LC3:
.string "%d "
.LC4:
.string "YOU SCREWED UP!"
.LC5:
.string " ... ]"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $40000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $40000000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $10000000, %esi
movq %rbp, %rdi
call _Z15initialize_listPii
movl $10000000, %esi
movq %r12, %rdi
call _Z15initialize_listPii
movq %rsp, %rdi
movl $40000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
leaq 8(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000000, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $39063, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L21:
movl $40000000, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movl $40000000, %edx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC4(%rip), %r14
jmp .L27
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $48, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl $10000000, %ecx
movl $2, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z5saxpyPiS_imPiS_im
jmp .L21
.L36:
movl 0(%r13,%rbx,4), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%r12,%rbx,4), %edx
movl 0(%rbp,%rbx,4), %eax
leal (%rax,%rdx,2), %eax
cmpl 0(%r13,%rbx,4), %eax
jne .L23
addq $1, %rbx
jmp .L27
.L25:
addq $1, %rbx
cmpq $10000000, %rbx
je .L35
.L27:
cmpl $9, %ebx
jle .L36
movl (%r12,%rbx,4), %edx
movl 0(%rbp,%rbx,4), %eax
leal (%rax,%rdx,2), %eax
cmpl 0(%r13,%rbx,4), %eax
je .L25
.L23:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L35:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z5saxpyPiS_im"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPiS_im(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy.hip"
.globl _Z20__device_stub__saxpyPiS_im # -- Begin function _Z20__device_stub__saxpyPiS_im
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPiS_im,@function
_Z20__device_stub__saxpyPiS_im: # @_Z20__device_stub__saxpyPiS_im
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPiS_im, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPiS_im, .Lfunc_end0-_Z20__device_stub__saxpyPiS_im
.cfi_endproc
# -- End function
.globl _Z15initialize_listPii # -- Begin function _Z15initialize_listPii
.p2align 4, 0x90
.type _Z15initialize_listPii,@function
_Z15initialize_listPii: # @_Z15initialize_listPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z15initialize_listPii, .Lfunc_end1-_Z15initialize_listPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.lr.ph.preheader.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %rbx
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $10000000, %r15 # imm = 0x989680
jne .LBB2_1
# %bb.2: # %.lr.ph.i35.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i35
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $10000000, %r15 # imm = 0x989680
jne .LBB2_3
# %bb.4: # %_Z15initialize_listPii.exit39
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
testl %eax, %eax
jne .LBB2_14
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit
movq %rsp, %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
movq 8(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 38807(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $2, 20(%rsp)
movq $10000000, 72(%rsp) # imm = 0x989680
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5saxpyPiS_im, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movl $40000000, %edi # imm = 0x2625A00
callq malloc
movq %rax, %r15
movq (%rsp), %rsi
movl $40000000, %edx # imm = 0x2625A00
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movl $91, %edi
callq putchar@PLT
xorl %r12d, %r12d
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_8 Depth=1
incq %r12
cmpq $10000000, %r12 # imm = 0x989680
je .LBB2_13
.LBB2_8: # =>This Inner Loop Header: Depth=1
cmpq $9, %r12
ja .LBB2_10
# %bb.9: # in Loop: Header=BB2_8 Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB2_10: # in Loop: Header=BB2_8 Depth=1
movl (%r14,%r12,4), %eax
addl %eax, %eax
addl (%rbx,%r12,4), %eax
cmpl (%r15,%r12,4), %eax
je .LBB2_12
# %bb.11: # in Loop: Header=BB2_8 Depth=1
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_12
.LBB2_13:
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_14:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $50, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPiS_im, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPiS_im,@object # @_Z5saxpyPiS_im
.section .rodata,"a",@progbits
.globl _Z5saxpyPiS_im
.p2align 3, 0x0
_Z5saxpyPiS_im:
.quad _Z20__device_stub__saxpyPiS_im
.size _Z5saxpyPiS_im, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/adhithadias/matrix-multiply/main/cuda-mat-mul/saxpy.hip"
.size .L.str, 113
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "YOU SCREWED UP!"
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " ... ]"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s in %s at line %d\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyPiS_im"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPiS_im
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPiS_im
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <limits.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(cudaError_t ret, const char *file, int line) {
if (ret != cudaSuccess) {
fprintf(stderr, "CudaErr: %s (%s:%d)\n", cudaGetErrorString(ret), file, line);
exit(1);
}
}
__constant__ int width_d;
__constant__ int height_d;
__constant__ int order_d;
__global__ void gaussian_calc_kernel(unsigned char *image_mat, unsigned char *result_mat, float *kernel)
{
float val = 0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int j = blockIdx.x * blockDim.x + tx; //col
int i = blockIdx.y * blockDim.y + ty; //row
if (i >= height_d || j >= width_d) {
return;
}
int center = (order_d - 1) / 2;
for (int x = 0; x < order_d; x++) {
for (int y = 0; y < order_d; y++) {
// Min accounts for right and bottom edges
// Max accounts for left and top edges
int mat_x = max(0, min(i + x - center, height_d - 1));
int mat_y = max(0, min(j + y - center, width_d - 1));
val += image_mat[mat_x * width_d + mat_y] * kernel[x * order_d + y];
}
}
result_mat[i * width_d + j] = (unsigned char) val;
}
void gaussian_calc(unsigned char *image_mat, unsigned char *result_mat, float *kernel, int width, int height, int order)
{
/* Allocate device memory for all matrices */
float *kernel_d;
unsigned char *image_mat_d, *result_mat_d;
cuda_check(cudaMalloc(&kernel_d, order * order * sizeof(float)));
cuda_check(cudaMalloc(&image_mat_d, width * height * sizeof(unsigned char)));
cuda_check(cudaMalloc(&result_mat_d, width * height * sizeof(unsigned char)));
/* Copy kernel and image_mat to device */
cuda_check(cudaMemcpy(kernel_d, kernel, order * order * sizeof(float), cudaMemcpyHostToDevice));
cuda_check(cudaMemcpy(image_mat_d, image_mat, width * height * sizeof(unsigned char), cudaMemcpyHostToDevice));
cuda_check(cudaMemcpyToSymbol(width_d, &width, sizeof(int)));
cuda_check(cudaMemcpyToSymbol(height_d, &height, sizeof(int)));
cuda_check(cudaMemcpyToSymbol(order_d, &order, sizeof(int)));
/* Invoke kernel function */
dim3 block_dim(779, 1);
dim3 grid_dim(DIV_ROUND_UP(width, block_dim.x), DIV_ROUND_UP(height, block_dim.y));
gaussian_calc_kernel<<<grid_dim, block_dim>>>(image_mat_d, result_mat_d, kernel_d);
/* Copy result back to host */
cuda_check(cudaMemcpy(result_mat, result_mat_d, width * height * sizeof(unsigned char), cudaMemcpyDeviceToHost));
/* Free device memory */
cuda_check(cudaFree(kernel_d));
cuda_check(cudaFree(image_mat_d));
cuda_check(cudaFree(result_mat_d));
}
void write_gaussian(char *filename, unsigned char *picture, int width, int height)
{
FILE *fp;
/* Open file */
fp = fopen(filename, "wb");
if (!fp) {
fprintf(stderr, "Error: cannot open file %s", filename);
exit(1);
}
/* Put structural information */
fprintf(fp, "P5\n%d %d\n255\n", width, height);
/* Output grayscale pixels */
fwrite(picture, sizeof(unsigned char), width * height, fp);
// free(pixels);
fclose(fp);
}
int main(int argc, char *argv[])
{
float sigma, order;
char *output_filename;
int width, height;
FILE *input_file;
/* Command line arguments */
if (argc < 4) {
fprintf(stderr, "Usage: %s <input_pgm> <output_pgm> <sigma>\n",
argv[0]);
exit(1);
}
input_file = fopen(argv[1], "rb");
if (!input_file) {
fprintf(stderr, "Error: cannot open file %s", argv[1]);
exit(1);
}
output_filename = argv[2];
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
if (fscanf(input_file, "%d %d\n", &width, &height) != 2) {
exit(1);
}
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
sigma = atof(argv[3]);
if (sigma <= 0) {
fprintf(stderr, "Error: invalid sigma value");
exit(1);
}
order = ceil(6 * sigma);
if ((int)order % 2 == 0) {
order++;
}
if (order > width || order > height) {
fprintf(stderr, "Error: sigma value too big for image size");
exit(1);
}
float *kernel;
unsigned char *image_mat, *result_mat;
kernel = (float*)aligned_alloc(64, (int) order * (int) order * sizeof(float));
image_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
result_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
if (fread(image_mat, sizeof(unsigned char), height * width, input_file) != (size_t)(height * width)) {
exit(1);
}
fclose(input_file);
float sum = 0;
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] = exp(-(pow(i - floor(order/2), 2) + pow(j - floor(order/2), 2))/(2 * sigma * sigma));
sum += kernel[i * (int) order + j];
}
}
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] /= sum;
}
}
gaussian_calc(image_mat, result_mat, kernel, width, height,(int) order);
// /* Save output image */
write_gaussian(output_filename, result_mat, width, height);
free(kernel);
free(image_mat);
free(result_mat);
return 0;
} | code for sm_80
Function : _Z20gaussian_calc_kernelPhS_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x3][0x0], PT ; /* 0x00c0000000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R13, R13, c[0x0][0x4], R2 ; /* 0x000001000d0d7a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R13, c[0x3][0x4], P0 ; /* 0x00c001000d007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x3][0x8] ; /* 0x00c00200ff0c7624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc600078e00ff */
/*00d0*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x7d0 ; /* 0x000006e000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R23, R12.reuse, -0x1, RZ ; /* 0xffffffff0c177810 */
/* 0x040fe20007ffe0ff */
/*0100*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0110*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fe200078ec0ff */
/*0120*/ ULDC.64 UR6, c[0x3][0x0] ; /* 0x00c0000000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ LEA.HI R2, R23, R23, RZ, 0x1 ; /* 0x0000001717027211 */
/* 0x000fe200078f08ff */
/*0140*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R15, -R12, c[0x3][0x8], RZ ; /* 0x00c002000c0f7a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0170*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011402 */
/*0180*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe4000fffe13f */
/*0190*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fc4000fffe13f */
/*01a0*/ IMAD.IADD R17, R13, 0x1, -R2.reuse ; /* 0x000000010d117824 */
/* 0x100fe400078e0a02 */
/*01b0*/ IMAD.IADD R16, R0, 0x1, -R2 ; /* 0x0000000100107824 */
/* 0x000fe400078e0a02 */
/*01c0*/ ISETP.GE.U32.AND P2, PT, R23, 0x3, PT ; /* 0x000000031700780c */
/* 0x000fe20003f46070 */
/*01d0*/ IMAD.IADD R2, R17, 0x1, R14.reuse ; /* 0x0000000111027824 */
/* 0x100fe200078e020e */
/*01e0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*01f0*/ IMAD.MOV.U32 R19, RZ, RZ, R14 ; /* 0x000000ffff137224 */
/* 0x000fe200078e000e */
/*0200*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0220*/ IMNMX R2, R2, UR4, PT ; /* 0x0000000402027c17 */
/* 0x000fe4000b800200 */
/*0230*/ ISETP.GE.AND P1, PT, R14, c[0x3][0x8], PT ; /* 0x00c002000e007a0c */
/* 0x000fc40003f26270 */
/*0240*/ IMNMX R20, RZ, R2, !PT ; /* 0x00000002ff147217 */
/* 0x000fc60007800200 */
/*0250*/ @!P2 BRA 0x570 ; /* 0x000003100000a947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R22, RZ, RZ, R15 ; /* 0x000000ffff167224 */
/* 0x000fe400078e000f */
/*0280*/ IMAD.IADD R2, R16, 0x1, R21 ; /* 0x0000000110027824 */
/* 0x000fca00078e0215 */
/*0290*/ IMNMX R3, R2.reuse, UR5, PT ; /* 0x0000000502037c17 */
/* 0x040fe4000b800200 */
/*02a0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*02b0*/ IADD3 R5, R2, 0x2, RZ ; /* 0x0000000202057810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ IMNMX R3, RZ, R3, !PT ; /* 0x00000003ff037217 */
/* 0x000fe40007800200 */
/*02d0*/ IMNMX R4, R4, UR5, PT ; /* 0x0000000504047c17 */
/* 0x000fe4000b800200 */
/*02e0*/ IADD3 R6, R2, 0x3, RZ ; /* 0x0000000302067810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD R3, R20, c[0x3][0x0], R3 ; /* 0x00c0000014037a24 */
/* 0x000fe200078e0203 */
/*0300*/ IMNMX R2, R5, UR5, PT ; /* 0x0000000505027c17 */
/* 0x000fc4000b800200 */
/*0310*/ IMNMX R5, RZ, R4, !PT ; /* 0x00000004ff057217 */
/* 0x000fe40007800200 */
/*0320*/ IMNMX R6, R6, UR5, PT ; /* 0x0000000506067c17 */
/* 0x000fe4000b800200 */
/*0330*/ IMNMX R7, RZ, R2, !PT ; /* 0x00000002ff077217 */
/* 0x000fe20007800200 */
/*0340*/ IMAD R5, R20.reuse, c[0x3][0x0], R5 ; /* 0x00c0000014057a24 */
/* 0x040fe200078e0205 */
/*0350*/ IADD3 R8, P2, R3.reuse, c[0x0][0x160], RZ ; /* 0x0000580003087a10 */
/* 0x040fe40007f5e0ff */
/*0360*/ IMNMX R11, RZ, R6, !PT ; /* 0x00000006ff0b7217 */
/* 0x000fe20007800200 */
/*0370*/ IMAD R7, R20, c[0x3][0x0], R7 ; /* 0x00c0000014077a24 */
/* 0x000fe200078e0207 */
/*0380*/ LEA.HI.X.SX32 R9, R3, c[0x0][0x164], 0x1, P2 ; /* 0x0000590003097a11 */
/* 0x000fc400010f0eff */
/*0390*/ IADD3 R2, P3, R5, c[0x0][0x160], RZ ; /* 0x0000580005027a10 */
/* 0x000fe20007f7e0ff */
/*03a0*/ IMAD R11, R20, c[0x3][0x0], R11 ; /* 0x00c00000140b7a24 */
/* 0x000fe200078e020b */
/*03b0*/ IADD3 R4, P2, R7, c[0x0][0x160], RZ ; /* 0x0000580007047a10 */
/* 0x000fe20007f5e0ff */
/*03c0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x0000a2000c1e1100 */
/*03d0*/ LEA.HI.X.SX32 R3, R5, c[0x0][0x164], 0x1, P3 ; /* 0x0000590005037a11 */
/* 0x000fe400018f0eff */
/*03e0*/ IADD3 R6, P3, R11, c[0x0][0x160], RZ ; /* 0x000058000b067a10 */
/* 0x000fe40007f7e0ff */
/*03f0*/ LEA.HI.X.SX32 R5, R7, c[0x0][0x164], 0x1, P2 ; /* 0x0000590007057a11 */
/* 0x000fe200010f0eff */
/*0400*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x0004e2000c1e1100 */
/*0410*/ IMAD R10, R19, c[0x3][0x8], R21 ; /* 0x00c00200130a7a24 */
/* 0x000fe200078e0215 */
/*0420*/ LEA.HI.X.SX32 R7, R11, c[0x0][0x164], 0x1, P3 ; /* 0x000059000b077a11 */
/* 0x000fe200018f0eff */
/*0430*/ IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff197424 */
/* 0x000fe200078e00ff */
/*0440*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000f26000c1e1100 */
/*0450*/ IMAD.WIDE R10, R10, R25, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fe200078e0219 */
/*0460*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000f68000c1e1100 */
/*0470*/ LDG.E R24, [R10.64] ; /* 0x000000080a187981 */
/* 0x000f68000c1e1900 */
/*0480*/ LDG.E R9, [R10.64+0x4] ; /* 0x000004080a097981 */
/* 0x001f68000c1e1900 */
/*0490*/ LDG.E R25, [R10.64+0x8] ; /* 0x000008080a197981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E R27, [R10.64+0xc] ; /* 0x00000c080a1b7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IADD3 R22, R22, -0x4, RZ ; /* 0xfffffffc16167810 */
/* 0x000fc80007ffe0ff */
/*04c0*/ ISETP.NE.AND P2, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f45270 */
/*04d0*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ I2F.U16 R3, R8 ; /* 0x0000000800037306 */
/* 0x004f700000101000 */
/*04f0*/ I2F.U16 R2, R2 ; /* 0x0000000200027306 */
/* 0x008e300000101000 */
/*0500*/ I2F.U16 R26, R4 ; /* 0x00000004001a7306 */
/* 0x010e620000101000 */
/*0510*/ FFMA R3, R3, R24, R18 ; /* 0x0000001803037223 */
/* 0x020fce0000000012 */
/*0520*/ I2F.U16 R28, R6 ; /* 0x00000006001c7306 */
/* 0x000ea20000101000 */
/*0530*/ FFMA R3, R2, R9, R3 ; /* 0x0000000902037223 */
/* 0x001fc80000000003 */
/*0540*/ FFMA R3, R26, R25, R3 ; /* 0x000000191a037223 */
/* 0x002fc80000000003 */
/*0550*/ FFMA R18, R28, R27, R3 ; /* 0x0000001b1c127223 */
/* 0x004fe20000000003 */
/*0560*/ @P2 BRA 0x280 ; /* 0xfffffd1000002947 */
/* 0x000fea000383ffff */
/*0570*/ @!P0 BRA 0x7c0 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0580*/ IMAD.IADD R8, R16, 0x1, R21 ; /* 0x0000000110087824 */
/* 0x000fca00078e0215 */
/*0590*/ IMNMX R2, R8, UR5, PT ; /* 0x0000000508027c17 */
/* 0x000fc8000b800200 */
/*05a0*/ IMNMX R3, RZ, R2, !PT ; /* 0x00000002ff037217 */
/* 0x000fca0007800200 */
/*05b0*/ IMAD R3, R20, c[0x3][0x0], R3 ; /* 0x00c0000014037a24 */
/* 0x000fca00078e0203 */
/*05c0*/ IADD3 R4, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fc80007f1e0ff */
/*05d0*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003057a11 */
/* 0x000fca00000f0eff */
/*05e0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea2000c1e1100 */
/*05f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0600*/ IMAD R2, R19, c[0x3][0x8], R21 ; /* 0x00c0020013027a24 */
/* 0x000fc800078e0215 */
/*0610*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0620*/ LDG.E R6, [R2.64] ; /* 0x0000000802067981 */
/* 0x000ee2000c1e1900 */
/*0630*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe20003f05270 */
/*0640*/ I2F.U16 R7, R4 ; /* 0x0000000400077306 */
/* 0x004ee40000101000 */
/*0650*/ FFMA R18, R7, R6, R18 ; /* 0x0000000607127223 */
/* 0x008fd40000000012 */
/*0660*/ @!P0 BRA 0x7c0 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0670*/ ISETP.NE.AND P0, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe40003f05270 */
/*0680*/ IADD3 R4, R8, 0x1, RZ ; /* 0x0000000108047810 */
/* 0x000fc80007ffe0ff */
/*0690*/ IMNMX R4, R4, UR5, PT ; /* 0x0000000504047c17 */
/* 0x000fc8000b800200 */
/*06a0*/ IMNMX R5, RZ, R4, !PT ; /* 0x00000004ff057217 */
/* 0x000fc60007800200 */
/*06b0*/ @P0 IADD3 R6, R8, 0x2, RZ ; /* 0x0000000208060810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ @P0 LDG.E R10, [R2.64+0x8] ; /* 0x00000808020a0981 */
/* 0x000ea2000c1e1900 */
/*06d0*/ IMAD R5, R20, c[0x3][0x0], R5 ; /* 0x00c0000014057a24 */
/* 0x000fe400078e0205 */
/*06e0*/ @P0 IMNMX R6, R6, UR5, PT ; /* 0x0000000506060c17 */
/* 0x000fe2000b800200 */
/*06f0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040802087981 */
/* 0x000ee4000c1e1900 */
/*0700*/ IADD3 R4, P2, R5.reuse, c[0x0][0x160], RZ ; /* 0x0000580005047a10 */
/* 0x040fe40007f5e0ff */
/*0710*/ @P0 IMNMX R7, RZ, R6, !PT ; /* 0x00000006ff070217 */
/* 0x000fe40007800200 */
/*0720*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x164], 0x1, P2 ; /* 0x0000590005057a11 */
/* 0x000fc600010f0eff */
/*0730*/ @P0 IMAD R7, R20, c[0x3][0x0], R7 ; /* 0x00c0000014070a24 */
/* 0x000fe400078e0207 */
/*0740*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000f26000c1e1100 */
/*0750*/ @P0 IADD3 R6, P2, R7, c[0x0][0x160], RZ ; /* 0x0000580007060a10 */
/* 0x000fc80007f5e0ff */
/*0760*/ @P0 LEA.HI.X.SX32 R7, R7, c[0x0][0x164], 0x1, P2 ; /* 0x0000590007070a11 */
/* 0x000fca00010f0eff */
/*0770*/ @P0 LDG.E.U8 R6, [R6.64] ; /* 0x0000000806060981 */
/* 0x000f62000c1e1100 */
/*0780*/ I2F.U16 R9, R4 ; /* 0x0000000400097306 */
/* 0x010ef00000101000 */
/*0790*/ @P0 I2F.U16 R11, R6 ; /* 0x00000006000b0306 */
/* 0x020ea20000101000 */
/*07a0*/ FFMA R18, R9, R8, R18 ; /* 0x0000000809127223 */
/* 0x008fc80000000012 */
/*07b0*/ @P0 FFMA R18, R11, R10, R18 ; /* 0x0000000a0b120223 */
/* 0x004fc60000000012 */
/*07c0*/ @!P1 BRA 0x1c0 ; /* 0xfffff9f000009947 */
/* 0x000fea000383ffff */
/*07d0*/ F2I.U32.TRUNC.NTZ R5, R18 ; /* 0x0000001200057305 */
/* 0x000e22000020f000 */
/*07e0*/ IMAD R0, R13, c[0x3][0x0], R0 ; /* 0x00c000000d007a24 */
/* 0x000fca00078e0200 */
/*07f0*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc80007f1e0ff */
/*0800*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f0eff */
/*0810*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101108 */
/*0820*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0830*/ BRA 0x830; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <limits.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(cudaError_t ret, const char *file, int line) {
if (ret != cudaSuccess) {
fprintf(stderr, "CudaErr: %s (%s:%d)\n", cudaGetErrorString(ret), file, line);
exit(1);
}
}
__constant__ int width_d;
__constant__ int height_d;
__constant__ int order_d;
__global__ void gaussian_calc_kernel(unsigned char *image_mat, unsigned char *result_mat, float *kernel)
{
float val = 0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int j = blockIdx.x * blockDim.x + tx; //col
int i = blockIdx.y * blockDim.y + ty; //row
if (i >= height_d || j >= width_d) {
return;
}
int center = (order_d - 1) / 2;
for (int x = 0; x < order_d; x++) {
for (int y = 0; y < order_d; y++) {
// Min accounts for right and bottom edges
// Max accounts for left and top edges
int mat_x = max(0, min(i + x - center, height_d - 1));
int mat_y = max(0, min(j + y - center, width_d - 1));
val += image_mat[mat_x * width_d + mat_y] * kernel[x * order_d + y];
}
}
result_mat[i * width_d + j] = (unsigned char) val;
}
void gaussian_calc(unsigned char *image_mat, unsigned char *result_mat, float *kernel, int width, int height, int order)
{
/* Allocate device memory for all matrices */
float *kernel_d;
unsigned char *image_mat_d, *result_mat_d;
cuda_check(cudaMalloc(&kernel_d, order * order * sizeof(float)));
cuda_check(cudaMalloc(&image_mat_d, width * height * sizeof(unsigned char)));
cuda_check(cudaMalloc(&result_mat_d, width * height * sizeof(unsigned char)));
/* Copy kernel and image_mat to device */
cuda_check(cudaMemcpy(kernel_d, kernel, order * order * sizeof(float), cudaMemcpyHostToDevice));
cuda_check(cudaMemcpy(image_mat_d, image_mat, width * height * sizeof(unsigned char), cudaMemcpyHostToDevice));
cuda_check(cudaMemcpyToSymbol(width_d, &width, sizeof(int)));
cuda_check(cudaMemcpyToSymbol(height_d, &height, sizeof(int)));
cuda_check(cudaMemcpyToSymbol(order_d, &order, sizeof(int)));
/* Invoke kernel function */
dim3 block_dim(779, 1);
dim3 grid_dim(DIV_ROUND_UP(width, block_dim.x), DIV_ROUND_UP(height, block_dim.y));
gaussian_calc_kernel<<<grid_dim, block_dim>>>(image_mat_d, result_mat_d, kernel_d);
/* Copy result back to host */
cuda_check(cudaMemcpy(result_mat, result_mat_d, width * height * sizeof(unsigned char), cudaMemcpyDeviceToHost));
/* Free device memory */
cuda_check(cudaFree(kernel_d));
cuda_check(cudaFree(image_mat_d));
cuda_check(cudaFree(result_mat_d));
}
void write_gaussian(char *filename, unsigned char *picture, int width, int height)
{
FILE *fp;
/* Open file */
fp = fopen(filename, "wb");
if (!fp) {
fprintf(stderr, "Error: cannot open file %s", filename);
exit(1);
}
/* Put structural information */
fprintf(fp, "P5\n%d %d\n255\n", width, height);
/* Output grayscale pixels */
fwrite(picture, sizeof(unsigned char), width * height, fp);
// free(pixels);
fclose(fp);
}
int main(int argc, char *argv[])
{
float sigma, order;
char *output_filename;
int width, height;
FILE *input_file;
/* Command line arguments */
if (argc < 4) {
fprintf(stderr, "Usage: %s <input_pgm> <output_pgm> <sigma>\n",
argv[0]);
exit(1);
}
input_file = fopen(argv[1], "rb");
if (!input_file) {
fprintf(stderr, "Error: cannot open file %s", argv[1]);
exit(1);
}
output_filename = argv[2];
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
if (fscanf(input_file, "%d %d\n", &width, &height) != 2) {
exit(1);
}
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
sigma = atof(argv[3]);
if (sigma <= 0) {
fprintf(stderr, "Error: invalid sigma value");
exit(1);
}
order = ceil(6 * sigma);
if ((int)order % 2 == 0) {
order++;
}
if (order > width || order > height) {
fprintf(stderr, "Error: sigma value too big for image size");
exit(1);
}
float *kernel;
unsigned char *image_mat, *result_mat;
kernel = (float*)aligned_alloc(64, (int) order * (int) order * sizeof(float));
image_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
result_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
if (fread(image_mat, sizeof(unsigned char), height * width, input_file) != (size_t)(height * width)) {
exit(1);
}
fclose(input_file);
float sum = 0;
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] = exp(-(pow(i - floor(order/2), 2) + pow(j - floor(order/2), 2))/(2 * sigma * sigma));
sum += kernel[i * (int) order + j];
}
}
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] /= sum;
}
}
gaussian_calc(image_mat, result_mat, kernel, width, height,(int) order);
// /* Save output image */
write_gaussian(output_filename, result_mat, width, height);
free(kernel);
free(image_mat);
free(result_mat);
return 0;
} | .file "tmpxft_00049bb2_00000000-6_gaussian_blur_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wb"
.LC1:
.string "Error: cannot open file %s"
.LC2:
.string "P5\n%d %d\n255\n"
.text
.globl _Z14write_gaussianPcPhii
.type _Z14write_gaussianPcPhii, @function
_Z14write_gaussianPcPhii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %r12d
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L6
movq %rax, %rbp
movl %r12d, %r8d
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
imull %r12d, %ebx
movslq %ebx, %rdx
movq %rbp, %rcx
movl $1, %esi
movq %r13, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movq %r14, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z14write_gaussianPcPhii, .-_Z14write_gaussianPcPhii
.globl _Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf
.type _Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf, @function
_Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20gaussian_calc_kernelPhS_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf, .-_Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf
.globl _Z20gaussian_calc_kernelPhS_Pf
.type _Z20gaussian_calc_kernelPhS_Pf, @function
_Z20gaussian_calc_kernelPhS_Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z20gaussian_calc_kernelPhS_Pf, .-_Z20gaussian_calc_kernelPhS_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/cwdaggs/gaussian/main/gaussian_blur_cuda.cu"
.section .rodata.str1.1
.LC4:
.string "CudaErr: %s (%s:%d)\n"
.text
.globl _Z13gaussian_calcPhS_Pfiii
.type _Z13gaussian_calcPhS_Pfiii, @function
_Z13gaussian_calcPhS_Pfiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rsi, %r12
movq %rdx, %rbp
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
imull %r9d, %r9d
movslq %r9d, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
movl 12(%rsp), %esi
imull 8(%rsp), %esi
movslq %esi, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
movl 12(%rsp), %esi
imull 8(%rsp), %esi
movslq %esi, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
movl 4(%rsp), %edx
imull %edx, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L34
movl 12(%rsp), %edx
imull 8(%rsp), %edx
movslq %edx, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L35
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL7width_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L36
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL8height_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L37
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL7order_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L38
movl 12(%rsp), %eax
leal 778(%rax), %eax
movl $2822879661, %edx
imulq %rdx, %rax
shrq $41, %rax
movl %eax, 60(%rsp)
movl 8(%rsp), %eax
movl %eax, 64(%rsp)
movl $779, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L24:
movl 12(%rsp), %edx
imull 8(%rsp), %edx
movslq %edx, %rdx
movl $2, %ecx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L40
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L41
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L42
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L43
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $53, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $54, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $55, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $58, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $59, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $60, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $61, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $62, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf
jmp .L24
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $70, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $73, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $74, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $75, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z13gaussian_calcPhS_Pfiii, .-_Z13gaussian_calcPhS_Pfiii
.section .rodata.str1.8
.align 8
.LC6:
.string "Usage: %s <input_pgm> <output_pgm> <sigma>\n"
.section .rodata.str1.1
.LC7:
.string "rb"
.LC8:
.string "%*[^\n]\n"
.LC9:
.string "%d %d\n"
.LC10:
.string "Error: invalid sigma value"
.section .rodata.str1.8
.align 8
.LC15:
.string "Error: sigma value too big for image size"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jle .L76
movq 8(%rsi), %rdi
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L77
movq 16(%rbx), %rax
movq %rax, 40(%rsp)
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
jne .L78
leaq 68(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
jne .L79
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L80
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
pxor %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
movss %xmm1, (%rsp)
pxor %xmm0, %xmm0
comiss %xmm1, %xmm0
jnb .L81
movss (%rsp), %xmm0
mulss .LC11(%rip), %xmm0
movaps %xmm0, %xmm2
movss .LC18(%rip), %xmm3
movaps %xmm0, %xmm1
andps %xmm3, %xmm1
movss .LC12(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L53
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm2
movss .LC14(%rip), %xmm4
andps %xmm4, %xmm2
addss %xmm1, %xmm2
andnps %xmm0, %xmm3
orps %xmm3, %xmm2
.L53:
movss %xmm2, 4(%rsp)
cvttss2sil %xmm2, %eax
testb $1, %al
jne .L54
addss .LC14(%rip), %xmm2
movss %xmm2, 4(%rsp)
.L54:
movl 64(%rsp), %ebx
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movss 4(%rsp), %xmm2
comiss %xmm0, %xmm2
ja .L55
movl 68(%rsp), %r12d
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
comiss %xmm0, %xmm2
ja .L55
cvttss2sil 4(%rsp), %esi
movl %esi, 28(%rsp)
imull %esi, %esi
movslq %esi, %rsi
salq $2, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, 32(%rsp)
imull %r12d, %ebx
movslq %ebx, %rbx
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %r14
movq %rax, 48(%rsp)
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, 56(%rsp)
movq %rbp, %r8
movq %rbx, %rcx
movl $1, %edx
movq %rbx, %rsi
movq %r14, %rdi
call __fread_chk@PLT
movq %rax, %rdx
movl 68(%rsp), %eax
imull 64(%rsp), %eax
cltq
cmpq %rdx, %rax
jne .L82
movq %rbp, %rdi
call fclose@PLT
pxor %xmm0, %xmm0
movss 4(%rsp), %xmm3
comiss %xmm0, %xmm3
jbe .L59
movaps %xmm3, %xmm0
mulss .LC16(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC18(%rip), %xmm1
movaps %xmm0, %xmm2
andps %xmm1, %xmm2
movss .LC12(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L61
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
andnps %xmm0, %xmm1
movaps %xmm2, %xmm3
orps %xmm1, %xmm3
.L61:
movss %xmm3, 24(%rsp)
movss (%rsp), %xmm4
movaps %xmm4, %xmm0
addss %xmm4, %xmm0
mulss %xmm4, %xmm0
pxor %xmm3, %xmm3
cvtss2sd %xmm0, %xmm3
movsd %xmm3, 16(%rsp)
movslq 28(%rsp), %r15
salq $2, %r15
movq 32(%rsp), %r12
movq %r12, %rbp
movl %r13d, %r14d
movl $0x00000000, (%rsp)
pxor %xmm0, %xmm0
.L62:
subss 24(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, 8(%rsp)
movl $1, %ebx
pxor %xmm0, %xmm0
.L63:
subss 24(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
addsd 8(%rsp), %xmm0
xorpd .LC17(%rip), %xmm0
divsd 16(%rsp), %xmm0
call exp@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -4(%r12,%rbx,4)
addss (%rsp), %xmm0
movss %xmm0, (%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
addq $1, %rbx
movss 4(%rsp), %xmm3
comiss %xmm0, %xmm3
ja .L63
addl $1, %r14d
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
addq %r15, %r12
comiss %xmm0, %xmm3
ja .L62
.L64:
movl $1, %eax
.L66:
movss -4(%rbp,%rax,4), %xmm0
divss (%rsp), %xmm0
movss %xmm0, -4(%rbp,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addq $1, %rax
movss 4(%rsp), %xmm2
comiss %xmm0, %xmm2
ja .L66
addl $1, %r13d
addq %r15, %rbp
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
comiss %xmm0, %xmm2
ja .L64
.L59:
movl 28(%rsp), %r9d
movl 68(%rsp), %r8d
movl 64(%rsp), %ecx
movq 32(%rsp), %r14
movq %r14, %rdx
movq 56(%rsp), %rbx
movq %rbx, %rsi
movq 48(%rsp), %r15
movq %r15, %rdi
call _Z13gaussian_calcPhS_Pfiii
movl 68(%rsp), %ecx
movl 64(%rsp), %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call _Z14write_gaussianPcPhii
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L83
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
movq 8(%rbx), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L78:
movl $1, %edi
call exit@PLT
.L79:
movl $1, %edi
call exit@PLT
.L80:
movl $1, %edi
call exit@PLT
.L81:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L82:
movl $1, %edi
call exit@PLT
.L83:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC19:
.string "_Z20gaussian_calc_kernelPhS_Pf"
.section .rodata.str1.1
.LC20:
.string "width_d"
.LC21:
.string "height_d"
.LC22:
.string "order_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z20gaussian_calc_kernelPhS_Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7width_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8height_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7order_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7order_d
.comm _ZL7order_d,4,4
.local _ZL8height_d
.comm _ZL8height_d,4,4
.local _ZL7width_d
.comm _ZL7width_d,4,4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1086324736
.align 4
.LC12:
.long 1258291200
.align 4
.LC14:
.long 1065353216
.align 4
.LC16:
.long 1056964608
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC17:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC18:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <limits.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(cudaError_t ret, const char *file, int line) {
if (ret != cudaSuccess) {
fprintf(stderr, "CudaErr: %s (%s:%d)\n", cudaGetErrorString(ret), file, line);
exit(1);
}
}
__constant__ int width_d;
__constant__ int height_d;
__constant__ int order_d;
__global__ void gaussian_calc_kernel(unsigned char *image_mat, unsigned char *result_mat, float *kernel)
{
float val = 0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int j = blockIdx.x * blockDim.x + tx; //col
int i = blockIdx.y * blockDim.y + ty; //row
if (i >= height_d || j >= width_d) {
return;
}
int center = (order_d - 1) / 2;
for (int x = 0; x < order_d; x++) {
for (int y = 0; y < order_d; y++) {
// Min accounts for right and bottom edges
// Max accounts for left and top edges
int mat_x = max(0, min(i + x - center, height_d - 1));
int mat_y = max(0, min(j + y - center, width_d - 1));
val += image_mat[mat_x * width_d + mat_y] * kernel[x * order_d + y];
}
}
result_mat[i * width_d + j] = (unsigned char) val;
}
void gaussian_calc(unsigned char *image_mat, unsigned char *result_mat, float *kernel, int width, int height, int order)
{
/* Allocate device memory for all matrices */
float *kernel_d;
unsigned char *image_mat_d, *result_mat_d;
cuda_check(cudaMalloc(&kernel_d, order * order * sizeof(float)));
cuda_check(cudaMalloc(&image_mat_d, width * height * sizeof(unsigned char)));
cuda_check(cudaMalloc(&result_mat_d, width * height * sizeof(unsigned char)));
/* Copy kernel and image_mat to device */
cuda_check(cudaMemcpy(kernel_d, kernel, order * order * sizeof(float), cudaMemcpyHostToDevice));
cuda_check(cudaMemcpy(image_mat_d, image_mat, width * height * sizeof(unsigned char), cudaMemcpyHostToDevice));
cuda_check(cudaMemcpyToSymbol(width_d, &width, sizeof(int)));
cuda_check(cudaMemcpyToSymbol(height_d, &height, sizeof(int)));
cuda_check(cudaMemcpyToSymbol(order_d, &order, sizeof(int)));
/* Invoke kernel function */
dim3 block_dim(779, 1);
dim3 grid_dim(DIV_ROUND_UP(width, block_dim.x), DIV_ROUND_UP(height, block_dim.y));
gaussian_calc_kernel<<<grid_dim, block_dim>>>(image_mat_d, result_mat_d, kernel_d);
/* Copy result back to host */
cuda_check(cudaMemcpy(result_mat, result_mat_d, width * height * sizeof(unsigned char), cudaMemcpyDeviceToHost));
/* Free device memory */
cuda_check(cudaFree(kernel_d));
cuda_check(cudaFree(image_mat_d));
cuda_check(cudaFree(result_mat_d));
}
void write_gaussian(char *filename, unsigned char *picture, int width, int height)
{
FILE *fp;
/* Open file */
fp = fopen(filename, "wb");
if (!fp) {
fprintf(stderr, "Error: cannot open file %s", filename);
exit(1);
}
/* Put structural information */
fprintf(fp, "P5\n%d %d\n255\n", width, height);
/* Output grayscale pixels */
fwrite(picture, sizeof(unsigned char), width * height, fp);
// free(pixels);
fclose(fp);
}
int main(int argc, char *argv[])
{
float sigma, order;
char *output_filename;
int width, height;
FILE *input_file;
/* Command line arguments */
if (argc < 4) {
fprintf(stderr, "Usage: %s <input_pgm> <output_pgm> <sigma>\n",
argv[0]);
exit(1);
}
input_file = fopen(argv[1], "rb");
if (!input_file) {
fprintf(stderr, "Error: cannot open file %s", argv[1]);
exit(1);
}
output_filename = argv[2];
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
if (fscanf(input_file, "%d %d\n", &width, &height) != 2) {
exit(1);
}
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
sigma = atof(argv[3]);
if (sigma <= 0) {
fprintf(stderr, "Error: invalid sigma value");
exit(1);
}
order = ceil(6 * sigma);
if ((int)order % 2 == 0) {
order++;
}
if (order > width || order > height) {
fprintf(stderr, "Error: sigma value too big for image size");
exit(1);
}
float *kernel;
unsigned char *image_mat, *result_mat;
kernel = (float*)aligned_alloc(64, (int) order * (int) order * sizeof(float));
image_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
result_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
if (fread(image_mat, sizeof(unsigned char), height * width, input_file) != (size_t)(height * width)) {
exit(1);
}
fclose(input_file);
float sum = 0;
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] = exp(-(pow(i - floor(order/2), 2) + pow(j - floor(order/2), 2))/(2 * sigma * sigma));
sum += kernel[i * (int) order + j];
}
}
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] /= sum;
}
}
gaussian_calc(image_mat, result_mat, kernel, width, height,(int) order);
// /* Save output image */
write_gaussian(output_filename, result_mat, width, height);
free(kernel);
free(image_mat);
free(result_mat);
return 0;
} | #include <hip/hip_runtime.h>
#include <limits.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(hipError_t ret, const char *file, int line) {
if (ret != hipSuccess) {
fprintf(stderr, "CudaErr: %s (%s:%d)\n", hipGetErrorString(ret), file, line);
exit(1);
}
}
__constant__ int width_d;
__constant__ int height_d;
__constant__ int order_d;
__global__ void gaussian_calc_kernel(unsigned char *image_mat, unsigned char *result_mat, float *kernel)
{
float val = 0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int j = blockIdx.x * blockDim.x + tx; //col
int i = blockIdx.y * blockDim.y + ty; //row
if (i >= height_d || j >= width_d) {
return;
}
int center = (order_d - 1) / 2;
for (int x = 0; x < order_d; x++) {
for (int y = 0; y < order_d; y++) {
// Min accounts for right and bottom edges
// Max accounts for left and top edges
int mat_x = max(0, min(i + x - center, height_d - 1));
int mat_y = max(0, min(j + y - center, width_d - 1));
val += image_mat[mat_x * width_d + mat_y] * kernel[x * order_d + y];
}
}
result_mat[i * width_d + j] = (unsigned char) val;
}
void gaussian_calc(unsigned char *image_mat, unsigned char *result_mat, float *kernel, int width, int height, int order)
{
/* Allocate device memory for all matrices */
float *kernel_d;
unsigned char *image_mat_d, *result_mat_d;
cuda_check(hipMalloc(&kernel_d, order * order * sizeof(float)));
cuda_check(hipMalloc(&image_mat_d, width * height * sizeof(unsigned char)));
cuda_check(hipMalloc(&result_mat_d, width * height * sizeof(unsigned char)));
/* Copy kernel and image_mat to device */
cuda_check(hipMemcpy(kernel_d, kernel, order * order * sizeof(float), hipMemcpyHostToDevice));
cuda_check(hipMemcpy(image_mat_d, image_mat, width * height * sizeof(unsigned char), hipMemcpyHostToDevice));
cuda_check(hipMemcpyToSymbol(HIP_SYMBOL(width_d), &width, sizeof(int)));
cuda_check(hipMemcpyToSymbol(HIP_SYMBOL(height_d), &height, sizeof(int)));
cuda_check(hipMemcpyToSymbol(HIP_SYMBOL(order_d), &order, sizeof(int)));
/* Invoke kernel function */
dim3 block_dim(779, 1);
dim3 grid_dim(DIV_ROUND_UP(width, block_dim.x), DIV_ROUND_UP(height, block_dim.y));
gaussian_calc_kernel<<<grid_dim, block_dim>>>(image_mat_d, result_mat_d, kernel_d);
/* Copy result back to host */
cuda_check(hipMemcpy(result_mat, result_mat_d, width * height * sizeof(unsigned char), hipMemcpyDeviceToHost));
/* Free device memory */
cuda_check(hipFree(kernel_d));
cuda_check(hipFree(image_mat_d));
cuda_check(hipFree(result_mat_d));
}
void write_gaussian(char *filename, unsigned char *picture, int width, int height)
{
FILE *fp;
/* Open file */
fp = fopen(filename, "wb");
if (!fp) {
fprintf(stderr, "Error: cannot open file %s", filename);
exit(1);
}
/* Put structural information */
fprintf(fp, "P5\n%d %d\n255\n", width, height);
/* Output grayscale pixels */
fwrite(picture, sizeof(unsigned char), width * height, fp);
// free(pixels);
fclose(fp);
}
int main(int argc, char *argv[])
{
float sigma, order;
char *output_filename;
int width, height;
FILE *input_file;
/* Command line arguments */
if (argc < 4) {
fprintf(stderr, "Usage: %s <input_pgm> <output_pgm> <sigma>\n",
argv[0]);
exit(1);
}
input_file = fopen(argv[1], "rb");
if (!input_file) {
fprintf(stderr, "Error: cannot open file %s", argv[1]);
exit(1);
}
output_filename = argv[2];
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
if (fscanf(input_file, "%d %d\n", &width, &height) != 2) {
exit(1);
}
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
sigma = atof(argv[3]);
if (sigma <= 0) {
fprintf(stderr, "Error: invalid sigma value");
exit(1);
}
order = ceil(6 * sigma);
if ((int)order % 2 == 0) {
order++;
}
if (order > width || order > height) {
fprintf(stderr, "Error: sigma value too big for image size");
exit(1);
}
float *kernel;
unsigned char *image_mat, *result_mat;
kernel = (float*)aligned_alloc(64, (int) order * (int) order * sizeof(float));
image_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
result_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
if (fread(image_mat, sizeof(unsigned char), height * width, input_file) != (size_t)(height * width)) {
exit(1);
}
fclose(input_file);
float sum = 0;
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] = exp(-(pow(i - floor(order/2), 2) + pow(j - floor(order/2), 2))/(2 * sigma * sigma));
sum += kernel[i * (int) order + j];
}
}
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] /= sum;
}
}
gaussian_calc(image_mat, result_mat, kernel, width, height,(int) order);
// /* Save output image */
write_gaussian(output_filename, result_mat, width, height);
free(kernel);
free(image_mat);
free(result_mat);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <limits.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(hipError_t ret, const char *file, int line) {
if (ret != hipSuccess) {
fprintf(stderr, "CudaErr: %s (%s:%d)\n", hipGetErrorString(ret), file, line);
exit(1);
}
}
__constant__ int width_d;
__constant__ int height_d;
__constant__ int order_d;
__global__ void gaussian_calc_kernel(unsigned char *image_mat, unsigned char *result_mat, float *kernel)
{
float val = 0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int j = blockIdx.x * blockDim.x + tx; //col
int i = blockIdx.y * blockDim.y + ty; //row
if (i >= height_d || j >= width_d) {
return;
}
int center = (order_d - 1) / 2;
for (int x = 0; x < order_d; x++) {
for (int y = 0; y < order_d; y++) {
// Min accounts for right and bottom edges
// Max accounts for left and top edges
int mat_x = max(0, min(i + x - center, height_d - 1));
int mat_y = max(0, min(j + y - center, width_d - 1));
val += image_mat[mat_x * width_d + mat_y] * kernel[x * order_d + y];
}
}
result_mat[i * width_d + j] = (unsigned char) val;
}
void gaussian_calc(unsigned char *image_mat, unsigned char *result_mat, float *kernel, int width, int height, int order)
{
/* Allocate device memory for all matrices */
float *kernel_d;
unsigned char *image_mat_d, *result_mat_d;
cuda_check(hipMalloc(&kernel_d, order * order * sizeof(float)));
cuda_check(hipMalloc(&image_mat_d, width * height * sizeof(unsigned char)));
cuda_check(hipMalloc(&result_mat_d, width * height * sizeof(unsigned char)));
/* Copy kernel and image_mat to device */
cuda_check(hipMemcpy(kernel_d, kernel, order * order * sizeof(float), hipMemcpyHostToDevice));
cuda_check(hipMemcpy(image_mat_d, image_mat, width * height * sizeof(unsigned char), hipMemcpyHostToDevice));
cuda_check(hipMemcpyToSymbol(HIP_SYMBOL(width_d), &width, sizeof(int)));
cuda_check(hipMemcpyToSymbol(HIP_SYMBOL(height_d), &height, sizeof(int)));
cuda_check(hipMemcpyToSymbol(HIP_SYMBOL(order_d), &order, sizeof(int)));
/* Invoke kernel function */
dim3 block_dim(779, 1);
dim3 grid_dim(DIV_ROUND_UP(width, block_dim.x), DIV_ROUND_UP(height, block_dim.y));
gaussian_calc_kernel<<<grid_dim, block_dim>>>(image_mat_d, result_mat_d, kernel_d);
/* Copy result back to host */
cuda_check(hipMemcpy(result_mat, result_mat_d, width * height * sizeof(unsigned char), hipMemcpyDeviceToHost));
/* Free device memory */
cuda_check(hipFree(kernel_d));
cuda_check(hipFree(image_mat_d));
cuda_check(hipFree(result_mat_d));
}
void write_gaussian(char *filename, unsigned char *picture, int width, int height)
{
FILE *fp;
/* Open file */
fp = fopen(filename, "wb");
if (!fp) {
fprintf(stderr, "Error: cannot open file %s", filename);
exit(1);
}
/* Put structural information */
fprintf(fp, "P5\n%d %d\n255\n", width, height);
/* Output grayscale pixels */
fwrite(picture, sizeof(unsigned char), width * height, fp);
// free(pixels);
fclose(fp);
}
int main(int argc, char *argv[])
{
float sigma, order;
char *output_filename;
int width, height;
FILE *input_file;
/* Command line arguments */
if (argc < 4) {
fprintf(stderr, "Usage: %s <input_pgm> <output_pgm> <sigma>\n",
argv[0]);
exit(1);
}
input_file = fopen(argv[1], "rb");
if (!input_file) {
fprintf(stderr, "Error: cannot open file %s", argv[1]);
exit(1);
}
output_filename = argv[2];
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
if (fscanf(input_file, "%d %d\n", &width, &height) != 2) {
exit(1);
}
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
sigma = atof(argv[3]);
if (sigma <= 0) {
fprintf(stderr, "Error: invalid sigma value");
exit(1);
}
order = ceil(6 * sigma);
if ((int)order % 2 == 0) {
order++;
}
if (order > width || order > height) {
fprintf(stderr, "Error: sigma value too big for image size");
exit(1);
}
float *kernel;
unsigned char *image_mat, *result_mat;
kernel = (float*)aligned_alloc(64, (int) order * (int) order * sizeof(float));
image_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
result_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
if (fread(image_mat, sizeof(unsigned char), height * width, input_file) != (size_t)(height * width)) {
exit(1);
}
fclose(input_file);
float sum = 0;
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] = exp(-(pow(i - floor(order/2), 2) + pow(j - floor(order/2), 2))/(2 * sigma * sigma));
sum += kernel[i * (int) order + j];
}
}
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] /= sum;
}
}
gaussian_calc(image_mat, result_mat, kernel, width, height,(int) order);
// /* Save output image */
write_gaussian(output_filename, result_mat, width, height);
free(kernel);
free(image_mat);
free(result_mat);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20gaussian_calc_kernelPhS_Pf
.globl _Z20gaussian_calc_kernelPhS_Pf
.p2align 8
.type _Z20gaussian_calc_kernelPhS_Pf,@function
_Z20gaussian_calc_kernelPhS_Pf:
s_load_b32 s6, s[0:1], 0x24
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, height_d@rel32@lo+4
s_addc_u32 s3, s3, height_d@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, width_d@rel32@lo+4
s_addc_u32 s5, s5, width_d@rel32@hi+12
s_load_b32 s12, s[2:3], 0x0
s_load_b32 s10, s[4:5], 0x0
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s6, 16
s_and_b32 s2, s6, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
s_mul_i32 s14, s14, s2
v_add_nc_u32_e32 v1, s14, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s12, v0
v_cmp_gt_i32_e64 s2, s10, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, order_d@rel32@lo+4
s_addc_u32 s3, s3, order_d@rel32@hi+12
s_load_b32 s11, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s11, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_add_i32 s6, s11, -1
s_add_i32 s12, s12, -1
s_lshr_b32 s7, s6, 31
s_add_i32 s13, s10, -1
s_add_i32 s6, s6, s7
s_mov_b32 s7, 0
s_ashr_i32 s6, s6, 1
v_mov_b32_e32 v4, 0
v_subrev_nc_u32_e32 v2, s6, v0
s_sub_i32 s6, s14, s6
s_mov_b32 s14, s7
v_add_nc_u32_e32 v3, s6, v3
s_mov_b32 s6, s7
.p2align 6
.LBB0_3:
v_add_nc_u32_e32 v5, s14, v2
s_lshl_b64 s[8:9], s[6:7], 2
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
v_minmax_i32 v5, v5, s12, 0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s10
.p2align 6
.LBB0_4:
v_add_nc_u32_e32 v6, s15, v3
s_load_b32 s16, s[8:9], 0x0
s_add_i32 s15, s15, 1
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
v_minmax_i32 v6, v6, s13, 0
s_cmp_eq_u32 s11, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, v6, v5
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_u8 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v4, s16, v6
s_cbranch_scc0 .LBB0_4
s_add_i32 s14, s14, 1
s_add_i32 s6, s6, s11
s_cmp_eq_u32 s14, s11
s_cbranch_scc0 .LBB0_3
v_cvt_i32_f32_e32 v2, v4
s_branch .LBB0_8
.LBB0_7:
v_mov_b32_e32 v2, 0
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s10, v[1:2]
v_ashrrev_i32_e32 v1, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20gaussian_calc_kernelPhS_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20gaussian_calc_kernelPhS_Pf, .Lfunc_end0-_Z20gaussian_calc_kernelPhS_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected width_d
.type width_d,@object
.section .bss,"aw",@nobits
.globl width_d
.p2align 2, 0x0
width_d:
.long 0
.size width_d, 4
.protected height_d
.type height_d,@object
.globl height_d
.p2align 2, 0x0
height_d:
.long 0
.size height_d, 4
.protected order_d
.type order_d,@object
.globl order_d
.p2align 2, 0x0
order_d:
.long 0
.size order_d, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym width_d
.addrsig_sym height_d
.addrsig_sym order_d
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20gaussian_calc_kernelPhS_Pf
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z20gaussian_calc_kernelPhS_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <limits.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define cuda_check(ret) _cuda_check((ret), __FILE__, __LINE__)
inline void _cuda_check(hipError_t ret, const char *file, int line) {
if (ret != hipSuccess) {
fprintf(stderr, "CudaErr: %s (%s:%d)\n", hipGetErrorString(ret), file, line);
exit(1);
}
}
__constant__ int width_d;
__constant__ int height_d;
__constant__ int order_d;
__global__ void gaussian_calc_kernel(unsigned char *image_mat, unsigned char *result_mat, float *kernel)
{
float val = 0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int j = blockIdx.x * blockDim.x + tx; //col
int i = blockIdx.y * blockDim.y + ty; //row
if (i >= height_d || j >= width_d) {
return;
}
int center = (order_d - 1) / 2;
for (int x = 0; x < order_d; x++) {
for (int y = 0; y < order_d; y++) {
// Min accounts for right and bottom edges
// Max accounts for left and top edges
int mat_x = max(0, min(i + x - center, height_d - 1));
int mat_y = max(0, min(j + y - center, width_d - 1));
val += image_mat[mat_x * width_d + mat_y] * kernel[x * order_d + y];
}
}
result_mat[i * width_d + j] = (unsigned char) val;
}
void gaussian_calc(unsigned char *image_mat, unsigned char *result_mat, float *kernel, int width, int height, int order)
{
/* Allocate device memory for all matrices */
float *kernel_d;
unsigned char *image_mat_d, *result_mat_d;
cuda_check(hipMalloc(&kernel_d, order * order * sizeof(float)));
cuda_check(hipMalloc(&image_mat_d, width * height * sizeof(unsigned char)));
cuda_check(hipMalloc(&result_mat_d, width * height * sizeof(unsigned char)));
/* Copy kernel and image_mat to device */
cuda_check(hipMemcpy(kernel_d, kernel, order * order * sizeof(float), hipMemcpyHostToDevice));
cuda_check(hipMemcpy(image_mat_d, image_mat, width * height * sizeof(unsigned char), hipMemcpyHostToDevice));
cuda_check(hipMemcpyToSymbol(HIP_SYMBOL(width_d), &width, sizeof(int)));
cuda_check(hipMemcpyToSymbol(HIP_SYMBOL(height_d), &height, sizeof(int)));
cuda_check(hipMemcpyToSymbol(HIP_SYMBOL(order_d), &order, sizeof(int)));
/* Invoke kernel function */
dim3 block_dim(779, 1);
dim3 grid_dim(DIV_ROUND_UP(width, block_dim.x), DIV_ROUND_UP(height, block_dim.y));
gaussian_calc_kernel<<<grid_dim, block_dim>>>(image_mat_d, result_mat_d, kernel_d);
/* Copy result back to host */
cuda_check(hipMemcpy(result_mat, result_mat_d, width * height * sizeof(unsigned char), hipMemcpyDeviceToHost));
/* Free device memory */
cuda_check(hipFree(kernel_d));
cuda_check(hipFree(image_mat_d));
cuda_check(hipFree(result_mat_d));
}
void write_gaussian(char *filename, unsigned char *picture, int width, int height)
{
FILE *fp;
/* Open file */
fp = fopen(filename, "wb");
if (!fp) {
fprintf(stderr, "Error: cannot open file %s", filename);
exit(1);
}
/* Put structural information */
fprintf(fp, "P5\n%d %d\n255\n", width, height);
/* Output grayscale pixels */
fwrite(picture, sizeof(unsigned char), width * height, fp);
// free(pixels);
fclose(fp);
}
int main(int argc, char *argv[])
{
float sigma, order;
char *output_filename;
int width, height;
FILE *input_file;
/* Command line arguments */
if (argc < 4) {
fprintf(stderr, "Usage: %s <input_pgm> <output_pgm> <sigma>\n",
argv[0]);
exit(1);
}
input_file = fopen(argv[1], "rb");
if (!input_file) {
fprintf(stderr, "Error: cannot open file %s", argv[1]);
exit(1);
}
output_filename = argv[2];
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
if (fscanf(input_file, "%d %d\n", &width, &height) != 2) {
exit(1);
}
if (fscanf(input_file, "%*[^\n]\n") != 0) {
exit(1);
}
sigma = atof(argv[3]);
if (sigma <= 0) {
fprintf(stderr, "Error: invalid sigma value");
exit(1);
}
order = ceil(6 * sigma);
if ((int)order % 2 == 0) {
order++;
}
if (order > width || order > height) {
fprintf(stderr, "Error: sigma value too big for image size");
exit(1);
}
float *kernel;
unsigned char *image_mat, *result_mat;
kernel = (float*)aligned_alloc(64, (int) order * (int) order * sizeof(float));
image_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
result_mat = (unsigned char*)aligned_alloc(64, width * height * sizeof(unsigned char));
if (fread(image_mat, sizeof(unsigned char), height * width, input_file) != (size_t)(height * width)) {
exit(1);
}
fclose(input_file);
float sum = 0;
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] = exp(-(pow(i - floor(order/2), 2) + pow(j - floor(order/2), 2))/(2 * sigma * sigma));
sum += kernel[i * (int) order + j];
}
}
for (int i = 0; i < order; i++) {
for (int j = 0; j < order; j++) {
kernel[i * (int) order + j] /= sum;
}
}
gaussian_calc(image_mat, result_mat, kernel, width, height,(int) order);
// /* Save output image */
write_gaussian(output_filename, result_mat, width, height);
free(kernel);
free(image_mat);
free(result_mat);
return 0;
} | .text
.file "gaussian_blur_cuda.hip"
.globl _Z35__device_stub__gaussian_calc_kernelPhS_Pf # -- Begin function _Z35__device_stub__gaussian_calc_kernelPhS_Pf
.p2align 4, 0x90
.type _Z35__device_stub__gaussian_calc_kernelPhS_Pf,@function
_Z35__device_stub__gaussian_calc_kernelPhS_Pf: # @_Z35__device_stub__gaussian_calc_kernelPhS_Pf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20gaussian_calc_kernelPhS_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__gaussian_calc_kernelPhS_Pf, .Lfunc_end0-_Z35__device_stub__gaussian_calc_kernelPhS_Pf
.cfi_endproc
# -- End function
.globl _Z13gaussian_calcPhS_Pfiii # -- Begin function _Z13gaussian_calcPhS_Pfiii
.p2align 4, 0x90
.type _Z13gaussian_calcPhS_Pfiii,@function
_Z13gaussian_calcPhS_Pfiii: # @_Z13gaussian_calcPhS_Pfiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
# kill: def $r9d killed $r9d def $r9
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r14
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, 12(%rsp)
imull %r9d, %r9d
leaq (,%r9,4), %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z11_cuda_check10hipError_tPKci.exit
movslq 8(%rsp), %rax
movslq 4(%rsp), %rsi
imulq %rax, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z11_cuda_check10hipError_tPKci.exit10
movslq 8(%rsp), %rax
movslq 4(%rsp), %rsi
imulq %rax, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z11_cuda_check10hipError_tPKci.exit12
movq 32(%rsp), %rdi
movl 12(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z11_cuda_check10hipError_tPKci.exit14
movq 24(%rsp), %rdi
movslq 8(%rsp), %rax
movslq 4(%rsp), %rdx
imulq %rax, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z11_cuda_check10hipError_tPKci.exit16
leaq 8(%rsp), %rsi
movl $width_d, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z11_cuda_check10hipError_tPKci.exit18
leaq 4(%rsp), %rsi
movl $height_d, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z11_cuda_check10hipError_tPKci.exit20
leaq 12(%rsp), %rsi
movl $order_d, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z11_cuda_check10hipError_tPKci.exit22
movl $778, %eax # imm = 0x30A
addl 8(%rsp), %eax
movl $2822879661, %ecx # imm = 0xA841B9AD
imulq %rax, %rcx
shrq $41, %rcx
movl 4(%rsp), %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $4294968075, %rdx # imm = 0x10000030B
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_19
# %bb.18:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20gaussian_calc_kernelPhS_Pf, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_19:
movq 16(%rsp), %rsi
movslq 8(%rsp), %rax
movslq 4(%rsp), %rdx
imulq %rax, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z11_cuda_check10hipError_tPKci.exit24
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_Z11_cuda_check10hipError_tPKci.exit26
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z11_cuda_check10hipError_tPKci.exit28
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_26
# %bb.27: # %_Z11_cuda_check10hipError_tPKci.exit30
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $55, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $56, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $57, %r8d
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $60, %r8d
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $61, %r8d
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $62, %r8d
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $63, %r8d
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $64, %r8d
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB1_2
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $75, %r8d
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $76, %r8d
jmp .LBB1_2
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $77, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z13gaussian_calcPhS_Pfiii, .Lfunc_end1-_Z13gaussian_calcPhS_Pfiii
.cfi_endproc
# -- End function
.globl _Z14write_gaussianPcPhii # -- Begin function _Z14write_gaussianPcPhii
.p2align 4, 0x90
.type _Z14write_gaussianPcPhii,@function
_Z14write_gaussianPcPhii: # @_Z14write_gaussianPcPhii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r14d
movq %rsi, %rbx
movq %rdi, %r12
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB2_1
# %bb.2:
movq %rax, %r15
movl $.L.str.3, %esi
movq %rax, %rdi
movl %r14d, %edx
movl %ebp, %ecx
xorl %eax, %eax
callq fprintf
imull %r14d, %ebp
movslq %ebp, %rdx
movl $1, %esi
movq %rbx, %rdi
movq %r15, %rcx
callq fwrite
movq %r15, %rdi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB2_1:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rdi
movl $.L.str.2, %esi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14write_gaussianPcPhii, .Lfunc_end2-_Z14write_gaussianPcPhii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x40c00000 # float 6
.LCPI3_1:
.long 0x3f800000 # float 1
.LCPI3_2:
.long 0x3f000000 # float 0.5
.LCPI3_4:
.long 0x00000000 # float 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_3:
.quad 0x8000000000000000 # double -0
.quad 0x8000000000000000 # double -0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
cmpl $3, %edi
jle .LBB3_1
# %bb.3:
movq 8(%r14), %rdi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB3_4
# %bb.5:
movq %rax, %r13
movq 16(%r14), %r15
movl $.L.str.6, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
jne .LBB3_30
# %bb.6:
leaq 12(%rsp), %rdx
leaq 8(%rsp), %rcx
movl $.L.str.7, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $2, %eax
jne .LBB3_30
# %bb.7:
movl $.L.str.6, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
jne .LBB3_30
# %bb.8:
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm1
xorps %xmm0, %xmm0
ucomiss %xmm1, %xmm0
jae .LBB3_9
# %bb.11:
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm1, 20(%rsp) # 4-byte Spill
mulss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
testb $1, %al
jne .LBB3_13
# %bb.12:
addss .LCPI3_1(%rip), %xmm0
.LBB3_13:
movl 12(%rsp), %ebx
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
ucomiss %xmm1, %xmm0
ja .LBB3_15
# %bb.14:
movl 8(%rsp), %ebp
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
ucomiss %xmm1, %xmm0
ja .LBB3_15
# %bb.16:
movq %r15, 48(%rsp) # 8-byte Spill
cvttss2si %xmm0, %r14d
movl %r14d, %esi
imull %esi, %esi
shlq $2, %rsi
movl $64, %edi
movss %xmm0, 16(%rsp) # 4-byte Spill
callq aligned_alloc
movq %rax, 24(%rsp) # 8-byte Spill
imull %ebx, %ebp
movslq %ebp, %rbx
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r15
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r12
movl $1, %esi
movq %r15, 40(%rsp) # 8-byte Spill
movq %r15, %rdi
movq %rbx, %rdx
movq %r13, %rcx
callq fread
movslq 8(%rsp), %rcx
movslq 12(%rsp), %rdx
imulq %rcx, %rdx
cmpq %rdx, %rax
jne .LBB3_30
# %bb.17:
movq %r13, %rdi
callq fclose
xorps %xmm0, %xmm0
movss 16(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
movl %r14d, 32(%rsp) # 4-byte Spill
movslq %r14d, %rbx
xorps %xmm3, %xmm3
movaps %xmm1, %xmm2
jbe .LBB3_23
# %bb.18: # %.preheader77.lr.ph
movss .LCPI3_2(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
callq floorf@PLT
movss 16(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movaps %xmm0, %xmm4
movss 20(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movaps %xmm1, %xmm0
addss %xmm1, %xmm0
mulss %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
leaq (,%rbx,4), %r13
xorl %r14d, %r14d
movapd .LCPI3_3(%rip), %xmm5 # xmm5 = [-0.0E+0,-0.0E+0]
movq 24(%rsp), %rbp # 8-byte Reload
xorps %xmm0, %xmm0
xorps %xmm3, %xmm3
movss %xmm4, 36(%rsp) # 4-byte Spill
movsd %xmm1, 56(%rsp) # 8-byte Spill
jmp .LBB3_19
.p2align 4, 0x90
.LBB3_22: # %._crit_edge
# in Loop: Header=BB3_19 Depth=1
incq %r14
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
addq %r13, %rbp
ucomiss %xmm0, %xmm2
jbe .LBB3_23
.LBB3_19: # %.preheader77
# =>This Loop Header: Depth=1
# Child Loop BB3_21 Depth 2
ucomiss .LCPI3_4(%rip), %xmm2
jbe .LBB3_22
# %bb.20: # %.lr.ph
# in Loop: Header=BB3_19 Depth=1
subss %xmm4, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, 64(%rsp) # 8-byte Spill
xorpd %xmm0, %xmm0
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_21: # Parent Loop BB3_19 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm3, 20(%rsp) # 4-byte Spill
subss %xmm4, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
addsd 64(%rsp), %xmm0 # 8-byte Folded Reload
xorpd %xmm5, %xmm0
divsd %xmm1, %xmm0
callq exp
movapd .LCPI3_3(%rip), %xmm5 # xmm5 = [-0.0E+0,-0.0E+0]
movss 36(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 20(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
movss %xmm1, (%rbp,%r15,4)
incq %r15
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
addss %xmm1, %xmm3
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
ucomiss %xmm0, %xmm2
ja .LBB3_21
jmp .LBB3_22
.LBB3_23: # %.preheader76
ucomiss .LCPI3_4(%rip), %xmm2
movq 48(%rsp), %r14 # 8-byte Reload
jbe .LBB3_29
# %bb.24: # %.preheader.lr.ph
shlq $2, %rbx
xorl %eax, %eax
xorps %xmm0, %xmm0
movq 24(%rsp), %rcx # 8-byte Reload
jmp .LBB3_25
.p2align 4, 0x90
.LBB3_28: # %._crit_edge85
# in Loop: Header=BB3_25 Depth=1
incq %rax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
addq %rbx, %rcx
ucomiss %xmm1, %xmm2
jbe .LBB3_29
.LBB3_25: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_27 Depth 2
ucomiss %xmm0, %xmm2
jbe .LBB3_28
# %bb.26: # %.lr.ph84
# in Loop: Header=BB3_25 Depth=1
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_27: # Parent Loop BB3_25 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm3, %xmm1
movss %xmm1, (%rcx,%rdx,4)
incq %rdx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
ucomiss %xmm1, %xmm2
ja .LBB3_27
jmp .LBB3_28
.LBB3_29: # %._crit_edge87
movl 12(%rsp), %ecx
movl 8(%rsp), %r8d
movq 40(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq %r12, %rsi
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdx
movl 32(%rsp), %r9d # 4-byte Reload
callq _Z13gaussian_calcPhS_Pfiii
movl 12(%rsp), %edx
movl 8(%rsp), %ecx
movq %r14, %rdi
movq %r12, %rsi
callq _Z14write_gaussianPcPhii
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_30:
.cfi_def_cfa_offset 128
movl $1, %edi
callq exit
.LBB3_15:
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $41, %esi
jmp .LBB3_10
.LBB3_1:
movq stderr(%rip), %rdi
movq (%r14), %rdx
movl $.L.str.4, %esi
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rdi
movq 8(%r14), %rdx
movl $.L.str.2, %esi
.LBB3_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB3_9:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $26, %esi
.LBB3_10:
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20gaussian_calc_kernelPhS_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $width_d, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $height_d, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $order_d, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type width_d,@object # @width_d
.local width_d
.comm width_d,4,4
.type height_d,@object # @height_d
.local height_d
.comm height_d,4,4
.type order_d,@object # @order_d
.local order_d
.comm order_d,4,4
.type _Z20gaussian_calc_kernelPhS_Pf,@object # @_Z20gaussian_calc_kernelPhS_Pf
.section .rodata,"a",@progbits
.globl _Z20gaussian_calc_kernelPhS_Pf
.p2align 3, 0x0
_Z20gaussian_calc_kernelPhS_Pf:
.quad _Z35__device_stub__gaussian_calc_kernelPhS_Pf
.size _Z20gaussian_calc_kernelPhS_Pf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/cwdaggs/gaussian/main/gaussian_blur_cuda.hip"
.size .L.str, 102
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "wb"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error: cannot open file %s"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "P5\n%d %d\n255\n"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Usage: %s <input_pgm> <output_pgm> <sigma>\n"
.size .L.str.4, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "rb"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%*[^\n]\n"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d %d\n"
.size .L.str.7, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error: invalid sigma value"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Error: sigma value too big for image size"
.size .L.str.9, 42
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "CudaErr: %s (%s:%d)\n"
.size .L.str.10, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20gaussian_calc_kernelPhS_Pf"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "width_d"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "height_d"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "order_d"
.size .L__unnamed_4, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__gaussian_calc_kernelPhS_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym width_d
.addrsig_sym height_d
.addrsig_sym order_d
.addrsig_sym _Z20gaussian_calc_kernelPhS_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20gaussian_calc_kernelPhS_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x3][0x0], PT ; /* 0x00c0000000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R13, R13, c[0x0][0x4], R2 ; /* 0x000001000d0d7a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R13, c[0x3][0x4], P0 ; /* 0x00c001000d007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x3][0x8] ; /* 0x00c00200ff0c7624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc600078e00ff */
/*00d0*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x7d0 ; /* 0x000006e000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R23, R12.reuse, -0x1, RZ ; /* 0xffffffff0c177810 */
/* 0x040fe20007ffe0ff */
/*0100*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0110*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT ; /* 0x000000030c0c7812 */
/* 0x000fe200078ec0ff */
/*0120*/ ULDC.64 UR6, c[0x3][0x0] ; /* 0x00c0000000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ LEA.HI R2, R23, R23, RZ, 0x1 ; /* 0x0000001717027211 */
/* 0x000fe200078f08ff */
/*0140*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R15, -R12, c[0x3][0x8], RZ ; /* 0x00c002000c0f7a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0170*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011402 */
/*0180*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe4000fffe13f */
/*0190*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fc4000fffe13f */
/*01a0*/ IMAD.IADD R17, R13, 0x1, -R2.reuse ; /* 0x000000010d117824 */
/* 0x100fe400078e0a02 */
/*01b0*/ IMAD.IADD R16, R0, 0x1, -R2 ; /* 0x0000000100107824 */
/* 0x000fe400078e0a02 */
/*01c0*/ ISETP.GE.U32.AND P2, PT, R23, 0x3, PT ; /* 0x000000031700780c */
/* 0x000fe20003f46070 */
/*01d0*/ IMAD.IADD R2, R17, 0x1, R14.reuse ; /* 0x0000000111027824 */
/* 0x100fe200078e020e */
/*01e0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*01f0*/ IMAD.MOV.U32 R19, RZ, RZ, R14 ; /* 0x000000ffff137224 */
/* 0x000fe200078e000e */
/*0200*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0220*/ IMNMX R2, R2, UR4, PT ; /* 0x0000000402027c17 */
/* 0x000fe4000b800200 */
/*0230*/ ISETP.GE.AND P1, PT, R14, c[0x3][0x8], PT ; /* 0x00c002000e007a0c */
/* 0x000fc40003f26270 */
/*0240*/ IMNMX R20, RZ, R2, !PT ; /* 0x00000002ff147217 */
/* 0x000fc60007800200 */
/*0250*/ @!P2 BRA 0x570 ; /* 0x000003100000a947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD.MOV.U32 R22, RZ, RZ, R15 ; /* 0x000000ffff167224 */
/* 0x000fe400078e000f */
/*0280*/ IMAD.IADD R2, R16, 0x1, R21 ; /* 0x0000000110027824 */
/* 0x000fca00078e0215 */
/*0290*/ IMNMX R3, R2.reuse, UR5, PT ; /* 0x0000000502037c17 */
/* 0x040fe4000b800200 */
/*02a0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*02b0*/ IADD3 R5, R2, 0x2, RZ ; /* 0x0000000202057810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ IMNMX R3, RZ, R3, !PT ; /* 0x00000003ff037217 */
/* 0x000fe40007800200 */
/*02d0*/ IMNMX R4, R4, UR5, PT ; /* 0x0000000504047c17 */
/* 0x000fe4000b800200 */
/*02e0*/ IADD3 R6, R2, 0x3, RZ ; /* 0x0000000302067810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD R3, R20, c[0x3][0x0], R3 ; /* 0x00c0000014037a24 */
/* 0x000fe200078e0203 */
/*0300*/ IMNMX R2, R5, UR5, PT ; /* 0x0000000505027c17 */
/* 0x000fc4000b800200 */
/*0310*/ IMNMX R5, RZ, R4, !PT ; /* 0x00000004ff057217 */
/* 0x000fe40007800200 */
/*0320*/ IMNMX R6, R6, UR5, PT ; /* 0x0000000506067c17 */
/* 0x000fe4000b800200 */
/*0330*/ IMNMX R7, RZ, R2, !PT ; /* 0x00000002ff077217 */
/* 0x000fe20007800200 */
/*0340*/ IMAD R5, R20.reuse, c[0x3][0x0], R5 ; /* 0x00c0000014057a24 */
/* 0x040fe200078e0205 */
/*0350*/ IADD3 R8, P2, R3.reuse, c[0x0][0x160], RZ ; /* 0x0000580003087a10 */
/* 0x040fe40007f5e0ff */
/*0360*/ IMNMX R11, RZ, R6, !PT ; /* 0x00000006ff0b7217 */
/* 0x000fe20007800200 */
/*0370*/ IMAD R7, R20, c[0x3][0x0], R7 ; /* 0x00c0000014077a24 */
/* 0x000fe200078e0207 */
/*0380*/ LEA.HI.X.SX32 R9, R3, c[0x0][0x164], 0x1, P2 ; /* 0x0000590003097a11 */
/* 0x000fc400010f0eff */
/*0390*/ IADD3 R2, P3, R5, c[0x0][0x160], RZ ; /* 0x0000580005027a10 */
/* 0x000fe20007f7e0ff */
/*03a0*/ IMAD R11, R20, c[0x3][0x0], R11 ; /* 0x00c00000140b7a24 */
/* 0x000fe200078e020b */
/*03b0*/ IADD3 R4, P2, R7, c[0x0][0x160], RZ ; /* 0x0000580007047a10 */
/* 0x000fe20007f5e0ff */
/*03c0*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x0000a2000c1e1100 */
/*03d0*/ LEA.HI.X.SX32 R3, R5, c[0x0][0x164], 0x1, P3 ; /* 0x0000590005037a11 */
/* 0x000fe400018f0eff */
/*03e0*/ IADD3 R6, P3, R11, c[0x0][0x160], RZ ; /* 0x000058000b067a10 */
/* 0x000fe40007f7e0ff */
/*03f0*/ LEA.HI.X.SX32 R5, R7, c[0x0][0x164], 0x1, P2 ; /* 0x0000590007057a11 */
/* 0x000fe200010f0eff */
/*0400*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x0004e2000c1e1100 */
/*0410*/ IMAD R10, R19, c[0x3][0x8], R21 ; /* 0x00c00200130a7a24 */
/* 0x000fe200078e0215 */
/*0420*/ LEA.HI.X.SX32 R7, R11, c[0x0][0x164], 0x1, P3 ; /* 0x000059000b077a11 */
/* 0x000fe200018f0eff */
/*0430*/ IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff197424 */
/* 0x000fe200078e00ff */
/*0440*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000f26000c1e1100 */
/*0450*/ IMAD.WIDE R10, R10, R25, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fe200078e0219 */
/*0460*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000f68000c1e1100 */
/*0470*/ LDG.E R24, [R10.64] ; /* 0x000000080a187981 */
/* 0x000f68000c1e1900 */
/*0480*/ LDG.E R9, [R10.64+0x4] ; /* 0x000004080a097981 */
/* 0x001f68000c1e1900 */
/*0490*/ LDG.E R25, [R10.64+0x8] ; /* 0x000008080a197981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E R27, [R10.64+0xc] ; /* 0x00000c080a1b7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IADD3 R22, R22, -0x4, RZ ; /* 0xfffffffc16167810 */
/* 0x000fc80007ffe0ff */
/*04c0*/ ISETP.NE.AND P2, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f45270 */
/*04d0*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ I2F.U16 R3, R8 ; /* 0x0000000800037306 */
/* 0x004f700000101000 */
/*04f0*/ I2F.U16 R2, R2 ; /* 0x0000000200027306 */
/* 0x008e300000101000 */
/*0500*/ I2F.U16 R26, R4 ; /* 0x00000004001a7306 */
/* 0x010e620000101000 */
/*0510*/ FFMA R3, R3, R24, R18 ; /* 0x0000001803037223 */
/* 0x020fce0000000012 */
/*0520*/ I2F.U16 R28, R6 ; /* 0x00000006001c7306 */
/* 0x000ea20000101000 */
/*0530*/ FFMA R3, R2, R9, R3 ; /* 0x0000000902037223 */
/* 0x001fc80000000003 */
/*0540*/ FFMA R3, R26, R25, R3 ; /* 0x000000191a037223 */
/* 0x002fc80000000003 */
/*0550*/ FFMA R18, R28, R27, R3 ; /* 0x0000001b1c127223 */
/* 0x004fe20000000003 */
/*0560*/ @P2 BRA 0x280 ; /* 0xfffffd1000002947 */
/* 0x000fea000383ffff */
/*0570*/ @!P0 BRA 0x7c0 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0580*/ IMAD.IADD R8, R16, 0x1, R21 ; /* 0x0000000110087824 */
/* 0x000fca00078e0215 */
/*0590*/ IMNMX R2, R8, UR5, PT ; /* 0x0000000508027c17 */
/* 0x000fc8000b800200 */
/*05a0*/ IMNMX R3, RZ, R2, !PT ; /* 0x00000002ff037217 */
/* 0x000fca0007800200 */
/*05b0*/ IMAD R3, R20, c[0x3][0x0], R3 ; /* 0x00c0000014037a24 */
/* 0x000fca00078e0203 */
/*05c0*/ IADD3 R4, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fc80007f1e0ff */
/*05d0*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003057a11 */
/* 0x000fca00000f0eff */
/*05e0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea2000c1e1100 */
/*05f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0600*/ IMAD R2, R19, c[0x3][0x8], R21 ; /* 0x00c0020013027a24 */
/* 0x000fc800078e0215 */
/*0610*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0620*/ LDG.E R6, [R2.64] ; /* 0x0000000802067981 */
/* 0x000ee2000c1e1900 */
/*0630*/ ISETP.NE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe20003f05270 */
/*0640*/ I2F.U16 R7, R4 ; /* 0x0000000400077306 */
/* 0x004ee40000101000 */
/*0650*/ FFMA R18, R7, R6, R18 ; /* 0x0000000607127223 */
/* 0x008fd40000000012 */
/*0660*/ @!P0 BRA 0x7c0 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0670*/ ISETP.NE.AND P0, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe40003f05270 */
/*0680*/ IADD3 R4, R8, 0x1, RZ ; /* 0x0000000108047810 */
/* 0x000fc80007ffe0ff */
/*0690*/ IMNMX R4, R4, UR5, PT ; /* 0x0000000504047c17 */
/* 0x000fc8000b800200 */
/*06a0*/ IMNMX R5, RZ, R4, !PT ; /* 0x00000004ff057217 */
/* 0x000fc60007800200 */
/*06b0*/ @P0 IADD3 R6, R8, 0x2, RZ ; /* 0x0000000208060810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ @P0 LDG.E R10, [R2.64+0x8] ; /* 0x00000808020a0981 */
/* 0x000ea2000c1e1900 */
/*06d0*/ IMAD R5, R20, c[0x3][0x0], R5 ; /* 0x00c0000014057a24 */
/* 0x000fe400078e0205 */
/*06e0*/ @P0 IMNMX R6, R6, UR5, PT ; /* 0x0000000506060c17 */
/* 0x000fe2000b800200 */
/*06f0*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040802087981 */
/* 0x000ee4000c1e1900 */
/*0700*/ IADD3 R4, P2, R5.reuse, c[0x0][0x160], RZ ; /* 0x0000580005047a10 */
/* 0x040fe40007f5e0ff */
/*0710*/ @P0 IMNMX R7, RZ, R6, !PT ; /* 0x00000006ff070217 */
/* 0x000fe40007800200 */
/*0720*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x164], 0x1, P2 ; /* 0x0000590005057a11 */
/* 0x000fc600010f0eff */
/*0730*/ @P0 IMAD R7, R20, c[0x3][0x0], R7 ; /* 0x00c0000014070a24 */
/* 0x000fe400078e0207 */
/*0740*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000f26000c1e1100 */
/*0750*/ @P0 IADD3 R6, P2, R7, c[0x0][0x160], RZ ; /* 0x0000580007060a10 */
/* 0x000fc80007f5e0ff */
/*0760*/ @P0 LEA.HI.X.SX32 R7, R7, c[0x0][0x164], 0x1, P2 ; /* 0x0000590007070a11 */
/* 0x000fca00010f0eff */
/*0770*/ @P0 LDG.E.U8 R6, [R6.64] ; /* 0x0000000806060981 */
/* 0x000f62000c1e1100 */
/*0780*/ I2F.U16 R9, R4 ; /* 0x0000000400097306 */
/* 0x010ef00000101000 */
/*0790*/ @P0 I2F.U16 R11, R6 ; /* 0x00000006000b0306 */
/* 0x020ea20000101000 */
/*07a0*/ FFMA R18, R9, R8, R18 ; /* 0x0000000809127223 */
/* 0x008fc80000000012 */
/*07b0*/ @P0 FFMA R18, R11, R10, R18 ; /* 0x0000000a0b120223 */
/* 0x004fc60000000012 */
/*07c0*/ @!P1 BRA 0x1c0 ; /* 0xfffff9f000009947 */
/* 0x000fea000383ffff */
/*07d0*/ F2I.U32.TRUNC.NTZ R5, R18 ; /* 0x0000001200057305 */
/* 0x000e22000020f000 */
/*07e0*/ IMAD R0, R13, c[0x3][0x0], R0 ; /* 0x00c000000d007a24 */
/* 0x000fca00078e0200 */
/*07f0*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc80007f1e0ff */
/*0800*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f0eff */
/*0810*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101108 */
/*0820*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0830*/ BRA 0x830; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20gaussian_calc_kernelPhS_Pf
.globl _Z20gaussian_calc_kernelPhS_Pf
.p2align 8
.type _Z20gaussian_calc_kernelPhS_Pf,@function
_Z20gaussian_calc_kernelPhS_Pf:
s_load_b32 s6, s[0:1], 0x24
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, height_d@rel32@lo+4
s_addc_u32 s3, s3, height_d@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, width_d@rel32@lo+4
s_addc_u32 s5, s5, width_d@rel32@hi+12
s_load_b32 s12, s[2:3], 0x0
s_load_b32 s10, s[4:5], 0x0
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s6, 16
s_and_b32 s2, s6, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
s_mul_i32 s14, s14, s2
v_add_nc_u32_e32 v1, s14, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s12, v0
v_cmp_gt_i32_e64 s2, s10, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, order_d@rel32@lo+4
s_addc_u32 s3, s3, order_d@rel32@hi+12
s_load_b32 s11, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s11, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_add_i32 s6, s11, -1
s_add_i32 s12, s12, -1
s_lshr_b32 s7, s6, 31
s_add_i32 s13, s10, -1
s_add_i32 s6, s6, s7
s_mov_b32 s7, 0
s_ashr_i32 s6, s6, 1
v_mov_b32_e32 v4, 0
v_subrev_nc_u32_e32 v2, s6, v0
s_sub_i32 s6, s14, s6
s_mov_b32 s14, s7
v_add_nc_u32_e32 v3, s6, v3
s_mov_b32 s6, s7
.p2align 6
.LBB0_3:
v_add_nc_u32_e32 v5, s14, v2
s_lshl_b64 s[8:9], s[6:7], 2
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
v_minmax_i32 v5, v5, s12, 0
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s10
.p2align 6
.LBB0_4:
v_add_nc_u32_e32 v6, s15, v3
s_load_b32 s16, s[8:9], 0x0
s_add_i32 s15, s15, 1
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
v_minmax_i32 v6, v6, s13, 0
s_cmp_eq_u32 s11, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, v6, v5
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_u8 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v4, s16, v6
s_cbranch_scc0 .LBB0_4
s_add_i32 s14, s14, 1
s_add_i32 s6, s6, s11
s_cmp_eq_u32 s14, s11
s_cbranch_scc0 .LBB0_3
v_cvt_i32_f32_e32 v2, v4
s_branch .LBB0_8
.LBB0_7:
v_mov_b32_e32 v2, 0
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s10, v[1:2]
v_ashrrev_i32_e32 v1, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20gaussian_calc_kernelPhS_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20gaussian_calc_kernelPhS_Pf, .Lfunc_end0-_Z20gaussian_calc_kernelPhS_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected width_d
.type width_d,@object
.section .bss,"aw",@nobits
.globl width_d
.p2align 2, 0x0
width_d:
.long 0
.size width_d, 4
.protected height_d
.type height_d,@object
.globl height_d
.p2align 2, 0x0
height_d:
.long 0
.size height_d, 4
.protected order_d
.type order_d,@object
.globl order_d
.p2align 2, 0x0
order_d:
.long 0
.size order_d, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym width_d
.addrsig_sym height_d
.addrsig_sym order_d
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20gaussian_calc_kernelPhS_Pf
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z20gaussian_calc_kernelPhS_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00049bb2_00000000-6_gaussian_blur_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wb"
.LC1:
.string "Error: cannot open file %s"
.LC2:
.string "P5\n%d %d\n255\n"
.text
.globl _Z14write_gaussianPcPhii
.type _Z14write_gaussianPcPhii, @function
_Z14write_gaussianPcPhii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %r12d
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L6
movq %rax, %rbp
movl %r12d, %r8d
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
imull %r12d, %ebx
movslq %ebx, %rdx
movq %rbp, %rcx
movl $1, %esi
movq %r13, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movq %r14, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z14write_gaussianPcPhii, .-_Z14write_gaussianPcPhii
.globl _Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf
.type _Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf, @function
_Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20gaussian_calc_kernelPhS_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf, .-_Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf
.globl _Z20gaussian_calc_kernelPhS_Pf
.type _Z20gaussian_calc_kernelPhS_Pf, @function
_Z20gaussian_calc_kernelPhS_Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z20gaussian_calc_kernelPhS_Pf, .-_Z20gaussian_calc_kernelPhS_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/cwdaggs/gaussian/main/gaussian_blur_cuda.cu"
.section .rodata.str1.1
.LC4:
.string "CudaErr: %s (%s:%d)\n"
.text
.globl _Z13gaussian_calcPhS_Pfiii
.type _Z13gaussian_calcPhS_Pfiii, @function
_Z13gaussian_calcPhS_Pfiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rsi, %r12
movq %rdx, %rbp
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
imull %r9d, %r9d
movslq %r9d, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
movl 12(%rsp), %esi
imull 8(%rsp), %esi
movslq %esi, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
movl 12(%rsp), %esi
imull 8(%rsp), %esi
movslq %esi, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
movl 4(%rsp), %edx
imull %edx, %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L34
movl 12(%rsp), %edx
imull 8(%rsp), %edx
movslq %edx, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L35
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL7width_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L36
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL8height_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L37
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL7order_d(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
jne .L38
movl 12(%rsp), %eax
leal 778(%rax), %eax
movl $2822879661, %edx
imulq %rdx, %rax
shrq $41, %rax
movl %eax, 60(%rsp)
movl 8(%rsp), %eax
movl %eax, 64(%rsp)
movl $779, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L24:
movl 12(%rsp), %edx
imull 8(%rsp), %edx
movslq %edx, %rdx
movl $2, %ecx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L40
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L41
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L42
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L43
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $53, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $54, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $55, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $58, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $59, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $60, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $61, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $62, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z44__device_stub__Z20gaussian_calc_kernelPhS_PfPhS_Pf
jmp .L24
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $70, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $73, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $74, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $75, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z13gaussian_calcPhS_Pfiii, .-_Z13gaussian_calcPhS_Pfiii
.section .rodata.str1.8
.align 8
.LC6:
.string "Usage: %s <input_pgm> <output_pgm> <sigma>\n"
.section .rodata.str1.1
.LC7:
.string "rb"
.LC8:
.string "%*[^\n]\n"
.LC9:
.string "%d %d\n"
.LC10:
.string "Error: invalid sigma value"
.section .rodata.str1.8
.align 8
.LC15:
.string "Error: sigma value too big for image size"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jle .L76
movq 8(%rsi), %rdi
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L77
movq 16(%rbx), %rax
movq %rax, 40(%rsp)
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
jne .L78
leaq 68(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
jne .L79
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L80
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
pxor %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
movss %xmm1, (%rsp)
pxor %xmm0, %xmm0
comiss %xmm1, %xmm0
jnb .L81
movss (%rsp), %xmm0
mulss .LC11(%rip), %xmm0
movaps %xmm0, %xmm2
movss .LC18(%rip), %xmm3
movaps %xmm0, %xmm1
andps %xmm3, %xmm1
movss .LC12(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L53
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm2
movss .LC14(%rip), %xmm4
andps %xmm4, %xmm2
addss %xmm1, %xmm2
andnps %xmm0, %xmm3
orps %xmm3, %xmm2
.L53:
movss %xmm2, 4(%rsp)
cvttss2sil %xmm2, %eax
testb $1, %al
jne .L54
addss .LC14(%rip), %xmm2
movss %xmm2, 4(%rsp)
.L54:
movl 64(%rsp), %ebx
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movss 4(%rsp), %xmm2
comiss %xmm0, %xmm2
ja .L55
movl 68(%rsp), %r12d
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
comiss %xmm0, %xmm2
ja .L55
cvttss2sil 4(%rsp), %esi
movl %esi, 28(%rsp)
imull %esi, %esi
movslq %esi, %rsi
salq $2, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, 32(%rsp)
imull %r12d, %ebx
movslq %ebx, %rbx
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, %r14
movq %rax, 48(%rsp)
movq %rbx, %rsi
movl $64, %edi
call aligned_alloc@PLT
movq %rax, 56(%rsp)
movq %rbp, %r8
movq %rbx, %rcx
movl $1, %edx
movq %rbx, %rsi
movq %r14, %rdi
call __fread_chk@PLT
movq %rax, %rdx
movl 68(%rsp), %eax
imull 64(%rsp), %eax
cltq
cmpq %rdx, %rax
jne .L82
movq %rbp, %rdi
call fclose@PLT
pxor %xmm0, %xmm0
movss 4(%rsp), %xmm3
comiss %xmm0, %xmm3
jbe .L59
movaps %xmm3, %xmm0
mulss .LC16(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC18(%rip), %xmm1
movaps %xmm0, %xmm2
andps %xmm1, %xmm2
movss .LC12(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L61
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
andnps %xmm0, %xmm1
movaps %xmm2, %xmm3
orps %xmm1, %xmm3
.L61:
movss %xmm3, 24(%rsp)
movss (%rsp), %xmm4
movaps %xmm4, %xmm0
addss %xmm4, %xmm0
mulss %xmm4, %xmm0
pxor %xmm3, %xmm3
cvtss2sd %xmm0, %xmm3
movsd %xmm3, 16(%rsp)
movslq 28(%rsp), %r15
salq $2, %r15
movq 32(%rsp), %r12
movq %r12, %rbp
movl %r13d, %r14d
movl $0x00000000, (%rsp)
pxor %xmm0, %xmm0
.L62:
subss 24(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, 8(%rsp)
movl $1, %ebx
pxor %xmm0, %xmm0
.L63:
subss 24(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
addsd 8(%rsp), %xmm0
xorpd .LC17(%rip), %xmm0
divsd 16(%rsp), %xmm0
call exp@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -4(%r12,%rbx,4)
addss (%rsp), %xmm0
movss %xmm0, (%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
addq $1, %rbx
movss 4(%rsp), %xmm3
comiss %xmm0, %xmm3
ja .L63
addl $1, %r14d
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
addq %r15, %r12
comiss %xmm0, %xmm3
ja .L62
.L64:
movl $1, %eax
.L66:
movss -4(%rbp,%rax,4), %xmm0
divss (%rsp), %xmm0
movss %xmm0, -4(%rbp,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addq $1, %rax
movss 4(%rsp), %xmm2
comiss %xmm0, %xmm2
ja .L66
addl $1, %r13d
addq %r15, %rbp
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
comiss %xmm0, %xmm2
ja .L64
.L59:
movl 28(%rsp), %r9d
movl 68(%rsp), %r8d
movl 64(%rsp), %ecx
movq 32(%rsp), %r14
movq %r14, %rdx
movq 56(%rsp), %rbx
movq %rbx, %rsi
movq 48(%rsp), %r15
movq %r15, %rdi
call _Z13gaussian_calcPhS_Pfiii
movl 68(%rsp), %ecx
movl 64(%rsp), %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call _Z14write_gaussianPcPhii
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L83
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
movq 8(%rbx), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L78:
movl $1, %edi
call exit@PLT
.L79:
movl $1, %edi
call exit@PLT
.L80:
movl $1, %edi
call exit@PLT
.L81:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L82:
movl $1, %edi
call exit@PLT
.L83:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC19:
.string "_Z20gaussian_calc_kernelPhS_Pf"
.section .rodata.str1.1
.LC20:
.string "width_d"
.LC21:
.string "height_d"
.LC22:
.string "order_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z20gaussian_calc_kernelPhS_Pf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7width_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8height_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7order_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7order_d
.comm _ZL7order_d,4,4
.local _ZL8height_d
.comm _ZL8height_d,4,4
.local _ZL7width_d
.comm _ZL7width_d,4,4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1086324736
.align 4
.LC12:
.long 1258291200
.align 4
.LC14:
.long 1065353216
.align 4
.LC16:
.long 1056964608
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC17:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC18:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gaussian_blur_cuda.hip"
.globl _Z35__device_stub__gaussian_calc_kernelPhS_Pf # -- Begin function _Z35__device_stub__gaussian_calc_kernelPhS_Pf
.p2align 4, 0x90
.type _Z35__device_stub__gaussian_calc_kernelPhS_Pf,@function
_Z35__device_stub__gaussian_calc_kernelPhS_Pf: # @_Z35__device_stub__gaussian_calc_kernelPhS_Pf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20gaussian_calc_kernelPhS_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__gaussian_calc_kernelPhS_Pf, .Lfunc_end0-_Z35__device_stub__gaussian_calc_kernelPhS_Pf
.cfi_endproc
# -- End function
.globl _Z13gaussian_calcPhS_Pfiii # -- Begin function _Z13gaussian_calcPhS_Pfiii
.p2align 4, 0x90
.type _Z13gaussian_calcPhS_Pfiii,@function
_Z13gaussian_calcPhS_Pfiii: # @_Z13gaussian_calcPhS_Pfiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
# kill: def $r9d killed $r9d def $r9
movq %rdx, %r15
movq %rsi, %rbx
movq %rdi, %r14
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, 12(%rsp)
imull %r9d, %r9d
leaq (,%r9,4), %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z11_cuda_check10hipError_tPKci.exit
movslq 8(%rsp), %rax
movslq 4(%rsp), %rsi
imulq %rax, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z11_cuda_check10hipError_tPKci.exit10
movslq 8(%rsp), %rax
movslq 4(%rsp), %rsi
imulq %rax, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z11_cuda_check10hipError_tPKci.exit12
movq 32(%rsp), %rdi
movl 12(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z11_cuda_check10hipError_tPKci.exit14
movq 24(%rsp), %rdi
movslq 8(%rsp), %rax
movslq 4(%rsp), %rdx
imulq %rax, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z11_cuda_check10hipError_tPKci.exit16
leaq 8(%rsp), %rsi
movl $width_d, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z11_cuda_check10hipError_tPKci.exit18
leaq 4(%rsp), %rsi
movl $height_d, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z11_cuda_check10hipError_tPKci.exit20
leaq 12(%rsp), %rsi
movl $order_d, %edi
movl $4, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z11_cuda_check10hipError_tPKci.exit22
movl $778, %eax # imm = 0x30A
addl 8(%rsp), %eax
movl $2822879661, %ecx # imm = 0xA841B9AD
imulq %rax, %rcx
shrq $41, %rcx
movl 4(%rsp), %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $4294968075, %rdx # imm = 0x10000030B
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_19
# %bb.18:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20gaussian_calc_kernelPhS_Pf, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_19:
movq 16(%rsp), %rsi
movslq 8(%rsp), %rax
movslq 4(%rsp), %rdx
imulq %rax, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z11_cuda_check10hipError_tPKci.exit24
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_22
# %bb.23: # %_Z11_cuda_check10hipError_tPKci.exit26
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_24
# %bb.25: # %_Z11_cuda_check10hipError_tPKci.exit28
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_26
# %bb.27: # %_Z11_cuda_check10hipError_tPKci.exit30
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $55, %r8d
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $56, %r8d
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $57, %r8d
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $60, %r8d
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $61, %r8d
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $62, %r8d
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $63, %r8d
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $64, %r8d
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %r8d
jmp .LBB1_2
.LBB1_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $75, %r8d
jmp .LBB1_2
.LBB1_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $76, %r8d
jmp .LBB1_2
.LBB1_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $77, %r8d
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z13gaussian_calcPhS_Pfiii, .Lfunc_end1-_Z13gaussian_calcPhS_Pfiii
.cfi_endproc
# -- End function
.globl _Z14write_gaussianPcPhii # -- Begin function _Z14write_gaussianPcPhii
.p2align 4, 0x90
.type _Z14write_gaussianPcPhii,@function
_Z14write_gaussianPcPhii: # @_Z14write_gaussianPcPhii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r14d
movq %rsi, %rbx
movq %rdi, %r12
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB2_1
# %bb.2:
movq %rax, %r15
movl $.L.str.3, %esi
movq %rax, %rdi
movl %r14d, %edx
movl %ebp, %ecx
xorl %eax, %eax
callq fprintf
imull %r14d, %ebp
movslq %ebp, %rdx
movl $1, %esi
movq %rbx, %rdi
movq %r15, %rcx
callq fwrite
movq %r15, %rdi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB2_1:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rdi
movl $.L.str.2, %esi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14write_gaussianPcPhii, .Lfunc_end2-_Z14write_gaussianPcPhii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x40c00000 # float 6
.LCPI3_1:
.long 0x3f800000 # float 1
.LCPI3_2:
.long 0x3f000000 # float 0.5
.LCPI3_4:
.long 0x00000000 # float 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_3:
.quad 0x8000000000000000 # double -0
.quad 0x8000000000000000 # double -0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
cmpl $3, %edi
jle .LBB3_1
# %bb.3:
movq 8(%r14), %rdi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB3_4
# %bb.5:
movq %rax, %r13
movq 16(%r14), %r15
movl $.L.str.6, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
jne .LBB3_30
# %bb.6:
leaq 12(%rsp), %rdx
leaq 8(%rsp), %rcx
movl $.L.str.7, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $2, %eax
jne .LBB3_30
# %bb.7:
movl $.L.str.6, %esi
movq %r13, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
testl %eax, %eax
jne .LBB3_30
# %bb.8:
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm1
xorps %xmm0, %xmm0
ucomiss %xmm1, %xmm0
jae .LBB3_9
# %bb.11:
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm1, 20(%rsp) # 4-byte Spill
mulss %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
testb $1, %al
jne .LBB3_13
# %bb.12:
addss .LCPI3_1(%rip), %xmm0
.LBB3_13:
movl 12(%rsp), %ebx
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
ucomiss %xmm1, %xmm0
ja .LBB3_15
# %bb.14:
movl 8(%rsp), %ebp
xorps %xmm1, %xmm1
cvtsi2ss %ebp, %xmm1
ucomiss %xmm1, %xmm0
ja .LBB3_15
# %bb.16:
movq %r15, 48(%rsp) # 8-byte Spill
cvttss2si %xmm0, %r14d
movl %r14d, %esi
imull %esi, %esi
shlq $2, %rsi
movl $64, %edi
movss %xmm0, 16(%rsp) # 4-byte Spill
callq aligned_alloc
movq %rax, 24(%rsp) # 8-byte Spill
imull %ebx, %ebp
movslq %ebp, %rbx
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r15
movl $64, %edi
movq %rbx, %rsi
callq aligned_alloc
movq %rax, %r12
movl $1, %esi
movq %r15, 40(%rsp) # 8-byte Spill
movq %r15, %rdi
movq %rbx, %rdx
movq %r13, %rcx
callq fread
movslq 8(%rsp), %rcx
movslq 12(%rsp), %rdx
imulq %rcx, %rdx
cmpq %rdx, %rax
jne .LBB3_30
# %bb.17:
movq %r13, %rdi
callq fclose
xorps %xmm0, %xmm0
movss 16(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
movl %r14d, 32(%rsp) # 4-byte Spill
movslq %r14d, %rbx
xorps %xmm3, %xmm3
movaps %xmm1, %xmm2
jbe .LBB3_23
# %bb.18: # %.preheader77.lr.ph
movss .LCPI3_2(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
callq floorf@PLT
movss 16(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movaps %xmm0, %xmm4
movss 20(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movaps %xmm1, %xmm0
addss %xmm1, %xmm0
mulss %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
leaq (,%rbx,4), %r13
xorl %r14d, %r14d
movapd .LCPI3_3(%rip), %xmm5 # xmm5 = [-0.0E+0,-0.0E+0]
movq 24(%rsp), %rbp # 8-byte Reload
xorps %xmm0, %xmm0
xorps %xmm3, %xmm3
movss %xmm4, 36(%rsp) # 4-byte Spill
movsd %xmm1, 56(%rsp) # 8-byte Spill
jmp .LBB3_19
.p2align 4, 0x90
.LBB3_22: # %._crit_edge
# in Loop: Header=BB3_19 Depth=1
incq %r14
xorps %xmm0, %xmm0
cvtsi2ss %r14d, %xmm0
addq %r13, %rbp
ucomiss %xmm0, %xmm2
jbe .LBB3_23
.LBB3_19: # %.preheader77
# =>This Loop Header: Depth=1
# Child Loop BB3_21 Depth 2
ucomiss .LCPI3_4(%rip), %xmm2
jbe .LBB3_22
# %bb.20: # %.lr.ph
# in Loop: Header=BB3_19 Depth=1
subss %xmm4, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, 64(%rsp) # 8-byte Spill
xorpd %xmm0, %xmm0
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_21: # Parent Loop BB3_19 Depth=1
# => This Inner Loop Header: Depth=2
movss %xmm3, 20(%rsp) # 4-byte Spill
subss %xmm4, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm0, %xmm0
addsd 64(%rsp), %xmm0 # 8-byte Folded Reload
xorpd %xmm5, %xmm0
divsd %xmm1, %xmm0
callq exp
movapd .LCPI3_3(%rip), %xmm5 # xmm5 = [-0.0E+0,-0.0E+0]
movss 36(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 20(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
movss %xmm1, (%rbp,%r15,4)
incq %r15
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
addss %xmm1, %xmm3
movsd 56(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
ucomiss %xmm0, %xmm2
ja .LBB3_21
jmp .LBB3_22
.LBB3_23: # %.preheader76
ucomiss .LCPI3_4(%rip), %xmm2
movq 48(%rsp), %r14 # 8-byte Reload
jbe .LBB3_29
# %bb.24: # %.preheader.lr.ph
shlq $2, %rbx
xorl %eax, %eax
xorps %xmm0, %xmm0
movq 24(%rsp), %rcx # 8-byte Reload
jmp .LBB3_25
.p2align 4, 0x90
.LBB3_28: # %._crit_edge85
# in Loop: Header=BB3_25 Depth=1
incq %rax
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
addq %rbx, %rcx
ucomiss %xmm1, %xmm2
jbe .LBB3_29
.LBB3_25: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_27 Depth 2
ucomiss %xmm0, %xmm2
jbe .LBB3_28
# %bb.26: # %.lr.ph84
# in Loop: Header=BB3_25 Depth=1
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_27: # Parent Loop BB3_25 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm3, %xmm1
movss %xmm1, (%rcx,%rdx,4)
incq %rdx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
ucomiss %xmm1, %xmm2
ja .LBB3_27
jmp .LBB3_28
.LBB3_29: # %._crit_edge87
movl 12(%rsp), %ecx
movl 8(%rsp), %r8d
movq 40(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq %r12, %rsi
movq 24(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdx
movl 32(%rsp), %r9d # 4-byte Reload
callq _Z13gaussian_calcPhS_Pfiii
movl 12(%rsp), %edx
movl 8(%rsp), %ecx
movq %r14, %rdi
movq %r12, %rsi
callq _Z14write_gaussianPcPhii
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_30:
.cfi_def_cfa_offset 128
movl $1, %edi
callq exit
.LBB3_15:
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $41, %esi
jmp .LBB3_10
.LBB3_1:
movq stderr(%rip), %rdi
movq (%r14), %rdx
movl $.L.str.4, %esi
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rdi
movq 8(%r14), %rdx
movl $.L.str.2, %esi
.LBB3_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB3_9:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $26, %esi
.LBB3_10:
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20gaussian_calc_kernelPhS_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $width_d, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $height_d, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $order_d, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type width_d,@object # @width_d
.local width_d
.comm width_d,4,4
.type height_d,@object # @height_d
.local height_d
.comm height_d,4,4
.type order_d,@object # @order_d
.local order_d
.comm order_d,4,4
.type _Z20gaussian_calc_kernelPhS_Pf,@object # @_Z20gaussian_calc_kernelPhS_Pf
.section .rodata,"a",@progbits
.globl _Z20gaussian_calc_kernelPhS_Pf
.p2align 3, 0x0
_Z20gaussian_calc_kernelPhS_Pf:
.quad _Z35__device_stub__gaussian_calc_kernelPhS_Pf
.size _Z20gaussian_calc_kernelPhS_Pf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/cwdaggs/gaussian/main/gaussian_blur_cuda.hip"
.size .L.str, 102
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "wb"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error: cannot open file %s"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "P5\n%d %d\n255\n"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Usage: %s <input_pgm> <output_pgm> <sigma>\n"
.size .L.str.4, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "rb"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%*[^\n]\n"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d %d\n"
.size .L.str.7, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error: invalid sigma value"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Error: sigma value too big for image size"
.size .L.str.9, 42
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "CudaErr: %s (%s:%d)\n"
.size .L.str.10, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20gaussian_calc_kernelPhS_Pf"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "width_d"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "height_d"
.size .L__unnamed_3, 9
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "order_d"
.size .L__unnamed_4, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__gaussian_calc_kernelPhS_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym width_d
.addrsig_sym height_d
.addrsig_sym order_d
.addrsig_sym _Z20gaussian_calc_kernelPhS_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <pthread.h>
#include <stdint.h>
#include <ctype.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <sys/time.h>
#include <malloc.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <time.h>
#define REPS 1
void SortChunkI(long ChunkSize, int Chunk_ID, signed int *ary);
void SortChunkL(long ChunkSize, int Chunk_ID, signed long long *ary);
void SortChunkF(long ChunkSize, int Chunk_ID, float *ary);
void SortChunkD(long ChunkSize, int Chunk_ID, double *ary);
void MergeSortI(signed int *list, long length);
void MergeSortL(signed long long *list, long length);
void MergeSortF(float *list, long length);
void MergeSortD(double *list, long length);
__global__ void SortChunkGI(signed int ary[], long ChunkSize)
{
unsigned long i,j;
unsigned long sp;
int temp;
sp = (blockIdx.x * blockDim.x +threadIdx.x)*ChunkSize;
printf("\n start:%li end:%li Chunksize: %li S_ary: %i E_ary:%i\n",sp,ChunkSize+sp-1,ChunkSize,ary[sp],ary[ChunkSize+sp-1]);
for(i = 0; i< ChunkSize; i++)
{
for(j = sp; j< (ChunkSize+sp-1-i); j++)
{
if( (ary[j]) > (ary[j+1]))
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
}
__global__ void SortChunkGL(signed long long ary[], long ChunkSize)
{
unsigned long i,j;
unsigned long sp;
long long temp;
sp = (blockIdx.x * blockDim.x +threadIdx.x)*ChunkSize;
//printf("\n start:%li end:%li Chunksize: %li S_ary: %i E_ary:%i\n",sp,ChunkSize+sp-1,ChunkSize,ary[sp],ary[ChunkSize+sp-1]);
for(i = 0; i< ChunkSize; i++)
{
for(j = sp; j< (ChunkSize+sp-1-i); j++)
{
if( (ary[j]) > (ary[j+1]))
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
}
__global__ void SortChunkGF(float ary[], long ChunkSize)
{
unsigned long i,j;
unsigned long sp;
float temp;
sp = (blockIdx.x * blockDim.x +threadIdx.x)*ChunkSize;
printf("\n start:%li end:%li Chunksize: %li S_ary: %i E_ary:%i\n",sp,ChunkSize+sp-1,ChunkSize,ary[sp],ary[ChunkSize+sp-1]);
for(i = 0; i< ChunkSize; i++)
{
for(j = sp; j< (ChunkSize+sp-1-i); j++)
{
if( (ary[j]) > (ary[j+1]))
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
}
__global__ void SortChunkGD(double ary[], long ChunkSize)
{
unsigned long i,j;
unsigned long sp;
double temp;
sp = (blockIdx.x * blockDim.x +threadIdx.x)*ChunkSize;
printf("\n start:%li end:%li Chunksize: %li S_ary: %i E_ary:%i\n",sp,ChunkSize+sp-1,ChunkSize,ary[sp],ary[ChunkSize+sp-1]);
for(i = 0; i< ChunkSize; i++)
{
for(j = sp; j< (ChunkSize+sp-1-i); j++)
{
if( (ary[j]) > (ary[j+1]))
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
}
int main(int argc, char** argv)
{
//**************** HOST variable ******************
struct timeval t;
double StartTime, EndTime;
double TimeElapsed;
long a,i;
long NumOfChunk;
long HowMany;
long ChunkSize;
char Type;
signed int *InputArrayI,*SortedArrayI;
signed long long *InputArrayL,*SortedArrayL;
float *InputArrayF,*SortedArrayF;
double *InputArrayD,*SortedArrayD;
long BlockSize;
long NumOfBlock;
//**************** GPU variable ******************
signed int *InputArrayG_I,*SortedArrayG_I;
signed long long *InputArrayG_L,*SortedArrayG_L;
float *InputArrayG_F,*SortedArrayG_F;
double *InputArrayG_D,*SortedArrayG_D;
FILE *ff = fopen("BubbleSortResult.txt", "w");
FILE *fp = fopen("MergeSortResult.txt", "w");
if(argc != 5)
{
printf("\n Argument is not correct \n\n");
printf("Nothing executed ... Exiting ...\n\n");
exit(EXIT_FAILURE);
}
HowMany = atoi(argv[1]);
ChunkSize = atoi(argv[3]);
Type = toupper(argv[2][0]);
BlockSize = atoi(argv[4]);
NumOfChunk = HowMany/(ChunkSize);
NumOfBlock = HowMany/((ChunkSize * BlockSize));
printf("\nElement type : %c\n",Type);
printf("BlockSize : %li\n",BlockSize);
printf("\nNumberOfChunk : %li\n",NumOfChunk);
printf("Total Block : %li\n",NumOfBlock);
printf("Total Element : %li\n\n\n\n",NumOfBlock*ChunkSize*BlockSize);
srand(time(NULL));
// HOST*************inital rand number
switch(Type)
{
case 'I':
InputArrayI = (signed int *)malloc(HowMany * sizeof(signed int));
SortedArrayI = (signed int *)malloc(HowMany * sizeof(signed int));
for(i=0;i<HowMany;i++)
{
InputArrayI[i] = ( ((-1)^i)*rand() );
}
break;
//*******************************************
case 'L':
InputArrayL = (signed long long *)malloc(HowMany * sizeof(signed long long ));
SortedArrayL = (signed long long *)malloc(HowMany * sizeof(signed long long ));
for(i=0;i<HowMany;i++)
{
InputArrayL[i] =(long long )( ((-1)^i)*rand()<<32 | rand() );
}
break;
//*******************************************
case 'F':
InputArrayF = (float *)malloc(HowMany * sizeof(float));
SortedArrayF = (float *)malloc(HowMany * sizeof(float));
int my_random_int;
for(i=0;i<HowMany;i++)
{
my_random_int = ((-1)^i)*rand() ;
InputArrayF[i] = *(float*)&my_random_int;
if(isnan(InputArrayF[i])){i--;}
}
break;
//*******************************************
case 'D':
InputArrayD = (double *)malloc(HowMany * sizeof(double));
SortedArrayD = (double *)malloc(HowMany * sizeof(double));
long long int my_random_long;
for(i=0;i<HowMany;i++)
{
my_random_long = (long long )(( ((-1)^i)*rand()<<32) | rand() );
InputArrayD[i] = *(double*)&my_random_long;
if(isnan(InputArrayD[i])){i--;}
}
break;
}
// GPU*********** inital GPU and transfer data HtoD
switch(Type)
{
case 'I':
cudaMalloc ((signed int **)&InputArrayG_I, HowMany*sizeof(signed int));
cudaMalloc ((signed int **)&SortedArrayG_I, HowMany*sizeof(signed int));
cudaMemcpy (InputArrayG_I, InputArrayI, HowMany*sizeof(signed int), cudaMemcpyHostToDevice);
cudaMemcpy (SortedArrayG_I, InputArrayI, HowMany*sizeof(signed int), cudaMemcpyHostToDevice);
break;
//*******************************************
case 'L':
cudaMalloc ((signed long long **)&InputArrayG_L, HowMany* sizeof(signed long long ));
cudaMalloc ((signed long long **)&SortedArrayG_L, HowMany* sizeof(signed long long ));
cudaMemcpy (InputArrayG_L, InputArrayL, HowMany, cudaMemcpyHostToDevice);
cudaMemcpy (SortedArrayG_L, InputArrayL, HowMany*sizeof(signed int), cudaMemcpyHostToDevice);
break;
//*******************************************
case 'F':
cudaMalloc ((float **)&InputArrayG_F, HowMany);
cudaMalloc ((float **)&SortedArrayG_F, HowMany);
cudaMemcpy (InputArrayG_F, InputArrayF, HowMany, cudaMemcpyHostToDevice);
cudaMemcpy (SortedArrayG_F, InputArrayF, HowMany*sizeof(signed int), cudaMemcpyHostToDevice);
break;
//*******************************************
case 'D':
cudaMalloc ((double **)&InputArrayG_D, HowMany);
cudaMalloc ((double **)&SortedArrayG_D, HowMany);
cudaMemcpy (InputArrayG_D, InputArrayD, HowMany, cudaMemcpyHostToDevice);
cudaMemcpy (SortedArrayG_D, InputArrayD, HowMany*sizeof(signed int), cudaMemcpyHostToDevice);
break;
}
gettimeofday(&t, NULL);
StartTime = (double)t.tv_sec*1000000.0 + ((double)t.tv_usec);
//******************* sort ***************
for(a=0; a<REPS; a++)
{
switch(Type)
{
case 'I':
// tot block element per block
SortChunkGI<<< NumOfBlock, BlockSize>>> (SortedArrayG_I,ChunkSize);
cudaMemcpy (SortedArrayI, SortedArrayG_I, HowMany*sizeof(signed int), cudaMemcpyDeviceToHost);
fprintf(ff, "Bubble sorted result of int done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(ff, "%i \n", SortedArrayI[i]);
if((i+1)%ChunkSize ==0){fprintf(ff, " \n");}
}
MergeSortI(SortedArrayI, HowMany);
break;
//*******************************************
case 'L':
// tot block element per block
SortChunkGL<<< NumOfBlock, BlockSize>>> (SortedArrayG_L,ChunkSize);
cudaMemcpy (SortedArrayL, SortedArrayG_L, HowMany*sizeof(signed long long), cudaMemcpyDeviceToHost);
fprintf(ff, "Bubble sorted result of long done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(ff, "%lli \n", SortedArrayL[i]);
if((i+1)%ChunkSize ==0){fprintf(ff, " \n");}
}
MergeSortL(SortedArrayL, HowMany);
break;
//*******************************************
case 'F':
// tot block element per block
SortChunkGF<<< NumOfBlock, BlockSize>>> (SortedArrayG_F,ChunkSize);
cudaMemcpy (SortedArrayF, SortedArrayG_F, HowMany*sizeof(float), cudaMemcpyDeviceToHost);
fprintf(ff, "Bubble sorted result of float done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(ff, "%f \n", SortedArrayF[i]);
if((i+1)%ChunkSize ==0){fprintf(ff, " \n");}
}
MergeSortF(SortedArrayF, HowMany);
break;
//*******************************************
case 'D':
// tot block element per block
SortChunkGD<<< NumOfBlock, BlockSize>>> (SortedArrayG_D,ChunkSize);
cudaMemcpy (SortedArrayD, SortedArrayG_D, HowMany*sizeof(double), cudaMemcpyDeviceToHost);
fprintf(ff, "Bubble sorted result of double done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(ff, "%lf \n", InputArrayD[i]);
if((i+1)%ChunkSize ==0){fprintf(ff, " \n");}
}
MergeSortD(SortedArrayD, HowMany);
break;
}
}
gettimeofday(&t, NULL);
EndTime = (double)t.tv_sec*1000000.0 + ((double)t.tv_usec);
TimeElapsed=(EndTime-StartTime)/1000.00;
TimeElapsed/=(double)REPS;
printf("\n\nExecution time:%10.4f ms ",TimeElapsed);
// print result
switch(Type)
{
case 'I':
fprintf(fp, "Merge sorted result of int done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(fp, "%i \n", SortedArrayI[i]);
}
break;
//*******************************************
case 'L':
fprintf(fp, "Merge sorted result of long done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(fp, "%lli \n", SortedArrayL[i]);
}
break;
//*******************************************
case 'F':
fprintf(fp, "Merge sorted result of float done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(fp, "%f \n", SortedArrayF[i]);
}
break;
//******************************************
case 'D':
fprintf(fp, "Merge sorted result of double done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(fp, "%lf \n", SortedArrayD[i]);
}
break;
}
//free memoary
switch(Type)
{
case 'I':
free(InputArrayI);
free(SortedArrayI);
cudaFree(InputArrayG_I);
cudaFree(SortedArrayG_I);
break;
//*******************************************
case 'L':
free(InputArrayL);
free(SortedArrayL);
cudaFree(InputArrayG_L);
cudaFree(SortedArrayG_L);
break;
//*******************************************
case 'F':
free(InputArrayF);
free(SortedArrayF);
cudaFree(InputArrayG_F);
cudaFree(SortedArrayG_F);
break;
//*******************************************
case 'D':
free(InputArrayD);
free(SortedArrayD);
cudaFree(InputArrayG_D);
cudaFree(SortedArrayG_D);
break;
}
fclose(ff);
fclose(fp);
return (EXIT_SUCCESS);
}
//************** bubble sort HOST****************
void SortChunkI(long ChunkSize, int Chunk_ID, signed int *ary)
{
long i,j;
long sp;
int temp;
sp = Chunk_ID * ChunkSize;
for(i = 0; i< (ChunkSize-1); i++)
{
for(j = sp; j< ((ChunkSize+sp)-1-i); j++)
{
if(ary[j] > ary[j+1])
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
for(i = sp; i< (ChunkSize+sp); i++)
{
printf("\n %i",ary[i]);
}
printf("\n \n");
return;
}
void SortChunkL(long ChunkSize, int Chunk_ID, signed long long *ary)
{
long i,j;
long sp;
long long temp;
sp = Chunk_ID * ChunkSize;
for(i = 0; i< (ChunkSize-1); i++)
{
for(j = sp; j< ((ChunkSize+sp)-1-i); j++)
{
if(ary[j] > ary[j+1])
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
for(i = sp; i< (ChunkSize+sp); i++)
{
printf("\n %lli",ary[i]);
}
printf("\n \n");
return;
}
void SortChunkF(long ChunkSize, int Chunk_ID, float *ary)
{
long i,j;
long sp;
float temp;
sp = Chunk_ID * ChunkSize;
for(i = 0; i< (ChunkSize-1); i++)
{
for(j = sp; j< ((ChunkSize+sp)-1-i); j++)
{
if(ary[j] > ary[j+1])
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
for(i = sp; i< (ChunkSize+sp); i++)
{
printf("\n %f",ary[i]);
}
printf("\n \n");
return;
}
void SortChunkD(long ChunkSize, int Chunk_ID, double *ary)
{
long i,j;
long sp;
double temp;
sp = Chunk_ID * ChunkSize;
for(i = 0; i< (ChunkSize-1); i++)
{
for(j = sp; j< ((ChunkSize+sp)-1-i); j++)
{
if(ary[j] > ary[j+1])
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
for(i = sp; i< (ChunkSize+sp); i++)
{
printf("\n %f",ary[i]);
}
printf("\n \n");
return;
}
//************** merge sort HOST *****************
void MergeSortI(signed int *list, long length)
{
long i;
long left_min, left_max, right_min, right_max, next;
signed int *tmp = (int*)malloc(sizeof(int) * length);
if (tmp == NULL)
{
fputs("Error: out of memory\n", stderr);
abort();
}
for (i = 1; i < length; i *= 2)
{
for (left_min = 0; left_min < length - i; left_min = right_max)
{
right_min = left_max = left_min + i;
right_max = left_max + i;
if (right_max > length)
right_max = length;
next = 0;
while (left_min < left_max && right_min < right_max)
tmp[next++] = list[left_min] > list[right_min] ? list[right_min++] : list[left_min++];
while (left_min < left_max)
list[--right_min] = list[--left_max];
while (next > 0)
list[--right_min] = tmp[--next];
}
}
free(tmp);
return;
}
void MergeSortL(signed long long *list, long length)
{
long i;
long left_min, left_max, right_min, right_max, next;
signed long long *tmp = (long long *)malloc(sizeof(long long ) * length);
if (tmp == NULL)
{
fputs("Error: out of memory\n", stderr);
abort();
}
for (i = 1; i < length; i *= 2)
{
for (left_min = 0; left_min < length - i; left_min = right_max)
{
right_min = left_max = left_min + i;
right_max = left_max + i;
if (right_max > length)
right_max = length;
next = 0;
while (left_min < left_max && right_min < right_max)
tmp[next++] = list[left_min] > list[right_min] ? list[right_min++] : list[left_min++];
while (left_min < left_max)
list[--right_min] = list[--left_max];
while (next > 0)
list[--right_min] = tmp[--next];
}
}
free(tmp);
return;
}
void MergeSortF(float *list, long length)
{
long i;
long left_min, left_max, right_min, right_max, next;
float *tmp = (float *)malloc(sizeof(float ) * length);
if (tmp == NULL)
{
fputs("Error: out of memory\n", stderr);
abort();
}
for (i = 1; i < length; i *= 2)
{
for (left_min = 0; left_min < length - i; left_min = right_max)
{
right_min = left_max = left_min + i;
right_max = left_max + i;
if (right_max > length)
right_max = length;
next = 0;
while (left_min < left_max && right_min < right_max)
tmp[next++] = list[left_min] > list[right_min] ? list[right_min++] : list[left_min++];
while (left_min < left_max)
list[--right_min] = list[--left_max];
while (next > 0)
list[--right_min] = tmp[--next];
}
}
free(tmp);
return;
}
void MergeSortD(double *list, long length)
{
long i;
long left_min, left_max, right_min, right_max, next;
double *tmp = (double *)malloc(sizeof(double ) * length);
if (tmp == NULL)
{
fputs("Error: out of memory\n", stderr);
abort();
}
for (i = 1; i < length; i *= 2)
{
for (left_min = 0; left_min < length - i; left_min = right_max)
{
right_min = left_max = left_min + i;
right_max = left_max + i;
if (right_max > length)
right_max = length;
next = 0;
while (left_min < left_max && right_min < right_max)
tmp[next++] = list[left_min] > list[right_min] ? list[right_min++] : list[left_min++];
while (left_min < left_max)
list[--right_min] = list[--left_max];
while (next > 0)
list[--right_min] = tmp[--next];
}
}
free(tmp);
return;
} | #include <pthread.h>
#include <stdint.h>
#include <ctype.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <sys/time.h>
#include <malloc.h>
#include "hip/hip_runtime.h"
#include <iostream>
#include <time.h>
#define REPS 1
void SortChunkI(long ChunkSize, int Chunk_ID, signed int *ary);
void SortChunkL(long ChunkSize, int Chunk_ID, signed long long *ary);
void SortChunkF(long ChunkSize, int Chunk_ID, float *ary);
void SortChunkD(long ChunkSize, int Chunk_ID, double *ary);
void MergeSortI(signed int *list, long length);
void MergeSortL(signed long long *list, long length);
void MergeSortF(float *list, long length);
void MergeSortD(double *list, long length);
__global__ void SortChunkGI(signed int ary[], long ChunkSize)
{
unsigned long i,j;
unsigned long sp;
int temp;
sp = (blockIdx.x * blockDim.x +threadIdx.x)*ChunkSize;
printf("\n start:%li end:%li Chunksize: %li S_ary: %i E_ary:%i\n",sp,ChunkSize+sp-1,ChunkSize,ary[sp],ary[ChunkSize+sp-1]);
for(i = 0; i< ChunkSize; i++)
{
for(j = sp; j< (ChunkSize+sp-1-i); j++)
{
if( (ary[j]) > (ary[j+1]))
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
}
__global__ void SortChunkGL(signed long long ary[], long ChunkSize)
{
unsigned long i,j;
unsigned long sp;
long long temp;
sp = (blockIdx.x * blockDim.x +threadIdx.x)*ChunkSize;
//printf("\n start:%li end:%li Chunksize: %li S_ary: %i E_ary:%i\n",sp,ChunkSize+sp-1,ChunkSize,ary[sp],ary[ChunkSize+sp-1]);
for(i = 0; i< ChunkSize; i++)
{
for(j = sp; j< (ChunkSize+sp-1-i); j++)
{
if( (ary[j]) > (ary[j+1]))
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
}
__global__ void SortChunkGF(float ary[], long ChunkSize)
{
unsigned long i,j;
unsigned long sp;
float temp;
sp = (blockIdx.x * blockDim.x +threadIdx.x)*ChunkSize;
printf("\n start:%li end:%li Chunksize: %li S_ary: %i E_ary:%i\n",sp,ChunkSize+sp-1,ChunkSize,ary[sp],ary[ChunkSize+sp-1]);
for(i = 0; i< ChunkSize; i++)
{
for(j = sp; j< (ChunkSize+sp-1-i); j++)
{
if( (ary[j]) > (ary[j+1]))
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
}
__global__ void SortChunkGD(double ary[], long ChunkSize)
{
unsigned long i,j;
unsigned long sp;
double temp;
sp = (blockIdx.x * blockDim.x +threadIdx.x)*ChunkSize;
printf("\n start:%li end:%li Chunksize: %li S_ary: %i E_ary:%i\n",sp,ChunkSize+sp-1,ChunkSize,ary[sp],ary[ChunkSize+sp-1]);
for(i = 0; i< ChunkSize; i++)
{
for(j = sp; j< (ChunkSize+sp-1-i); j++)
{
if( (ary[j]) > (ary[j+1]))
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
}
int main(int argc, char** argv)
{
//**************** HOST variable ******************
struct timeval t;
double StartTime, EndTime;
double TimeElapsed;
long a,i;
long NumOfChunk;
long HowMany;
long ChunkSize;
char Type;
signed int *InputArrayI,*SortedArrayI;
signed long long *InputArrayL,*SortedArrayL;
float *InputArrayF,*SortedArrayF;
double *InputArrayD,*SortedArrayD;
long BlockSize;
long NumOfBlock;
//**************** GPU variable ******************
signed int *InputArrayG_I,*SortedArrayG_I;
signed long long *InputArrayG_L,*SortedArrayG_L;
float *InputArrayG_F,*SortedArrayG_F;
double *InputArrayG_D,*SortedArrayG_D;
FILE *ff = fopen("BubbleSortResult.txt", "w");
FILE *fp = fopen("MergeSortResult.txt", "w");
if(argc != 5)
{
printf("\n Argument is not correct \n\n");
printf("Nothing executed ... Exiting ...\n\n");
exit(EXIT_FAILURE);
}
HowMany = atoi(argv[1]);
ChunkSize = atoi(argv[3]);
Type = toupper(argv[2][0]);
BlockSize = atoi(argv[4]);
NumOfChunk = HowMany/(ChunkSize);
NumOfBlock = HowMany/((ChunkSize * BlockSize));
printf("\nElement type : %c\n",Type);
printf("BlockSize : %li\n",BlockSize);
printf("\nNumberOfChunk : %li\n",NumOfChunk);
printf("Total Block : %li\n",NumOfBlock);
printf("Total Element : %li\n\n\n\n",NumOfBlock*ChunkSize*BlockSize);
srand(time(NULL));
// HOST*************inital rand number
switch(Type)
{
case 'I':
InputArrayI = (signed int *)malloc(HowMany * sizeof(signed int));
SortedArrayI = (signed int *)malloc(HowMany * sizeof(signed int));
for(i=0;i<HowMany;i++)
{
InputArrayI[i] = ( ((-1)^i)*rand() );
}
break;
//*******************************************
case 'L':
InputArrayL = (signed long long *)malloc(HowMany * sizeof(signed long long ));
SortedArrayL = (signed long long *)malloc(HowMany * sizeof(signed long long ));
for(i=0;i<HowMany;i++)
{
InputArrayL[i] =(long long )( ((-1)^i)*rand()<<32 | rand() );
}
break;
//*******************************************
case 'F':
InputArrayF = (float *)malloc(HowMany * sizeof(float));
SortedArrayF = (float *)malloc(HowMany * sizeof(float));
int my_random_int;
for(i=0;i<HowMany;i++)
{
my_random_int = ((-1)^i)*rand() ;
InputArrayF[i] = *(float*)&my_random_int;
if(isnan(InputArrayF[i])){i--;}
}
break;
//*******************************************
case 'D':
InputArrayD = (double *)malloc(HowMany * sizeof(double));
SortedArrayD = (double *)malloc(HowMany * sizeof(double));
long long int my_random_long;
for(i=0;i<HowMany;i++)
{
my_random_long = (long long )(( ((-1)^i)*rand()<<32) | rand() );
InputArrayD[i] = *(double*)&my_random_long;
if(isnan(InputArrayD[i])){i--;}
}
break;
}
// GPU*********** inital GPU and transfer data HtoD
switch(Type)
{
case 'I':
hipMalloc ((signed int **)&InputArrayG_I, HowMany*sizeof(signed int));
hipMalloc ((signed int **)&SortedArrayG_I, HowMany*sizeof(signed int));
hipMemcpy (InputArrayG_I, InputArrayI, HowMany*sizeof(signed int), hipMemcpyHostToDevice);
hipMemcpy (SortedArrayG_I, InputArrayI, HowMany*sizeof(signed int), hipMemcpyHostToDevice);
break;
//*******************************************
case 'L':
hipMalloc ((signed long long **)&InputArrayG_L, HowMany* sizeof(signed long long ));
hipMalloc ((signed long long **)&SortedArrayG_L, HowMany* sizeof(signed long long ));
hipMemcpy (InputArrayG_L, InputArrayL, HowMany, hipMemcpyHostToDevice);
hipMemcpy (SortedArrayG_L, InputArrayL, HowMany*sizeof(signed int), hipMemcpyHostToDevice);
break;
//*******************************************
case 'F':
hipMalloc ((float **)&InputArrayG_F, HowMany);
hipMalloc ((float **)&SortedArrayG_F, HowMany);
hipMemcpy (InputArrayG_F, InputArrayF, HowMany, hipMemcpyHostToDevice);
hipMemcpy (SortedArrayG_F, InputArrayF, HowMany*sizeof(signed int), hipMemcpyHostToDevice);
break;
//*******************************************
case 'D':
hipMalloc ((double **)&InputArrayG_D, HowMany);
hipMalloc ((double **)&SortedArrayG_D, HowMany);
hipMemcpy (InputArrayG_D, InputArrayD, HowMany, hipMemcpyHostToDevice);
hipMemcpy (SortedArrayG_D, InputArrayD, HowMany*sizeof(signed int), hipMemcpyHostToDevice);
break;
}
gettimeofday(&t, NULL);
StartTime = (double)t.tv_sec*1000000.0 + ((double)t.tv_usec);
//******************* sort ***************
for(a=0; a<REPS; a++)
{
switch(Type)
{
case 'I':
// tot block element per block
SortChunkGI<<< NumOfBlock, BlockSize>>> (SortedArrayG_I,ChunkSize);
hipMemcpy (SortedArrayI, SortedArrayG_I, HowMany*sizeof(signed int), hipMemcpyDeviceToHost);
fprintf(ff, "Bubble sorted result of int done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(ff, "%i \n", SortedArrayI[i]);
if((i+1)%ChunkSize ==0){fprintf(ff, " \n");}
}
MergeSortI(SortedArrayI, HowMany);
break;
//*******************************************
case 'L':
// tot block element per block
SortChunkGL<<< NumOfBlock, BlockSize>>> (SortedArrayG_L,ChunkSize);
hipMemcpy (SortedArrayL, SortedArrayG_L, HowMany*sizeof(signed long long), hipMemcpyDeviceToHost);
fprintf(ff, "Bubble sorted result of long done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(ff, "%lli \n", SortedArrayL[i]);
if((i+1)%ChunkSize ==0){fprintf(ff, " \n");}
}
MergeSortL(SortedArrayL, HowMany);
break;
//*******************************************
case 'F':
// tot block element per block
SortChunkGF<<< NumOfBlock, BlockSize>>> (SortedArrayG_F,ChunkSize);
hipMemcpy (SortedArrayF, SortedArrayG_F, HowMany*sizeof(float), hipMemcpyDeviceToHost);
fprintf(ff, "Bubble sorted result of float done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(ff, "%f \n", SortedArrayF[i]);
if((i+1)%ChunkSize ==0){fprintf(ff, " \n");}
}
MergeSortF(SortedArrayF, HowMany);
break;
//*******************************************
case 'D':
// tot block element per block
SortChunkGD<<< NumOfBlock, BlockSize>>> (SortedArrayG_D,ChunkSize);
hipMemcpy (SortedArrayD, SortedArrayG_D, HowMany*sizeof(double), hipMemcpyDeviceToHost);
fprintf(ff, "Bubble sorted result of double done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(ff, "%lf \n", InputArrayD[i]);
if((i+1)%ChunkSize ==0){fprintf(ff, " \n");}
}
MergeSortD(SortedArrayD, HowMany);
break;
}
}
gettimeofday(&t, NULL);
EndTime = (double)t.tv_sec*1000000.0 + ((double)t.tv_usec);
TimeElapsed=(EndTime-StartTime)/1000.00;
TimeElapsed/=(double)REPS;
printf("\n\nExecution time:%10.4f ms ",TimeElapsed);
// print result
switch(Type)
{
case 'I':
fprintf(fp, "Merge sorted result of int done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(fp, "%i \n", SortedArrayI[i]);
}
break;
//*******************************************
case 'L':
fprintf(fp, "Merge sorted result of long done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(fp, "%lli \n", SortedArrayL[i]);
}
break;
//*******************************************
case 'F':
fprintf(fp, "Merge sorted result of float done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(fp, "%f \n", SortedArrayF[i]);
}
break;
//******************************************
case 'D':
fprintf(fp, "Merge sorted result of double done by GPU\n***********************************\n");
for(i=0;i<HowMany;i++)
{
fprintf(fp, "%lf \n", SortedArrayD[i]);
}
break;
}
//free memoary
switch(Type)
{
case 'I':
free(InputArrayI);
free(SortedArrayI);
hipFree(InputArrayG_I);
hipFree(SortedArrayG_I);
break;
//*******************************************
case 'L':
free(InputArrayL);
free(SortedArrayL);
hipFree(InputArrayG_L);
hipFree(SortedArrayG_L);
break;
//*******************************************
case 'F':
free(InputArrayF);
free(SortedArrayF);
hipFree(InputArrayG_F);
hipFree(SortedArrayG_F);
break;
//*******************************************
case 'D':
free(InputArrayD);
free(SortedArrayD);
hipFree(InputArrayG_D);
hipFree(SortedArrayG_D);
break;
}
fclose(ff);
fclose(fp);
return (EXIT_SUCCESS);
}
//************** bubble sort HOST****************
void SortChunkI(long ChunkSize, int Chunk_ID, signed int *ary)
{
long i,j;
long sp;
int temp;
sp = Chunk_ID * ChunkSize;
for(i = 0; i< (ChunkSize-1); i++)
{
for(j = sp; j< ((ChunkSize+sp)-1-i); j++)
{
if(ary[j] > ary[j+1])
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
for(i = sp; i< (ChunkSize+sp); i++)
{
printf("\n %i",ary[i]);
}
printf("\n \n");
return;
}
void SortChunkL(long ChunkSize, int Chunk_ID, signed long long *ary)
{
long i,j;
long sp;
long long temp;
sp = Chunk_ID * ChunkSize;
for(i = 0; i< (ChunkSize-1); i++)
{
for(j = sp; j< ((ChunkSize+sp)-1-i); j++)
{
if(ary[j] > ary[j+1])
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
for(i = sp; i< (ChunkSize+sp); i++)
{
printf("\n %lli",ary[i]);
}
printf("\n \n");
return;
}
void SortChunkF(long ChunkSize, int Chunk_ID, float *ary)
{
long i,j;
long sp;
float temp;
sp = Chunk_ID * ChunkSize;
for(i = 0; i< (ChunkSize-1); i++)
{
for(j = sp; j< ((ChunkSize+sp)-1-i); j++)
{
if(ary[j] > ary[j+1])
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
for(i = sp; i< (ChunkSize+sp); i++)
{
printf("\n %f",ary[i]);
}
printf("\n \n");
return;
}
void SortChunkD(long ChunkSize, int Chunk_ID, double *ary)
{
long i,j;
long sp;
double temp;
sp = Chunk_ID * ChunkSize;
for(i = 0; i< (ChunkSize-1); i++)
{
for(j = sp; j< ((ChunkSize+sp)-1-i); j++)
{
if(ary[j] > ary[j+1])
{
temp = ary[j+1];
ary[j+1] = ary[j];
ary[j] = temp;
}
}
}
for(i = sp; i< (ChunkSize+sp); i++)
{
printf("\n %f",ary[i]);
}
printf("\n \n");
return;
}
//************** merge sort HOST *****************
void MergeSortI(signed int *list, long length)
{
long i;
long left_min, left_max, right_min, right_max, next;
signed int *tmp = (int*)malloc(sizeof(int) * length);
if (tmp == NULL)
{
fputs("Error: out of memory\n", stderr);
abort();
}
for (i = 1; i < length; i *= 2)
{
for (left_min = 0; left_min < length - i; left_min = right_max)
{
right_min = left_max = left_min + i;
right_max = left_max + i;
if (right_max > length)
right_max = length;
next = 0;
while (left_min < left_max && right_min < right_max)
tmp[next++] = list[left_min] > list[right_min] ? list[right_min++] : list[left_min++];
while (left_min < left_max)
list[--right_min] = list[--left_max];
while (next > 0)
list[--right_min] = tmp[--next];
}
}
free(tmp);
return;
}
void MergeSortL(signed long long *list, long length)
{
long i;
long left_min, left_max, right_min, right_max, next;
signed long long *tmp = (long long *)malloc(sizeof(long long ) * length);
if (tmp == NULL)
{
fputs("Error: out of memory\n", stderr);
abort();
}
for (i = 1; i < length; i *= 2)
{
for (left_min = 0; left_min < length - i; left_min = right_max)
{
right_min = left_max = left_min + i;
right_max = left_max + i;
if (right_max > length)
right_max = length;
next = 0;
while (left_min < left_max && right_min < right_max)
tmp[next++] = list[left_min] > list[right_min] ? list[right_min++] : list[left_min++];
while (left_min < left_max)
list[--right_min] = list[--left_max];
while (next > 0)
list[--right_min] = tmp[--next];
}
}
free(tmp);
return;
}
void MergeSortF(float *list, long length)
{
long i;
long left_min, left_max, right_min, right_max, next;
float *tmp = (float *)malloc(sizeof(float ) * length);
if (tmp == NULL)
{
fputs("Error: out of memory\n", stderr);
abort();
}
for (i = 1; i < length; i *= 2)
{
for (left_min = 0; left_min < length - i; left_min = right_max)
{
right_min = left_max = left_min + i;
right_max = left_max + i;
if (right_max > length)
right_max = length;
next = 0;
while (left_min < left_max && right_min < right_max)
tmp[next++] = list[left_min] > list[right_min] ? list[right_min++] : list[left_min++];
while (left_min < left_max)
list[--right_min] = list[--left_max];
while (next > 0)
list[--right_min] = tmp[--next];
}
}
free(tmp);
return;
}
void MergeSortD(double *list, long length)
{
long i;
long left_min, left_max, right_min, right_max, next;
double *tmp = (double *)malloc(sizeof(double ) * length);
if (tmp == NULL)
{
fputs("Error: out of memory\n", stderr);
abort();
}
for (i = 1; i < length; i *= 2)
{
for (left_min = 0; left_min < length - i; left_min = right_max)
{
right_min = left_max = left_min + i;
right_max = left_max + i;
if (right_max > length)
right_max = length;
next = 0;
while (left_min < left_max && right_min < right_max)
tmp[next++] = list[left_min] > list[right_min] ? list[right_min++] : list[left_min++];
while (left_min < left_max)
list[--right_min] = list[--left_max];
while (next > 0)
list[--right_min] = tmp[--next];
}
}
free(tmp);
return;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifndef __U_TENSOR_OPERATION_GPU_HPP__
#define __U_TENSOR_OPERATION_GPU_HPP__
/***
u-op-gpu.hpp base functions for tensor
Copyright (C) 2017 Renweu Gao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
***/
#ifdef USE_CUDA
#include <cuda.h>
namespace u {
}
#endif
#endif | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef __U_TENSOR_OPERATION_GPU_HPP__
#define __U_TENSOR_OPERATION_GPU_HPP__
/***
u-op-gpu.hpp base functions for tensor
Copyright (C) 2017 Renweu Gao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
***/
#ifdef USE_CUDA
#include <cuda.h>
namespace u {
}
#endif
#endif | .file "tmpxft_001a6a07_00000000-6_u-op-gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef __U_TENSOR_OPERATION_GPU_HPP__
#define __U_TENSOR_OPERATION_GPU_HPP__
/***
u-op-gpu.hpp base functions for tensor
Copyright (C) 2017 Renweu Gao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
***/
#ifdef USE_CUDA
#include <cuda.h>
namespace u {
}
#endif
#endif | #ifndef __U_TENSOR_OPERATION_GPU_HPP__
#define __U_TENSOR_OPERATION_GPU_HPP__
/***
u-op-gpu.hpp base functions for tensor
Copyright (C) 2017 Renweu Gao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
***/
#ifdef USE_CUDA
#include <hip/hip_runtime.h>
namespace u {
}
#endif
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef __U_TENSOR_OPERATION_GPU_HPP__
#define __U_TENSOR_OPERATION_GPU_HPP__
/***
u-op-gpu.hpp base functions for tensor
Copyright (C) 2017 Renweu Gao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
***/
#ifdef USE_CUDA
#include <hip/hip_runtime.h>
namespace u {
}
#endif
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef __U_TENSOR_OPERATION_GPU_HPP__
#define __U_TENSOR_OPERATION_GPU_HPP__
/***
u-op-gpu.hpp base functions for tensor
Copyright (C) 2017 Renweu Gao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
***/
#ifdef USE_CUDA
#include <hip/hip_runtime.h>
namespace u {
}
#endif
#endif | .text
.file "u-op-gpu.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a6a07_00000000-6_u-op-gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "u-op-gpu.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#define CUDACHECK(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
class TestClass {
public:
int * data;
size_t len;
TestClass(size_t len) {
printf("Constructor\n");
this->data = nullptr;
this->len = len;
}
~TestClass(){
printf("~Destructor\n");
}
__host__ void allocate(){
CUDACHECK(cudaMalloc((void**) &this->data, this->len * sizeof(int)));
CUDACHECK(cudaMemset(this->data, 0, this->len * sizeof(int)));
}
__host__ void free(){
CUDACHECK(cudaFree(this->data));
this->data = nullptr;
}
__device__ int get(size_t index){
return this->data[index];
}
__device__ void set(size_t index, int value){
this->data[index] = value;
}
};
__global__ void test_kernel(unsigned int threads, TestClass * d_instance){
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < threads){
// printf("Thread %u\n", tid);
printf("Thread %u: d_isntance %p, element %d\n", tid, d_instance, d_instance->get(tid));
}
}
void test_class_launch(){
const size_t N = 16;
// Construct on the host
TestClass * h_instance = new TestClass(N);
// Construct.
printf("construct...\n");
h_instance->allocate();
printf("h_instance %p \n", h_instance);
// Launch a kernel with the instance as the parameter
printf("kernel...\n");
test_kernel<<<1, N>>>(N, h_instance);
CUDACHECK(cudaDeviceSynchronize());
printf("synced...\n");
// Free
printf("free...\n");
h_instance->free();
delete h_instance;
}
int main(int argc, char * argv[]){
printf("main\n");
test_class_launch();
return 1;
} | code for sm_80
Function : _Z11test_kerneljP9TestClass
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*00b0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1b00 */
/*00c0*/ IMAD.WIDE.U32 R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x004fcc00078e0008 */
/*00d0*/ LD.E R8, [R8.64] ; /* 0x0000000408087980 */
/* 0x000ea2000c101900 */
/*00e0*/ MOV R10, 0x0 ; /* 0x00000000000a7802 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*0100*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001e20000100a00 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0120*/ LDC.64 R10, c[0x4][R10] ; /* 0x010000000a0a7b82 */
/* 0x000e620000000a00 */
/*0130*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0001e20000100800 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*0150*/ STL [R1+0x10], R8 ; /* 0x0000100801007387 */
/* 0x0041e80000100800 */
/*0160*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe40000000000 */
/*0170*/ MOV R9, 0x1e0 ; /* 0x000001e000097802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R20, 0x160 ; /* 0x0000016000147802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01b0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*01c0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*01d0*/ CALL.ABS.NOINC R10 ; /* 0x000000000a007343 */
/* 0x000fea0003c00000 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#define CUDACHECK(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
class TestClass {
public:
int * data;
size_t len;
TestClass(size_t len) {
printf("Constructor\n");
this->data = nullptr;
this->len = len;
}
~TestClass(){
printf("~Destructor\n");
}
__host__ void allocate(){
CUDACHECK(cudaMalloc((void**) &this->data, this->len * sizeof(int)));
CUDACHECK(cudaMemset(this->data, 0, this->len * sizeof(int)));
}
__host__ void free(){
CUDACHECK(cudaFree(this->data));
this->data = nullptr;
}
__device__ int get(size_t index){
return this->data[index];
}
__device__ void set(size_t index, int value){
this->data[index] = value;
}
};
__global__ void test_kernel(unsigned int threads, TestClass * d_instance){
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < threads){
// printf("Thread %u\n", tid);
printf("Thread %u: d_isntance %p, element %d\n", tid, d_instance, d_instance->get(tid));
}
}
void test_class_launch(){
const size_t N = 16;
// Construct on the host
TestClass * h_instance = new TestClass(N);
// Construct.
printf("construct...\n");
h_instance->allocate();
printf("h_instance %p \n", h_instance);
// Launch a kernel with the instance as the parameter
printf("kernel...\n");
test_kernel<<<1, N>>>(N, h_instance);
CUDACHECK(cudaDeviceSynchronize());
printf("synced...\n");
// Free
printf("free...\n");
h_instance->free();
delete h_instance;
}
int main(int argc, char * argv[]){
printf("main\n");
test_class_launch();
return 1;
} | .file "tmpxft_000ff2b4_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass
.type _Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass, @function
_Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass:
.LFB2094:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11test_kerneljP9TestClass(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass, .-_Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass
.globl _Z11test_kerneljP9TestClass
.type _Z11test_kerneljP9TestClass, @function
_Z11test_kerneljP9TestClass:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z11test_kerneljP9TestClass, .-_Z11test_kerneljP9TestClass
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Constructor\n"
.LC1:
.string "construct...\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ptheywood/cuda-class-test/master/main.cu"
.section .rodata.str1.1
.LC3:
.string "GPUassert: %s %s %d\n"
.LC4:
.string "h_instance %p \n"
.LC5:
.string "kernel...\n"
.LC6:
.string "synced...\n"
.LC7:
.string "free...\n"
.LC8:
.string "~Destructor\n"
.text
.globl _Z17test_class_launchv
.type _Z17test_class_launchv, @function
_Z17test_class_launchv:
.LFB2068:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2068
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movl $16, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB1:
call __printf_chk@PLT
.LEHE1:
movq $0, (%rbx)
movq $16, 8(%rbx)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
movq 8(%rbx), %rax
leaq 0(,%rax,4), %rsi
movq %rbx, %rdi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L21
movq 8(%rbx), %rax
leaq 0(,%rax,4), %rdx
movq (%rbx), %rdi
movl $0, %esi
call cudaMemset@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L22
movq %rbx, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L14:
call cudaDeviceSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L24
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdi
call cudaFree@PLT
.LEHE2:
movl %eax, %ebp
testl %eax, %eax
jne .L25
movq $0, (%rbx)
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %eax, %edi
.LEHB3:
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $33, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $34, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L23:
movq %rbx, %rsi
movl $16, %edi
call _Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass
jmp .L14
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $79, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $38, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L18:
endbr64
movq %rax, %rbp
movl $16, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movq %rbp, %rdi
call _Unwind_Resume@PLT
.LEHE3:
.cfi_endproc
.LFE2068:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2068:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2068-.LLSDACSB2068
.LLSDACSB2068:
.uleb128 .LEHB0-.LFB2068
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2068
.uleb128 .LEHE1-.LEHB1
.uleb128 .L18-.LFB2068
.uleb128 0
.uleb128 .LEHB2-.LFB2068
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB2068
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE2068:
.text
.size _Z17test_class_launchv, .-_Z17test_class_launchv
.section .rodata.str1.1
.LC9:
.string "main\n"
.text
.globl main
.type main, @function
main:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z17test_class_launchv
movl $1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z11test_kerneljP9TestClass"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z11test_kerneljP9TestClass(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#define CUDACHECK(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
class TestClass {
public:
int * data;
size_t len;
TestClass(size_t len) {
printf("Constructor\n");
this->data = nullptr;
this->len = len;
}
~TestClass(){
printf("~Destructor\n");
}
__host__ void allocate(){
CUDACHECK(cudaMalloc((void**) &this->data, this->len * sizeof(int)));
CUDACHECK(cudaMemset(this->data, 0, this->len * sizeof(int)));
}
__host__ void free(){
CUDACHECK(cudaFree(this->data));
this->data = nullptr;
}
__device__ int get(size_t index){
return this->data[index];
}
__device__ void set(size_t index, int value){
this->data[index] = value;
}
};
__global__ void test_kernel(unsigned int threads, TestClass * d_instance){
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < threads){
// printf("Thread %u\n", tid);
printf("Thread %u: d_isntance %p, element %d\n", tid, d_instance, d_instance->get(tid));
}
}
void test_class_launch(){
const size_t N = 16;
// Construct on the host
TestClass * h_instance = new TestClass(N);
// Construct.
printf("construct...\n");
h_instance->allocate();
printf("h_instance %p \n", h_instance);
// Launch a kernel with the instance as the parameter
printf("kernel...\n");
test_kernel<<<1, N>>>(N, h_instance);
CUDACHECK(cudaDeviceSynchronize());
printf("synced...\n");
// Free
printf("free...\n");
h_instance->free();
delete h_instance;
}
int main(int argc, char * argv[]){
printf("main\n");
test_class_launch();
return 1;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define CUDACHECK(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
class TestClass {
public:
int * data;
size_t len;
TestClass(size_t len) {
printf("Constructor\n");
this->data = nullptr;
this->len = len;
}
~TestClass(){
printf("~Destructor\n");
}
__host__ void allocate(){
CUDACHECK(hipMalloc((void**) &this->data, this->len * sizeof(int)));
CUDACHECK(hipMemset(this->data, 0, this->len * sizeof(int)));
}
__host__ void free(){
CUDACHECK(hipFree(this->data));
this->data = nullptr;
}
__device__ int get(size_t index){
return this->data[index];
}
__device__ void set(size_t index, int value){
this->data[index] = value;
}
};
__global__ void test_kernel(unsigned int threads, TestClass * d_instance){
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < threads){
// printf("Thread %u\n", tid);
printf("Thread %u: d_isntance %p, element %d\n", tid, d_instance, d_instance->get(tid));
}
}
void test_class_launch(){
const size_t N = 16;
// Construct on the host
TestClass * h_instance = new TestClass(N);
// Construct.
printf("construct...\n");
h_instance->allocate();
printf("h_instance %p \n", h_instance);
// Launch a kernel with the instance as the parameter
printf("kernel...\n");
test_kernel<<<1, N>>>(N, h_instance);
CUDACHECK(hipDeviceSynchronize());
printf("synced...\n");
// Free
printf("free...\n");
h_instance->free();
delete h_instance;
}
int main(int argc, char * argv[]){
printf("main\n");
test_class_launch();
return 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define CUDACHECK(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
class TestClass {
public:
int * data;
size_t len;
TestClass(size_t len) {
printf("Constructor\n");
this->data = nullptr;
this->len = len;
}
~TestClass(){
printf("~Destructor\n");
}
__host__ void allocate(){
CUDACHECK(hipMalloc((void**) &this->data, this->len * sizeof(int)));
CUDACHECK(hipMemset(this->data, 0, this->len * sizeof(int)));
}
__host__ void free(){
CUDACHECK(hipFree(this->data));
this->data = nullptr;
}
__device__ int get(size_t index){
return this->data[index];
}
__device__ void set(size_t index, int value){
this->data[index] = value;
}
};
__global__ void test_kernel(unsigned int threads, TestClass * d_instance){
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < threads){
// printf("Thread %u\n", tid);
printf("Thread %u: d_isntance %p, element %d\n", tid, d_instance, d_instance->get(tid));
}
}
void test_class_launch(){
const size_t N = 16;
// Construct on the host
TestClass * h_instance = new TestClass(N);
// Construct.
printf("construct...\n");
h_instance->allocate();
printf("h_instance %p \n", h_instance);
// Launch a kernel with the instance as the parameter
printf("kernel...\n");
test_kernel<<<1, N>>>(N, h_instance);
CUDACHECK(hipDeviceSynchronize());
printf("synced...\n");
// Free
printf("free...\n");
h_instance->free();
delete h_instance;
}
int main(int argc, char * argv[]){
printf("main\n");
test_class_launch();
return 1;
} | .text
.file "main.hip"
.globl _Z26__device_stub__test_kerneljP9TestClass # -- Begin function _Z26__device_stub__test_kerneljP9TestClass
.p2align 4, 0x90
.type _Z26__device_stub__test_kerneljP9TestClass,@function
_Z26__device_stub__test_kerneljP9TestClass: # @_Z26__device_stub__test_kerneljP9TestClass
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11test_kerneljP9TestClass, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__test_kerneljP9TestClass, .Lfunc_end0-_Z26__device_stub__test_kerneljP9TestClass
.cfi_endproc
# -- End function
.globl _Z17test_class_launchv # -- Begin function _Z17test_class_launchv
.p2align 4, 0x90
.type _Z17test_class_launchv,@function
_Z17test_class_launchv: # @_Z17test_class_launchv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $16, %edi
callq _Znwm
movq %rax, %rbx
movl $.Lstr.4, %edi
callq puts@PLT
movq $0, (%rbx)
movq $16, 8(%rbx)
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq _ZN9TestClass8allocateEv
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl $16, 4(%rsp)
movq %rbx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11test_kerneljP9TestClass, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movq (%rbx), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_ZN9TestClass4freeEv.exit
movq $0, (%rbx)
movl $.Lstr.5, %edi
callq puts@PLT
movq %rbx, %rdi
callq _ZdlPv
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 112
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $79, %r8d
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $38, %r8d
.LBB1_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size _Z17test_class_launchv, .Lfunc_end1-_Z17test_class_launchv
.cfi_endproc
# -- End function
.section .text._ZN9TestClass8allocateEv,"axG",@progbits,_ZN9TestClass8allocateEv,comdat
.weak _ZN9TestClass8allocateEv # -- Begin function _ZN9TestClass8allocateEv
.p2align 4, 0x90
.type _ZN9TestClass8allocateEv,@function
_ZN9TestClass8allocateEv: # @_ZN9TestClass8allocateEv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movq 8(%rdi), %rsi
shlq $2, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
movq (%rbx), %rdi
movq 8(%rbx), %rdx
shlq $2, %rdx
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit2
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $33, %r8d
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $34, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size _ZN9TestClass8allocateEv, .Lfunc_end2-_ZN9TestClass8allocateEv
.cfi_endproc
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr.6, %edi
callq puts@PLT
callq _Z17test_class_launchv
movl $1, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11test_kerneljP9TestClass, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11test_kerneljP9TestClass,@object # @_Z11test_kerneljP9TestClass
.section .rodata,"a",@progbits
.globl _Z11test_kerneljP9TestClass
.p2align 3, 0x0
_Z11test_kerneljP9TestClass:
.quad _Z26__device_stub__test_kerneljP9TestClass
.size _Z11test_kerneljP9TestClass, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "h_instance %p \n"
.size .L.str.1, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ptheywood/cuda-class-test/master/main.hip"
.size .L.str.3, 99
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11test_kerneljP9TestClass"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "construct..."
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "kernel..."
.size .Lstr.1, 10
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "synced..."
.size .Lstr.2, 10
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "free..."
.size .Lstr.3, 8
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Constructor"
.size .Lstr.4, 12
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "~Destructor"
.size .Lstr.5, 12
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "main"
.size .Lstr.6, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__test_kerneljP9TestClass
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11test_kerneljP9TestClass
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ff2b4_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass
.type _Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass, @function
_Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass:
.LFB2094:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11test_kerneljP9TestClass(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass, .-_Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass
.globl _Z11test_kerneljP9TestClass
.type _Z11test_kerneljP9TestClass, @function
_Z11test_kerneljP9TestClass:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z11test_kerneljP9TestClass, .-_Z11test_kerneljP9TestClass
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Constructor\n"
.LC1:
.string "construct...\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ptheywood/cuda-class-test/master/main.cu"
.section .rodata.str1.1
.LC3:
.string "GPUassert: %s %s %d\n"
.LC4:
.string "h_instance %p \n"
.LC5:
.string "kernel...\n"
.LC6:
.string "synced...\n"
.LC7:
.string "free...\n"
.LC8:
.string "~Destructor\n"
.text
.globl _Z17test_class_launchv
.type _Z17test_class_launchv, @function
_Z17test_class_launchv:
.LFB2068:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2068
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movl $16, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB1:
call __printf_chk@PLT
.LEHE1:
movq $0, (%rbx)
movq $16, 8(%rbx)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
movq 8(%rbx), %rax
leaq 0(,%rax,4), %rsi
movq %rbx, %rdi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L21
movq 8(%rbx), %rax
leaq 0(,%rax,4), %rdx
movq (%rbx), %rdi
movl $0, %esi
call cudaMemset@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L22
movq %rbx, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L14:
call cudaDeviceSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L24
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdi
call cudaFree@PLT
.LEHE2:
movl %eax, %ebp
testl %eax, %eax
jne .L25
movq $0, (%rbx)
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %eax, %edi
.LEHB3:
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $33, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $34, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L23:
movq %rbx, %rsi
movl $16, %edi
call _Z41__device_stub__Z11test_kerneljP9TestClassjP9TestClass
jmp .L14
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $79, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L25:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $38, %r9d
leaq .LC2(%rip), %r8
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L18:
endbr64
movq %rax, %rbp
movl $16, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movq %rbp, %rdi
call _Unwind_Resume@PLT
.LEHE3:
.cfi_endproc
.LFE2068:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2068:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2068-.LLSDACSB2068
.LLSDACSB2068:
.uleb128 .LEHB0-.LFB2068
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2068
.uleb128 .LEHE1-.LEHB1
.uleb128 .L18-.LFB2068
.uleb128 0
.uleb128 .LEHB2-.LFB2068
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB2068
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE2068:
.text
.size _Z17test_class_launchv, .-_Z17test_class_launchv
.section .rodata.str1.1
.LC9:
.string "main\n"
.text
.globl main
.type main, @function
main:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z17test_class_launchv
movl $1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z11test_kerneljP9TestClass"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z11test_kerneljP9TestClass(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z26__device_stub__test_kerneljP9TestClass # -- Begin function _Z26__device_stub__test_kerneljP9TestClass
.p2align 4, 0x90
.type _Z26__device_stub__test_kerneljP9TestClass,@function
_Z26__device_stub__test_kerneljP9TestClass: # @_Z26__device_stub__test_kerneljP9TestClass
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11test_kerneljP9TestClass, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__test_kerneljP9TestClass, .Lfunc_end0-_Z26__device_stub__test_kerneljP9TestClass
.cfi_endproc
# -- End function
.globl _Z17test_class_launchv # -- Begin function _Z17test_class_launchv
.p2align 4, 0x90
.type _Z17test_class_launchv,@function
_Z17test_class_launchv: # @_Z17test_class_launchv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl $16, %edi
callq _Znwm
movq %rax, %rbx
movl $.Lstr.4, %edi
callq puts@PLT
movq $0, (%rbx)
movq $16, 8(%rbx)
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq _ZN9TestClass8allocateEv
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 15(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl $16, 4(%rsp)
movq %rbx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11test_kerneljP9TestClass, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movq (%rbx), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_ZN9TestClass4freeEv.exit
movq $0, (%rbx)
movl $.Lstr.5, %edi
callq puts@PLT
movq %rbx, %rdi
callq _ZdlPv
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 112
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $79, %r8d
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $38, %r8d
.LBB1_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size _Z17test_class_launchv, .Lfunc_end1-_Z17test_class_launchv
.cfi_endproc
# -- End function
.section .text._ZN9TestClass8allocateEv,"axG",@progbits,_ZN9TestClass8allocateEv,comdat
.weak _ZN9TestClass8allocateEv # -- Begin function _ZN9TestClass8allocateEv
.p2align 4, 0x90
.type _ZN9TestClass8allocateEv,@function
_ZN9TestClass8allocateEv: # @_ZN9TestClass8allocateEv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movq 8(%rdi), %rsi
shlq $2, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit
movq (%rbx), %rdi
movq 8(%rbx), %rdx
shlq $2, %rdx
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit2
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $33, %r8d
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.8, %esi
movl $.L.str.3, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $34, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end2:
.size _ZN9TestClass8allocateEv, .Lfunc_end2-_ZN9TestClass8allocateEv
.cfi_endproc
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr.6, %edi
callq puts@PLT
callq _Z17test_class_launchv
movl $1, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11test_kerneljP9TestClass, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11test_kerneljP9TestClass,@object # @_Z11test_kerneljP9TestClass
.section .rodata,"a",@progbits
.globl _Z11test_kerneljP9TestClass
.p2align 3, 0x0
_Z11test_kerneljP9TestClass:
.quad _Z26__device_stub__test_kerneljP9TestClass
.size _Z11test_kerneljP9TestClass, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "h_instance %p \n"
.size .L.str.1, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ptheywood/cuda-class-test/master/main.hip"
.size .L.str.3, 99
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11test_kerneljP9TestClass"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "construct..."
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "kernel..."
.size .Lstr.1, 10
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "synced..."
.size .Lstr.2, 10
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "free..."
.size .Lstr.3, 8
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Constructor"
.size .Lstr.4, 12
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "~Destructor"
.size .Lstr.5, 12
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "main"
.size .Lstr.6, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__test_kerneljP9TestClass
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11test_kerneljP9TestClass
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// カーネル関数
__global__ void helloFromGPU(){
if(threadIdx.x == 5){
printf("Hello World form GPU! thread %d\n",threadIdx.x);
}
}
int main(int argc, char **argv){
printf("Hello World from CPU!\n");
// カーネル関数の呼び出し
helloFromGPU<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0030*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f3e0ff */
/*0040*/ ISETP.NE.AND P0, PT, R0, 0x5, PT ; /* 0x000000050000780c */
/* 0x001fda0003f05270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, 0x5 ; /* 0x00000005ff087424 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00a0*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100800 */
/*00b0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000620000000a00 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fce00078e00ff */
/*00d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0130*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0140*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// カーネル関数
__global__ void helloFromGPU(){
if(threadIdx.x == 5){
printf("Hello World form GPU! thread %d\n",threadIdx.x);
}
}
int main(int argc, char **argv){
printf("Hello World from CPU!\n");
// カーネル関数の呼び出し
helloFromGPU<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | .file "tmpxft_0000e600_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// カーネル関数
__global__ void helloFromGPU(){
if(threadIdx.x == 5){
printf("Hello World form GPU! thread %d\n",threadIdx.x);
}
}
int main(int argc, char **argv){
printf("Hello World from CPU!\n");
// カーネル関数の呼び出し
helloFromGPU<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// カーネル関数
__global__ void helloFromGPU(){
if(threadIdx.x == 5){
printf("Hello World form GPU! thread %d\n",threadIdx.x);
}
}
int main(int argc, char **argv){
printf("Hello World from CPU!\n");
// カーネル関数の呼び出し
helloFromGPU<<<1, 10>>>();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// カーネル関数
__global__ void helloFromGPU(){
if(threadIdx.x == 5){
printf("Hello World form GPU! thread %d\n",threadIdx.x);
}
}
int main(int argc, char **argv){
printf("Hello World from CPU!\n");
// カーネル関数の呼び出し
helloFromGPU<<<1, 10>>>();
hipDeviceReset();
return 0;
} | .text
.file "hello.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000e600_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--blockDim=32 --gridDim=1
#include <cuda.h>
__global__ void test_Prog(int *A, int N) {
const int tid = threadIdx.x;
int alpha=A[tid+1];
if(tid>=0)
{
int temp2=A[tid+2];
A[tid]+=temp2;
}
A[tid]+=alpha;
} | code for sm_80
Function : _Z9test_ProgPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ ISETP.GT.AND P0, PT, R2.reuse, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x041fe40003f04270 */
/*0050*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0060*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ee8000c1e1900 */
/*0080*/ @P0 LDG.E R4, [R2.64+0x8] ; /* 0x0000080402040981 */
/* 0x000ea4000c1e1900 */
/*0090*/ @P0 IADD3 R5, R4, R5, RZ ; /* 0x0000000504050210 */
/* 0x004fc80007ffe0ff */
/*00a0*/ IADD3 R7, R0, R5, RZ ; /* 0x0000000500077210 */
/* 0x008fe20007ffe0ff */
/*00b0*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x000fe8000c101904 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=32 --gridDim=1
#include <cuda.h>
__global__ void test_Prog(int *A, int N) {
const int tid = threadIdx.x;
int alpha=A[tid+1];
if(tid>=0)
{
int temp2=A[tid+2];
A[tid]+=temp2;
}
A[tid]+=alpha;
} | .file "tmpxft_00047451_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9test_ProgPiiPii
.type _Z29__device_stub__Z9test_ProgPiiPii, @function
_Z29__device_stub__Z9test_ProgPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9test_ProgPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z9test_ProgPiiPii, .-_Z29__device_stub__Z9test_ProgPiiPii
.globl _Z9test_ProgPii
.type _Z9test_ProgPii, @function
_Z9test_ProgPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9test_ProgPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9test_ProgPii, .-_Z9test_ProgPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9test_ProgPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9test_ProgPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=32 --gridDim=1
#include <cuda.h>
__global__ void test_Prog(int *A, int N) {
const int tid = threadIdx.x;
int alpha=A[tid+1];
if(tid>=0)
{
int temp2=A[tid+2];
A[tid]+=temp2;
}
A[tid]+=alpha;
} | //pass
//--blockDim=32 --gridDim=1
#include <hip/hip_runtime.h>
__global__ void test_Prog(int *A, int N) {
const int tid = threadIdx.x;
int alpha=A[tid+1];
if(tid>=0)
{
int temp2=A[tid+2];
A[tid]+=temp2;
}
A[tid]+=alpha;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=32 --gridDim=1
#include <hip/hip_runtime.h>
__global__ void test_Prog(int *A, int N) {
const int tid = threadIdx.x;
int alpha=A[tid+1];
if(tid>=0)
{
int temp2=A[tid+2];
A[tid]+=temp2;
}
A[tid]+=alpha;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9test_ProgPii
.globl _Z9test_ProgPii
.p2align 8
.type _Z9test_ProgPii,@function
_Z9test_ProgPii:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b96 v[0:2], v3, s[0:1]
s_waitcnt vmcnt(0)
v_add3_u32 v0, v2, v1, v0
global_store_b32 v3, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9test_ProgPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9test_ProgPii, .Lfunc_end0-_Z9test_ProgPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9test_ProgPii
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z9test_ProgPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=32 --gridDim=1
#include <hip/hip_runtime.h>
__global__ void test_Prog(int *A, int N) {
const int tid = threadIdx.x;
int alpha=A[tid+1];
if(tid>=0)
{
int temp2=A[tid+2];
A[tid]+=temp2;
}
A[tid]+=alpha;
} | .text
.file "kernel.hip"
.globl _Z24__device_stub__test_ProgPii # -- Begin function _Z24__device_stub__test_ProgPii
.p2align 4, 0x90
.type _Z24__device_stub__test_ProgPii,@function
_Z24__device_stub__test_ProgPii: # @_Z24__device_stub__test_ProgPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9test_ProgPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__test_ProgPii, .Lfunc_end0-_Z24__device_stub__test_ProgPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9test_ProgPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9test_ProgPii,@object # @_Z9test_ProgPii
.section .rodata,"a",@progbits
.globl _Z9test_ProgPii
.p2align 3, 0x0
_Z9test_ProgPii:
.quad _Z24__device_stub__test_ProgPii
.size _Z9test_ProgPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9test_ProgPii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__test_ProgPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9test_ProgPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9test_ProgPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ ISETP.GT.AND P0, PT, R2.reuse, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x041fe40003f04270 */
/*0050*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0060*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ee8000c1e1900 */
/*0080*/ @P0 LDG.E R4, [R2.64+0x8] ; /* 0x0000080402040981 */
/* 0x000ea4000c1e1900 */
/*0090*/ @P0 IADD3 R5, R4, R5, RZ ; /* 0x0000000504050210 */
/* 0x004fc80007ffe0ff */
/*00a0*/ IADD3 R7, R0, R5, RZ ; /* 0x0000000500077210 */
/* 0x008fe20007ffe0ff */
/*00b0*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x000fe8000c101904 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9test_ProgPii
.globl _Z9test_ProgPii
.p2align 8
.type _Z9test_ProgPii,@function
_Z9test_ProgPii:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b96 v[0:2], v3, s[0:1]
s_waitcnt vmcnt(0)
v_add3_u32 v0, v2, v1, v0
global_store_b32 v3, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9test_ProgPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9test_ProgPii, .Lfunc_end0-_Z9test_ProgPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9test_ProgPii
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z9test_ProgPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00047451_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9test_ProgPiiPii
.type _Z29__device_stub__Z9test_ProgPiiPii, @function
_Z29__device_stub__Z9test_ProgPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9test_ProgPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z9test_ProgPiiPii, .-_Z29__device_stub__Z9test_ProgPiiPii
.globl _Z9test_ProgPii
.type _Z9test_ProgPii, @function
_Z9test_ProgPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9test_ProgPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9test_ProgPii, .-_Z9test_ProgPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9test_ProgPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9test_ProgPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z24__device_stub__test_ProgPii # -- Begin function _Z24__device_stub__test_ProgPii
.p2align 4, 0x90
.type _Z24__device_stub__test_ProgPii,@function
_Z24__device_stub__test_ProgPii: # @_Z24__device_stub__test_ProgPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9test_ProgPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__test_ProgPii, .Lfunc_end0-_Z24__device_stub__test_ProgPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9test_ProgPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9test_ProgPii,@object # @_Z9test_ProgPii
.section .rodata,"a",@progbits
.globl _Z9test_ProgPii
.p2align 3, 0x0
_Z9test_ProgPii:
.quad _Z24__device_stub__test_ProgPii
.size _Z9test_ProgPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9test_ProgPii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__test_ProgPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9test_ProgPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <iostream>
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors( CUresult err, const char *file, const int line )
{
if( CUDA_SUCCESS != err) {
fprintf(stderr,
"CUDA Driver API error = %04d from file <%s>, line %i.\n",
err, file, line );
exit(-1);
}
}
int main() {
checkCudaErrors(cuInit(0));
int device_count = 0;
checkCudaErrors(cuDeviceGetCount(&device_count));
std::cout << "Hello World!" << std::endl;
std::cout << "Find " << device_count << " device(s)." << std::endl;
CUdevice device;
checkCudaErrors(cuDeviceGet(&device, 0));
char name[100];
checkCudaErrors(cuDeviceGetName(name, 100, device));
size_t bytes = 0;
checkCudaErrors(cuDeviceTotalMem(&bytes, device));
std::cout << name << " has total memory of " << bytes << " bytes." << std::endl;
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <iostream>
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors( CUresult err, const char *file, const int line )
{
if( CUDA_SUCCESS != err) {
fprintf(stderr,
"CUDA Driver API error = %04d from file <%s>, line %i.\n",
err, file, line );
exit(-1);
}
}
int main() {
checkCudaErrors(cuInit(0));
int device_count = 0;
checkCudaErrors(cuDeviceGetCount(&device_count));
std::cout << "Hello World!" << std::endl;
std::cout << "Find " << device_count << " device(s)." << std::endl;
CUdevice device;
checkCudaErrors(cuDeviceGet(&device, 0));
char name[100];
checkCudaErrors(cuDeviceGetName(name, 100, device));
size_t bytes = 0;
checkCudaErrors(cuDeviceTotalMem(&bytes, device));
std::cout << name << " has total memory of " << bytes << " bytes." << std::endl;
return 0;
} | .file "tmpxft_00122003_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z17__checkCudaErrors14cudaError_enumPKci.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CUDA Driver API error = %04d from file <%s>, line %i.\n"
.section .text._Z17__checkCudaErrors14cudaError_enumPKci,"axG",@progbits,_Z17__checkCudaErrors14cudaError_enumPKci,comdat
.weak _Z17__checkCudaErrors14cudaError_enumPKci
.type _Z17__checkCudaErrors14cudaError_enumPKci, @function
_Z17__checkCudaErrors14cudaError_enumPKci:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edx, %r9d
movq %rsi, %r8
movl %edi, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z17__checkCudaErrors14cudaError_enumPKci, .-_Z17__checkCudaErrors14cudaError_enumPKci
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/zw0610/dragon-li/master/poc/v1/hello_world.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Hello World!"
.LC3:
.string "Find "
.LC4:
.string " device(s)."
.LC5:
.string " has total memory of "
.LC6:
.string " bytes."
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, %edi
call cuInit@PLT
movl %eax, %edi
movl $20, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z17__checkCudaErrors14cudaError_enumPKci
movl $0, (%rsp)
movq %rsp, %rdi
call cuDeviceGetCount@PLT
movl %eax, %edi
movl $23, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors14cudaError_enumPKci
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 4(%rsp), %rdi
movl $0, %esi
call cuDeviceGet@PLT
movl %eax, %edi
movl $29, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors14cudaError_enumPKci
leaq 16(%rsp), %r12
movl 4(%rsp), %edx
movl $100, %esi
movq %r12, %rdi
call cuDeviceGetName@PLT
movl %eax, %edi
movl $32, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors14cudaError_enumPKci
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl 4(%rsp), %esi
call cuDeviceTotalMem_v2@PLT
movl %eax, %edi
movl $35, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors14cudaError_enumPKci
movq %r12, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <iostream>
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors( CUresult err, const char *file, const int line )
{
if( CUDA_SUCCESS != err) {
fprintf(stderr,
"CUDA Driver API error = %04d from file <%s>, line %i.\n",
err, file, line );
exit(-1);
}
}
int main() {
checkCudaErrors(cuInit(0));
int device_count = 0;
checkCudaErrors(cuDeviceGetCount(&device_count));
std::cout << "Hello World!" << std::endl;
std::cout << "Find " << device_count << " device(s)." << std::endl;
CUdevice device;
checkCudaErrors(cuDeviceGet(&device, 0));
char name[100];
checkCudaErrors(cuDeviceGetName(name, 100, device));
size_t bytes = 0;
checkCudaErrors(cuDeviceTotalMem(&bytes, device));
std::cout << name << " has total memory of " << bytes << " bytes." << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors( hipError_t err, const char *file, const int line )
{
if( hipSuccess != err) {
fprintf(stderr,
"CUDA Driver API error = %04d from file <%s>, line %i.\n",
err, file, line );
exit(-1);
}
}
int main() {
checkCudaErrors(hipInit(0));
int device_count = 0;
checkCudaErrors(hipGetDeviceCount(&device_count));
std::cout << "Hello World!" << std::endl;
std::cout << "Find " << device_count << " device(s)." << std::endl;
hipDevice_t device;
checkCudaErrors(hipDeviceGet(&device, 0));
char name[100];
checkCudaErrors(hipDeviceGetName(name, 100, device));
size_t bytes = 0;
checkCudaErrors(hipDeviceTotalMem(&bytes, device));
std::cout << name << " has total memory of " << bytes << " bytes." << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors( hipError_t err, const char *file, const int line )
{
if( hipSuccess != err) {
fprintf(stderr,
"CUDA Driver API error = %04d from file <%s>, line %i.\n",
err, file, line );
exit(-1);
}
}
int main() {
checkCudaErrors(hipInit(0));
int device_count = 0;
checkCudaErrors(hipGetDeviceCount(&device_count));
std::cout << "Hello World!" << std::endl;
std::cout << "Find " << device_count << " device(s)." << std::endl;
hipDevice_t device;
checkCudaErrors(hipDeviceGet(&device, 0));
char name[100];
checkCudaErrors(hipDeviceGetName(name, 100, device));
size_t bytes = 0;
checkCudaErrors(hipDeviceTotalMem(&bytes, device));
std::cout << name << " has total memory of " << bytes << " bytes." << std::endl;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define checkCudaErrors(err) __checkCudaErrors (err, __FILE__, __LINE__)
inline void __checkCudaErrors( hipError_t err, const char *file, const int line )
{
if( hipSuccess != err) {
fprintf(stderr,
"CUDA Driver API error = %04d from file <%s>, line %i.\n",
err, file, line );
exit(-1);
}
}
int main() {
checkCudaErrors(hipInit(0));
int device_count = 0;
checkCudaErrors(hipGetDeviceCount(&device_count));
std::cout << "Hello World!" << std::endl;
std::cout << "Find " << device_count << " device(s)." << std::endl;
hipDevice_t device;
checkCudaErrors(hipDeviceGet(&device, 0));
char name[100];
checkCudaErrors(hipDeviceGetName(name, 100, device));
size_t bytes = 0;
checkCudaErrors(hipDeviceTotalMem(&bytes, device));
std::cout << name << " has total memory of " << bytes << " bytes." << std::endl;
return 0;
} | .text
.file "hello_world.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %edi, %edi
callq hipInit
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_Z17__checkCudaErrors10hipError_tPKci.exit
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_Z17__checkCudaErrors10hipError_tPKci.exit2
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_24
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_8
# %bb.7:
movzbl 67(%rbx), %eax
jmp .LBB0_9
.LBB0_8:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.3, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_24
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%r14)
je .LBB0_12
# %bb.11:
movzbl 67(%r14), %eax
jmp .LBB0_13
.LBB0_12:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
xorl %esi, %esi
callq hipDeviceGet
testl %eax, %eax
jne .LBB0_14
# %bb.15: # %_Z17__checkCudaErrors10hipError_tPKci.exit4
movl (%rsp), %edx
leaq 16(%rsp), %rdi
movl $100, %esi
callq hipDeviceGetName
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z17__checkCudaErrors10hipError_tPKci.exit6
movq $0, 8(%rsp)
movl (%rsp), %esi
leaq 8(%rsp), %rdi
callq hipDeviceTotalMem
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z17__checkCudaErrors10hipError_tPKci.exit8
leaq 16(%rsp), %rbx
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.5, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%r14)
je .LBB0_22
# %bb.21:
movzbl 67(%r14), %eax
jmp .LBB0_23
.LBB0_22:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_24:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.LBB0_1:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl $.L.str, %ecx
movl %eax, %edx
movl $20, %r8d
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl $.L.str, %ecx
movl %eax, %edx
movl $23, %r8d
jmp .LBB0_2
.LBB0_14:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl $.L.str, %ecx
movl %eax, %edx
movl $29, %r8d
jmp .LBB0_2
.LBB0_16:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl $.L.str, %ecx
movl %eax, %edx
movl $32, %r8d
jmp .LBB0_2
.LBB0_18:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl $.L.str, %ecx
movl %eax, %edx
movl $35, %r8d
.LBB0_2:
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/zw0610/dragon-li/master/poc/v1/hello_world.hip"
.size .L.str, 104
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Hello World!"
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Find "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " device(s)."
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " has total memory of "
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " bytes."
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA Driver API error = %04d from file <%s>, line %i.\n"
.size .L.str.6, 55
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00122003_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z17__checkCudaErrors14cudaError_enumPKci.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CUDA Driver API error = %04d from file <%s>, line %i.\n"
.section .text._Z17__checkCudaErrors14cudaError_enumPKci,"axG",@progbits,_Z17__checkCudaErrors14cudaError_enumPKci,comdat
.weak _Z17__checkCudaErrors14cudaError_enumPKci
.type _Z17__checkCudaErrors14cudaError_enumPKci, @function
_Z17__checkCudaErrors14cudaError_enumPKci:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edx, %r9d
movq %rsi, %r8
movl %edi, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z17__checkCudaErrors14cudaError_enumPKci, .-_Z17__checkCudaErrors14cudaError_enumPKci
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/zw0610/dragon-li/master/poc/v1/hello_world.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Hello World!"
.LC3:
.string "Find "
.LC4:
.string " device(s)."
.LC5:
.string " has total memory of "
.LC6:
.string " bytes."
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $0, %edi
call cuInit@PLT
movl %eax, %edi
movl $20, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z17__checkCudaErrors14cudaError_enumPKci
movl $0, (%rsp)
movq %rsp, %rdi
call cuDeviceGetCount@PLT
movl %eax, %edi
movl $23, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors14cudaError_enumPKci
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 4(%rsp), %rdi
movl $0, %esi
call cuDeviceGet@PLT
movl %eax, %edi
movl $29, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors14cudaError_enumPKci
leaq 16(%rsp), %r12
movl 4(%rsp), %edx
movl $100, %esi
movq %r12, %rdi
call cuDeviceGetName@PLT
movl %eax, %edi
movl $32, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors14cudaError_enumPKci
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl 4(%rsp), %esi
call cuDeviceTotalMem_v2@PLT
movl %eax, %edi
movl $35, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors14cudaError_enumPKci
movq %r12, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_world.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %edi, %edi
callq hipInit
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_Z17__checkCudaErrors10hipError_tPKci.exit
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_Z17__checkCudaErrors10hipError_tPKci.exit2
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_24
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_8
# %bb.7:
movzbl 67(%rbx), %eax
jmp .LBB0_9
.LBB0_8:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.3, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_24
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%r14)
je .LBB0_12
# %bb.11:
movzbl 67(%r14), %eax
jmp .LBB0_13
.LBB0_12:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
xorl %esi, %esi
callq hipDeviceGet
testl %eax, %eax
jne .LBB0_14
# %bb.15: # %_Z17__checkCudaErrors10hipError_tPKci.exit4
movl (%rsp), %edx
leaq 16(%rsp), %rdi
movl $100, %esi
callq hipDeviceGetName
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z17__checkCudaErrors10hipError_tPKci.exit6
movq $0, 8(%rsp)
movl (%rsp), %esi
leaq 8(%rsp), %rdi
callq hipDeviceTotalMem
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z17__checkCudaErrors10hipError_tPKci.exit8
leaq 16(%rsp), %rbx
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.5, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_24
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%r14)
je .LBB0_22
# %bb.21:
movzbl 67(%r14), %eax
jmp .LBB0_23
.LBB0_22:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_24:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.LBB0_1:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl $.L.str, %ecx
movl %eax, %edx
movl $20, %r8d
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl $.L.str, %ecx
movl %eax, %edx
movl $23, %r8d
jmp .LBB0_2
.LBB0_14:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl $.L.str, %ecx
movl %eax, %edx
movl $29, %r8d
jmp .LBB0_2
.LBB0_16:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl $.L.str, %ecx
movl %eax, %edx
movl $32, %r8d
jmp .LBB0_2
.LBB0_18:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
movl $.L.str, %ecx
movl %eax, %edx
movl $35, %r8d
.LBB0_2:
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/zw0610/dragon-li/master/poc/v1/hello_world.hip"
.size .L.str, 104
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Hello World!"
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Find "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " device(s)."
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " has total memory of "
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " bytes."
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA Driver API error = %04d from file <%s>, line %i.\n"
.size .L.str.6, 55
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cstdio>
#include<fstream>
#include<cmath>
#include<cuda.h>
int threshold=256;
int xthread=32;
__global__ void multiply(float* A,float* B,float* C,int jump,int jump1,int jump2,int iter)
{
__shared__ float A1[32][32],B1[32][32];
int posy=blockIdx.y*blockDim.y+threadIdx.y;
int posx=blockIdx.x*blockDim.x+threadIdx.x;
int row=posy*jump+threadIdx.x;
int col=posx+threadIdx.y*jump1;
int place=posy*jump2+posx;
for(int i=0;i<iter;i++)
{
A1[threadIdx.y][threadIdx.x]=A[row];
B1[threadIdx.y][threadIdx.x]=B[col];
__syncthreads();
for(int i=0;i<blockDim.x;i++)
C[place]+=A1[threadIdx.y][i]*B1[i][threadIdx.x];
row+=blockDim.x;
col+=blockDim.y*jump1;
__syncthreads();
}
}
//non_square matrix multiplication
__global__ void kernel1(float* A,int jump1,int n1,float* B,int jump2,int n2,float* C,int jump3,float* D,int jump4,int m1,int m2,int m3)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y+threadIdx.y;
if(col<m2 && row<m1)
C[col+jump3*row]=A[col+jump1*row]+A[n1+col+jump1*row];
if(col<m3 && row<m2)
D[col+jump4*row]=B[col+jump2*row]+B[n2+col+jump2*row];
}
__global__ void kernel7(float* A,int jump1,int n1,float* B,int jump2,int n2,float* C,int jump3,float* D,int jump4,int m1,int m2,int m3)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y+threadIdx.y;
if(col<m2 && row<m1)
C[col+jump3*row]=A[col+jump1*row]-A[n1+col+jump1*row];
if(col<m3 && row<m2)
D[col+jump4*row]=B[col+jump2*row]+B[n2+col+jump2*row];
}
__global__ void kernel2(float* A,int jump,int n1,int n2,float* B,int jump1,float* C,int jump2,int n3,int m2,int m3)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
if(col<m3)
{
if(3*blockIdx.y<gridDim.y)
{
int point=col+(blockIdx.y * blockDim.y + threadIdx.y)*jump;
A[point+n2]+=A[point];
}
else if(3*blockIdx.y<2*gridDim.y)
{
int point=col+((blockIdx.y-gridDim.y/3) * blockDim.y + threadIdx.y)*jump;
A[point]+=A[point+n1];
A[point+n1]=0;
}
}
if(col<m2 && 3*blockIdx.y>=2*gridDim.y)
{
int row=(blockIdx.y-2*gridDim.y/3) * blockDim.y + threadIdx.y;
B[col+jump1*row]=C[col+jump2*row]+C[col+jump2*row+n3];
}
}
__global__ void kernel3(float* A,int jump,int n,float* B,int jump1,float* C,int jump2,int n1,int m2,int m3)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
if(col<m2)
A[col+jump*row+n]-=A[col+jump*row];
if(col<m3)
B[col+jump1*row]=C[col+jump2*row]+C[col+jump2*row+n1];
}
__global__ void kernel4(float* A,int jump,int n1,float* B,int jump1,float* C,int jump2,float* D,int jump3,int n2,int m1,int m2)
{
int col=blockIdx.x * blockDim.x+threadIdx.x,row;
if(2*blockIdx.y<gridDim.y)
{
row=blockIdx.y * blockDim.y + threadIdx.y;
if(row<m1)
{
A[col+jump*row]+=B[col+jump1*row];
A[col+jump*row+n1]+=B[col+jump1*row];
B[col+jump1*row]=0;
}
}
else
{
row=(blockIdx.y-gridDim.y/2) * blockDim.y + threadIdx.y;
if(row<m2)
C[col+jump2*row]=D[col+jump3*row+n2]-D[col+jump3*row];
}
}
__global__ void kernel5(float* A,int jump,int n1,float* B,int jump1)
{
int point=(blockIdx.x * blockDim.x+threadIdx.x)+(blockIdx.y * blockDim.y + threadIdx.y)*jump;
int point1=(blockIdx.x * blockDim.x+threadIdx.x)+(blockIdx.y * blockDim.y + threadIdx.y)*jump1;
A[point]+=B[point1];
A[point+n1]+=B[point1];
}
__global__ void kernel6(float* A,int jump,float* B,int jump1,int n1,float* C,int jump2,float* D,int jump3,int n2,int m1,int m2,int m3)
{
int col=blockIdx.x*blockDim.x+threadIdx.x;
if(col<m2 && 3*blockIdx.y<gridDim.y)
{
int row=blockIdx.y*blockDim.y+threadIdx.y;
if(row<m1)
A[col+row*jump]=0;
}
if(col<m3 && 3*blockIdx.y>=gridDim.y && 3*blockIdx.y<2*gridDim.y)
{
int row=(blockIdx.y-gridDim.y/3) * blockDim.y + threadIdx.y;
if(row<m1)
B[col+row*jump1]-=B[col+row*jump1+n1];
}
if(col<m3 && 3*blockIdx.y>2*gridDim.y)
{
int row=(blockIdx.y-(2*gridDim.y/3)) * blockDim.y + threadIdx.y;
if(row<m2)
C[col+jump2*row]=D[col+jump3*row]-D[col+jump3*row+n2];
}
}
void strassen(float* A,int jump,float* B,int jump1,float* C,int jump2,int n1,int n2,int n3,float* temp1,float* temp2,int n,int n_)
{
if(n1<=threshold || n2<=threshold || n3<=threshold)
{
multiply <<<dim3(n3/xthread,n1/xthread),dim3(xthread,xthread)>>> (A,B,C,jump,jump1,jump2,n2/xthread);
}
else
{
n1/=2;n2/=2;n3/=2;
n/=2;n_/=2;
//M1
kernel1 <<<dim3(n_/xthread,n/xthread),dim3(xthread,xthread)>>> (A,jump,jump*n1+n2,B,jump1,jump1*n2+n3,temp1,n2,temp2,n3,n1,n2,n3); //temp1=A11+A22 //temp2=B11+B22
strassen(temp1,n2,temp2,n3,C,jump2,n1,n2,n3,temp1+n1*n2,temp2+n2*n3,n,n_); //C11=temp1*temp2
//M6
kernel7 <<<dim3(n_/xthread,n/xthread),dim3(xthread,xthread)>>> (A+jump*n1,jump,-jump*n1,B,jump1,n3,temp1,n2,temp2,n3,n1,n2,n3); //temp1=A21-A11//temp2=B11+B12
strassen(temp1,n2,temp2,n3,C+jump2*n1+n3,jump2,n1,n2,n3,temp1+n1*n2,temp2+n2*n3,n,n_); //C22=temp1*temp2
//M7
kernel7 <<<dim3(n_/xthread,n/xthread),dim3(xthread,xthread)>>> (A+n2,jump,jump*n1,B+jump1*n2,jump1,n3,temp1,n2,temp2,n3,n1,n2,n3);//temp1=A12-A22 //temp2=B21+B22
strassen(temp1,n2,temp2,n3,C+n3,jump2,n1,n2,n3,temp1+n1*n2,temp2+n2*n3,n,n_); //C12+=temp1*temp2
kernel2 <<<dim3(n_/xthread,(3*n1)/xthread),dim3(xthread,xthread)>>> (C,jump2,n3,jump2*n1+n3,temp1,n2,A+jump*n1,jump,n2,n2,n3); //C22+=C11//C11+=C12 //temp1=A21+A22 //C12=0
//M2
strassen(temp1,n2,B,jump1,C+jump2*n1,jump2,n1,n2,n3,temp1+n1*n2,temp2+n2*n3,n,n_); //C21=temp1*B11
kernel3 <<<dim3(n_/xthread,n1/xthread),dim3(xthread,xthread)>>> (C+jump2*n1,jump2,n3,temp1,n2,A,jump,n2,n2,n3); //C22-=C21 //temp1=A11+A12
//M5
strassen(temp1,n2,B+jump1*n2+n3,jump1,C+n3,jump2,n1,n2,n3,temp1+n1*n2,temp2+n2*n3,n,n_); //C12=temp1*B22
kernel6<<<dim3(n_/xthread,(3*n)/xthread),dim3(xthread,xthread)>>>(temp1,n2,C,jump2,n3,temp2,n3,B+n3,jump1,jump1*n2,n1,n2,n3); //C11-=C12 //temp2=B12-B22 //temp1=0
//M3
strassen(A,jump,temp2,n3,temp1,n3,n1,n2,n3,temp1+n1*n3,temp2+n2*n3,n,n_); //temp1=A11*temp2
kernel4 <<<dim3(n3/xthread,(2*n)/xthread),dim3(xthread,xthread)>>> (C+n3,jump2,jump2*n1,temp1,n2,temp2,n3,B,jump1,jump1*n2,n1,n2); //C12=C12+temp1//C22=C22+temp1 //temp2=B21-B11 //temp1=0
//M4
strassen(A+jump*n1+n2,jump,temp2,n3,temp1,n3,n1,n2,n3,temp1+n1*n3,temp2+n2*n3,n,n_); //temp1=A22*temp2
kernel5 <<<dim3(n3/xthread,n1/xthread),dim3(xthread,xthread)>>> (C,jump2,jump2*n1,temp1,n2); //C21=C21+temp1//C11=C11+temp1
}
}
//Square matrix multiplication
__global__ void kernel1_sq(float* A,int jump1,int n1,float* B,int jump2,int n2,float* C,float* D,int jump)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y+threadIdx.y;
C[col+jump*row]=A[col+jump1*row]+A[n1+col+jump1*row];
D[col+jump*row]=B[col+jump2*row]+B[n2+col+jump2*row];
}
__global__ void kernel7_sq(float* A,int jump1,int n1,float* B,int jump2,int n2,float* C,float* D,int jump)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y+threadIdx.y;
C[col+jump*row]=A[col+jump1*row]-A[n1+col+jump1*row];
D[col+jump*row]=B[col+jump2*row]+B[n2+col+jump2*row];
}
__global__ void kernel2_sq(float* A,int jump,int n1,int n2,float* B,int jump1,float* C,int jump2,int n3)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
if(3*blockIdx.y<gridDim.y)
{
int point=col+(blockIdx.y * blockDim.y + threadIdx.y)*jump;
A[point+n2]+=A[point];
}
else if(3*blockIdx.y<2*gridDim.y)
{
int point=col+((blockIdx.y-gridDim.y/3) * blockDim.y + threadIdx.y)*jump;
A[point]+=A[point+n1];
A[point+n1]=0;
}
else
{
int row=(blockIdx.y-2*gridDim.y/3) * blockDim.y + threadIdx.y;
B[col+jump1*row]=C[col+jump2*row]+C[col+jump2*row+n3];
}
}
__global__ void kernel3_sq(float* A,int jump,int n,float* B,int jump1,float* C,int jump2,int n1)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
A[col+jump*row+n]-=A[col+jump*row];
B[col+jump1*row]=C[col+jump2*row]+C[col+jump2*row+n1];
}
__global__ void kernel4_sq(float* A,int jump,int n1,float* B,int jump1,float* C,int jump2,float* D,int jump3,int n2)
{
int col=blockIdx.x * blockDim.x+threadIdx.x,row;
if(2*blockIdx.y<gridDim.y)
{
row=blockIdx.y * blockDim.y + threadIdx.y;
A[col+jump*row]+=B[col+jump1*row];
A[col+jump*row+n1]+=B[col+jump1*row];
B[col+jump1*row]=0;
}
else
{
row=(blockIdx.y-gridDim.y/2) * blockDim.y + threadIdx.y;
C[col+jump2*row]=D[col+jump3*row+n2]-D[col+jump3*row];
}
}
__global__ void kernel6_sq(float* A,int jump,float* B,int jump1,int n1,float* C,int jump2,float* D,int jump3,int n2)
{
int col=blockIdx.x*blockDim.x+threadIdx.x;
if(3*blockIdx.y<gridDim.y)
{
int row=blockIdx.y*blockDim.y+threadIdx.y;
A[col+row*jump]=0;
}
else if(3*blockIdx.y<2*gridDim.y)
{
int row=(blockIdx.y-gridDim.y/3) * blockDim.y + threadIdx.y;
B[col+row*jump1]-=B[col+row*jump1+n1];
}
else
{
int row=(blockIdx.y-(2*gridDim.y/3)) * blockDim.y + threadIdx.y;
C[col+jump2*row]=D[col+jump3*row]-D[col+jump3*row+n2];
}
}
void strassen_sq(float* A,int jump,float* B,int jump1,float* C,int jump2,int n,float* temp1,float* temp2,int block_len)
{
if(n<=threshold)
multiply<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(A,B,C,jump,jump1,jump2,n/xthread);
else
{
n/=2;
block_len/=2;
kernel1_sq<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(A,jump,jump*n+n,B,jump1,jump1*n+n,temp1,temp2,n);
strassen_sq(temp1,n,temp2,n,C,jump2,n,temp1+n*n,temp2+n*n,block_len);
kernel7_sq<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(A+jump*n,jump,-jump*n,B,jump1,n,temp1,temp2,n);
strassen_sq(temp1,n,temp2,n,C+jump2*n+n,jump2,n,temp1+n*n,temp2+n*n,block_len);
kernel7_sq<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(A+n,jump,jump*n,B+jump1*n,jump1,n,temp1,temp2,n);
strassen_sq(temp1,n,temp2,n,C+n,jump2,n,temp1+n*n,temp2+n*n,block_len);
kernel2_sq<<<dim3(block_len,3*block_len),dim3(xthread,xthread)>>>(C,jump2,n,jump2*n+n,temp1,n,A+jump*n,jump,n);
strassen_sq(temp1,n,B,jump1,C+jump2*n,jump2,n,temp1+n*n,temp2+n*n,block_len);
kernel3_sq<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(C+jump2*n,jump2,n,temp1,n,A,jump,n);
strassen_sq(temp1,n,B+jump1*n+n,jump1,C+n,jump2,n,temp1+n*n,temp2+n*n,block_len);
kernel6_sq<<<dim3(block_len,3*block_len),dim3(xthread,xthread)>>>(temp1,n,C,jump2,n,temp2,n,B+n,jump1,jump1*n);
strassen_sq(A,jump,temp2,n,temp1,n,n,temp1+n*n,temp2+n*n,block_len);
kernel4_sq<<<dim3(block_len,2*block_len),dim3(xthread,xthread)>>>(C+n,jump2,jump2*n,temp1,n,temp2,n,B,jump1,jump1*n);
strassen_sq(A+jump*n+n,jump,temp2,n,temp1,n,n,temp1+n*n,temp2+n*n,block_len);
kernel5<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(C,jump2,jump2*n,temp1,n);
}
}
int nearest_ideal(int &n,int &temp)
{
int temp1=(xthread-n%xthread)%xthread;
int pow=1;
n+=temp1;
int m=n/xthread;
while(m>threshold/xthread)
{
if(m%2==1)
{
temp+=pow;
m++;
}
m/=2;
pow*=2;
}
n+=temp*xthread;
temp=temp*xthread;
temp+=temp1;
return pow;
}
int main(int argc,char** argv)
{
std::ifstream in(argv[1]);
std::ifstream in1(argv[2]);
std::ofstream out(argv[3]);
float *A,*B,*C;
int n1,n2,n3;
int temp1=0,temp2=0,temp3=0;
in>>n1>>n2;
in1>>n2>>n3;
out<<n1<<'\t'<<n3<<'\n';
int power=nearest_ideal(n1,temp1);
power=std::min(power,nearest_ideal(n2,temp2));
power=std::min(power,nearest_ideal(n3,temp3));
float factor=0;
for(int i=power;i>1;i/=2)
factor+=1/(float)(i*i);
A=new float[n1*n2];
B=new float[n2*n3];
C=new float[n1*n3];
for(int i=0; i<n1-temp1; i++)
{
for(int j=0; j<n2-temp2; j++)
in>>A[i*n2+j];
for(int j=n2-temp2;j<n2;j++)
A[i*n2+j]=0;
}
for(int i=(n1-temp1)*n2;i<n1*n2;i++)
A[i]=0;
in.close();
for(int i=0; i<n2-temp2; i++)
{
for(int j=0; j<n3-temp3; j++)
in1>>B[i*n3+j];
for(int j=n3-temp3;j<n3;j++)
B[i*n3+j]=0;
}
for(int i=(n2-temp2)*n3;i<n2*n3;i++)
B[i]=0;
in1.close();
struct timespec start,end;
int size_temp1,size_temp2,n_,n;
n=n2>n3?n2:n3;
n_=n1>n2?n1:n2;
size_temp1=(int)(n1*n_)*factor;
size_temp2=(int)(n2*n3)*factor;
float *d_A, *d_B, *d_C,*temp1_,*temp2_;
cudaMalloc( (void **) &d_A, sizeof(float)*n1*n2);
cudaMalloc( (void **) &d_B, sizeof(float)*n2*n3);
cudaMalloc( (void **) &d_C, sizeof(float)*n1*n3);
cudaMalloc( (void **) &temp1_,sizeof(float)*size_temp1);
cudaMalloc( (void **) &temp2_,sizeof(float)*size_temp2);
//copy from host to device
cudaMemcpy (d_A, A, sizeof(float)*n1*n2, cudaMemcpyHostToDevice);
cudaMemcpy (d_B, B, sizeof(float)*n2*n3, cudaMemcpyHostToDevice);
cudaMemset(d_C,0,sizeof(float)*n1*n3);
cudaMemset(temp1_,0,sizeof(float)*size_temp1);
cudaMemset(temp2_,0,sizeof(float)*size_temp2);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID,&start);
if(n1!=n2 || n3!=n2)
strassen(d_A,n2,d_B,n3,d_C,n3,n1,n2,n3,temp1_,temp2_,n,n_);
else
strassen_sq(d_A,n1,d_B,n1,d_C,n1,n1,temp1_,temp2_,n1/xthread);
cudaDeviceSynchronize();
clock_gettime(CLOCK_PROCESS_CPUTIME_ID,&end);
cudaMemcpy (C, d_C, sizeof(float)*n1*n3, cudaMemcpyDeviceToHost);
printf("Error %s \n",cudaGetErrorString(cudaGetLastError()));
double time_taken = (end.tv_nsec-start.tv_nsec)+1e+9*(end.tv_sec-start.tv_sec);
printf("StrassenRec - Time taken: %f\n",time_taken);
for(int i=0;i<n1-temp1;i++)
{
for(int j=0;j<n3-temp3;j++)
out<<C[i*n3+j]<<'\t';
out<<'\n';
}
std::ofstream ofile;
ofile.open(argv[4],std::ios_base::app);
ofile<<"strassenRec - Time taken (ns): "<<time_taken<<"\n";
ofile.close();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaFree(temp1_);
cudaFree(temp2_);
delete C,A,B;
} | #include<cstdio>
#include<fstream>
#include<cmath>
#include<hip/hip_runtime.h>
int threshold=256;
int xthread=32;
__global__ void multiply(float* A,float* B,float* C,int jump,int jump1,int jump2,int iter)
{
__shared__ float A1[32][32],B1[32][32];
int posy=blockIdx.y*blockDim.y+threadIdx.y;
int posx=blockIdx.x*blockDim.x+threadIdx.x;
int row=posy*jump+threadIdx.x;
int col=posx+threadIdx.y*jump1;
int place=posy*jump2+posx;
for(int i=0;i<iter;i++)
{
A1[threadIdx.y][threadIdx.x]=A[row];
B1[threadIdx.y][threadIdx.x]=B[col];
__syncthreads();
for(int i=0;i<blockDim.x;i++)
C[place]+=A1[threadIdx.y][i]*B1[i][threadIdx.x];
row+=blockDim.x;
col+=blockDim.y*jump1;
__syncthreads();
}
}
//non_square matrix multiplication
__global__ void kernel1(float* A,int jump1,int n1,float* B,int jump2,int n2,float* C,int jump3,float* D,int jump4,int m1,int m2,int m3)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y+threadIdx.y;
if(col<m2 && row<m1)
C[col+jump3*row]=A[col+jump1*row]+A[n1+col+jump1*row];
if(col<m3 && row<m2)
D[col+jump4*row]=B[col+jump2*row]+B[n2+col+jump2*row];
}
__global__ void kernel7(float* A,int jump1,int n1,float* B,int jump2,int n2,float* C,int jump3,float* D,int jump4,int m1,int m2,int m3)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y+threadIdx.y;
if(col<m2 && row<m1)
C[col+jump3*row]=A[col+jump1*row]-A[n1+col+jump1*row];
if(col<m3 && row<m2)
D[col+jump4*row]=B[col+jump2*row]+B[n2+col+jump2*row];
}
__global__ void kernel2(float* A,int jump,int n1,int n2,float* B,int jump1,float* C,int jump2,int n3,int m2,int m3)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
if(col<m3)
{
if(3*blockIdx.y<gridDim.y)
{
int point=col+(blockIdx.y * blockDim.y + threadIdx.y)*jump;
A[point+n2]+=A[point];
}
else if(3*blockIdx.y<2*gridDim.y)
{
int point=col+((blockIdx.y-gridDim.y/3) * blockDim.y + threadIdx.y)*jump;
A[point]+=A[point+n1];
A[point+n1]=0;
}
}
if(col<m2 && 3*blockIdx.y>=2*gridDim.y)
{
int row=(blockIdx.y-2*gridDim.y/3) * blockDim.y + threadIdx.y;
B[col+jump1*row]=C[col+jump2*row]+C[col+jump2*row+n3];
}
}
__global__ void kernel3(float* A,int jump,int n,float* B,int jump1,float* C,int jump2,int n1,int m2,int m3)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
if(col<m2)
A[col+jump*row+n]-=A[col+jump*row];
if(col<m3)
B[col+jump1*row]=C[col+jump2*row]+C[col+jump2*row+n1];
}
__global__ void kernel4(float* A,int jump,int n1,float* B,int jump1,float* C,int jump2,float* D,int jump3,int n2,int m1,int m2)
{
int col=blockIdx.x * blockDim.x+threadIdx.x,row;
if(2*blockIdx.y<gridDim.y)
{
row=blockIdx.y * blockDim.y + threadIdx.y;
if(row<m1)
{
A[col+jump*row]+=B[col+jump1*row];
A[col+jump*row+n1]+=B[col+jump1*row];
B[col+jump1*row]=0;
}
}
else
{
row=(blockIdx.y-gridDim.y/2) * blockDim.y + threadIdx.y;
if(row<m2)
C[col+jump2*row]=D[col+jump3*row+n2]-D[col+jump3*row];
}
}
__global__ void kernel5(float* A,int jump,int n1,float* B,int jump1)
{
int point=(blockIdx.x * blockDim.x+threadIdx.x)+(blockIdx.y * blockDim.y + threadIdx.y)*jump;
int point1=(blockIdx.x * blockDim.x+threadIdx.x)+(blockIdx.y * blockDim.y + threadIdx.y)*jump1;
A[point]+=B[point1];
A[point+n1]+=B[point1];
}
__global__ void kernel6(float* A,int jump,float* B,int jump1,int n1,float* C,int jump2,float* D,int jump3,int n2,int m1,int m2,int m3)
{
int col=blockIdx.x*blockDim.x+threadIdx.x;
if(col<m2 && 3*blockIdx.y<gridDim.y)
{
int row=blockIdx.y*blockDim.y+threadIdx.y;
if(row<m1)
A[col+row*jump]=0;
}
if(col<m3 && 3*blockIdx.y>=gridDim.y && 3*blockIdx.y<2*gridDim.y)
{
int row=(blockIdx.y-gridDim.y/3) * blockDim.y + threadIdx.y;
if(row<m1)
B[col+row*jump1]-=B[col+row*jump1+n1];
}
if(col<m3 && 3*blockIdx.y>2*gridDim.y)
{
int row=(blockIdx.y-(2*gridDim.y/3)) * blockDim.y + threadIdx.y;
if(row<m2)
C[col+jump2*row]=D[col+jump3*row]-D[col+jump3*row+n2];
}
}
void strassen(float* A,int jump,float* B,int jump1,float* C,int jump2,int n1,int n2,int n3,float* temp1,float* temp2,int n,int n_)
{
if(n1<=threshold || n2<=threshold || n3<=threshold)
{
multiply <<<dim3(n3/xthread,n1/xthread),dim3(xthread,xthread)>>> (A,B,C,jump,jump1,jump2,n2/xthread);
}
else
{
n1/=2;n2/=2;n3/=2;
n/=2;n_/=2;
//M1
kernel1 <<<dim3(n_/xthread,n/xthread),dim3(xthread,xthread)>>> (A,jump,jump*n1+n2,B,jump1,jump1*n2+n3,temp1,n2,temp2,n3,n1,n2,n3); //temp1=A11+A22 //temp2=B11+B22
strassen(temp1,n2,temp2,n3,C,jump2,n1,n2,n3,temp1+n1*n2,temp2+n2*n3,n,n_); //C11=temp1*temp2
//M6
kernel7 <<<dim3(n_/xthread,n/xthread),dim3(xthread,xthread)>>> (A+jump*n1,jump,-jump*n1,B,jump1,n3,temp1,n2,temp2,n3,n1,n2,n3); //temp1=A21-A11//temp2=B11+B12
strassen(temp1,n2,temp2,n3,C+jump2*n1+n3,jump2,n1,n2,n3,temp1+n1*n2,temp2+n2*n3,n,n_); //C22=temp1*temp2
//M7
kernel7 <<<dim3(n_/xthread,n/xthread),dim3(xthread,xthread)>>> (A+n2,jump,jump*n1,B+jump1*n2,jump1,n3,temp1,n2,temp2,n3,n1,n2,n3);//temp1=A12-A22 //temp2=B21+B22
strassen(temp1,n2,temp2,n3,C+n3,jump2,n1,n2,n3,temp1+n1*n2,temp2+n2*n3,n,n_); //C12+=temp1*temp2
kernel2 <<<dim3(n_/xthread,(3*n1)/xthread),dim3(xthread,xthread)>>> (C,jump2,n3,jump2*n1+n3,temp1,n2,A+jump*n1,jump,n2,n2,n3); //C22+=C11//C11+=C12 //temp1=A21+A22 //C12=0
//M2
strassen(temp1,n2,B,jump1,C+jump2*n1,jump2,n1,n2,n3,temp1+n1*n2,temp2+n2*n3,n,n_); //C21=temp1*B11
kernel3 <<<dim3(n_/xthread,n1/xthread),dim3(xthread,xthread)>>> (C+jump2*n1,jump2,n3,temp1,n2,A,jump,n2,n2,n3); //C22-=C21 //temp1=A11+A12
//M5
strassen(temp1,n2,B+jump1*n2+n3,jump1,C+n3,jump2,n1,n2,n3,temp1+n1*n2,temp2+n2*n3,n,n_); //C12=temp1*B22
kernel6<<<dim3(n_/xthread,(3*n)/xthread),dim3(xthread,xthread)>>>(temp1,n2,C,jump2,n3,temp2,n3,B+n3,jump1,jump1*n2,n1,n2,n3); //C11-=C12 //temp2=B12-B22 //temp1=0
//M3
strassen(A,jump,temp2,n3,temp1,n3,n1,n2,n3,temp1+n1*n3,temp2+n2*n3,n,n_); //temp1=A11*temp2
kernel4 <<<dim3(n3/xthread,(2*n)/xthread),dim3(xthread,xthread)>>> (C+n3,jump2,jump2*n1,temp1,n2,temp2,n3,B,jump1,jump1*n2,n1,n2); //C12=C12+temp1//C22=C22+temp1 //temp2=B21-B11 //temp1=0
//M4
strassen(A+jump*n1+n2,jump,temp2,n3,temp1,n3,n1,n2,n3,temp1+n1*n3,temp2+n2*n3,n,n_); //temp1=A22*temp2
kernel5 <<<dim3(n3/xthread,n1/xthread),dim3(xthread,xthread)>>> (C,jump2,jump2*n1,temp1,n2); //C21=C21+temp1//C11=C11+temp1
}
}
//Square matrix multiplication
__global__ void kernel1_sq(float* A,int jump1,int n1,float* B,int jump2,int n2,float* C,float* D,int jump)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y+threadIdx.y;
C[col+jump*row]=A[col+jump1*row]+A[n1+col+jump1*row];
D[col+jump*row]=B[col+jump2*row]+B[n2+col+jump2*row];
}
__global__ void kernel7_sq(float* A,int jump1,int n1,float* B,int jump2,int n2,float* C,float* D,int jump)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y+threadIdx.y;
C[col+jump*row]=A[col+jump1*row]-A[n1+col+jump1*row];
D[col+jump*row]=B[col+jump2*row]+B[n2+col+jump2*row];
}
__global__ void kernel2_sq(float* A,int jump,int n1,int n2,float* B,int jump1,float* C,int jump2,int n3)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
if(3*blockIdx.y<gridDim.y)
{
int point=col+(blockIdx.y * blockDim.y + threadIdx.y)*jump;
A[point+n2]+=A[point];
}
else if(3*blockIdx.y<2*gridDim.y)
{
int point=col+((blockIdx.y-gridDim.y/3) * blockDim.y + threadIdx.y)*jump;
A[point]+=A[point+n1];
A[point+n1]=0;
}
else
{
int row=(blockIdx.y-2*gridDim.y/3) * blockDim.y + threadIdx.y;
B[col+jump1*row]=C[col+jump2*row]+C[col+jump2*row+n3];
}
}
__global__ void kernel3_sq(float* A,int jump,int n,float* B,int jump1,float* C,int jump2,int n1)
{
int col=blockIdx.x * blockDim.x+threadIdx.x;
int row=blockIdx.y * blockDim.y + threadIdx.y;
A[col+jump*row+n]-=A[col+jump*row];
B[col+jump1*row]=C[col+jump2*row]+C[col+jump2*row+n1];
}
__global__ void kernel4_sq(float* A,int jump,int n1,float* B,int jump1,float* C,int jump2,float* D,int jump3,int n2)
{
int col=blockIdx.x * blockDim.x+threadIdx.x,row;
if(2*blockIdx.y<gridDim.y)
{
row=blockIdx.y * blockDim.y + threadIdx.y;
A[col+jump*row]+=B[col+jump1*row];
A[col+jump*row+n1]+=B[col+jump1*row];
B[col+jump1*row]=0;
}
else
{
row=(blockIdx.y-gridDim.y/2) * blockDim.y + threadIdx.y;
C[col+jump2*row]=D[col+jump3*row+n2]-D[col+jump3*row];
}
}
__global__ void kernel6_sq(float* A,int jump,float* B,int jump1,int n1,float* C,int jump2,float* D,int jump3,int n2)
{
int col=blockIdx.x*blockDim.x+threadIdx.x;
if(3*blockIdx.y<gridDim.y)
{
int row=blockIdx.y*blockDim.y+threadIdx.y;
A[col+row*jump]=0;
}
else if(3*blockIdx.y<2*gridDim.y)
{
int row=(blockIdx.y-gridDim.y/3) * blockDim.y + threadIdx.y;
B[col+row*jump1]-=B[col+row*jump1+n1];
}
else
{
int row=(blockIdx.y-(2*gridDim.y/3)) * blockDim.y + threadIdx.y;
C[col+jump2*row]=D[col+jump3*row]-D[col+jump3*row+n2];
}
}
void strassen_sq(float* A,int jump,float* B,int jump1,float* C,int jump2,int n,float* temp1,float* temp2,int block_len)
{
if(n<=threshold)
multiply<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(A,B,C,jump,jump1,jump2,n/xthread);
else
{
n/=2;
block_len/=2;
kernel1_sq<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(A,jump,jump*n+n,B,jump1,jump1*n+n,temp1,temp2,n);
strassen_sq(temp1,n,temp2,n,C,jump2,n,temp1+n*n,temp2+n*n,block_len);
kernel7_sq<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(A+jump*n,jump,-jump*n,B,jump1,n,temp1,temp2,n);
strassen_sq(temp1,n,temp2,n,C+jump2*n+n,jump2,n,temp1+n*n,temp2+n*n,block_len);
kernel7_sq<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(A+n,jump,jump*n,B+jump1*n,jump1,n,temp1,temp2,n);
strassen_sq(temp1,n,temp2,n,C+n,jump2,n,temp1+n*n,temp2+n*n,block_len);
kernel2_sq<<<dim3(block_len,3*block_len),dim3(xthread,xthread)>>>(C,jump2,n,jump2*n+n,temp1,n,A+jump*n,jump,n);
strassen_sq(temp1,n,B,jump1,C+jump2*n,jump2,n,temp1+n*n,temp2+n*n,block_len);
kernel3_sq<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(C+jump2*n,jump2,n,temp1,n,A,jump,n);
strassen_sq(temp1,n,B+jump1*n+n,jump1,C+n,jump2,n,temp1+n*n,temp2+n*n,block_len);
kernel6_sq<<<dim3(block_len,3*block_len),dim3(xthread,xthread)>>>(temp1,n,C,jump2,n,temp2,n,B+n,jump1,jump1*n);
strassen_sq(A,jump,temp2,n,temp1,n,n,temp1+n*n,temp2+n*n,block_len);
kernel4_sq<<<dim3(block_len,2*block_len),dim3(xthread,xthread)>>>(C+n,jump2,jump2*n,temp1,n,temp2,n,B,jump1,jump1*n);
strassen_sq(A+jump*n+n,jump,temp2,n,temp1,n,n,temp1+n*n,temp2+n*n,block_len);
kernel5<<<dim3(block_len,block_len),dim3(xthread,xthread)>>>(C,jump2,jump2*n,temp1,n);
}
}
int nearest_ideal(int &n,int &temp)
{
int temp1=(xthread-n%xthread)%xthread;
int pow=1;
n+=temp1;
int m=n/xthread;
while(m>threshold/xthread)
{
if(m%2==1)
{
temp+=pow;
m++;
}
m/=2;
pow*=2;
}
n+=temp*xthread;
temp=temp*xthread;
temp+=temp1;
return pow;
}
int main(int argc,char** argv)
{
std::ifstream in(argv[1]);
std::ifstream in1(argv[2]);
std::ofstream out(argv[3]);
float *A,*B,*C;
int n1,n2,n3;
int temp1=0,temp2=0,temp3=0;
in>>n1>>n2;
in1>>n2>>n3;
out<<n1<<'\t'<<n3<<'\n';
int power=nearest_ideal(n1,temp1);
power=std::min(power,nearest_ideal(n2,temp2));
power=std::min(power,nearest_ideal(n3,temp3));
float factor=0;
for(int i=power;i>1;i/=2)
factor+=1/(float)(i*i);
A=new float[n1*n2];
B=new float[n2*n3];
C=new float[n1*n3];
for(int i=0; i<n1-temp1; i++)
{
for(int j=0; j<n2-temp2; j++)
in>>A[i*n2+j];
for(int j=n2-temp2;j<n2;j++)
A[i*n2+j]=0;
}
for(int i=(n1-temp1)*n2;i<n1*n2;i++)
A[i]=0;
in.close();
for(int i=0; i<n2-temp2; i++)
{
for(int j=0; j<n3-temp3; j++)
in1>>B[i*n3+j];
for(int j=n3-temp3;j<n3;j++)
B[i*n3+j]=0;
}
for(int i=(n2-temp2)*n3;i<n2*n3;i++)
B[i]=0;
in1.close();
struct timespec start,end;
int size_temp1,size_temp2,n_,n;
n=n2>n3?n2:n3;
n_=n1>n2?n1:n2;
size_temp1=(int)(n1*n_)*factor;
size_temp2=(int)(n2*n3)*factor;
float *d_A, *d_B, *d_C,*temp1_,*temp2_;
hipMalloc( (void **) &d_A, sizeof(float)*n1*n2);
hipMalloc( (void **) &d_B, sizeof(float)*n2*n3);
hipMalloc( (void **) &d_C, sizeof(float)*n1*n3);
hipMalloc( (void **) &temp1_,sizeof(float)*size_temp1);
hipMalloc( (void **) &temp2_,sizeof(float)*size_temp2);
//copy from host to device
hipMemcpy (d_A, A, sizeof(float)*n1*n2, hipMemcpyHostToDevice);
hipMemcpy (d_B, B, sizeof(float)*n2*n3, hipMemcpyHostToDevice);
hipMemset(d_C,0,sizeof(float)*n1*n3);
hipMemset(temp1_,0,sizeof(float)*size_temp1);
hipMemset(temp2_,0,sizeof(float)*size_temp2);
clock_gettime(CLOCK_PROCESS_CPUTIME_ID,&start);
if(n1!=n2 || n3!=n2)
strassen(d_A,n2,d_B,n3,d_C,n3,n1,n2,n3,temp1_,temp2_,n,n_);
else
strassen_sq(d_A,n1,d_B,n1,d_C,n1,n1,temp1_,temp2_,n1/xthread);
hipDeviceSynchronize();
clock_gettime(CLOCK_PROCESS_CPUTIME_ID,&end);
hipMemcpy (C, d_C, sizeof(float)*n1*n3, hipMemcpyDeviceToHost);
printf("Error %s \n",hipGetErrorString(hipGetLastError()));
double time_taken = (end.tv_nsec-start.tv_nsec)+1e+9*(end.tv_sec-start.tv_sec);
printf("StrassenRec - Time taken: %f\n",time_taken);
for(int i=0;i<n1-temp1;i++)
{
for(int j=0;j<n3-temp3;j++)
out<<C[i*n3+j]<<'\t';
out<<'\n';
}
std::ofstream ofile;
ofile.open(argv[4],std::ios_base::app);
ofile<<"strassenRec - Time taken (ns): "<<time_taken<<"\n";
ofile.close();
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipFree(temp1_);
hipFree(temp2_);
delete C,A,B;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define N 2560
#define M 512
#define BLOCK_SIZE (N/M)
#define RADIUS 5
__global__ void add(double *a, double *b, double *c, int n){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if(idx < n){
c[idx] = a[idx] + b[idx];
}
} | code for sm_80
Function : _Z3addPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R8, R3, c[0x0][0x0], R8 ; /* 0x0000000003087a24 */
/* 0x001fca00078e0208 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define N 2560
#define M 512
#define BLOCK_SIZE (N/M)
#define RADIUS 5
__global__ void add(double *a, double *b, double *c, int n){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if(idx < n){
c[idx] = a[idx] + b[idx];
}
} | .file "tmpxft_000757e1_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPdS_S_iPdS_S_i
.type _Z27__device_stub__Z3addPdS_S_iPdS_S_i, @function
_Z27__device_stub__Z3addPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addPdS_S_iPdS_S_i, .-_Z27__device_stub__Z3addPdS_S_iPdS_S_i
.globl _Z3addPdS_S_i
.type _Z3addPdS_S_i, @function
_Z3addPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPdS_S_i, .-_Z3addPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define N 2560
#define M 512
#define BLOCK_SIZE (N/M)
#define RADIUS 5
__global__ void add(double *a, double *b, double *c, int n){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if(idx < n){
c[idx] = a[idx] + b[idx];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 2560
#define M 512
#define BLOCK_SIZE (N/M)
#define RADIUS 5
__global__ void add(double *a, double *b, double *c, int n){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if(idx < n){
c[idx] = a[idx] + b[idx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 2560
#define M 512
#define BLOCK_SIZE (N/M)
#define RADIUS 5
__global__ void add(double *a, double *b, double *c, int n){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if(idx < n){
c[idx] = a[idx] + b[idx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdS_S_i
.globl _Z3addPdS_S_i
.p2align 8
.type _Z3addPdS_S_i,@function
_Z3addPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPdS_S_i, .Lfunc_end0-_Z3addPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 2560
#define M 512
#define BLOCK_SIZE (N/M)
#define RADIUS 5
__global__ void add(double *a, double *b, double *c, int n){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if(idx < n){
c[idx] = a[idx] + b[idx];
}
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPdS_S_i # -- Begin function _Z18__device_stub__addPdS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPdS_S_i,@function
_Z18__device_stub__addPdS_S_i: # @_Z18__device_stub__addPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPdS_S_i, .Lfunc_end0-_Z18__device_stub__addPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPdS_S_i,@object # @_Z3addPdS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPdS_S_i
.p2align 3, 0x0
_Z3addPdS_S_i:
.quad _Z18__device_stub__addPdS_S_i
.size _Z3addPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPdS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R8, R3, c[0x0][0x0], R8 ; /* 0x0000000003087a24 */
/* 0x001fca00078e0208 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdS_S_i
.globl _Z3addPdS_S_i
.p2align 8
.type _Z3addPdS_S_i,@function
_Z3addPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPdS_S_i, .Lfunc_end0-_Z3addPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000757e1_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPdS_S_iPdS_S_i
.type _Z27__device_stub__Z3addPdS_S_iPdS_S_i, @function
_Z27__device_stub__Z3addPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addPdS_S_iPdS_S_i, .-_Z27__device_stub__Z3addPdS_S_iPdS_S_i
.globl _Z3addPdS_S_i
.type _Z3addPdS_S_i, @function
_Z3addPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPdS_S_i, .-_Z3addPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPdS_S_i # -- Begin function _Z18__device_stub__addPdS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPdS_S_i,@function
_Z18__device_stub__addPdS_S_i: # @_Z18__device_stub__addPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPdS_S_i, .Lfunc_end0-_Z18__device_stub__addPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPdS_S_i,@object # @_Z3addPdS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPdS_S_i
.p2align 3, 0x0
_Z3addPdS_S_i:
.quad _Z18__device_stub__addPdS_S_i
.size _Z3addPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPdS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "softmax-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SoftmaxCrossEntropyGrad::SoftmaxCrossEntropyGrad(Op* y, Op* logits)
: Op("softmax_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SoftmaxCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(rows * cols);
auto out_node = rt::Node::op_softmax_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
rows, cols,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "softmax-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SoftmaxCrossEntropyGrad::SoftmaxCrossEntropyGrad(Op* y, Op* logits)
: Op("softmax_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SoftmaxCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(rows * cols);
auto out_node = rt::Node::op_softmax_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
rows, cols,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .file "tmpxft_00118212_00000000-6_softmax-cross-entropy-grad.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4620:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4620:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops23SoftmaxCrossEntropyGradD2Ev,"axG",@progbits,_ZN3ops23SoftmaxCrossEntropyGradD5Ev,comdat
.align 2
.weak _ZN3ops23SoftmaxCrossEntropyGradD2Ev
.type _ZN3ops23SoftmaxCrossEntropyGradD2Ev, @function
_ZN3ops23SoftmaxCrossEntropyGradD2Ev:
.LFB5632:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5632:
.size _ZN3ops23SoftmaxCrossEntropyGradD2Ev, .-_ZN3ops23SoftmaxCrossEntropyGradD2Ev
.weak _ZN3ops23SoftmaxCrossEntropyGradD1Ev
.set _ZN3ops23SoftmaxCrossEntropyGradD1Ev,_ZN3ops23SoftmaxCrossEntropyGradD2Ev
.section .text._ZN3ops23SoftmaxCrossEntropyGradD0Ev,"axG",@progbits,_ZN3ops23SoftmaxCrossEntropyGradD5Ev,comdat
.align 2
.weak _ZN3ops23SoftmaxCrossEntropyGradD0Ev
.type _ZN3ops23SoftmaxCrossEntropyGradD0Ev, @function
_ZN3ops23SoftmaxCrossEntropyGradD0Ev:
.LFB5634:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $112, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5634:
.size _ZN3ops23SoftmaxCrossEntropyGradD0Ev, .-_ZN3ops23SoftmaxCrossEntropyGradD0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4643:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4643:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4947:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4947:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4982:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4982:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.type _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_, @function
_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_:
.LFB4615:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4615
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movl $16, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, 16(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 32(%rsp)
movq %rbx, (%rax)
movq %r12, 8(%rax)
movq %rdx, 24(%rsp)
movq %rbx, %rdi
.LEHB1:
call _ZNK3ops2Op9shape_getEv@PLT
movq %rax, %rbx
leaq 80(%rsp), %rdi
leaq 96(%rsp), %rax
movq %rax, 80(%rsp)
movq $26, 8(%rsp)
leaq 8(%rsp), %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE1:
jmp .L47
.L43:
endbr64
movq %rax, %rbx
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L33
call _ZdlPvm@PLT
.L33:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L47:
movq %rax, 80(%rsp)
movq 8(%rsp), %rdx
movq %rdx, 96(%rsp)
movabsq $6879355553540632435, %rsi
movabsq $7954869266282410595, %rdi
movq %rsi, (%rax)
movq %rdi, 8(%rax)
movabsq $8247338199294374767, %rsi
movabsq $7233188264842719343, %rdi
movq %rsi, 10(%rax)
movq %rdi, 18(%rax)
movq %rdx, 88(%rsp)
movq 80(%rsp), %rax
movb $0, (%rax,%rdx)
leaq 16(%rsp), %rcx
leaq 80(%rsp), %rsi
leaq 48(%rsp), %r8
movq %rbx, %rdx
movq %rbp, %rdi
.LEHB2:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE2:
movq 80(%rsp), %rdi
leaq 96(%rsp), %rax
cmpq %rax, %rdi
je .L34
movq 96(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L34:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .L35
movq 32(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L35:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .L36
movq 64(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L36:
leaq 16+_ZTVN3ops23SoftmaxCrossEntropyGradE(%rip), %rax
movq %rax, 0(%rbp)
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L38:
leaq 16(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
jmp .L33
.L41:
endbr64
movq %rax, %rbx
jmp .L38
.L39:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4615:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4615:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4615-.LLSDACSB4615
.LLSDACSB4615:
.uleb128 .LEHB0-.LFB4615
.uleb128 .LEHE0-.LEHB0
.uleb128 .L43-.LFB4615
.uleb128 0
.uleb128 .LEHB1-.LFB4615
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB4615
.uleb128 0
.uleb128 .LEHB2-.LFB4615
.uleb128 .LEHE2-.LEHB2
.uleb128 .L42-.LFB4615
.uleb128 0
.uleb128 .LEHB3-.LFB4615
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4615:
.text
.size _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_, .-_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.globl _ZN3ops23SoftmaxCrossEntropyGradC1EPNS_2OpES2_
.set _ZN3ops23SoftmaxCrossEntropyGradC1EPNS_2OpES2_,_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.section .text._ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev:
.LFB5162:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L52
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L52:
ret
.cfi_endproc
.LFE5162:
.size _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.type _ZN3ops23SoftmaxCrossEntropyGrad7compileEv, @function
_ZN3ops23SoftmaxCrossEntropyGrad7compileEv:
.LFB4617:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4617
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r13
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB4:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %rbx
movq %rax, -168(%rbp)
leaq -80(%rbp), %rdi
movq %r13, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE4:
movq -80(%rbp), %rax
movq (%rax), %rsi
movq %rbx, %rdi
.LEHB5:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE5:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L56
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L56:
leaq -80(%rbp), %rdi
movq %r13, %rsi
.LEHB6:
call _ZN3ops2Op5predsEv@PLT
.LEHE6:
movq -80(%rbp), %rax
movq 8(%rax), %rsi
movq -168(%rbp), %rdi
.LEHB7:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE7:
movq %rax, -152(%rbp)
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L57
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L57:
leaq 64(%rbx), %r15
movl $0, %esi
movq %r15, %rdi
.LEHB8:
call _ZNK3ops5ShapeixEm@PLT
movslq %eax, %r14
movl $1, %esi
movq %r15, %rdi
call _ZNK3ops5ShapeixEm@PLT
movslq %eax, %r15
movq 72(%rbx), %r12
movq $0, -144(%rbp)
movq $0, -136(%rbp)
movq $0, -128(%rbp)
subq 64(%rbx), %r12
je .L86
movabsq $9223372036854775804, %rax
cmpq %r12, %rax
jb .L99
movq %r12, %rdi
call _Znwm@PLT
.LEHE8:
movq %rax, -160(%rbp)
.L58:
movq -160(%rbp), %rdi
movq %rdi, -144(%rbp)
movq %rdi, -136(%rbp)
addq %rdi, %r12
movq %r12, -128(%rbp)
movq 64(%rbx), %rsi
movq 72(%rbx), %r12
subq %rsi, %r12
cmpq $4, %r12
jle .L61
movq %r12, %rdx
call memmove@PLT
.L62:
movq -160(%rbp), %rax
addq %r12, %rax
movq %rax, -136(%rbp)
movq %r14, %rdi
imulq %r15, %rdi
.LEHB9:
call _Z12tensor_allocm@PLT
.LEHE9:
jmp .L100
.L99:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L101
.LEHB10:
call _ZSt28__throw_bad_array_new_lengthv@PLT
.LEHE10:
.L101:
call __stack_chk_fail@PLT
.L86:
movq $0, -160(%rbp)
jmp .L58
.L61:
jne .L62
movl (%rsi), %eax
movq -160(%rbp), %rcx
movl %eax, (%rcx)
jmp .L62
.L100:
movq %rax, -160(%rbp)
movq 56(%rbx), %r12
movq -152(%rbp), %rcx
movq 56(%rcx), %rsi
movq %rsi, -176(%rbp)
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $16, %edi
.LEHB11:
call _Znwm@PLT
.LEHE11:
movq %rax, -80(%rbp)
leaq 16(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r12, (%rax)
movq -176(%rbp), %rsi
movq %rsi, 8(%rax)
movq %rdx, -72(%rbp)
movq -152(%rbp), %rcx
movq 88(%rcx), %rsi
movq 88(%rbx), %rdi
leaq -80(%rbp), %r9
movq %r15, %r8
movq %r14, %rcx
movq -160(%rbp), %rdx
.LEHB12:
call _ZN2rt4Node29op_softmax_cross_entropy_gradEPKfS2_PfmmRKSt6vectorIPS0_SaIS5_EE@PLT
.LEHE12:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L66
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L66:
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB13:
call _Znwm@PLT
.LEHE13:
jmp .L102
.L92:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L65:
movq -144(%rbp), %rdi
movq -128(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L83
call _ZdlPvm@PLT
.L83:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L84
call __stack_chk_fail@PLT
.L102:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq -160(%rbp), %r14
movq %r14, (%rax)
movq %rdx, -72(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
movl $8, %edi
.LEHB14:
call _Znwm@PLT
.LEHE14:
movq %rax, -112(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -96(%rbp)
movq %rbx, (%rax)
movq %rdx, -104(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r14
leaq -144(%rbp), %r9
movq %rbx, %r8
movq %r13, %rsi
movq -168(%rbp), %rdi
.LEHB15:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE15:
jmp .L103
.L93:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L65
call _ZdlPvm@PLT
jmp .L65
.L103:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L73
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L73:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L74
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L74:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L55
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L55:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L104
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L94:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L72:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L65
call _ZdlPvm@PLT
jmp .L65
.L87:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L77
call __stack_chk_fail@PLT
.L77:
movq %rbx, %rdi
.LEHB16:
call _Unwind_Resume@PLT
.L88:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L79
call __stack_chk_fail@PLT
.L79:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L90:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L65
.L91:
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L72
.L89:
endbr64
movq %rax, %rbx
jmp .L65
.L84:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE16:
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4617:
.section .gcc_except_table
.LLSDA4617:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4617-.LLSDACSB4617
.LLSDACSB4617:
.uleb128 .LEHB4-.LFB4617
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4617
.uleb128 .LEHE5-.LEHB5
.uleb128 .L87-.LFB4617
.uleb128 0
.uleb128 .LEHB6-.LFB4617
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4617
.uleb128 .LEHE7-.LEHB7
.uleb128 .L88-.LFB4617
.uleb128 0
.uleb128 .LEHB8-.LFB4617
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB4617
.uleb128 .LEHE9-.LEHB9
.uleb128 .L89-.LFB4617
.uleb128 0
.uleb128 .LEHB10-.LFB4617
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB4617
.uleb128 .LEHE11-.LEHB11
.uleb128 .L92-.LFB4617
.uleb128 0
.uleb128 .LEHB12-.LFB4617
.uleb128 .LEHE12-.LEHB12
.uleb128 .L90-.LFB4617
.uleb128 0
.uleb128 .LEHB13-.LFB4617
.uleb128 .LEHE13-.LEHB13
.uleb128 .L93-.LFB4617
.uleb128 0
.uleb128 .LEHB14-.LFB4617
.uleb128 .LEHE14-.LEHB14
.uleb128 .L94-.LFB4617
.uleb128 0
.uleb128 .LEHB15-.LFB4617
.uleb128 .LEHE15-.LEHB15
.uleb128 .L91-.LFB4617
.uleb128 0
.uleb128 .LEHB16-.LFB4617
.uleb128 .LEHE16-.LEHB16
.uleb128 0
.uleb128 0
.LLSDACSE4617:
.text
.size _ZN3ops23SoftmaxCrossEntropyGrad7compileEv, .-_ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.weak _ZTSN3ops23SoftmaxCrossEntropyGradE
.section .rodata._ZTSN3ops23SoftmaxCrossEntropyGradE,"aG",@progbits,_ZTSN3ops23SoftmaxCrossEntropyGradE,comdat
.align 32
.type _ZTSN3ops23SoftmaxCrossEntropyGradE, @object
.size _ZTSN3ops23SoftmaxCrossEntropyGradE, 32
_ZTSN3ops23SoftmaxCrossEntropyGradE:
.string "N3ops23SoftmaxCrossEntropyGradE"
.weak _ZTIN3ops23SoftmaxCrossEntropyGradE
.section .data.rel.ro._ZTIN3ops23SoftmaxCrossEntropyGradE,"awG",@progbits,_ZTIN3ops23SoftmaxCrossEntropyGradE,comdat
.align 8
.type _ZTIN3ops23SoftmaxCrossEntropyGradE, @object
.size _ZTIN3ops23SoftmaxCrossEntropyGradE, 24
_ZTIN3ops23SoftmaxCrossEntropyGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops23SoftmaxCrossEntropyGradE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops23SoftmaxCrossEntropyGradE
.section .data.rel.ro._ZTVN3ops23SoftmaxCrossEntropyGradE,"awG",@progbits,_ZTVN3ops23SoftmaxCrossEntropyGradE,comdat
.align 8
.type _ZTVN3ops23SoftmaxCrossEntropyGradE, @object
.size _ZTVN3ops23SoftmaxCrossEntropyGradE, 48
_ZTVN3ops23SoftmaxCrossEntropyGradE:
.quad 0
.quad _ZTIN3ops23SoftmaxCrossEntropyGradE
.quad _ZN3ops23SoftmaxCrossEntropyGradD1Ev
.quad _ZN3ops23SoftmaxCrossEntropyGradD0Ev
.quad _ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "softmax-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SoftmaxCrossEntropyGrad::SoftmaxCrossEntropyGrad(Op* y, Op* logits)
: Op("softmax_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SoftmaxCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(rows * cols);
auto out_node = rt::Node::op_softmax_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
rows, cols,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | #include <hip/hip_runtime.h>
#include "softmax-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SoftmaxCrossEntropyGrad::SoftmaxCrossEntropyGrad(Op* y, Op* logits)
: Op("softmax_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SoftmaxCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(rows * cols);
auto out_node = rt::Node::op_softmax_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
rows, cols,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "softmax-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SoftmaxCrossEntropyGrad::SoftmaxCrossEntropyGrad(Op* y, Op* logits)
: Op("softmax_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SoftmaxCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(rows * cols);
auto out_node = rt::Node::op_softmax_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
rows, cols,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "softmax-cross-entropy-grad.hh"
#include "graph.hh"
#include "../runtime/node.hh"
#include "../memory/alloc.hh"
namespace ops
{
SoftmaxCrossEntropyGrad::SoftmaxCrossEntropyGrad(Op* y, Op* logits)
: Op("softmax_cross_entropy_grad", y->shape_get(), {y, logits})
{}
void SoftmaxCrossEntropyGrad::compile()
{
auto& g = Graph::instance();
auto& cy = g.compiled(preds()[0]);
auto& clogits = g.compiled(preds()[1]);
std::size_t rows = cy.out_shape[0];
std::size_t cols = cy.out_shape[1];
Shape out_shape = cy.out_shape;
dbl_t* out_data = tensor_alloc(rows * cols);
auto out_node = rt::Node::op_softmax_cross_entropy_grad(cy.out_data, clogits.out_data, out_data,
rows, cols,
{cy.out_node, clogits.out_node});
g.add_compiled(this, {out_node}, {out_data}, out_node, out_shape, out_data);
}
} | .text
.file "softmax-cross-entropy-grad.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.LCPI0_0:
.zero 16
.text
.globl _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.p2align 4, 0x90
.type _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_,@function
_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_: # @_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
leaq 48(%rsp), %r13
movq %r13, 32(%rsp)
movl $27, %edi
callq _Znwm
movq %rax, 32(%rsp)
movq $26, 48(%rsp)
movups .L.str(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str+10(%rip), %xmm0
movups %xmm0, 10(%rax)
movq $26, 40(%rsp)
movb $0, 26(%rax)
.Ltmp0:
movq %r15, %rdi
callq _ZNK3ops2Op9shape_getEv
.Ltmp1:
# %bb.1:
movq %rax, %r12
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp3:
movl $16, %edi
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, (%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 16(%rsp)
movq %r15, (%rax)
movq %r14, 8(%rax)
movq %rcx, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp6:
leaq 32(%rsp), %rsi
movq %rsp, %rcx
leaq 64(%rsp), %r8
movq %rbx, %rdi
movq %r12, %rdx
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp7:
# %bb.3:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_5
# %bb.4:
callq _ZdlPv
.LBB0_5: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_7
# %bb.6:
callq _ZdlPv
.LBB0_7: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit16
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_9
# %bb.8: # %.critedge.i.i
callq _ZdlPv
.LBB0_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops23SoftmaxCrossEntropyGradE+16, (%rbx)
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 144
.Ltmp8:
movq %rax, %rbx
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_14
# %bb.13:
callq _ZdlPv
jmp .LBB0_14
.LBB0_10:
.Ltmp5:
movq %rax, %rbx
.LBB0_14: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit19
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_16
# %bb.15:
callq _ZdlPv
jmp .LBB0_16
.LBB0_11:
.Ltmp2:
movq %rax, %rbx
.LBB0_16: # %.body
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_18
# %bb.17: # %.critedge.i.i23
callq _ZdlPv
.LBB0_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit25
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_, .Lfunc_end0-_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.p2align 4, 0x90
.type _ZN3ops23SoftmaxCrossEntropyGrad7compileEv,@function
_ZN3ops23SoftmaxCrossEntropyGrad7compileEv: # @_ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbp
callq _ZN3ops5Graph8instanceEv
movq %rax, %rbx
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq _ZN3ops2Op5predsEv
movq 16(%rsp), %rax
movq (%rax), %rsi
.Ltmp9:
movq %rbx, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp10:
# %bb.1:
movq %rax, %r15
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq _ZN3ops2Op5predsEv
movq 16(%rsp), %rax
movq 8(%rax), %rsi
.Ltmp12:
movq %rbx, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp13:
# %bb.4:
movq %rax, 160(%rsp) # 8-byte Spill
movq %rbx, 152(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_6
# %bb.5:
callq _ZdlPv
.LBB1_6: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit41
movq %r15, %r14
addq $64, %r14
xorl %r13d, %r13d
movq %r14, %rdi
xorl %esi, %esi
callq _ZNK3ops5ShapeixEm
movl %eax, %ebx
movl $1, %esi
movq %r14, %rdi
callq _ZNK3ops5ShapeixEm
movl %eax, %r14d
movq 72(%r15), %rdi
movq 64(%r15), %rax
movq %rdi, %r12
subq %rax, %r12
sarq $2, %r12
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
subq %rax, %rdi
je .LBB1_9
# %bb.7:
movq %r12, %rax
shrq $61, %rax
jne .LBB1_28
# %bb.8: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i.i.i.i
callq _Znwm
movq %rax, %r13
.LBB1_9: # %_ZNSt12_Vector_baseIiSaIiEEC2EmRKS0_.exit.i.i
movq %rbp, 136(%rsp) # 8-byte Spill
movslq %ebx, %rbp
movslq %r14d, %rbx
movq %r13, 16(%rsp)
movq %r13, 24(%rsp)
leaq (%r13,%r12,4), %rax
movq %rax, 32(%rsp)
movq 64(%r15), %rsi
movq 72(%r15), %r14
subq %rsi, %r14
cmpq $5, %r14
jl .LBB1_26
# %bb.10:
movq %r13, %rdi
movq %r14, %rdx
callq memmove@PLT
.LBB1_11: # %_ZN3ops5ShapeC2ERKS0_.exit
addq %r14, %r13
movq %r13, 24(%rsp)
movq %rbx, 144(%rsp) # 8-byte Spill
movq %rbx, %rdi
imulq %rbp, %rdi
.Ltmp15:
callq _Z12tensor_allocm
.Ltmp16:
# %bb.12:
movq %rax, %r13
movq 88(%r15), %r14
movq 160(%rsp), %rax # 8-byte Reload
movq 88(%rax), %r12
movq 56(%r15), %r15
movq 56(%rax), %rbx
xorps %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movq $0, 128(%rsp)
.Ltmp18:
movl $16, %edi
callq _Znwm
.Ltmp19:
# %bb.13: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, 112(%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 128(%rsp)
movq %r15, (%rax)
movq %rbx, 8(%rax)
movq %rcx, 120(%rsp)
.Ltmp21:
leaq 112(%rsp), %r9
movq %r14, %rdi
movq %r12, %rsi
movq %r13, %rdx
movq %rbp, %rcx
movq 144(%rsp), %r8 # 8-byte Reload
callq _ZN2rt4Node29op_softmax_cross_entropy_gradEPKfS2_PfmmRKSt6vectorIPS0_SaIS5_EE
.Ltmp22:
# %bb.14:
movq %rax, %rbx
movq 112(%rsp), %rdi
testq %rdi, %rdi
movq 136(%rsp), %r14 # 8-byte Reload
je .LBB1_16
# %bb.15:
callq _ZdlPv
.LBB1_16: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movq $0, 96(%rsp)
.Ltmp24:
movl $8, %edi
callq _Znwm
.Ltmp25:
# %bb.17: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit48
movq %rax, 80(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 96(%rsp)
movq %rbx, (%rax)
movq %rcx, 88(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movq $0, 64(%rsp)
.Ltmp27:
movl $8, %edi
callq _Znwm
.Ltmp28:
# %bb.18: # %_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_.exit
movq %rax, 48(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 64(%rsp)
movq %r13, (%rax)
movq %rcx, 56(%rsp)
.Ltmp30:
movq %r13, (%rsp)
leaq 80(%rsp), %rdx
leaq 48(%rsp), %rcx
leaq 16(%rsp), %r9
movq 152(%rsp), %rdi # 8-byte Reload
movq %r14, %rsi
movq %rbx, %r8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp31:
# %bb.19:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_21
# %bb.20:
callq _ZdlPv
.LBB1_21: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_23
# %bb.22:
callq _ZdlPv
.LBB1_23: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit56
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_25
# %bb.24:
callq _ZdlPv
.LBB1_25: # %_ZN3ops5ShapeD2Ev.exit
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_26:
.cfi_def_cfa_offset 224
cmpq $4, %r14
jne .LBB1_11
# %bb.27:
movl (%rsi), %eax
movl %eax, (%r13)
jmp .LBB1_11
.LBB1_28:
shrq $62, %r12
je .LBB1_30
# %bb.29: # %.noexc.i.i.i
callq _ZSt28__throw_bad_array_new_lengthv
.LBB1_30: # %.noexc4.i.i.i
callq _ZSt17__throw_bad_allocv
.LBB1_31:
.Ltmp32:
jmp .LBB1_33
.LBB1_32:
.Ltmp29:
.LBB1_33:
movq %rax, %rbx
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_36
# %bb.34: # %.body50.sink.split
callq _ZdlPv
jmp .LBB1_36
.LBB1_35:
.Ltmp26:
movq %rax, %rbx
.LBB1_36: # %.body50
movq 80(%rsp), %rdi
jmp .LBB1_40
.LBB1_37:
.Ltmp23:
jmp .LBB1_39
.LBB1_38:
.Ltmp20:
.LBB1_39:
movq %rax, %rbx
movq 112(%rsp), %rdi
.LBB1_40: # %.body50
testq %rdi, %rdi
je .LBB1_46
# %bb.41:
callq _ZdlPv
jmp .LBB1_46
.LBB1_42:
.Ltmp17:
jmp .LBB1_45
.LBB1_43:
.Ltmp14:
jmp .LBB1_45
.LBB1_44:
.Ltmp11:
.LBB1_45: # %.body46
movq %rax, %rbx
.LBB1_46: # %.body46
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_48
# %bb.47:
callq _ZdlPv
.LBB1_48:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops23SoftmaxCrossEntropyGrad7compileEv, .Lfunc_end1-_ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin1 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp13 # Call between .Ltmp13 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin1 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin1 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin1 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin1 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin1 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin1 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Lfunc_end1-.Ltmp31 # Call between .Ltmp31 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq _ZdlPv
.LBB2_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq _ZdlPv
.LBB2_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq _ZdlPv
.LBB2_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB2_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3ops2OpD2Ev, .Lfunc_end2-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops23SoftmaxCrossEntropyGradD0Ev,"axG",@progbits,_ZN3ops23SoftmaxCrossEntropyGradD0Ev,comdat
.weak _ZN3ops23SoftmaxCrossEntropyGradD0Ev # -- Begin function _ZN3ops23SoftmaxCrossEntropyGradD0Ev
.p2align 4, 0x90
.type _ZN3ops23SoftmaxCrossEntropyGradD0Ev,@function
_ZN3ops23SoftmaxCrossEntropyGradD0Ev: # @_ZN3ops23SoftmaxCrossEntropyGradD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB3_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB3_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end3:
.size _ZN3ops23SoftmaxCrossEntropyGradD0Ev, .Lfunc_end3-_ZN3ops23SoftmaxCrossEntropyGradD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "softmax_cross_entropy_grad"
.size .L.str, 27
.type _ZTVN3ops23SoftmaxCrossEntropyGradE,@object # @_ZTVN3ops23SoftmaxCrossEntropyGradE
.section .rodata,"a",@progbits
.globl _ZTVN3ops23SoftmaxCrossEntropyGradE
.p2align 3, 0x0
_ZTVN3ops23SoftmaxCrossEntropyGradE:
.quad 0
.quad _ZTIN3ops23SoftmaxCrossEntropyGradE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops23SoftmaxCrossEntropyGradD0Ev
.quad _ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops23SoftmaxCrossEntropyGradE, 48
.type _ZTSN3ops23SoftmaxCrossEntropyGradE,@object # @_ZTSN3ops23SoftmaxCrossEntropyGradE
.globl _ZTSN3ops23SoftmaxCrossEntropyGradE
_ZTSN3ops23SoftmaxCrossEntropyGradE:
.asciz "N3ops23SoftmaxCrossEntropyGradE"
.size _ZTSN3ops23SoftmaxCrossEntropyGradE, 32
.type _ZTIN3ops23SoftmaxCrossEntropyGradE,@object # @_ZTIN3ops23SoftmaxCrossEntropyGradE
.globl _ZTIN3ops23SoftmaxCrossEntropyGradE
.p2align 3, 0x0
_ZTIN3ops23SoftmaxCrossEntropyGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops23SoftmaxCrossEntropyGradE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops23SoftmaxCrossEntropyGradE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops23SoftmaxCrossEntropyGradC1EPNS_2OpES2_
.type _ZN3ops23SoftmaxCrossEntropyGradC1EPNS_2OpES2_,@function
.set _ZN3ops23SoftmaxCrossEntropyGradC1EPNS_2OpES2_, _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops23SoftmaxCrossEntropyGradE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops23SoftmaxCrossEntropyGradE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00118212_00000000-6_softmax-cross-entropy-grad.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4620:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4620:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN3ops23SoftmaxCrossEntropyGradD2Ev,"axG",@progbits,_ZN3ops23SoftmaxCrossEntropyGradD5Ev,comdat
.align 2
.weak _ZN3ops23SoftmaxCrossEntropyGradD2Ev
.type _ZN3ops23SoftmaxCrossEntropyGradD2Ev, @function
_ZN3ops23SoftmaxCrossEntropyGradD2Ev:
.LFB5632:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L4
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L4:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L5
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L5:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L6
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L6:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L3
movq 24(%rbx), %rsi
addq $1, %rsi
call _ZdlPvm@PLT
.L3:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5632:
.size _ZN3ops23SoftmaxCrossEntropyGradD2Ev, .-_ZN3ops23SoftmaxCrossEntropyGradD2Ev
.weak _ZN3ops23SoftmaxCrossEntropyGradD1Ev
.set _ZN3ops23SoftmaxCrossEntropyGradD1Ev,_ZN3ops23SoftmaxCrossEntropyGradD2Ev
.section .text._ZN3ops23SoftmaxCrossEntropyGradD0Ev,"axG",@progbits,_ZN3ops23SoftmaxCrossEntropyGradD5Ev,comdat
.align 2
.weak _ZN3ops23SoftmaxCrossEntropyGradD0Ev
.type _ZN3ops23SoftmaxCrossEntropyGradD0Ev, @function
_ZN3ops23SoftmaxCrossEntropyGradD0Ev:
.LFB5634:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVN3ops2OpE(%rip), %rax
movq %rax, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .L10
movq 104(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L10:
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .L11
movq 80(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L11:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L12
movq 56(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L12:
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .L13
movq 24(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L13:
movl $112, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5634:
.size _ZN3ops23SoftmaxCrossEntropyGradD0Ev, .-_ZN3ops23SoftmaxCrossEntropyGradD0Ev
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4643:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4643:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev:
.LFB4947:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4947:
.size _ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev,_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev
.section .text._ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIPN3ops2OpESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.type _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, @function
_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev:
.LFB4982:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L26
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L26:
ret
.cfi_endproc
.LFE4982:
.size _ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev, .-_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.weak _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
.set _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev,_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.type _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_, @function
_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_:
.LFB4615:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4615
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %rbp
movq %rsi, %rbx
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movl $16, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, 16(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 32(%rsp)
movq %rbx, (%rax)
movq %r12, 8(%rax)
movq %rdx, 24(%rsp)
movq %rbx, %rdi
.LEHB1:
call _ZNK3ops2Op9shape_getEv@PLT
movq %rax, %rbx
leaq 80(%rsp), %rdi
leaq 96(%rsp), %rax
movq %rax, 80(%rsp)
movq $26, 8(%rsp)
leaq 8(%rsp), %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE1:
jmp .L47
.L43:
endbr64
movq %rax, %rbx
movq 16(%rsp), %rdi
movq 32(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L33
call _ZdlPvm@PLT
.L33:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L47:
movq %rax, 80(%rsp)
movq 8(%rsp), %rdx
movq %rdx, 96(%rsp)
movabsq $6879355553540632435, %rsi
movabsq $7954869266282410595, %rdi
movq %rsi, (%rax)
movq %rdi, 8(%rax)
movabsq $8247338199294374767, %rsi
movabsq $7233188264842719343, %rdi
movq %rsi, 10(%rax)
movq %rdi, 18(%rax)
movq %rdx, 88(%rsp)
movq 80(%rsp), %rax
movb $0, (%rax,%rdx)
leaq 16(%rsp), %rcx
leaq 80(%rsp), %rsi
leaq 48(%rsp), %r8
movq %rbx, %rdx
movq %rbp, %rdi
.LEHB2:
call _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_@PLT
.LEHE2:
movq 80(%rsp), %rdi
leaq 96(%rsp), %rax
cmpq %rax, %rdi
je .L34
movq 96(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L34:
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .L35
movq 32(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L35:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .L36
movq 64(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L36:
leaq 16+_ZTVN3ops23SoftmaxCrossEntropyGradE(%rip), %rax
movq %rax, 0(%rbp)
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L38:
leaq 16(%rsp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
jmp .L33
.L41:
endbr64
movq %rax, %rbx
jmp .L38
.L39:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4615:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4615:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4615-.LLSDACSB4615
.LLSDACSB4615:
.uleb128 .LEHB0-.LFB4615
.uleb128 .LEHE0-.LEHB0
.uleb128 .L43-.LFB4615
.uleb128 0
.uleb128 .LEHB1-.LFB4615
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB4615
.uleb128 0
.uleb128 .LEHB2-.LFB4615
.uleb128 .LEHE2-.LEHB2
.uleb128 .L42-.LFB4615
.uleb128 0
.uleb128 .LEHB3-.LFB4615
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4615:
.text
.size _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_, .-_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.globl _ZN3ops23SoftmaxCrossEntropyGradC1EPNS_2OpES2_
.set _ZN3ops23SoftmaxCrossEntropyGradC1EPNS_2OpES2_,_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.section .text._ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.type _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, @function
_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev:
.LFB5162:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L52
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L52:
ret
.cfi_endproc
.LFE5162:
.size _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev, .-_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.weak _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev
.set _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED1Ev,_ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.text
.align 2
.globl _ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.type _ZN3ops23SoftmaxCrossEntropyGrad7compileEv, @function
_ZN3ops23SoftmaxCrossEntropyGrad7compileEv:
.LFB4617:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4617
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, %r13
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
.LEHB4:
call _ZN3ops5Graph8instanceEv@PLT
movq %rax, %rbx
movq %rax, -168(%rbp)
leaq -80(%rbp), %rdi
movq %r13, %rsi
call _ZN3ops2Op5predsEv@PLT
.LEHE4:
movq -80(%rbp), %rax
movq (%rax), %rsi
movq %rbx, %rdi
.LEHB5:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE5:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L56
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L56:
leaq -80(%rbp), %rdi
movq %r13, %rsi
.LEHB6:
call _ZN3ops2Op5predsEv@PLT
.LEHE6:
movq -80(%rbp), %rax
movq 8(%rax), %rsi
movq -168(%rbp), %rdi
.LEHB7:
call _ZN3ops5Graph8compiledEPNS_2OpE@PLT
.LEHE7:
movq %rax, -152(%rbp)
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L57
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L57:
leaq 64(%rbx), %r15
movl $0, %esi
movq %r15, %rdi
.LEHB8:
call _ZNK3ops5ShapeixEm@PLT
movslq %eax, %r14
movl $1, %esi
movq %r15, %rdi
call _ZNK3ops5ShapeixEm@PLT
movslq %eax, %r15
movq 72(%rbx), %r12
movq $0, -144(%rbp)
movq $0, -136(%rbp)
movq $0, -128(%rbp)
subq 64(%rbx), %r12
je .L86
movabsq $9223372036854775804, %rax
cmpq %r12, %rax
jb .L99
movq %r12, %rdi
call _Znwm@PLT
.LEHE8:
movq %rax, -160(%rbp)
.L58:
movq -160(%rbp), %rdi
movq %rdi, -144(%rbp)
movq %rdi, -136(%rbp)
addq %rdi, %r12
movq %r12, -128(%rbp)
movq 64(%rbx), %rsi
movq 72(%rbx), %r12
subq %rsi, %r12
cmpq $4, %r12
jle .L61
movq %r12, %rdx
call memmove@PLT
.L62:
movq -160(%rbp), %rax
addq %r12, %rax
movq %rax, -136(%rbp)
movq %r14, %rdi
imulq %r15, %rdi
.LEHB9:
call _Z12tensor_allocm@PLT
.LEHE9:
jmp .L100
.L99:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L101
.LEHB10:
call _ZSt28__throw_bad_array_new_lengthv@PLT
.LEHE10:
.L101:
call __stack_chk_fail@PLT
.L86:
movq $0, -160(%rbp)
jmp .L58
.L61:
jne .L62
movl (%rsi), %eax
movq -160(%rbp), %rcx
movl %eax, (%rcx)
jmp .L62
.L100:
movq %rax, -160(%rbp)
movq 56(%rbx), %r12
movq -152(%rbp), %rcx
movq 56(%rcx), %rsi
movq %rsi, -176(%rbp)
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $16, %edi
.LEHB11:
call _Znwm@PLT
.LEHE11:
movq %rax, -80(%rbp)
leaq 16(%rax), %rdx
movq %rdx, -64(%rbp)
movq %r12, (%rax)
movq -176(%rbp), %rsi
movq %rsi, 8(%rax)
movq %rdx, -72(%rbp)
movq -152(%rbp), %rcx
movq 88(%rcx), %rsi
movq 88(%rbx), %rdi
leaq -80(%rbp), %r9
movq %r15, %r8
movq %r14, %rcx
movq -160(%rbp), %rdx
.LEHB12:
call _ZN2rt4Node29op_softmax_cross_entropy_gradEPKfS2_PfmmRKSt6vectorIPS0_SaIS5_EE@PLT
.LEHE12:
movq %rax, %rbx
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L66
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L66:
movq $0, -80(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $8, %edi
.LEHB13:
call _Znwm@PLT
.LEHE13:
jmp .L102
.L92:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L65:
movq -144(%rbp), %rdi
movq -128(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L83
call _ZdlPvm@PLT
.L83:
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L84
call __stack_chk_fail@PLT
.L102:
movq %rax, -80(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -64(%rbp)
movq -160(%rbp), %r14
movq %r14, (%rax)
movq %rdx, -72(%rbp)
movq $0, -112(%rbp)
movq $0, -104(%rbp)
movq $0, -96(%rbp)
movl $8, %edi
.LEHB14:
call _Znwm@PLT
.LEHE14:
movq %rax, -112(%rbp)
leaq 8(%rax), %rdx
movq %rdx, -96(%rbp)
movq %rbx, (%rax)
movq %rdx, -104(%rbp)
leaq -80(%rbp), %rcx
leaq -112(%rbp), %rdx
subq $8, %rsp
pushq %r14
leaq -144(%rbp), %r9
movq %rbx, %r8
movq %r13, %rsi
movq -168(%rbp), %rdi
.LEHB15:
.cfi_escape 0x2e,0x10
call _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_@PLT
.LEHE15:
jmp .L103
.L93:
endbr64
movq %rax, %rbx
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L65
call _ZdlPvm@PLT
jmp .L65
.L103:
addq $16, %rsp
movq -112(%rbp), %rdi
testq %rdi, %rdi
je .L73
movq -96(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L73:
movq -80(%rbp), %rdi
testq %rdi, %rdi
je .L74
movq -64(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L74:
movq -144(%rbp), %rdi
testq %rdi, %rdi
je .L55
movq -128(%rbp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L55:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L104
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L94:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt12_Vector_baseIPN2rt4NodeESaIS2_EED2Ev
.L72:
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L65
call _ZdlPvm@PLT
jmp .L65
.L87:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L77
call __stack_chk_fail@PLT
.L77:
movq %rbx, %rdi
.LEHB16:
call _Unwind_Resume@PLT
.L88:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN3ops2OpESaIS2_EED1Ev
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L79
call __stack_chk_fail@PLT
.L79:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L90:
endbr64
movq %rax, %rbx
leaq -80(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L65
.L91:
endbr64
movq %rax, %rbx
leaq -112(%rbp), %rdi
call _ZNSt6vectorIPN2rt4NodeESaIS2_EED1Ev
jmp .L72
.L89:
endbr64
movq %rax, %rbx
jmp .L65
.L84:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE16:
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4617:
.section .gcc_except_table
.LLSDA4617:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4617-.LLSDACSB4617
.LLSDACSB4617:
.uleb128 .LEHB4-.LFB4617
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4617
.uleb128 .LEHE5-.LEHB5
.uleb128 .L87-.LFB4617
.uleb128 0
.uleb128 .LEHB6-.LFB4617
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4617
.uleb128 .LEHE7-.LEHB7
.uleb128 .L88-.LFB4617
.uleb128 0
.uleb128 .LEHB8-.LFB4617
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB4617
.uleb128 .LEHE9-.LEHB9
.uleb128 .L89-.LFB4617
.uleb128 0
.uleb128 .LEHB10-.LFB4617
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB4617
.uleb128 .LEHE11-.LEHB11
.uleb128 .L92-.LFB4617
.uleb128 0
.uleb128 .LEHB12-.LFB4617
.uleb128 .LEHE12-.LEHB12
.uleb128 .L90-.LFB4617
.uleb128 0
.uleb128 .LEHB13-.LFB4617
.uleb128 .LEHE13-.LEHB13
.uleb128 .L93-.LFB4617
.uleb128 0
.uleb128 .LEHB14-.LFB4617
.uleb128 .LEHE14-.LEHB14
.uleb128 .L94-.LFB4617
.uleb128 0
.uleb128 .LEHB15-.LFB4617
.uleb128 .LEHE15-.LEHB15
.uleb128 .L91-.LFB4617
.uleb128 0
.uleb128 .LEHB16-.LFB4617
.uleb128 .LEHE16-.LEHB16
.uleb128 0
.uleb128 0
.LLSDACSE4617:
.text
.size _ZN3ops23SoftmaxCrossEntropyGrad7compileEv, .-_ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.weak _ZTSN3ops23SoftmaxCrossEntropyGradE
.section .rodata._ZTSN3ops23SoftmaxCrossEntropyGradE,"aG",@progbits,_ZTSN3ops23SoftmaxCrossEntropyGradE,comdat
.align 32
.type _ZTSN3ops23SoftmaxCrossEntropyGradE, @object
.size _ZTSN3ops23SoftmaxCrossEntropyGradE, 32
_ZTSN3ops23SoftmaxCrossEntropyGradE:
.string "N3ops23SoftmaxCrossEntropyGradE"
.weak _ZTIN3ops23SoftmaxCrossEntropyGradE
.section .data.rel.ro._ZTIN3ops23SoftmaxCrossEntropyGradE,"awG",@progbits,_ZTIN3ops23SoftmaxCrossEntropyGradE,comdat
.align 8
.type _ZTIN3ops23SoftmaxCrossEntropyGradE, @object
.size _ZTIN3ops23SoftmaxCrossEntropyGradE, 24
_ZTIN3ops23SoftmaxCrossEntropyGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops23SoftmaxCrossEntropyGradE
.quad _ZTIN3ops2OpE
.weak _ZTVN3ops23SoftmaxCrossEntropyGradE
.section .data.rel.ro._ZTVN3ops23SoftmaxCrossEntropyGradE,"awG",@progbits,_ZTVN3ops23SoftmaxCrossEntropyGradE,comdat
.align 8
.type _ZTVN3ops23SoftmaxCrossEntropyGradE, @object
.size _ZTVN3ops23SoftmaxCrossEntropyGradE, 48
_ZTVN3ops23SoftmaxCrossEntropyGradE:
.quad 0
.quad _ZTIN3ops23SoftmaxCrossEntropyGradE
.quad _ZN3ops23SoftmaxCrossEntropyGradD1Ev
.quad _ZN3ops23SoftmaxCrossEntropyGradD0Ev
.quad _ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "softmax-cross-entropy-grad.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.LCPI0_0:
.zero 16
.text
.globl _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.p2align 4, 0x90
.type _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_,@function
_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_: # @_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
leaq 48(%rsp), %r13
movq %r13, 32(%rsp)
movl $27, %edi
callq _Znwm
movq %rax, 32(%rsp)
movq $26, 48(%rsp)
movups .L.str(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str+10(%rip), %xmm0
movups %xmm0, 10(%rax)
movq $26, 40(%rsp)
movb $0, 26(%rax)
.Ltmp0:
movq %r15, %rdi
callq _ZNK3ops2Op9shape_getEv
.Ltmp1:
# %bb.1:
movq %rax, %r12
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp3:
movl $16, %edi
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, (%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 16(%rsp)
movq %r15, (%rax)
movq %r14, 8(%rax)
movq %rcx, 8(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp6:
leaq 32(%rsp), %rsi
movq %rsp, %rcx
leaq 64(%rsp), %r8
movq %rbx, %rdi
movq %r12, %rdx
callq _ZN3ops2OpC2ERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEERKNS_5ShapeESt6vectorIPS0_SaISD_EESF_
.Ltmp7:
# %bb.3:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_5
# %bb.4:
callq _ZdlPv
.LBB0_5: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_7
# %bb.6:
callq _ZdlPv
.LBB0_7: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit16
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_9
# %bb.8: # %.critedge.i.i
callq _ZdlPv
.LBB0_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $_ZTVN3ops23SoftmaxCrossEntropyGradE+16, (%rbx)
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 144
.Ltmp8:
movq %rax, %rbx
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_14
# %bb.13:
callq _ZdlPv
jmp .LBB0_14
.LBB0_10:
.Ltmp5:
movq %rax, %rbx
.LBB0_14: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit19
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_16
# %bb.15:
callq _ZdlPv
jmp .LBB0_16
.LBB0_11:
.Ltmp2:
movq %rax, %rbx
.LBB0_16: # %.body
movq 32(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_18
# %bb.17: # %.critedge.i.i23
callq _ZdlPv
.LBB0_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit25
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_, .Lfunc_end0-_ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.LCPI1_0:
.zero 16
.text
.globl _ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.p2align 4, 0x90
.type _ZN3ops23SoftmaxCrossEntropyGrad7compileEv,@function
_ZN3ops23SoftmaxCrossEntropyGrad7compileEv: # @_ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbp
callq _ZN3ops5Graph8instanceEv
movq %rax, %rbx
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq _ZN3ops2Op5predsEv
movq 16(%rsp), %rax
movq (%rax), %rsi
.Ltmp9:
movq %rbx, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp10:
# %bb.1:
movq %rax, %r15
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_3
# %bb.2:
callq _ZdlPv
.LBB1_3: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq _ZN3ops2Op5predsEv
movq 16(%rsp), %rax
movq 8(%rax), %rsi
.Ltmp12:
movq %rbx, %rdi
callq _ZN3ops5Graph8compiledEPNS_2OpE
.Ltmp13:
# %bb.4:
movq %rax, 160(%rsp) # 8-byte Spill
movq %rbx, 152(%rsp) # 8-byte Spill
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_6
# %bb.5:
callq _ZdlPv
.LBB1_6: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit41
movq %r15, %r14
addq $64, %r14
xorl %r13d, %r13d
movq %r14, %rdi
xorl %esi, %esi
callq _ZNK3ops5ShapeixEm
movl %eax, %ebx
movl $1, %esi
movq %r14, %rdi
callq _ZNK3ops5ShapeixEm
movl %eax, %r14d
movq 72(%r15), %rdi
movq 64(%r15), %rax
movq %rdi, %r12
subq %rax, %r12
sarq $2, %r12
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movq $0, 32(%rsp)
subq %rax, %rdi
je .LBB1_9
# %bb.7:
movq %r12, %rax
shrq $61, %rax
jne .LBB1_28
# %bb.8: # %_ZNSt16allocator_traitsISaIiEE8allocateERS0_m.exit.i.i.i.i.i
callq _Znwm
movq %rax, %r13
.LBB1_9: # %_ZNSt12_Vector_baseIiSaIiEEC2EmRKS0_.exit.i.i
movq %rbp, 136(%rsp) # 8-byte Spill
movslq %ebx, %rbp
movslq %r14d, %rbx
movq %r13, 16(%rsp)
movq %r13, 24(%rsp)
leaq (%r13,%r12,4), %rax
movq %rax, 32(%rsp)
movq 64(%r15), %rsi
movq 72(%r15), %r14
subq %rsi, %r14
cmpq $5, %r14
jl .LBB1_26
# %bb.10:
movq %r13, %rdi
movq %r14, %rdx
callq memmove@PLT
.LBB1_11: # %_ZN3ops5ShapeC2ERKS0_.exit
addq %r14, %r13
movq %r13, 24(%rsp)
movq %rbx, 144(%rsp) # 8-byte Spill
movq %rbx, %rdi
imulq %rbp, %rdi
.Ltmp15:
callq _Z12tensor_allocm
.Ltmp16:
# %bb.12:
movq %rax, %r13
movq 88(%r15), %r14
movq 160(%rsp), %rax # 8-byte Reload
movq 88(%rax), %r12
movq 56(%r15), %r15
movq 56(%rax), %rbx
xorps %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movq $0, 128(%rsp)
.Ltmp18:
movl $16, %edi
callq _Znwm
.Ltmp19:
# %bb.13: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit
movq %rax, 112(%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 128(%rsp)
movq %r15, (%rax)
movq %rbx, 8(%rax)
movq %rcx, 120(%rsp)
.Ltmp21:
leaq 112(%rsp), %r9
movq %r14, %rdi
movq %r12, %rsi
movq %r13, %rdx
movq %rbp, %rcx
movq 144(%rsp), %r8 # 8-byte Reload
callq _ZN2rt4Node29op_softmax_cross_entropy_gradEPKfS2_PfmmRKSt6vectorIPS0_SaIS5_EE
.Ltmp22:
# %bb.14:
movq %rax, %rbx
movq 112(%rsp), %rdi
testq %rdi, %rdi
movq 136(%rsp), %r14 # 8-byte Reload
je .LBB1_16
# %bb.15:
callq _ZdlPv
.LBB1_16: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movq $0, 96(%rsp)
.Ltmp24:
movl $8, %edi
callq _Znwm
.Ltmp25:
# %bb.17: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EEC2ESt16initializer_listIS2_ERKS3_.exit48
movq %rax, 80(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 96(%rsp)
movq %rbx, (%rax)
movq %rcx, 88(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movq $0, 64(%rsp)
.Ltmp27:
movl $8, %edi
callq _Znwm
.Ltmp28:
# %bb.18: # %_ZNSt6vectorIPfSaIS0_EEC2ESt16initializer_listIS0_ERKS1_.exit
movq %rax, 48(%rsp)
movq %rax, %rcx
addq $8, %rcx
movq %rcx, 64(%rsp)
movq %r13, (%rax)
movq %rcx, 56(%rsp)
.Ltmp30:
movq %r13, (%rsp)
leaq 80(%rsp), %rdx
leaq 48(%rsp), %rcx
leaq 16(%rsp), %r9
movq 152(%rsp), %rdi # 8-byte Reload
movq %r14, %rsi
movq %rbx, %r8
callq _ZN3ops5Graph12add_compiledEPNS_2OpESt6vectorIPN2rt4NodeESaIS6_EES3_IPfSaIS9_EES6_RKNS_5ShapeES9_
.Ltmp31:
# %bb.19:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_21
# %bb.20:
callq _ZdlPv
.LBB1_21: # %_ZNSt6vectorIPfSaIS0_EED2Ev.exit
movq 80(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_23
# %bb.22:
callq _ZdlPv
.LBB1_23: # %_ZNSt6vectorIPN2rt4NodeESaIS2_EED2Ev.exit56
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_25
# %bb.24:
callq _ZdlPv
.LBB1_25: # %_ZN3ops5ShapeD2Ev.exit
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_26:
.cfi_def_cfa_offset 224
cmpq $4, %r14
jne .LBB1_11
# %bb.27:
movl (%rsi), %eax
movl %eax, (%r13)
jmp .LBB1_11
.LBB1_28:
shrq $62, %r12
je .LBB1_30
# %bb.29: # %.noexc.i.i.i
callq _ZSt28__throw_bad_array_new_lengthv
.LBB1_30: # %.noexc4.i.i.i
callq _ZSt17__throw_bad_allocv
.LBB1_31:
.Ltmp32:
jmp .LBB1_33
.LBB1_32:
.Ltmp29:
.LBB1_33:
movq %rax, %rbx
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_36
# %bb.34: # %.body50.sink.split
callq _ZdlPv
jmp .LBB1_36
.LBB1_35:
.Ltmp26:
movq %rax, %rbx
.LBB1_36: # %.body50
movq 80(%rsp), %rdi
jmp .LBB1_40
.LBB1_37:
.Ltmp23:
jmp .LBB1_39
.LBB1_38:
.Ltmp20:
.LBB1_39:
movq %rax, %rbx
movq 112(%rsp), %rdi
.LBB1_40: # %.body50
testq %rdi, %rdi
je .LBB1_46
# %bb.41:
callq _ZdlPv
jmp .LBB1_46
.LBB1_42:
.Ltmp17:
jmp .LBB1_45
.LBB1_43:
.Ltmp14:
jmp .LBB1_45
.LBB1_44:
.Ltmp11:
.LBB1_45: # %.body46
movq %rax, %rbx
.LBB1_46: # %.body46
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_48
# %bb.47:
callq _ZdlPv
.LBB1_48:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _ZN3ops23SoftmaxCrossEntropyGrad7compileEv, .Lfunc_end1-_ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin1 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp10 # Call between .Ltmp10 and .Ltmp12
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin1 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp13 # Call between .Ltmp13 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin1 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin1 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin1 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin1 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin1 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp32-.Lfunc_begin1 # jumps to .Ltmp32
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin1 # >> Call Site 12 <<
.uleb128 .Lfunc_end1-.Ltmp31 # Call between .Ltmp31 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN3ops2OpD2Ev,"axG",@progbits,_ZN3ops2OpD2Ev,comdat
.weak _ZN3ops2OpD2Ev # -- Begin function _ZN3ops2OpD2Ev
.p2align 4, 0x90
.type _ZN3ops2OpD2Ev,@function
_ZN3ops2OpD2Ev: # @_ZN3ops2OpD2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq _ZdlPv
.LBB2_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq _ZdlPv
.LBB2_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq _ZdlPv
.LBB2_6: # %_ZN3ops5ShapeD2Ev.exit
movq 8(%rbx), %rdi
addq $24, %rbx
cmpq %rbx, %rdi
je .LBB2_7
# %bb.8: # %.critedge.i.i
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3ops2OpD2Ev, .Lfunc_end2-_ZN3ops2OpD2Ev
.cfi_endproc
# -- End function
.section .text._ZN3ops23SoftmaxCrossEntropyGradD0Ev,"axG",@progbits,_ZN3ops23SoftmaxCrossEntropyGradD0Ev,comdat
.weak _ZN3ops23SoftmaxCrossEntropyGradD0Ev # -- Begin function _ZN3ops23SoftmaxCrossEntropyGradD0Ev
.p2align 4, 0x90
.type _ZN3ops23SoftmaxCrossEntropyGradD0Ev,@function
_ZN3ops23SoftmaxCrossEntropyGradD0Ev: # @_ZN3ops23SoftmaxCrossEntropyGradD0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq $_ZTVN3ops2OpE+16, (%rdi)
movq 88(%rdi), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
callq _ZdlPv
.LBB3_2: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit.i
movq 64(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_4
# %bb.3:
callq _ZdlPv
.LBB3_4: # %_ZNSt6vectorIPN3ops2OpESaIS2_EED2Ev.exit2.i
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB3_6
# %bb.5:
callq _ZdlPv
.LBB3_6: # %_ZN3ops5ShapeD2Ev.exit.i
movq 8(%rbx), %rdi
leaq 24(%rbx), %rax
cmpq %rax, %rdi
je .LBB3_8
# %bb.7: # %.critedge.i.i.i
callq _ZdlPv
.LBB3_8: # %_ZN3ops2OpD2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end3:
.size _ZN3ops23SoftmaxCrossEntropyGradD0Ev, .Lfunc_end3-_ZN3ops23SoftmaxCrossEntropyGradD0Ev
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "softmax_cross_entropy_grad"
.size .L.str, 27
.type _ZTVN3ops23SoftmaxCrossEntropyGradE,@object # @_ZTVN3ops23SoftmaxCrossEntropyGradE
.section .rodata,"a",@progbits
.globl _ZTVN3ops23SoftmaxCrossEntropyGradE
.p2align 3, 0x0
_ZTVN3ops23SoftmaxCrossEntropyGradE:
.quad 0
.quad _ZTIN3ops23SoftmaxCrossEntropyGradE
.quad _ZN3ops2OpD2Ev
.quad _ZN3ops23SoftmaxCrossEntropyGradD0Ev
.quad _ZN3ops23SoftmaxCrossEntropyGrad7compileEv
.quad _ZN3ops2Op10child_gradEmPS0_
.size _ZTVN3ops23SoftmaxCrossEntropyGradE, 48
.type _ZTSN3ops23SoftmaxCrossEntropyGradE,@object # @_ZTSN3ops23SoftmaxCrossEntropyGradE
.globl _ZTSN3ops23SoftmaxCrossEntropyGradE
_ZTSN3ops23SoftmaxCrossEntropyGradE:
.asciz "N3ops23SoftmaxCrossEntropyGradE"
.size _ZTSN3ops23SoftmaxCrossEntropyGradE, 32
.type _ZTIN3ops23SoftmaxCrossEntropyGradE,@object # @_ZTIN3ops23SoftmaxCrossEntropyGradE
.globl _ZTIN3ops23SoftmaxCrossEntropyGradE
.p2align 3, 0x0
_ZTIN3ops23SoftmaxCrossEntropyGradE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSN3ops23SoftmaxCrossEntropyGradE
.quad _ZTIN3ops2OpE
.size _ZTIN3ops23SoftmaxCrossEntropyGradE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN3ops23SoftmaxCrossEntropyGradC1EPNS_2OpES2_
.type _ZN3ops23SoftmaxCrossEntropyGradC1EPNS_2OpES2_,@function
.set _ZN3ops23SoftmaxCrossEntropyGradC1EPNS_2OpES2_, _ZN3ops23SoftmaxCrossEntropyGradC2EPNS_2OpES2_
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSN3ops23SoftmaxCrossEntropyGradE
.addrsig_sym _ZTIN3ops2OpE
.addrsig_sym _ZTIN3ops23SoftmaxCrossEntropyGradE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
void Algorithm1(int m, int n, int l);
#define BLOCK_SIZE 256
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,
double* device_matrix_C,
const int m,
const int n,
const int l
)
{
int threadid = threadIdx.x + blockDim.x*blockIdx.x;
int column = threadid%l;
int row = threadid/l;
if (row >= m || column >= l)
{
return;
}
int idx = column*m + row;
double sum = 0.0;
for (int k = 0; k < n; k++){
int idxA = k*m + row;
int idxB = column*n + k;
sum += device_matrix_A[idxA]*device_matrix_B[idxB];
}
device_matrix_C[idx] = sum;
}
int main()
{
Algorithm1(32, 32, 32);
Algorithm1(64, 64, 64);
Algorithm1(128,128, 128);
Algorithm1(256, 256, 256);
Algorithm1(512, 512, 512);
Algorithm1(1024, 1024, 1024);
Algorithm1(2048, 2048, 2048);
Algorithm1(4096, 4096, 4096);
}
void Algorithm1(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
cudaMalloc(&device_matrix_A, m*n*sizeof(double));
cudaMalloc(&device_matrix_B, n*l*sizeof(double));
cudaMalloc(&device_matrix_C, m*l*sizeof(double));
//initializing the matrixrix// Omit D and C
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
cudaMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), cudaMemcpyHostToDevice);
int num_blocks = (m*l + BLOCK_SIZE - 1)/BLOCK_SIZE;
cudaEventRecord(start);
device_Matrix_multi <<<num_blocks, BLOCK_SIZE>>> (
device_matrix_A,
device_matrix_B,
device_matrix_C,
m,
n,
l
);
cudaMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
//print to check whether the matrixrixs give correct output or not
}
}
cudaEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n",milliseconds);
cudaFree(device_matrix_A);
cudaFree(device_matrix_B);
cudaFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
} | code for sm_80
Function : _Z19device_Matrix_multiPKdS0_Pdiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R7, c[0x0][0x180] ; /* 0x0000600000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00a0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00b0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fe200078e02ff */
/*00c0*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc80000000000 */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a00 */
/*0100*/ IMAD R2, R7, R3, R6 ; /* 0x0000000307027224 */
/* 0x000fca00078e0206 */
/*0110*/ ISETP.GT.U32.AND P2, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f44070 */
/*0120*/ @!P2 IADD3 R2, R2, -R7.reuse, RZ ; /* 0x800000070202a210 */
/* 0x080fe40007ffe0ff */
/*0130*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*0150*/ LOP3.LUT R2, R4, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600004027a12 */
/* 0x000fe400078e3cff */
/*0160*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f45270 */
/*0170*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*0180*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fcc0007ffe0ff */
/*0190*/ @!P1 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff009224 */
/* 0x000fe200078e0a00 */
/*01a0*/ @!P2 LOP3.LUT R0, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff00aa12 */
/* 0x000fc800078e33ff */
/*01b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06270 */
/*01c0*/ ISETP.GT.OR P0, PT, RZ, c[0x0][0x180], P0 ; /* 0x00006000ff007a0c */
/* 0x000fda0000704670 */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01e0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a00 */
/*0200*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0210*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0220*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0230*/ IMAD R3, R3, c[0x0][0x180], R4 ; /* 0x0000600003037a24 */
/* 0x000fd800078e0204 */
/*0240*/ @!P0 BRA 0xd70 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0260*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0270*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*0280*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0290*/ MOV R26, RZ ; /* 0x000000ff001a7202 */
/* 0x000fd60000000f00 */
/*02a0*/ @!P0 BRA 0xc30 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IADD3 R4, -R2, c[0x0][0x17c], RZ ; /* 0x00005f0002047a10 */
/* 0x000fe20007ffe1ff */
/*02c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*02d0*/ HFMA2.MMA R26, -RZ, RZ, 0, 0 ; /* 0x00000000ff1a7435 */
/* 0x000fe200000001ff */
/*02e0*/ IMAD R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a24 */
/* 0x000fe200078e02ff */
/*02f0*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*0300*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0310*/ IMAD.WIDE R28, R0, R5, c[0x0][0x160] ; /* 0x00005800001c7625 */
/* 0x000fc800078e0205 */
/*0320*/ IMAD.WIDE R6, R6, R5, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fce00078e0205 */
/*0330*/ @!P0 BRA 0xab0 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0360*/ @!P1 BRA 0x800 ; /* 0x0000049000009947 */
/* 0x000fea0003800000 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0380*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1b00 */
/*0390*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0010a2000c1e1b00 */
/*03a0*/ IMAD.WIDE R24, R5, c[0x0][0x178], R28 ; /* 0x00005e0005187a25 */
/* 0x000fc600078e021c */
/*03b0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*03c0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*03d0*/ IMAD.WIDE R22, R5, c[0x0][0x178], R24 ; /* 0x00005e0005167a25 */
/* 0x000fc600078e0218 */
/*03e0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f28000c1e1b00 */
/*03f0*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x002322000c1e1b00 */
/*0400*/ IMAD.WIDE R28, R5, c[0x0][0x178], R22 ; /* 0x00005e00051c7a25 */
/* 0x001fca00078e0216 */
/*0410*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002162000c1e1b00 */
/*0420*/ DFMA R18, R20, R10, R18 ; /* 0x0000000a1412722b */
/* 0x0042c60000000012 */
/*0430*/ LDG.E.64 R10, [R6.64+0x18] ; /* 0x00001804060a7981 */
/* 0x002f62000c1e1b00 */
/*0440*/ IMAD.WIDE R28, R5.reuse, c[0x0][0x178], R28 ; /* 0x00005e00051c7a25 */
/* 0x041fe400078e021c */
/*0450*/ DFMA R18, R16, R8, R18 ; /* 0x000000081012722b */
/* 0x0081240000000012 */
/*0460*/ LDG.E.64 R8, [R6.64+0x20] ; /* 0x0000200406087981 */
/* 0x001ea8000c1e1b00 */
/*0470*/ LDG.E.64 R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x000ea2000c1e1b00 */
/*0480*/ IMAD.WIDE R24, R5, c[0x0][0x178], R28 ; /* 0x00005e0005187a25 */
/* 0x000fe200078e021c */
/*0490*/ DFMA R18, R14, R12, R18 ; /* 0x0000000c0e12722b */
/* 0x0101440000000012 */
/*04a0*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001ee8000c1e1b00 */
/*04b0*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000ee2000c1e1b00 */
/*04c0*/ IMAD.WIDE R20, R5, c[0x0][0x178], R24 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0218 */
/*04d0*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x0200a40000000012 */
/*04e0*/ LDG.E.64 R10, [R6.64+0x30] ; /* 0x00003004060a7981 */
/* 0x001f28000c1e1b00 */
/*04f0*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x000122000c1e1b00 */
/*0500*/ DFMA R16, R8, R16, R22 ; /* 0x000000100810722b */
/* 0x0042c60000000016 */
/*0510*/ LDG.E.64 R8, [R6.64+0x38] ; /* 0x0000380406087981 */
/* 0x002ea2000c1e1b00 */
/*0520*/ IMAD.WIDE R20, R5, c[0x0][0x178], R20 ; /* 0x00005e0005147a25 */
/* 0x001fca00078e0214 */
/*0530*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ea2000c1e1b00 */
/*0540*/ IMAD.WIDE R28, R5.reuse, c[0x0][0x178], R20 ; /* 0x00005e00051c7a25 */
/* 0x040fe200078e0214 */
/*0550*/ DFMA R12, R14, R12, R16 ; /* 0x0000000c0e0c722b */
/* 0x0081240000000010 */
/*0560*/ LDG.E.64 R16, [R6.64+0x40] ; /* 0x0000400406107981 */
/* 0x001ee8000c1e1b00 */
/*0570*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ee2000c1e1b00 */
/*0580*/ IMAD.WIDE R24, R5, c[0x0][0x178], R28 ; /* 0x00005e0005187a25 */
/* 0x000fe200078e021c */
/*0590*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x010084000000000c */
/*05a0*/ LDG.E.64 R12, [R6.64+0x48] ; /* 0x00004804060c7981 */
/* 0x001f28000c1e1b00 */
/*05b0*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000124000c1e1b00 */
/*05c0*/ IMAD.WIDE R24, R5.reuse, c[0x0][0x178], R24 ; /* 0x00005e0005187a25 */
/* 0x041fe200078e0218 */
/*05d0*/ DFMA R22, R8, R22, R18 ; /* 0x000000160816722b */
/* 0x0040e40000000012 */
/*05e0*/ LDG.E.64 R8, [R6.64+0x50] ; /* 0x0000500406087981 */
/* 0x001ea8000c1e1b00 */
/*05f0*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ea2000c1e1b00 */
/*0600*/ IMAD.WIDE R20, R5, c[0x0][0x178], R24 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0218 */
/*0610*/ DFMA R14, R16, R14, R22 ; /* 0x0000000e100e722b */
/* 0x0081040000000016 */
/*0620*/ LDG.E.64 R16, [R6.64+0x58] ; /* 0x0000580406107981 */
/* 0x001ee8000c1e1b00 */
/*0630*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ee2000c1e1b00 */
/*0640*/ IMAD.WIDE R28, R5.reuse, c[0x0][0x178], R20 ; /* 0x00005e00051c7a25 */
/* 0x040fe200078e0214 */
/*0650*/ DFMA R10, R12, R10, R14 ; /* 0x0000000a0c0a722b */
/* 0x0100a4000000000e */
/*0660*/ LDG.E.64 R14, [R6.64+0x60] ; /* 0x00006004060e7981 */
/* 0x001f28000c1e1b00 */
/*0670*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x000124000c1e1b00 */
/*0680*/ IMAD.WIDE R28, R5, c[0x0][0x178], R28 ; /* 0x00005e00051c7a25 */
/* 0x001fe200078e021c */
/*0690*/ DFMA R18, R8, R18, R10 ; /* 0x000000120812722b */
/* 0x0040c4000000000a */
/*06a0*/ LDG.E.64 R8, [R6.64+0x68] ; /* 0x0000680406087981 */
/* 0x001ea6000c1e1b00 */
/*06b0*/ IMAD.WIDE R24, R5, c[0x0][0x178], R28 ; /* 0x00005e0005187a25 */
/* 0x000fe200078e021c */
/*06c0*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ea2000c1e1b00 */
/*06d0*/ DFMA R22, R16, R22, R18 ; /* 0x000000161016722b */
/* 0x0081060000000012 */
/*06e0*/ LDG.E.64 R16, [R6.64+0x70] ; /* 0x0000700406107981 */
/* 0x001ee2000c1e1b00 */
/*06f0*/ IMAD.WIDE R20, R5, c[0x0][0x178], R24 ; /* 0x00005e0005147a25 */
/* 0x000fc600078e0218 */
/*0700*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ee2000c1e1b00 */
/*0710*/ DFMA R22, R14, R12, R22 ; /* 0x0000000c0e16722b */
/* 0x0100860000000016 */
/*0720*/ LDG.E.64 R12, [R6.64+0x78] ; /* 0x00007804060c7981 */
/* 0x001128000c1e1b00 */
/*0730*/ LDG.E.64 R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000f22000c1e1b00 */
/*0740*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc80007ffe0ff */
/*0750*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*0760*/ DFMA R8, R8, R10, R22 ; /* 0x0000000a0808722b */
/* 0x004ecc0000000016 */
/*0770*/ DFMA R18, R16, R18, R8 ; /* 0x000000121012722b */
/* 0x0083240000000008 */
/*0780*/ IADD3 R8, P2, R6, 0x80, RZ ; /* 0x0000008006087810 */
/* 0x002fe20007f5e0ff */
/*0790*/ IMAD.WIDE R28, R5, c[0x0][0x178], R20 ; /* 0x00005e00051c7a25 */
/* 0x000fc800078e0214 */
/*07a0*/ IMAD.X R9, RZ, RZ, R7, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0607 */
/*07b0*/ IADD3 R26, R26, 0x10, RZ ; /* 0x000000101a1a7810 */
/* 0x000fe40007ffe0ff */
/*07c0*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x001fe20000000f00 */
/*07d0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*07e0*/ DFMA R18, R12, R14, R18 ; /* 0x0000000e0c12722b */
/* 0x0100620000000012 */
/*07f0*/ @P1 BRA 0x380 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*0800*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0810*/ @!P1 BRA 0xa90 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0820*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1b00 */
/*0830*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x0010a2000c1e1b00 */
/*0840*/ IMAD.WIDE R22, R5, c[0x0][0x178], R28 ; /* 0x00005e0005167a25 */
/* 0x000fc600078e021c */
/*0850*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*0860*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x0008e8000c1e1b00 */
/*0870*/ LDG.E.64 R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x000f62000c1e1b00 */
/*0880*/ IMAD.WIDE R22, R5, c[0x0][0x178], R22 ; /* 0x00005e0005167a25 */
/* 0x010fca00078e0216 */
/*0890*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x000f62000c1e1b00 */
/*08a0*/ IMAD.WIDE R24, R5, c[0x0][0x178], R22 ; /* 0x00005e0005187a25 */
/* 0x000fcc00078e0216 */
/*08b0*/ IMAD.WIDE R28, R5, c[0x0][0x178], R24 ; /* 0x00005e00051c7a25 */
/* 0x001fe200078e0218 */
/*08c0*/ DFMA R18, R20, R12, R18 ; /* 0x0000000c1412722b */
/* 0x0060e40000000012 */
/*08d0*/ LDG.E.64 R12, [R6.64+0x18] ; /* 0x00001804060c7981 */
/* 0x001ea8000c1e1b00 */
/*08e0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x0000a2000c1e1b00 */
/*08f0*/ DFMA R10, R16, R10, R18 ; /* 0x0000000a100a722b */
/* 0x0083460000000012 */
/*0900*/ LDG.E.64 R16, [R6.64+0x20] ; /* 0x0000200406107981 */
/* 0x002ee8000c1e1b00 */
/*0910*/ LDG.E.64 R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x0002e2000c1e1b00 */
/*0920*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x0208a2000000000a */
/*0930*/ IMAD.WIDE R28, R5.reuse, c[0x0][0x178], R28 ; /* 0x00005e00051c7a25 */
/* 0x042fe400078e021c */
/*0940*/ LDG.E.64 R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x010f28000c1e1b00 */
/*0950*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000f22000c1e1b00 */
/*0960*/ IMAD.WIDE R22, R5, c[0x0][0x178], R28 ; /* 0x00005e0005167a25 */
/* 0x000fcc00078e021c */
/*0970*/ IMAD.WIDE R24, R5, c[0x0][0x178], R22 ; /* 0x00005e0005187a25 */
/* 0x001fe200078e0216 */
/*0980*/ DFMA R20, R12, R20, R14 ; /* 0x000000140c14722b */
/* 0x0040e4000000000e */
/*0990*/ LDG.E.64 R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x0010a8000c1e1b00 */
/*09a0*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x000ea2000c1e1b00 */
/*09b0*/ DFMA R20, R16, R18, R20 ; /* 0x000000121014722b */
/* 0x0083060000000014 */
/*09c0*/ LDG.E.64 R18, [R6.64+0x38] ; /* 0x0000380406127981 */
/* 0x0020e8000c1e1b00 */
/*09d0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000ee2000c1e1b00 */
/*09e0*/ DFMA R8, R8, R10, R20 ; /* 0x0000000a0808722b */
/* 0x0102a40000000014 */
/*09f0*/ IADD3 R10, P1, R6, 0x40, RZ ; /* 0x00000040060a7810 */
/* 0x002fc80007f3e0ff */
/*0a00*/ IADD3.X R11, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0b7210 */
/* 0x000fe20000ffe4ff */
/*0a10*/ IMAD.WIDE R28, R5, c[0x0][0x178], R24 ; /* 0x00005e00051c7a25 */
/* 0x000fe200078e0218 */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a30*/ IADD3 R26, R26, 0x8, RZ ; /* 0x000000081a1a7810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x001fe200078e000a */
/*0a50*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe40007ffe0ff */
/*0a60*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fe20000000f00 */
/*0a70*/ DFMA R8, R12, R14, R8 ; /* 0x0000000e0c08722b */
/* 0x004ecc0000000008 */
/*0a80*/ DFMA R18, R18, R16, R8 ; /* 0x000000101212722b */
/* 0x0080480000000008 */
/*0a90*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0aa0*/ @!P0 BRA 0xc30 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ LDG.E.64 R22, [R6.64] ; /* 0x0000000406167981 */
/* 0x000ea8000c1e1b00 */
/*0ac0*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x001ea2000c1e1b00 */
/*0ad0*/ IMAD.WIDE R24, R5, c[0x0][0x178], R28 ; /* 0x00005e0005187a25 */
/* 0x000fc600078e021c */
/*0ae0*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ee8000c1e1b00 */
/*0af0*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x0000e8000c1e1b00 */
/*0b00*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f22000c1e1b00 */
/*0b10*/ IMAD.WIDE R24, R5, c[0x0][0x178], R24 ; /* 0x00005e0005187a25 */
/* 0x001fca00078e0218 */
/*0b20*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000f22000c1e1b00 */
/*0b30*/ IMAD.WIDE R20, R5, c[0x0][0x178], R24 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0218 */
/*0b40*/ DFMA R22, R22, R8, R18 ; /* 0x000000081616722b */
/* 0x0060e40000000012 */
/*0b50*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x0010a8000c1e1b00 */
/*0b60*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ea2000c1e1b00 */
/*0b70*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0b80*/ DFMA R10, R10, R12, R22 ; /* 0x0000000c0a0a722b */
/* 0x0083060000000016 */
/*0b90*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0ba0*/ IADD3 R12, P1, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x002fc80007f3e0ff */
/*0bb0*/ IADD3.X R13, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fe20000ffe4ff */
/*0bc0*/ DFMA R10, R14, R16, R10 ; /* 0x000000100e0a722b */
/* 0x010ea2000000000a */
/*0bd0*/ IADD3 R26, R26, 0x4, RZ ; /* 0x000000041a1a7810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ IMAD.WIDE R28, R5, c[0x0][0x178], R20 ; /* 0x00005e00051c7a25 */
/* 0x000fe200078e0214 */
/*0bf0*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x001fc60000000f00 */
/*0c00*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*0c10*/ DFMA R18, R18, R8, R10 ; /* 0x000000081212722b */
/* 0x004064000000000a */
/*0c20*/ @P0 BRA 0xab0 ; /* 0xfffffe8000000947 */
/* 0x003fea000383ffff */
/*0c30*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0c40*/ @!P0 BRA 0xd70 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0c50*/ MOV R13, 0x8 ; /* 0x00000008000d7802 */
/* 0x001fe20000000f00 */
/*0c60*/ IMAD R4, R3, c[0x0][0x17c], R26 ; /* 0x00005f0003047a24 */
/* 0x000fe400078e021a */
/*0c70*/ IMAD R6, R26, c[0x0][0x178], R0 ; /* 0x00005e001a067a24 */
/* 0x000fe400078e0200 */
/*0c80*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020d */
/*0c90*/ IMAD.WIDE R6, R6, R13, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e020d */
/*0ca0*/ MOV R11, R5 ; /* 0x00000005000b7202 */
/* 0x000fc60000000f00 */
/*0cb0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0004 */
/*0cc0*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x001fe20000000f00 */
/*0cd0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0ce0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0000aa000c1e1b00 */
/*0cf0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0d00*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0d10*/ IADD3 R10, P1, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fc40007f3e0ff */
/*0d20*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0d30*/ IMAD.WIDE R6, R13, c[0x0][0x178], R6 ; /* 0x00005e000d067a25 */
/* 0x001fe200078e0206 */
/*0d40*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0d50*/ DFMA R18, R4, R8, R18 ; /* 0x000000080412722b */
/* 0x0060540000000012 */
/*0d60*/ @P0 BRA 0xcc0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0d70*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*0d80*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fc800078e0200 */
/*0d90*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0da0*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x002fe2000c101b04 */
/*0db0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dc0*/ BRA 0xdc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
void Algorithm1(int m, int n, int l);
#define BLOCK_SIZE 256
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,
double* device_matrix_C,
const int m,
const int n,
const int l
)
{
int threadid = threadIdx.x + blockDim.x*blockIdx.x;
int column = threadid%l;
int row = threadid/l;
if (row >= m || column >= l)
{
return;
}
int idx = column*m + row;
double sum = 0.0;
for (int k = 0; k < n; k++){
int idxA = k*m + row;
int idxB = column*n + k;
sum += device_matrix_A[idxA]*device_matrix_B[idxB];
}
device_matrix_C[idx] = sum;
}
int main()
{
Algorithm1(32, 32, 32);
Algorithm1(64, 64, 64);
Algorithm1(128,128, 128);
Algorithm1(256, 256, 256);
Algorithm1(512, 512, 512);
Algorithm1(1024, 1024, 1024);
Algorithm1(2048, 2048, 2048);
Algorithm1(4096, 4096, 4096);
}
void Algorithm1(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
cudaMalloc(&device_matrix_A, m*n*sizeof(double));
cudaMalloc(&device_matrix_B, n*l*sizeof(double));
cudaMalloc(&device_matrix_C, m*l*sizeof(double));
//initializing the matrixrix// Omit D and C
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
cudaMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), cudaMemcpyHostToDevice);
int num_blocks = (m*l + BLOCK_SIZE - 1)/BLOCK_SIZE;
cudaEventRecord(start);
device_Matrix_multi <<<num_blocks, BLOCK_SIZE>>> (
device_matrix_A,
device_matrix_B,
device_matrix_C,
m,
n,
l
);
cudaMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
//print to check whether the matrixrixs give correct output or not
}
}
cudaEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n",milliseconds);
cudaFree(device_matrix_A);
cudaFree(device_matrix_B);
cudaFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
} | .file "tmpxft_0017f1ac_00000000-6_algorithm1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii
.type _Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii, @function
_Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19device_Matrix_multiPKdS0_Pdiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii, .-_Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii
.globl _Z19device_Matrix_multiPKdS0_Pdiii
.type _Z19device_Matrix_multiPKdS0_Pdiii, @function
_Z19device_Matrix_multiPKdS0_Pdiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19device_Matrix_multiPKdS0_Pdiii, .-_Z19device_Matrix_multiPKdS0_Pdiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "inside function"
.LC3:
.string "elaspsed = %f ms\n"
.text
.globl _Z10Algorithm1iii
.type _Z10Algorithm1iii, @function
_Z10Algorithm1iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movl %edi, %ebx
movl %esi, %r12d
movl %edx, %r14d
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 68(%rsp)
movl %ebx, %eax
imull %r12d, %eax
cltq
salq $3, %rax
movq %rax, 32(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r15
movl %ebx, 20(%rsp)
movl %r14d, 48(%rsp)
imull %r14d, %ebx
movslq %ebx, %rax
leaq 0(,%rax,8), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
leaq 72(%rsp), %rdi
movq 32(%rsp), %rsi
call cudaMalloc@PLT
movl 48(%rsp), %eax
imull %r12d, %eax
cltq
leaq 0(,%rax,8), %rdi
movq %rdi, %rsi
movq %rdi, 40(%rsp)
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
cmpl $0, 20(%rsp)
jle .L12
movl $0, %ecx
movl $0, %edx
movslq %r12d, %rax
movq %rax, 24(%rsp)
movl %ebx, 52(%rsp)
movq %rbp, 56(%rsp)
movl %r12d, %esi
movl %ecx, %r12d
jmp .L13
.L15:
movslq %r12d, %rbp
leaq 0(,%rbp,8), %rbx
movq 24(%rsp), %rax
addq %rax, %rbp
salq $3, %rbp
movl %edx, 12(%rsp)
movl %esi, 16(%rsp)
.L14:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r15,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r14,%rbx)
movq $0x000000000, 0(%r13,%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L14
movl 12(%rsp), %edx
movl 16(%rsp), %esi
.L16:
addl $1, %edx
addl %esi, %r12d
cmpl %edx, 20(%rsp)
je .L29
.L13:
testl %esi, %esi
jg .L15
jmp .L16
.L29:
movl 52(%rsp), %ebx
movq 56(%rsp), %rbp
movl %esi, %r12d
.L12:
movl $1, %ecx
movq 32(%rsp), %rdx
movq %r15, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq 40(%rsp), %rdx
movq %r14, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 124(%rsp)
movl $1, 128(%rsp)
leal 510(%rbx), %eax
addl $255, %ebx
cmovns %ebx, %eax
sarl $8, %eax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L17:
movl $2, %ecx
movq %rbp, %rdx
movq 88(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %edx
movl 20(%rsp), %ecx
cmpl $0, 20(%rsp)
jg .L18
.L19:
leaq 68(%rsp), %rdi
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl 48(%rsp), %r9d
movl %r12d, %r8d
movl 20(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii
jmp .L17
.L20:
addl $1, %eax
cmpl %eax, %r12d
jne .L20
.L21:
addl $1, %edx
cmpl %edx, %ecx
je .L19
.L18:
movl $0, %eax
testl %r12d, %r12d
jg .L20
jmp .L21
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z10Algorithm1iii, .-_Z10Algorithm1iii
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $32, %edx
movl $32, %esi
movl $32, %edi
call _Z10Algorithm1iii
movl $64, %edx
movl $64, %esi
movl $64, %edi
call _Z10Algorithm1iii
movl $128, %edx
movl $128, %esi
movl $128, %edi
call _Z10Algorithm1iii
movl $256, %edx
movl $256, %esi
movl $256, %edi
call _Z10Algorithm1iii
movl $512, %edx
movl $512, %esi
movl $512, %edi
call _Z10Algorithm1iii
movl $1024, %edx
movl $1024, %esi
movl $1024, %edi
call _Z10Algorithm1iii
movl $2048, %edx
movl $2048, %esi
movl $2048, %edi
call _Z10Algorithm1iii
movl $4096, %edx
movl $4096, %esi
movl $4096, %edi
call _Z10Algorithm1iii
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z19device_Matrix_multiPKdS0_Pdiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z19device_Matrix_multiPKdS0_Pdiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
void Algorithm1(int m, int n, int l);
#define BLOCK_SIZE 256
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,
double* device_matrix_C,
const int m,
const int n,
const int l
)
{
int threadid = threadIdx.x + blockDim.x*blockIdx.x;
int column = threadid%l;
int row = threadid/l;
if (row >= m || column >= l)
{
return;
}
int idx = column*m + row;
double sum = 0.0;
for (int k = 0; k < n; k++){
int idxA = k*m + row;
int idxB = column*n + k;
sum += device_matrix_A[idxA]*device_matrix_B[idxB];
}
device_matrix_C[idx] = sum;
}
int main()
{
Algorithm1(32, 32, 32);
Algorithm1(64, 64, 64);
Algorithm1(128,128, 128);
Algorithm1(256, 256, 256);
Algorithm1(512, 512, 512);
Algorithm1(1024, 1024, 1024);
Algorithm1(2048, 2048, 2048);
Algorithm1(4096, 4096, 4096);
}
void Algorithm1(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
cudaMalloc(&device_matrix_A, m*n*sizeof(double));
cudaMalloc(&device_matrix_B, n*l*sizeof(double));
cudaMalloc(&device_matrix_C, m*l*sizeof(double));
//initializing the matrixrix// Omit D and C
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
cudaMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), cudaMemcpyHostToDevice);
int num_blocks = (m*l + BLOCK_SIZE - 1)/BLOCK_SIZE;
cudaEventRecord(start);
device_Matrix_multi <<<num_blocks, BLOCK_SIZE>>> (
device_matrix_A,
device_matrix_B,
device_matrix_C,
m,
n,
l
);
cudaMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
//print to check whether the matrixrixs give correct output or not
}
}
cudaEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n",milliseconds);
cudaFree(device_matrix_A);
cudaFree(device_matrix_B);
cudaFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
void Algorithm1(int m, int n, int l);
#define BLOCK_SIZE 256
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,
double* device_matrix_C,
const int m,
const int n,
const int l
)
{
int threadid = threadIdx.x + blockDim.x*blockIdx.x;
int column = threadid%l;
int row = threadid/l;
if (row >= m || column >= l)
{
return;
}
int idx = column*m + row;
double sum = 0.0;
for (int k = 0; k < n; k++){
int idxA = k*m + row;
int idxB = column*n + k;
sum += device_matrix_A[idxA]*device_matrix_B[idxB];
}
device_matrix_C[idx] = sum;
}
int main()
{
Algorithm1(32, 32, 32);
Algorithm1(64, 64, 64);
Algorithm1(128,128, 128);
Algorithm1(256, 256, 256);
Algorithm1(512, 512, 512);
Algorithm1(1024, 1024, 1024);
Algorithm1(2048, 2048, 2048);
Algorithm1(4096, 4096, 4096);
}
void Algorithm1(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
hipMalloc(&device_matrix_A, m*n*sizeof(double));
hipMalloc(&device_matrix_B, n*l*sizeof(double));
hipMalloc(&device_matrix_C, m*l*sizeof(double));
//initializing the matrixrix// Omit D and C
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
hipMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), hipMemcpyHostToDevice);
int num_blocks = (m*l + BLOCK_SIZE - 1)/BLOCK_SIZE;
hipEventRecord(start);
device_Matrix_multi <<<num_blocks, BLOCK_SIZE>>> (
device_matrix_A,
device_matrix_B,
device_matrix_C,
m,
n,
l
);
hipMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), hipMemcpyDeviceToHost);
hipEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
//print to check whether the matrixrixs give correct output or not
}
}
hipEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n",milliseconds);
hipFree(device_matrix_A);
hipFree(device_matrix_B);
hipFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
void Algorithm1(int m, int n, int l);
#define BLOCK_SIZE 256
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,
double* device_matrix_C,
const int m,
const int n,
const int l
)
{
int threadid = threadIdx.x + blockDim.x*blockIdx.x;
int column = threadid%l;
int row = threadid/l;
if (row >= m || column >= l)
{
return;
}
int idx = column*m + row;
double sum = 0.0;
for (int k = 0; k < n; k++){
int idxA = k*m + row;
int idxB = column*n + k;
sum += device_matrix_A[idxA]*device_matrix_B[idxB];
}
device_matrix_C[idx] = sum;
}
int main()
{
Algorithm1(32, 32, 32);
Algorithm1(64, 64, 64);
Algorithm1(128,128, 128);
Algorithm1(256, 256, 256);
Algorithm1(512, 512, 512);
Algorithm1(1024, 1024, 1024);
Algorithm1(2048, 2048, 2048);
Algorithm1(4096, 4096, 4096);
}
void Algorithm1(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
hipMalloc(&device_matrix_A, m*n*sizeof(double));
hipMalloc(&device_matrix_B, n*l*sizeof(double));
hipMalloc(&device_matrix_C, m*l*sizeof(double));
//initializing the matrixrix// Omit D and C
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
hipMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), hipMemcpyHostToDevice);
int num_blocks = (m*l + BLOCK_SIZE - 1)/BLOCK_SIZE;
hipEventRecord(start);
device_Matrix_multi <<<num_blocks, BLOCK_SIZE>>> (
device_matrix_A,
device_matrix_B,
device_matrix_C,
m,
n,
l
);
hipMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), hipMemcpyDeviceToHost);
hipEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
//print to check whether the matrixrixs give correct output or not
}
}
hipEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n",milliseconds);
hipFree(device_matrix_A);
hipFree(device_matrix_B);
hipFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19device_Matrix_multiPKdS0_Pdiii
.globl _Z19device_Matrix_multiPKdS0_Pdiii
.p2align 8
.type _Z19device_Matrix_multiPKdS0_Pdiii,@function
_Z19device_Matrix_multiPKdS0_Pdiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s4, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s5, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s3
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s5
s_cmp_gt_i32 s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, s2, v3
s_load_b32 s2, s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v3, v0
v_add_nc_u32_e32 v4, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s3, v2
v_add_nc_u32_e32 v0, v3, v0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v3, v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v0, v0, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s5, s3
s_cbranch_execz .LBB0_6
s_load_b32 s3, s[0:1], 0x1c
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v1, v2
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v1, v7, s3
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[8:9], 3, v[5:6]
v_add_nc_u32_e32 v5, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b64 v[10:11], v[3:4], off
global_load_b64 v[8:9], v[8:9], off
v_add_co_u32 v3, vcc_lo, v3, 8
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[1:2], v[8:9], v[10:11], v[1:2]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v7, s2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19device_Matrix_multiPKdS0_Pdiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19device_Matrix_multiPKdS0_Pdiii, .Lfunc_end0-_Z19device_Matrix_multiPKdS0_Pdiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19device_Matrix_multiPKdS0_Pdiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19device_Matrix_multiPKdS0_Pdiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
void Algorithm1(int m, int n, int l);
#define BLOCK_SIZE 256
__global__ void device_Matrix_multi(const double* const device_matrix_A,const double* const device_matrix_B,
double* device_matrix_C,
const int m,
const int n,
const int l
)
{
int threadid = threadIdx.x + blockDim.x*blockIdx.x;
int column = threadid%l;
int row = threadid/l;
if (row >= m || column >= l)
{
return;
}
int idx = column*m + row;
double sum = 0.0;
for (int k = 0; k < n; k++){
int idxA = k*m + row;
int idxB = column*n + k;
sum += device_matrix_A[idxA]*device_matrix_B[idxB];
}
device_matrix_C[idx] = sum;
}
int main()
{
Algorithm1(32, 32, 32);
Algorithm1(64, 64, 64);
Algorithm1(128,128, 128);
Algorithm1(256, 256, 256);
Algorithm1(512, 512, 512);
Algorithm1(1024, 1024, 1024);
Algorithm1(2048, 2048, 2048);
Algorithm1(4096, 4096, 4096);
}
void Algorithm1(int m, int n, int l) {
printf("inside function");
double* matrix_A;
double* matrix_B;
double* matrix_C;
double *device_matrix_A;
double *device_matrix_B;
double *device_matrix_C;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
// Allocate the device memory
matrix_A = (double*)malloc( m*n* sizeof(double));
matrix_B = (double*)malloc( m*l* sizeof(double));
matrix_C = (double*)malloc( m*l*sizeof(double));
hipMalloc(&device_matrix_A, m*n*sizeof(double));
hipMalloc(&device_matrix_B, n*l*sizeof(double));
hipMalloc(&device_matrix_C, m*l*sizeof(double));
//initializing the matrixrix// Omit D and C
for(int i = 0; i < m; i++)
{
for(int j = 0; j <n; j++){
matrix_A[i *n + j] = rand()%10;
matrix_B[i *n + j] = rand()%10;
matrix_C[i *n + j] = 0;
}
}
hipMemcpy(device_matrix_A, matrix_A, m*n*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(device_matrix_B, matrix_B, n*l*sizeof(double), hipMemcpyHostToDevice);
int num_blocks = (m*l + BLOCK_SIZE - 1)/BLOCK_SIZE;
hipEventRecord(start);
device_Matrix_multi <<<num_blocks, BLOCK_SIZE>>> (
device_matrix_A,
device_matrix_B,
device_matrix_C,
m,
n,
l
);
hipMemcpy(matrix_C, device_matrix_C, m*l*sizeof(double), hipMemcpyDeviceToHost);
hipEventRecord(stop);
for(int i=0; i<m;i++){
for(int j =0; j<n; j++){
//print to check whether the matrixrixs give correct output or not
}
}
hipEventElapsedTime(&milliseconds, start, stop);
printf("elaspsed = %f ms\n",milliseconds);
hipFree(device_matrix_A);
hipFree(device_matrix_B);
hipFree(device_matrix_C);
free(matrix_A);
free(matrix_B);
free(matrix_C);
} | .text
.file "algorithm1.hip"
.globl _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii # -- Begin function _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii
.p2align 4, 0x90
.type _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii,@function
_Z34__device_stub__device_Matrix_multiPKdS0_Pdiii: # @_Z34__device_stub__device_Matrix_multiPKdS0_Pdiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19device_Matrix_multiPKdS0_Pdiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii, .Lfunc_end0-_Z34__device_stub__device_Matrix_multiPKdS0_Pdiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $32, %edi
movl $32, %esi
movl $32, %edx
callq _Z10Algorithm1iii
movl $64, %edi
movl $64, %esi
movl $64, %edx
callq _Z10Algorithm1iii
movl $128, %edi
movl $128, %esi
movl $128, %edx
callq _Z10Algorithm1iii
movl $256, %edi # imm = 0x100
movl $256, %esi # imm = 0x100
movl $256, %edx # imm = 0x100
callq _Z10Algorithm1iii
movl $512, %edi # imm = 0x200
movl $512, %esi # imm = 0x200
movl $512, %edx # imm = 0x200
callq _Z10Algorithm1iii
movl $1024, %edi # imm = 0x400
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
callq _Z10Algorithm1iii
movl $2048, %edi # imm = 0x800
movl $2048, %esi # imm = 0x800
movl $2048, %edx # imm = 0x800
callq _Z10Algorithm1iii
movl $4096, %edi # imm = 0x1000
movl $4096, %esi # imm = 0x1000
movl $4096, %edx # imm = 0x1000
callq _Z10Algorithm1iii
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10Algorithm1iii # -- Begin function _Z10Algorithm1iii
.p2align 4, 0x90
.type _Z10Algorithm1iii,@function
_Z10Algorithm1iii: # @_Z10Algorithm1iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r12d
movl %edi, %r14d
xorl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
movl %r12d, %eax
imull %r14d, %eax
movslq %eax, %r15
shlq $3, %r15
movq %r15, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
movl %ebp, %eax
imull %r14d, %eax
movq %rax, 128(%rsp) # 8-byte Spill
movslq %eax, %rbx
shlq $3, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
leaq 40(%rsp), %rdi
movq %r15, 120(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
movl %ebp, 52(%rsp) # 4-byte Spill
imull %r12d, %ebp
movslq %ebp, %rsi
shlq $3, %rsi
leaq 32(%rsp), %rdi
movq %rsi, 112(%rsp) # 8-byte Spill
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, 136(%rsp) # 8-byte Spill
movq %rbx, %rsi
callq hipMalloc
movl %r14d, 8(%rsp) # 4-byte Spill
testl %r14d, %r14d
jle .LBB2_6
# %bb.1: # %.preheader63.lr.ph
movl 8(%rsp), %eax # 4-byte Reload
movq %rax, 144(%rsp) # 8-byte Spill
movl %r12d, %r14d
xorl %r15d, %r15d
movl %r12d, 56(%rsp) # 4-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r15
movl 56(%rsp), %r12d # 4-byte Reload
movq 16(%rsp), %rax # 8-byte Reload
addl %r12d, %eax
movq %rax, 16(%rsp) # 8-byte Spill
cmpq 144(%rsp), %r15 # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader63
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %r12d, %r12d
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl 16(%rsp), %eax # 4-byte Reload
movq 72(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbp
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r13
movq 88(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r12,8)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r13,%r12,8)
movq $0, (%rbp,%r12,8)
incq %r12
cmpq %r12, %r14
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge66
movq 40(%rsp), %rdi
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq 120(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 80(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 128(%rsp), %r15 # 8-byte Reload
leal 255(%r15), %eax
addl $510, %r15d # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %r15d
sarl $8, %r15d
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r15
orq $256, %rdx # imm = 0x100
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movq %rdx, 200(%rsp)
movl 8(%rsp), %eax # 4-byte Reload
movl %eax, 68(%rsp)
movl %r12d, 64(%rsp)
movl 52(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 200(%rsp), %rax
movq %rax, 240(%rsp)
leaq 68(%rsp), %rax
movq %rax, 248(%rsp)
leaq 64(%rsp), %rax
movq %rax, 256(%rsp)
leaq 60(%rsp), %rax
movq %rax, 264(%rsp)
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z19device_Matrix_multiPKdS0_Pdiii, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8: # %._crit_edge68
movq 24(%rsp), %rsi
movq 72(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq 136(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 104(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10Algorithm1iii, .Lfunc_end2-_Z10Algorithm1iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19device_Matrix_multiPKdS0_Pdiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19device_Matrix_multiPKdS0_Pdiii,@object # @_Z19device_Matrix_multiPKdS0_Pdiii
.section .rodata,"a",@progbits
.globl _Z19device_Matrix_multiPKdS0_Pdiii
.p2align 3, 0x0
_Z19device_Matrix_multiPKdS0_Pdiii:
.quad _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii
.size _Z19device_Matrix_multiPKdS0_Pdiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "inside function"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "elaspsed = %f ms\n"
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19device_Matrix_multiPKdS0_Pdiii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19device_Matrix_multiPKdS0_Pdiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19device_Matrix_multiPKdS0_Pdiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R7, c[0x0][0x180] ; /* 0x0000600000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00a0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00b0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fe200078e02ff */
/*00c0*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc80000000000 */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a00 */
/*0100*/ IMAD R2, R7, R3, R6 ; /* 0x0000000307027224 */
/* 0x000fca00078e0206 */
/*0110*/ ISETP.GT.U32.AND P2, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f44070 */
/*0120*/ @!P2 IADD3 R2, R2, -R7.reuse, RZ ; /* 0x800000070202a210 */
/* 0x080fe40007ffe0ff */
/*0130*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*0150*/ LOP3.LUT R2, R4, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600004027a12 */
/* 0x000fe400078e3cff */
/*0160*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f45270 */
/*0170*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*0180*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fcc0007ffe0ff */
/*0190*/ @!P1 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff009224 */
/* 0x000fe200078e0a00 */
/*01a0*/ @!P2 LOP3.LUT R0, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff00aa12 */
/* 0x000fc800078e33ff */
/*01b0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06270 */
/*01c0*/ ISETP.GT.OR P0, PT, RZ, c[0x0][0x180], P0 ; /* 0x00006000ff007a0c */
/* 0x000fda0000704670 */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01e0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a00 */
/*0200*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0210*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0220*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0230*/ IMAD R3, R3, c[0x0][0x180], R4 ; /* 0x0000600003037a24 */
/* 0x000fd800078e0204 */
/*0240*/ @!P0 BRA 0xd70 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0260*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0270*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*0280*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0290*/ MOV R26, RZ ; /* 0x000000ff001a7202 */
/* 0x000fd60000000f00 */
/*02a0*/ @!P0 BRA 0xc30 ; /* 0x0000098000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IADD3 R4, -R2, c[0x0][0x17c], RZ ; /* 0x00005f0002047a10 */
/* 0x000fe20007ffe1ff */
/*02c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*02d0*/ HFMA2.MMA R26, -RZ, RZ, 0, 0 ; /* 0x00000000ff1a7435 */
/* 0x000fe200000001ff */
/*02e0*/ IMAD R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a24 */
/* 0x000fe200078e02ff */
/*02f0*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f04270 */
/*0300*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0310*/ IMAD.WIDE R28, R0, R5, c[0x0][0x160] ; /* 0x00005800001c7625 */
/* 0x000fc800078e0205 */
/*0320*/ IMAD.WIDE R6, R6, R5, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fce00078e0205 */
/*0330*/ @!P0 BRA 0xab0 ; /* 0x0000077000008947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0360*/ @!P1 BRA 0x800 ; /* 0x0000049000009947 */
/* 0x000fea0003800000 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0380*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1b00 */
/*0390*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x0010a2000c1e1b00 */
/*03a0*/ IMAD.WIDE R24, R5, c[0x0][0x178], R28 ; /* 0x00005e0005187a25 */
/* 0x000fc600078e021c */
/*03b0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*03c0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*03d0*/ IMAD.WIDE R22, R5, c[0x0][0x178], R24 ; /* 0x00005e0005167a25 */
/* 0x000fc600078e0218 */
/*03e0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f28000c1e1b00 */
/*03f0*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x002322000c1e1b00 */
/*0400*/ IMAD.WIDE R28, R5, c[0x0][0x178], R22 ; /* 0x00005e00051c7a25 */
/* 0x001fca00078e0216 */
/*0410*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002162000c1e1b00 */
/*0420*/ DFMA R18, R20, R10, R18 ; /* 0x0000000a1412722b */
/* 0x0042c60000000012 */
/*0430*/ LDG.E.64 R10, [R6.64+0x18] ; /* 0x00001804060a7981 */
/* 0x002f62000c1e1b00 */
/*0440*/ IMAD.WIDE R28, R5.reuse, c[0x0][0x178], R28 ; /* 0x00005e00051c7a25 */
/* 0x041fe400078e021c */
/*0450*/ DFMA R18, R16, R8, R18 ; /* 0x000000081012722b */
/* 0x0081240000000012 */
/*0460*/ LDG.E.64 R8, [R6.64+0x20] ; /* 0x0000200406087981 */
/* 0x001ea8000c1e1b00 */
/*0470*/ LDG.E.64 R16, [R28.64] ; /* 0x000000041c107981 */
/* 0x000ea2000c1e1b00 */
/*0480*/ IMAD.WIDE R24, R5, c[0x0][0x178], R28 ; /* 0x00005e0005187a25 */
/* 0x000fe200078e021c */
/*0490*/ DFMA R18, R14, R12, R18 ; /* 0x0000000c0e12722b */
/* 0x0101440000000012 */
/*04a0*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001ee8000c1e1b00 */
/*04b0*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000ee2000c1e1b00 */
/*04c0*/ IMAD.WIDE R20, R5, c[0x0][0x178], R24 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0218 */
/*04d0*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x0200a40000000012 */
/*04e0*/ LDG.E.64 R10, [R6.64+0x30] ; /* 0x00003004060a7981 */
/* 0x001f28000c1e1b00 */
/*04f0*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x000122000c1e1b00 */
/*0500*/ DFMA R16, R8, R16, R22 ; /* 0x000000100810722b */
/* 0x0042c60000000016 */
/*0510*/ LDG.E.64 R8, [R6.64+0x38] ; /* 0x0000380406087981 */
/* 0x002ea2000c1e1b00 */
/*0520*/ IMAD.WIDE R20, R5, c[0x0][0x178], R20 ; /* 0x00005e0005147a25 */
/* 0x001fca00078e0214 */
/*0530*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ea2000c1e1b00 */
/*0540*/ IMAD.WIDE R28, R5.reuse, c[0x0][0x178], R20 ; /* 0x00005e00051c7a25 */
/* 0x040fe200078e0214 */
/*0550*/ DFMA R12, R14, R12, R16 ; /* 0x0000000c0e0c722b */
/* 0x0081240000000010 */
/*0560*/ LDG.E.64 R16, [R6.64+0x40] ; /* 0x0000400406107981 */
/* 0x001ee8000c1e1b00 */
/*0570*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ee2000c1e1b00 */
/*0580*/ IMAD.WIDE R24, R5, c[0x0][0x178], R28 ; /* 0x00005e0005187a25 */
/* 0x000fe200078e021c */
/*0590*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x010084000000000c */
/*05a0*/ LDG.E.64 R12, [R6.64+0x48] ; /* 0x00004804060c7981 */
/* 0x001f28000c1e1b00 */
/*05b0*/ LDG.E.64 R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000124000c1e1b00 */
/*05c0*/ IMAD.WIDE R24, R5.reuse, c[0x0][0x178], R24 ; /* 0x00005e0005187a25 */
/* 0x041fe200078e0218 */
/*05d0*/ DFMA R22, R8, R22, R18 ; /* 0x000000160816722b */
/* 0x0040e40000000012 */
/*05e0*/ LDG.E.64 R8, [R6.64+0x50] ; /* 0x0000500406087981 */
/* 0x001ea8000c1e1b00 */
/*05f0*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ea2000c1e1b00 */
/*0600*/ IMAD.WIDE R20, R5, c[0x0][0x178], R24 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0218 */
/*0610*/ DFMA R14, R16, R14, R22 ; /* 0x0000000e100e722b */
/* 0x0081040000000016 */
/*0620*/ LDG.E.64 R16, [R6.64+0x58] ; /* 0x0000580406107981 */
/* 0x001ee8000c1e1b00 */
/*0630*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ee2000c1e1b00 */
/*0640*/ IMAD.WIDE R28, R5.reuse, c[0x0][0x178], R20 ; /* 0x00005e00051c7a25 */
/* 0x040fe200078e0214 */
/*0650*/ DFMA R10, R12, R10, R14 ; /* 0x0000000a0c0a722b */
/* 0x0100a4000000000e */
/*0660*/ LDG.E.64 R14, [R6.64+0x60] ; /* 0x00006004060e7981 */
/* 0x001f28000c1e1b00 */
/*0670*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x000124000c1e1b00 */
/*0680*/ IMAD.WIDE R28, R5, c[0x0][0x178], R28 ; /* 0x00005e00051c7a25 */
/* 0x001fe200078e021c */
/*0690*/ DFMA R18, R8, R18, R10 ; /* 0x000000120812722b */
/* 0x0040c4000000000a */
/*06a0*/ LDG.E.64 R8, [R6.64+0x68] ; /* 0x0000680406087981 */
/* 0x001ea6000c1e1b00 */
/*06b0*/ IMAD.WIDE R24, R5, c[0x0][0x178], R28 ; /* 0x00005e0005187a25 */
/* 0x000fe200078e021c */
/*06c0*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ea2000c1e1b00 */
/*06d0*/ DFMA R22, R16, R22, R18 ; /* 0x000000161016722b */
/* 0x0081060000000012 */
/*06e0*/ LDG.E.64 R16, [R6.64+0x70] ; /* 0x0000700406107981 */
/* 0x001ee2000c1e1b00 */
/*06f0*/ IMAD.WIDE R20, R5, c[0x0][0x178], R24 ; /* 0x00005e0005147a25 */
/* 0x000fc600078e0218 */
/*0700*/ LDG.E.64 R18, [R24.64] ; /* 0x0000000418127981 */
/* 0x000ee2000c1e1b00 */
/*0710*/ DFMA R22, R14, R12, R22 ; /* 0x0000000c0e16722b */
/* 0x0100860000000016 */
/*0720*/ LDG.E.64 R12, [R6.64+0x78] ; /* 0x00007804060c7981 */
/* 0x001128000c1e1b00 */
/*0730*/ LDG.E.64 R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000f22000c1e1b00 */
/*0740*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc80007ffe0ff */
/*0750*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*0760*/ DFMA R8, R8, R10, R22 ; /* 0x0000000a0808722b */
/* 0x004ecc0000000016 */
/*0770*/ DFMA R18, R16, R18, R8 ; /* 0x000000121012722b */
/* 0x0083240000000008 */
/*0780*/ IADD3 R8, P2, R6, 0x80, RZ ; /* 0x0000008006087810 */
/* 0x002fe20007f5e0ff */
/*0790*/ IMAD.WIDE R28, R5, c[0x0][0x178], R20 ; /* 0x00005e00051c7a25 */
/* 0x000fc800078e0214 */
/*07a0*/ IMAD.X R9, RZ, RZ, R7, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0607 */
/*07b0*/ IADD3 R26, R26, 0x10, RZ ; /* 0x000000101a1a7810 */
/* 0x000fe40007ffe0ff */
/*07c0*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x001fe20000000f00 */
/*07d0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*07e0*/ DFMA R18, R12, R14, R18 ; /* 0x0000000e0c12722b */
/* 0x0100620000000012 */
/*07f0*/ @P1 BRA 0x380 ; /* 0xfffffb8000001947 */
/* 0x000fea000383ffff */
/*0800*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0810*/ @!P1 BRA 0xa90 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0820*/ LDG.E.64 R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1b00 */
/*0830*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x0010a2000c1e1b00 */
/*0840*/ IMAD.WIDE R22, R5, c[0x0][0x178], R28 ; /* 0x00005e0005167a25 */
/* 0x000fc600078e021c */
/*0850*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*0860*/ LDG.E.64 R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x0008e8000c1e1b00 */
/*0870*/ LDG.E.64 R8, [R6.64+0x10] ; /* 0x0000100406087981 */
/* 0x000f62000c1e1b00 */
/*0880*/ IMAD.WIDE R22, R5, c[0x0][0x178], R22 ; /* 0x00005e0005167a25 */
/* 0x010fca00078e0216 */
/*0890*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x000f62000c1e1b00 */
/*08a0*/ IMAD.WIDE R24, R5, c[0x0][0x178], R22 ; /* 0x00005e0005187a25 */
/* 0x000fcc00078e0216 */
/*08b0*/ IMAD.WIDE R28, R5, c[0x0][0x178], R24 ; /* 0x00005e00051c7a25 */
/* 0x001fe200078e0218 */
/*08c0*/ DFMA R18, R20, R12, R18 ; /* 0x0000000c1412722b */
/* 0x0060e40000000012 */
/*08d0*/ LDG.E.64 R12, [R6.64+0x18] ; /* 0x00001804060c7981 */
/* 0x001ea8000c1e1b00 */
/*08e0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000418147981 */
/* 0x0000a2000c1e1b00 */
/*08f0*/ DFMA R10, R16, R10, R18 ; /* 0x0000000a100a722b */
/* 0x0083460000000012 */
/*0900*/ LDG.E.64 R16, [R6.64+0x20] ; /* 0x0000200406107981 */
/* 0x002ee8000c1e1b00 */
/*0910*/ LDG.E.64 R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x0002e2000c1e1b00 */
/*0920*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x0208a2000000000a */
/*0930*/ IMAD.WIDE R28, R5.reuse, c[0x0][0x178], R28 ; /* 0x00005e00051c7a25 */
/* 0x042fe400078e021c */
/*0940*/ LDG.E.64 R8, [R6.64+0x28] ; /* 0x0000280406087981 */
/* 0x010f28000c1e1b00 */
/*0950*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000f22000c1e1b00 */
/*0960*/ IMAD.WIDE R22, R5, c[0x0][0x178], R28 ; /* 0x00005e0005167a25 */
/* 0x000fcc00078e021c */
/*0970*/ IMAD.WIDE R24, R5, c[0x0][0x178], R22 ; /* 0x00005e0005187a25 */
/* 0x001fe200078e0216 */
/*0980*/ DFMA R20, R12, R20, R14 ; /* 0x000000140c14722b */
/* 0x0040e4000000000e */
/*0990*/ LDG.E.64 R12, [R6.64+0x30] ; /* 0x00003004060c7981 */
/* 0x0010a8000c1e1b00 */
/*09a0*/ LDG.E.64 R14, [R22.64] ; /* 0x00000004160e7981 */
/* 0x000ea2000c1e1b00 */
/*09b0*/ DFMA R20, R16, R18, R20 ; /* 0x000000121014722b */
/* 0x0083060000000014 */
/*09c0*/ LDG.E.64 R18, [R6.64+0x38] ; /* 0x0000380406127981 */
/* 0x0020e8000c1e1b00 */
/*09d0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000ee2000c1e1b00 */
/*09e0*/ DFMA R8, R8, R10, R20 ; /* 0x0000000a0808722b */
/* 0x0102a40000000014 */
/*09f0*/ IADD3 R10, P1, R6, 0x40, RZ ; /* 0x00000040060a7810 */
/* 0x002fc80007f3e0ff */
/*0a00*/ IADD3.X R11, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0b7210 */
/* 0x000fe20000ffe4ff */
/*0a10*/ IMAD.WIDE R28, R5, c[0x0][0x178], R24 ; /* 0x00005e00051c7a25 */
/* 0x000fe200078e0218 */
/*0a20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0a30*/ IADD3 R26, R26, 0x8, RZ ; /* 0x000000081a1a7810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x001fe200078e000a */
/*0a50*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe40007ffe0ff */
/*0a60*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fe20000000f00 */
/*0a70*/ DFMA R8, R12, R14, R8 ; /* 0x0000000e0c08722b */
/* 0x004ecc0000000008 */
/*0a80*/ DFMA R18, R18, R16, R8 ; /* 0x000000101212722b */
/* 0x0080480000000008 */
/*0a90*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0aa0*/ @!P0 BRA 0xc30 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ LDG.E.64 R22, [R6.64] ; /* 0x0000000406167981 */
/* 0x000ea8000c1e1b00 */
/*0ac0*/ LDG.E.64 R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x001ea2000c1e1b00 */
/*0ad0*/ IMAD.WIDE R24, R5, c[0x0][0x178], R28 ; /* 0x00005e0005187a25 */
/* 0x000fc600078e021c */
/*0ae0*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ee8000c1e1b00 */
/*0af0*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x0000e8000c1e1b00 */
/*0b00*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f22000c1e1b00 */
/*0b10*/ IMAD.WIDE R24, R5, c[0x0][0x178], R24 ; /* 0x00005e0005187a25 */
/* 0x001fca00078e0218 */
/*0b20*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000f22000c1e1b00 */
/*0b30*/ IMAD.WIDE R20, R5, c[0x0][0x178], R24 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0218 */
/*0b40*/ DFMA R22, R22, R8, R18 ; /* 0x000000081616722b */
/* 0x0060e40000000012 */
/*0b50*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x0010a8000c1e1b00 */
/*0b60*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ea2000c1e1b00 */
/*0b70*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0b80*/ DFMA R10, R10, R12, R22 ; /* 0x0000000c0a0a722b */
/* 0x0083060000000016 */
/*0b90*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0ba0*/ IADD3 R12, P1, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x002fc80007f3e0ff */
/*0bb0*/ IADD3.X R13, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fe20000ffe4ff */
/*0bc0*/ DFMA R10, R14, R16, R10 ; /* 0x000000100e0a722b */
/* 0x010ea2000000000a */
/*0bd0*/ IADD3 R26, R26, 0x4, RZ ; /* 0x000000041a1a7810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ IMAD.WIDE R28, R5, c[0x0][0x178], R20 ; /* 0x00005e00051c7a25 */
/* 0x000fe200078e0214 */
/*0bf0*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x001fc60000000f00 */
/*0c00*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*0c10*/ DFMA R18, R18, R8, R10 ; /* 0x000000081212722b */
/* 0x004064000000000a */
/*0c20*/ @P0 BRA 0xab0 ; /* 0xfffffe8000000947 */
/* 0x003fea000383ffff */
/*0c30*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0c40*/ @!P0 BRA 0xd70 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0c50*/ MOV R13, 0x8 ; /* 0x00000008000d7802 */
/* 0x001fe20000000f00 */
/*0c60*/ IMAD R4, R3, c[0x0][0x17c], R26 ; /* 0x00005f0003047a24 */
/* 0x000fe400078e021a */
/*0c70*/ IMAD R6, R26, c[0x0][0x178], R0 ; /* 0x00005e001a067a24 */
/* 0x000fe400078e0200 */
/*0c80*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020d */
/*0c90*/ IMAD.WIDE R6, R6, R13, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e020d */
/*0ca0*/ MOV R11, R5 ; /* 0x00000005000b7202 */
/* 0x000fc60000000f00 */
/*0cb0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0004 */
/*0cc0*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x001fe20000000f00 */
/*0cd0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0ce0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0000aa000c1e1b00 */
/*0cf0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0d00*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0d10*/ IADD3 R10, P1, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fc40007f3e0ff */
/*0d20*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0d30*/ IMAD.WIDE R6, R13, c[0x0][0x178], R6 ; /* 0x00005e000d067a25 */
/* 0x001fe200078e0206 */
/*0d40*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0d50*/ DFMA R18, R4, R8, R18 ; /* 0x000000080412722b */
/* 0x0060540000000012 */
/*0d60*/ @P0 BRA 0xcc0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0d70*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fe20000000f00 */
/*0d80*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fc800078e0200 */
/*0d90*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0da0*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x002fe2000c101b04 */
/*0db0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dc0*/ BRA 0xdc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19device_Matrix_multiPKdS0_Pdiii
.globl _Z19device_Matrix_multiPKdS0_Pdiii
.p2align 8
.type _Z19device_Matrix_multiPKdS0_Pdiii,@function
_Z19device_Matrix_multiPKdS0_Pdiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s4, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s5, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s3
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s5
s_cmp_gt_i32 s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, s2, v3
s_load_b32 s2, s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v3, v0
v_add_nc_u32_e32 v4, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s3, v2
v_add_nc_u32_e32 v0, v3, v0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v3, v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_cmp_le_u32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v0, v0, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s5, s3
s_cbranch_execz .LBB0_6
s_load_b32 s3, s[0:1], 0x1c
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v1, v2
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v1, v7, s3
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[8:9], 3, v[5:6]
v_add_nc_u32_e32 v5, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b64 v[10:11], v[3:4], off
global_load_b64 v[8:9], v[8:9], off
v_add_co_u32 v3, vcc_lo, v3, 8
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[1:2], v[8:9], v[10:11], v[1:2]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v7, s2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19device_Matrix_multiPKdS0_Pdiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19device_Matrix_multiPKdS0_Pdiii, .Lfunc_end0-_Z19device_Matrix_multiPKdS0_Pdiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19device_Matrix_multiPKdS0_Pdiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19device_Matrix_multiPKdS0_Pdiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017f1ac_00000000-6_algorithm1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii
.type _Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii, @function
_Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19device_Matrix_multiPKdS0_Pdiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii, .-_Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii
.globl _Z19device_Matrix_multiPKdS0_Pdiii
.type _Z19device_Matrix_multiPKdS0_Pdiii, @function
_Z19device_Matrix_multiPKdS0_Pdiii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19device_Matrix_multiPKdS0_Pdiii, .-_Z19device_Matrix_multiPKdS0_Pdiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "inside function"
.LC3:
.string "elaspsed = %f ms\n"
.text
.globl _Z10Algorithm1iii
.type _Z10Algorithm1iii, @function
_Z10Algorithm1iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movl %edi, %ebx
movl %esi, %r12d
movl %edx, %r14d
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 68(%rsp)
movl %ebx, %eax
imull %r12d, %eax
cltq
salq $3, %rax
movq %rax, 32(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r15
movl %ebx, 20(%rsp)
movl %r14d, 48(%rsp)
imull %r14d, %ebx
movslq %ebx, %rax
leaq 0(,%rax,8), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
leaq 72(%rsp), %rdi
movq 32(%rsp), %rsi
call cudaMalloc@PLT
movl 48(%rsp), %eax
imull %r12d, %eax
cltq
leaq 0(,%rax,8), %rdi
movq %rdi, %rsi
movq %rdi, 40(%rsp)
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
cmpl $0, 20(%rsp)
jle .L12
movl $0, %ecx
movl $0, %edx
movslq %r12d, %rax
movq %rax, 24(%rsp)
movl %ebx, 52(%rsp)
movq %rbp, 56(%rsp)
movl %r12d, %esi
movl %ecx, %r12d
jmp .L13
.L15:
movslq %r12d, %rbp
leaq 0(,%rbp,8), %rbx
movq 24(%rsp), %rax
addq %rax, %rbp
salq $3, %rbp
movl %edx, 12(%rsp)
movl %esi, 16(%rsp)
.L14:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r15,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r14,%rbx)
movq $0x000000000, 0(%r13,%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L14
movl 12(%rsp), %edx
movl 16(%rsp), %esi
.L16:
addl $1, %edx
addl %esi, %r12d
cmpl %edx, 20(%rsp)
je .L29
.L13:
testl %esi, %esi
jg .L15
jmp .L16
.L29:
movl 52(%rsp), %ebx
movq 56(%rsp), %rbp
movl %esi, %r12d
.L12:
movl $1, %ecx
movq 32(%rsp), %rdx
movq %r15, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq 40(%rsp), %rdx
movq %r14, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 124(%rsp)
movl $1, 128(%rsp)
leal 510(%rbx), %eax
addl $255, %ebx
cmovns %ebx, %eax
sarl $8, %eax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L17:
movl $2, %ecx
movq %rbp, %rdx
movq 88(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %edx
movl 20(%rsp), %ecx
cmpl $0, 20(%rsp)
jg .L18
.L19:
leaq 68(%rsp), %rdi
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl 48(%rsp), %r9d
movl %r12d, %r8d
movl 20(%rsp), %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z48__device_stub__Z19device_Matrix_multiPKdS0_PdiiiPKdS0_Pdiii
jmp .L17
.L20:
addl $1, %eax
cmpl %eax, %r12d
jne .L20
.L21:
addl $1, %edx
cmpl %edx, %ecx
je .L19
.L18:
movl $0, %eax
testl %r12d, %r12d
jg .L20
jmp .L21
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z10Algorithm1iii, .-_Z10Algorithm1iii
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $32, %edx
movl $32, %esi
movl $32, %edi
call _Z10Algorithm1iii
movl $64, %edx
movl $64, %esi
movl $64, %edi
call _Z10Algorithm1iii
movl $128, %edx
movl $128, %esi
movl $128, %edi
call _Z10Algorithm1iii
movl $256, %edx
movl $256, %esi
movl $256, %edi
call _Z10Algorithm1iii
movl $512, %edx
movl $512, %esi
movl $512, %edi
call _Z10Algorithm1iii
movl $1024, %edx
movl $1024, %esi
movl $1024, %edi
call _Z10Algorithm1iii
movl $2048, %edx
movl $2048, %esi
movl $2048, %edi
call _Z10Algorithm1iii
movl $4096, %edx
movl $4096, %esi
movl $4096, %edi
call _Z10Algorithm1iii
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z19device_Matrix_multiPKdS0_Pdiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z19device_Matrix_multiPKdS0_Pdiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "algorithm1.hip"
.globl _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii # -- Begin function _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii
.p2align 4, 0x90
.type _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii,@function
_Z34__device_stub__device_Matrix_multiPKdS0_Pdiii: # @_Z34__device_stub__device_Matrix_multiPKdS0_Pdiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19device_Matrix_multiPKdS0_Pdiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii, .Lfunc_end0-_Z34__device_stub__device_Matrix_multiPKdS0_Pdiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $32, %edi
movl $32, %esi
movl $32, %edx
callq _Z10Algorithm1iii
movl $64, %edi
movl $64, %esi
movl $64, %edx
callq _Z10Algorithm1iii
movl $128, %edi
movl $128, %esi
movl $128, %edx
callq _Z10Algorithm1iii
movl $256, %edi # imm = 0x100
movl $256, %esi # imm = 0x100
movl $256, %edx # imm = 0x100
callq _Z10Algorithm1iii
movl $512, %edi # imm = 0x200
movl $512, %esi # imm = 0x200
movl $512, %edx # imm = 0x200
callq _Z10Algorithm1iii
movl $1024, %edi # imm = 0x400
movl $1024, %esi # imm = 0x400
movl $1024, %edx # imm = 0x400
callq _Z10Algorithm1iii
movl $2048, %edi # imm = 0x800
movl $2048, %esi # imm = 0x800
movl $2048, %edx # imm = 0x800
callq _Z10Algorithm1iii
movl $4096, %edi # imm = 0x1000
movl $4096, %esi # imm = 0x1000
movl $4096, %edx # imm = 0x1000
callq _Z10Algorithm1iii
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10Algorithm1iii # -- Begin function _Z10Algorithm1iii
.p2align 4, 0x90
.type _Z10Algorithm1iii,@function
_Z10Algorithm1iii: # @_Z10Algorithm1iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r12d
movl %edi, %r14d
xorl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
movl %r12d, %eax
imull %r14d, %eax
movslq %eax, %r15
shlq $3, %r15
movq %r15, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
movl %ebp, %eax
imull %r14d, %eax
movq %rax, 128(%rsp) # 8-byte Spill
movslq %eax, %rbx
shlq $3, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
leaq 40(%rsp), %rdi
movq %r15, 120(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
movl %ebp, 52(%rsp) # 4-byte Spill
imull %r12d, %ebp
movslq %ebp, %rsi
shlq $3, %rsi
leaq 32(%rsp), %rdi
movq %rsi, 112(%rsp) # 8-byte Spill
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, 136(%rsp) # 8-byte Spill
movq %rbx, %rsi
callq hipMalloc
movl %r14d, 8(%rsp) # 4-byte Spill
testl %r14d, %r14d
jle .LBB2_6
# %bb.1: # %.preheader63.lr.ph
movl 8(%rsp), %eax # 4-byte Reload
movq %rax, 144(%rsp) # 8-byte Spill
movl %r12d, %r14d
xorl %r15d, %r15d
movl %r12d, 56(%rsp) # 4-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r15
movl 56(%rsp), %r12d # 4-byte Reload
movq 16(%rsp), %rax # 8-byte Reload
addl %r12d, %eax
movq %rax, 16(%rsp) # 8-byte Spill
cmpq 144(%rsp), %r15 # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader63
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %r12d, %r12d
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl 16(%rsp), %eax # 4-byte Reload
movq 72(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbp
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r13
movq 88(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r12,8)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r13,%r12,8)
movq $0, (%rbp,%r12,8)
incq %r12
cmpq %r12, %r14
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge66
movq 40(%rsp), %rdi
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq 120(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 80(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq 112(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 128(%rsp), %r15 # 8-byte Reload
leal 255(%r15), %eax
addl $510, %r15d # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %r15d
sarl $8, %r15d
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r15
orq $256, %rdx # imm = 0x100
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movq %rdx, 200(%rsp)
movl 8(%rsp), %eax # 4-byte Reload
movl %eax, 68(%rsp)
movl %r12d, 64(%rsp)
movl 52(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 200(%rsp), %rax
movq %rax, 240(%rsp)
leaq 68(%rsp), %rax
movq %rax, 248(%rsp)
leaq 64(%rsp), %rax
movq %rax, 256(%rsp)
leaq 60(%rsp), %rax
movq %rax, 264(%rsp)
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z19device_Matrix_multiPKdS0_Pdiii, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8: # %._crit_edge68
movq 24(%rsp), %rsi
movq 72(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq 136(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 104(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10Algorithm1iii, .Lfunc_end2-_Z10Algorithm1iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19device_Matrix_multiPKdS0_Pdiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19device_Matrix_multiPKdS0_Pdiii,@object # @_Z19device_Matrix_multiPKdS0_Pdiii
.section .rodata,"a",@progbits
.globl _Z19device_Matrix_multiPKdS0_Pdiii
.p2align 3, 0x0
_Z19device_Matrix_multiPKdS0_Pdiii:
.quad _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii
.size _Z19device_Matrix_multiPKdS0_Pdiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "inside function"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "elaspsed = %f ms\n"
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19device_Matrix_multiPKdS0_Pdiii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__device_Matrix_multiPKdS0_Pdiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19device_Matrix_multiPKdS0_Pdiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Sqrt( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sqrt(abs(x[(idx-1)*N+i])*W0);
}
return;
} | code for sm_80
Function : _Z4SqrtPfmmf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R4 ; /* 0x0000001fff027819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*00b0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe20000000f00 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IADD3 R0, P0, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fc80007f1e1ff */
/*00e0*/ IADD3.X R5, R5, -0x1, RZ, P0, !PT ; /* 0xffffffff05057810 */
/* 0x000fca00007fe4ff */
/*00f0*/ IMAD R3, R5, c[0x0][0x170], RZ ; /* 0x00005c0005037a24 */
/* 0x000fe400078e02ff */
/*0100*/ IMAD.WIDE.U32 R6, R0, c[0x0][0x170], R6 ; /* 0x00005c0000067a25 */
/* 0x000fc800078e0006 */
/*0110*/ IMAD R3, R0, c[0x0][0x174], R3 ; /* 0x00005d0000037a24 */
/* 0x000fe200078e0203 */
/*0120*/ LEA R2, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006027a11 */
/* 0x000fc600078010ff */
/*0130*/ IMAD.IADD R3, R7, 0x1, R3 ; /* 0x0000000107037824 */
/* 0x000fca00078e0203 */
/*0140*/ LEA.HI.X R3, R6, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590006037a11 */
/* 0x000fca00000f1403 */
/*0150*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0160*/ BSSY B0, 0x250 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0170*/ FMUL R10, |R6|, c[0x0][0x178] ; /* 0x00005e00060a7a20 */
/* 0x004fc80000400200 */
/*0180*/ MUFU.RSQ R9, R10 ; /* 0x0000000a00097308 */
/* 0x0000620000001400 */
/*0190*/ IADD3 R6, R10, -0xd000000, RZ ; /* 0xf30000000a067810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ MOV R12, 0x1e0 ; /* 0x000001e0000c7802 */
/* 0x003fe40000000f00 */
/*01d0*/ CALL.REL.NOINC 0x2e0 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*01e0*/ MOV R7, R8 ; /* 0x0000000800077202 */
/* 0x000fe20000000f00 */
/*01f0*/ BRA 0x240 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0200*/ FMUL.FTZ R7, R10, R9 ; /* 0x000000090a077220 */
/* 0x003fe40000410000 */
/*0210*/ FMUL.FTZ R8, R9, 0.5 ; /* 0x3f00000009087820 */
/* 0x000fe40000410000 */
/*0220*/ FFMA R6, -R7, R7, R10 ; /* 0x0000000707067223 */
/* 0x000fc8000000010a */
/*0230*/ FFMA R7, R6, R8, R7 ; /* 0x0000000806077223 */
/* 0x000fe40000000007 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0260*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e6000c101904 */
/*0270*/ IMAD R6, R9, c[0x0][0xc], R4 ; /* 0x0000030009067a24 */
/* 0x000fca00078e0204 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f06070 */
/*0290*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*02a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x001fc80000011406 */
/*02b0*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x174], PT, P0 ; /* 0x00005d0007007a0c */
/* 0x000fda0003f06100 */
/*02c0*/ @!P0 BRA 0xf0 ; /* 0xfffffe2000008947 */
/* 0x000fea000383ffff */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*02f0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff078224 */
/* 0x000fe200078e000a */
/*0300*/ @!P0 BRA 0x420 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.GEU.FTZ.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fe40003f1e000 */
/*0320*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fd60000000f00 */
/*0330*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff078424 */
/* 0x000fe200078e00ff */
/*0340*/ @!P0 BRA 0x420 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fda0003f1c200 */
/*0360*/ @P0 FADD.FTZ R7, R6, 1 ; /* 0x3f80000006070421 */
/* 0x000fe20000010000 */
/*0370*/ @P0 BRA 0x420 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0380*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fda0003f1d200 */
/*0390*/ @P0 FFMA R8, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006080823 */
/* 0x000fc800000000ff */
/*03a0*/ @P0 MUFU.RSQ R7, R8 ; /* 0x0000000800070308 */
/* 0x000e240000001400 */
/*03b0*/ @P0 FMUL.FTZ R9, R8, R7 ; /* 0x0000000708090220 */
/* 0x001fe40000410000 */
/*03c0*/ @P0 FMUL.FTZ R11, R7, 0.5 ; /* 0x3f000000070b0820 */
/* 0x000fe20000410000 */
/*03d0*/ @!P0 MOV R7, R6 ; /* 0x0000000600078202 */
/* 0x000fe20000000f00 */
/*03e0*/ @P0 FADD.FTZ R10, -R9, -RZ ; /* 0x800000ff090a0221 */
/* 0x000fc80000010100 */
/*03f0*/ @P0 FFMA R10, R9, R10, R8 ; /* 0x0000000a090a0223 */
/* 0x000fc80000000008 */
/*0400*/ @P0 FFMA R10, R10, R11, R9 ; /* 0x0000000b0a0a0223 */
/* 0x000fc80000000009 */
/*0410*/ @P0 FMUL.FTZ R7, R10, 2.3283064365386962891e-10 ; /* 0x2f8000000a070820 */
/* 0x000fc80000410000 */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0007 */
/*0430*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0440*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x000fca0000000f00 */
/*0450*/ RET.REL.NODEC R6 0x0 ; /* 0xfffffba006007950 */
/* 0x000fea0003c3ffff */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Sqrt( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sqrt(abs(x[(idx-1)*N+i])*W0);
}
return;
} | .file "tmpxft_0014567e_00000000-6_Sqrt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4SqrtPfmmfPfmmf
.type _Z26__device_stub__Z4SqrtPfmmfPfmmf, @function
_Z26__device_stub__Z4SqrtPfmmfPfmmf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4SqrtPfmmf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z4SqrtPfmmfPfmmf, .-_Z26__device_stub__Z4SqrtPfmmfPfmmf
.globl _Z4SqrtPfmmf
.type _Z4SqrtPfmmf, @function
_Z4SqrtPfmmf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4SqrtPfmmfPfmmf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4SqrtPfmmf, .-_Z4SqrtPfmmf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4SqrtPfmmf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4SqrtPfmmf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Sqrt( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sqrt(abs(x[(idx-1)*N+i])*W0);
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Sqrt( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sqrt(abs(x[(idx-1)*N+i])*W0);
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Sqrt( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sqrt(abs(x[(idx-1)*N+i])*W0);
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4SqrtPfmmf
.globl _Z4SqrtPfmmf
.p2align 8
.type _Z4SqrtPfmmf,@function
_Z4SqrtPfmmf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s7, s[4:5], 0x0
s_load_b32 s1, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s10, -1
s_addc_u32 s4, s11, -1
s_mul_i32 s5, s0, s3
s_mul_hi_u32 s10, s0, s2
s_mul_i32 s11, s4, s2
s_add_i32 s5, s10, s5
s_mul_i32 s4, s0, s2
s_add_i32 s5, s5, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_add_i32 s15, s15, s7
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mul_i32 s6, s7, s6
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e64 v0, |v0|, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v1, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v2, -1, v1
v_add_nc_u32_e32 v4, 1, v1
v_fma_f32 v7, -v2, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v4, v1, v0
v_cmp_ge_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, v1, v2, s0
v_cmp_lt_f32_e64 s0, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, v1, v4, s0
v_ashrrev_i32_e32 v4, 31, v3
v_mul_f32_e32 v2, 0x37800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v7, v1, v2, vcc_lo
v_cmp_class_f32_e64 s0, v0, 0x260
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_nc_u32_e32 v3, s6, v3
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e64 v0, v7, v0, s0
s_or_b32 s7, vcc_lo, s7
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4SqrtPfmmf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4SqrtPfmmf, .Lfunc_end0-_Z4SqrtPfmmf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4SqrtPfmmf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4SqrtPfmmf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Sqrt( float * x, size_t idx, size_t N, float W0)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
x[(idx-1)*N+i] = sqrt(abs(x[(idx-1)*N+i])*W0);
}
return;
} | .text
.file "Sqrt.hip"
.globl _Z19__device_stub__SqrtPfmmf # -- Begin function _Z19__device_stub__SqrtPfmmf
.p2align 4, 0x90
.type _Z19__device_stub__SqrtPfmmf,@function
_Z19__device_stub__SqrtPfmmf: # @_Z19__device_stub__SqrtPfmmf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4SqrtPfmmf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__SqrtPfmmf, .Lfunc_end0-_Z19__device_stub__SqrtPfmmf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4SqrtPfmmf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4SqrtPfmmf,@object # @_Z4SqrtPfmmf
.section .rodata,"a",@progbits
.globl _Z4SqrtPfmmf
.p2align 3, 0x0
_Z4SqrtPfmmf:
.quad _Z19__device_stub__SqrtPfmmf
.size _Z4SqrtPfmmf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4SqrtPfmmf"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__SqrtPfmmf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4SqrtPfmmf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4SqrtPfmmf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R4 ; /* 0x0000001fff027819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*00b0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe20000000f00 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IADD3 R0, P0, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fc80007f1e1ff */
/*00e0*/ IADD3.X R5, R5, -0x1, RZ, P0, !PT ; /* 0xffffffff05057810 */
/* 0x000fca00007fe4ff */
/*00f0*/ IMAD R3, R5, c[0x0][0x170], RZ ; /* 0x00005c0005037a24 */
/* 0x000fe400078e02ff */
/*0100*/ IMAD.WIDE.U32 R6, R0, c[0x0][0x170], R6 ; /* 0x00005c0000067a25 */
/* 0x000fc800078e0006 */
/*0110*/ IMAD R3, R0, c[0x0][0x174], R3 ; /* 0x00005d0000037a24 */
/* 0x000fe200078e0203 */
/*0120*/ LEA R2, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006027a11 */
/* 0x000fc600078010ff */
/*0130*/ IMAD.IADD R3, R7, 0x1, R3 ; /* 0x0000000107037824 */
/* 0x000fca00078e0203 */
/*0140*/ LEA.HI.X R3, R6, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590006037a11 */
/* 0x000fca00000f1403 */
/*0150*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*0160*/ BSSY B0, 0x250 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0170*/ FMUL R10, |R6|, c[0x0][0x178] ; /* 0x00005e00060a7a20 */
/* 0x004fc80000400200 */
/*0180*/ MUFU.RSQ R9, R10 ; /* 0x0000000a00097308 */
/* 0x0000620000001400 */
/*0190*/ IADD3 R6, R10, -0xd000000, RZ ; /* 0xf30000000a067810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ MOV R12, 0x1e0 ; /* 0x000001e0000c7802 */
/* 0x003fe40000000f00 */
/*01d0*/ CALL.REL.NOINC 0x2e0 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*01e0*/ MOV R7, R8 ; /* 0x0000000800077202 */
/* 0x000fe20000000f00 */
/*01f0*/ BRA 0x240 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0200*/ FMUL.FTZ R7, R10, R9 ; /* 0x000000090a077220 */
/* 0x003fe40000410000 */
/*0210*/ FMUL.FTZ R8, R9, 0.5 ; /* 0x3f00000009087820 */
/* 0x000fe40000410000 */
/*0220*/ FFMA R6, -R7, R7, R10 ; /* 0x0000000707067223 */
/* 0x000fc8000000010a */
/*0230*/ FFMA R7, R6, R8, R7 ; /* 0x0000000806077223 */
/* 0x000fe40000000007 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0260*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e6000c101904 */
/*0270*/ IMAD R6, R9, c[0x0][0xc], R4 ; /* 0x0000030009067a24 */
/* 0x000fca00078e0204 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f06070 */
/*0290*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*02a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x001fc80000011406 */
/*02b0*/ ISETP.GE.U32.AND.EX P0, PT, R7, c[0x0][0x174], PT, P0 ; /* 0x00005d0007007a0c */
/* 0x000fda0003f06100 */
/*02c0*/ @!P0 BRA 0xf0 ; /* 0xfffffe2000008947 */
/* 0x000fea000383ffff */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*02f0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff078224 */
/* 0x000fe200078e000a */
/*0300*/ @!P0 BRA 0x420 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.GEU.FTZ.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fe40003f1e000 */
/*0320*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fd60000000f00 */
/*0330*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff078424 */
/* 0x000fe200078e00ff */
/*0340*/ @!P0 BRA 0x420 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fda0003f1c200 */
/*0360*/ @P0 FADD.FTZ R7, R6, 1 ; /* 0x3f80000006070421 */
/* 0x000fe20000010000 */
/*0370*/ @P0 BRA 0x420 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0380*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fda0003f1d200 */
/*0390*/ @P0 FFMA R8, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006080823 */
/* 0x000fc800000000ff */
/*03a0*/ @P0 MUFU.RSQ R7, R8 ; /* 0x0000000800070308 */
/* 0x000e240000001400 */
/*03b0*/ @P0 FMUL.FTZ R9, R8, R7 ; /* 0x0000000708090220 */
/* 0x001fe40000410000 */
/*03c0*/ @P0 FMUL.FTZ R11, R7, 0.5 ; /* 0x3f000000070b0820 */
/* 0x000fe20000410000 */
/*03d0*/ @!P0 MOV R7, R6 ; /* 0x0000000600078202 */
/* 0x000fe20000000f00 */
/*03e0*/ @P0 FADD.FTZ R10, -R9, -RZ ; /* 0x800000ff090a0221 */
/* 0x000fc80000010100 */
/*03f0*/ @P0 FFMA R10, R9, R10, R8 ; /* 0x0000000a090a0223 */
/* 0x000fc80000000008 */
/*0400*/ @P0 FFMA R10, R10, R11, R9 ; /* 0x0000000b0a0a0223 */
/* 0x000fc80000000009 */
/*0410*/ @P0 FMUL.FTZ R7, R10, 2.3283064365386962891e-10 ; /* 0x2f8000000a070820 */
/* 0x000fc80000410000 */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0007 */
/*0430*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0440*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x000fca0000000f00 */
/*0450*/ RET.REL.NODEC R6 0x0 ; /* 0xfffffba006007950 */
/* 0x000fea0003c3ffff */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4SqrtPfmmf
.globl _Z4SqrtPfmmf
.p2align 8
.type _Z4SqrtPfmmf,@function
_Z4SqrtPfmmf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s7, s[4:5], 0x0
s_load_b32 s1, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s10, -1
s_addc_u32 s4, s11, -1
s_mul_i32 s5, s0, s3
s_mul_hi_u32 s10, s0, s2
s_mul_i32 s11, s4, s2
s_add_i32 s5, s10, s5
s_mul_i32 s4, s0, s2
s_add_i32 s5, s5, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_add_i32 s15, s15, s7
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mul_i32 s6, s7, s6
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e64 v0, |v0|, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v1, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v2, -1, v1
v_add_nc_u32_e32 v4, 1, v1
v_fma_f32 v7, -v2, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v4, v1, v0
v_cmp_ge_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, v1, v2, s0
v_cmp_lt_f32_e64 s0, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, v1, v4, s0
v_ashrrev_i32_e32 v4, 31, v3
v_mul_f32_e32 v2, 0x37800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v7, v1, v2, vcc_lo
v_cmp_class_f32_e64 s0, v0, 0x260
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_nc_u32_e32 v3, s6, v3
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e64 v0, v7, v0, s0
s_or_b32 s7, vcc_lo, s7
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4SqrtPfmmf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4SqrtPfmmf, .Lfunc_end0-_Z4SqrtPfmmf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4SqrtPfmmf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4SqrtPfmmf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014567e_00000000-6_Sqrt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4SqrtPfmmfPfmmf
.type _Z26__device_stub__Z4SqrtPfmmfPfmmf, @function
_Z26__device_stub__Z4SqrtPfmmfPfmmf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4SqrtPfmmf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z4SqrtPfmmfPfmmf, .-_Z26__device_stub__Z4SqrtPfmmfPfmmf
.globl _Z4SqrtPfmmf
.type _Z4SqrtPfmmf, @function
_Z4SqrtPfmmf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4SqrtPfmmfPfmmf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4SqrtPfmmf, .-_Z4SqrtPfmmf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4SqrtPfmmf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4SqrtPfmmf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Sqrt.hip"
.globl _Z19__device_stub__SqrtPfmmf # -- Begin function _Z19__device_stub__SqrtPfmmf
.p2align 4, 0x90
.type _Z19__device_stub__SqrtPfmmf,@function
_Z19__device_stub__SqrtPfmmf: # @_Z19__device_stub__SqrtPfmmf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4SqrtPfmmf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__SqrtPfmmf, .Lfunc_end0-_Z19__device_stub__SqrtPfmmf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4SqrtPfmmf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4SqrtPfmmf,@object # @_Z4SqrtPfmmf
.section .rodata,"a",@progbits
.globl _Z4SqrtPfmmf
.p2align 3, 0x0
_Z4SqrtPfmmf:
.quad _Z19__device_stub__SqrtPfmmf
.size _Z4SqrtPfmmf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4SqrtPfmmf"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__SqrtPfmmf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4SqrtPfmmf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include "cuda_runtime.h"
__global__ void helloFromGPU(){
printf("Hello World");
}
__global__ void VecAdd(float *A,float *B,float *C){
int i=threadIdx.x+blockIdx.x*blockDim.x;
C[i]=A[i]+B[i];
}
int main(){
helloFromGPU<<<1,10>>>();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x8 ; /* 0x0000000800007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include "cuda_runtime.h"
__global__ void helloFromGPU(){
printf("Hello World");
}
__global__ void VecAdd(float *A,float *B,float *C){
int i=threadIdx.x+blockIdx.x*blockDim.x;
C[i]=A[i]+B[i];
}
int main(){
helloFromGPU<<<1,10>>>();
cudaDeviceReset();
return 0;
} | .file "tmpxft_0014eb41_00000000-6_test2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPfS_S_"
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include "cuda_runtime.h"
__global__ void helloFromGPU(){
printf("Hello World");
}
__global__ void VecAdd(float *A,float *B,float *C){
int i=threadIdx.x+blockIdx.x*blockDim.x;
C[i]=A[i]+B[i];
}
int main(){
helloFromGPU<<<1,10>>>();
cudaDeviceReset();
return 0;
} | #include<stdio.h>
#include "hip/hip_runtime.h"
__global__ void helloFromGPU(){
printf("Hello World");
}
__global__ void VecAdd(float *A,float *B,float *C){
int i=threadIdx.x+blockIdx.x*blockDim.x;
C[i]=A[i]+B[i];
}
int main(){
helloFromGPU<<<1,10>>>();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include "hip/hip_runtime.h"
__global__ void helloFromGPU(){
printf("Hello World");
}
__global__ void VecAdd(float *A,float *B,float *C){
int i=threadIdx.x+blockIdx.x*blockDim.x;
C[i]=A[i]+B[i];
}
int main(){
helloFromGPU<<<1,10>>>();
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12helloFromGPUv
.globl _Z12helloFromGPUv
.p2align 8
.type _Z12helloFromGPUv,@function
_Z12helloFromGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 12
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12helloFromGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12helloFromGPUv, .Lfunc_end0-_Z12helloFromGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 8
.type _Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6VecAddPfS_S_, .Lfunc_end1-_Z6VecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World"
.size .str, 12
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12helloFromGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12helloFromGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include "hip/hip_runtime.h"
__global__ void helloFromGPU(){
printf("Hello World");
}
__global__ void VecAdd(float *A,float *B,float *C){
int i=threadIdx.x+blockIdx.x*blockDim.x;
C[i]=A[i]+B[i];
}
int main(){
helloFromGPU<<<1,10>>>();
hipDeviceReset();
return 0;
} | .text
.file "test2.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end1-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014eb41_00000000-6_test2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6VecAddPfS_S_"
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test2.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end1-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // g++ -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -I../../../thrust/ -fopenmp -x c++ stocks_time.cu -o stocks_time-cpu && ./stocks_time-cpu < stocks.txt
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <chrono>
int main()
{
int N = 0;
thrust::host_vector<double> vec_cpu;
while (std::cin.fail() == false)
{
N += 1;
double price;
std::cin >> price;
vec_cpu.push_back(price);
}
std::cout << N << "\n";
// alocado na CPU
// aloca vetor na GPU e transfere dados CPU->GPU
std::chrono::time_point<std::chrono::system_clock> start, end, start_c, end_c;
start = std::chrono::system_clock::now();
thrust::device_vector<double>
vec_gpu(vec_cpu);
end = std::chrono::system_clock::now();
std::chrono::duration<double> elapsed_seconds = end - start;
std::cout << "elapsed time da alocação e cópia: " << elapsed_seconds.count() << "s\n";
//processa vec_gpu
// ver os tempos separados
// apenas alocação
//thrust::device_vector<double>
// vec_gpu(sizeof(vec_cpu));
//apenas cópia
// vec_gpu = ve= cpu;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // g++ -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -I../../../thrust/ -fopenmp -x c++ stocks_time.cu -o stocks_time-cpu && ./stocks_time-cpu < stocks.txt
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <chrono>
int main()
{
int N = 0;
thrust::host_vector<double> vec_cpu;
while (std::cin.fail() == false)
{
N += 1;
double price;
std::cin >> price;
vec_cpu.push_back(price);
}
std::cout << N << "\n";
// alocado na CPU
// aloca vetor na GPU e transfere dados CPU->GPU
std::chrono::time_point<std::chrono::system_clock> start, end, start_c, end_c;
start = std::chrono::system_clock::now();
thrust::device_vector<double>
vec_gpu(vec_cpu);
end = std::chrono::system_clock::now();
std::chrono::duration<double> elapsed_seconds = end - start;
std::cout << "elapsed time da alocação e cópia: " << elapsed_seconds.count() << "s\n";
//processa vec_gpu
// ver os tempos separados
// apenas alocação
//thrust::device_vector<double>
// vec_gpu(sizeof(vec_cpu));
//apenas cópia
// vec_gpu = ve= cpu;
} | // g++ -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -I../../../thrust/ -fopenmp -x c++ stocks_time.cu -o stocks_time-cpu && ./stocks_time-cpu < stocks.txt
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <chrono>
int main()
{
int N = 0;
thrust::host_vector<double> vec_cpu;
while (std::cin.fail() == false)
{
N += 1;
double price;
std::cin >> price;
vec_cpu.push_back(price);
}
std::cout << N << "\n";
// alocado na CPU
// aloca vetor na GPU e transfere dados CPU->GPU
std::chrono::time_point<std::chrono::system_clock> start, end, start_c, end_c;
start = std::chrono::system_clock::now();
thrust::device_vector<double>
vec_gpu(vec_cpu);
end = std::chrono::system_clock::now();
std::chrono::duration<double> elapsed_seconds = end - start;
std::cout << "elapsed time da alocação e cópia: " << elapsed_seconds.count() << "s\n";
//processa vec_gpu
// ver os tempos separados
// apenas alocação
//thrust::device_vector<double>
// vec_gpu(sizeof(vec_cpu));
//apenas cópia
// vec_gpu = ve= cpu;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // g++ -DTHRUST_DEVICE_SYSTEM=THRUST_DEVICE_SYSTEM_OMP -I../../../thrust/ -fopenmp -x c++ stocks_time.cu -o stocks_time-cpu && ./stocks_time-cpu < stocks.txt
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <chrono>
int main()
{
int N = 0;
thrust::host_vector<double> vec_cpu;
while (std::cin.fail() == false)
{
N += 1;
double price;
std::cin >> price;
vec_cpu.push_back(price);
}
std::cout << N << "\n";
// alocado na CPU
// aloca vetor na GPU e transfere dados CPU->GPU
std::chrono::time_point<std::chrono::system_clock> start, end, start_c, end_c;
start = std::chrono::system_clock::now();
thrust::device_vector<double>
vec_gpu(vec_cpu);
end = std::chrono::system_clock::now();
std::chrono::duration<double> elapsed_seconds = end - start;
std::cout << "elapsed time da alocação e cópia: " << elapsed_seconds.count() << "s\n";
//processa vec_gpu
// ver os tempos separados
// apenas alocação
//thrust::device_vector<double>
// vec_gpu(sizeof(vec_cpu));
//apenas cópia
// vec_gpu = ve= cpu;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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