system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dc463_00000000-6_CalcAngMom.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ibPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.type _Z58__device_stub__Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ibPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib, @function
_Z58__device_stub__Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ibPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib:
.LFB2051:
.cfi_startproc
endbr64
subq $344, %rsp
.cfi_def_cfa_offset 352
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 56(%rsp)
movsd %xmm1, 48(%rsp)
movq 352(%rsp), %rax
movq %rax, 72(%rsp)
movq 360(%rsp), %rax
movq %rax, 64(%rsp)
movq 368(%rsp), %rax
movq %rax, 40(%rsp)
movq 376(%rsp), %rax
movq %rax, 32(%rsp)
movq 384(%rsp), %rax
movq %rax, 24(%rsp)
movq 392(%rsp), %rax
movq %rax, 16(%rsp)
movq 400(%rsp), %rax
movq %rax, 8(%rsp)
movl 416(%rsp), %eax
movb %al, 4(%rsp)
movq %fs:40, %rax
movq %rax, 328(%rsp)
xorl %eax, %eax
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rax
movq %rax, 216(%rsp)
leaq 88(%rsp), %rax
movq %rax, 224(%rsp)
leaq 80(%rsp), %rax
movq %rax, 232(%rsp)
leaq 72(%rsp), %rax
movq %rax, 240(%rsp)
leaq 64(%rsp), %rax
movq %rax, 248(%rsp)
leaq 56(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rax
movq %rax, 264(%rsp)
leaq 40(%rsp), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rax
movq %rax, 280(%rsp)
leaq 24(%rsp), %rax
movq %rax, 288(%rsp)
leaq 16(%rsp), %rax
movq %rax, 296(%rsp)
leaq 8(%rsp), %rax
movq %rax, 304(%rsp)
leaq 408(%rsp), %rax
movq %rax, 312(%rsp)
leaq 4(%rsp), %rax
movq %rax, 320(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
leaq 136(%rsp), %rcx
leaq 128(%rsp), %rdx
leaq 156(%rsp), %rsi
leaq 144(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 328(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $344, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 136(%rsp)
.cfi_def_cfa_offset 360
pushq 136(%rsp)
.cfi_def_cfa_offset 368
leaq 208(%rsp), %r9
movq 172(%rsp), %rcx
movl 180(%rsp), %r8d
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
leaq _Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 352
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ibPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib, .-_Z58__device_stub__Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ibPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.globl _Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.type _Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib, @function
_Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movzbl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 88(%rsp)
.cfi_def_cfa_offset 48
pushq 88(%rsp)
.cfi_def_cfa_offset 56
pushq 88(%rsp)
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z58__device_stub__Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ibPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib, .-_Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CalcAngMom.hip"
.globl _Z25__device_stub__CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib # -- Begin function _Z25__device_stub__CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.p2align 4, 0x90
.type _Z25__device_stub__CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib,@function
_Z25__device_stub__CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib: # @_Z25__device_stub__CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movzbl 336(%rsp), %eax
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movb %al, 15(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 272(%rsp), %rax
movq %rax, 176(%rsp)
leaq 280(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
leaq 312(%rsp), %rax
movq %rax, 232(%rsp)
leaq 320(%rsp), %rax
movq %rax, 240(%rsp)
leaq 328(%rsp), %rax
movq %rax, 248(%rsp)
leaq 15(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z25__device_stub__CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib, .Lfunc_end0-_Z25__device_stub__CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib,@object # @_Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.section .rodata,"a",@progbits
.globl _Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.p2align 3, 0x0
_Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib:
.quad _Z25__device_stub__CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.size _Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10CalcAngMomPdS_S_S_S_S_S_S_ddS_S_S_S_S_ib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //nvcc -ptx EM3.cu -ccbin "F:Visual Studio\VC\Tools\MSVC\14.12.25827\bin\Hostx64\x64"
__device__ void EM1( double * Er0,
double * Ez0,
double * Hphi0,
double * Er,
double * Ez,
double * jr,
double * jz,
const double mu,
const double epsilon,
const double dr,
const double dz,
const double dt ) {
int nz = blockIdx.x + blockIdx.y * gridDim.x;
int nr = threadIdx.x + blockDim.x * threadIdx.y;
int threadsPerBlock = blockDim.x*blockDim.y;
int BlocksPerGrid = gridDim.x*gridDim.y;
int n_r = nr + nz*(threadsPerBlock-1);
int n_z = nr + nz*threadsPerBlock;
if( nr < threadsPerBlock-1 ){
if( nz < 1){
Er[n_r] = Er0[n_r + (threadsPerBlock-1)];
}
else{
if( nz >= BlocksPerGrid-1 ){
Er[n_r] = Er0[n_r - (threadsPerBlock-1)];
}
else{
Er[n_r] = Er0[n_r] - dt/epsilon*(jr[n_r-(threadsPerBlock-1)]+jr[n_r])/2 - dt/(epsilon*dz)*( Hphi0[n_r]-Hphi0[n_r - (threadsPerBlock-1)] );
}
}
}
if( nz < BlocksPerGrid-1 ){
if( nr < 1 ){
Ez[n_z] = Ez0[n_z] + dt/epsilon*jz[n_r] + 4*dt/(epsilon*dr)*Hphi0[n_r];
}
else{
if( nr < threadsPerBlock-1 ){
Ez[n_z] = Ez0[n_z] - dt/epsilon*(jz[n_r-1]+jz[n_r])/2 + dt/epsilon*(1/(2*(nr+1)*dr)+1/dr)*Hphi0[n_r] + dt/epsilon*(1/(2*(nr+1)*dr)-1/dr)*Hphi0[n_r-1] ;
}
}
}
}
__global__ void processMandelbrotElement(
double * Er0,
double * Ez0,
double * Hphi0,
double * Er,
double * Ez,
double * jr,
double * jz,
const double mu,
const double epsilon,
const double dr,
const double dz,
const double dt ) {
EM1(Er0,Ez0,Hphi0,Er,Ez,jr,jz,mu,epsilon,dr,dz,dt);
} | .file "tmpxft_0006fbe8_00000000-6_EM3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3EM1PdS_S_S_S_S_S_ddddd
.type _Z3EM1PdS_S_S_S_S_S_ddddd, @function
_Z3EM1PdS_S_S_S_S_S_ddddd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z3EM1PdS_S_S_S_S_S_ddddd, .-_Z3EM1PdS_S_S_S_S_S_ddddd
.globl _Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd
.type _Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd, @function
_Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd:
.LFB2052:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movsd %xmm2, 16(%rsp)
movsd %xmm3, 8(%rsp)
movsd %xmm4, (%rsp)
movq 288(%rsp), %rax
movq %rax, 40(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 8(%rsp), %rax
movq %rax, 240(%rsp)
movq %rsp, %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd, .-_Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd
.globl _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.type _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd, @function
_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd, .-_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //nvcc -ptx EM3.cu -ccbin "F:Visual Studio\VC\Tools\MSVC\14.12.25827\bin\Hostx64\x64"
__device__ void EM1( double * Er0,
double * Ez0,
double * Hphi0,
double * Er,
double * Ez,
double * jr,
double * jz,
const double mu,
const double epsilon,
const double dr,
const double dz,
const double dt ) {
int nz = blockIdx.x + blockIdx.y * gridDim.x;
int nr = threadIdx.x + blockDim.x * threadIdx.y;
int threadsPerBlock = blockDim.x*blockDim.y;
int BlocksPerGrid = gridDim.x*gridDim.y;
int n_r = nr + nz*(threadsPerBlock-1);
int n_z = nr + nz*threadsPerBlock;
if( nr < threadsPerBlock-1 ){
if( nz < 1){
Er[n_r] = Er0[n_r + (threadsPerBlock-1)];
}
else{
if( nz >= BlocksPerGrid-1 ){
Er[n_r] = Er0[n_r - (threadsPerBlock-1)];
}
else{
Er[n_r] = Er0[n_r] - dt/epsilon*(jr[n_r-(threadsPerBlock-1)]+jr[n_r])/2 - dt/(epsilon*dz)*( Hphi0[n_r]-Hphi0[n_r - (threadsPerBlock-1)] );
}
}
}
if( nz < BlocksPerGrid-1 ){
if( nr < 1 ){
Ez[n_z] = Ez0[n_z] + dt/epsilon*jz[n_r] + 4*dt/(epsilon*dr)*Hphi0[n_r];
}
else{
if( nr < threadsPerBlock-1 ){
Ez[n_z] = Ez0[n_z] - dt/epsilon*(jz[n_r-1]+jz[n_r])/2 + dt/epsilon*(1/(2*(nr+1)*dr)+1/dr)*Hphi0[n_r] + dt/epsilon*(1/(2*(nr+1)*dr)-1/dr)*Hphi0[n_r-1] ;
}
}
}
}
__global__ void processMandelbrotElement(
double * Er0,
double * Ez0,
double * Hphi0,
double * Er,
double * Ez,
double * jr,
double * jz,
const double mu,
const double epsilon,
const double dr,
const double dz,
const double dt ) {
EM1(Er0,Ez0,Hphi0,Er,Ez,jr,jz,mu,epsilon,dr,dz,dt);
} | #include <hip/hip_runtime.h>
//nvcc -ptx EM3.cu -ccbin "F:Visual Studio\VC\Tools\MSVC\14.12.25827\bin\Hostx64\x64"
__device__ void EM1( double * Er0,
double * Ez0,
double * Hphi0,
double * Er,
double * Ez,
double * jr,
double * jz,
const double mu,
const double epsilon,
const double dr,
const double dz,
const double dt ) {
int nz = blockIdx.x + blockIdx.y * gridDim.x;
int nr = threadIdx.x + blockDim.x * threadIdx.y;
int threadsPerBlock = blockDim.x*blockDim.y;
int BlocksPerGrid = gridDim.x*gridDim.y;
int n_r = nr + nz*(threadsPerBlock-1);
int n_z = nr + nz*threadsPerBlock;
if( nr < threadsPerBlock-1 ){
if( nz < 1){
Er[n_r] = Er0[n_r + (threadsPerBlock-1)];
}
else{
if( nz >= BlocksPerGrid-1 ){
Er[n_r] = Er0[n_r - (threadsPerBlock-1)];
}
else{
Er[n_r] = Er0[n_r] - dt/epsilon*(jr[n_r-(threadsPerBlock-1)]+jr[n_r])/2 - dt/(epsilon*dz)*( Hphi0[n_r]-Hphi0[n_r - (threadsPerBlock-1)] );
}
}
}
if( nz < BlocksPerGrid-1 ){
if( nr < 1 ){
Ez[n_z] = Ez0[n_z] + dt/epsilon*jz[n_r] + 4*dt/(epsilon*dr)*Hphi0[n_r];
}
else{
if( nr < threadsPerBlock-1 ){
Ez[n_z] = Ez0[n_z] - dt/epsilon*(jz[n_r-1]+jz[n_r])/2 + dt/epsilon*(1/(2*(nr+1)*dr)+1/dr)*Hphi0[n_r] + dt/epsilon*(1/(2*(nr+1)*dr)-1/dr)*Hphi0[n_r-1] ;
}
}
}
}
__global__ void processMandelbrotElement(
double * Er0,
double * Ez0,
double * Hphi0,
double * Er,
double * Ez,
double * jr,
double * jz,
const double mu,
const double epsilon,
const double dr,
const double dz,
const double dt ) {
EM1(Er0,Ez0,Hphi0,Er,Ez,jr,jz,mu,epsilon,dr,dz,dt);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//nvcc -ptx EM3.cu -ccbin "F:Visual Studio\VC\Tools\MSVC\14.12.25827\bin\Hostx64\x64"
__device__ void EM1( double * Er0,
double * Ez0,
double * Hphi0,
double * Er,
double * Ez,
double * jr,
double * jz,
const double mu,
const double epsilon,
const double dr,
const double dz,
const double dt ) {
int nz = blockIdx.x + blockIdx.y * gridDim.x;
int nr = threadIdx.x + blockDim.x * threadIdx.y;
int threadsPerBlock = blockDim.x*blockDim.y;
int BlocksPerGrid = gridDim.x*gridDim.y;
int n_r = nr + nz*(threadsPerBlock-1);
int n_z = nr + nz*threadsPerBlock;
if( nr < threadsPerBlock-1 ){
if( nz < 1){
Er[n_r] = Er0[n_r + (threadsPerBlock-1)];
}
else{
if( nz >= BlocksPerGrid-1 ){
Er[n_r] = Er0[n_r - (threadsPerBlock-1)];
}
else{
Er[n_r] = Er0[n_r] - dt/epsilon*(jr[n_r-(threadsPerBlock-1)]+jr[n_r])/2 - dt/(epsilon*dz)*( Hphi0[n_r]-Hphi0[n_r - (threadsPerBlock-1)] );
}
}
}
if( nz < BlocksPerGrid-1 ){
if( nr < 1 ){
Ez[n_z] = Ez0[n_z] + dt/epsilon*jz[n_r] + 4*dt/(epsilon*dr)*Hphi0[n_r];
}
else{
if( nr < threadsPerBlock-1 ){
Ez[n_z] = Ez0[n_z] - dt/epsilon*(jz[n_r-1]+jz[n_r])/2 + dt/epsilon*(1/(2*(nr+1)*dr)+1/dr)*Hphi0[n_r] + dt/epsilon*(1/(2*(nr+1)*dr)-1/dr)*Hphi0[n_r-1] ;
}
}
}
}
__global__ void processMandelbrotElement(
double * Er0,
double * Ez0,
double * Hphi0,
double * Er,
double * Ez,
double * jr,
double * jz,
const double mu,
const double epsilon,
const double dr,
const double dz,
const double dt ) {
EM1(Er0,Ez0,Hphi0,Er,Ez,jr,jz,mu,epsilon,dr,dz,dt);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.globl _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.p2align 8
.type _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd,@function
_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd:
s_load_b128 s[4:7], s[0:1], 0x58
s_add_u32 s2, s0, 0x60
s_addc_u32 s3, s1, 0
s_load_b32 s8, s[0:1], 0x6c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s16, s6, s15
s_mul_i32 s12, s7, s6
s_add_i32 s16, s16, s14
s_cmp_lt_u32 s14, s6
s_cselect_b32 s9, 12, 18
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s9
global_load_u16 v1, v1, s[2:3]
s_lshr_b32 s2, s8, 16
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x40
s_mov_b32 s3, -1
s_waitcnt vmcnt(0)
v_mul_lo_u32 v7, s2, v1
v_mad_u32_u24 v4, v0, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, -1, v7
v_mad_u64_u32 v[0:1], null, v8, s16, v[4:5]
v_cmp_lt_i32_e64 s2, v4, v8
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s13, s2
s_cbranch_execz .LBB0_10
s_load_b64 s[6:7], s[0:1], 0x0
s_cmp_gt_i32 s16, 0
s_cbranch_scc0 .LBB0_4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_sub_nc_u32_e32 v2, v0, v8
s_add_i32 s3, s12, -1
s_cmp_lt_i32 s16, s3
s_mov_b32 s3, -1
s_cbranch_scc1 .LBB0_5
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_cbranch_execz .LBB0_6
s_branch .LBB0_7
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_8
s_branch .LBB0_9
.LBB0_5:
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_7
.LBB0_6:
s_clause 0x1
s_load_b64 s[14:15], s[0:1], 0x28
s_load_b64 s[18:19], s[0:1], 0x50
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f64 v[5:6], null, s[8:9], s[8:9], s[4:5]
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[9:10], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s14, v2
v_add_co_ci_u32_e32 v12, vcc_lo, s15, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s14, v9
v_add_co_ci_u32_e32 v14, vcc_lo, s15, v10, vcc_lo
v_mul_f64 v[15:16], s[8:9], s[18:19]
s_clause 0x1
global_load_b64 v[11:12], v[11:12], off
global_load_b64 v[13:14], v[13:14], off
v_add_co_u32 v23, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v24, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
v_add_co_u32 v2, vcc_lo, s10, v2
v_rcp_f64_e32 v[17:18], v[5:6]
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
global_load_b64 v[23:24], v[23:24], off
s_clause 0x1
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[2:3], v[2:3], off
v_div_scale_f64 v[19:20], null, v[15:16], v[15:16], s[4:5]
v_div_scale_f64 v[31:32], s3, s[4:5], v[15:16], s[4:5]
v_fma_f64 v[21:22], -v[5:6], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[25:26], v[19:20]
v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
s_waitcnt_depctr 0xfff
v_fma_f64 v[21:22], -v[19:20], v[25:26], 1.0
v_fma_f64 v[27:28], -v[5:6], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[21:22], v[25:26], v[21:22], v[25:26]
v_div_scale_f64 v[25:26], vcc_lo, s[4:5], s[8:9], s[4:5]
v_fma_f64 v[17:18], v[17:18], v[27:28], v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[27:28], -v[19:20], v[21:22], 1.0
v_mul_f64 v[29:30], v[25:26], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[21:22], v[21:22], v[27:28], v[21:22]
v_fma_f64 v[5:6], -v[5:6], v[29:30], v[25:26]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[25:26], v[31:32], v[21:22]
v_div_fmas_f64 v[5:6], v[5:6], v[17:18], v[29:30]
s_mov_b32 vcc_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[17:18], -v[19:20], v[25:26], v[31:32]
v_div_fixup_f64 v[5:6], v[5:6], s[8:9], s[4:5]
s_waitcnt vmcnt(3)
v_add_f64 v[11:12], v[11:12], v[13:14]
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[9:10], -v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[13:14], v[17:18], v[21:22], v[25:26]
v_mul_f64 v[5:6], v[5:6], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[11:12], v[13:14], v[15:16], s[4:5]
v_fma_f64 v[5:6], v[5:6], -0.5, v[23:24]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[5:6], -v[11:12], v[2:3], v[5:6]
.LBB0_7:
s_cbranch_execnz .LBB0_9
.LBB0_8:
v_add_nc_u32_e32 v1, v0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b64 v[5:6], v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
.LBB0_9:
s_waitcnt lgkmcnt(0)
s_load_b64 s[6:7], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[1:2], v[5:6], off
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s13
s_add_i32 s12, s12, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s16, s12
s_cbranch_scc1 .LBB0_19
s_clause 0x2
s_load_b64 s[12:13], s[0:1], 0x8
s_load_b64 s[6:7], s[0:1], 0x30
s_load_b64 s[14:15], s[0:1], 0x48
v_mad_u64_u32 v[2:3], null, v7, s16, v[4:5]
s_mov_b32 s3, 0
s_mov_b32 s16, exec_lo
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s16, exec_lo, s16
s_cbranch_execz .LBB0_15
s_mov_b32 s17, 0
s_and_saveexec_b32 s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s18, exec_lo, s3
s_cbranch_execz .LBB0_14
v_lshl_add_u32 v1, v4, 1, 2
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[6:7], null, s[8:9], s[8:9], s[4:5]
v_div_scale_f64 v[10:11], null, s[14:15], s[14:15], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[3:4], v1
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s17, exec_lo
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v30, vcc_lo, v0, -8
v_add_co_ci_u32_e32 v31, vcc_lo, -1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s6, v30
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v31, vcc_lo
v_add_co_u32 v14, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v1, vcc_lo
s_clause 0x1
global_load_b64 v[12:13], v[12:13], off
global_load_b64 v[14:15], v[14:15], off
v_rcp_f64_e32 v[16:17], v[6:7]
v_rcp_f64_e32 v[20:21], v[10:11]
v_mul_f64 v[4:5], v[3:4], s[14:15]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[28:29], 3, v[2:3]
v_add_co_u32 v28, vcc_lo, s12, v28
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v29, vcc_lo, s13, v29, vcc_lo
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
global_load_b64 v[28:29], v[28:29], off
v_fma_f64 v[22:23], -v[6:7], v[16:17], 1.0
v_fma_f64 v[26:27], -v[10:11], v[20:21], 1.0
v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
v_add_co_u32 v22, vcc_lo, s10, v30
v_rcp_f64_e32 v[18:19], v[8:9]
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[20:21], v[20:21], v[26:27], v[20:21]
v_add_co_ci_u32_e32 v23, vcc_lo, s11, v31, vcc_lo
s_clause 0x1
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[22:23], v[22:23], off
v_div_scale_f64 v[32:33], vcc_lo, s[4:5], s[8:9], s[4:5]
v_fma_f64 v[30:31], -v[10:11], v[20:21], 1.0
v_fma_f64 v[24:25], -v[8:9], v[18:19], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], v[20:21], v[30:31], v[20:21]
v_fma_f64 v[18:19], v[18:19], v[24:25], v[18:19]
v_fma_f64 v[24:25], -v[6:7], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[26:27], -v[8:9], v[18:19], 1.0
v_fma_f64 v[16:17], v[16:17], v[24:25], v[16:17]
v_div_scale_f64 v[24:25], s2, 1.0, v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f64 v[18:19], v[18:19], v[26:27], v[18:19]
v_div_scale_f64 v[26:27], s3, 1.0, s[14:15], 1.0
v_mul_f64 v[30:31], v[32:33], v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[34:35], v[24:25], v[18:19]
v_mul_f64 v[36:37], v[26:27], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], -v[6:7], v[30:31], v[32:33]
v_fma_f64 v[8:9], -v[8:9], v[34:35], v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f64 v[10:11], -v[10:11], v[36:37], v[26:27]
s_waitcnt vmcnt(3)
v_add_f64 v[12:13], v[12:13], v[14:15]
v_div_fmas_f64 v[6:7], v[6:7], v[16:17], v[30:31]
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[8:9], v[8:9], v[18:19], v[34:35]
s_mov_b32 vcc_lo, s3
v_div_fmas_f64 v[10:11], v[10:11], v[20:21], v[36:37]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[6:7], v[6:7], s[8:9], s[4:5]
v_div_fixup_f64 v[4:5], v[8:9], v[4:5], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[8:9], v[10:11], s[14:15], 1.0
v_mul_f64 v[10:11], v[6:7], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[8:9], v[4:5]
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_waitcnt vmcnt(2)
v_fma_f64 v[8:9], v[10:11], -0.5, v[28:29]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[10:11], v[6:7], v[12:13]
v_mul_f64 v[4:5], v[6:7], v[4:5]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], v[10:11], v[0:1], v[8:9]
s_waitcnt vmcnt(0)
v_mul_f64 v[5:6], v[4:5], v[22:23]
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s3, s17, exec_lo
.LBB0_15:
s_and_not1_saveexec_b32 s16, s16
s_cbranch_execz .LBB0_17
v_mul_f64 v[4:5], s[4:5], 4.0
s_waitcnt lgkmcnt(0)
v_mul_f64 v[6:7], s[8:9], s[14:15]
v_div_scale_f64 v[8:9], null, s[8:9], s[8:9], s[4:5]
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_or_b32 s3, s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[16:17], 3, v[2:3]
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v16, vcc_lo, s12, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v18, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v19, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
global_load_b64 v[16:17], v[16:17], off
global_load_b64 v[18:19], v[18:19], off
global_load_b64 v[0:1], v[0:1], off
v_div_scale_f64 v[24:25], vcc_lo, s[4:5], s[8:9], s[4:5]
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[4:5]
v_rcp_f64_e32 v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[14:15], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[8:9], v[12:13], 1.0
v_fma_f64 v[22:23], -v[10:11], v[14:15], 1.0
v_fma_f64 v[12:13], v[12:13], v[20:21], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[14:15], v[22:23], v[14:15]
v_fma_f64 v[20:21], -v[8:9], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[22:23], -v[10:11], v[14:15], 1.0
v_fma_f64 v[12:13], v[12:13], v[20:21], v[12:13]
v_div_scale_f64 v[20:21], s2, v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[14:15], v[22:23], v[14:15]
v_mul_f64 v[22:23], v[24:25], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[26:27], v[20:21], v[14:15]
v_fma_f64 v[8:9], -v[8:9], v[22:23], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[26:27], v[20:21]
v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[22:23]
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[26:27]
v_div_fixup_f64 v[8:9], v[8:9], s[8:9], s[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[10:11], v[10:11], v[6:7], v[4:5]
s_waitcnt vmcnt(1)
v_fma_f64 v[5:6], v[8:9], v[18:19], v[16:17]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[7:8], v[10:11], v[0:1]
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[5:6], v[7:8]
s_load_b64 s[0:1], s[0:1], 0x20
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 352
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 38
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd, .Lfunc_end0-_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 8
.value_kind: by_value
- .offset: 72
.size: 8
.value_kind: by_value
- .offset: 80
.size: 8
.value_kind: by_value
- .offset: 88
.size: 8
.value_kind: by_value
- .offset: 96
.size: 4
.value_kind: hidden_block_count_x
- .offset: 100
.size: 4
.value_kind: hidden_block_count_y
- .offset: 104
.size: 4
.value_kind: hidden_block_count_z
- .offset: 108
.size: 2
.value_kind: hidden_group_size_x
- .offset: 110
.size: 2
.value_kind: hidden_group_size_y
- .offset: 112
.size: 2
.value_kind: hidden_group_size_z
- .offset: 114
.size: 2
.value_kind: hidden_remainder_x
- .offset: 116
.size: 2
.value_kind: hidden_remainder_y
- .offset: 118
.size: 2
.value_kind: hidden_remainder_z
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 160
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 352
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 38
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//nvcc -ptx EM3.cu -ccbin "F:Visual Studio\VC\Tools\MSVC\14.12.25827\bin\Hostx64\x64"
__device__ void EM1( double * Er0,
double * Ez0,
double * Hphi0,
double * Er,
double * Ez,
double * jr,
double * jz,
const double mu,
const double epsilon,
const double dr,
const double dz,
const double dt ) {
int nz = blockIdx.x + blockIdx.y * gridDim.x;
int nr = threadIdx.x + blockDim.x * threadIdx.y;
int threadsPerBlock = blockDim.x*blockDim.y;
int BlocksPerGrid = gridDim.x*gridDim.y;
int n_r = nr + nz*(threadsPerBlock-1);
int n_z = nr + nz*threadsPerBlock;
if( nr < threadsPerBlock-1 ){
if( nz < 1){
Er[n_r] = Er0[n_r + (threadsPerBlock-1)];
}
else{
if( nz >= BlocksPerGrid-1 ){
Er[n_r] = Er0[n_r - (threadsPerBlock-1)];
}
else{
Er[n_r] = Er0[n_r] - dt/epsilon*(jr[n_r-(threadsPerBlock-1)]+jr[n_r])/2 - dt/(epsilon*dz)*( Hphi0[n_r]-Hphi0[n_r - (threadsPerBlock-1)] );
}
}
}
if( nz < BlocksPerGrid-1 ){
if( nr < 1 ){
Ez[n_z] = Ez0[n_z] + dt/epsilon*jz[n_r] + 4*dt/(epsilon*dr)*Hphi0[n_r];
}
else{
if( nr < threadsPerBlock-1 ){
Ez[n_z] = Ez0[n_z] - dt/epsilon*(jz[n_r-1]+jz[n_r])/2 + dt/epsilon*(1/(2*(nr+1)*dr)+1/dr)*Hphi0[n_r] + dt/epsilon*(1/(2*(nr+1)*dr)-1/dr)*Hphi0[n_r-1] ;
}
}
}
}
__global__ void processMandelbrotElement(
double * Er0,
double * Ez0,
double * Hphi0,
double * Er,
double * Ez,
double * jr,
double * jz,
const double mu,
const double epsilon,
const double dr,
const double dz,
const double dt ) {
EM1(Er0,Ez0,Hphi0,Er,Ez,jr,jz,mu,epsilon,dr,dz,dt);
} | .text
.file "EM3.hip"
.globl _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd # -- Begin function _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd
.p2align 4, 0x90
.type _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd,@function
_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd: # @_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 136(%rsp)
movq %rsi, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rcx, 112(%rsp)
movq %r8, 104(%rsp)
movq %r9, 96(%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movsd %xmm2, 72(%rsp)
movsd %xmm3, 64(%rsp)
movsd %xmm4, 56(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 88(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
leaq 72(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd, .Lfunc_end0-_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd,@object # @_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.section .rodata,"a",@progbits
.globl _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.p2align 3, 0x0
_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd:
.quad _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd
.size _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006fbe8_00000000-6_EM3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3EM1PdS_S_S_S_S_S_ddddd
.type _Z3EM1PdS_S_S_S_S_S_ddddd, @function
_Z3EM1PdS_S_S_S_S_S_ddddd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z3EM1PdS_S_S_S_S_S_ddddd, .-_Z3EM1PdS_S_S_S_S_S_ddddd
.globl _Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd
.type _Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd, @function
_Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd:
.LFB2052:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movsd %xmm2, 16(%rsp)
movsd %xmm3, 8(%rsp)
movsd %xmm4, (%rsp)
movq 288(%rsp), %rax
movq %rax, 40(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 48(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rax
movq %rax, 216(%rsp)
leaq 24(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 8(%rsp), %rax
movq %rax, 240(%rsp)
movq %rsp, %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd, .-_Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd
.globl _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.type _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd, @function
_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd:
.LFB2053:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z61__device_stub__Z24processMandelbrotElementPdS_S_S_S_S_S_dddddPdS_S_S_S_S_S_ddddd
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd, .-_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "EM3.hip"
.globl _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd # -- Begin function _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd
.p2align 4, 0x90
.type _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd,@function
_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd: # @_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 136(%rsp)
movq %rsi, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rcx, 112(%rsp)
movq %r8, 104(%rsp)
movq %r9, 96(%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movsd %xmm2, 72(%rsp)
movsd %xmm3, 64(%rsp)
movsd %xmm4, 56(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 88(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
leaq 72(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd, .Lfunc_end0-_Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd,@object # @_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.section .rodata,"a",@progbits
.globl _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.p2align 3, 0x0
_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd:
.quad _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd
.size _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__processMandelbrotElementPdS_S_S_S_S_S_ddddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24processMandelbrotElementPdS_S_S_S_S_S_ddddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void integrateBins(int width, int height, int nbins, int* devImage, int binPitch, int* devIntegrals) {
__shared__ int pixels[16];
const int blockX = blockDim.y * blockIdx.x;
const int threadX = threadIdx.y;
const int bin = threadIdx.x;
const int x = blockX + threadX;
if (x >= width) return;
if (bin > nbins) return;
int* imagePointer = devImage + x;
int* outputPointer = devIntegrals + binPitch * x + bin;
int accumulant = 0;
for(int y = 0; y < height; y++) {
if (bin == 0) {
pixels[threadX] = *imagePointer;
}
__syncthreads();
if (pixels[threadX] == bin) accumulant++;
*outputPointer = accumulant;
imagePointer += width;
outputPointer += width * binPitch;
}
} | code for sm_80
Function : _Z13integrateBinsiiiPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R6, R5, c[0x0][0x4], R2 ; /* 0x0000010005067a24 */
/* 0x001fe200078e0202 */
/*0050*/ ISETP.GT.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x002fc80003f04270 */
/*0060*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x160], P0 ; /* 0x0000580006007a0c */
/* 0x000fda0000706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff047624 */
/* 0x000fe200078e00ff */
/*0090*/ SHF.R.S32.HI R5, RZ, 0x1f, R3 ; /* 0x0000001fff057819 */
/* 0x000fe20000011403 */
/*00a0*/ IMAD R0, R6, c[0x0][0x178], RZ ; /* 0x00005e0006007a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f06270 */
/*00d0*/ IADD3 R17, P1, R0, R3, RZ ; /* 0x0000000300117210 */
/* 0x000fe20007f3e0ff */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc600078e0207 */
/*00f0*/ LEA.HI.X.SX32 R0, R0, R5, 0x1, P1 ; /* 0x0000000500007211 */
/* 0x000fe400008f0eff */
/*0100*/ LEA R16, P1, R17, c[0x0][0x180], 0x2 ; /* 0x0000600011107a11 */
/* 0x000fc800078210ff */
/*0110*/ LEA.HI.X R17, R17, c[0x0][0x184], R0, 0x2, P1 ; /* 0x0000610011117a11 */
/* 0x000fe200008f1400 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000ff00003800000 */
/*0130*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fe200078e00ff */
/*0150*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0007 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f06070 */
/*0180*/ IMAD R5, R0, c[0x0][0x178], RZ ; /* 0x00005e0000057a24 */
/* 0x000fe200078e02ff */
/*0190*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe200078ec0ff */
/*01a0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*01b0*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe40000011400 */
/*01c0*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fce0000011405 */
/*01d0*/ @!P0 BRA 0x680 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0010 */
/*01f0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*0200*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0011 */
/*0210*/ SHF.L.U64.HI R10, R0.reuse, 0x4, R9.reuse ; /* 0x00000004000a7819 */
/* 0x140fe20000010209 */
/*0220*/ IMAD.SHL.U32 R19, R0.reuse, 0x10, RZ ; /* 0x0000001000137824 */
/* 0x040fe200078e00ff */
/*0230*/ SHF.L.U64.HI R12, R0.reuse, 0x3, R9.reuse ; /* 0x00000003000c7819 */
/* 0x140fe20000010209 */
/*0240*/ IMAD.SHL.U32 R21, R0.reuse, 0x8, RZ ; /* 0x0000000800157824 */
/* 0x040fe200078e00ff */
/*0250*/ SHF.L.U64.HI R18, R0.reuse, 0x2, R9 ; /* 0x0000000200127819 */
/* 0x040fe20000010209 */
/*0260*/ IMAD.SHL.U32 R23, R0, 0x4, RZ ; /* 0x0000000400177824 */
/* 0x000fe200078e00ff */
/*0270*/ IADD3 R4, -R7, c[0x0][0x164], RZ ; /* 0x0000590007047a10 */
/* 0x000fe20007ffe1ff */
/*0280*/ IMAD.SHL.U32 R25, R5.reuse, 0x4, RZ ; /* 0x0000000405197824 */
/* 0x040fe200078e00ff */
/*0290*/ SHF.L.U64.HI R22, R5.reuse, 0x4, R8.reuse ; /* 0x0000000405167819 */
/* 0x140fe20000010208 */
/*02a0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*02b0*/ SHF.L.U64.HI R24, R5, 0x2, R8 ; /* 0x0000000205187819 */
/* 0x000fc40000010208 */
/*02c0*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0006 */
/*02d0*/ IMAD.MOV.U32 R17, RZ, RZ, R13 ; /* 0x000000ffff117224 */
/* 0x000fca00078e000d */
/*02e0*/ @!P0 LDG.E R15, [R16.64] ; /* 0x00000004100f8981 */
/* 0x001ea2000c1e1900 */
/*02f0*/ IADD3 R14, R29, 0x1, RZ ; /* 0x000000011d0e7810 */
/* 0x000fe20007ffe0ff */
/*0300*/ IMAD.MOV.U32 R28, RZ, RZ, R20 ; /* 0x000000ffff1c7224 */
/* 0x000fe400078e0014 */
/*0310*/ @!P0 STS [R2.X4], R15 ; /* 0x0000000f02008388 */
/* 0x004fe80000004800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0330*/ LDS R0, [R2.X4] ; /* 0x0000000002007984 */
/* 0x000e240000004800 */
/*0340*/ ISETP.NE.AND P1, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x001fda0003f25270 */
/*0350*/ @P1 IMAD.MOV R14, RZ, RZ, R29 ; /* 0x000000ffff0e1224 */
/* 0x000fe200078e021d */
/*0360*/ IADD3 R26, P1, R6, R23, RZ ; /* 0x00000017061a7210 */
/* 0x000fe20007f3e0ff */
/*0370*/ IMAD.MOV.U32 R29, RZ, RZ, R11 ; /* 0x000000ffff1d7224 */
/* 0x000fc800078e000b */
/*0380*/ IMAD.X R27, R13, 0x1, R18, P1 ; /* 0x000000010d1b7824 */
/* 0x000fe200008e0612 */
/*0390*/ STG.E [R28.64], R14 ; /* 0x0000000e1c007986 */
/* 0x0001ea000c101904 */
/*03a0*/ @!P0 LDG.E R27, [R26.64] ; /* 0x000000041a1b8981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IADD3 R28, P2, R20, R25, RZ ; /* 0x00000019141c7210 */
/* 0x001fca0007f5e0ff */
/*03c0*/ IMAD.X R29, R11, 0x1, R24, P2 ; /* 0x000000010b1d7824 */
/* 0x000fe200010e0618 */
/*03d0*/ @!P0 STS [R2.X4], R27 ; /* 0x0000001b02008388 */
/* 0x004fe80000004800 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ LDS R0, [R2.X4] ; /* 0x0000000002007984 */
/* 0x000e240000004800 */
/*0400*/ ISETP.NE.AND P1, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x001fc40003f25270 */
/*0410*/ IADD3 R0, R14, 0x1, RZ ; /* 0x000000010e007810 */
/* 0x000fd60007ffe0ff */
/*0420*/ @P1 IMAD.MOV R0, RZ, RZ, R14 ; /* 0x000000ffff001224 */
/* 0x000fe200078e020e */
/*0430*/ IADD3 R14, P1, R6, R21, RZ ; /* 0x00000015060e7210 */
/* 0x000fc80007f3e0ff */
/*0440*/ STG.E [R28.64], R0 ; /* 0x000000001c007986 */
/* 0x0001e2000c101904 */
/*0450*/ IMAD.X R15, R13, 0x1, R12, P1 ; /* 0x000000010d0f7824 */
/* 0x000fca00008e060c */
/*0460*/ @!P0 LDG.E R26, [R14.64] ; /* 0x000000040e1a8981 */
/* 0x0002a4000c1e1900 */
/*0470*/ IADD3 R14, P2, R28, R25, RZ ; /* 0x000000191c0e7210 */
/* 0x002fca0007f5e0ff */
/*0480*/ IMAD.X R15, R29, 0x1, R24, P2 ; /* 0x000000011d0f7824 */
/* 0x000fe400010e0618 */
/*0490*/ IMAD R29, R9, 0xc, RZ ; /* 0x0000000c091d7824 */
/* 0x001fe200078e02ff */
/*04a0*/ @!P0 STS [R2.X4], R26 ; /* 0x0000001a02008388 */
/* 0x004fe80000004800 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04c0*/ LDS R27, [R2.X4] ; /* 0x00000000021b7984 */
/* 0x000e240000004800 */
/*04d0*/ ISETP.NE.AND P1, PT, R27, R3, PT ; /* 0x000000031b00720c */
/* 0x001fc40003f25270 */
/*04e0*/ IADD3 R27, R0, 0x1, RZ ; /* 0x00000001001b7810 */
/* 0x000fd60007ffe0ff */
/*04f0*/ @P1 IMAD.MOV R27, RZ, RZ, R0 ; /* 0x000000ffff1b1224 */
/* 0x000fe400078e0200 */
/*0500*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fc600078e00ff */
/*0510*/ STG.E [R14.64], R27 ; /* 0x0000001b0e007986 */
/* 0x0001e2000c101904 */
/*0520*/ IMAD.WIDE.U32 R16, R0, 0xc, R16 ; /* 0x0000000c00107825 */
/* 0x000fc800078e0010 */
/*0530*/ IMAD.IADD R17, R17, 0x1, R29 ; /* 0x0000000111117824 */
/* 0x000fcc00078e021d */
/*0540*/ @!P0 LDG.E R17, [R16.64] ; /* 0x0000000410118981 */
/* 0x0002a2000c1e1900 */
/*0550*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe40007ffe0ff */
/*0560*/ IADD3 R29, R27, 0x1, RZ ; /* 0x000000011b1d7810 */
/* 0x000fe40007ffe0ff */
/*0570*/ IADD3 R14, P2, R14, R25, RZ ; /* 0x000000190e0e7210 */
/* 0x001fe40007f5e0ff */
/*0580*/ IADD3 R6, P4, R6, R19, RZ ; /* 0x0000001306067210 */
/* 0x000fc60007f9e0ff */
/*0590*/ IMAD.X R15, R15, 0x1, R24, P2 ; /* 0x000000010f0f7824 */
/* 0x000fe200010e0618 */
/*05a0*/ LEA R16, P3, R5, R20, 0x4 ; /* 0x0000001405107211 */
/* 0x002fe200078620ff */
/*05b0*/ IMAD.X R13, R13, 0x1, R10, P4 ; /* 0x000000010d0d7824 */
/* 0x000fe200020e060a */
/*05c0*/ IADD3 R20, P2, R14, R25, RZ ; /* 0x000000190e147210 */
/* 0x000fe20007f5e0ff */
/*05d0*/ @!P0 STS [R2.X4], R17 ; /* 0x0000001102008388 */
/* 0x0041e80000004800 */
/*05e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05f0*/ IMAD.X R17, R11, 0x1, R22, P3 ; /* 0x000000010b117824 */
/* 0x001fca00018e0616 */
/*0600*/ LDS R26, [R2.X4] ; /* 0x00000000021a7984 */
/* 0x000e240000004800 */
/*0610*/ ISETP.NE.AND P1, PT, R26, R3, PT ; /* 0x000000031a00720c */
/* 0x001fe20003f25270 */
/*0620*/ IMAD.X R26, R15, 0x1, R24, P2 ; /* 0x000000010f1a7824 */
/* 0x000fc800010e0618 */
/*0630*/ IMAD.MOV.U32 R11, RZ, RZ, R26 ; /* 0x000000ffff0b7224 */
/* 0x000fd000078e001a */
/*0640*/ @P1 IMAD.MOV R29, RZ, RZ, R27 ; /* 0x000000ffff1d1224 */
/* 0x000fe200078e021b */
/*0650*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f25270 */
/*0660*/ STG.E [R14.64], R29 ; /* 0x0000001d0e007986 */
/* 0x0001f2000c101904 */
/*0670*/ @P1 BRA 0x2c0 ; /* 0xfffffc4000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0690*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*06a0*/ SHF.L.U64.HI R4, R5, 0x2, R8 ; /* 0x0000000205047819 */
/* 0x000fe20000010208 */
/*06b0*/ IMAD.SHL.U32 R15, R0.reuse, 0x4, RZ ; /* 0x00000004000f7824 */
/* 0x041fe200078e00ff */
/*06c0*/ SHF.L.U64.HI R10, R0, 0x2, R9 ; /* 0x00000002000a7819 */
/* 0x000fe40000010209 */
/*06d0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*06e0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c8224 */
/* 0x000fca00078e0006 */
/*06f0*/ @!P0 LDG.E R9, [R12.64] ; /* 0x000000040c098981 */
/* 0x0010a2000c1e1900 */
/*0700*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe20007ffe0ff */
/*0710*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0010 */
/*0720*/ IADD3 R11, R29, 0x1, RZ ; /* 0x000000011d0b7810 */
/* 0x000fe40007ffe0ff */
/*0730*/ LEA R16, P1, R5, R16, 0x2 ; /* 0x0000001005107211 */
/* 0x000fe400078210ff */
/*0740*/ IADD3 R6, P2, R6, R15, RZ ; /* 0x0000000f06067210 */
/* 0x000fca0007f5e0ff */
/*0750*/ IMAD.X R13, R13, 0x1, R10, P2 ; /* 0x000000010d0d7824 */
/* 0x001fe200010e060a */
/*0760*/ @!P0 STS [R2.X4], R9 ; /* 0x0000000902008388 */
/* 0x0041e80000004800 */
/*0770*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0780*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0011 */
/*0790*/ IMAD.X R17, R17, 0x1, R4, P1 ; /* 0x0000000111117824 */
/* 0x000fc600008e0604 */
/*07a0*/ LDS R0, [R2.X4] ; /* 0x0000000002007984 */
/* 0x000e240000004800 */
/*07b0*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x001fda0003f05270 */
/*07c0*/ @P0 IMAD.MOV R11, RZ, RZ, R29 ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e021d */
/*07d0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f05270 */
/*07e0*/ IMAD.MOV.U32 R29, RZ, RZ, R11 ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e000b */
/*07f0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001f2000c101904 */
/*0800*/ @P0 BRA 0x6d0 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0810*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0820*/ BRA 0x820; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void integrateBins(int width, int height, int nbins, int* devImage, int binPitch, int* devIntegrals) {
__shared__ int pixels[16];
const int blockX = blockDim.y * blockIdx.x;
const int threadX = threadIdx.y;
const int bin = threadIdx.x;
const int x = blockX + threadX;
if (x >= width) return;
if (bin > nbins) return;
int* imagePointer = devImage + x;
int* outputPointer = devIntegrals + binPitch * x + bin;
int accumulant = 0;
for(int y = 0; y < height; y++) {
if (bin == 0) {
pixels[threadX] = *imagePointer;
}
__syncthreads();
if (pixels[threadX] == bin) accumulant++;
*outputPointer = accumulant;
imagePointer += width;
outputPointer += width * binPitch;
}
} | .file "tmpxft_000b1a4a_00000000-6_integrateBins.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_
.type _Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_, @function
_Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 16(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13integrateBinsiiiPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_, .-_Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_
.globl _Z13integrateBinsiiiPiiS_
.type _Z13integrateBinsiiiPiiS_, @function
_Z13integrateBinsiiiPiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13integrateBinsiiiPiiS_, .-_Z13integrateBinsiiiPiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13integrateBinsiiiPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13integrateBinsiiiPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void integrateBins(int width, int height, int nbins, int* devImage, int binPitch, int* devIntegrals) {
__shared__ int pixels[16];
const int blockX = blockDim.y * blockIdx.x;
const int threadX = threadIdx.y;
const int bin = threadIdx.x;
const int x = blockX + threadX;
if (x >= width) return;
if (bin > nbins) return;
int* imagePointer = devImage + x;
int* outputPointer = devIntegrals + binPitch * x + bin;
int accumulant = 0;
for(int y = 0; y < height; y++) {
if (bin == 0) {
pixels[threadX] = *imagePointer;
}
__syncthreads();
if (pixels[threadX] == bin) accumulant++;
*outputPointer = accumulant;
imagePointer += width;
outputPointer += width * binPitch;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void integrateBins(int width, int height, int nbins, int* devImage, int binPitch, int* devIntegrals) {
__shared__ int pixels[16];
const int blockX = blockDim.y * blockIdx.x;
const int threadX = threadIdx.y;
const int bin = threadIdx.x;
const int x = blockX + threadX;
if (x >= width) return;
if (bin > nbins) return;
int* imagePointer = devImage + x;
int* outputPointer = devIntegrals + binPitch * x + bin;
int accumulant = 0;
for(int y = 0; y < height; y++) {
if (bin == 0) {
pixels[threadX] = *imagePointer;
}
__syncthreads();
if (pixels[threadX] == bin) accumulant++;
*outputPointer = accumulant;
imagePointer += width;
outputPointer += width * binPitch;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void integrateBins(int width, int height, int nbins, int* devImage, int binPitch, int* devIntegrals) {
__shared__ int pixels[16];
const int blockX = blockDim.y * blockIdx.x;
const int threadX = threadIdx.y;
const int bin = threadIdx.x;
const int x = blockX + threadX;
if (x >= width) return;
if (bin > nbins) return;
int* imagePointer = devImage + x;
int* outputPointer = devIntegrals + binPitch * x + bin;
int accumulant = 0;
for(int y = 0; y < height; y++) {
if (bin == 0) {
pixels[threadX] = *imagePointer;
}
__syncthreads();
if (pixels[threadX] == bin) accumulant++;
*outputPointer = accumulant;
imagePointer += width;
outputPointer += width * binPitch;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13integrateBinsiiiPiiS_
.globl _Z13integrateBinsiiiPiiS_
.p2align 8
.type _Z13integrateBinsiiiPiiS_,@function
_Z13integrateBinsiiiPiiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e64 s2, s3, v4
v_cmp_gt_i32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_cmp_gt_i32 s5, 0
s_cselect_b32 s3, -1, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v5, 2, v1
v_lshlrev_b32_e32 v8, 2, v4
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_ashr_i32 s1, s4, 31
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v6, v2, s8
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, s0, s2, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v1, s0, s3, v3, s0
s_mul_i32 s2, s8, s4
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[2:3], s[2:3], 2
v_add_co_u32 v2, s0, s6, v6
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s7, v7, s0
v_add_co_u32 v2, s0, v2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_mov_b32 s0, s4
s_lshl_b64 s[6:7], s[0:1], 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v7, v5
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e64 s0, v7, v4
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
global_store_b32 v[2:3], v6, off
v_add_co_u32 v2, s0, v2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
v_add_co_u32 v0, s0, v0, s6
v_add_co_ci_u32_e64 v1, s0, s7, v1, s0
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_2
global_load_b32 v7, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v7
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13integrateBinsiiiPiiS_
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13integrateBinsiiiPiiS_, .Lfunc_end0-_Z13integrateBinsiiiPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13integrateBinsiiiPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13integrateBinsiiiPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void integrateBins(int width, int height, int nbins, int* devImage, int binPitch, int* devIntegrals) {
__shared__ int pixels[16];
const int blockX = blockDim.y * blockIdx.x;
const int threadX = threadIdx.y;
const int bin = threadIdx.x;
const int x = blockX + threadX;
if (x >= width) return;
if (bin > nbins) return;
int* imagePointer = devImage + x;
int* outputPointer = devIntegrals + binPitch * x + bin;
int accumulant = 0;
for(int y = 0; y < height; y++) {
if (bin == 0) {
pixels[threadX] = *imagePointer;
}
__syncthreads();
if (pixels[threadX] == bin) accumulant++;
*outputPointer = accumulant;
imagePointer += width;
outputPointer += width * binPitch;
}
} | .text
.file "integrateBins.hip"
.globl _Z28__device_stub__integrateBinsiiiPiiS_ # -- Begin function _Z28__device_stub__integrateBinsiiiPiiS_
.p2align 4, 0x90
.type _Z28__device_stub__integrateBinsiiiPiiS_,@function
_Z28__device_stub__integrateBinsiiiPiiS_: # @_Z28__device_stub__integrateBinsiiiPiiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13integrateBinsiiiPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__integrateBinsiiiPiiS_, .Lfunc_end0-_Z28__device_stub__integrateBinsiiiPiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13integrateBinsiiiPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13integrateBinsiiiPiiS_,@object # @_Z13integrateBinsiiiPiiS_
.section .rodata,"a",@progbits
.globl _Z13integrateBinsiiiPiiS_
.p2align 3, 0x0
_Z13integrateBinsiiiPiiS_:
.quad _Z28__device_stub__integrateBinsiiiPiiS_
.size _Z13integrateBinsiiiPiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13integrateBinsiiiPiiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__integrateBinsiiiPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13integrateBinsiiiPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13integrateBinsiiiPiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R6, R5, c[0x0][0x4], R2 ; /* 0x0000010005067a24 */
/* 0x001fe200078e0202 */
/*0050*/ ISETP.GT.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x002fc80003f04270 */
/*0060*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x160], P0 ; /* 0x0000580006007a0c */
/* 0x000fda0000706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff047624 */
/* 0x000fe200078e00ff */
/*0090*/ SHF.R.S32.HI R5, RZ, 0x1f, R3 ; /* 0x0000001fff057819 */
/* 0x000fe20000011403 */
/*00a0*/ IMAD R0, R6, c[0x0][0x178], RZ ; /* 0x00005e0006007a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f06270 */
/*00d0*/ IADD3 R17, P1, R0, R3, RZ ; /* 0x0000000300117210 */
/* 0x000fe20007f3e0ff */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc600078e0207 */
/*00f0*/ LEA.HI.X.SX32 R0, R0, R5, 0x1, P1 ; /* 0x0000000500007211 */
/* 0x000fe400008f0eff */
/*0100*/ LEA R16, P1, R17, c[0x0][0x180], 0x2 ; /* 0x0000600011107a11 */
/* 0x000fc800078210ff */
/*0110*/ LEA.HI.X R17, R17, c[0x0][0x184], R0, 0x2, P1 ; /* 0x0000610011117a11 */
/* 0x000fe200008f1400 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000ff00003800000 */
/*0130*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fe200078e00ff */
/*0150*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0007 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f06070 */
/*0180*/ IMAD R5, R0, c[0x0][0x178], RZ ; /* 0x00005e0000057a24 */
/* 0x000fe200078e02ff */
/*0190*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe200078ec0ff */
/*01a0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*01b0*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe40000011400 */
/*01c0*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fce0000011405 */
/*01d0*/ @!P0 BRA 0x680 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0010 */
/*01f0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f05270 */
/*0200*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0011 */
/*0210*/ SHF.L.U64.HI R10, R0.reuse, 0x4, R9.reuse ; /* 0x00000004000a7819 */
/* 0x140fe20000010209 */
/*0220*/ IMAD.SHL.U32 R19, R0.reuse, 0x10, RZ ; /* 0x0000001000137824 */
/* 0x040fe200078e00ff */
/*0230*/ SHF.L.U64.HI R12, R0.reuse, 0x3, R9.reuse ; /* 0x00000003000c7819 */
/* 0x140fe20000010209 */
/*0240*/ IMAD.SHL.U32 R21, R0.reuse, 0x8, RZ ; /* 0x0000000800157824 */
/* 0x040fe200078e00ff */
/*0250*/ SHF.L.U64.HI R18, R0.reuse, 0x2, R9 ; /* 0x0000000200127819 */
/* 0x040fe20000010209 */
/*0260*/ IMAD.SHL.U32 R23, R0, 0x4, RZ ; /* 0x0000000400177824 */
/* 0x000fe200078e00ff */
/*0270*/ IADD3 R4, -R7, c[0x0][0x164], RZ ; /* 0x0000590007047a10 */
/* 0x000fe20007ffe1ff */
/*0280*/ IMAD.SHL.U32 R25, R5.reuse, 0x4, RZ ; /* 0x0000000405197824 */
/* 0x040fe200078e00ff */
/*0290*/ SHF.L.U64.HI R22, R5.reuse, 0x4, R8.reuse ; /* 0x0000000405167819 */
/* 0x140fe20000010208 */
/*02a0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e00ff */
/*02b0*/ SHF.L.U64.HI R24, R5, 0x2, R8 ; /* 0x0000000205187819 */
/* 0x000fc40000010208 */
/*02c0*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0006 */
/*02d0*/ IMAD.MOV.U32 R17, RZ, RZ, R13 ; /* 0x000000ffff117224 */
/* 0x000fca00078e000d */
/*02e0*/ @!P0 LDG.E R15, [R16.64] ; /* 0x00000004100f8981 */
/* 0x001ea2000c1e1900 */
/*02f0*/ IADD3 R14, R29, 0x1, RZ ; /* 0x000000011d0e7810 */
/* 0x000fe20007ffe0ff */
/*0300*/ IMAD.MOV.U32 R28, RZ, RZ, R20 ; /* 0x000000ffff1c7224 */
/* 0x000fe400078e0014 */
/*0310*/ @!P0 STS [R2.X4], R15 ; /* 0x0000000f02008388 */
/* 0x004fe80000004800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0330*/ LDS R0, [R2.X4] ; /* 0x0000000002007984 */
/* 0x000e240000004800 */
/*0340*/ ISETP.NE.AND P1, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x001fda0003f25270 */
/*0350*/ @P1 IMAD.MOV R14, RZ, RZ, R29 ; /* 0x000000ffff0e1224 */
/* 0x000fe200078e021d */
/*0360*/ IADD3 R26, P1, R6, R23, RZ ; /* 0x00000017061a7210 */
/* 0x000fe20007f3e0ff */
/*0370*/ IMAD.MOV.U32 R29, RZ, RZ, R11 ; /* 0x000000ffff1d7224 */
/* 0x000fc800078e000b */
/*0380*/ IMAD.X R27, R13, 0x1, R18, P1 ; /* 0x000000010d1b7824 */
/* 0x000fe200008e0612 */
/*0390*/ STG.E [R28.64], R14 ; /* 0x0000000e1c007986 */
/* 0x0001ea000c101904 */
/*03a0*/ @!P0 LDG.E R27, [R26.64] ; /* 0x000000041a1b8981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IADD3 R28, P2, R20, R25, RZ ; /* 0x00000019141c7210 */
/* 0x001fca0007f5e0ff */
/*03c0*/ IMAD.X R29, R11, 0x1, R24, P2 ; /* 0x000000010b1d7824 */
/* 0x000fe200010e0618 */
/*03d0*/ @!P0 STS [R2.X4], R27 ; /* 0x0000001b02008388 */
/* 0x004fe80000004800 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ LDS R0, [R2.X4] ; /* 0x0000000002007984 */
/* 0x000e240000004800 */
/*0400*/ ISETP.NE.AND P1, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x001fc40003f25270 */
/*0410*/ IADD3 R0, R14, 0x1, RZ ; /* 0x000000010e007810 */
/* 0x000fd60007ffe0ff */
/*0420*/ @P1 IMAD.MOV R0, RZ, RZ, R14 ; /* 0x000000ffff001224 */
/* 0x000fe200078e020e */
/*0430*/ IADD3 R14, P1, R6, R21, RZ ; /* 0x00000015060e7210 */
/* 0x000fc80007f3e0ff */
/*0440*/ STG.E [R28.64], R0 ; /* 0x000000001c007986 */
/* 0x0001e2000c101904 */
/*0450*/ IMAD.X R15, R13, 0x1, R12, P1 ; /* 0x000000010d0f7824 */
/* 0x000fca00008e060c */
/*0460*/ @!P0 LDG.E R26, [R14.64] ; /* 0x000000040e1a8981 */
/* 0x0002a4000c1e1900 */
/*0470*/ IADD3 R14, P2, R28, R25, RZ ; /* 0x000000191c0e7210 */
/* 0x002fca0007f5e0ff */
/*0480*/ IMAD.X R15, R29, 0x1, R24, P2 ; /* 0x000000011d0f7824 */
/* 0x000fe400010e0618 */
/*0490*/ IMAD R29, R9, 0xc, RZ ; /* 0x0000000c091d7824 */
/* 0x001fe200078e02ff */
/*04a0*/ @!P0 STS [R2.X4], R26 ; /* 0x0000001a02008388 */
/* 0x004fe80000004800 */
/*04b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04c0*/ LDS R27, [R2.X4] ; /* 0x00000000021b7984 */
/* 0x000e240000004800 */
/*04d0*/ ISETP.NE.AND P1, PT, R27, R3, PT ; /* 0x000000031b00720c */
/* 0x001fc40003f25270 */
/*04e0*/ IADD3 R27, R0, 0x1, RZ ; /* 0x00000001001b7810 */
/* 0x000fd60007ffe0ff */
/*04f0*/ @P1 IMAD.MOV R27, RZ, RZ, R0 ; /* 0x000000ffff1b1224 */
/* 0x000fe400078e0200 */
/*0500*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fc600078e00ff */
/*0510*/ STG.E [R14.64], R27 ; /* 0x0000001b0e007986 */
/* 0x0001e2000c101904 */
/*0520*/ IMAD.WIDE.U32 R16, R0, 0xc, R16 ; /* 0x0000000c00107825 */
/* 0x000fc800078e0010 */
/*0530*/ IMAD.IADD R17, R17, 0x1, R29 ; /* 0x0000000111117824 */
/* 0x000fcc00078e021d */
/*0540*/ @!P0 LDG.E R17, [R16.64] ; /* 0x0000000410118981 */
/* 0x0002a2000c1e1900 */
/*0550*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe40007ffe0ff */
/*0560*/ IADD3 R29, R27, 0x1, RZ ; /* 0x000000011b1d7810 */
/* 0x000fe40007ffe0ff */
/*0570*/ IADD3 R14, P2, R14, R25, RZ ; /* 0x000000190e0e7210 */
/* 0x001fe40007f5e0ff */
/*0580*/ IADD3 R6, P4, R6, R19, RZ ; /* 0x0000001306067210 */
/* 0x000fc60007f9e0ff */
/*0590*/ IMAD.X R15, R15, 0x1, R24, P2 ; /* 0x000000010f0f7824 */
/* 0x000fe200010e0618 */
/*05a0*/ LEA R16, P3, R5, R20, 0x4 ; /* 0x0000001405107211 */
/* 0x002fe200078620ff */
/*05b0*/ IMAD.X R13, R13, 0x1, R10, P4 ; /* 0x000000010d0d7824 */
/* 0x000fe200020e060a */
/*05c0*/ IADD3 R20, P2, R14, R25, RZ ; /* 0x000000190e147210 */
/* 0x000fe20007f5e0ff */
/*05d0*/ @!P0 STS [R2.X4], R17 ; /* 0x0000001102008388 */
/* 0x0041e80000004800 */
/*05e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05f0*/ IMAD.X R17, R11, 0x1, R22, P3 ; /* 0x000000010b117824 */
/* 0x001fca00018e0616 */
/*0600*/ LDS R26, [R2.X4] ; /* 0x00000000021a7984 */
/* 0x000e240000004800 */
/*0610*/ ISETP.NE.AND P1, PT, R26, R3, PT ; /* 0x000000031a00720c */
/* 0x001fe20003f25270 */
/*0620*/ IMAD.X R26, R15, 0x1, R24, P2 ; /* 0x000000010f1a7824 */
/* 0x000fc800010e0618 */
/*0630*/ IMAD.MOV.U32 R11, RZ, RZ, R26 ; /* 0x000000ffff0b7224 */
/* 0x000fd000078e001a */
/*0640*/ @P1 IMAD.MOV R29, RZ, RZ, R27 ; /* 0x000000ffff1d1224 */
/* 0x000fe200078e021b */
/*0650*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc80003f25270 */
/*0660*/ STG.E [R14.64], R29 ; /* 0x0000001d0e007986 */
/* 0x0001f2000c101904 */
/*0670*/ @P1 BRA 0x2c0 ; /* 0xfffffc4000001947 */
/* 0x000fea000383ffff */
/*0680*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0690*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*06a0*/ SHF.L.U64.HI R4, R5, 0x2, R8 ; /* 0x0000000205047819 */
/* 0x000fe20000010208 */
/*06b0*/ IMAD.SHL.U32 R15, R0.reuse, 0x4, RZ ; /* 0x00000004000f7824 */
/* 0x041fe200078e00ff */
/*06c0*/ SHF.L.U64.HI R10, R0, 0x2, R9 ; /* 0x00000002000a7819 */
/* 0x000fe40000010209 */
/*06d0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*06e0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c8224 */
/* 0x000fca00078e0006 */
/*06f0*/ @!P0 LDG.E R9, [R12.64] ; /* 0x000000040c098981 */
/* 0x0010a2000c1e1900 */
/*0700*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe20007ffe0ff */
/*0710*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0010 */
/*0720*/ IADD3 R11, R29, 0x1, RZ ; /* 0x000000011d0b7810 */
/* 0x000fe40007ffe0ff */
/*0730*/ LEA R16, P1, R5, R16, 0x2 ; /* 0x0000001005107211 */
/* 0x000fe400078210ff */
/*0740*/ IADD3 R6, P2, R6, R15, RZ ; /* 0x0000000f06067210 */
/* 0x000fca0007f5e0ff */
/*0750*/ IMAD.X R13, R13, 0x1, R10, P2 ; /* 0x000000010d0d7824 */
/* 0x001fe200010e060a */
/*0760*/ @!P0 STS [R2.X4], R9 ; /* 0x0000000902008388 */
/* 0x0041e80000004800 */
/*0770*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0780*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0011 */
/*0790*/ IMAD.X R17, R17, 0x1, R4, P1 ; /* 0x0000000111117824 */
/* 0x000fc600008e0604 */
/*07a0*/ LDS R0, [R2.X4] ; /* 0x0000000002007984 */
/* 0x000e240000004800 */
/*07b0*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x001fda0003f05270 */
/*07c0*/ @P0 IMAD.MOV R11, RZ, RZ, R29 ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e021d */
/*07d0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f05270 */
/*07e0*/ IMAD.MOV.U32 R29, RZ, RZ, R11 ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e000b */
/*07f0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001f2000c101904 */
/*0800*/ @P0 BRA 0x6d0 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0810*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0820*/ BRA 0x820; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13integrateBinsiiiPiiS_
.globl _Z13integrateBinsiiiPiiS_
.p2align 8
.type _Z13integrateBinsiiiPiiS_,@function
_Z13integrateBinsiiiPiiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e64 s2, s3, v4
v_cmp_gt_i32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_cmp_gt_i32 s5, 0
s_cselect_b32 s3, -1, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b32_e32 v5, 2, v1
v_lshlrev_b32_e32 v8, 2, v4
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_ashr_i32 s1, s4, 31
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v6, v2, s8
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, s0, s2, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v1, s0, s3, v3, s0
s_mul_i32 s2, s8, s4
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[2:3], s[2:3], 2
v_add_co_u32 v2, s0, s6, v6
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s7, v7, s0
v_add_co_u32 v2, s0, v2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_mov_b32 s0, s4
s_lshl_b64 s[6:7], s[0:1], 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v7, v5
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e64 s0, v7, v4
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
global_store_b32 v[2:3], v6, off
v_add_co_u32 v2, s0, v2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
v_add_co_u32 v0, s0, v0, s6
v_add_co_ci_u32_e64 v1, s0, s7, v1, s0
s_cbranch_scc0 .LBB0_5
.LBB0_3:
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_2
global_load_b32 v7, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v7
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13integrateBinsiiiPiiS_
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13integrateBinsiiiPiiS_, .Lfunc_end0-_Z13integrateBinsiiiPiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13integrateBinsiiiPiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13integrateBinsiiiPiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b1a4a_00000000-6_integrateBins.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_
.type _Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_, @function
_Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 16(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13integrateBinsiiiPiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_, .-_Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_
.globl _Z13integrateBinsiiiPiiS_
.type _Z13integrateBinsiiiPiiS_, @function
_Z13integrateBinsiiiPiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13integrateBinsiiiPiiS_iiiPiiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13integrateBinsiiiPiiS_, .-_Z13integrateBinsiiiPiiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13integrateBinsiiiPiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13integrateBinsiiiPiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "integrateBins.hip"
.globl _Z28__device_stub__integrateBinsiiiPiiS_ # -- Begin function _Z28__device_stub__integrateBinsiiiPiiS_
.p2align 4, 0x90
.type _Z28__device_stub__integrateBinsiiiPiiS_,@function
_Z28__device_stub__integrateBinsiiiPiiS_: # @_Z28__device_stub__integrateBinsiiiPiiS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13integrateBinsiiiPiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__integrateBinsiiiPiiS_, .Lfunc_end0-_Z28__device_stub__integrateBinsiiiPiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13integrateBinsiiiPiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13integrateBinsiiiPiiS_,@object # @_Z13integrateBinsiiiPiiS_
.section .rodata,"a",@progbits
.globl _Z13integrateBinsiiiPiiS_
.p2align 3, 0x0
_Z13integrateBinsiiiPiiS_:
.quad _Z28__device_stub__integrateBinsiiiPiiS_
.size _Z13integrateBinsiiiPiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13integrateBinsiiiPiiS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__integrateBinsiiiPiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13integrateBinsiiiPiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda_runtime.h>
struct memoryPointer{
memoryPointer *ptr;
unsigned size;
unsigned *data;
};
typedef struct memoryPointer MemoryPointer;
static MemoryPointer base;
static MemoryPointer *freep = NULL;
void fastAddList(MemoryPointer *bp){
MemoryPointer *p;
for(p = freep; !(bp->data > p->data && bp->data < (p->ptr)->data); p = p->ptr)
if(p->data >= (p->ptr)->data && (bp->data > p->data || bp->data < (p->ptr)->data))
break;
if( ((MemoryPointer *) (((char *)bp->data) + bp->size)) == p->ptr){
bp->size += (p->ptr)->size;
bp->ptr = (p->ptr)->ptr;
cudaMemcpy(bp->data, &bp->size, sizeof(unsigned), cudaMemcpyHostToDevice);
free(p->ptr);
}else
bp->ptr = p->ptr;
if( ((MemoryPointer *) (((char *)p->data) + p->size)) == bp){
p->size += bp->size;
p->ptr = bp->ptr;
cudaMemcpy(p->data, &p->size, sizeof(unsigned), cudaMemcpyHostToDevice);
free(bp);
}else
p->ptr = bp;
freep = p;
}
void fastFree(void *loc){
loc = ((void *)(((char *)loc)-sizeof(unsigned)));
MemoryPointer *v = (MemoryPointer *) malloc(sizeof(MemoryPointer));
cudaMemcpy(&v->size, loc, sizeof(unsigned), cudaMemcpyDeviceToHost);
v->data = (unsigned *) loc;
fastAddList(v);
}
static MemoryPointer *morecore(unsigned nu){
void *cp;
MemoryPointer *up = (MemoryPointer *)malloc(sizeof(MemoryPointer));
if (nu < 1048576) nu = 1048576;
cudaMalloc(&cp, nu);
up->data = (unsigned *)cp;
up->size = nu;
cudaMemcpy(cp,&(up->size),sizeof(unsigned),cudaMemcpyHostToDevice);
fastAddList(up);
return freep;
}
void *fastMalloc(unsigned nbytes){
MemoryPointer *p, *prevp;
if ((prevp = freep)==NULL){
base.ptr = freep = prevp = &base;
base.size = 0;
}
nbytes+=sizeof(unsigned);
char *loc;
for(p = prevp->ptr; ;prevp = p, p = p->ptr){
if(p->size >= nbytes){
if(p->size == nbytes){
prevp->ptr = p->ptr;
loc = (char *) p->data;
free(p);
}else{
p->size -= nbytes;
loc =((char *) p->data)+p->size;
}
freep = prevp;
cudaMemcpy(loc,&nbytes,sizeof(unsigned),cudaMemcpyHostToDevice);
return (void *)(loc+sizeof(unsigned));
}
if (p == freep)
if((p = morecore(nbytes))==NULL)
return NULL;
}
}
int main(int argc, char **argv){
void *v;
int i, cap=0;
if(argc>1)cap=atoi(argv[1]);
for(i=0; i<cap; i++){
v = fastMalloc(1);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda_runtime.h>
struct memoryPointer{
memoryPointer *ptr;
unsigned size;
unsigned *data;
};
typedef struct memoryPointer MemoryPointer;
static MemoryPointer base;
static MemoryPointer *freep = NULL;
void fastAddList(MemoryPointer *bp){
MemoryPointer *p;
for(p = freep; !(bp->data > p->data && bp->data < (p->ptr)->data); p = p->ptr)
if(p->data >= (p->ptr)->data && (bp->data > p->data || bp->data < (p->ptr)->data))
break;
if( ((MemoryPointer *) (((char *)bp->data) + bp->size)) == p->ptr){
bp->size += (p->ptr)->size;
bp->ptr = (p->ptr)->ptr;
cudaMemcpy(bp->data, &bp->size, sizeof(unsigned), cudaMemcpyHostToDevice);
free(p->ptr);
}else
bp->ptr = p->ptr;
if( ((MemoryPointer *) (((char *)p->data) + p->size)) == bp){
p->size += bp->size;
p->ptr = bp->ptr;
cudaMemcpy(p->data, &p->size, sizeof(unsigned), cudaMemcpyHostToDevice);
free(bp);
}else
p->ptr = bp;
freep = p;
}
void fastFree(void *loc){
loc = ((void *)(((char *)loc)-sizeof(unsigned)));
MemoryPointer *v = (MemoryPointer *) malloc(sizeof(MemoryPointer));
cudaMemcpy(&v->size, loc, sizeof(unsigned), cudaMemcpyDeviceToHost);
v->data = (unsigned *) loc;
fastAddList(v);
}
static MemoryPointer *morecore(unsigned nu){
void *cp;
MemoryPointer *up = (MemoryPointer *)malloc(sizeof(MemoryPointer));
if (nu < 1048576) nu = 1048576;
cudaMalloc(&cp, nu);
up->data = (unsigned *)cp;
up->size = nu;
cudaMemcpy(cp,&(up->size),sizeof(unsigned),cudaMemcpyHostToDevice);
fastAddList(up);
return freep;
}
void *fastMalloc(unsigned nbytes){
MemoryPointer *p, *prevp;
if ((prevp = freep)==NULL){
base.ptr = freep = prevp = &base;
base.size = 0;
}
nbytes+=sizeof(unsigned);
char *loc;
for(p = prevp->ptr; ;prevp = p, p = p->ptr){
if(p->size >= nbytes){
if(p->size == nbytes){
prevp->ptr = p->ptr;
loc = (char *) p->data;
free(p);
}else{
p->size -= nbytes;
loc =((char *) p->data)+p->size;
}
freep = prevp;
cudaMemcpy(loc,&nbytes,sizeof(unsigned),cudaMemcpyHostToDevice);
return (void *)(loc+sizeof(unsigned));
}
if (p == freep)
if((p = morecore(nbytes))==NULL)
return NULL;
}
}
int main(int argc, char **argv){
void *v;
int i, cap=0;
if(argc>1)cap=atoi(argv[1]);
for(i=0; i<cap; i++){
v = fastMalloc(1);
}
} | .file "tmpxft_001b2e32_00000000-6_FastMalloc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11fastAddListP13memoryPointer
.type _Z11fastAddListP13memoryPointer, @function
_Z11fastAddListP13memoryPointer:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq _ZL5freep(%rip), %rbx
movq 16(%rdi), %rdi
jmp .L4
.L7:
movq (%rbx), %rdx
movq 16(%rdx), %rcx
cmpq %rcx, %rax
jb .L5
cmpq %rcx, %rdi
jb .L6
.L5:
movq %rdx, %rbx
.L4:
movq 16(%rbx), %rax
cmpq %rdi, %rax
jnb .L7
movq (%rbx), %rdx
movq 16(%rdx), %rcx
cmpq %rcx, %rdi
jb .L6
cmpq %rcx, %rax
jb .L5
.L6:
movl 8(%rbp), %ecx
movq (%rbx), %rdx
movl %ecx, %eax
addq %rdi, %rax
cmpq %rax, %rdx
je .L15
movq %rdx, 0(%rbp)
.L10:
movq 16(%rbx), %rdi
movl 8(%rbx), %edx
movl %edx, %eax
addq %rdi, %rax
cmpq %rax, %rbp
je .L16
movq %rbp, (%rbx)
.L12:
movq %rbx, _ZL5freep(%rip)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
addl 8(%rdx), %ecx
movl %ecx, 8(%rbp)
movq (%rbx), %rax
movq (%rax), %rax
movq %rax, 0(%rbp)
leaq 8(%rbp), %rsi
movl $1, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movq (%rbx), %rdi
call free@PLT
jmp .L10
.L16:
addl 8(%rbp), %edx
movl %edx, 8(%rbx)
movq 0(%rbp), %rax
movq %rax, (%rbx)
leaq 8(%rbx), %rsi
movl $1, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
jmp .L12
.cfi_endproc
.LFE2057:
.size _Z11fastAddListP13memoryPointer, .-_Z11fastAddListP13memoryPointer
.globl _Z8fastFreePv
.type _Z8fastFreePv, @function
_Z8fastFreePv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq -4(%rdi), %rbp
movl $24, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rax), %rdi
movl $2, %ecx
movl $4, %edx
movq %rbp, %rsi
call cudaMemcpy@PLT
movq %rbp, 16(%rbx)
movq %rbx, %rdi
call _Z11fastAddListP13memoryPointer
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8fastFreePv, .-_Z8fastFreePv
.globl _Z10fastMallocj
.type _Z10fastMallocj, @function
_Z10fastMallocj:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq _ZL5freep(%rip), %rbx
testq %rbx, %rbx
je .L31
.L20:
movl 12(%rsp), %eax
leal 4(%rax), %ebp
movl %ebp, 12(%rsp)
movq (%rbx), %rdi
movl 8(%rdi), %eax
leaq 16(%rsp), %r12
cmpl %ebp, %eax
jb .L21
.L26:
cmpl %ebp, %eax
je .L32
subl %ebp, %eax
movl %eax, 8(%rdi)
movl %eax, %ebp
addq 16(%rdi), %rbp
.L23:
movq %rbx, _ZL5freep(%rip)
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 4(%rbp), %rbx
.L19:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L33
movq %rbx, %rax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
leaq _ZL4base(%rip), %rbx
movq %rbx, _ZL5freep(%rip)
movq %rbx, _ZL4base(%rip)
movl $0, 8+_ZL4base(%rip)
jmp .L20
.L32:
movq (%rdi), %rax
movq %rax, (%rbx)
movq 16(%rdi), %rbp
call free@PLT
jmp .L23
.L25:
movq (%rbx), %rdi
movl 8(%rdi), %eax
movl 12(%rsp), %ebp
cmpl %ebp, %eax
jnb .L26
.L21:
movq %rdi, %rbx
cmpq %rdi, _ZL5freep(%rip)
jne .L25
movl $24, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %eax
cmpl %eax, %ebp
cmovb %eax, %ebp
movl %ebp, %esi
movq %r12, %rdi
call cudaMalloc@PLT
movq 16(%rsp), %rdi
movq %rdi, 16(%rbx)
movl %ebp, 8(%rbx)
leaq 8(%rbx), %rsi
movl $1, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movq %rbx, %rdi
call _Z11fastAddListP13memoryPointer
movq _ZL5freep(%rip), %rbx
testq %rbx, %rbx
jne .L25
jmp .L19
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z10fastMallocj, .-_Z10fastMallocj
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
cmpl $1, %edi
jg .L42
movl $0, %eax
ret
.L42:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
testl %eax, %eax
jle .L35
movl $0, %ebx
.L36:
movl $1, %edi
call _Z10fastMallocj
addl $1, %ebx
cmpl %ebp, %ebx
jne .L36
.L35:
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5freep
.comm _ZL5freep,8,8
.local _ZL4base
.comm _ZL4base,24,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda_runtime.h>
struct memoryPointer{
memoryPointer *ptr;
unsigned size;
unsigned *data;
};
typedef struct memoryPointer MemoryPointer;
static MemoryPointer base;
static MemoryPointer *freep = NULL;
void fastAddList(MemoryPointer *bp){
MemoryPointer *p;
for(p = freep; !(bp->data > p->data && bp->data < (p->ptr)->data); p = p->ptr)
if(p->data >= (p->ptr)->data && (bp->data > p->data || bp->data < (p->ptr)->data))
break;
if( ((MemoryPointer *) (((char *)bp->data) + bp->size)) == p->ptr){
bp->size += (p->ptr)->size;
bp->ptr = (p->ptr)->ptr;
cudaMemcpy(bp->data, &bp->size, sizeof(unsigned), cudaMemcpyHostToDevice);
free(p->ptr);
}else
bp->ptr = p->ptr;
if( ((MemoryPointer *) (((char *)p->data) + p->size)) == bp){
p->size += bp->size;
p->ptr = bp->ptr;
cudaMemcpy(p->data, &p->size, sizeof(unsigned), cudaMemcpyHostToDevice);
free(bp);
}else
p->ptr = bp;
freep = p;
}
void fastFree(void *loc){
loc = ((void *)(((char *)loc)-sizeof(unsigned)));
MemoryPointer *v = (MemoryPointer *) malloc(sizeof(MemoryPointer));
cudaMemcpy(&v->size, loc, sizeof(unsigned), cudaMemcpyDeviceToHost);
v->data = (unsigned *) loc;
fastAddList(v);
}
static MemoryPointer *morecore(unsigned nu){
void *cp;
MemoryPointer *up = (MemoryPointer *)malloc(sizeof(MemoryPointer));
if (nu < 1048576) nu = 1048576;
cudaMalloc(&cp, nu);
up->data = (unsigned *)cp;
up->size = nu;
cudaMemcpy(cp,&(up->size),sizeof(unsigned),cudaMemcpyHostToDevice);
fastAddList(up);
return freep;
}
void *fastMalloc(unsigned nbytes){
MemoryPointer *p, *prevp;
if ((prevp = freep)==NULL){
base.ptr = freep = prevp = &base;
base.size = 0;
}
nbytes+=sizeof(unsigned);
char *loc;
for(p = prevp->ptr; ;prevp = p, p = p->ptr){
if(p->size >= nbytes){
if(p->size == nbytes){
prevp->ptr = p->ptr;
loc = (char *) p->data;
free(p);
}else{
p->size -= nbytes;
loc =((char *) p->data)+p->size;
}
freep = prevp;
cudaMemcpy(loc,&nbytes,sizeof(unsigned),cudaMemcpyHostToDevice);
return (void *)(loc+sizeof(unsigned));
}
if (p == freep)
if((p = morecore(nbytes))==NULL)
return NULL;
}
}
int main(int argc, char **argv){
void *v;
int i, cap=0;
if(argc>1)cap=atoi(argv[1]);
for(i=0; i<cap; i++){
v = fastMalloc(1);
}
} | #include<stdio.h>
#include<hip/hip_runtime.h>
struct memoryPointer{
memoryPointer *ptr;
unsigned size;
unsigned *data;
};
typedef struct memoryPointer MemoryPointer;
static MemoryPointer base;
static MemoryPointer *freep = NULL;
void fastAddList(MemoryPointer *bp){
MemoryPointer *p;
for(p = freep; !(bp->data > p->data && bp->data < (p->ptr)->data); p = p->ptr)
if(p->data >= (p->ptr)->data && (bp->data > p->data || bp->data < (p->ptr)->data))
break;
if( ((MemoryPointer *) (((char *)bp->data) + bp->size)) == p->ptr){
bp->size += (p->ptr)->size;
bp->ptr = (p->ptr)->ptr;
hipMemcpy(bp->data, &bp->size, sizeof(unsigned), hipMemcpyHostToDevice);
free(p->ptr);
}else
bp->ptr = p->ptr;
if( ((MemoryPointer *) (((char *)p->data) + p->size)) == bp){
p->size += bp->size;
p->ptr = bp->ptr;
hipMemcpy(p->data, &p->size, sizeof(unsigned), hipMemcpyHostToDevice);
free(bp);
}else
p->ptr = bp;
freep = p;
}
void fastFree(void *loc){
loc = ((void *)(((char *)loc)-sizeof(unsigned)));
MemoryPointer *v = (MemoryPointer *) malloc(sizeof(MemoryPointer));
hipMemcpy(&v->size, loc, sizeof(unsigned), hipMemcpyDeviceToHost);
v->data = (unsigned *) loc;
fastAddList(v);
}
static MemoryPointer *morecore(unsigned nu){
void *cp;
MemoryPointer *up = (MemoryPointer *)malloc(sizeof(MemoryPointer));
if (nu < 1048576) nu = 1048576;
hipMalloc(&cp, nu);
up->data = (unsigned *)cp;
up->size = nu;
hipMemcpy(cp,&(up->size),sizeof(unsigned),hipMemcpyHostToDevice);
fastAddList(up);
return freep;
}
void *fastMalloc(unsigned nbytes){
MemoryPointer *p, *prevp;
if ((prevp = freep)==NULL){
base.ptr = freep = prevp = &base;
base.size = 0;
}
nbytes+=sizeof(unsigned);
char *loc;
for(p = prevp->ptr; ;prevp = p, p = p->ptr){
if(p->size >= nbytes){
if(p->size == nbytes){
prevp->ptr = p->ptr;
loc = (char *) p->data;
free(p);
}else{
p->size -= nbytes;
loc =((char *) p->data)+p->size;
}
freep = prevp;
hipMemcpy(loc,&nbytes,sizeof(unsigned),hipMemcpyHostToDevice);
return (void *)(loc+sizeof(unsigned));
}
if (p == freep)
if((p = morecore(nbytes))==NULL)
return NULL;
}
}
int main(int argc, char **argv){
void *v;
int i, cap=0;
if(argc>1)cap=atoi(argv[1]);
for(i=0; i<cap; i++){
v = fastMalloc(1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
struct memoryPointer{
memoryPointer *ptr;
unsigned size;
unsigned *data;
};
typedef struct memoryPointer MemoryPointer;
static MemoryPointer base;
static MemoryPointer *freep = NULL;
void fastAddList(MemoryPointer *bp){
MemoryPointer *p;
for(p = freep; !(bp->data > p->data && bp->data < (p->ptr)->data); p = p->ptr)
if(p->data >= (p->ptr)->data && (bp->data > p->data || bp->data < (p->ptr)->data))
break;
if( ((MemoryPointer *) (((char *)bp->data) + bp->size)) == p->ptr){
bp->size += (p->ptr)->size;
bp->ptr = (p->ptr)->ptr;
hipMemcpy(bp->data, &bp->size, sizeof(unsigned), hipMemcpyHostToDevice);
free(p->ptr);
}else
bp->ptr = p->ptr;
if( ((MemoryPointer *) (((char *)p->data) + p->size)) == bp){
p->size += bp->size;
p->ptr = bp->ptr;
hipMemcpy(p->data, &p->size, sizeof(unsigned), hipMemcpyHostToDevice);
free(bp);
}else
p->ptr = bp;
freep = p;
}
void fastFree(void *loc){
loc = ((void *)(((char *)loc)-sizeof(unsigned)));
MemoryPointer *v = (MemoryPointer *) malloc(sizeof(MemoryPointer));
hipMemcpy(&v->size, loc, sizeof(unsigned), hipMemcpyDeviceToHost);
v->data = (unsigned *) loc;
fastAddList(v);
}
static MemoryPointer *morecore(unsigned nu){
void *cp;
MemoryPointer *up = (MemoryPointer *)malloc(sizeof(MemoryPointer));
if (nu < 1048576) nu = 1048576;
hipMalloc(&cp, nu);
up->data = (unsigned *)cp;
up->size = nu;
hipMemcpy(cp,&(up->size),sizeof(unsigned),hipMemcpyHostToDevice);
fastAddList(up);
return freep;
}
void *fastMalloc(unsigned nbytes){
MemoryPointer *p, *prevp;
if ((prevp = freep)==NULL){
base.ptr = freep = prevp = &base;
base.size = 0;
}
nbytes+=sizeof(unsigned);
char *loc;
for(p = prevp->ptr; ;prevp = p, p = p->ptr){
if(p->size >= nbytes){
if(p->size == nbytes){
prevp->ptr = p->ptr;
loc = (char *) p->data;
free(p);
}else{
p->size -= nbytes;
loc =((char *) p->data)+p->size;
}
freep = prevp;
hipMemcpy(loc,&nbytes,sizeof(unsigned),hipMemcpyHostToDevice);
return (void *)(loc+sizeof(unsigned));
}
if (p == freep)
if((p = morecore(nbytes))==NULL)
return NULL;
}
}
int main(int argc, char **argv){
void *v;
int i, cap=0;
if(argc>1)cap=atoi(argv[1]);
for(i=0; i<cap; i++){
v = fastMalloc(1);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
struct memoryPointer{
memoryPointer *ptr;
unsigned size;
unsigned *data;
};
typedef struct memoryPointer MemoryPointer;
static MemoryPointer base;
static MemoryPointer *freep = NULL;
void fastAddList(MemoryPointer *bp){
MemoryPointer *p;
for(p = freep; !(bp->data > p->data && bp->data < (p->ptr)->data); p = p->ptr)
if(p->data >= (p->ptr)->data && (bp->data > p->data || bp->data < (p->ptr)->data))
break;
if( ((MemoryPointer *) (((char *)bp->data) + bp->size)) == p->ptr){
bp->size += (p->ptr)->size;
bp->ptr = (p->ptr)->ptr;
hipMemcpy(bp->data, &bp->size, sizeof(unsigned), hipMemcpyHostToDevice);
free(p->ptr);
}else
bp->ptr = p->ptr;
if( ((MemoryPointer *) (((char *)p->data) + p->size)) == bp){
p->size += bp->size;
p->ptr = bp->ptr;
hipMemcpy(p->data, &p->size, sizeof(unsigned), hipMemcpyHostToDevice);
free(bp);
}else
p->ptr = bp;
freep = p;
}
void fastFree(void *loc){
loc = ((void *)(((char *)loc)-sizeof(unsigned)));
MemoryPointer *v = (MemoryPointer *) malloc(sizeof(MemoryPointer));
hipMemcpy(&v->size, loc, sizeof(unsigned), hipMemcpyDeviceToHost);
v->data = (unsigned *) loc;
fastAddList(v);
}
static MemoryPointer *morecore(unsigned nu){
void *cp;
MemoryPointer *up = (MemoryPointer *)malloc(sizeof(MemoryPointer));
if (nu < 1048576) nu = 1048576;
hipMalloc(&cp, nu);
up->data = (unsigned *)cp;
up->size = nu;
hipMemcpy(cp,&(up->size),sizeof(unsigned),hipMemcpyHostToDevice);
fastAddList(up);
return freep;
}
void *fastMalloc(unsigned nbytes){
MemoryPointer *p, *prevp;
if ((prevp = freep)==NULL){
base.ptr = freep = prevp = &base;
base.size = 0;
}
nbytes+=sizeof(unsigned);
char *loc;
for(p = prevp->ptr; ;prevp = p, p = p->ptr){
if(p->size >= nbytes){
if(p->size == nbytes){
prevp->ptr = p->ptr;
loc = (char *) p->data;
free(p);
}else{
p->size -= nbytes;
loc =((char *) p->data)+p->size;
}
freep = prevp;
hipMemcpy(loc,&nbytes,sizeof(unsigned),hipMemcpyHostToDevice);
return (void *)(loc+sizeof(unsigned));
}
if (p == freep)
if((p = morecore(nbytes))==NULL)
return NULL;
}
}
int main(int argc, char **argv){
void *v;
int i, cap=0;
if(argc>1)cap=atoi(argv[1]);
for(i=0; i<cap; i++){
v = fastMalloc(1);
}
} | .text
.file "FastMalloc.hip"
.globl _Z11fastAddListP13memoryPointer # -- Begin function _Z11fastAddListP13memoryPointer
.p2align 4, 0x90
.type _Z11fastAddListP13memoryPointer,@function
_Z11fastAddListP13memoryPointer: # @_Z11fastAddListP13memoryPointer
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movq 16(%rdi), %rdi
movl $_ZL5freep, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movq (%r14), %r14
movq 16(%r14), %rax
cmpq %rax, %rdi
jbe .LBB0_3
# %bb.2: # in Loop: Header=BB0_1 Depth=1
movq (%r14), %rcx
cmpq 16(%rcx), %rdi
jb .LBB0_5
.LBB0_3: # %.critedge
# in Loop: Header=BB0_1 Depth=1
cmpq %rax, %rdi
seta %cl
movq (%r14), %rdx
movq 16(%rdx), %rsi
cmpq %rsi, %rdi
setb %dl
cmpq %rsi, %rax
jb .LBB0_1
# %bb.4: # %.critedge
# in Loop: Header=BB0_1 Depth=1
orb %dl, %cl
je .LBB0_1
.LBB0_5:
movl 8(%rbx), %eax
leaq (%rdi,%rax), %rdx
movq (%r14), %rcx
cmpq %rcx, %rdx
je .LBB0_6
# %bb.7:
movq %rcx, (%rbx)
jmp .LBB0_8
.LBB0_6:
addl 8(%rcx), %eax
leaq 8(%rbx), %rsi
movl %eax, 8(%rbx)
movq (%rcx), %rax
movq %rax, (%rbx)
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq (%r14), %rdi
callq free
.LBB0_8:
movq 16(%r14), %rdi
movl 8(%r14), %eax
leaq (%rdi,%rax), %rcx
cmpq %rbx, %rcx
je .LBB0_9
# %bb.10:
movq %rbx, (%r14)
jmp .LBB0_11
.LBB0_9:
addl 8(%rbx), %eax
leaq 8(%r14), %rsi
movl %eax, 8(%r14)
movq (%rbx), %rax
movq %rax, (%r14)
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
.LBB0_11:
movq %r14, _ZL5freep(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11fastAddListP13memoryPointer, .Lfunc_end0-_Z11fastAddListP13memoryPointer
.cfi_endproc
# -- End function
.globl _Z8fastFreePv # -- Begin function _Z8fastFreePv
.p2align 4, 0x90
.type _Z8fastFreePv,@function
_Z8fastFreePv: # @_Z8fastFreePv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
addq $-4, %rbx
movl $24, %edi
callq malloc
movq %rax, %r14
leaq 8(%rax), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $2, %ecx
callq hipMemcpy
movq %rbx, 16(%r14)
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _Z11fastAddListP13memoryPointer # TAILCALL
.Lfunc_end1:
.size _Z8fastFreePv, .Lfunc_end1-_Z8fastFreePv
.cfi_endproc
# -- End function
.globl _Z10fastMallocj # -- Begin function _Z10fastMallocj
.p2align 4, 0x90
.type _Z10fastMallocj,@function
_Z10fastMallocj: # @_Z10fastMallocj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl %edi, 4(%rsp)
movq _ZL5freep(%rip), %r12
testq %r12, %r12
jne .LBB2_2
# %bb.1:
movq $_ZL4base, _ZL5freep(%rip)
movl $_ZL4base, %r12d
movq $_ZL4base, _ZL4base(%rip)
movl $0, _ZL4base+8(%rip)
.LBB2_2:
addl $4, %ebx
movl %ebx, 4(%rsp)
movq (%r12), %rax
movl 8(%rax), %r15d
cmpl %ebx, %r15d
jae .LBB2_3
# %bb.8:
movl $1048576, %ebp # imm = 0x100000
leaq 8(%rsp), %r14
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_9 Depth=1
movq (%rax), %rdi
movl 8(%rdi), %r15d
movl 4(%rsp), %ebx
movq %rax, %r12
movq %rdi, %rax
cmpl %ebx, %r15d
jae .LBB2_4
.LBB2_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq _ZL5freep(%rip), %rax
jne .LBB2_13
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movl $24, %edi
callq malloc
movq %rax, %r15
cmpl $1048577, %ebx # imm = 0x100001
cmovbl %ebp, %ebx
movq %r14, %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rdi, 16(%r15)
leaq 8(%r15), %rsi
movl %ebx, 8(%r15)
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
callq _Z11fastAddListP13memoryPointer
movq _ZL5freep(%rip), %rax
testq %rax, %rax
jne .LBB2_13
# %bb.11:
xorl %r15d, %r15d
jmp .LBB2_12
.LBB2_3:
movq %rax, %rdi
.LBB2_4: # %._crit_edge
subl %ebx, %r15d
jne .LBB2_6
# %bb.5:
movq (%rdi), %rax
movq %rax, (%r12)
movq 16(%rdi), %r15
callq free
jmp .LBB2_7
.LBB2_6:
movl %r15d, 8(%rdi)
addq 16(%rdi), %r15
.LBB2_7:
movq %r12, _ZL5freep(%rip)
leaq 4(%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $1, %ecx
callq hipMemcpy
addq $4, %r15
.LBB2_12: # %.loopexit
movq %r15, %rax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10fastMallocj, .Lfunc_end2-_Z10fastMallocj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
xorl %ebx, %ebx
cmpl $2, %edi
jl .LBB3_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB3_2:
testl %ebx, %ebx
jle .LBB3_4
.p2align 4, 0x90
.LBB3_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, %edi
callq _Z10fastMallocj
decl %ebx
jne .LBB3_3
.LBB3_4: # %._crit_edge
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type _ZL5freep,@object # @_ZL5freep
.local _ZL5freep
.comm _ZL5freep,8,8
.type _ZL4base,@object # @_ZL4base
.local _ZL4base
.comm _ZL4base,24,8
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL4base
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b2e32_00000000-6_FastMalloc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11fastAddListP13memoryPointer
.type _Z11fastAddListP13memoryPointer, @function
_Z11fastAddListP13memoryPointer:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq _ZL5freep(%rip), %rbx
movq 16(%rdi), %rdi
jmp .L4
.L7:
movq (%rbx), %rdx
movq 16(%rdx), %rcx
cmpq %rcx, %rax
jb .L5
cmpq %rcx, %rdi
jb .L6
.L5:
movq %rdx, %rbx
.L4:
movq 16(%rbx), %rax
cmpq %rdi, %rax
jnb .L7
movq (%rbx), %rdx
movq 16(%rdx), %rcx
cmpq %rcx, %rdi
jb .L6
cmpq %rcx, %rax
jb .L5
.L6:
movl 8(%rbp), %ecx
movq (%rbx), %rdx
movl %ecx, %eax
addq %rdi, %rax
cmpq %rax, %rdx
je .L15
movq %rdx, 0(%rbp)
.L10:
movq 16(%rbx), %rdi
movl 8(%rbx), %edx
movl %edx, %eax
addq %rdi, %rax
cmpq %rax, %rbp
je .L16
movq %rbp, (%rbx)
.L12:
movq %rbx, _ZL5freep(%rip)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
addl 8(%rdx), %ecx
movl %ecx, 8(%rbp)
movq (%rbx), %rax
movq (%rax), %rax
movq %rax, 0(%rbp)
leaq 8(%rbp), %rsi
movl $1, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movq (%rbx), %rdi
call free@PLT
jmp .L10
.L16:
addl 8(%rbp), %edx
movl %edx, 8(%rbx)
movq 0(%rbp), %rax
movq %rax, (%rbx)
leaq 8(%rbx), %rsi
movl $1, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
jmp .L12
.cfi_endproc
.LFE2057:
.size _Z11fastAddListP13memoryPointer, .-_Z11fastAddListP13memoryPointer
.globl _Z8fastFreePv
.type _Z8fastFreePv, @function
_Z8fastFreePv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq -4(%rdi), %rbp
movl $24, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rax), %rdi
movl $2, %ecx
movl $4, %edx
movq %rbp, %rsi
call cudaMemcpy@PLT
movq %rbp, 16(%rbx)
movq %rbx, %rdi
call _Z11fastAddListP13memoryPointer
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8fastFreePv, .-_Z8fastFreePv
.globl _Z10fastMallocj
.type _Z10fastMallocj, @function
_Z10fastMallocj:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq _ZL5freep(%rip), %rbx
testq %rbx, %rbx
je .L31
.L20:
movl 12(%rsp), %eax
leal 4(%rax), %ebp
movl %ebp, 12(%rsp)
movq (%rbx), %rdi
movl 8(%rdi), %eax
leaq 16(%rsp), %r12
cmpl %ebp, %eax
jb .L21
.L26:
cmpl %ebp, %eax
je .L32
subl %ebp, %eax
movl %eax, 8(%rdi)
movl %eax, %ebp
addq 16(%rdi), %rbp
.L23:
movq %rbx, _ZL5freep(%rip)
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 4(%rbp), %rbx
.L19:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L33
movq %rbx, %rax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
leaq _ZL4base(%rip), %rbx
movq %rbx, _ZL5freep(%rip)
movq %rbx, _ZL4base(%rip)
movl $0, 8+_ZL4base(%rip)
jmp .L20
.L32:
movq (%rdi), %rax
movq %rax, (%rbx)
movq 16(%rdi), %rbp
call free@PLT
jmp .L23
.L25:
movq (%rbx), %rdi
movl 8(%rdi), %eax
movl 12(%rsp), %ebp
cmpl %ebp, %eax
jnb .L26
.L21:
movq %rdi, %rbx
cmpq %rdi, _ZL5freep(%rip)
jne .L25
movl $24, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %eax
cmpl %eax, %ebp
cmovb %eax, %ebp
movl %ebp, %esi
movq %r12, %rdi
call cudaMalloc@PLT
movq 16(%rsp), %rdi
movq %rdi, 16(%rbx)
movl %ebp, 8(%rbx)
leaq 8(%rbx), %rsi
movl $1, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movq %rbx, %rdi
call _Z11fastAddListP13memoryPointer
movq _ZL5freep(%rip), %rbx
testq %rbx, %rbx
jne .L25
jmp .L19
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z10fastMallocj, .-_Z10fastMallocj
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
cmpl $1, %edi
jg .L42
movl $0, %eax
ret
.L42:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
testl %eax, %eax
jle .L35
movl $0, %ebx
.L36:
movl $1, %edi
call _Z10fastMallocj
addl $1, %ebx
cmpl %ebp, %ebx
jne .L36
.L35:
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5freep
.comm _ZL5freep,8,8
.local _ZL4base
.comm _ZL4base,24,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "FastMalloc.hip"
.globl _Z11fastAddListP13memoryPointer # -- Begin function _Z11fastAddListP13memoryPointer
.p2align 4, 0x90
.type _Z11fastAddListP13memoryPointer,@function
_Z11fastAddListP13memoryPointer: # @_Z11fastAddListP13memoryPointer
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movq 16(%rdi), %rdi
movl $_ZL5freep, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movq (%r14), %r14
movq 16(%r14), %rax
cmpq %rax, %rdi
jbe .LBB0_3
# %bb.2: # in Loop: Header=BB0_1 Depth=1
movq (%r14), %rcx
cmpq 16(%rcx), %rdi
jb .LBB0_5
.LBB0_3: # %.critedge
# in Loop: Header=BB0_1 Depth=1
cmpq %rax, %rdi
seta %cl
movq (%r14), %rdx
movq 16(%rdx), %rsi
cmpq %rsi, %rdi
setb %dl
cmpq %rsi, %rax
jb .LBB0_1
# %bb.4: # %.critedge
# in Loop: Header=BB0_1 Depth=1
orb %dl, %cl
je .LBB0_1
.LBB0_5:
movl 8(%rbx), %eax
leaq (%rdi,%rax), %rdx
movq (%r14), %rcx
cmpq %rcx, %rdx
je .LBB0_6
# %bb.7:
movq %rcx, (%rbx)
jmp .LBB0_8
.LBB0_6:
addl 8(%rcx), %eax
leaq 8(%rbx), %rsi
movl %eax, 8(%rbx)
movq (%rcx), %rax
movq %rax, (%rbx)
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq (%r14), %rdi
callq free
.LBB0_8:
movq 16(%r14), %rdi
movl 8(%r14), %eax
leaq (%rdi,%rax), %rcx
cmpq %rbx, %rcx
je .LBB0_9
# %bb.10:
movq %rbx, (%r14)
jmp .LBB0_11
.LBB0_9:
addl 8(%rbx), %eax
leaq 8(%r14), %rsi
movl %eax, 8(%r14)
movq (%rbx), %rax
movq %rax, (%r14)
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
.LBB0_11:
movq %r14, _ZL5freep(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11fastAddListP13memoryPointer, .Lfunc_end0-_Z11fastAddListP13memoryPointer
.cfi_endproc
# -- End function
.globl _Z8fastFreePv # -- Begin function _Z8fastFreePv
.p2align 4, 0x90
.type _Z8fastFreePv,@function
_Z8fastFreePv: # @_Z8fastFreePv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
addq $-4, %rbx
movl $24, %edi
callq malloc
movq %rax, %r14
leaq 8(%rax), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $2, %ecx
callq hipMemcpy
movq %rbx, 16(%r14)
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _Z11fastAddListP13memoryPointer # TAILCALL
.Lfunc_end1:
.size _Z8fastFreePv, .Lfunc_end1-_Z8fastFreePv
.cfi_endproc
# -- End function
.globl _Z10fastMallocj # -- Begin function _Z10fastMallocj
.p2align 4, 0x90
.type _Z10fastMallocj,@function
_Z10fastMallocj: # @_Z10fastMallocj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl %edi, 4(%rsp)
movq _ZL5freep(%rip), %r12
testq %r12, %r12
jne .LBB2_2
# %bb.1:
movq $_ZL4base, _ZL5freep(%rip)
movl $_ZL4base, %r12d
movq $_ZL4base, _ZL4base(%rip)
movl $0, _ZL4base+8(%rip)
.LBB2_2:
addl $4, %ebx
movl %ebx, 4(%rsp)
movq (%r12), %rax
movl 8(%rax), %r15d
cmpl %ebx, %r15d
jae .LBB2_3
# %bb.8:
movl $1048576, %ebp # imm = 0x100000
leaq 8(%rsp), %r14
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_9 Depth=1
movq (%rax), %rdi
movl 8(%rdi), %r15d
movl 4(%rsp), %ebx
movq %rax, %r12
movq %rdi, %rax
cmpl %ebx, %r15d
jae .LBB2_4
.LBB2_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq _ZL5freep(%rip), %rax
jne .LBB2_13
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movl $24, %edi
callq malloc
movq %rax, %r15
cmpl $1048577, %ebx # imm = 0x100001
cmovbl %ebp, %ebx
movq %r14, %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rdi, 16(%r15)
leaq 8(%r15), %rsi
movl %ebx, 8(%r15)
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
callq _Z11fastAddListP13memoryPointer
movq _ZL5freep(%rip), %rax
testq %rax, %rax
jne .LBB2_13
# %bb.11:
xorl %r15d, %r15d
jmp .LBB2_12
.LBB2_3:
movq %rax, %rdi
.LBB2_4: # %._crit_edge
subl %ebx, %r15d
jne .LBB2_6
# %bb.5:
movq (%rdi), %rax
movq %rax, (%r12)
movq 16(%rdi), %r15
callq free
jmp .LBB2_7
.LBB2_6:
movl %r15d, 8(%rdi)
addq 16(%rdi), %r15
.LBB2_7:
movq %r12, _ZL5freep(%rip)
leaq 4(%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $1, %ecx
callq hipMemcpy
addq $4, %r15
.LBB2_12: # %.loopexit
movq %r15, %rax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10fastMallocj, .Lfunc_end2-_Z10fastMallocj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
xorl %ebx, %ebx
cmpl $2, %edi
jl .LBB3_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB3_2:
testl %ebx, %ebx
jle .LBB3_4
.p2align 4, 0x90
.LBB3_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, %edi
callq _Z10fastMallocj
decl %ebx
jne .LBB3_3
.LBB3_4: # %._crit_edge
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type _ZL5freep,@object # @_ZL5freep
.local _ZL5freep
.comm _ZL5freep,8,8
.type _ZL4base,@object # @_ZL4base
.local _ZL4base
.comm _ZL4base,24,8
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL4base
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// First solution with global memory
// Shared memory residual calculation
// Reduction code from CUDA Slides - Mark Harris
__global__ void gpu_HeatReduction (float *res, float *result) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int index= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = res[index];
__syncthreads();
// Reduce the shared table to compute the residual
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0)
{
int blockIndex = blockIdx.x;
result[blockIndex] = sdata[tid];
}
} | code for sm_80
Function : _Z17gpu_HeatReductionPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x001fe200000006ff */
/*0100*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x000fe200078e10ff */
/*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0160*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*01e0*/ IMAD.WIDE R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0203 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// First solution with global memory
// Shared memory residual calculation
// Reduction code from CUDA Slides - Mark Harris
__global__ void gpu_HeatReduction (float *res, float *result) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int index= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = res[index];
__syncthreads();
// Reduce the shared table to compute the residual
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0)
{
int blockIndex = blockIdx.x;
result[blockIndex] = sdata[tid];
}
} | .file "tmpxft_0001319a_00000000-6_gpu_HeatReduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_
.type _Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_, @function
_Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17gpu_HeatReductionPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_, .-_Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_
.globl _Z17gpu_HeatReductionPfS_
.type _Z17gpu_HeatReductionPfS_, @function
_Z17gpu_HeatReductionPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17gpu_HeatReductionPfS_, .-_Z17gpu_HeatReductionPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17gpu_HeatReductionPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17gpu_HeatReductionPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// First solution with global memory
// Shared memory residual calculation
// Reduction code from CUDA Slides - Mark Harris
__global__ void gpu_HeatReduction (float *res, float *result) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int index= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = res[index];
__syncthreads();
// Reduce the shared table to compute the residual
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0)
{
int blockIndex = blockIdx.x;
result[blockIndex] = sdata[tid];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// First solution with global memory
// Shared memory residual calculation
// Reduction code from CUDA Slides - Mark Harris
__global__ void gpu_HeatReduction (float *res, float *result) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int index= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = res[index];
__syncthreads();
// Reduce the shared table to compute the residual
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0)
{
int blockIndex = blockIdx.x;
result[blockIndex] = sdata[tid];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// First solution with global memory
// Shared memory residual calculation
// Reduction code from CUDA Slides - Mark Harris
__global__ void gpu_HeatReduction (float *res, float *result) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int index= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = res[index];
__syncthreads();
// Reduce the shared table to compute the residual
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0)
{
int blockIndex = blockIdx.x;
result[blockIndex] = sdata[tid];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17gpu_HeatReductionPfS_
.globl _Z17gpu_HeatReductionPfS_
.p2align 8
.type _Z17gpu_HeatReductionPfS_,@function
_Z17gpu_HeatReductionPfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v1
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17gpu_HeatReductionPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17gpu_HeatReductionPfS_, .Lfunc_end0-_Z17gpu_HeatReductionPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17gpu_HeatReductionPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17gpu_HeatReductionPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// First solution with global memory
// Shared memory residual calculation
// Reduction code from CUDA Slides - Mark Harris
__global__ void gpu_HeatReduction (float *res, float *result) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int index= blockIdx.x*blockDim.x+ threadIdx.x;
sdata[tid] = res[index];
__syncthreads();
// Reduce the shared table to compute the residual
for(unsigned int s=blockDim.x/2; s>0; s>>=1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0)
{
int blockIndex = blockIdx.x;
result[blockIndex] = sdata[tid];
}
} | .text
.file "gpu_HeatReduction.hip"
.globl _Z32__device_stub__gpu_HeatReductionPfS_ # -- Begin function _Z32__device_stub__gpu_HeatReductionPfS_
.p2align 4, 0x90
.type _Z32__device_stub__gpu_HeatReductionPfS_,@function
_Z32__device_stub__gpu_HeatReductionPfS_: # @_Z32__device_stub__gpu_HeatReductionPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17gpu_HeatReductionPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__gpu_HeatReductionPfS_, .Lfunc_end0-_Z32__device_stub__gpu_HeatReductionPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17gpu_HeatReductionPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17gpu_HeatReductionPfS_,@object # @_Z17gpu_HeatReductionPfS_
.section .rodata,"a",@progbits
.globl _Z17gpu_HeatReductionPfS_
.p2align 3, 0x0
_Z17gpu_HeatReductionPfS_:
.quad _Z32__device_stub__gpu_HeatReductionPfS_
.size _Z17gpu_HeatReductionPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17gpu_HeatReductionPfS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__gpu_HeatReductionPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17gpu_HeatReductionPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17gpu_HeatReductionPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x001fe200000006ff */
/*0100*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x000fe200078e10ff */
/*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0160*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*01e0*/ IMAD.WIDE R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0203 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17gpu_HeatReductionPfS_
.globl _Z17gpu_HeatReductionPfS_
.p2align 8
.type _Z17gpu_HeatReductionPfS_,@function
_Z17gpu_HeatReductionPfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v1
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17gpu_HeatReductionPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17gpu_HeatReductionPfS_, .Lfunc_end0-_Z17gpu_HeatReductionPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17gpu_HeatReductionPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17gpu_HeatReductionPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001319a_00000000-6_gpu_HeatReduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_
.type _Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_, @function
_Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17gpu_HeatReductionPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_, .-_Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_
.globl _Z17gpu_HeatReductionPfS_
.type _Z17gpu_HeatReductionPfS_, @function
_Z17gpu_HeatReductionPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17gpu_HeatReductionPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17gpu_HeatReductionPfS_, .-_Z17gpu_HeatReductionPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17gpu_HeatReductionPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17gpu_HeatReductionPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_HeatReduction.hip"
.globl _Z32__device_stub__gpu_HeatReductionPfS_ # -- Begin function _Z32__device_stub__gpu_HeatReductionPfS_
.p2align 4, 0x90
.type _Z32__device_stub__gpu_HeatReductionPfS_,@function
_Z32__device_stub__gpu_HeatReductionPfS_: # @_Z32__device_stub__gpu_HeatReductionPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17gpu_HeatReductionPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__gpu_HeatReductionPfS_, .Lfunc_end0-_Z32__device_stub__gpu_HeatReductionPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17gpu_HeatReductionPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17gpu_HeatReductionPfS_,@object # @_Z17gpu_HeatReductionPfS_
.section .rodata,"a",@progbits
.globl _Z17gpu_HeatReductionPfS_
.p2align 3, 0x0
_Z17gpu_HeatReductionPfS_:
.quad _Z32__device_stub__gpu_HeatReductionPfS_
.size _Z17gpu_HeatReductionPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17gpu_HeatReductionPfS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__gpu_HeatReductionPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17gpu_HeatReductionPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda.h"
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
inline double gettime_ms() {
struct timeval t;
gettimeofday(&t,NULL);
return (t.tv_sec+t.tv_usec*1e-6)*1000;
}
__device__ int cost_func(int costX){
int tem=0;
for(int i=0;i<costX;++i){
tem++;
}
return tem;
}
__global__ void ctrl_kernel(int D, int* res_arr, int costX) {
int result=0;
for(int i=0; i<D; ++i){ //D’s maximum value is 4
int tmp=1;
for (int j=0;j<4-i;++j) tmp=tmp*2;
int t=16-tmp;
if(threadIdx.x<16-t){
result+=cost_func(costX);
}else if (threadIdx.x>=16+t){
result+=cost_func(costX);
}
}
res_arr[blockIdx.x*blockDim.x+threadIdx.x]=result;
}
int main(int argc, char **argv){
//input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergen D
int U, A, B, T, X, D;
if (argc!=7) {
printf("\nInput arguments wrong!\n input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergence D \n ");
return 0;
}
U=atof(argv[1]);
A=atoi(argv[2]);
B=atoi(argv[3]);
T=atoi(argv[4]);
X=atoi(argv[5]);
D=atoi(argv[6]);
if(D>4||D<0) {
printf("\nDivergence D has to be between 0~4\n");
return 0;
}
cudaSetDevice(1);
int *res_arr_h=(int *)malloc(B*T*sizeof(int));
int *res_arr_d;
cudaMalloc(&res_arr_d,B*T*sizeof(int));
printf("\nkernel starts\n");
double ktime=gettime_ms();
ctrl_kernel<<<B,T>>>(D,res_arr_d,X);
cudaDeviceSynchronize();
ktime=gettime_ms()-ktime;
printf("\nKernel_Finish_in %f ms\n",ktime);
cudaMemcpy(res_arr_h,res_arr_d,B*T*sizeof(int),cudaMemcpyDeviceToHost);
printf("results:\n");
for(int i=0;i<32;++i){
printf("%d ",res_arr_h[i]);
}
printf("\n");
free(res_arr_h);
cudaFree(res_arr_d);
return 0;
} | code for sm_80
Function : _Z11ctrl_kerneliPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe20003f01270 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0030*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff008224 */
/* 0x000fe200078e00ff */
/*0040*/ @!P0 BRA 0x990 ; /* 0x0000094000008947 */
/* 0x000fea0003800000 */
/*0050*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f01270 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff077624 */
/* 0x000fca00078e00ff */
/*0070*/ LOP3.LUT R2, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307027812 */
/* 0x000fce00078ec0ff */
/*0080*/ @P0 BRA 0x1d0 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*00c0*/ ISETP.GT.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fda0003f24270 */
/*00d0*/ @!P1 BRA 0x140 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*00e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*00f0*/ IADD3 R3, R3, -0x3, RZ ; /* 0xfffffffd03037810 */
/* 0x000fe40007ffe0ff */
/*0100*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GE.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f26270 */
/*0120*/ @!P1 BRA 0x100 ; /* 0xffffffd000009947 */
/* 0x000fea000383ffff */
/*0130*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0140*/ IADD3 R3, -R2, c[0x0][0x160], RZ ; /* 0x0000580002037a10 */
/* 0x000fc80007ffe1ff */
/*0150*/ ISETP.GT.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f24270 */
/*0160*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe20003f0e170 */
/*0170*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff001224 */
/* 0x000fe200078e00ff */
/*0180*/ @P1 IADD3 R2, R2, 0x2, RZ ; /* 0x0000000202021810 */
/* 0x000fd60007ffe0ff */
/*0190*/ ISETP.LT.OR P0, PT, R2, c[0x0][0x160], P0 ; /* 0x0000580002007a0c */
/* 0x000fda0000701670 */
/*01a0*/ @!P0 BRA 0x990 ; /* 0x000007e000008947 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*01c0*/ BRA 0x990 ; /* 0x000007c000007947 */
/* 0x000fea0003800000 */
/*01d0*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*01e0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0200*/ IADD3 R8, -R2, c[0x0][0x170], RZ ; /* 0x00005c0002087a10 */
/* 0x000fe20007ffe1ff */
/*0210*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc600078e00ff */
/*0220*/ ISETP.GT.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f04070 */
/*0230*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fd800078e00ff */
/*0240*/ @P0 BRA 0x4c0 ; /* 0x0000027000000947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R4, -R3, 0x3, RZ ; /* 0x0000000303047810 */
/* 0x000fe20007ffe1ff */
/*0260*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0280*/ IADD3 R4, -R3, 0x4, RZ ; /* 0x0000000403047810 */
/* 0x000fc80007ffe1ff */
/*0290*/ LOP3.LUT R6, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304067812 */
/* 0x000fce00078ec0ff */
/*02a0*/ @!P0 BRA 0x430 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IADD3 R4, RZ, -R6, -R3 ; /* 0x80000006ff047210 */
/* 0x000fe20007ffe803 */
/*02c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*02d0*/ ISETP.GT.AND P0, PT, R4, -0x4, PT ; /* 0xfffffffc0400780c */
/* 0x000fda0003f04270 */
/*02e0*/ @!P0 BRA 0x3f0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*02f0*/ IADD3 R10, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fe40007ffe0ff */
/*0300*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0310*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fda0003f24270 */
/*0320*/ @!P1 BRA 0x380 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0330*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0340*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0350*/ IMAD.U32 R5, R5, 0x10000, RZ ; /* 0x0001000005057824 */
/* 0x000fc600078e00ff */
/*0360*/ ISETP.GT.AND P1, PT, R4, 0x8, PT ; /* 0x000000080400780c */
/* 0x000fda0003f24270 */
/*0370*/ @P1 BRA 0x340 ; /* 0xffffffc000001947 */
/* 0x000fea000383ffff */
/*0380*/ IADD3 R10, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fc80007ffe0ff */
/*0390*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*03a0*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe20003f0e170 */
/*03b0*/ @P1 IMAD.SHL.U32 R5, R5, 0x100, RZ ; /* 0x0000010005051824 */
/* 0x000fe200078e00ff */
/*03c0*/ @P1 IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804041810 */
/* 0x000fd60007ffe0ff */
/*03d0*/ ISETP.NE.OR P0, PT, R4, -0x4, P0 ; /* 0xfffffffc0400780c */
/* 0x000fda0000705670 */
/*03e0*/ @!P0 BRA 0x430 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*03f0*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0400*/ IMAD.SHL.U32 R5, R5, 0x10, RZ ; /* 0x0000001005057824 */
/* 0x000fc600078e00ff */
/*0410*/ ISETP.NE.AND P0, PT, R4, -0x4, PT ; /* 0xfffffffc0400780c */
/* 0x000fda0003f05270 */
/*0420*/ @P0 BRA 0x3f0 ; /* 0xffffffc000000947 */
/* 0x001fea000383ffff */
/*0430*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0440*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x000fd800078e0005 */
/*0450*/ @!P0 BRA 0x4c0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0460*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05270 */
/*0470*/ IMAD.SHL.U32 R4, R5, 0x2, RZ ; /* 0x0000000205047824 */
/* 0x000fd800078e00ff */
/*0480*/ @P0 ISETP.NE.AND P1, PT, R6, 0x2, PT ; /* 0x000000020600080c */
/* 0x000fe20003f25270 */
/*0490*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, 0x2 ; /* 0x00000002ff060424 */
/* 0x000fca00078e00ff */
/*04a0*/ @P0 SEL R6, R6, 0x3, !P1 ; /* 0x0000000306060807 */
/* 0x000fc80004800000 */
/*04b0*/ @P0 SHF.L.U32 R4, R5, R6, RZ ; /* 0x0000000605040219 */
/* 0x000fc800000006ff */
/*04c0*/ ISETP.GE.U32.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x001fe20003f06070 */
/*04d0*/ BSSY B0, 0x960 ; /* 0x0000048000007945 */
/* 0x000fd80003800000 */
/*04e0*/ @!P0 BRA 0x740 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*04f0*/ IADD3 R4, -R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x000fc80007ffe1ff */
/*0500*/ ISETP.GE.U32.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fda0003f06070 */
/*0510*/ @!P0 BRA 0x950 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0520*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe20003f06070 */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd800078e00ff */
/*0540*/ @!P0 BRA 0x6b0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0560*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fd400078e0008 */
/*0580*/ @!P0 BRA 0x670 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*05a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*05b0*/ @!P1 BRA 0x610 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*05c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*05d0*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe40007ffe0ff */
/*05e0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fda0003f24270 */
/*0600*/ @P1 BRA 0x5d0 ; /* 0xffffffc000001947 */
/* 0x000fea000383ffff */
/*0610*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0620*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*0630*/ @P1 IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804041810 */
/* 0x000fe40007ffe0ff */
/*0640*/ @P1 IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805051810 */
/* 0x000fd20007ffe0ff */
/*0650*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0660*/ @!P0 BRA 0x6b0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0670*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe40007ffe0ff */
/*0680*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0690*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*06a0*/ @P0 BRA 0x670 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*06c0*/ @!P0 BRA 0x720 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0002 */
/*06e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*06f0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0700*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0710*/ @P0 BRA 0x6e0 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*0720*/ IMAD.IADD R0, R0, 0x1, R5 ; /* 0x0000000100007824 */
/* 0x000fe200078e0205 */
/*0730*/ BRA 0x950 ; /* 0x0000021000007947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe20003f06070 */
/*0750*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd800078e00ff */
/*0760*/ @!P0 BRA 0x8d0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0780*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0790*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fd400078e0008 */
/*07a0*/ @!P0 BRA 0x890 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*07b0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*07c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*07d0*/ @!P1 BRA 0x830 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*07e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*07f0*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe40007ffe0ff */
/*0800*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*0810*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fda0003f24270 */
/*0820*/ @P1 BRA 0x7f0 ; /* 0xffffffc000001947 */
/* 0x000fea000383ffff */
/*0830*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0840*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*0850*/ @P1 IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804041810 */
/* 0x000fe40007ffe0ff */
/*0860*/ @P1 IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805051810 */
/* 0x000fd20007ffe0ff */
/*0870*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0880*/ @!P0 BRA 0x8d0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0890*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*08c0*/ @P0 BRA 0x890 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*08d0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*08e0*/ @!P0 BRA 0x940 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0002 */
/*0900*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0910*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0920*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0930*/ @P0 BRA 0x900 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*0940*/ IMAD.IADD R0, R0, 0x1, R5 ; /* 0x0000000100007824 */
/* 0x000fe400078e0205 */
/*0950*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0960*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc80007ffe0ff */
/*0970*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0980*/ @!P0 BRA 0x220 ; /* 0xfffff89000008947 */
/* 0x000fea000383ffff */
/*0990*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*09a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*09b0*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*09c0*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0205 */
/*09d0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0003 */
/*09e0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
inline double gettime_ms() {
struct timeval t;
gettimeofday(&t,NULL);
return (t.tv_sec+t.tv_usec*1e-6)*1000;
}
__device__ int cost_func(int costX){
int tem=0;
for(int i=0;i<costX;++i){
tem++;
}
return tem;
}
__global__ void ctrl_kernel(int D, int* res_arr, int costX) {
int result=0;
for(int i=0; i<D; ++i){ //D’s maximum value is 4
int tmp=1;
for (int j=0;j<4-i;++j) tmp=tmp*2;
int t=16-tmp;
if(threadIdx.x<16-t){
result+=cost_func(costX);
}else if (threadIdx.x>=16+t){
result+=cost_func(costX);
}
}
res_arr[blockIdx.x*blockDim.x+threadIdx.x]=result;
}
int main(int argc, char **argv){
//input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergen D
int U, A, B, T, X, D;
if (argc!=7) {
printf("\nInput arguments wrong!\n input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergence D \n ");
return 0;
}
U=atof(argv[1]);
A=atoi(argv[2]);
B=atoi(argv[3]);
T=atoi(argv[4]);
X=atoi(argv[5]);
D=atoi(argv[6]);
if(D>4||D<0) {
printf("\nDivergence D has to be between 0~4\n");
return 0;
}
cudaSetDevice(1);
int *res_arr_h=(int *)malloc(B*T*sizeof(int));
int *res_arr_d;
cudaMalloc(&res_arr_d,B*T*sizeof(int));
printf("\nkernel starts\n");
double ktime=gettime_ms();
ctrl_kernel<<<B,T>>>(D,res_arr_d,X);
cudaDeviceSynchronize();
ktime=gettime_ms()-ktime;
printf("\nKernel_Finish_in %f ms\n",ktime);
cudaMemcpy(res_arr_h,res_arr_d,B*T*sizeof(int),cudaMemcpyDeviceToHost);
printf("results:\n");
for(int i=0;i<32;++i){
printf("%d ",res_arr_h[i]);
}
printf("\n");
free(res_arr_h);
cudaFree(res_arr_d);
return 0;
} | .file "tmpxft_001020b3_00000000-6_ctrl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._Z10gettime_msv,"axG",@progbits,_Z10gettime_msv,comdat
.weak _Z10gettime_msv
.type _Z10gettime_msv, @function
_Z10gettime_msv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
mulsd .LC1(%rip), %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10gettime_msv, .-_Z10gettime_msv
.text
.globl _Z9cost_funci
.type _Z9cost_funci, @function
_Z9cost_funci:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z9cost_funci, .-_Z9cost_funci
.globl _Z33__device_stub__Z11ctrl_kerneliPiiiPii
.type _Z33__device_stub__Z11ctrl_kerneliPiiiPii, @function
_Z33__device_stub__Z11ctrl_kerneliPiiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11ctrl_kerneliPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z11ctrl_kerneliPiiiPii, .-_Z33__device_stub__Z11ctrl_kerneliPiiiPii
.globl _Z11ctrl_kerneliPii
.type _Z11ctrl_kerneliPii, @function
_Z11ctrl_kerneliPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11ctrl_kerneliPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11ctrl_kerneliPii, .-_Z11ctrl_kerneliPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\nInput arguments wrong!\n input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergence D \n "
.align 8
.LC3:
.string "\nDivergence D has to be between 0~4\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\nkernel starts\n"
.LC5:
.string "\nKernel_Finish_in %f ms\n"
.LC6:
.string "results:\n"
.LC7:
.string "%d "
.LC8:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $7, %edi
je .L18
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L19:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq 48(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
cmpl $4, %eax
ja .L27
movl $1, %edi
call cudaSetDevice@PLT
movl %r12d, %ebx
imull %ebp, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10gettime_msv
movsd %xmm0, 8(%rsp)
movl %r12d, 44(%rsp)
movl $1, 48(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
call cudaDeviceSynchronize@PLT
call _Z10gettime_msv
subsd 8(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 128(%r13), %r12
leaq .LC7(%rip), %rbp
.L22:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L22
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L19
.L27:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L28:
movl %r14d, %edx
movq 24(%rsp), %rsi
movl %r15d, %edi
call _Z33__device_stub__Z11ctrl_kerneliPiiiPii
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z11ctrl_kerneliPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z11ctrl_kerneliPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC1:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
inline double gettime_ms() {
struct timeval t;
gettimeofday(&t,NULL);
return (t.tv_sec+t.tv_usec*1e-6)*1000;
}
__device__ int cost_func(int costX){
int tem=0;
for(int i=0;i<costX;++i){
tem++;
}
return tem;
}
__global__ void ctrl_kernel(int D, int* res_arr, int costX) {
int result=0;
for(int i=0; i<D; ++i){ //D’s maximum value is 4
int tmp=1;
for (int j=0;j<4-i;++j) tmp=tmp*2;
int t=16-tmp;
if(threadIdx.x<16-t){
result+=cost_func(costX);
}else if (threadIdx.x>=16+t){
result+=cost_func(costX);
}
}
res_arr[blockIdx.x*blockDim.x+threadIdx.x]=result;
}
int main(int argc, char **argv){
//input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergen D
int U, A, B, T, X, D;
if (argc!=7) {
printf("\nInput arguments wrong!\n input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergence D \n ");
return 0;
}
U=atof(argv[1]);
A=atoi(argv[2]);
B=atoi(argv[3]);
T=atoi(argv[4]);
X=atoi(argv[5]);
D=atoi(argv[6]);
if(D>4||D<0) {
printf("\nDivergence D has to be between 0~4\n");
return 0;
}
cudaSetDevice(1);
int *res_arr_h=(int *)malloc(B*T*sizeof(int));
int *res_arr_d;
cudaMalloc(&res_arr_d,B*T*sizeof(int));
printf("\nkernel starts\n");
double ktime=gettime_ms();
ctrl_kernel<<<B,T>>>(D,res_arr_d,X);
cudaDeviceSynchronize();
ktime=gettime_ms()-ktime;
printf("\nKernel_Finish_in %f ms\n",ktime);
cudaMemcpy(res_arr_h,res_arr_d,B*T*sizeof(int),cudaMemcpyDeviceToHost);
printf("results:\n");
for(int i=0;i<32;++i){
printf("%d ",res_arr_h[i]);
}
printf("\n");
free(res_arr_h);
cudaFree(res_arr_d);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
inline double gettime_ms() {
struct timeval t;
gettimeofday(&t,NULL);
return (t.tv_sec+t.tv_usec*1e-6)*1000;
}
__device__ int cost_func(int costX){
int tem=0;
for(int i=0;i<costX;++i){
tem++;
}
return tem;
}
__global__ void ctrl_kernel(int D, int* res_arr, int costX) {
int result=0;
for(int i=0; i<D; ++i){ //D’s maximum value is 4
int tmp=1;
for (int j=0;j<4-i;++j) tmp=tmp*2;
int t=16-tmp;
if(threadIdx.x<16-t){
result+=cost_func(costX);
}else if (threadIdx.x>=16+t){
result+=cost_func(costX);
}
}
res_arr[blockIdx.x*blockDim.x+threadIdx.x]=result;
}
int main(int argc, char **argv){
//input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergen D
int U, A, B, T, X, D;
if (argc!=7) {
printf("\nInput arguments wrong!\n input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergence D \n ");
return 0;
}
U=atof(argv[1]);
A=atoi(argv[2]);
B=atoi(argv[3]);
T=atoi(argv[4]);
X=atoi(argv[5]);
D=atoi(argv[6]);
if(D>4||D<0) {
printf("\nDivergence D has to be between 0~4\n");
return 0;
}
hipSetDevice(1);
int *res_arr_h=(int *)malloc(B*T*sizeof(int));
int *res_arr_d;
hipMalloc(&res_arr_d,B*T*sizeof(int));
printf("\nkernel starts\n");
double ktime=gettime_ms();
ctrl_kernel<<<B,T>>>(D,res_arr_d,X);
hipDeviceSynchronize();
ktime=gettime_ms()-ktime;
printf("\nKernel_Finish_in %f ms\n",ktime);
hipMemcpy(res_arr_h,res_arr_d,B*T*sizeof(int),hipMemcpyDeviceToHost);
printf("results:\n");
for(int i=0;i<32;++i){
printf("%d ",res_arr_h[i]);
}
printf("\n");
free(res_arr_h);
hipFree(res_arr_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
inline double gettime_ms() {
struct timeval t;
gettimeofday(&t,NULL);
return (t.tv_sec+t.tv_usec*1e-6)*1000;
}
__device__ int cost_func(int costX){
int tem=0;
for(int i=0;i<costX;++i){
tem++;
}
return tem;
}
__global__ void ctrl_kernel(int D, int* res_arr, int costX) {
int result=0;
for(int i=0; i<D; ++i){ //D’s maximum value is 4
int tmp=1;
for (int j=0;j<4-i;++j) tmp=tmp*2;
int t=16-tmp;
if(threadIdx.x<16-t){
result+=cost_func(costX);
}else if (threadIdx.x>=16+t){
result+=cost_func(costX);
}
}
res_arr[blockIdx.x*blockDim.x+threadIdx.x]=result;
}
int main(int argc, char **argv){
//input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergen D
int U, A, B, T, X, D;
if (argc!=7) {
printf("\nInput arguments wrong!\n input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergence D \n ");
return 0;
}
U=atof(argv[1]);
A=atoi(argv[2]);
B=atoi(argv[3]);
T=atoi(argv[4]);
X=atoi(argv[5]);
D=atoi(argv[6]);
if(D>4||D<0) {
printf("\nDivergence D has to be between 0~4\n");
return 0;
}
hipSetDevice(1);
int *res_arr_h=(int *)malloc(B*T*sizeof(int));
int *res_arr_d;
hipMalloc(&res_arr_d,B*T*sizeof(int));
printf("\nkernel starts\n");
double ktime=gettime_ms();
ctrl_kernel<<<B,T>>>(D,res_arr_d,X);
hipDeviceSynchronize();
ktime=gettime_ms()-ktime;
printf("\nKernel_Finish_in %f ms\n",ktime);
hipMemcpy(res_arr_h,res_arr_d,B*T*sizeof(int),hipMemcpyDeviceToHost);
printf("results:\n");
for(int i=0;i<32;++i){
printf("%d ",res_arr_h[i]);
}
printf("\n");
free(res_arr_h);
hipFree(res_arr_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11ctrl_kerneliPii
.globl _Z11ctrl_kerneliPii
.p2align 8
.type _Z11ctrl_kerneliPii,@function
_Z11ctrl_kerneliPii:
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_load_b32 s4, s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_mov_b32 s3, 0
s_mov_b32 s5, 4
s_waitcnt lgkmcnt(0)
s_max_i32 s4, s4, 0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_sub_i32 s7, 32, s6
s_add_i32 s3, s3, 1
v_cmp_le_u32_e32 vcc_lo, s7, v0
s_add_i32 s5, s5, -1
s_cmp_eq_u32 s3, s2
v_cndmask_b32_e64 v2, 0, s4, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v2, s4, vcc_lo
v_add_nc_u32_e32 v1, v1, v2
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_cmp_gt_u32 s3, 3
s_mov_b32 s6, 1
s_cbranch_scc1 .LBB0_2
s_max_i32 s7, s5, 1
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s7, s7, -1
s_lshl_b32 s6, s6, 1
s_cmp_eq_u32 s7, 0
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
v_mov_b32_e32 v1, 0
.LBB0_7:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11ctrl_kerneliPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11ctrl_kerneliPii, .Lfunc_end0-_Z11ctrl_kerneliPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11ctrl_kerneliPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11ctrl_kerneliPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
inline double gettime_ms() {
struct timeval t;
gettimeofday(&t,NULL);
return (t.tv_sec+t.tv_usec*1e-6)*1000;
}
__device__ int cost_func(int costX){
int tem=0;
for(int i=0;i<costX;++i){
tem++;
}
return tem;
}
__global__ void ctrl_kernel(int D, int* res_arr, int costX) {
int result=0;
for(int i=0; i<D; ++i){ //D’s maximum value is 4
int tmp=1;
for (int j=0;j<4-i;++j) tmp=tmp*2;
int t=16-tmp;
if(threadIdx.x<16-t){
result+=cost_func(costX);
}else if (threadIdx.x>=16+t){
result+=cost_func(costX);
}
}
res_arr[blockIdx.x*blockDim.x+threadIdx.x]=result;
}
int main(int argc, char **argv){
//input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergen D
int U, A, B, T, X, D;
if (argc!=7) {
printf("\nInput arguments wrong!\n input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergence D \n ");
return 0;
}
U=atof(argv[1]);
A=atoi(argv[2]);
B=atoi(argv[3]);
T=atoi(argv[4]);
X=atoi(argv[5]);
D=atoi(argv[6]);
if(D>4||D<0) {
printf("\nDivergence D has to be between 0~4\n");
return 0;
}
hipSetDevice(1);
int *res_arr_h=(int *)malloc(B*T*sizeof(int));
int *res_arr_d;
hipMalloc(&res_arr_d,B*T*sizeof(int));
printf("\nkernel starts\n");
double ktime=gettime_ms();
ctrl_kernel<<<B,T>>>(D,res_arr_d,X);
hipDeviceSynchronize();
ktime=gettime_ms()-ktime;
printf("\nKernel_Finish_in %f ms\n",ktime);
hipMemcpy(res_arr_h,res_arr_d,B*T*sizeof(int),hipMemcpyDeviceToHost);
printf("results:\n");
for(int i=0;i<32;++i){
printf("%d ",res_arr_h[i]);
}
printf("\n");
free(res_arr_h);
hipFree(res_arr_d);
return 0;
} | .text
.file "ctrl.hip"
.globl _Z26__device_stub__ctrl_kerneliPii # -- Begin function _Z26__device_stub__ctrl_kerneliPii
.p2align 4, 0x90
.type _Z26__device_stub__ctrl_kerneliPii,@function
_Z26__device_stub__ctrl_kerneliPii: # @_Z26__device_stub__ctrl_kerneliPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11ctrl_kerneliPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__ctrl_kerneliPii, .Lfunc_end0-_Z26__device_stub__ctrl_kerneliPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI1_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $7, %edi
jne .LBB1_1
# %bb.2:
movq %rsi, %rbx
movq 40(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 48(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $5, %eax
jb .LBB1_4
# %bb.3:
movl $.Lstr.2, %edi
callq puts@PLT
jmp .LBB1_9
.LBB1_1:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_9
.LBB1_4:
movq %rax, %rbp
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movl $1, %edi
callq hipSetDevice
movl %r12d, %eax
imull %r13d, %eax
movslq %eax, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 16(%rsp), %xmm0
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
mulsd .LCPI1_1(%rip), %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
movl %r13d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq (%rsp), %rax
movl %ebp, 12(%rsp)
movq %rax, 96(%rsp)
movl %r15d, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rax
movq %rax, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11ctrl_kerneliPii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI1_1(%rip), %xmm0
subsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $32, %r14
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
.LBB1_9:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11ctrl_kerneliPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11ctrl_kerneliPii,@object # @_Z11ctrl_kerneliPii
.section .rodata,"a",@progbits
.globl _Z11ctrl_kerneliPii
.p2align 3, 0x0
_Z11ctrl_kerneliPii:
.quad _Z26__device_stub__ctrl_kerneliPii
.size _Z11ctrl_kerneliPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nInput arguments wrong!\n input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergence D \n "
.size .L.str, 110
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nKernel_Finish_in %f ms\n"
.size .L.str.3, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d "
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11ctrl_kerneliPii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nkernel starts"
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "results:"
.size .Lstr.1, 9
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nDivergence D has to be between 0~4"
.size .Lstr.2, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__ctrl_kerneliPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11ctrl_kerneliPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11ctrl_kerneliPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe20003f01270 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0030*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff008224 */
/* 0x000fe200078e00ff */
/*0040*/ @!P0 BRA 0x990 ; /* 0x0000094000008947 */
/* 0x000fea0003800000 */
/*0050*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f01270 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff077624 */
/* 0x000fca00078e00ff */
/*0070*/ LOP3.LUT R2, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307027812 */
/* 0x000fce00078ec0ff */
/*0080*/ @P0 BRA 0x1d0 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff037624 */
/* 0x000fe200078e00ff */
/*00a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*00c0*/ ISETP.GT.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fda0003f24270 */
/*00d0*/ @!P1 BRA 0x140 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*00e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*00f0*/ IADD3 R3, R3, -0x3, RZ ; /* 0xfffffffd03037810 */
/* 0x000fe40007ffe0ff */
/*0100*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GE.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f26270 */
/*0120*/ @!P1 BRA 0x100 ; /* 0xffffffd000009947 */
/* 0x000fea000383ffff */
/*0130*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0140*/ IADD3 R3, -R2, c[0x0][0x160], RZ ; /* 0x0000580002037a10 */
/* 0x000fc80007ffe1ff */
/*0150*/ ISETP.GT.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f24270 */
/*0160*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe20003f0e170 */
/*0170*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff001224 */
/* 0x000fe200078e00ff */
/*0180*/ @P1 IADD3 R2, R2, 0x2, RZ ; /* 0x0000000202021810 */
/* 0x000fd60007ffe0ff */
/*0190*/ ISETP.LT.OR P0, PT, R2, c[0x0][0x160], P0 ; /* 0x0000580002007a0c */
/* 0x000fda0000701670 */
/*01a0*/ @!P0 BRA 0x990 ; /* 0x000007e000008947 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*01c0*/ BRA 0x990 ; /* 0x000007c000007947 */
/* 0x000fea0003800000 */
/*01d0*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*01e0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0200*/ IADD3 R8, -R2, c[0x0][0x170], RZ ; /* 0x00005c0002087a10 */
/* 0x000fe20007ffe1ff */
/*0210*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc600078e00ff */
/*0220*/ ISETP.GT.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f04070 */
/*0230*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fd800078e00ff */
/*0240*/ @P0 BRA 0x4c0 ; /* 0x0000027000000947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R4, -R3, 0x3, RZ ; /* 0x0000000303047810 */
/* 0x000fe20007ffe1ff */
/*0260*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0280*/ IADD3 R4, -R3, 0x4, RZ ; /* 0x0000000403047810 */
/* 0x000fc80007ffe1ff */
/*0290*/ LOP3.LUT R6, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304067812 */
/* 0x000fce00078ec0ff */
/*02a0*/ @!P0 BRA 0x430 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IADD3 R4, RZ, -R6, -R3 ; /* 0x80000006ff047210 */
/* 0x000fe20007ffe803 */
/*02c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*02d0*/ ISETP.GT.AND P0, PT, R4, -0x4, PT ; /* 0xfffffffc0400780c */
/* 0x000fda0003f04270 */
/*02e0*/ @!P0 BRA 0x3f0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*02f0*/ IADD3 R10, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fe40007ffe0ff */
/*0300*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0310*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fda0003f24270 */
/*0320*/ @!P1 BRA 0x380 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0330*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0340*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0350*/ IMAD.U32 R5, R5, 0x10000, RZ ; /* 0x0001000005057824 */
/* 0x000fc600078e00ff */
/*0360*/ ISETP.GT.AND P1, PT, R4, 0x8, PT ; /* 0x000000080400780c */
/* 0x000fda0003f24270 */
/*0370*/ @P1 BRA 0x340 ; /* 0xffffffc000001947 */
/* 0x000fea000383ffff */
/*0380*/ IADD3 R10, R4, 0x4, RZ ; /* 0x00000004040a7810 */
/* 0x000fc80007ffe0ff */
/*0390*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*03a0*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe20003f0e170 */
/*03b0*/ @P1 IMAD.SHL.U32 R5, R5, 0x100, RZ ; /* 0x0000010005051824 */
/* 0x000fe200078e00ff */
/*03c0*/ @P1 IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804041810 */
/* 0x000fd60007ffe0ff */
/*03d0*/ ISETP.NE.OR P0, PT, R4, -0x4, P0 ; /* 0xfffffffc0400780c */
/* 0x000fda0000705670 */
/*03e0*/ @!P0 BRA 0x430 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*03f0*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0400*/ IMAD.SHL.U32 R5, R5, 0x10, RZ ; /* 0x0000001005057824 */
/* 0x000fc600078e00ff */
/*0410*/ ISETP.NE.AND P0, PT, R4, -0x4, PT ; /* 0xfffffffc0400780c */
/* 0x000fda0003f05270 */
/*0420*/ @P0 BRA 0x3f0 ; /* 0xffffffc000000947 */
/* 0x001fea000383ffff */
/*0430*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0440*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x000fd800078e0005 */
/*0450*/ @!P0 BRA 0x4c0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0460*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05270 */
/*0470*/ IMAD.SHL.U32 R4, R5, 0x2, RZ ; /* 0x0000000205047824 */
/* 0x000fd800078e00ff */
/*0480*/ @P0 ISETP.NE.AND P1, PT, R6, 0x2, PT ; /* 0x000000020600080c */
/* 0x000fe20003f25270 */
/*0490*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, 0x2 ; /* 0x00000002ff060424 */
/* 0x000fca00078e00ff */
/*04a0*/ @P0 SEL R6, R6, 0x3, !P1 ; /* 0x0000000306060807 */
/* 0x000fc80004800000 */
/*04b0*/ @P0 SHF.L.U32 R4, R5, R6, RZ ; /* 0x0000000605040219 */
/* 0x000fc800000006ff */
/*04c0*/ ISETP.GE.U32.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x001fe20003f06070 */
/*04d0*/ BSSY B0, 0x960 ; /* 0x0000048000007945 */
/* 0x000fd80003800000 */
/*04e0*/ @!P0 BRA 0x740 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*04f0*/ IADD3 R4, -R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x000fc80007ffe1ff */
/*0500*/ ISETP.GE.U32.AND P0, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fda0003f06070 */
/*0510*/ @!P0 BRA 0x950 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0520*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe20003f06070 */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd800078e00ff */
/*0540*/ @!P0 BRA 0x6b0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0560*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fd400078e0008 */
/*0580*/ @!P0 BRA 0x670 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*05a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*05b0*/ @!P1 BRA 0x610 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*05c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*05d0*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe40007ffe0ff */
/*05e0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fda0003f24270 */
/*0600*/ @P1 BRA 0x5d0 ; /* 0xffffffc000001947 */
/* 0x000fea000383ffff */
/*0610*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0620*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*0630*/ @P1 IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804041810 */
/* 0x000fe40007ffe0ff */
/*0640*/ @P1 IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805051810 */
/* 0x000fd20007ffe0ff */
/*0650*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0660*/ @!P0 BRA 0x6b0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0670*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe40007ffe0ff */
/*0680*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0690*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*06a0*/ @P0 BRA 0x670 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*06c0*/ @!P0 BRA 0x720 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0002 */
/*06e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*06f0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0700*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0710*/ @P0 BRA 0x6e0 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*0720*/ IMAD.IADD R0, R0, 0x1, R5 ; /* 0x0000000100007824 */
/* 0x000fe200078e0205 */
/*0730*/ BRA 0x950 ; /* 0x0000021000007947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe20003f06070 */
/*0750*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fd800078e00ff */
/*0760*/ @!P0 BRA 0x8d0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0780*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0790*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fd400078e0008 */
/*07a0*/ @!P0 BRA 0x890 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*07b0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*07c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*07d0*/ @!P1 BRA 0x830 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*07e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*07f0*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe40007ffe0ff */
/*0800*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe40007ffe0ff */
/*0810*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fda0003f24270 */
/*0820*/ @P1 BRA 0x7f0 ; /* 0xffffffc000001947 */
/* 0x000fea000383ffff */
/*0830*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0840*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*0850*/ @P1 IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804041810 */
/* 0x000fe40007ffe0ff */
/*0860*/ @P1 IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805051810 */
/* 0x000fd20007ffe0ff */
/*0870*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0880*/ @!P0 BRA 0x8d0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0890*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*08c0*/ @P0 BRA 0x890 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*08d0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*08e0*/ @!P0 BRA 0x940 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0002 */
/*0900*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0910*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0920*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0930*/ @P0 BRA 0x900 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*0940*/ IMAD.IADD R0, R0, 0x1, R5 ; /* 0x0000000100007824 */
/* 0x000fe400078e0205 */
/*0950*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0960*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc80007ffe0ff */
/*0970*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0980*/ @!P0 BRA 0x220 ; /* 0xfffff89000008947 */
/* 0x000fea000383ffff */
/*0990*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*09a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*09b0*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*09c0*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0205 */
/*09d0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0003 */
/*09e0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11ctrl_kerneliPii
.globl _Z11ctrl_kerneliPii
.p2align 8
.type _Z11ctrl_kerneliPii,@function
_Z11ctrl_kerneliPii:
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_load_b32 s4, s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_mov_b32 s3, 0
s_mov_b32 s5, 4
s_waitcnt lgkmcnt(0)
s_max_i32 s4, s4, 0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_sub_i32 s7, 32, s6
s_add_i32 s3, s3, 1
v_cmp_le_u32_e32 vcc_lo, s7, v0
s_add_i32 s5, s5, -1
s_cmp_eq_u32 s3, s2
v_cndmask_b32_e64 v2, 0, s4, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v2, s4, vcc_lo
v_add_nc_u32_e32 v1, v1, v2
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_cmp_gt_u32 s3, 3
s_mov_b32 s6, 1
s_cbranch_scc1 .LBB0_2
s_max_i32 s7, s5, 1
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s7, s7, -1
s_lshl_b32 s6, s6, 1
s_cmp_eq_u32 s7, 0
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
v_mov_b32_e32 v1, 0
.LBB0_7:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11ctrl_kerneliPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11ctrl_kerneliPii, .Lfunc_end0-_Z11ctrl_kerneliPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11ctrl_kerneliPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11ctrl_kerneliPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001020b3_00000000-6_ctrl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._Z10gettime_msv,"axG",@progbits,_Z10gettime_msv,comdat
.weak _Z10gettime_msv
.type _Z10gettime_msv, @function
_Z10gettime_msv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
mulsd .LC1(%rip), %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10gettime_msv, .-_Z10gettime_msv
.text
.globl _Z9cost_funci
.type _Z9cost_funci, @function
_Z9cost_funci:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z9cost_funci, .-_Z9cost_funci
.globl _Z33__device_stub__Z11ctrl_kerneliPiiiPii
.type _Z33__device_stub__Z11ctrl_kerneliPiiiPii, @function
_Z33__device_stub__Z11ctrl_kerneliPiiiPii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11ctrl_kerneliPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z11ctrl_kerneliPiiiPii, .-_Z33__device_stub__Z11ctrl_kerneliPiiiPii
.globl _Z11ctrl_kerneliPii
.type _Z11ctrl_kerneliPii, @function
_Z11ctrl_kerneliPii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11ctrl_kerneliPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11ctrl_kerneliPii, .-_Z11ctrl_kerneliPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\nInput arguments wrong!\n input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergence D \n "
.align 8
.LC3:
.string "\nDivergence D has to be between 0~4\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\nkernel starts\n"
.LC5:
.string "\nKernel_Finish_in %f ms\n"
.LC6:
.string "results:\n"
.LC7:
.string "%d "
.LC8:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $7, %edi
je .L18
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L19:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq 48(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
cmpl $4, %eax
ja .L27
movl $1, %edi
call cudaSetDevice@PLT
movl %r12d, %ebx
imull %ebp, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10gettime_msv
movsd %xmm0, 8(%rsp)
movl %r12d, 44(%rsp)
movl $1, 48(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
call cudaDeviceSynchronize@PLT
call _Z10gettime_msv
subsd 8(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 128(%r13), %r12
leaq .LC7(%rip), %rbp
.L22:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L22
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L19
.L27:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L28:
movl %r14d, %edx
movq 24(%rsp), %rsi
movl %r15d, %edi
call _Z33__device_stub__Z11ctrl_kerneliPiiiPii
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z11ctrl_kerneliPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z11ctrl_kerneliPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC1:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ctrl.hip"
.globl _Z26__device_stub__ctrl_kerneliPii # -- Begin function _Z26__device_stub__ctrl_kerneliPii
.p2align 4, 0x90
.type _Z26__device_stub__ctrl_kerneliPii,@function
_Z26__device_stub__ctrl_kerneliPii: # @_Z26__device_stub__ctrl_kerneliPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11ctrl_kerneliPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__ctrl_kerneliPii, .Lfunc_end0-_Z26__device_stub__ctrl_kerneliPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI1_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $7, %edi
jne .LBB1_1
# %bb.2:
movq %rsi, %rbx
movq 40(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 48(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $5, %eax
jb .LBB1_4
# %bb.3:
movl $.Lstr.2, %edi
callq puts@PLT
jmp .LBB1_9
.LBB1_1:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_9
.LBB1_4:
movq %rax, %rbp
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movl $1, %edi
callq hipSetDevice
movl %r12d, %eax
imull %r13d, %eax
movslq %eax, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 16(%rsp), %xmm0
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
mulsd .LCPI1_1(%rip), %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
movl %r13d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq (%rsp), %rax
movl %ebp, 12(%rsp)
movq %rax, 96(%rsp)
movl %r15d, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rax
movq %rax, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11ctrl_kerneliPii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
mulsd .LCPI1_1(%rip), %xmm0
subsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $32, %r14
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
.LBB1_9:
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11ctrl_kerneliPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11ctrl_kerneliPii,@object # @_Z11ctrl_kerneliPii
.section .rodata,"a",@progbits
.globl _Z11ctrl_kerneliPii
.p2align 3, 0x0
_Z11ctrl_kerneliPii:
.quad _Z26__device_stub__ctrl_kerneliPii
.size _Z11ctrl_kerneliPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nInput arguments wrong!\n input: Utilization U, Affinity A, BlockNum B, ThreadsNum T, Cost X, Divergence D \n "
.size .L.str, 110
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nKernel_Finish_in %f ms\n"
.size .L.str.3, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d "
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11ctrl_kerneliPii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nkernel starts"
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "results:"
.size .Lstr.1, 9
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nDivergence D has to be between 0~4"
.size .Lstr.2, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__ctrl_kerneliPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11ctrl_kerneliPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // magictoken.ex_mul_f32_f32.begin
// Foreign function example: multiplication of a pair of floats
extern "C" __device__ int
mul_f32_f32(
float* return_value,
float x,
float y)
{
// Compute result and store in caller-provided slot
*return_value = x * y;
// Signal that no Python exception occurred
return 0;
}
// magictoken.ex_mul_f32_f32.end
// magictoken.ex_sum_reduce_proto.begin
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
);
// magictoken.ex_sum_reduce_proto.end
// Performs a simple reduction on an array passed by pointer using the
// ffi.from_buffer() method. Implements the prototype above.
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
)
{
double sum = 0.0;
for (size_t i = 0; i < n; ++i) {
sum += array[i];
}
*return_value = (float)sum;
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // magictoken.ex_mul_f32_f32.begin
// Foreign function example: multiplication of a pair of floats
extern "C" __device__ int
mul_f32_f32(
float* return_value,
float x,
float y)
{
// Compute result and store in caller-provided slot
*return_value = x * y;
// Signal that no Python exception occurred
return 0;
}
// magictoken.ex_mul_f32_f32.end
// magictoken.ex_sum_reduce_proto.begin
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
);
// magictoken.ex_sum_reduce_proto.end
// Performs a simple reduction on an array passed by pointer using the
// ffi.from_buffer() method. Implements the prototype above.
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
)
{
double sum = 0.0;
for (size_t i = 0; i < n; ++i) {
sum += array[i];
}
*return_value = (float)sum;
return 0;
} | .file "tmpxft_00134d1b_00000000-6_functions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl mul_f32_f32
.type mul_f32_f32, @function
mul_f32_f32:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size mul_f32_f32, .-mul_f32_f32
.globl sum_reduce
.type sum_reduce, @function
sum_reduce:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size sum_reduce, .-sum_reduce
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // magictoken.ex_mul_f32_f32.begin
// Foreign function example: multiplication of a pair of floats
extern "C" __device__ int
mul_f32_f32(
float* return_value,
float x,
float y)
{
// Compute result and store in caller-provided slot
*return_value = x * y;
// Signal that no Python exception occurred
return 0;
}
// magictoken.ex_mul_f32_f32.end
// magictoken.ex_sum_reduce_proto.begin
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
);
// magictoken.ex_sum_reduce_proto.end
// Performs a simple reduction on an array passed by pointer using the
// ffi.from_buffer() method. Implements the prototype above.
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
)
{
double sum = 0.0;
for (size_t i = 0; i < n; ++i) {
sum += array[i];
}
*return_value = (float)sum;
return 0;
} | #include <hip/hip_runtime.h>
// magictoken.ex_mul_f32_f32.begin
// Foreign function example: multiplication of a pair of floats
extern "C" __device__ int
mul_f32_f32(
float* return_value,
float x,
float y)
{
// Compute result and store in caller-provided slot
*return_value = x * y;
// Signal that no Python exception occurred
return 0;
}
// magictoken.ex_mul_f32_f32.end
// magictoken.ex_sum_reduce_proto.begin
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
);
// magictoken.ex_sum_reduce_proto.end
// Performs a simple reduction on an array passed by pointer using the
// ffi.from_buffer() method. Implements the prototype above.
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
)
{
double sum = 0.0;
for (size_t i = 0; i < n; ++i) {
sum += array[i];
}
*return_value = (float)sum;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// magictoken.ex_mul_f32_f32.begin
// Foreign function example: multiplication of a pair of floats
extern "C" __device__ int
mul_f32_f32(
float* return_value,
float x,
float y)
{
// Compute result and store in caller-provided slot
*return_value = x * y;
// Signal that no Python exception occurred
return 0;
}
// magictoken.ex_mul_f32_f32.end
// magictoken.ex_sum_reduce_proto.begin
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
);
// magictoken.ex_sum_reduce_proto.end
// Performs a simple reduction on an array passed by pointer using the
// ffi.from_buffer() method. Implements the prototype above.
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
)
{
double sum = 0.0;
for (size_t i = 0; i < n; ++i) {
sum += array[i];
}
*return_value = (float)sum;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// magictoken.ex_mul_f32_f32.begin
// Foreign function example: multiplication of a pair of floats
extern "C" __device__ int
mul_f32_f32(
float* return_value,
float x,
float y)
{
// Compute result and store in caller-provided slot
*return_value = x * y;
// Signal that no Python exception occurred
return 0;
}
// magictoken.ex_mul_f32_f32.end
// magictoken.ex_sum_reduce_proto.begin
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
);
// magictoken.ex_sum_reduce_proto.end
// Performs a simple reduction on an array passed by pointer using the
// ffi.from_buffer() method. Implements the prototype above.
extern "C"
__device__ int
sum_reduce(
float* return_value,
float* array,
int n
)
{
double sum = 0.0;
for (size_t i = 0; i < n; ++i) {
sum += array[i];
}
*return_value = (float)sum;
return 0;
} | .text
.file "functions.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00134d1b_00000000-6_functions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl mul_f32_f32
.type mul_f32_f32, @function
mul_f32_f32:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size mul_f32_f32, .-mul_f32_f32
.globl sum_reduce
.type sum_reduce, @function
sum_reduce:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size sum_reduce, .-sum_reduce
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "functions.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void EFD_2dBM( int width, int height, int pitch_n, int pitch_npo, float *d_val_n, float *d_val_npo, float alpha, float beta ){
int idx = blockIdx.x; //row
int idy = threadIdx.x; //column
if ((idx < height) && (idy <width)){
//d_val_npo[i] = Pu * d_val_n[i + 1] + Pm * d_val_n[i] + Pd * d_val_n[i - 1];
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = alpha*(d_val_n[(idx + 1)*(pitch_n / sizeof(float)) + idy]
+ d_val_n[(idx - 1)*(pitch_n / sizeof(float)) + idy])
+ beta*(d_val_n[idx*(pitch_n / sizeof(float)) + idy + 1]
+ d_val_n[idx*(pitch_n / sizeof(float)) + idy - 1])
+ (1.0 - 2.0*alpha - 2.0*beta)*d_val_n[idx*(pitch_n / sizeof(float)) + idy];
//modify the ones on the top
if (idx == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx + 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the bottom
if (idx == (height - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the left
if (idy == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy + 1];
}
//modify the ones on the right
if (idx == (width - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy - 1];
}
}
} | code for sm_80
Function : _Z8EFD_2dBMiiiiPfS_ff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x001fc80003f06270 */
/*0040*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x160], P0 ; /* 0x0000580002007a0c */
/* 0x002fda0000706670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IADD3 R9, R5.reuse, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x040fe20007ffe0ff */
/*0080*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR6 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011406 */
/*0090*/ IADD3 R7, R5, -0x1, RZ ; /* 0xffffffff05077810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe20000011402 */
/*00c0*/ USHF.R.U32.HI UR5, URZ, 0x2, UR4 ; /* 0x000000023f057899 */
/* 0x000fe20008011604 */
/*00d0*/ SHF.R.S32.HI R4, RZ, 0x1f, R9 ; /* 0x0000001fff047819 */
/* 0x000fe20000011409 */
/*00e0*/ USHF.R.U64 UR4, UR6, 0x2, UR4 ; /* 0x0000000206047899 */
/* 0x000fe20008001204 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fe40000011405 */
/*0100*/ SHF.R.S32.HI R0, RZ, 0x1f, R7 ; /* 0x0000001fff007819 */
/* 0x000fe20000011407 */
/*0110*/ IMAD R13, R9, UR5, RZ ; /* 0x00000005090d7c24 */
/* 0x000fc4000f8e02ff */
/*0120*/ IMAD R21, R5, UR5, RZ ; /* 0x0000000505157c24 */
/* 0x000fe4000f8e02ff */
/*0130*/ IMAD R15, R7, UR5, RZ ; /* 0x00000005070f7c24 */
/* 0x000fe4000f8e02ff */
/*0140*/ IMAD.WIDE.U32 R18, R9, UR4, R2 ; /* 0x0000000409127c25 */
/* 0x000fc8000f8e0002 */
/*0150*/ IMAD R13, R4, UR4, R13 ; /* 0x00000004040d7c24 */
/* 0x000fe2000f8e020d */
/*0160*/ LEA R20, P0, R18, c[0x0][0x170], 0x2 ; /* 0x00005c0012147a11 */
/* 0x000fe200078010ff */
/*0170*/ IMAD.WIDE.U32 R16, R5, UR4, R2 ; /* 0x0000000405107c25 */
/* 0x000fc8000f8e0002 */
/*0180*/ IMAD R23, R6, UR4, R21 ; /* 0x0000000406177c24 */
/* 0x000fe2000f8e0215 */
/*0190*/ LEA R12, P2, R16, c[0x0][0x170], 0x2 ; /* 0x00005c00100c7a11 */
/* 0x000fe200078410ff */
/*01a0*/ IMAD R21, R0, UR4, R15 ; /* 0x0000000400157c24 */
/* 0x000fe4000f8e020f */
/*01b0*/ IMAD.IADD R15, R19, 0x1, R13 ; /* 0x00000001130f7824 */
/* 0x000fe400078e020d */
/*01c0*/ IMAD.WIDE.U32 R10, R7, UR4, R2 ; /* 0x00000004070a7c25 */
/* 0x000fc8000f8e0002 */
/*01d0*/ IMAD.IADD R13, R17, 0x1, R23 ; /* 0x00000001110d7824 */
/* 0x000fe200078e0217 */
/*01e0*/ LEA R14, P1, R10, c[0x0][0x170], 0x2 ; /* 0x00005c000a0e7a11 */
/* 0x000fe200078210ff */
/*01f0*/ IMAD.IADD R11, R11, 0x1, R21 ; /* 0x000000010b0b7824 */
/* 0x000fe200078e0215 */
/*0200*/ LEA.HI.X R21, R18, c[0x0][0x174], R15, 0x2, P0 ; /* 0x00005d0012157a11 */
/* 0x000fe400000f140f */
/*0210*/ LEA.HI.X R13, R16, c[0x0][0x174], R13, 0x2, P2 ; /* 0x00005d00100d7a11 */
/* 0x000fe400010f140d */
/*0220*/ LEA.HI.X R15, R10, c[0x0][0x174], R11, 0x2, P1 ; /* 0x00005d000a0f7a11 */
/* 0x000fe400008f140b */
/*0230*/ LDG.E R21, [R20.64] ; /* 0x0000000814157981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R8, [R12.64+-0x4] ; /* 0xfffffc080c087981 */
/* 0x0000e8000c1e1900 */
/*0250*/ LDG.E R11, [R12.64+0x4] ; /* 0x000004080c0b7981 */
/* 0x0000e8000c1e1900 */
/*0260*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R10, [R12.64] ; /* 0x000000080c0a7981 */
/* 0x000122000c1e1900 */
/*0280*/ F2F.F64.F32 R18, c[0x0][0x180] ; /* 0x0000600000127b10 */
/* 0x000e620000201800 */
/*0290*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*02a0*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR7 ; /* 0x0000001f3f047899 */
/* 0x000fc80008011407 */
/*02b0*/ USHF.R.U32.HI UR5, URZ, 0x2, UR4 ; /* 0x000000023f057899 */
/* 0x000fe40008011604 */
/*02c0*/ F2F.F64.F32 R16, c[0x0][0x184] ; /* 0x0000610000107b10 */
/* 0x000f620000201800 */
/*02d0*/ USHF.R.U64 UR4, UR7, 0x2, UR4 ; /* 0x0000000207047899 */
/* 0x000fc60008001204 */
/*02e0*/ IMAD R13, R5, UR5, RZ ; /* 0x00000005050d7c24 */
/* 0x001fe2000f8e02ff */
/*02f0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0300*/ DADD R18, R18, R18 ; /* 0x0000000012127229 */
/* 0x002e0c0000000012 */
/*0310*/ DADD R18, -R18, 1 ; /* 0x3ff0000012127429 */
/* 0x001fc80000000100 */
/*0320*/ DADD R16, R16, R16 ; /* 0x0000000010107229 */
/* 0x020e0c0000000010 */
/*0330*/ DADD R16, R18, -R16 ; /* 0x0000000012107229 */
/* 0x0010640000000810 */
/*0340*/ @!P0 IMAD R19, R9, UR5, RZ ; /* 0x0000000509138c24 */
/* 0x001fe4000f8e02ff */
/*0350*/ FADD R22, R8, R11 ; /* 0x0000000b08167221 */
/* 0x008fe40000000000 */
/*0360*/ FADD R8, R14, R21 ; /* 0x000000150e087221 */
/* 0x004fe40000000000 */
/*0370*/ FMUL R23, R22, c[0x0][0x184] ; /* 0x0000610016177a20 */
/* 0x000fe20000400000 */
/*0380*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x010fe60000201800 */
/*0390*/ FFMA R8, R8, c[0x0][0x180], R23 ; /* 0x0000600008087a23 */
/* 0x000fca0000000017 */
/*03a0*/ F2F.F64.F32 R14, R8 ; /* 0x00000008000e7310 */
/* 0x000e640000201800 */
/*03b0*/ DFMA R14, R16, R10, R14 ; /* 0x0000000a100e722b */
/* 0x002064000000000e */
/*03c0*/ IMAD.WIDE.U32 R10, R5, UR4, RZ ; /* 0x00000004050a7c25 */
/* 0x001fc8000f8e00ff */
/*03d0*/ IMAD R17, R6, UR4, R13 ; /* 0x0000000406117c24 */
/* 0x000fe4000f8e020d */
/*03e0*/ @!P0 IMAD.WIDE.U32 R12, R9, UR4, R2 ; /* 0x00000004090c8c25 */
/* 0x000fc8000f8e0002 */
/*03f0*/ @!P0 IMAD R9, R4, UR4, R19 ; /* 0x0000000404098c24 */
/* 0x000fe2000f8e0213 */
/*0400*/ IADD3 R4, P1, R2, R10, RZ ; /* 0x0000000a02047210 */
/* 0x000fe20007f3e0ff */
/*0410*/ F2F.F32.F64 R19, R14 ; /* 0x0000000e00137310 */
/* 0x002e220000301000 */
/*0420*/ IMAD.IADD R11, R11, 0x1, R17 ; /* 0x000000010b0b7824 */
/* 0x000fe200078e0211 */
/*0430*/ @!P0 LEA R16, P3, R12, c[0x0][0x178], 0x2 ; /* 0x00005e000c108a11 */
/* 0x000fe200078610ff */
/*0440*/ @!P0 IMAD.IADD R9, R13, 0x1, R9 ; /* 0x000000010d098824 */
/* 0x000fe200078e0209 */
/*0450*/ LEA R8, P2, R4, c[0x0][0x178], 0x2 ; /* 0x00005e0004087a11 */
/* 0x000fe200078410ff */
/*0460*/ IMAD.X R13, R3, 0x1, R11, P1 ; /* 0x00000001030d7824 */
/* 0x000fc600008e060b */
/*0470*/ @!P0 LEA.HI.X R17, R12, c[0x0][0x17c], R9, 0x2, P3 ; /* 0x00005f000c118a11 */
/* 0x000fe400018f1409 */
/*0480*/ LEA.HI.X R9, R4, c[0x0][0x17c], R13, 0x2, P2 ; /* 0x00005f0004097a11 */
/* 0x000fca00010f140d */
/*0490*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0011e8000c101908 */
/*04a0*/ @!P0 LDG.E R17, [R16.64] ; /* 0x0000000810118981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IMAD R15, R7.reuse, UR5, RZ ; /* 0x00000005070f7c24 */
/* 0x040fe2000f8e02ff */
/*04c0*/ @!P0 LEA R14, P2, R2, c[0x0][0x178], 0x2 ; /* 0x00005e00020e8a11 */
/* 0x000fe200078410ff */
/*04d0*/ IMAD.WIDE.U32 R12, R7, UR4, RZ ; /* 0x00000004070c7c25 */
/* 0x000fc8000f8e00ff */
/*04e0*/ IMAD R15, R0, UR4, R15 ; /* 0x00000004000f7c24 */
/* 0x000fe2000f8e020f */
/*04f0*/ UIADD3 UR4, UR7, -0x1, URZ ; /* 0xffffffff07047890 */
/* 0x000fe2000fffe03f */
/*0500*/ IADD3 R0, P3, R2.reuse, R12, RZ ; /* 0x0000000c02007210 */
/* 0x040fe40007f7e0ff */
/*0510*/ IMAD.IADD R21, R13, 0x1, R15 ; /* 0x000000010d157824 */
/* 0x000fe200078e020f */
/*0520*/ @!P0 LEA.HI.X R15, R2, c[0x0][0x17c], R3, 0x2, P2 ; /* 0x00005f00020f8a11 */
/* 0x000fe400010f1403 */
/*0530*/ ISETP.NE.AND P1, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf25270 */
/*0540*/ IMAD.X R7, R3, 0x1, R21, P3 ; /* 0x0000000103077824 */
/* 0x000fe200018e0615 */
/*0550*/ LEA R6, P4, R0, c[0x0][0x178], 0x2 ; /* 0x00005e0000067a11 */
/* 0x000fc800078810ff */
/*0560*/ LEA.HI.X R7, R0, c[0x0][0x17c], R7, 0x2, P4 ; /* 0x00005f0000077a11 */
/* 0x000fe200020f1407 */
/*0570*/ @!P0 STG.E [R14.64], R17 ; /* 0x000000110e008986 */
/* 0x0041ec000c101908 */
/*0580*/ @!P1 LDG.E R13, [R6.64] ; /* 0x00000008060d9981 */
/* 0x000ea2000c1e1900 */
/*0590*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*05a0*/ @!P0 LEA R2, P2, R12, c[0x0][0x178], 0x2 ; /* 0x00005e000c028a11 */
/* 0x000fc800078410ff */
/*05b0*/ @!P0 LEA.HI.X R3, R12, c[0x0][0x17c], R21, 0x2, P2 ; /* 0x00005f000c038a11 */
/* 0x000fe200010f1415 */
/*05c0*/ @!P1 STG.E [R8.64], R13 ; /* 0x0000000d08009986 */
/* 0x0041ea000c101908 */
/*05d0*/ @!P0 LDG.E R3, [R2.64+0x4] ; /* 0x0000040802038981 */
/* 0x000ea2000c1e1900 */
/*05e0*/ UIADD3 UR4, UR6, -0x1, URZ ; /* 0xffffffff06047890 */
/* 0x000fe2000fffe03f */
/*05f0*/ @!P0 LEA R4, P2, R10, c[0x0][0x178], 0x2 ; /* 0x00005e000a048a11 */
/* 0x000fca00078410ff */
/*0600*/ ISETP.NE.AND P1, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe4000bf25270 */
/*0610*/ @!P0 LEA.HI.X R5, R10, c[0x0][0x17c], R11, 0x2, P2 ; /* 0x00005f000a058a11 */
/* 0x000fca00010f140b */
/*0620*/ @!P0 STG.E [R4.64], R3 ; /* 0x0000000304008986 */
/* 0x0041ec000c101908 */
/*0630*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0640*/ LDG.E R7, [R6.64+-0x4] ; /* 0xfffffc0806077981 */
/* 0x000ea8000c1e1900 */
/*0650*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fe2000c101908 */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ BRA 0x670; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void EFD_2dBM( int width, int height, int pitch_n, int pitch_npo, float *d_val_n, float *d_val_npo, float alpha, float beta ){
int idx = blockIdx.x; //row
int idy = threadIdx.x; //column
if ((idx < height) && (idy <width)){
//d_val_npo[i] = Pu * d_val_n[i + 1] + Pm * d_val_n[i] + Pd * d_val_n[i - 1];
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = alpha*(d_val_n[(idx + 1)*(pitch_n / sizeof(float)) + idy]
+ d_val_n[(idx - 1)*(pitch_n / sizeof(float)) + idy])
+ beta*(d_val_n[idx*(pitch_n / sizeof(float)) + idy + 1]
+ d_val_n[idx*(pitch_n / sizeof(float)) + idy - 1])
+ (1.0 - 2.0*alpha - 2.0*beta)*d_val_n[idx*(pitch_n / sizeof(float)) + idy];
//modify the ones on the top
if (idx == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx + 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the bottom
if (idx == (height - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the left
if (idy == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy + 1];
}
//modify the ones on the right
if (idx == (width - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy - 1];
}
}
} | .file "tmpxft_000ec53d_00000000-6_EFD_2dBM.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff
.type _Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff, @function
_Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8EFD_2dBMiiiiPfS_ff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff, .-_Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff
.globl _Z8EFD_2dBMiiiiPfS_ff
.type _Z8EFD_2dBMiiiiPfS_ff, @function
_Z8EFD_2dBMiiiiPfS_ff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8EFD_2dBMiiiiPfS_ff, .-_Z8EFD_2dBMiiiiPfS_ff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8EFD_2dBMiiiiPfS_ff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8EFD_2dBMiiiiPfS_ff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void EFD_2dBM( int width, int height, int pitch_n, int pitch_npo, float *d_val_n, float *d_val_npo, float alpha, float beta ){
int idx = blockIdx.x; //row
int idy = threadIdx.x; //column
if ((idx < height) && (idy <width)){
//d_val_npo[i] = Pu * d_val_n[i + 1] + Pm * d_val_n[i] + Pd * d_val_n[i - 1];
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = alpha*(d_val_n[(idx + 1)*(pitch_n / sizeof(float)) + idy]
+ d_val_n[(idx - 1)*(pitch_n / sizeof(float)) + idy])
+ beta*(d_val_n[idx*(pitch_n / sizeof(float)) + idy + 1]
+ d_val_n[idx*(pitch_n / sizeof(float)) + idy - 1])
+ (1.0 - 2.0*alpha - 2.0*beta)*d_val_n[idx*(pitch_n / sizeof(float)) + idy];
//modify the ones on the top
if (idx == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx + 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the bottom
if (idx == (height - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the left
if (idy == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy + 1];
}
//modify the ones on the right
if (idx == (width - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy - 1];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void EFD_2dBM( int width, int height, int pitch_n, int pitch_npo, float *d_val_n, float *d_val_npo, float alpha, float beta ){
int idx = blockIdx.x; //row
int idy = threadIdx.x; //column
if ((idx < height) && (idy <width)){
//d_val_npo[i] = Pu * d_val_n[i + 1] + Pm * d_val_n[i] + Pd * d_val_n[i - 1];
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = alpha*(d_val_n[(idx + 1)*(pitch_n / sizeof(float)) + idy]
+ d_val_n[(idx - 1)*(pitch_n / sizeof(float)) + idy])
+ beta*(d_val_n[idx*(pitch_n / sizeof(float)) + idy + 1]
+ d_val_n[idx*(pitch_n / sizeof(float)) + idy - 1])
+ (1.0 - 2.0*alpha - 2.0*beta)*d_val_n[idx*(pitch_n / sizeof(float)) + idy];
//modify the ones on the top
if (idx == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx + 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the bottom
if (idx == (height - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the left
if (idy == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy + 1];
}
//modify the ones on the right
if (idx == (width - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy - 1];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void EFD_2dBM( int width, int height, int pitch_n, int pitch_npo, float *d_val_n, float *d_val_npo, float alpha, float beta ){
int idx = blockIdx.x; //row
int idy = threadIdx.x; //column
if ((idx < height) && (idy <width)){
//d_val_npo[i] = Pu * d_val_n[i + 1] + Pm * d_val_n[i] + Pd * d_val_n[i - 1];
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = alpha*(d_val_n[(idx + 1)*(pitch_n / sizeof(float)) + idy]
+ d_val_n[(idx - 1)*(pitch_n / sizeof(float)) + idy])
+ beta*(d_val_n[idx*(pitch_n / sizeof(float)) + idy + 1]
+ d_val_n[idx*(pitch_n / sizeof(float)) + idy - 1])
+ (1.0 - 2.0*alpha - 2.0*beta)*d_val_n[idx*(pitch_n / sizeof(float)) + idy];
//modify the ones on the top
if (idx == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx + 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the bottom
if (idx == (height - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the left
if (idy == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy + 1];
}
//modify the ones on the right
if (idx == (width - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy - 1];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8EFD_2dBMiiiiPfS_ff
.globl _Z8EFD_2dBMiiiiPfS_ff
.p2align 8
.type _Z8EFD_2dBMiiiiPfS_ff,@function
_Z8EFD_2dBMiiiiPfS_ff:
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_cmp_lt_i32 s15, s9
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_load_b256 s[0:7], s[0:1], 0x8
s_add_i32 s12, s15, 1
s_add_i32 s10, s15, -1
s_ashr_i32 s13, s12, 31
s_ashr_i32 s11, s10, 31
s_waitcnt lgkmcnt(0)
s_ashr_i32 s14, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v4, s14, s0, 2
s_ashr_i32 s0, s15, 31
s_lshr_b32 s14, s14, 2
s_mul_i32 s16, s14, s12
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v1, v4, s13
v_mul_hi_u32 v2, v4, s12
v_mul_lo_u32 v5, v4, s11
v_mul_hi_u32 v6, v4, s10
v_mul_lo_u32 v7, v4, s0
v_mul_hi_u32 v8, v4, s15
s_mul_i32 s17, s14, s10
s_mul_i32 s14, s14, s15
v_mul_lo_u32 v3, v4, s10
v_add_nc_u32_e32 v2, v2, v1
v_mul_lo_u32 v1, v4, s12
v_add_nc_u32_e32 v6, v6, v5
v_mul_lo_u32 v5, v4, s15
v_add_nc_u32_e32 v7, v8, v7
v_add_nc_u32_e32 v2, s16, v2
v_lshlrev_b32_e32 v8, 2, v0
v_add_nc_u32_e32 v4, s17, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, s14, v7
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_readfirstlane_b32 s2, v5
v_readfirstlane_b32 s3, v6
v_readfirstlane_b32 s16, v1
v_readfirstlane_b32 s17, v2
v_readfirstlane_b32 s18, v3
v_readfirstlane_b32 s19, v4
s_clause 0x3
global_load_b64 v[1:2], v8, s[2:3]
global_load_b32 v7, v8, s[2:3] offset:-4
global_load_b32 v9, v8, s[16:17]
global_load_b32 v10, v8, s[18:19]
v_cvt_f64_f32_e32 v[3:4], s6
v_cvt_f64_f32_e32 v[5:6], s7
s_ashr_i32 s3, s1, 31
s_mov_b32 s2, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[3:4], -2.0, 1.0
s_waitcnt vmcnt(0)
v_dual_add_f32 v2, v2, v7 :: v_dual_add_f32 v7, v9, v10
v_mul_f32_e32 v9, s7, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[5:6], -2.0, v[3:4]
v_fmac_f32_e32 v9, s6, v7
v_cvt_f64_f32_e32 v[6:7], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v9
v_fma_f64 v[1:2], v[2:3], v[6:7], v[4:5]
v_alignbit_b32 v3, s3, s1, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v4, v3, s0
v_mul_hi_u32 v5, v3, s15
s_lshr_b32 s0, s3, 2
s_mul_i32 s0, s0, s15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v6, v[1:2]
v_add_nc_u32_e32 v2, v5, v4
v_mul_lo_u32 v1, v3, s15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s0, v2
s_lshr_b64 s[0:1], s[2:3], 2
s_cmp_lg_u32 s15, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s6, v1
v_add_co_u32 v1, vcc_lo, v1, v8
v_readfirstlane_b32 s7, v2
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
global_store_b32 v8, v6, s[6:7]
s_cbranch_scc1 .LBB0_3
s_mul_i32 s2, s0, s13
s_mul_hi_u32 s3, s0, s12
s_mul_i32 s6, s1, s12
s_add_i32 s3, s3, s2
s_mul_i32 s2, s0, s12
s_add_i32 s3, s3, s6
v_lshlrev_b32_e32 v3, 2, v0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
global_load_b32 v3, v3, s[2:3]
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
.LBB0_3:
s_add_i32 s2, s9, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s15, s2
s_cbranch_scc1 .LBB0_5
s_mul_i32 s2, s0, s11
s_mul_hi_u32 s3, s0, s10
s_mul_i32 s6, s1, s10
s_add_i32 s3, s3, s2
s_mul_i32 s2, s0, s10
s_add_i32 s3, s3, s6
v_lshlrev_b32_e32 v3, 2, v0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
global_load_b32 v3, v3, s[2:3]
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
.LBB0_5:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
s_mul_i32 s3, s0, s11
s_mul_hi_u32 s6, s0, s10
s_mul_i32 s7, s1, s10
s_add_i32 s3, s6, s3
s_mul_i32 s6, s0, s10
s_add_i32 s7, s3, s7
v_mov_b32_e32 v3, 0
s_lshl_b64 s[6:7], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s4, s6
s_addc_u32 s7, s5, s7
global_load_b32 v3, v3, s[6:7] offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s2, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s15, s2
s_cbranch_scc1 .LBB0_9
s_mul_i32 s2, s0, s11
s_mul_hi_u32 s3, s0, s10
s_mul_i32 s1, s1, s10
s_add_i32 s2, s3, s2
s_mul_i32 s0, s0, s10
s_add_i32 s1, s2, s1
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
global_load_b32 v0, v0, s[0:1] offset:-4
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8EFD_2dBMiiiiPfS_ff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8EFD_2dBMiiiiPfS_ff, .Lfunc_end0-_Z8EFD_2dBMiiiiPfS_ff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8EFD_2dBMiiiiPfS_ff
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z8EFD_2dBMiiiiPfS_ff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void EFD_2dBM( int width, int height, int pitch_n, int pitch_npo, float *d_val_n, float *d_val_npo, float alpha, float beta ){
int idx = blockIdx.x; //row
int idy = threadIdx.x; //column
if ((idx < height) && (idy <width)){
//d_val_npo[i] = Pu * d_val_n[i + 1] + Pm * d_val_n[i] + Pd * d_val_n[i - 1];
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = alpha*(d_val_n[(idx + 1)*(pitch_n / sizeof(float)) + idy]
+ d_val_n[(idx - 1)*(pitch_n / sizeof(float)) + idy])
+ beta*(d_val_n[idx*(pitch_n / sizeof(float)) + idy + 1]
+ d_val_n[idx*(pitch_n / sizeof(float)) + idy - 1])
+ (1.0 - 2.0*alpha - 2.0*beta)*d_val_n[idx*(pitch_n / sizeof(float)) + idy];
//modify the ones on the top
if (idx == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx + 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the bottom
if (idx == (height - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy];
}
//modify the ones on the left
if (idy == 0){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy + 1];
}
//modify the ones on the right
if (idx == (width - 1)){
d_val_npo[idx*(pitch_npo / sizeof(float)) + idy] = d_val_npo[(idx - 1)*(pitch_npo / sizeof(float)) + idy - 1];
}
}
} | .text
.file "EFD_2dBM.hip"
.globl _Z23__device_stub__EFD_2dBMiiiiPfS_ff # -- Begin function _Z23__device_stub__EFD_2dBMiiiiPfS_ff
.p2align 4, 0x90
.type _Z23__device_stub__EFD_2dBMiiiiPfS_ff,@function
_Z23__device_stub__EFD_2dBMiiiiPfS_ff: # @_Z23__device_stub__EFD_2dBMiiiiPfS_ff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8EFD_2dBMiiiiPfS_ff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z23__device_stub__EFD_2dBMiiiiPfS_ff, .Lfunc_end0-_Z23__device_stub__EFD_2dBMiiiiPfS_ff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8EFD_2dBMiiiiPfS_ff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8EFD_2dBMiiiiPfS_ff,@object # @_Z8EFD_2dBMiiiiPfS_ff
.section .rodata,"a",@progbits
.globl _Z8EFD_2dBMiiiiPfS_ff
.p2align 3, 0x0
_Z8EFD_2dBMiiiiPfS_ff:
.quad _Z23__device_stub__EFD_2dBMiiiiPfS_ff
.size _Z8EFD_2dBMiiiiPfS_ff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8EFD_2dBMiiiiPfS_ff"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__EFD_2dBMiiiiPfS_ff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8EFD_2dBMiiiiPfS_ff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8EFD_2dBMiiiiPfS_ff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x001fc80003f06270 */
/*0040*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x160], P0 ; /* 0x0000580002007a0c */
/* 0x002fda0000706670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IADD3 R9, R5.reuse, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x040fe20007ffe0ff */
/*0080*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR6 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011406 */
/*0090*/ IADD3 R7, R5, -0x1, RZ ; /* 0xffffffff05077810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe20000011402 */
/*00c0*/ USHF.R.U32.HI UR5, URZ, 0x2, UR4 ; /* 0x000000023f057899 */
/* 0x000fe20008011604 */
/*00d0*/ SHF.R.S32.HI R4, RZ, 0x1f, R9 ; /* 0x0000001fff047819 */
/* 0x000fe20000011409 */
/*00e0*/ USHF.R.U64 UR4, UR6, 0x2, UR4 ; /* 0x0000000206047899 */
/* 0x000fe20008001204 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fe40000011405 */
/*0100*/ SHF.R.S32.HI R0, RZ, 0x1f, R7 ; /* 0x0000001fff007819 */
/* 0x000fe20000011407 */
/*0110*/ IMAD R13, R9, UR5, RZ ; /* 0x00000005090d7c24 */
/* 0x000fc4000f8e02ff */
/*0120*/ IMAD R21, R5, UR5, RZ ; /* 0x0000000505157c24 */
/* 0x000fe4000f8e02ff */
/*0130*/ IMAD R15, R7, UR5, RZ ; /* 0x00000005070f7c24 */
/* 0x000fe4000f8e02ff */
/*0140*/ IMAD.WIDE.U32 R18, R9, UR4, R2 ; /* 0x0000000409127c25 */
/* 0x000fc8000f8e0002 */
/*0150*/ IMAD R13, R4, UR4, R13 ; /* 0x00000004040d7c24 */
/* 0x000fe2000f8e020d */
/*0160*/ LEA R20, P0, R18, c[0x0][0x170], 0x2 ; /* 0x00005c0012147a11 */
/* 0x000fe200078010ff */
/*0170*/ IMAD.WIDE.U32 R16, R5, UR4, R2 ; /* 0x0000000405107c25 */
/* 0x000fc8000f8e0002 */
/*0180*/ IMAD R23, R6, UR4, R21 ; /* 0x0000000406177c24 */
/* 0x000fe2000f8e0215 */
/*0190*/ LEA R12, P2, R16, c[0x0][0x170], 0x2 ; /* 0x00005c00100c7a11 */
/* 0x000fe200078410ff */
/*01a0*/ IMAD R21, R0, UR4, R15 ; /* 0x0000000400157c24 */
/* 0x000fe4000f8e020f */
/*01b0*/ IMAD.IADD R15, R19, 0x1, R13 ; /* 0x00000001130f7824 */
/* 0x000fe400078e020d */
/*01c0*/ IMAD.WIDE.U32 R10, R7, UR4, R2 ; /* 0x00000004070a7c25 */
/* 0x000fc8000f8e0002 */
/*01d0*/ IMAD.IADD R13, R17, 0x1, R23 ; /* 0x00000001110d7824 */
/* 0x000fe200078e0217 */
/*01e0*/ LEA R14, P1, R10, c[0x0][0x170], 0x2 ; /* 0x00005c000a0e7a11 */
/* 0x000fe200078210ff */
/*01f0*/ IMAD.IADD R11, R11, 0x1, R21 ; /* 0x000000010b0b7824 */
/* 0x000fe200078e0215 */
/*0200*/ LEA.HI.X R21, R18, c[0x0][0x174], R15, 0x2, P0 ; /* 0x00005d0012157a11 */
/* 0x000fe400000f140f */
/*0210*/ LEA.HI.X R13, R16, c[0x0][0x174], R13, 0x2, P2 ; /* 0x00005d00100d7a11 */
/* 0x000fe400010f140d */
/*0220*/ LEA.HI.X R15, R10, c[0x0][0x174], R11, 0x2, P1 ; /* 0x00005d000a0f7a11 */
/* 0x000fe400008f140b */
/*0230*/ LDG.E R21, [R20.64] ; /* 0x0000000814157981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R8, [R12.64+-0x4] ; /* 0xfffffc080c087981 */
/* 0x0000e8000c1e1900 */
/*0250*/ LDG.E R11, [R12.64+0x4] ; /* 0x000004080c0b7981 */
/* 0x0000e8000c1e1900 */
/*0260*/ LDG.E R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R10, [R12.64] ; /* 0x000000080c0a7981 */
/* 0x000122000c1e1900 */
/*0280*/ F2F.F64.F32 R18, c[0x0][0x180] ; /* 0x0000600000127b10 */
/* 0x000e620000201800 */
/*0290*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*02a0*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR7 ; /* 0x0000001f3f047899 */
/* 0x000fc80008011407 */
/*02b0*/ USHF.R.U32.HI UR5, URZ, 0x2, UR4 ; /* 0x000000023f057899 */
/* 0x000fe40008011604 */
/*02c0*/ F2F.F64.F32 R16, c[0x0][0x184] ; /* 0x0000610000107b10 */
/* 0x000f620000201800 */
/*02d0*/ USHF.R.U64 UR4, UR7, 0x2, UR4 ; /* 0x0000000207047899 */
/* 0x000fc60008001204 */
/*02e0*/ IMAD R13, R5, UR5, RZ ; /* 0x00000005050d7c24 */
/* 0x001fe2000f8e02ff */
/*02f0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0300*/ DADD R18, R18, R18 ; /* 0x0000000012127229 */
/* 0x002e0c0000000012 */
/*0310*/ DADD R18, -R18, 1 ; /* 0x3ff0000012127429 */
/* 0x001fc80000000100 */
/*0320*/ DADD R16, R16, R16 ; /* 0x0000000010107229 */
/* 0x020e0c0000000010 */
/*0330*/ DADD R16, R18, -R16 ; /* 0x0000000012107229 */
/* 0x0010640000000810 */
/*0340*/ @!P0 IMAD R19, R9, UR5, RZ ; /* 0x0000000509138c24 */
/* 0x001fe4000f8e02ff */
/*0350*/ FADD R22, R8, R11 ; /* 0x0000000b08167221 */
/* 0x008fe40000000000 */
/*0360*/ FADD R8, R14, R21 ; /* 0x000000150e087221 */
/* 0x004fe40000000000 */
/*0370*/ FMUL R23, R22, c[0x0][0x184] ; /* 0x0000610016177a20 */
/* 0x000fe20000400000 */
/*0380*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x010fe60000201800 */
/*0390*/ FFMA R8, R8, c[0x0][0x180], R23 ; /* 0x0000600008087a23 */
/* 0x000fca0000000017 */
/*03a0*/ F2F.F64.F32 R14, R8 ; /* 0x00000008000e7310 */
/* 0x000e640000201800 */
/*03b0*/ DFMA R14, R16, R10, R14 ; /* 0x0000000a100e722b */
/* 0x002064000000000e */
/*03c0*/ IMAD.WIDE.U32 R10, R5, UR4, RZ ; /* 0x00000004050a7c25 */
/* 0x001fc8000f8e00ff */
/*03d0*/ IMAD R17, R6, UR4, R13 ; /* 0x0000000406117c24 */
/* 0x000fe4000f8e020d */
/*03e0*/ @!P0 IMAD.WIDE.U32 R12, R9, UR4, R2 ; /* 0x00000004090c8c25 */
/* 0x000fc8000f8e0002 */
/*03f0*/ @!P0 IMAD R9, R4, UR4, R19 ; /* 0x0000000404098c24 */
/* 0x000fe2000f8e0213 */
/*0400*/ IADD3 R4, P1, R2, R10, RZ ; /* 0x0000000a02047210 */
/* 0x000fe20007f3e0ff */
/*0410*/ F2F.F32.F64 R19, R14 ; /* 0x0000000e00137310 */
/* 0x002e220000301000 */
/*0420*/ IMAD.IADD R11, R11, 0x1, R17 ; /* 0x000000010b0b7824 */
/* 0x000fe200078e0211 */
/*0430*/ @!P0 LEA R16, P3, R12, c[0x0][0x178], 0x2 ; /* 0x00005e000c108a11 */
/* 0x000fe200078610ff */
/*0440*/ @!P0 IMAD.IADD R9, R13, 0x1, R9 ; /* 0x000000010d098824 */
/* 0x000fe200078e0209 */
/*0450*/ LEA R8, P2, R4, c[0x0][0x178], 0x2 ; /* 0x00005e0004087a11 */
/* 0x000fe200078410ff */
/*0460*/ IMAD.X R13, R3, 0x1, R11, P1 ; /* 0x00000001030d7824 */
/* 0x000fc600008e060b */
/*0470*/ @!P0 LEA.HI.X R17, R12, c[0x0][0x17c], R9, 0x2, P3 ; /* 0x00005f000c118a11 */
/* 0x000fe400018f1409 */
/*0480*/ LEA.HI.X R9, R4, c[0x0][0x17c], R13, 0x2, P2 ; /* 0x00005f0004097a11 */
/* 0x000fca00010f140d */
/*0490*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0011e8000c101908 */
/*04a0*/ @!P0 LDG.E R17, [R16.64] ; /* 0x0000000810118981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IMAD R15, R7.reuse, UR5, RZ ; /* 0x00000005070f7c24 */
/* 0x040fe2000f8e02ff */
/*04c0*/ @!P0 LEA R14, P2, R2, c[0x0][0x178], 0x2 ; /* 0x00005e00020e8a11 */
/* 0x000fe200078410ff */
/*04d0*/ IMAD.WIDE.U32 R12, R7, UR4, RZ ; /* 0x00000004070c7c25 */
/* 0x000fc8000f8e00ff */
/*04e0*/ IMAD R15, R0, UR4, R15 ; /* 0x00000004000f7c24 */
/* 0x000fe2000f8e020f */
/*04f0*/ UIADD3 UR4, UR7, -0x1, URZ ; /* 0xffffffff07047890 */
/* 0x000fe2000fffe03f */
/*0500*/ IADD3 R0, P3, R2.reuse, R12, RZ ; /* 0x0000000c02007210 */
/* 0x040fe40007f7e0ff */
/*0510*/ IMAD.IADD R21, R13, 0x1, R15 ; /* 0x000000010d157824 */
/* 0x000fe200078e020f */
/*0520*/ @!P0 LEA.HI.X R15, R2, c[0x0][0x17c], R3, 0x2, P2 ; /* 0x00005f00020f8a11 */
/* 0x000fe400010f1403 */
/*0530*/ ISETP.NE.AND P1, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf25270 */
/*0540*/ IMAD.X R7, R3, 0x1, R21, P3 ; /* 0x0000000103077824 */
/* 0x000fe200018e0615 */
/*0550*/ LEA R6, P4, R0, c[0x0][0x178], 0x2 ; /* 0x00005e0000067a11 */
/* 0x000fc800078810ff */
/*0560*/ LEA.HI.X R7, R0, c[0x0][0x17c], R7, 0x2, P4 ; /* 0x00005f0000077a11 */
/* 0x000fe200020f1407 */
/*0570*/ @!P0 STG.E [R14.64], R17 ; /* 0x000000110e008986 */
/* 0x0041ec000c101908 */
/*0580*/ @!P1 LDG.E R13, [R6.64] ; /* 0x00000008060d9981 */
/* 0x000ea2000c1e1900 */
/*0590*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*05a0*/ @!P0 LEA R2, P2, R12, c[0x0][0x178], 0x2 ; /* 0x00005e000c028a11 */
/* 0x000fc800078410ff */
/*05b0*/ @!P0 LEA.HI.X R3, R12, c[0x0][0x17c], R21, 0x2, P2 ; /* 0x00005f000c038a11 */
/* 0x000fe200010f1415 */
/*05c0*/ @!P1 STG.E [R8.64], R13 ; /* 0x0000000d08009986 */
/* 0x0041ea000c101908 */
/*05d0*/ @!P0 LDG.E R3, [R2.64+0x4] ; /* 0x0000040802038981 */
/* 0x000ea2000c1e1900 */
/*05e0*/ UIADD3 UR4, UR6, -0x1, URZ ; /* 0xffffffff06047890 */
/* 0x000fe2000fffe03f */
/*05f0*/ @!P0 LEA R4, P2, R10, c[0x0][0x178], 0x2 ; /* 0x00005e000a048a11 */
/* 0x000fca00078410ff */
/*0600*/ ISETP.NE.AND P1, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe4000bf25270 */
/*0610*/ @!P0 LEA.HI.X R5, R10, c[0x0][0x17c], R11, 0x2, P2 ; /* 0x00005f000a058a11 */
/* 0x000fca00010f140b */
/*0620*/ @!P0 STG.E [R4.64], R3 ; /* 0x0000000304008986 */
/* 0x0041ec000c101908 */
/*0630*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0640*/ LDG.E R7, [R6.64+-0x4] ; /* 0xfffffc0806077981 */
/* 0x000ea8000c1e1900 */
/*0650*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fe2000c101908 */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ BRA 0x670; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8EFD_2dBMiiiiPfS_ff
.globl _Z8EFD_2dBMiiiiPfS_ff
.p2align 8
.type _Z8EFD_2dBMiiiiPfS_ff,@function
_Z8EFD_2dBMiiiiPfS_ff:
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_cmp_lt_i32 s15, s9
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_load_b256 s[0:7], s[0:1], 0x8
s_add_i32 s12, s15, 1
s_add_i32 s10, s15, -1
s_ashr_i32 s13, s12, 31
s_ashr_i32 s11, s10, 31
s_waitcnt lgkmcnt(0)
s_ashr_i32 s14, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v4, s14, s0, 2
s_ashr_i32 s0, s15, 31
s_lshr_b32 s14, s14, 2
s_mul_i32 s16, s14, s12
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v1, v4, s13
v_mul_hi_u32 v2, v4, s12
v_mul_lo_u32 v5, v4, s11
v_mul_hi_u32 v6, v4, s10
v_mul_lo_u32 v7, v4, s0
v_mul_hi_u32 v8, v4, s15
s_mul_i32 s17, s14, s10
s_mul_i32 s14, s14, s15
v_mul_lo_u32 v3, v4, s10
v_add_nc_u32_e32 v2, v2, v1
v_mul_lo_u32 v1, v4, s12
v_add_nc_u32_e32 v6, v6, v5
v_mul_lo_u32 v5, v4, s15
v_add_nc_u32_e32 v7, v8, v7
v_add_nc_u32_e32 v2, s16, v2
v_lshlrev_b32_e32 v8, 2, v0
v_add_nc_u32_e32 v4, s17, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, s14, v7
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_readfirstlane_b32 s2, v5
v_readfirstlane_b32 s3, v6
v_readfirstlane_b32 s16, v1
v_readfirstlane_b32 s17, v2
v_readfirstlane_b32 s18, v3
v_readfirstlane_b32 s19, v4
s_clause 0x3
global_load_b64 v[1:2], v8, s[2:3]
global_load_b32 v7, v8, s[2:3] offset:-4
global_load_b32 v9, v8, s[16:17]
global_load_b32 v10, v8, s[18:19]
v_cvt_f64_f32_e32 v[3:4], s6
v_cvt_f64_f32_e32 v[5:6], s7
s_ashr_i32 s3, s1, 31
s_mov_b32 s2, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[3:4], -2.0, 1.0
s_waitcnt vmcnt(0)
v_dual_add_f32 v2, v2, v7 :: v_dual_add_f32 v7, v9, v10
v_mul_f32_e32 v9, s7, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[5:6], -2.0, v[3:4]
v_fmac_f32_e32 v9, s6, v7
v_cvt_f64_f32_e32 v[6:7], v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[4:5], v9
v_fma_f64 v[1:2], v[2:3], v[6:7], v[4:5]
v_alignbit_b32 v3, s3, s1, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v4, v3, s0
v_mul_hi_u32 v5, v3, s15
s_lshr_b32 s0, s3, 2
s_mul_i32 s0, s0, s15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v6, v[1:2]
v_add_nc_u32_e32 v2, v5, v4
v_mul_lo_u32 v1, v3, s15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s0, v2
s_lshr_b64 s[0:1], s[2:3], 2
s_cmp_lg_u32 s15, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s6, v1
v_add_co_u32 v1, vcc_lo, v1, v8
v_readfirstlane_b32 s7, v2
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
global_store_b32 v8, v6, s[6:7]
s_cbranch_scc1 .LBB0_3
s_mul_i32 s2, s0, s13
s_mul_hi_u32 s3, s0, s12
s_mul_i32 s6, s1, s12
s_add_i32 s3, s3, s2
s_mul_i32 s2, s0, s12
s_add_i32 s3, s3, s6
v_lshlrev_b32_e32 v3, 2, v0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
global_load_b32 v3, v3, s[2:3]
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
.LBB0_3:
s_add_i32 s2, s9, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s15, s2
s_cbranch_scc1 .LBB0_5
s_mul_i32 s2, s0, s11
s_mul_hi_u32 s3, s0, s10
s_mul_i32 s6, s1, s10
s_add_i32 s3, s3, s2
s_mul_i32 s2, s0, s10
s_add_i32 s3, s3, s6
v_lshlrev_b32_e32 v3, 2, v0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
global_load_b32 v3, v3, s[2:3]
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
.LBB0_5:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
s_mul_i32 s3, s0, s11
s_mul_hi_u32 s6, s0, s10
s_mul_i32 s7, s1, s10
s_add_i32 s3, s6, s3
s_mul_i32 s6, s0, s10
s_add_i32 s7, s3, s7
v_mov_b32_e32 v3, 0
s_lshl_b64 s[6:7], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s4, s6
s_addc_u32 s7, s5, s7
global_load_b32 v3, v3, s[6:7] offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s2, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s15, s2
s_cbranch_scc1 .LBB0_9
s_mul_i32 s2, s0, s11
s_mul_hi_u32 s3, s0, s10
s_mul_i32 s1, s1, s10
s_add_i32 s2, s3, s2
s_mul_i32 s0, s0, s10
s_add_i32 s1, s2, s1
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
global_load_b32 v0, v0, s[0:1] offset:-4
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8EFD_2dBMiiiiPfS_ff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8EFD_2dBMiiiiPfS_ff, .Lfunc_end0-_Z8EFD_2dBMiiiiPfS_ff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8EFD_2dBMiiiiPfS_ff
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z8EFD_2dBMiiiiPfS_ff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ec53d_00000000-6_EFD_2dBM.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff
.type _Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff, @function
_Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8EFD_2dBMiiiiPfS_ff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff, .-_Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff
.globl _Z8EFD_2dBMiiiiPfS_ff
.type _Z8EFD_2dBMiiiiPfS_ff, @function
_Z8EFD_2dBMiiiiPfS_ff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8EFD_2dBMiiiiPfS_ffiiiiPfS_ff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8EFD_2dBMiiiiPfS_ff, .-_Z8EFD_2dBMiiiiPfS_ff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8EFD_2dBMiiiiPfS_ff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8EFD_2dBMiiiiPfS_ff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "EFD_2dBM.hip"
.globl _Z23__device_stub__EFD_2dBMiiiiPfS_ff # -- Begin function _Z23__device_stub__EFD_2dBMiiiiPfS_ff
.p2align 4, 0x90
.type _Z23__device_stub__EFD_2dBMiiiiPfS_ff,@function
_Z23__device_stub__EFD_2dBMiiiiPfS_ff: # @_Z23__device_stub__EFD_2dBMiiiiPfS_ff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8EFD_2dBMiiiiPfS_ff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z23__device_stub__EFD_2dBMiiiiPfS_ff, .Lfunc_end0-_Z23__device_stub__EFD_2dBMiiiiPfS_ff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8EFD_2dBMiiiiPfS_ff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8EFD_2dBMiiiiPfS_ff,@object # @_Z8EFD_2dBMiiiiPfS_ff
.section .rodata,"a",@progbits
.globl _Z8EFD_2dBMiiiiPfS_ff
.p2align 3, 0x0
_Z8EFD_2dBMiiiiPfS_ff:
.quad _Z23__device_stub__EFD_2dBMiiiiPfS_ff
.size _Z8EFD_2dBMiiiiPfS_ff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8EFD_2dBMiiiiPfS_ff"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__EFD_2dBMiiiiPfS_ff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8EFD_2dBMiiiiPfS_ff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // https://devblogs.nvidia.com/even-easier-introduction-cuda
// https://devblogs.nvidia.com/unified-memory-cuda-beginners
#include <iostream>
#include <math.h>
// cuda kernel
__global__
void add(size_t num_elements, const float* x, float* result)
{
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
size_t stride = blockDim.x * gridDim.x;
for (size_t i = index; i < num_elements; i += stride)
{
result[i] += x[i];
}
}
int main()
{
const size_t num_elements = 1 << 20; // 1M elements
float* x;
float* y;
cudaMallocManaged(&x, num_elements * sizeof(float));
cudaMallocManaged(&y, num_elements * sizeof(float));
for (size_t i = 0; i < num_elements; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
// prefetch data to GPU
int device = -1;
cudaGetDevice(&device);
cudaMemPrefetchAsync(x, num_elements * sizeof(float), device, NULL);
cudaMemPrefetchAsync(y, num_elements * sizeof(float), device, NULL);
size_t block_size = 256;
size_t num_blocks = (num_elements + block_size - 1) / block_size;
// run kernel on GPU
add<<<num_blocks, block_size>>>(num_elements, x, y);
// wait for GPU to finish
cudaDeviceSynchronize();
float max_error = 0.0f;
for (size_t i = 0; i < num_elements; i++)
{
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
cudaFree(x);
cudaFree(y);
} | code for sm_80
Function : _Z3addmPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0000 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.SHL.U32 R4, R6.reuse, 0x4, RZ ; /* 0x0000000406047824 */
/* 0x040fe200078e00ff */
/*00c0*/ SHF.L.U64.HI R0, R6, 0x2, R9 ; /* 0x0000000206007819 */
/* 0x000fc80000010209 */
/*00d0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x170], RZ ; /* 0x00005c0004027a10 */
/* 0x041fe40007f1e0ff */
/*00e0*/ IADD3 R4, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe40007f3e0ff */
/*00f0*/ IADD3.X R3, R0.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000037a10 */
/* 0x040fe400007fe4ff */
/*0100*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x000fc60000ffe4ff */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD R11, R8, c[0x0][0xc], RZ ; /* 0x00000300080b7a24 */
/* 0x000fca00078e02ff */
/*0140*/ IADD3 R6, P0, R11, R6, RZ ; /* 0x000000060b067210 */
/* 0x000fca0007f1e0ff */
/*0150*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fc80003f06070 */
/*0170*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x164], PT, P0 ; /* 0x0000590009007a0c */
/* 0x000fe20003f06100 */
/*0180*/ FADD R7, R0, R5 ; /* 0x0000000500077221 */
/* 0x004fca0000000000 */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ee000c101904 */
/*01a0*/ @!P0 BRA 0xb0 ; /* 0xffffff0000008947 */
/* 0x000fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // https://devblogs.nvidia.com/even-easier-introduction-cuda
// https://devblogs.nvidia.com/unified-memory-cuda-beginners
#include <iostream>
#include <math.h>
// cuda kernel
__global__
void add(size_t num_elements, const float* x, float* result)
{
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
size_t stride = blockDim.x * gridDim.x;
for (size_t i = index; i < num_elements; i += stride)
{
result[i] += x[i];
}
}
int main()
{
const size_t num_elements = 1 << 20; // 1M elements
float* x;
float* y;
cudaMallocManaged(&x, num_elements * sizeof(float));
cudaMallocManaged(&y, num_elements * sizeof(float));
for (size_t i = 0; i < num_elements; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
// prefetch data to GPU
int device = -1;
cudaGetDevice(&device);
cudaMemPrefetchAsync(x, num_elements * sizeof(float), device, NULL);
cudaMemPrefetchAsync(y, num_elements * sizeof(float), device, NULL);
size_t block_size = 256;
size_t num_blocks = (num_elements + block_size - 1) / block_size;
// run kernel on GPU
add<<<num_blocks, block_size>>>(num_elements, x, y);
// wait for GPU to finish
cudaDeviceSynchronize();
float max_error = 0.0f;
for (size_t i = 0; i < num_elements; i++)
{
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
cudaFree(x);
cudaFree(y);
} | .file "tmpxft_0010548c_00000000-6_add_arrays.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addmPKfPfmPKfPf
.type _Z26__device_stub__Z3addmPKfPfmPKfPf, @function
_Z26__device_stub__Z3addmPKfPfmPKfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addmPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3addmPKfPfmPKfPf, .-_Z26__device_stub__Z3addmPKfPfmPKfPf
.globl _Z3addmPKfPf
.type _Z3addmPKfPf, @function
_Z3addmPKfPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addmPKfPfmPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addmPKfPf, .-_Z3addmPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 32(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 40(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $-1, 28(%rsp)
leaq 28(%rsp), %rdi
call cudaGetDevice@PLT
movl $0, %ecx
movl 28(%rsp), %edx
movl $4194304, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl 28(%rsp), %edx
movl $4194304, %esi
movq 40(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4096, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movl $1048576, %edi
call _Z26__device_stub__Z3addmPKfPfmPKfPf
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addmPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addmPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // https://devblogs.nvidia.com/even-easier-introduction-cuda
// https://devblogs.nvidia.com/unified-memory-cuda-beginners
#include <iostream>
#include <math.h>
// cuda kernel
__global__
void add(size_t num_elements, const float* x, float* result)
{
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
size_t stride = blockDim.x * gridDim.x;
for (size_t i = index; i < num_elements; i += stride)
{
result[i] += x[i];
}
}
int main()
{
const size_t num_elements = 1 << 20; // 1M elements
float* x;
float* y;
cudaMallocManaged(&x, num_elements * sizeof(float));
cudaMallocManaged(&y, num_elements * sizeof(float));
for (size_t i = 0; i < num_elements; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
// prefetch data to GPU
int device = -1;
cudaGetDevice(&device);
cudaMemPrefetchAsync(x, num_elements * sizeof(float), device, NULL);
cudaMemPrefetchAsync(y, num_elements * sizeof(float), device, NULL);
size_t block_size = 256;
size_t num_blocks = (num_elements + block_size - 1) / block_size;
// run kernel on GPU
add<<<num_blocks, block_size>>>(num_elements, x, y);
// wait for GPU to finish
cudaDeviceSynchronize();
float max_error = 0.0f;
for (size_t i = 0; i < num_elements; i++)
{
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
cudaFree(x);
cudaFree(y);
} | // https://devblogs.nvidia.com/even-easier-introduction-cuda
// https://devblogs.nvidia.com/unified-memory-cuda-beginners
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// cuda kernel
__global__
void add(size_t num_elements, const float* x, float* result)
{
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
size_t stride = blockDim.x * gridDim.x;
for (size_t i = index; i < num_elements; i += stride)
{
result[i] += x[i];
}
}
int main()
{
const size_t num_elements = 1 << 20; // 1M elements
float* x;
float* y;
hipMallocManaged(&x, num_elements * sizeof(float));
hipMallocManaged(&y, num_elements * sizeof(float));
for (size_t i = 0; i < num_elements; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
// prefetch data to GPU
int device = -1;
hipGetDevice(&device);
hipMemPrefetchAsync(x, num_elements * sizeof(float), device, NULL);
hipMemPrefetchAsync(y, num_elements * sizeof(float), device, NULL);
size_t block_size = 256;
size_t num_blocks = (num_elements + block_size - 1) / block_size;
// run kernel on GPU
add<<<num_blocks, block_size>>>(num_elements, x, y);
// wait for GPU to finish
hipDeviceSynchronize();
float max_error = 0.0f;
for (size_t i = 0; i < num_elements; i++)
{
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
hipFree(x);
hipFree(y);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // https://devblogs.nvidia.com/even-easier-introduction-cuda
// https://devblogs.nvidia.com/unified-memory-cuda-beginners
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// cuda kernel
__global__
void add(size_t num_elements, const float* x, float* result)
{
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
size_t stride = blockDim.x * gridDim.x;
for (size_t i = index; i < num_elements; i += stride)
{
result[i] += x[i];
}
}
int main()
{
const size_t num_elements = 1 << 20; // 1M elements
float* x;
float* y;
hipMallocManaged(&x, num_elements * sizeof(float));
hipMallocManaged(&y, num_elements * sizeof(float));
for (size_t i = 0; i < num_elements; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
// prefetch data to GPU
int device = -1;
hipGetDevice(&device);
hipMemPrefetchAsync(x, num_elements * sizeof(float), device, NULL);
hipMemPrefetchAsync(y, num_elements * sizeof(float), device, NULL);
size_t block_size = 256;
size_t num_blocks = (num_elements + block_size - 1) / block_size;
// run kernel on GPU
add<<<num_blocks, block_size>>>(num_elements, x, y);
// wait for GPU to finish
hipDeviceSynchronize();
float max_error = 0.0f;
for (size_t i = 0; i < num_elements; i++)
{
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
hipFree(x);
hipFree(y);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addmPKfPf
.globl _Z3addmPKfPf
.p2align 8
.type _Z3addmPKfPf,@function
_Z3addmPKfPf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s9
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s10, s8
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v3, s0, v3, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s0, s11, v4, s0
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v5
global_store_b32 v[7:8], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addmPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addmPKfPf, .Lfunc_end0-_Z3addmPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addmPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addmPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // https://devblogs.nvidia.com/even-easier-introduction-cuda
// https://devblogs.nvidia.com/unified-memory-cuda-beginners
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// cuda kernel
__global__
void add(size_t num_elements, const float* x, float* result)
{
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
size_t stride = blockDim.x * gridDim.x;
for (size_t i = index; i < num_elements; i += stride)
{
result[i] += x[i];
}
}
int main()
{
const size_t num_elements = 1 << 20; // 1M elements
float* x;
float* y;
hipMallocManaged(&x, num_elements * sizeof(float));
hipMallocManaged(&y, num_elements * sizeof(float));
for (size_t i = 0; i < num_elements; i++)
{
x[i] = 1.0f;
y[i] = 2.0f;
}
// prefetch data to GPU
int device = -1;
hipGetDevice(&device);
hipMemPrefetchAsync(x, num_elements * sizeof(float), device, NULL);
hipMemPrefetchAsync(y, num_elements * sizeof(float), device, NULL);
size_t block_size = 256;
size_t num_blocks = (num_elements + block_size - 1) / block_size;
// run kernel on GPU
add<<<num_blocks, block_size>>>(num_elements, x, y);
// wait for GPU to finish
hipDeviceSynchronize();
float max_error = 0.0f;
for (size_t i = 0; i < num_elements; i++)
{
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
hipFree(x);
hipFree(y);
} | .text
.file "add_arrays.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addmPKfPf # -- Begin function _Z18__device_stub__addmPKfPf
.p2align 4, 0x90
.type _Z18__device_stub__addmPKfPf,@function
_Z18__device_stub__addmPKfPf: # @_Z18__device_stub__addmPKfPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addmPKfPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addmPKfPf, .Lfunc_end0-_Z18__device_stub__addmPKfPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movl $-1, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDevice
movq 16(%rsp), %rdi
movl 4(%rsp), %edx
movl $4194304, %esi # imm = 0x400000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 8(%rsp), %rdi
movl 4(%rsp), %edx
movl $4194304, %esi # imm = 0x400000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq $1048576, 88(%rsp) # imm = 0x100000
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addmPKfPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addmPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addmPKfPf,@object # @_Z3addmPKfPf
.section .rodata,"a",@progbits
.globl _Z3addmPKfPf
.p2align 3, 0x0
_Z3addmPKfPf:
.quad _Z18__device_stub__addmPKfPf
.size _Z3addmPKfPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addmPKfPf"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addmPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addmPKfPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addmPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x164], PT, P0 ; /* 0x00005900ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0000 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.SHL.U32 R4, R6.reuse, 0x4, RZ ; /* 0x0000000406047824 */
/* 0x040fe200078e00ff */
/*00c0*/ SHF.L.U64.HI R0, R6, 0x2, R9 ; /* 0x0000000206007819 */
/* 0x000fc80000010209 */
/*00d0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x170], RZ ; /* 0x00005c0004027a10 */
/* 0x041fe40007f1e0ff */
/*00e0*/ IADD3 R4, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe40007f3e0ff */
/*00f0*/ IADD3.X R3, R0.reuse, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000037a10 */
/* 0x040fe400007fe4ff */
/*0100*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x000fc60000ffe4ff */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD R11, R8, c[0x0][0xc], RZ ; /* 0x00000300080b7a24 */
/* 0x000fca00078e02ff */
/*0140*/ IADD3 R6, P0, R11, R6, RZ ; /* 0x000000060b067210 */
/* 0x000fca0007f1e0ff */
/*0150*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fc80003f06070 */
/*0170*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x164], PT, P0 ; /* 0x0000590009007a0c */
/* 0x000fe20003f06100 */
/*0180*/ FADD R7, R0, R5 ; /* 0x0000000500077221 */
/* 0x004fca0000000000 */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ee000c101904 */
/*01a0*/ @!P0 BRA 0xb0 ; /* 0xffffff0000008947 */
/* 0x000fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addmPKfPf
.globl _Z3addmPKfPf
.p2align 8
.type _Z3addmPKfPf,@function
_Z3addmPKfPf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[4:5], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mov_b32 s1, s9
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s10, s8
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v3, s0, v3, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s0, s11, v4, s0
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v5
global_store_b32 v[7:8], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addmPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addmPKfPf, .Lfunc_end0-_Z3addmPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addmPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addmPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010548c_00000000-6_add_arrays.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addmPKfPfmPKfPf
.type _Z26__device_stub__Z3addmPKfPfmPKfPf, @function
_Z26__device_stub__Z3addmPKfPfmPKfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addmPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3addmPKfPfmPKfPf, .-_Z26__device_stub__Z3addmPKfPfmPKfPf
.globl _Z3addmPKfPf
.type _Z3addmPKfPf, @function
_Z3addmPKfPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addmPKfPfmPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addmPKfPf, .-_Z3addmPKfPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 32(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 40(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $-1, 28(%rsp)
leaq 28(%rsp), %rdi
call cudaGetDevice@PLT
movl $0, %ecx
movl 28(%rsp), %edx
movl $4194304, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl 28(%rsp), %edx
movl $4194304, %esi
movq 40(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4096, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movq 40(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movl $1048576, %edi
call _Z26__device_stub__Z3addmPKfPfmPKfPf
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addmPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addmPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_arrays.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addmPKfPf # -- Begin function _Z18__device_stub__addmPKfPf
.p2align 4, 0x90
.type _Z18__device_stub__addmPKfPf,@function
_Z18__device_stub__addmPKfPf: # @_Z18__device_stub__addmPKfPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addmPKfPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addmPKfPf, .Lfunc_end0-_Z18__device_stub__addmPKfPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movl $-1, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDevice
movq 16(%rsp), %rdi
movl 4(%rsp), %edx
movl $4194304, %esi # imm = 0x400000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 8(%rsp), %rdi
movl 4(%rsp), %edx
movl $4194304, %esi # imm = 0x400000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq $1048576, 88(%rsp) # imm = 0x100000
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addmPKfPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addmPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addmPKfPf,@object # @_Z3addmPKfPf
.section .rodata,"a",@progbits
.globl _Z3addmPKfPf
.p2align 3, 0x0
_Z3addmPKfPf:
.quad _Z18__device_stub__addmPKfPf
.size _Z3addmPKfPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addmPKfPf"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addmPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addmPKfPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <sys/time.h>
const int MAXTILE = 32;
__global__ void gpu_mult_kernel(int* A, int* B, int* C, const int n)
{
// determine access location based on block ids and threadids
int i = blockIdx.y * blockDim.y + threadIdx.y; // row
int j = blockIdx.x * blockDim.x + threadIdx.x; // col
for (int k = 0; k < n; k++)
{
// each thread responsible for one cell in C
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
};
__global__ void sgpu_mult_kernel(int* A, int* B, int* C, const int n, const int b)
{
__shared__ int sharedA[MAXTILE][MAXTILE];
__shared__ int sharedB[MAXTILE][MAXTILE];
int i = (blockIdx.y * b) + threadIdx.y; // row
int j = (blockIdx.x * b) + threadIdx.x; // col
// for each tiled section
int ntile = n / b;
for (int t = 0; t < ntile; t++)
{
// copy data to for this shared tiles (each thread works to acheive this goal)
sharedA[threadIdx.y][threadIdx.x] = A[i * n + (t * b + threadIdx.x)];
sharedB[threadIdx.y][threadIdx.x] = B[(t * b + threadIdx.y) * n + j];
// synchronize to ensure shared tiles are updated by all threads
__syncthreads();
// calculate the values for the tile section
for (int k = 0; k < b; k++)
{
// each thread responsible for one cell in C
C[i * n + j] += sharedA[threadIdx.y][k] * sharedB[k][threadIdx.x];
}
// synchronize before moving to next tile (prevents premature changes to shared memory)
__syncthreads();
}
};
void cpu_mult(int n, int* A, int* B, int* C);
int* allocate_matrix(int n);
void randomize_matrix(int n, int* A);
void print_matrix(int n, int* A);
bool equal_matrix(int n, int* A, int* B);
double rtclock();
int main(int argc, char * argv[])
{
if (argc != 2)
{
printf("Error: Missing argument");
return 0;
}
srand(time(NULL));
int n = atoi(argv[1]);
int m = n * n * sizeof(int);
if (n < 1)
{
printf("Error: Invalid Matrix Size");
return 0;
}
int b = 1;
if (n <= MAXTILE)
{
b = n;
}
else
{
b = MAXTILE;
while (b > 1 && n % b != 0) // while b is not a factor of n
{
b--;
}
}
int *X, *Y, *Zcpu, *Zgpu, *Zsgpu;
int *X_d, *Y_d, *Zgpu_d, *Zsgpu_d;
double start, end;
allocate_matrix(n);
X = allocate_matrix(n);
Y = allocate_matrix(n);
Zcpu = allocate_matrix(n);
Zgpu = allocate_matrix(n);
Zsgpu = allocate_matrix(n);
randomize_matrix(n, X);
randomize_matrix(n, Y);
// print X
//print_matrix(n, X);
//print_matrix(n, Y);
start = rtclock();
cpu_mult(n, X, Y, Zcpu);
end = rtclock();
printf("CPU time:\t%f\n", end - start);
//print_matrix(n, Zcpu);
// allocate memory on gpu
cudaMalloc((void **)&X_d, m);
cudaMalloc((void **)&Y_d, m);
// copy host data to gpu
cudaMemcpy(X_d, X, m, cudaMemcpyHostToDevice);
cudaMemcpy(Y_d, Y, m, cudaMemcpyHostToDevice);
// kernel parameters
dim3 dimGrid(n / b, n / b, 1);
dim3 dimBlock(b, b, 1);
// run kernels
start = rtclock();
cudaMalloc((void **)&Zgpu_d, m);
cudaMemcpy(Zgpu_d, Zgpu, m, cudaMemcpyHostToDevice);
gpu_mult_kernel <<<dimGrid, dimBlock>>> (X_d, Y_d, Zgpu_d, n);
cudaMemcpy(Zgpu, Zgpu_d, m, cudaMemcpyDeviceToHost);
end = rtclock();
printf("GPU time:\t%f\n", end - start);
start = rtclock();
cudaMalloc((void **)&Zsgpu_d, m);
cudaMemcpy(Zsgpu_d, Zsgpu, m, cudaMemcpyHostToDevice);
sgpu_mult_kernel <<<dimGrid, dimBlock>>> (X_d, Y_d, Zsgpu_d, n, b);
cudaMemcpy(Zsgpu, Zsgpu_d, m, cudaMemcpyDeviceToHost);
end = rtclock();
printf("sGPU time:\t%f\n", end - start);
//print_matrix(n, Zgpu);
//print_matrix(n, Zsgpu);
printf("Zcpu == Zgpu? %s\n", equal_matrix(n, Zcpu, Zgpu) ? "true" : "false");
printf("Zcpu == Zsgpu? %s\n", equal_matrix(n, Zcpu, Zsgpu) ? "true" : "false");
}
void cpu_mult(int n, int* A, int* B, int* C)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
for (int k = 0; k < n; k++)
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
int* allocate_matrix(int n)
{
int* A = (int *)malloc(n * n * sizeof(int*));
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
A[i * n + j] = 0;
return A;
}
void randomize_matrix(int n, int * A)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
A[i * n + j] = rand() % 10;
}
void print_matrix(int n, int* A)
{
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
printf("%4d ", A[i * n + j]);
printf("\n");
}
printf("\n");
}
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0)
{
printf("Error return from gettimeofday: %d\n", stat);
}
return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
bool equal_matrix(int n, int* A, int* B)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
{
int index = i * n + j;
if (A[index] != B[index])
return false;
}
return true;
} | .file "tmpxft_001b49b8_00000000-6_MatrixMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8cpu_multiPiS_S_
.type _Z8cpu_multiPiS_S_, @function
_Z8cpu_multiPiS_S_:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L11
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %ebx
movq %rsi, %r8
movq %rdx, %r13
movq %rcx, %rbp
movslq %edi, %rdi
salq $2, %rdi
movq %rsi, %r11
addq %rdi, %r8
movl $0, %r12d
movl $0, %r14d
jmp .L5
.L7:
leal 1(%r12), %eax
addq %rdi, %r11
addq %rdi, %r8
addq %rdi, %rbp
cmpl %r10d, %r12d
je .L3
movl %eax, %r12d
.L5:
movq %r13, %r9
movq %rbp, %rsi
movl %r14d, %r10d
.L8:
movq %r9, %rcx
movq %r11, %rax
.L6:
movl (%rax), %edx
imull (%rcx), %edx
addl %edx, (%rsi)
addq $4, %rax
addq %rdi, %rcx
cmpq %r8, %rax
jne .L6
leal 1(%r10), %eax
addq $4, %r9
addq $4, %rsi
cmpl %eax, %ebx
je .L7
movl %eax, %r10d
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2058:
.size _Z8cpu_multiPiS_S_, .-_Z8cpu_multiPiS_S_
.globl _Z15allocate_matrixi
.type _Z15allocate_matrixi, @function
_Z15allocate_matrixi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
imull %edi, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
testl %ebx, %ebx
jle .L14
movslq %ebx, %rdi
leaq 0(,%rdi,4), %r8
leaq (%rax,%r8), %rcx
negq %rdi
salq $2, %rdi
movl $0, %esi
.L16:
leaq (%rcx,%rdi), %rdx
.L17:
movl $0, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L17
addl $1, %esi
addq %r8, %rcx
cmpl %esi, %ebx
jne .L16
.L14:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z15allocate_matrixi, .-_Z15allocate_matrixi
.globl _Z16randomize_matrixiPi
.type _Z16randomize_matrixiPi, @function
_Z16randomize_matrixiPi:
.LFB2060:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L26
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %edi, %r14d
movslq %edi, %r13
leaq 0(,%r13,4), %r15
leaq (%rsi,%r15), %rbp
negq %r13
salq $2, %r13
movl $0, %r12d
.L22:
leaq 0(%rbp,%r13), %rbx
.L23:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L23
addl $1, %r12d
addq %r15, %rbp
cmpl %r12d, %r14d
jne .L22
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2060:
.size _Z16randomize_matrixiPi, .-_Z16randomize_matrixiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%4d "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixiPi
.type _Z12print_matrixiPi, @function
_Z12print_matrixiPi:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
testl %edi, %edi
jle .L30
movslq %edi, %r14
leaq 0(,%r14,4), %r15
leaq (%rsi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC0(%rip), %r12
.L31:
leaq 0(%rbp,%r14), %rbx
.L32:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L32
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L31
.L30:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z12print_matrixiPi, .-_Z12print_matrixiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Error return from gettimeofday: %d\n"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2062:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L39
.L36:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC3(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L36
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z7rtclockv, .-_Z7rtclockv
.globl _Z12equal_matrixiPiS_
.type _Z12equal_matrixiPiS_, @function
_Z12equal_matrixiPiS_:
.LFB2063:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L45
movslq %edi, %rax
leaq 0(,%rax,4), %r10
negq %rax
leaq 0(,%rax,4), %r8
movq %r10, %rcx
movl $0, %r9d
.L43:
leaq (%rcx,%r8), %rax
.L44:
movl (%rdx,%rax), %r11d
cmpl %r11d, (%rsi,%rax)
jne .L46
addq $4, %rax
cmpq %rcx, %rax
jne .L44
addl $1, %r9d
addq %r10, %rcx
cmpl %r9d, %edi
jne .L43
movl $1, %eax
ret
.L45:
movl $1, %eax
ret
.L46:
movl $0, %eax
ret
.cfi_endproc
.LFE2063:
.size _Z12equal_matrixiPiS_, .-_Z12equal_matrixiPiS_
.globl _Z40__device_stub__Z15gpu_mult_kernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15gpu_mult_kernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15gpu_mult_kernelPiS_S_iPiS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15gpu_mult_kernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z40__device_stub__Z15gpu_mult_kernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15gpu_mult_kernelPiS_S_iPiS_S_i
.globl _Z15gpu_mult_kernelPiS_S_i
.type _Z15gpu_mult_kernelPiS_S_i, @function
_Z15gpu_mult_kernelPiS_S_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15gpu_mult_kernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z15gpu_mult_kernelPiS_S_i, .-_Z15gpu_mult_kernelPiS_S_i
.globl _Z42__device_stub__Z16sgpu_mult_kernelPiS_S_iiPiS_S_ii
.type _Z42__device_stub__Z16sgpu_mult_kernelPiS_S_iiPiS_S_ii, @function
_Z42__device_stub__Z16sgpu_mult_kernelPiS_S_iiPiS_S_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L61
.L57:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16sgpu_mult_kernelPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L57
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z42__device_stub__Z16sgpu_mult_kernelPiS_S_iiPiS_S_ii, .-_Z42__device_stub__Z16sgpu_mult_kernelPiS_S_iiPiS_S_ii
.globl _Z16sgpu_mult_kernelPiS_S_ii
.type _Z16sgpu_mult_kernelPiS_S_ii, @function
_Z16sgpu_mult_kernelPiS_S_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z16sgpu_mult_kernelPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z16sgpu_mult_kernelPiS_S_ii, .-_Z16sgpu_mult_kernelPiS_S_ii
.section .rodata.str1.1
.LC4:
.string "true"
.LC5:
.string "false"
.LC6:
.string "Error: Missing argument"
.LC7:
.string "Error: Invalid Matrix Size"
.LC8:
.string "CPU time:\t%f\n"
.LC9:
.string "GPU time:\t%f\n"
.LC10:
.string "sGPU time:\t%f\n"
.LC11:
.string "Zcpu == Zgpu? %s\n"
.LC12:
.string "Zcpu == Zsgpu? %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L66
leaq .LC6(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L67:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L82
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore_state
movq %rsi, %rbx
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
movl %eax, %edx
imull %eax, %edx
leal 0(,%rdx,4), %r12d
testl %eax, %eax
jle .L83
movl %eax, %ebx
cmpl $32, %eax
jle .L69
testb $31, %al
je .L77
movl $32, %ebx
.L70:
subl $1, %ebx
cmpl $1, %ebx
je .L69
movl %ebp, %eax
cltd
idivl %ebx
testl %edx, %edx
jne .L70
.L69:
movl %ebp, %edi
call _Z15allocate_matrixi
movl %ebp, %edi
call _Z15allocate_matrixi
movq %rax, %r15
movl %ebp, %edi
call _Z15allocate_matrixi
movq %rax, %r14
movl %ebp, %edi
call _Z15allocate_matrixi
movq %rax, 8(%rsp)
movl %ebp, %edi
call _Z15allocate_matrixi
movq %rax, %r13
movl %ebp, %edi
call _Z15allocate_matrixi
movq %rax, 16(%rsp)
movq %r15, %rsi
movl %ebp, %edi
call _Z16randomize_matrixiPi
movq %r14, %rsi
movl %ebp, %edi
call _Z16randomize_matrixiPi
call _Z7rtclockv
movsd %xmm0, 24(%rsp)
movq 8(%rsp), %rcx
movq %r14, %rdx
movq %r15, %rsi
movl %ebp, %edi
call _Z8cpu_multiPiS_S_
call _Z7rtclockv
subsd 24(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %r12d, %r12
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, %eax
cltd
idivl %ebx
movl %eax, 64(%rsp)
movl %eax, 68(%rsp)
movl $1, 72(%rsp)
movl %ebx, 76(%rsp)
movl %ebx, 80(%rsp)
movl $1, 84(%rsp)
call _Z7rtclockv
movsd %xmm0, 24(%rsp)
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L71:
movl $2, %ecx
movq %r12, %rdx
movq 48(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call _Z7rtclockv
subsd 24(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z7rtclockv
movsd %xmm0, 24(%rsp)
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl 84(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movq 64(%rsp), %rdi
movl 72(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L72:
movl $2, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 16(%rsp), %r14
movq %r14, %rdi
call cudaMemcpy@PLT
call _Z7rtclockv
subsd 24(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdx
movq 8(%rsp), %rbx
movq %rbx, %rsi
movl %ebp, %edi
call _Z12equal_matrixiPiS_
testb %al, %al
leaq .LC5(%rip), %rdx
leaq .LC4(%rip), %rax
cmovne %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdx
movq %rbx, %rsi
movl %ebp, %edi
call _Z12equal_matrixiPiS_
testb %al, %al
leaq .LC5(%rip), %rdx
leaq .LC4(%rip), %rax
cmovne %rax, %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L67
.L83:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L67
.L77:
movl $32, %ebx
jmp .L69
.L84:
movl %ebp, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z40__device_stub__Z15gpu_mult_kernelPiS_S_iPiS_S_i
jmp .L71
.L85:
movl %ebx, %r8d
movl %ebp, %ecx
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z42__device_stub__Z16sgpu_mult_kernelPiS_S_iiPiS_S_ii
jmp .L72
.L82:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z16sgpu_mult_kernelPiS_S_ii"
.LC14:
.string "_Z15gpu_mult_kernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z16sgpu_mult_kernelPiS_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z15gpu_mult_kernelPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <sys/time.h>
const int MAXTILE = 32;
__global__ void gpu_mult_kernel(int* A, int* B, int* C, const int n)
{
// determine access location based on block ids and threadids
int i = blockIdx.y * blockDim.y + threadIdx.y; // row
int j = blockIdx.x * blockDim.x + threadIdx.x; // col
for (int k = 0; k < n; k++)
{
// each thread responsible for one cell in C
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
};
__global__ void sgpu_mult_kernel(int* A, int* B, int* C, const int n, const int b)
{
__shared__ int sharedA[MAXTILE][MAXTILE];
__shared__ int sharedB[MAXTILE][MAXTILE];
int i = (blockIdx.y * b) + threadIdx.y; // row
int j = (blockIdx.x * b) + threadIdx.x; // col
// for each tiled section
int ntile = n / b;
for (int t = 0; t < ntile; t++)
{
// copy data to for this shared tiles (each thread works to acheive this goal)
sharedA[threadIdx.y][threadIdx.x] = A[i * n + (t * b + threadIdx.x)];
sharedB[threadIdx.y][threadIdx.x] = B[(t * b + threadIdx.y) * n + j];
// synchronize to ensure shared tiles are updated by all threads
__syncthreads();
// calculate the values for the tile section
for (int k = 0; k < b; k++)
{
// each thread responsible for one cell in C
C[i * n + j] += sharedA[threadIdx.y][k] * sharedB[k][threadIdx.x];
}
// synchronize before moving to next tile (prevents premature changes to shared memory)
__syncthreads();
}
};
void cpu_mult(int n, int* A, int* B, int* C);
int* allocate_matrix(int n);
void randomize_matrix(int n, int* A);
void print_matrix(int n, int* A);
bool equal_matrix(int n, int* A, int* B);
double rtclock();
int main(int argc, char * argv[])
{
if (argc != 2)
{
printf("Error: Missing argument");
return 0;
}
srand(time(NULL));
int n = atoi(argv[1]);
int m = n * n * sizeof(int);
if (n < 1)
{
printf("Error: Invalid Matrix Size");
return 0;
}
int b = 1;
if (n <= MAXTILE)
{
b = n;
}
else
{
b = MAXTILE;
while (b > 1 && n % b != 0) // while b is not a factor of n
{
b--;
}
}
int *X, *Y, *Zcpu, *Zgpu, *Zsgpu;
int *X_d, *Y_d, *Zgpu_d, *Zsgpu_d;
double start, end;
allocate_matrix(n);
X = allocate_matrix(n);
Y = allocate_matrix(n);
Zcpu = allocate_matrix(n);
Zgpu = allocate_matrix(n);
Zsgpu = allocate_matrix(n);
randomize_matrix(n, X);
randomize_matrix(n, Y);
// print X
//print_matrix(n, X);
//print_matrix(n, Y);
start = rtclock();
cpu_mult(n, X, Y, Zcpu);
end = rtclock();
printf("CPU time:\t%f\n", end - start);
//print_matrix(n, Zcpu);
// allocate memory on gpu
cudaMalloc((void **)&X_d, m);
cudaMalloc((void **)&Y_d, m);
// copy host data to gpu
cudaMemcpy(X_d, X, m, cudaMemcpyHostToDevice);
cudaMemcpy(Y_d, Y, m, cudaMemcpyHostToDevice);
// kernel parameters
dim3 dimGrid(n / b, n / b, 1);
dim3 dimBlock(b, b, 1);
// run kernels
start = rtclock();
cudaMalloc((void **)&Zgpu_d, m);
cudaMemcpy(Zgpu_d, Zgpu, m, cudaMemcpyHostToDevice);
gpu_mult_kernel <<<dimGrid, dimBlock>>> (X_d, Y_d, Zgpu_d, n);
cudaMemcpy(Zgpu, Zgpu_d, m, cudaMemcpyDeviceToHost);
end = rtclock();
printf("GPU time:\t%f\n", end - start);
start = rtclock();
cudaMalloc((void **)&Zsgpu_d, m);
cudaMemcpy(Zsgpu_d, Zsgpu, m, cudaMemcpyHostToDevice);
sgpu_mult_kernel <<<dimGrid, dimBlock>>> (X_d, Y_d, Zsgpu_d, n, b);
cudaMemcpy(Zsgpu, Zsgpu_d, m, cudaMemcpyDeviceToHost);
end = rtclock();
printf("sGPU time:\t%f\n", end - start);
//print_matrix(n, Zgpu);
//print_matrix(n, Zsgpu);
printf("Zcpu == Zgpu? %s\n", equal_matrix(n, Zcpu, Zgpu) ? "true" : "false");
printf("Zcpu == Zsgpu? %s\n", equal_matrix(n, Zcpu, Zsgpu) ? "true" : "false");
}
void cpu_mult(int n, int* A, int* B, int* C)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
for (int k = 0; k < n; k++)
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
int* allocate_matrix(int n)
{
int* A = (int *)malloc(n * n * sizeof(int*));
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
A[i * n + j] = 0;
return A;
}
void randomize_matrix(int n, int * A)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
A[i * n + j] = rand() % 10;
}
void print_matrix(int n, int* A)
{
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
printf("%4d ", A[i * n + j]);
printf("\n");
}
printf("\n");
}
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0)
{
printf("Error return from gettimeofday: %d\n", stat);
}
return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
bool equal_matrix(int n, int* A, int* B)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
{
int index = i * n + j;
if (A[index] != B[index])
return false;
}
return true;
} | #include <hip/hip_runtime.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <sys/time.h>
const int MAXTILE = 32;
__global__ void gpu_mult_kernel(int* A, int* B, int* C, const int n)
{
// determine access location based on block ids and threadids
int i = blockIdx.y * blockDim.y + threadIdx.y; // row
int j = blockIdx.x * blockDim.x + threadIdx.x; // col
for (int k = 0; k < n; k++)
{
// each thread responsible for one cell in C
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
};
__global__ void sgpu_mult_kernel(int* A, int* B, int* C, const int n, const int b)
{
__shared__ int sharedA[MAXTILE][MAXTILE];
__shared__ int sharedB[MAXTILE][MAXTILE];
int i = (blockIdx.y * b) + threadIdx.y; // row
int j = (blockIdx.x * b) + threadIdx.x; // col
// for each tiled section
int ntile = n / b;
for (int t = 0; t < ntile; t++)
{
// copy data to for this shared tiles (each thread works to acheive this goal)
sharedA[threadIdx.y][threadIdx.x] = A[i * n + (t * b + threadIdx.x)];
sharedB[threadIdx.y][threadIdx.x] = B[(t * b + threadIdx.y) * n + j];
// synchronize to ensure shared tiles are updated by all threads
__syncthreads();
// calculate the values for the tile section
for (int k = 0; k < b; k++)
{
// each thread responsible for one cell in C
C[i * n + j] += sharedA[threadIdx.y][k] * sharedB[k][threadIdx.x];
}
// synchronize before moving to next tile (prevents premature changes to shared memory)
__syncthreads();
}
};
void cpu_mult(int n, int* A, int* B, int* C);
int* allocate_matrix(int n);
void randomize_matrix(int n, int* A);
void print_matrix(int n, int* A);
bool equal_matrix(int n, int* A, int* B);
double rtclock();
int main(int argc, char * argv[])
{
if (argc != 2)
{
printf("Error: Missing argument");
return 0;
}
srand(time(NULL));
int n = atoi(argv[1]);
int m = n * n * sizeof(int);
if (n < 1)
{
printf("Error: Invalid Matrix Size");
return 0;
}
int b = 1;
if (n <= MAXTILE)
{
b = n;
}
else
{
b = MAXTILE;
while (b > 1 && n % b != 0) // while b is not a factor of n
{
b--;
}
}
int *X, *Y, *Zcpu, *Zgpu, *Zsgpu;
int *X_d, *Y_d, *Zgpu_d, *Zsgpu_d;
double start, end;
allocate_matrix(n);
X = allocate_matrix(n);
Y = allocate_matrix(n);
Zcpu = allocate_matrix(n);
Zgpu = allocate_matrix(n);
Zsgpu = allocate_matrix(n);
randomize_matrix(n, X);
randomize_matrix(n, Y);
// print X
//print_matrix(n, X);
//print_matrix(n, Y);
start = rtclock();
cpu_mult(n, X, Y, Zcpu);
end = rtclock();
printf("CPU time:\t%f\n", end - start);
//print_matrix(n, Zcpu);
// allocate memory on gpu
hipMalloc((void **)&X_d, m);
hipMalloc((void **)&Y_d, m);
// copy host data to gpu
hipMemcpy(X_d, X, m, hipMemcpyHostToDevice);
hipMemcpy(Y_d, Y, m, hipMemcpyHostToDevice);
// kernel parameters
dim3 dimGrid(n / b, n / b, 1);
dim3 dimBlock(b, b, 1);
// run kernels
start = rtclock();
hipMalloc((void **)&Zgpu_d, m);
hipMemcpy(Zgpu_d, Zgpu, m, hipMemcpyHostToDevice);
gpu_mult_kernel <<<dimGrid, dimBlock>>> (X_d, Y_d, Zgpu_d, n);
hipMemcpy(Zgpu, Zgpu_d, m, hipMemcpyDeviceToHost);
end = rtclock();
printf("GPU time:\t%f\n", end - start);
start = rtclock();
hipMalloc((void **)&Zsgpu_d, m);
hipMemcpy(Zsgpu_d, Zsgpu, m, hipMemcpyHostToDevice);
sgpu_mult_kernel <<<dimGrid, dimBlock>>> (X_d, Y_d, Zsgpu_d, n, b);
hipMemcpy(Zsgpu, Zsgpu_d, m, hipMemcpyDeviceToHost);
end = rtclock();
printf("sGPU time:\t%f\n", end - start);
//print_matrix(n, Zgpu);
//print_matrix(n, Zsgpu);
printf("Zcpu == Zgpu? %s\n", equal_matrix(n, Zcpu, Zgpu) ? "true" : "false");
printf("Zcpu == Zsgpu? %s\n", equal_matrix(n, Zcpu, Zsgpu) ? "true" : "false");
}
void cpu_mult(int n, int* A, int* B, int* C)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
for (int k = 0; k < n; k++)
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
int* allocate_matrix(int n)
{
int* A = (int *)malloc(n * n * sizeof(int*));
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
A[i * n + j] = 0;
return A;
}
void randomize_matrix(int n, int * A)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
A[i * n + j] = rand() % 10;
}
void print_matrix(int n, int* A)
{
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
printf("%4d ", A[i * n + j]);
printf("\n");
}
printf("\n");
}
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0)
{
printf("Error return from gettimeofday: %d\n", stat);
}
return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
bool equal_matrix(int n, int* A, int* B)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
{
int index = i * n + j;
if (A[index] != B[index])
return false;
}
return true;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <sys/time.h>
const int MAXTILE = 32;
__global__ void gpu_mult_kernel(int* A, int* B, int* C, const int n)
{
// determine access location based on block ids and threadids
int i = blockIdx.y * blockDim.y + threadIdx.y; // row
int j = blockIdx.x * blockDim.x + threadIdx.x; // col
for (int k = 0; k < n; k++)
{
// each thread responsible for one cell in C
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
};
__global__ void sgpu_mult_kernel(int* A, int* B, int* C, const int n, const int b)
{
__shared__ int sharedA[MAXTILE][MAXTILE];
__shared__ int sharedB[MAXTILE][MAXTILE];
int i = (blockIdx.y * b) + threadIdx.y; // row
int j = (blockIdx.x * b) + threadIdx.x; // col
// for each tiled section
int ntile = n / b;
for (int t = 0; t < ntile; t++)
{
// copy data to for this shared tiles (each thread works to acheive this goal)
sharedA[threadIdx.y][threadIdx.x] = A[i * n + (t * b + threadIdx.x)];
sharedB[threadIdx.y][threadIdx.x] = B[(t * b + threadIdx.y) * n + j];
// synchronize to ensure shared tiles are updated by all threads
__syncthreads();
// calculate the values for the tile section
for (int k = 0; k < b; k++)
{
// each thread responsible for one cell in C
C[i * n + j] += sharedA[threadIdx.y][k] * sharedB[k][threadIdx.x];
}
// synchronize before moving to next tile (prevents premature changes to shared memory)
__syncthreads();
}
};
void cpu_mult(int n, int* A, int* B, int* C);
int* allocate_matrix(int n);
void randomize_matrix(int n, int* A);
void print_matrix(int n, int* A);
bool equal_matrix(int n, int* A, int* B);
double rtclock();
int main(int argc, char * argv[])
{
if (argc != 2)
{
printf("Error: Missing argument");
return 0;
}
srand(time(NULL));
int n = atoi(argv[1]);
int m = n * n * sizeof(int);
if (n < 1)
{
printf("Error: Invalid Matrix Size");
return 0;
}
int b = 1;
if (n <= MAXTILE)
{
b = n;
}
else
{
b = MAXTILE;
while (b > 1 && n % b != 0) // while b is not a factor of n
{
b--;
}
}
int *X, *Y, *Zcpu, *Zgpu, *Zsgpu;
int *X_d, *Y_d, *Zgpu_d, *Zsgpu_d;
double start, end;
allocate_matrix(n);
X = allocate_matrix(n);
Y = allocate_matrix(n);
Zcpu = allocate_matrix(n);
Zgpu = allocate_matrix(n);
Zsgpu = allocate_matrix(n);
randomize_matrix(n, X);
randomize_matrix(n, Y);
// print X
//print_matrix(n, X);
//print_matrix(n, Y);
start = rtclock();
cpu_mult(n, X, Y, Zcpu);
end = rtclock();
printf("CPU time:\t%f\n", end - start);
//print_matrix(n, Zcpu);
// allocate memory on gpu
hipMalloc((void **)&X_d, m);
hipMalloc((void **)&Y_d, m);
// copy host data to gpu
hipMemcpy(X_d, X, m, hipMemcpyHostToDevice);
hipMemcpy(Y_d, Y, m, hipMemcpyHostToDevice);
// kernel parameters
dim3 dimGrid(n / b, n / b, 1);
dim3 dimBlock(b, b, 1);
// run kernels
start = rtclock();
hipMalloc((void **)&Zgpu_d, m);
hipMemcpy(Zgpu_d, Zgpu, m, hipMemcpyHostToDevice);
gpu_mult_kernel <<<dimGrid, dimBlock>>> (X_d, Y_d, Zgpu_d, n);
hipMemcpy(Zgpu, Zgpu_d, m, hipMemcpyDeviceToHost);
end = rtclock();
printf("GPU time:\t%f\n", end - start);
start = rtclock();
hipMalloc((void **)&Zsgpu_d, m);
hipMemcpy(Zsgpu_d, Zsgpu, m, hipMemcpyHostToDevice);
sgpu_mult_kernel <<<dimGrid, dimBlock>>> (X_d, Y_d, Zsgpu_d, n, b);
hipMemcpy(Zsgpu, Zsgpu_d, m, hipMemcpyDeviceToHost);
end = rtclock();
printf("sGPU time:\t%f\n", end - start);
//print_matrix(n, Zgpu);
//print_matrix(n, Zsgpu);
printf("Zcpu == Zgpu? %s\n", equal_matrix(n, Zcpu, Zgpu) ? "true" : "false");
printf("Zcpu == Zsgpu? %s\n", equal_matrix(n, Zcpu, Zsgpu) ? "true" : "false");
}
void cpu_mult(int n, int* A, int* B, int* C)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
for (int k = 0; k < n; k++)
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
int* allocate_matrix(int n)
{
int* A = (int *)malloc(n * n * sizeof(int*));
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
A[i * n + j] = 0;
return A;
}
void randomize_matrix(int n, int * A)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
A[i * n + j] = rand() % 10;
}
void print_matrix(int n, int* A)
{
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
printf("%4d ", A[i * n + j]);
printf("\n");
}
printf("\n");
}
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0)
{
printf("Error return from gettimeofday: %d\n", stat);
}
return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
bool equal_matrix(int n, int* A, int* B)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
{
int index = i * n + j;
if (A[index] != B[index])
return false;
}
return true;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15gpu_mult_kernelPiS_S_i
.globl _Z15gpu_mult_kernelPiS_S_i
.p2align 8
.type _Z15gpu_mult_kernelPiS_S_i,@function
_Z15gpu_mult_kernelPiS_S_i:
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s2, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
v_mad_u64_u32 v[0:1], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v2, s4
s_load_b64 s[2:3], s[0:1], 0x10
v_add_nc_u32_e32 v1, v4, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v6, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s0, s4
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v9, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, v1, v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v7
global_store_b32 v[2:3], v7, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15gpu_mult_kernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15gpu_mult_kernelPiS_S_i, .Lfunc_end0-_Z15gpu_mult_kernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16sgpu_mult_kernelPiS_S_ii
.globl _Z16sgpu_mult_kernelPiS_S_ii
.p2align 8
.type _Z16sgpu_mult_kernelPiS_S_ii,@function
_Z16sgpu_mult_kernelPiS_S_ii:
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s3, 31
s_ashr_i32 s8, s2, 31
s_add_i32 s5, s3, s4
s_add_i32 s9, s2, s8
s_xor_b32 s5, s5, s4
s_xor_b32 s9, s9, s8
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s7, 0, s5
s_xor_b32 s4, s8, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s6, v1
s_mul_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s6, s7
s_add_i32 s6, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s9, s6
s_mul_i32 s7, s6, s5
s_add_i32 s8, s6, 1
s_sub_i32 s7, s9, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s7, s5
s_cmp_ge_u32 s7, s5
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s5
s_mov_b32 s9, 0
s_cselect_b32 s5, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
s_sub_i32 s8, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB1_7
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_cmp_gt_i32 s3, 0
v_mad_u64_u32 v[4:5], null, s15, s3, v[1:2]
v_mad_u64_u32 v[2:3], null, s14, s3, v[0:1]
v_lshlrev_b32_e32 v7, 2, v0
s_cselect_b32 s0, -1, 0
v_lshlrev_b32_e32 v9, 7, v1
v_cndmask_b32_e64 v8, 0, 1, s0
v_mul_lo_u32 v3, v4, s2
v_or_b32_e32 v10, 0x1000, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v11, v9, v7
v_cmp_ne_u32_e64 s0, 1, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, v10, v9
v_add_nc_u32_e32 v5, v3, v2
v_add_nc_u32_e32 v13, v3, v0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s10, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
s_branch .LBB1_3
.LBB1_2:
s_add_i32 s9, s9, 1
s_waitcnt_vscnt null, 0x0
s_cmp_eq_u32 s9, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
.LBB1_3:
s_mul_i32 s1, s9, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s1, v1
v_add_nc_u32_e32 v3, s1, v13
v_mad_u64_u32 v[7:8], null, v0, s2, v[2:3]
v_mov_b32_e32 v8, v4
v_lshlrev_b64 v[14:15], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v14, vcc_lo, s4, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_and_b32 vcc_lo, exec_lo, s0
global_load_b32 v0, v[14:15], off
global_load_b32 v3, v[7:8], off
s_waitcnt vmcnt(1)
ds_store_b32 v11, v0
s_waitcnt vmcnt(0)
ds_store_b32 v12, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB1_2
global_load_b32 v0, v[5:6], off
v_dual_mov_b32 v3, v10 :: v_dual_mov_b32 v14, v9
s_mov_b32 s1, s3
.LBB1_5:
ds_load_b32 v15, v14
ds_load_b32 v16, v3
v_add_nc_u32_e32 v14, 4, v14
s_add_i32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s1, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[7:8], null, v16, v15, v[0:1]
v_dual_mov_b32 v0, v7 :: v_dual_add_nc_u32 v3, 0x80, v3
s_cbranch_scc0 .LBB1_5
global_store_b32 v[5:6], v7, off
s_branch .LBB1_2
.LBB1_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16sgpu_mult_kernelPiS_S_ii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16sgpu_mult_kernelPiS_S_ii, .Lfunc_end1-_Z16sgpu_mult_kernelPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15gpu_mult_kernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15gpu_mult_kernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16sgpu_mult_kernelPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16sgpu_mult_kernelPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <sys/time.h>
const int MAXTILE = 32;
__global__ void gpu_mult_kernel(int* A, int* B, int* C, const int n)
{
// determine access location based on block ids and threadids
int i = blockIdx.y * blockDim.y + threadIdx.y; // row
int j = blockIdx.x * blockDim.x + threadIdx.x; // col
for (int k = 0; k < n; k++)
{
// each thread responsible for one cell in C
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
};
__global__ void sgpu_mult_kernel(int* A, int* B, int* C, const int n, const int b)
{
__shared__ int sharedA[MAXTILE][MAXTILE];
__shared__ int sharedB[MAXTILE][MAXTILE];
int i = (blockIdx.y * b) + threadIdx.y; // row
int j = (blockIdx.x * b) + threadIdx.x; // col
// for each tiled section
int ntile = n / b;
for (int t = 0; t < ntile; t++)
{
// copy data to for this shared tiles (each thread works to acheive this goal)
sharedA[threadIdx.y][threadIdx.x] = A[i * n + (t * b + threadIdx.x)];
sharedB[threadIdx.y][threadIdx.x] = B[(t * b + threadIdx.y) * n + j];
// synchronize to ensure shared tiles are updated by all threads
__syncthreads();
// calculate the values for the tile section
for (int k = 0; k < b; k++)
{
// each thread responsible for one cell in C
C[i * n + j] += sharedA[threadIdx.y][k] * sharedB[k][threadIdx.x];
}
// synchronize before moving to next tile (prevents premature changes to shared memory)
__syncthreads();
}
};
void cpu_mult(int n, int* A, int* B, int* C);
int* allocate_matrix(int n);
void randomize_matrix(int n, int* A);
void print_matrix(int n, int* A);
bool equal_matrix(int n, int* A, int* B);
double rtclock();
int main(int argc, char * argv[])
{
if (argc != 2)
{
printf("Error: Missing argument");
return 0;
}
srand(time(NULL));
int n = atoi(argv[1]);
int m = n * n * sizeof(int);
if (n < 1)
{
printf("Error: Invalid Matrix Size");
return 0;
}
int b = 1;
if (n <= MAXTILE)
{
b = n;
}
else
{
b = MAXTILE;
while (b > 1 && n % b != 0) // while b is not a factor of n
{
b--;
}
}
int *X, *Y, *Zcpu, *Zgpu, *Zsgpu;
int *X_d, *Y_d, *Zgpu_d, *Zsgpu_d;
double start, end;
allocate_matrix(n);
X = allocate_matrix(n);
Y = allocate_matrix(n);
Zcpu = allocate_matrix(n);
Zgpu = allocate_matrix(n);
Zsgpu = allocate_matrix(n);
randomize_matrix(n, X);
randomize_matrix(n, Y);
// print X
//print_matrix(n, X);
//print_matrix(n, Y);
start = rtclock();
cpu_mult(n, X, Y, Zcpu);
end = rtclock();
printf("CPU time:\t%f\n", end - start);
//print_matrix(n, Zcpu);
// allocate memory on gpu
hipMalloc((void **)&X_d, m);
hipMalloc((void **)&Y_d, m);
// copy host data to gpu
hipMemcpy(X_d, X, m, hipMemcpyHostToDevice);
hipMemcpy(Y_d, Y, m, hipMemcpyHostToDevice);
// kernel parameters
dim3 dimGrid(n / b, n / b, 1);
dim3 dimBlock(b, b, 1);
// run kernels
start = rtclock();
hipMalloc((void **)&Zgpu_d, m);
hipMemcpy(Zgpu_d, Zgpu, m, hipMemcpyHostToDevice);
gpu_mult_kernel <<<dimGrid, dimBlock>>> (X_d, Y_d, Zgpu_d, n);
hipMemcpy(Zgpu, Zgpu_d, m, hipMemcpyDeviceToHost);
end = rtclock();
printf("GPU time:\t%f\n", end - start);
start = rtclock();
hipMalloc((void **)&Zsgpu_d, m);
hipMemcpy(Zsgpu_d, Zsgpu, m, hipMemcpyHostToDevice);
sgpu_mult_kernel <<<dimGrid, dimBlock>>> (X_d, Y_d, Zsgpu_d, n, b);
hipMemcpy(Zsgpu, Zsgpu_d, m, hipMemcpyDeviceToHost);
end = rtclock();
printf("sGPU time:\t%f\n", end - start);
//print_matrix(n, Zgpu);
//print_matrix(n, Zsgpu);
printf("Zcpu == Zgpu? %s\n", equal_matrix(n, Zcpu, Zgpu) ? "true" : "false");
printf("Zcpu == Zsgpu? %s\n", equal_matrix(n, Zcpu, Zsgpu) ? "true" : "false");
}
void cpu_mult(int n, int* A, int* B, int* C)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
for (int k = 0; k < n; k++)
C[i * n + j] += A[i * n + k] * B[k * n + j];
}
int* allocate_matrix(int n)
{
int* A = (int *)malloc(n * n * sizeof(int*));
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
A[i * n + j] = 0;
return A;
}
void randomize_matrix(int n, int * A)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
A[i * n + j] = rand() % 10;
}
void print_matrix(int n, int* A)
{
for (int i = 0; i < n; i++)
{
for (int j = 0; j < n; j++)
printf("%4d ", A[i * n + j]);
printf("\n");
}
printf("\n");
}
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0)
{
printf("Error return from gettimeofday: %d\n", stat);
}
return (Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
bool equal_matrix(int n, int* A, int* B)
{
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
{
int index = i * n + j;
if (A[index] != B[index])
return false;
}
return true;
} | .text
.file "MatrixMult.hip"
.globl _Z30__device_stub__gpu_mult_kernelPiS_S_i # -- Begin function _Z30__device_stub__gpu_mult_kernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__gpu_mult_kernelPiS_S_i,@function
_Z30__device_stub__gpu_mult_kernelPiS_S_i: # @_Z30__device_stub__gpu_mult_kernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gpu_mult_kernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__gpu_mult_kernelPiS_S_i, .Lfunc_end0-_Z30__device_stub__gpu_mult_kernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z31__device_stub__sgpu_mult_kernelPiS_S_ii # -- Begin function _Z31__device_stub__sgpu_mult_kernelPiS_S_ii
.p2align 4, 0x90
.type _Z31__device_stub__sgpu_mult_kernelPiS_S_ii,@function
_Z31__device_stub__sgpu_mult_kernelPiS_S_ii: # @_Z31__device_stub__sgpu_mult_kernelPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16sgpu_mult_kernelPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z31__device_stub__sgpu_mult_kernelPiS_S_ii, .Lfunc_end1-_Z31__device_stub__sgpu_mult_kernelPiS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB2_1
# %bb.3:
movq %rsi, %rbx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
testl %ebp, %ebp
jle .LBB2_4
# %bb.5:
movl %ebp, %ecx
movq %rbp, %rax
movq %rbp, 8(%rsp) # 8-byte Spill
movl %ebp, %r8d
imull %ecx, %r8d
movl %ebp, %esi
cmpl $33, %ebp
jl .LBB2_10
# %bb.6: # %.preheader.preheader
movl $32, %esi
.p2align 4, 0x90
.LBB2_7: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %ecx, %eax
xorl %edx, %edx
divl %esi
testl %edx, %edx
je .LBB2_10
# %bb.8: # in Loop: Header=BB2_7 Depth=1
leal -1(%rsi), %eax
cmpl $2, %esi
movl %eax, %esi
ja .LBB2_7
# %bb.9:
movl $1, %esi
.LBB2_10: # %.critedge
movq %rsi, 216(%rsp) # 8-byte Spill
movl %ecx, 52(%rsp) # 4-byte Spill
movl %r8d, %edi
shll $2, %r8d
movl %r8d, 204(%rsp) # 4-byte Spill
shlq $3, %rdi
movq %rdi, 32(%rsp) # 8-byte Spill
callq malloc
movq %rax, %r13
movl 8(%rsp), %r12d # 4-byte Reload
leaq (,%r12,4), %rbx
shlq $2, %rbp
xorl %r14d, %r14d
movq %r12, %r15
.p2align 4, 0x90
.LBB2_11: # %.preheader.i83
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdi
addq %r13, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
addq %rbp, %r14
decq %r15
jne .LBB2_11
# %bb.12: # %_Z15allocate_matrixi.exit88
movq %r13, 16(%rsp) # 8-byte Spill
movq 32(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r13
movl 8(%rsp), %ebx # 4-byte Reload
shlq $2, %rbx
xorl %r14d, %r14d
movq %r12, %r15
.p2align 4, 0x90
.LBB2_13: # %.preheader.i91
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdi
addq %r13, %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq memset@PLT
addq %rbp, %r14
decq %r15
jne .LBB2_13
# %bb.14: # %_Z15allocate_matrixi.exit96
movq 32(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, 224(%rsp) # 8-byte Spill
movl 8(%rsp), %r15d # 4-byte Reload
shlq $2, %r15
xorl %ebx, %ebx
movq %r12, %r14
.p2align 4, 0x90
.LBB2_15: # %.preheader.i99
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdi
addq 224(%rsp), %rdi # 8-byte Folded Reload
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
addq %rbp, %rbx
decq %r14
jne .LBB2_15
# %bb.16: # %_Z15allocate_matrixi.exit104
movq 32(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, 112(%rsp) # 8-byte Spill
movl 8(%rsp), %r14d # 4-byte Reload
shlq $2, %r14
xorl %ebx, %ebx
movq %r12, %r15
.p2align 4, 0x90
.LBB2_17: # %.preheader.i107
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdi
addq 112(%rsp), %rdi # 8-byte Folded Reload
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
addq %rbp, %rbx
decq %r15
jne .LBB2_17
# %bb.18: # %_Z15allocate_matrixi.exit112
movq 32(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movl 8(%rsp), %r14d # 4-byte Reload
shlq $2, %r14
xorl %ebx, %ebx
movq %r12, %r15
.p2align 4, 0x90
.LBB2_19: # %.preheader.i115
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
andq %rax, %rdi
addq 32(%rsp), %rdi # 8-byte Folded Reload
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
addq %rbp, %rbx
decq %r15
jne .LBB2_19
# %bb.20: # %.preheader.lr.ph.i121
movl 8(%rsp), %eax # 4-byte Reload
movq %rax, 24(%rsp) # 8-byte Spill
xorl %ebp, %ebp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_21: # %.preheader.i122
# =>This Loop Header: Depth=1
# Child Loop BB2_22 Depth 2
movl %ebp, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_22: # Parent Loop BB2_21 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq %r14, %r12
jne .LBB2_22
# %bb.23: # %._crit_edge.i
# in Loop: Header=BB2_21 Depth=1
incq %r15
addl 8(%rsp), %ebp # 4-byte Folded Reload
cmpq 24(%rsp), %r15 # 8-byte Folded Reload
jne .LBB2_21
# %bb.24: # %.preheader.lr.ph.i127
movl 8(%rsp), %r14d # 4-byte Reload
xorl %r12d, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_25: # %.preheader.i129
# =>This Loop Header: Depth=1
# Child Loop BB2_26 Depth 2
movl %r12d, %eax
leaq (,%rax,4), %rbx
addq %r13, %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_26: # Parent Loop BB2_25 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%rbp,4)
incq %rbp
cmpq %rbp, %r14
jne .LBB2_26
# %bb.27: # %._crit_edge.i135
# in Loop: Header=BB2_25 Depth=1
incq %r15
addl 8(%rsp), %r12d # 4-byte Folded Reload
cmpq %r14, %r15
jne .LBB2_25
# %bb.28: # %_Z16randomize_matrixiPi.exit138
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB2_30
# %bb.29:
movl $.L.str.11, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB2_30: # %_Z7rtclockv.exit
cvtsi2sdq 72(%rsp), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
movq 64(%rsp), %rax
movl 8(%rsp), %ecx # 4-byte Reload
xorl %edx, %edx
xorl %esi, %esi
movq 224(%rsp), %r14 # 8-byte Reload
movq 32(%rsp), %r15 # 8-byte Reload
movq 16(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB2_31: # %.preheader23.i
# =>This Loop Header: Depth=1
# Child Loop BB2_32 Depth 2
# Child Loop BB2_33 Depth 3
movl %edx, %edi
leaq (%r12,%rdi,4), %rdi
movq %rsi, %r8
imulq %rcx, %r8
leaq (%r14,%r8,4), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_32: # %.preheader.i139
# Parent Loop BB2_31 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_33 Depth 3
movl (%r8,%r9,4), %r10d
movq %r9, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_33: # Parent Loop BB2_31 Depth=1
# Parent Loop BB2_32 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r13,%r11,4), %ebp
imull (%rdi,%rbx,4), %ebp
addl %ebp, %r10d
incq %rbx
addq %rcx, %r11
cmpq %rbx, %rcx
jne .LBB2_33
# %bb.34: # %._crit_edge.i144
# in Loop: Header=BB2_32 Depth=2
movl %r10d, (%r8,%r9,4)
incq %r9
cmpq %rcx, %r9
jne .LBB2_32
# %bb.35: # %._crit_edge26.i
# in Loop: Header=BB2_31 Depth=1
incq %rsi
addl 8(%rsp), %edx # 4-byte Folded Reload
cmpq %rcx, %rsi
jne .LBB2_31
# %bb.36: # %_Z8cpu_multiPiS_S_.exit
cvtsi2sd %rax, %xmm0
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB2_38
# %bb.37:
movl $.L.str.11, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB2_38: # %_Z7rtclockv.exit146
xorps %xmm1, %xmm1
cvtsi2sdq 64(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.2, %edi
movb $1, %al
callq printf
movslq 204(%rsp), %rbp # 4-byte Folded Reload
leaq 136(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 128(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 136(%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 128(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movl 52(%rsp), %eax # 4-byte Reload
cltd
movq 216(%rsp), %rcx # 8-byte Reload
idivl %ecx
# kill: def $eax killed $eax def $rax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
movl %ecx, %eax
movq %rax, %r13
shlq $32, %r13
orq %rax, %r13
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB2_40
# %bb.39:
movl $.L.str.11, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB2_40: # %_Z7rtclockv.exit148
xorps %xmm0, %xmm0
cvtsi2sdq 64(%rsp), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
leaq 120(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 120(%rsp), %rdi
movq 112(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_42
# %bb.41:
movq 136(%rsp), %rax
movq 128(%rsp), %rcx
movq 120(%rsp), %rdx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movl 52(%rsp), %eax # 4-byte Reload
movl %eax, 56(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 72(%rsp)
leaq 176(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15gpu_mult_kernelPiS_S_i, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_42:
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq 120(%rsp), %rsi
movq %rbx, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB2_44
# %bb.43:
movl $.L.str.11, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB2_44: # %_Z7rtclockv.exit150
cvtsi2sdq 64(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB2_46
# %bb.45:
movl $.L.str.11, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB2_46: # %_Z7rtclockv.exit152
xorps %xmm0, %xmm0
cvtsi2sdq 64(%rsp), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
leaq 56(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 56(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_48
# %bb.47:
movq 136(%rsp), %rax
movq 128(%rsp), %rcx
movq 56(%rsp), %rdx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movl 52(%rsp), %eax # 4-byte Reload
movl %eax, 212(%rsp)
movq 216(%rsp), %rax # 8-byte Reload
movl %eax, 208(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 72(%rsp)
leaq 176(%rsp), %rax
movq %rax, 80(%rsp)
leaq 212(%rsp), %rax
movq %rax, 88(%rsp)
leaq 208(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16sgpu_mult_kernelPiS_S_ii, %edi
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_48:
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq 56(%rsp), %rsi
movq %r15, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
movq 112(%rsp), %r13 # 8-byte Reload
je .LBB2_50
# %bb.49:
movl $.L.str.11, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB2_50: # %_Z7rtclockv.exit160
xorps %xmm1, %xmm1
cvtsi2sdq 64(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl (%r14), %eax
movl $.L.str.7, %r12d
movl $.L.str.7, %esi
cmpl (%r13), %eax
jne .LBB2_59
# %bb.51: # %.lr.ph.preheader.preheader
movl 8(%rsp), %eax # 4-byte Reload
movq %r13, %rcx
addq $4, %rcx
leaq (,%rax,4), %rdx
leaq 4(%r14), %rsi
leaq -1(%rax), %r8
xorl %edi, %edi
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_53: # %.lr.ph.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_54 Depth 2
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_54: # %.lr.ph
# Parent Loop BB2_53 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r10, %r8
je .LBB2_57
# %bb.55: # in Loop: Header=BB2_54 Depth=2
movl (%rsi,%r10,4), %ebx
leaq 1(%r10), %r11
cmpl (%rcx,%r10,4), %ebx
movq %r11, %r10
je .LBB2_54
# %bb.56: # %._crit_edge
# in Loop: Header=BB2_53 Depth=1
cmpq %rax, %r11
jb .LBB2_58
.LBB2_57: # %.critedge.i
# in Loop: Header=BB2_53 Depth=1
incq %r9
cmpq %rax, %r9
setae %dil
je .LBB2_58
# %bb.52: # %.preheader.i162
# in Loop: Header=BB2_53 Depth=1
movq %r9, %r10
imulq %rax, %r10
movl (%r14,%r10,4), %r11d
addq %rdx, %rcx
addq %rdx, %rsi
cmpl (%r13,%r10,4), %r11d
je .LBB2_53
.LBB2_58: # %_Z12equal_matrixiPiS_.exit.loopexit
movl $.L.str.6, %eax
movl $.L.str.7, %esi
testb $1, %dil
cmovneq %rax, %rsi
.LBB2_59: # %_Z12equal_matrixiPiS_.exit
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl (%r14), %eax
cmpl (%r15), %eax
jne .LBB2_68
# %bb.60: # %.lr.ph207.preheader.preheader
movl 8(%rsp), %eax # 4-byte Reload
movq %r15, %rcx
addq $4, %rcx
leaq (,%rax,4), %rdx
movq %r14, %rsi
addq $4, %rsi
leaq -1(%rax), %r8
xorl %edi, %edi
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_62: # %.lr.ph207.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_63 Depth 2
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_63: # %.lr.ph207
# Parent Loop BB2_62 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r10, %r8
je .LBB2_66
# %bb.64: # in Loop: Header=BB2_63 Depth=2
movl (%rsi,%r10,4), %ebx
leaq 1(%r10), %r11
cmpl (%rcx,%r10,4), %ebx
movq %r11, %r10
je .LBB2_63
# %bb.65: # %._crit_edge208
# in Loop: Header=BB2_62 Depth=1
cmpq %rax, %r11
jb .LBB2_67
.LBB2_66: # %.critedge.i177
# in Loop: Header=BB2_62 Depth=1
incq %r9
cmpq %rax, %r9
setae %dil
je .LBB2_67
# %bb.61: # %.preheader.i171
# in Loop: Header=BB2_62 Depth=1
movq %r9, %r10
imulq %rax, %r10
movl (%r14,%r10,4), %r11d
addq %rdx, %rcx
addq %rdx, %rsi
cmpl (%r15,%r10,4), %r11d
je .LBB2_62
.LBB2_67: # %_Z12equal_matrixiPiS_.exit185.loopexit
movl $.L.str.6, %eax
movl $.L.str.7, %r12d
testb $1, %dil
cmovneq %rax, %r12
.LBB2_68: # %_Z12equal_matrixiPiS_.exit185
movl $.L.str.8, %edi
movq %r12, %rsi
xorl %eax, %eax
callq printf
jmp .LBB2_69
.LBB2_1:
movl $.L.str, %edi
jmp .LBB2_2
.LBB2_4:
movl $.L.str.1, %edi
.LBB2_2:
xorl %eax, %eax
callq printf
.LBB2_69:
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z15allocate_matrixi # -- Begin function _Z15allocate_matrixi
.p2align 4, 0x90
.type _Z15allocate_matrixi,@function
_Z15allocate_matrixi: # @_Z15allocate_matrixi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
imull %edi, %edi
shlq $3, %rdi
callq malloc
movq %rax, %r14
testl %ebx, %ebx
jle .LBB3_3
# %bb.1: # %.preheader.lr.ph
movl %ebx, %r12d
leaq (,%r12,4), %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movl %ebp, %eax
leaq (%r14,%rax,4), %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
addl %ebx, %ebp
decq %r12
jne .LBB3_2
.LBB3_3: # %._crit_edge16
movq %r14, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15allocate_matrixi, .Lfunc_end3-_Z15allocate_matrixi
.cfi_endproc
# -- End function
.globl _Z16randomize_matrixiPi # -- Begin function _Z16randomize_matrixiPi
.p2align 4, 0x90
.type _Z16randomize_matrixiPi,@function
_Z16randomize_matrixiPi: # @_Z16randomize_matrixiPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, (%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB4_5
# %bb.1: # %.preheader.lr.ph
movl %edi, %ebp
movl %edi, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %r15d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r13,%rbx,4)
incq %rbx
cmpq %rbx, %r14
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r12
addl %ebp, %r15d
cmpq %r14, %r12
jne .LBB4_2
.LBB4_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16randomize_matrixiPi, .Lfunc_end4-_Z16randomize_matrixiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI5_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB5_2
# %bb.1:
movl $.L.str.11, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB5_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI5_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z7rtclockv, .Lfunc_end5-_Z7rtclockv
.cfi_endproc
# -- End function
.globl _Z8cpu_multiPiS_S_ # -- Begin function _Z8cpu_multiPiS_S_
.p2align 4, 0x90
.type _Z8cpu_multiPiS_S_,@function
_Z8cpu_multiPiS_S_: # @_Z8cpu_multiPiS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, -8(%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB6_7
# %bb.1: # %.preheader23.lr.ph
movl %edi, %eax
leaq (,%rax,4), %r8
xorl %ecx, %ecx
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB6_2: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB6_3 Depth 2
# Child Loop BB6_4 Depth 3
movl %ecx, %r11d
leaq (%rsi,%r11,4), %r11
movq %r10, %rbx
imulq %rax, %rbx
movq -8(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rbx,4), %rbx
movq %rdx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_3: # %.preheader
# Parent Loop BB6_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_4 Depth 3
movl (%rbx,%r15,4), %ebp
movq %r14, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB6_4: # Parent Loop BB6_2 Depth=1
# Parent Loop BB6_3 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r12), %r9d
imull (%r11,%r13,4), %r9d
addl %r9d, %ebp
movl %ebp, (%rbx,%r15,4)
incq %r13
addq %r8, %r12
cmpq %r13, %rax
jne .LBB6_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB6_3 Depth=2
incq %r15
addq $4, %r14
cmpq %rax, %r15
jne .LBB6_3
# %bb.6: # %._crit_edge26
# in Loop: Header=BB6_2 Depth=1
incq %r10
addl %edi, %ecx
cmpq %rax, %r10
jne .LBB6_2
.LBB6_7: # %._crit_edge28
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z8cpu_multiPiS_S_, .Lfunc_end6-_Z8cpu_multiPiS_S_
.cfi_endproc
# -- End function
.globl _Z12equal_matrixiPiS_ # -- Begin function _Z12equal_matrixiPiS_
.p2align 4, 0x90
.type _Z12equal_matrixiPiS_,@function
_Z12equal_matrixiPiS_: # @_Z12equal_matrixiPiS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
setle %al
jle .LBB7_9
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edi, %ecx
leaq 4(%rsi), %rdi
leaq (,%rcx,4), %r8
leaq 4(%rdx), %r9
leaq -1(%rcx), %r10
xorl %r11d, %r11d
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_7: # %.critedge
# in Loop: Header=BB7_2 Depth=1
incq %r11
cmpq %rcx, %r11
setae %al
addq %r8, %rdi
addq %r8, %r9
cmpq %rcx, %r11
je .LBB7_8
.LBB7_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
movq %r11, %rbx
imulq %rcx, %rbx
movl (%rsi,%rbx,4), %ebp
cmpl (%rdx,%rbx,4), %ebp
jne .LBB7_8
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB7_2 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB7_4: # %.lr.ph
# Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rbx, %r10
je .LBB7_7
# %bb.5: # in Loop: Header=BB7_4 Depth=2
movl (%rdi,%rbx,4), %ebp
leaq 1(%rbx), %r14
cmpl (%r9,%rbx,4), %ebp
movq %r14, %rbx
je .LBB7_4
# %bb.6: # %._crit_edge40
# in Loop: Header=BB7_2 Depth=1
cmpq %rcx, %r14
jae .LBB7_7
.LBB7_8:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %rbp
.LBB7_9: # %._crit_edge
andb $1, %al
retq
.Lfunc_end7:
.size _Z12equal_matrixiPiS_, .Lfunc_end7-_Z12equal_matrixiPiS_
.cfi_endproc
# -- End function
.globl _Z12print_matrixiPi # -- Begin function _Z12print_matrixiPi
.p2align 4, 0x90
.type _Z12print_matrixiPi,@function
_Z12print_matrixiPi: # @_Z12print_matrixiPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, (%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB8_5
# %bb.1: # %.preheader.lr.ph
movl %edi, %ebp
movl %edi, %r14d
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB8_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB8_3 Depth 2
movl %r15d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_3: # Parent Loop BB8_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%rbx,4), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r14
jne .LBB8_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB8_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
addl %ebp, %r15d
cmpq %r14, %r12
jne .LBB8_2
.LBB8_5: # %._crit_edge14
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end8:
.size _Z12print_matrixiPi, .Lfunc_end8-_Z12print_matrixiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gpu_mult_kernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16sgpu_mult_kernelPiS_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15gpu_mult_kernelPiS_S_i,@object # @_Z15gpu_mult_kernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z15gpu_mult_kernelPiS_S_i
.p2align 3, 0x0
_Z15gpu_mult_kernelPiS_S_i:
.quad _Z30__device_stub__gpu_mult_kernelPiS_S_i
.size _Z15gpu_mult_kernelPiS_S_i, 8
.type _Z16sgpu_mult_kernelPiS_S_ii,@object # @_Z16sgpu_mult_kernelPiS_S_ii
.globl _Z16sgpu_mult_kernelPiS_S_ii
.p2align 3, 0x0
_Z16sgpu_mult_kernelPiS_S_ii:
.quad _Z31__device_stub__sgpu_mult_kernelPiS_S_ii
.size _Z16sgpu_mult_kernelPiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: Missing argument"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: Invalid Matrix Size"
.size .L.str.1, 27
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU time:\t%f\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU time:\t%f\n"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "sGPU time:\t%f\n"
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Zcpu == Zgpu? %s\n"
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "true"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "false"
.size .L.str.7, 6
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Zcpu == Zsgpu? %s\n"
.size .L.str.8, 19
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%4d "
.size .L.str.9, 5
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Error return from gettimeofday: %d\n"
.size .L.str.11, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15gpu_mult_kernelPiS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16sgpu_mult_kernelPiS_S_ii"
.size .L__unnamed_2, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__gpu_mult_kernelPiS_S_i
.addrsig_sym _Z31__device_stub__sgpu_mult_kernelPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15gpu_mult_kernelPiS_S_i
.addrsig_sym _Z16sgpu_mult_kernelPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <ostream>
#include <sstream>
#include <iostream>
int main(){
cudaDeviceProp prop{};
//query device
cudaGetDeviceProperties(&prop,0);
//store device parameters as variables
std::string name = prop.name;
double clockRate = prop.clockRate;
double globalMem = prop.totalGlobalMem;
double memFreq = prop.memoryClockRate;
double maxThreads = prop.maxThreadsPerBlock;
double maxBlocks = prop.maxBlocksPerMultiProcessor;
//print results
std::cout
<< "Name: "<< name << std::endl
<< "Clock Rate: "<< clockRate << std::endl
<< "Memory Available: "<< globalMem << std::endl
<< "Memory Frequency: "<< memFreq << std::endl
<< "Max Threads: "<< maxThreads << std::endl
<< "Max Blocks: "<< maxBlocks << std::endl;
printf("done");
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <ostream>
#include <sstream>
#include <iostream>
int main(){
cudaDeviceProp prop{};
//query device
cudaGetDeviceProperties(&prop,0);
//store device parameters as variables
std::string name = prop.name;
double clockRate = prop.clockRate;
double globalMem = prop.totalGlobalMem;
double memFreq = prop.memoryClockRate;
double maxThreads = prop.maxThreadsPerBlock;
double maxBlocks = prop.maxBlocksPerMultiProcessor;
//print results
std::cout
<< "Name: "<< name << std::endl
<< "Clock Rate: "<< clockRate << std::endl
<< "Memory Available: "<< globalMem << std::endl
<< "Memory Frequency: "<< memFreq << std::endl
<< "Max Threads: "<< maxThreads << std::endl
<< "Max Blocks: "<< maxBlocks << std::endl;
printf("done");
} | .file "tmpxft_0013fb0d_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3730:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3730:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Name: "
.LC1:
.string "Clock Rate: "
.LC2:
.string "Memory Available: "
.LC3:
.string "Memory Frequency: "
.LC4:
.string "Max Threads: "
.LC5:
.string "Max Blocks: "
.LC6:
.string "done"
.text
.globl main
.type main, @function
main:
.LFB3727:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3727
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1104, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdi
movl $129, %ecx
rep stosq
leaq 64(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
.LEHB0:
call cudaGetDeviceProperties_v2@PLT
.LEHE0:
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
movq %rbx, %rdi
call strlen@PLT
movq %rax, %rbx
movq %rax, 24(%rsp)
cmpq $15, %rax
ja .L20
cmpq $1, %rax
jne .L6
movzbl 64(%rsp), %eax
movb %al, 48(%rsp)
.L7:
movq 24(%rsp), %rax
movq %rax, 40(%rsp)
movq 32(%rsp), %rdx
movb $0, (%rdx,%rax)
pxor %xmm1, %xmm1
cvtsi2sdl 412(%rsp), %xmm1
movq %xmm1, %r14
movq 352(%rsp), %rax
testq %rax, %rax
js .L12
pxor %xmm5, %xmm5
cvtsi2sdq %rax, %xmm5
movq %xmm5, %r15
.L13:
pxor %xmm2, %xmm2
cvtsi2sdl 672(%rsp), %xmm2
movsd %xmm2, (%rsp)
pxor %xmm3, %xmm3
cvtsi2sdl 384(%rsp), %xmm3
movsd %xmm3, 8(%rsp)
pxor %xmm4, %xmm4
cvtsi2sdl 776(%rsp), %xmm4
movq %xmm4, %rbx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB1:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE1:
jmp .L21
.L20:
leaq 24(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $0, %edx
.LEHB2:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE2:
movq %rax, 32(%rsp)
movq 24(%rsp), %rdx
movq %rdx, 48(%rsp)
.L5:
leaq 64(%rsp), %rsi
movq %rax, %rdx
cmpl $8, %ebx
jnb .L8
testb $4, %bl
jne .L22
testl %ebx, %ebx
je .L7
movzbl 64(%rsp), %eax
movb %al, (%rdx)
testb $2, %bl
je .L7
movl %ebx, %ebx
movzwl -2(%rsi,%rbx), %eax
movw %ax, -2(%rdx,%rbx)
jmp .L7
.L6:
testq %rax, %rax
je .L7
leaq 48(%rsp), %rax
jmp .L5
.L22:
movl 64(%rsp), %eax
movl %eax, (%rdx)
movl %ebx, %ebx
movl -4(%rsi,%rbx), %eax
movl %eax, -4(%rdx,%rbx)
jmp .L7
.L8:
movq 64(%rsp), %rdx
movq %rdx, (%rax)
movl %ebx, %edx
movq -8(%rsi,%rdx), %rcx
movq %rcx, -8(%rax,%rdx)
leaq 8(%rax), %rdi
andq $-8, %rdi
subq %rdi, %rax
subq %rax, %rsi
leal (%rbx,%rax), %ecx
shrl $3, %ecx
movl %ecx, %ecx
rep movsq
jmp .L7
.L12:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
movq %xmm0, %r15
jmp .L13
.L21:
movq %rax, %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
.LEHB3:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r14, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r15, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd (%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE3:
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $1104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3727:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3727:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3727-.LLSDACSB3727
.LLSDACSB3727:
.uleb128 .LEHB0-.LFB3727
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3727
.uleb128 .LEHE1-.LEHB1
.uleb128 .L17-.LFB3727
.uleb128 0
.uleb128 .LEHB2-.LFB3727
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3727
.uleb128 .LEHE3-.LEHB3
.uleb128 .L17-.LFB3727
.uleb128 0
.uleb128 .LEHB4-.LFB3727
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3727:
.text
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3753:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3753:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <ostream>
#include <sstream>
#include <iostream>
int main(){
cudaDeviceProp prop{};
//query device
cudaGetDeviceProperties(&prop,0);
//store device parameters as variables
std::string name = prop.name;
double clockRate = prop.clockRate;
double globalMem = prop.totalGlobalMem;
double memFreq = prop.memoryClockRate;
double maxThreads = prop.maxThreadsPerBlock;
double maxBlocks = prop.maxBlocksPerMultiProcessor;
//print results
std::cout
<< "Name: "<< name << std::endl
<< "Clock Rate: "<< clockRate << std::endl
<< "Memory Available: "<< globalMem << std::endl
<< "Memory Frequency: "<< memFreq << std::endl
<< "Max Threads: "<< maxThreads << std::endl
<< "Max Blocks: "<< maxBlocks << std::endl;
printf("done");
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <ostream>
#include <sstream>
#include <iostream>
int main(){
hipDeviceProp_t prop{};
//query device
hipGetDeviceProperties(&prop,0);
//store device parameters as variables
std::string name = prop.name;
double clockRate = prop.clockRate;
double globalMem = prop.totalGlobalMem;
double memFreq = prop.memoryClockRate;
double maxThreads = prop.maxThreadsPerBlock;
double maxBlocks = prop.maxBlocksPerMultiProcessor;
//print results
std::cout
<< "Name: "<< name << std::endl
<< "Clock Rate: "<< clockRate << std::endl
<< "Memory Available: "<< globalMem << std::endl
<< "Memory Frequency: "<< memFreq << std::endl
<< "Max Threads: "<< maxThreads << std::endl
<< "Max Blocks: "<< maxBlocks << std::endl;
printf("done");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <ostream>
#include <sstream>
#include <iostream>
int main(){
hipDeviceProp_t prop{};
//query device
hipGetDeviceProperties(&prop,0);
//store device parameters as variables
std::string name = prop.name;
double clockRate = prop.clockRate;
double globalMem = prop.totalGlobalMem;
double memFreq = prop.memoryClockRate;
double maxThreads = prop.maxThreadsPerBlock;
double maxBlocks = prop.maxBlocksPerMultiProcessor;
//print results
std::cout
<< "Name: "<< name << std::endl
<< "Clock Rate: "<< clockRate << std::endl
<< "Memory Available: "<< globalMem << std::endl
<< "Memory Frequency: "<< memFreq << std::endl
<< "Max Threads: "<< maxThreads << std::endl
<< "Max Blocks: "<< maxBlocks << std::endl;
printf("done");
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <ostream>
#include <sstream>
#include <iostream>
int main(){
hipDeviceProp_t prop{};
//query device
hipGetDeviceProperties(&prop,0);
//store device parameters as variables
std::string name = prop.name;
double clockRate = prop.clockRate;
double globalMem = prop.totalGlobalMem;
double memFreq = prop.memoryClockRate;
double maxThreads = prop.maxThreadsPerBlock;
double maxBlocks = prop.maxBlocksPerMultiProcessor;
//print results
std::cout
<< "Name: "<< name << std::endl
<< "Clock Rate: "<< clockRate << std::endl
<< "Memory Available: "<< globalMem << std::endl
<< "Memory Frequency: "<< memFreq << std::endl
<< "Max Threads: "<< maxThreads << std::endl
<< "Max Blocks: "<< maxBlocks << std::endl;
printf("done");
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 80(%rsp), %rbx
movl $1472, %edx # imm = 0x5C0
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
leaq 16(%rsp), %r15
movq %r15, (%rsp)
movq %rbx, %rdi
callq strlen
movq %rax, %rbx
cmpq $16, %rax
jb .LBB0_4
# %bb.1:
testq %rbx, %rbx
js .LBB0_70
# %bb.2:
movq %rbx, %rdi
incq %rdi
js .LBB0_71
# %bb.3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
callq _Znwm
movq %rax, (%rsp)
movq %rbx, 16(%rsp)
.LBB0_4:
testq %rbx, %rbx
je .LBB0_8
# %bb.5:
movq (%rsp), %rdi
cmpq $1, %rbx
jne .LBB0_7
# %bb.6:
movzbl 80(%rsp), %eax
movb %al, (%rdi)
jmp .LBB0_8
.LBB0_7:
leaq 80(%rsp), %rsi
movq %rbx, %rdx
callq memcpy@PLT
.LBB0_8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
cvtsi2sdl 428(%rsp), %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
movsd 368(%rsp), %xmm0 # xmm0 = mem[0],zero
movaps %xmm0, 64(%rsp) # 16-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdl 688(%rsp), %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdl 400(%rsp), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdl 792(%rsp), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
.Ltmp0:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq (%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp2:
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp3:
# %bb.10: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_13
# %bb.12:
movzbl 67(%r14), %eax
jmp .LBB0_15
.LBB0_13:
.Ltmp4:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp5:
# %bb.14: # %.noexc46
movq (%r14), %rax
.Ltmp6:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp7:
.LBB0_15: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp8:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp9:
# %bb.16: # %.noexc48
.Ltmp10:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp11:
# %bb.17: # %_ZNSolsEPFRSoS_E.exit
.Ltmp12:
movq %rax, %rbx
movl $.L.str.1, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit14
.Ltmp14:
movq %rbx, %rdi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp15:
# %bb.19: # %_ZNSolsEd.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r14)
je .LBB0_22
# %bb.21:
movzbl 67(%r14), %eax
jmp .LBB0_24
.LBB0_22:
.Ltmp16:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp17:
# %bb.23: # %.noexc56
movq (%r14), %rax
.Ltmp18:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp19:
.LBB0_24: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i53
.Ltmp20:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp21:
# %bb.25: # %.noexc58
.Ltmp22:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp23:
# %bb.26: # %_ZNSolsEPFRSoS_E.exit17
.Ltmp24:
movq %rax, %rbx
movl $.L.str.2, %esi
movl $18, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp25:
# %bb.27: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19
.Ltmp26:
movapd 64(%rsp), %xmm1 # 16-byte Reload
unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp27:
# %bb.28: # %_ZNSolsEd.exit21
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i62
cmpb $0, 56(%r14)
je .LBB0_31
# %bb.30:
movzbl 67(%r14), %eax
jmp .LBB0_33
.LBB0_31:
.Ltmp28:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp29:
# %bb.32: # %.noexc67
movq (%r14), %rax
.Ltmp30:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp31:
.LBB0_33: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i64
.Ltmp32:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp33:
# %bb.34: # %.noexc69
.Ltmp34:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp35:
# %bb.35: # %_ZNSolsEPFRSoS_E.exit23
.Ltmp36:
movq %rax, %rbx
movl $.L.str.3, %esi
movl $18, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp37:
# %bb.36: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit25
.Ltmp38:
movq %rbx, %rdi
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp39:
# %bb.37: # %_ZNSolsEd.exit27
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.38: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i73
cmpb $0, 56(%r14)
je .LBB0_40
# %bb.39:
movzbl 67(%r14), %eax
jmp .LBB0_42
.LBB0_40:
.Ltmp40:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp41:
# %bb.41: # %.noexc78
movq (%r14), %rax
.Ltmp42:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp43:
.LBB0_42: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i75
.Ltmp44:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp45:
# %bb.43: # %.noexc80
.Ltmp46:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp47:
# %bb.44: # %_ZNSolsEPFRSoS_E.exit29
.Ltmp48:
movq %rax, %rbx
movl $.L.str.4, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp49:
# %bb.45: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit31
.Ltmp50:
movq %rbx, %rdi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp51:
# %bb.46: # %_ZNSolsEd.exit33
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.47: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i84
cmpb $0, 56(%r14)
je .LBB0_49
# %bb.48:
movzbl 67(%r14), %eax
jmp .LBB0_51
.LBB0_49:
.Ltmp52:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp53:
# %bb.50: # %.noexc89
movq (%r14), %rax
.Ltmp54:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp55:
.LBB0_51: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i86
.Ltmp56:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp57:
# %bb.52: # %.noexc91
.Ltmp58:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp59:
# %bb.53: # %_ZNSolsEPFRSoS_E.exit35
.Ltmp60:
movq %rax, %rbx
movl $.L.str.5, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp61:
# %bb.54: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit37
.Ltmp62:
movq %rbx, %rdi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp63:
# %bb.55: # %_ZNSolsEd.exit39
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.58: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i95
cmpb $0, 56(%r14)
je .LBB0_60
# %bb.59:
movzbl 67(%r14), %eax
jmp .LBB0_62
.LBB0_60:
.Ltmp64:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp65:
# %bb.61: # %.noexc100
movq (%r14), %rax
.Ltmp66:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp67:
.LBB0_62: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i97
.Ltmp68:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp69:
# %bb.63: # %.noexc102
.Ltmp70:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp71:
# %bb.64: # %_ZNSolsEPFRSoS_E.exit41
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
cmpq %r15, %rdi
je .LBB0_66
# %bb.65: # %.critedge.i.i
callq _ZdlPv
.LBB0_66: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
xorl %eax, %eax
addq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_71: # %.noexc11.i
.cfi_def_cfa_offset 1584
callq _ZSt17__throw_bad_allocv
.LBB0_56: # %.invoke
.Ltmp72:
callq _ZSt16__throw_bad_castv
.Ltmp73:
# %bb.57: # %.cont
.LBB0_70: # %.noexc.i
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.LBB0_67:
.Ltmp74:
movq %rax, %rbx
movq (%rsp), %rdi
cmpq %r15, %rdi
je .LBB0_69
# %bb.68: # %.critedge.i.i42
callq _ZdlPv
.LBB0_69: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit44
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp71-.Ltmp0 # Call between .Ltmp0 and .Ltmp71
.uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74
.byte 0 # On action: cleanup
.uleb128 .Ltmp71-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp72-.Ltmp71 # Call between .Ltmp71 and .Ltmp72
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp72-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp73-.Ltmp72 # Call between .Ltmp72 and .Ltmp73
.uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp73 # Call between .Ltmp73 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Name: "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Clock Rate: "
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Memory Available: "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Memory Frequency: "
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Max Threads: "
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Max Blocks: "
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "done"
.size .L.str.6, 5
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "basic_string::_M_create"
.size .L.str.8, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013fb0d_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3730:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3730:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Name: "
.LC1:
.string "Clock Rate: "
.LC2:
.string "Memory Available: "
.LC3:
.string "Memory Frequency: "
.LC4:
.string "Max Threads: "
.LC5:
.string "Max Blocks: "
.LC6:
.string "done"
.text
.globl main
.type main, @function
main:
.LFB3727:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3727
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1104, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %rdi
movl $129, %ecx
rep stosq
leaq 64(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
.LEHB0:
call cudaGetDeviceProperties_v2@PLT
.LEHE0:
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
movq %rbx, %rdi
call strlen@PLT
movq %rax, %rbx
movq %rax, 24(%rsp)
cmpq $15, %rax
ja .L20
cmpq $1, %rax
jne .L6
movzbl 64(%rsp), %eax
movb %al, 48(%rsp)
.L7:
movq 24(%rsp), %rax
movq %rax, 40(%rsp)
movq 32(%rsp), %rdx
movb $0, (%rdx,%rax)
pxor %xmm1, %xmm1
cvtsi2sdl 412(%rsp), %xmm1
movq %xmm1, %r14
movq 352(%rsp), %rax
testq %rax, %rax
js .L12
pxor %xmm5, %xmm5
cvtsi2sdq %rax, %xmm5
movq %xmm5, %r15
.L13:
pxor %xmm2, %xmm2
cvtsi2sdl 672(%rsp), %xmm2
movsd %xmm2, (%rsp)
pxor %xmm3, %xmm3
cvtsi2sdl 384(%rsp), %xmm3
movsd %xmm3, 8(%rsp)
pxor %xmm4, %xmm4
cvtsi2sdl 776(%rsp), %xmm4
movq %xmm4, %rbx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB1:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE1:
jmp .L21
.L20:
leaq 24(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $0, %edx
.LEHB2:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE2:
movq %rax, 32(%rsp)
movq 24(%rsp), %rdx
movq %rdx, 48(%rsp)
.L5:
leaq 64(%rsp), %rsi
movq %rax, %rdx
cmpl $8, %ebx
jnb .L8
testb $4, %bl
jne .L22
testl %ebx, %ebx
je .L7
movzbl 64(%rsp), %eax
movb %al, (%rdx)
testb $2, %bl
je .L7
movl %ebx, %ebx
movzwl -2(%rsi,%rbx), %eax
movw %ax, -2(%rdx,%rbx)
jmp .L7
.L6:
testq %rax, %rax
je .L7
leaq 48(%rsp), %rax
jmp .L5
.L22:
movl 64(%rsp), %eax
movl %eax, (%rdx)
movl %ebx, %ebx
movl -4(%rsi,%rbx), %eax
movl %eax, -4(%rdx,%rbx)
jmp .L7
.L8:
movq 64(%rsp), %rdx
movq %rdx, (%rax)
movl %ebx, %edx
movq -8(%rsi,%rdx), %rcx
movq %rcx, -8(%rax,%rdx)
leaq 8(%rax), %rdi
andq $-8, %rdi
subq %rdi, %rax
subq %rax, %rsi
leal (%rbx,%rax), %ecx
shrl $3, %ecx
movl %ecx, %ecx
rep movsq
jmp .L7
.L12:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
movq %xmm0, %r15
jmp .L13
.L21:
movq %rax, %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
.LEHB3:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r14, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r15, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd (%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE3:
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $1104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3727:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3727:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3727-.LLSDACSB3727
.LLSDACSB3727:
.uleb128 .LEHB0-.LFB3727
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3727
.uleb128 .LEHE1-.LEHB1
.uleb128 .L17-.LFB3727
.uleb128 0
.uleb128 .LEHB2-.LFB3727
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3727
.uleb128 .LEHE3-.LEHB3
.uleb128 .L17-.LFB3727
.uleb128 0
.uleb128 .LEHB4-.LFB3727
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3727:
.text
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3753:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3753:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 1584
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 80(%rsp), %rbx
movl $1472, %edx # imm = 0x5C0
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
leaq 16(%rsp), %r15
movq %r15, (%rsp)
movq %rbx, %rdi
callq strlen
movq %rax, %rbx
cmpq $16, %rax
jb .LBB0_4
# %bb.1:
testq %rbx, %rbx
js .LBB0_70
# %bb.2:
movq %rbx, %rdi
incq %rdi
js .LBB0_71
# %bb.3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
callq _Znwm
movq %rax, (%rsp)
movq %rbx, 16(%rsp)
.LBB0_4:
testq %rbx, %rbx
je .LBB0_8
# %bb.5:
movq (%rsp), %rdi
cmpq $1, %rbx
jne .LBB0_7
# %bb.6:
movzbl 80(%rsp), %eax
movb %al, (%rdi)
jmp .LBB0_8
.LBB0_7:
leaq 80(%rsp), %rsi
movq %rbx, %rdx
callq memcpy@PLT
.LBB0_8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
movq %rbx, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%rbx)
cvtsi2sdl 428(%rsp), %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
movsd 368(%rsp), %xmm0 # xmm0 = mem[0],zero
movaps %xmm0, 64(%rsp) # 16-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdl 688(%rsp), %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdl 400(%rsp), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdl 792(%rsp), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
.Ltmp0:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq (%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp2:
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp3:
# %bb.10: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_13
# %bb.12:
movzbl 67(%r14), %eax
jmp .LBB0_15
.LBB0_13:
.Ltmp4:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp5:
# %bb.14: # %.noexc46
movq (%r14), %rax
.Ltmp6:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp7:
.LBB0_15: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp8:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp9:
# %bb.16: # %.noexc48
.Ltmp10:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp11:
# %bb.17: # %_ZNSolsEPFRSoS_E.exit
.Ltmp12:
movq %rax, %rbx
movl $.L.str.1, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit14
.Ltmp14:
movq %rbx, %rdi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp15:
# %bb.19: # %_ZNSolsEd.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r14)
je .LBB0_22
# %bb.21:
movzbl 67(%r14), %eax
jmp .LBB0_24
.LBB0_22:
.Ltmp16:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp17:
# %bb.23: # %.noexc56
movq (%r14), %rax
.Ltmp18:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp19:
.LBB0_24: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i53
.Ltmp20:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp21:
# %bb.25: # %.noexc58
.Ltmp22:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp23:
# %bb.26: # %_ZNSolsEPFRSoS_E.exit17
.Ltmp24:
movq %rax, %rbx
movl $.L.str.2, %esi
movl $18, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp25:
# %bb.27: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19
.Ltmp26:
movapd 64(%rsp), %xmm1 # 16-byte Reload
unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp27:
# %bb.28: # %_ZNSolsEd.exit21
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i62
cmpb $0, 56(%r14)
je .LBB0_31
# %bb.30:
movzbl 67(%r14), %eax
jmp .LBB0_33
.LBB0_31:
.Ltmp28:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp29:
# %bb.32: # %.noexc67
movq (%r14), %rax
.Ltmp30:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp31:
.LBB0_33: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i64
.Ltmp32:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp33:
# %bb.34: # %.noexc69
.Ltmp34:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp35:
# %bb.35: # %_ZNSolsEPFRSoS_E.exit23
.Ltmp36:
movq %rax, %rbx
movl $.L.str.3, %esi
movl $18, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp37:
# %bb.36: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit25
.Ltmp38:
movq %rbx, %rdi
movsd 48(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp39:
# %bb.37: # %_ZNSolsEd.exit27
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.38: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i73
cmpb $0, 56(%r14)
je .LBB0_40
# %bb.39:
movzbl 67(%r14), %eax
jmp .LBB0_42
.LBB0_40:
.Ltmp40:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp41:
# %bb.41: # %.noexc78
movq (%r14), %rax
.Ltmp42:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp43:
.LBB0_42: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i75
.Ltmp44:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp45:
# %bb.43: # %.noexc80
.Ltmp46:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp47:
# %bb.44: # %_ZNSolsEPFRSoS_E.exit29
.Ltmp48:
movq %rax, %rbx
movl $.L.str.4, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp49:
# %bb.45: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit31
.Ltmp50:
movq %rbx, %rdi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp51:
# %bb.46: # %_ZNSolsEd.exit33
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.47: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i84
cmpb $0, 56(%r14)
je .LBB0_49
# %bb.48:
movzbl 67(%r14), %eax
jmp .LBB0_51
.LBB0_49:
.Ltmp52:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp53:
# %bb.50: # %.noexc89
movq (%r14), %rax
.Ltmp54:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp55:
.LBB0_51: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i86
.Ltmp56:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp57:
# %bb.52: # %.noexc91
.Ltmp58:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp59:
# %bb.53: # %_ZNSolsEPFRSoS_E.exit35
.Ltmp60:
movq %rax, %rbx
movl $.L.str.5, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp61:
# %bb.54: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit37
.Ltmp62:
movq %rbx, %rdi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp63:
# %bb.55: # %_ZNSolsEd.exit39
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_56
# %bb.58: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i95
cmpb $0, 56(%r14)
je .LBB0_60
# %bb.59:
movzbl 67(%r14), %eax
jmp .LBB0_62
.LBB0_60:
.Ltmp64:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp65:
# %bb.61: # %.noexc100
movq (%r14), %rax
.Ltmp66:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp67:
.LBB0_62: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i97
.Ltmp68:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp69:
# %bb.63: # %.noexc102
.Ltmp70:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp71:
# %bb.64: # %_ZNSolsEPFRSoS_E.exit41
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
cmpq %r15, %rdi
je .LBB0_66
# %bb.65: # %.critedge.i.i
callq _ZdlPv
.LBB0_66: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
xorl %eax, %eax
addq $1552, %rsp # imm = 0x610
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_71: # %.noexc11.i
.cfi_def_cfa_offset 1584
callq _ZSt17__throw_bad_allocv
.LBB0_56: # %.invoke
.Ltmp72:
callq _ZSt16__throw_bad_castv
.Ltmp73:
# %bb.57: # %.cont
.LBB0_70: # %.noexc.i
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.LBB0_67:
.Ltmp74:
movq %rax, %rbx
movq (%rsp), %rdi
cmpq %r15, %rdi
je .LBB0_69
# %bb.68: # %.critedge.i.i42
callq _ZdlPv
.LBB0_69: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit44
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp71-.Ltmp0 # Call between .Ltmp0 and .Ltmp71
.uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74
.byte 0 # On action: cleanup
.uleb128 .Ltmp71-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp72-.Ltmp71 # Call between .Ltmp71 and .Ltmp72
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp72-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp73-.Ltmp72 # Call between .Ltmp72 and .Ltmp73
.uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp73 # Call between .Ltmp73 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Name: "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Clock Rate: "
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Memory Available: "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Memory Frequency: "
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Max Threads: "
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Max Blocks: "
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "done"
.size .L.str.6, 5
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "basic_string::_M_create"
.size .L.str.8, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void addition_kernel(float* a, float* b, float* c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
c[idx] = a[idx] + b[idx];
}
/*
#define N (2048*2048)
#define THREADS_PER_BLOCK 512
__global__ void dot( int *a, int *b, int *c ) {
__shared__ int temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if( 0 == threadIdx.x ) {
int sum = 0;
for( int i = 0; i < THREADS_PER_BLOCK; i++ )
sum += temp[i];
atomicAdd(
*c += sum; c , sum );
}
}
*/ | code for sm_80
Function : _Z15addition_kernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void addition_kernel(float* a, float* b, float* c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
c[idx] = a[idx] + b[idx];
}
/*
#define N (2048*2048)
#define THREADS_PER_BLOCK 512
__global__ void dot( int *a, int *b, int *c ) {
__shared__ int temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if( 0 == threadIdx.x ) {
int sum = 0;
for( int i = 0; i < THREADS_PER_BLOCK; i++ )
sum += temp[i];
atomicAdd(
*c += sum; c , sum );
}
}
*/ | .file "tmpxft_00068f70_00000000-6_addition_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_
.type _Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_, @function
_Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15addition_kernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_, .-_Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_
.globl _Z15addition_kernelPfS_S_
.type _Z15addition_kernelPfS_S_, @function
_Z15addition_kernelPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15addition_kernelPfS_S_, .-_Z15addition_kernelPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15addition_kernelPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15addition_kernelPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void addition_kernel(float* a, float* b, float* c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
c[idx] = a[idx] + b[idx];
}
/*
#define N (2048*2048)
#define THREADS_PER_BLOCK 512
__global__ void dot( int *a, int *b, int *c ) {
__shared__ int temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if( 0 == threadIdx.x ) {
int sum = 0;
for( int i = 0; i < THREADS_PER_BLOCK; i++ )
sum += temp[i];
atomicAdd(
*c += sum; c , sum );
}
}
*/ | #include <hip/hip_runtime.h>
__global__ void addition_kernel(float* a, float* b, float* c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
c[idx] = a[idx] + b[idx];
}
/*
#define N (2048*2048)
#define THREADS_PER_BLOCK 512
__global__ void dot( int *a, int *b, int *c ) {
__shared__ int temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if( 0 == threadIdx.x ) {
int sum = 0;
for( int i = 0; i < THREADS_PER_BLOCK; i++ )
sum += temp[i];
atomicAdd(
*c += sum; c , sum );
}
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void addition_kernel(float* a, float* b, float* c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
c[idx] = a[idx] + b[idx];
}
/*
#define N (2048*2048)
#define THREADS_PER_BLOCK 512
__global__ void dot( int *a, int *b, int *c ) {
__shared__ int temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if( 0 == threadIdx.x ) {
int sum = 0;
for( int i = 0; i < THREADS_PER_BLOCK; i++ )
sum += temp[i];
atomicAdd(
*c += sum; c , sum );
}
}
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15addition_kernelPfS_S_
.globl _Z15addition_kernelPfS_S_
.p2align 8
.type _Z15addition_kernelPfS_S_,@function
_Z15addition_kernelPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15addition_kernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15addition_kernelPfS_S_, .Lfunc_end0-_Z15addition_kernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15addition_kernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15addition_kernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void addition_kernel(float* a, float* b, float* c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
c[idx] = a[idx] + b[idx];
}
/*
#define N (2048*2048)
#define THREADS_PER_BLOCK 512
__global__ void dot( int *a, int *b, int *c ) {
__shared__ int temp[THREADS_PER_BLOCK];
int index = threadIdx.x + blockIdx.x * blockDim.x;
temp[threadIdx.x] = a[index] * b[index];
__syncthreads();
if( 0 == threadIdx.x ) {
int sum = 0;
for( int i = 0; i < THREADS_PER_BLOCK; i++ )
sum += temp[i];
atomicAdd(
*c += sum; c , sum );
}
}
*/ | .text
.file "addition_kernel.hip"
.globl _Z30__device_stub__addition_kernelPfS_S_ # -- Begin function _Z30__device_stub__addition_kernelPfS_S_
.p2align 4, 0x90
.type _Z30__device_stub__addition_kernelPfS_S_,@function
_Z30__device_stub__addition_kernelPfS_S_: # @_Z30__device_stub__addition_kernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15addition_kernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__addition_kernelPfS_S_, .Lfunc_end0-_Z30__device_stub__addition_kernelPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15addition_kernelPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15addition_kernelPfS_S_,@object # @_Z15addition_kernelPfS_S_
.section .rodata,"a",@progbits
.globl _Z15addition_kernelPfS_S_
.p2align 3, 0x0
_Z15addition_kernelPfS_S_:
.quad _Z30__device_stub__addition_kernelPfS_S_
.size _Z15addition_kernelPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15addition_kernelPfS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__addition_kernelPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15addition_kernelPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15addition_kernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15addition_kernelPfS_S_
.globl _Z15addition_kernelPfS_S_
.p2align 8
.type _Z15addition_kernelPfS_S_,@function
_Z15addition_kernelPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15addition_kernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15addition_kernelPfS_S_, .Lfunc_end0-_Z15addition_kernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15addition_kernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15addition_kernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00068f70_00000000-6_addition_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_
.type _Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_, @function
_Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15addition_kernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_, .-_Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_
.globl _Z15addition_kernelPfS_S_
.type _Z15addition_kernelPfS_S_, @function
_Z15addition_kernelPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15addition_kernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15addition_kernelPfS_S_, .-_Z15addition_kernelPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15addition_kernelPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15addition_kernelPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addition_kernel.hip"
.globl _Z30__device_stub__addition_kernelPfS_S_ # -- Begin function _Z30__device_stub__addition_kernelPfS_S_
.p2align 4, 0x90
.type _Z30__device_stub__addition_kernelPfS_S_,@function
_Z30__device_stub__addition_kernelPfS_S_: # @_Z30__device_stub__addition_kernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15addition_kernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__addition_kernelPfS_S_, .Lfunc_end0-_Z30__device_stub__addition_kernelPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15addition_kernelPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15addition_kernelPfS_S_,@object # @_Z15addition_kernelPfS_S_
.section .rodata,"a",@progbits
.globl _Z15addition_kernelPfS_S_
.p2align 3, 0x0
_Z15addition_kernelPfS_S_:
.quad _Z30__device_stub__addition_kernelPfS_S_
.size _Z15addition_kernelPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15addition_kernelPfS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__addition_kernelPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15addition_kernelPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*用cpu实现2个矩阵之间的加法*/
#include<iostream>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#include"cuda_runtime.h"
using namespace std;
#define cols 1024
#define rows 1024
int main()
{
struct timeval start, end;
int n=cols*rows;
float **A,**B,**C;
float *a,*b,*c;
A=new float* [cols];
B=new float* [cols];
C=new float* [cols];
a=new float [n];
b=new float [n];
c=new float [n];
for(int i=0;i<n;i++)
{
a[i]=2;
b[i]=2;
}
for(int i=0;i<cols;i++)
{
A[i]=a+i*rows;
B[i]=b+i*rows;
C[i]=c+i*rows;
}
gettimeofday( &start, NULL);
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
C[i][j]+=A[i][j]+B[i][j];
}
}
gettimeofday( &end, NULL );
float target=4.0;
float error=0.0;
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
error+=abs(C[i][j]-target);
}
}
cout<<"error is "<<error<<endl;
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
cout << "total time is " << timeuse/1000 << "ms" <<endl;
delete [] a;
delete [] b;
delete [] c;
delete [] A;
delete [] B;
delete [] C;
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*用cpu实现2个矩阵之间的加法*/
#include<iostream>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#include"cuda_runtime.h"
using namespace std;
#define cols 1024
#define rows 1024
int main()
{
struct timeval start, end;
int n=cols*rows;
float **A,**B,**C;
float *a,*b,*c;
A=new float* [cols];
B=new float* [cols];
C=new float* [cols];
a=new float [n];
b=new float [n];
c=new float [n];
for(int i=0;i<n;i++)
{
a[i]=2;
b[i]=2;
}
for(int i=0;i<cols;i++)
{
A[i]=a+i*rows;
B[i]=b+i*rows;
C[i]=c+i*rows;
}
gettimeofday( &start, NULL);
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
C[i][j]+=A[i][j]+B[i][j];
}
}
gettimeofday( &end, NULL );
float target=4.0;
float error=0.0;
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
error+=abs(C[i][j]-target);
}
}
cout<<"error is "<<error<<endl;
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
cout << "total time is " << timeuse/1000 << "ms" <<endl;
delete [] a;
delete [] b;
delete [] c;
delete [] A;
delete [] B;
delete [] C;
return 0;
} | .file "tmpxft_0009370d_00000000-6_add_cpp.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "error is "
.LC5:
.string "total time is "
.LC6:
.string "ms"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $8192, %edi
call _Znam@PLT
movq %rax, %r12
movl $8192, %edi
call _Znam@PLT
movq %rax, %rbp
movl $8192, %edi
call _Znam@PLT
movq %rax, %rbx
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r14
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r13
movl $4194304, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $0, %eax
movss .LC1(%rip), %xmm0
.L4:
movss %xmm0, (%r14,%rax)
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L4
movq %r14, %rsi
movq %r13, %rcx
movq 8(%rsp), %rdx
movl $0, %eax
.L5:
movq %rsi, (%r12,%rax)
movq %rcx, 0(%rbp,%rax)
movq %rdx, (%rbx,%rax)
addq $4096, %rsi
addq $4096, %rcx
addq $4096, %rdx
addq $8, %rax
cmpq $8192, %rax
jne .L5
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %edi
.L6:
movq (%rbx,%rdi), %rdx
movq (%r12,%rdi), %rsi
movq 0(%rbp,%rdi), %rcx
movl $0, %eax
.L7:
movss (%rsi,%rax), %xmm0
addss (%rcx,%rax), %xmm0
addss (%rdx,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L7
addq $8, %rdi
cmpq $8192, %rdi
jne .L6
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq %rbx, %rcx
leaq 8192(%rbx), %rsi
movl $0x00000000, 4(%rsp)
movss .LC2(%rip), %xmm2
movss .LC3(%rip), %xmm1
.L9:
movq (%rcx), %rax
leaq 4096(%rax), %rdx
.L10:
movss (%rax), %xmm0
subss %xmm2, %xmm0
andps %xmm1, %xmm0
addss 4(%rsp), %xmm0
movss %xmm0, 4(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L10
addq $8, %rcx
cmpq %rsi, %rcx
jne .L9
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %r15
subq 16(%rsp), %r15
imull $1000000, %r15d, %r15d
subl 24(%rsp), %r15d
addl 40(%rsp), %r15d
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movslq %r15d, %rsi
imulq $274877907, %rsi, %rsi
sarq $38, %rsi
sarl $31, %r15d
subl %r15d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1073741824
.align 4
.LC2:
.long 1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*用cpu实现2个矩阵之间的加法*/
#include<iostream>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#include"cuda_runtime.h"
using namespace std;
#define cols 1024
#define rows 1024
int main()
{
struct timeval start, end;
int n=cols*rows;
float **A,**B,**C;
float *a,*b,*c;
A=new float* [cols];
B=new float* [cols];
C=new float* [cols];
a=new float [n];
b=new float [n];
c=new float [n];
for(int i=0;i<n;i++)
{
a[i]=2;
b[i]=2;
}
for(int i=0;i<cols;i++)
{
A[i]=a+i*rows;
B[i]=b+i*rows;
C[i]=c+i*rows;
}
gettimeofday( &start, NULL);
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
C[i][j]+=A[i][j]+B[i][j];
}
}
gettimeofday( &end, NULL );
float target=4.0;
float error=0.0;
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
error+=abs(C[i][j]-target);
}
}
cout<<"error is "<<error<<endl;
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
cout << "total time is " << timeuse/1000 << "ms" <<endl;
delete [] a;
delete [] b;
delete [] c;
delete [] A;
delete [] B;
delete [] C;
return 0;
} | /*用cpu实现2个矩阵之间的加法*/
#include<iostream>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#include"hip/hip_runtime.h"
using namespace std;
#define cols 1024
#define rows 1024
int main()
{
struct timeval start, end;
int n=cols*rows;
float **A,**B,**C;
float *a,*b,*c;
A=new float* [cols];
B=new float* [cols];
C=new float* [cols];
a=new float [n];
b=new float [n];
c=new float [n];
for(int i=0;i<n;i++)
{
a[i]=2;
b[i]=2;
}
for(int i=0;i<cols;i++)
{
A[i]=a+i*rows;
B[i]=b+i*rows;
C[i]=c+i*rows;
}
gettimeofday( &start, NULL);
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
C[i][j]+=A[i][j]+B[i][j];
}
}
gettimeofday( &end, NULL );
float target=4.0;
float error=0.0;
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
error+=abs(C[i][j]-target);
}
}
cout<<"error is "<<error<<endl;
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
cout << "total time is " << timeuse/1000 << "ms" <<endl;
delete [] a;
delete [] b;
delete [] c;
delete [] A;
delete [] B;
delete [] C;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*用cpu实现2个矩阵之间的加法*/
#include<iostream>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#include"hip/hip_runtime.h"
using namespace std;
#define cols 1024
#define rows 1024
int main()
{
struct timeval start, end;
int n=cols*rows;
float **A,**B,**C;
float *a,*b,*c;
A=new float* [cols];
B=new float* [cols];
C=new float* [cols];
a=new float [n];
b=new float [n];
c=new float [n];
for(int i=0;i<n;i++)
{
a[i]=2;
b[i]=2;
}
for(int i=0;i<cols;i++)
{
A[i]=a+i*rows;
B[i]=b+i*rows;
C[i]=c+i*rows;
}
gettimeofday( &start, NULL);
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
C[i][j]+=A[i][j]+B[i][j];
}
}
gettimeofday( &end, NULL );
float target=4.0;
float error=0.0;
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
error+=abs(C[i][j]-target);
}
}
cout<<"error is "<<error<<endl;
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
cout << "total time is " << timeuse/1000 << "ms" <<endl;
delete [] a;
delete [] b;
delete [] c;
delete [] A;
delete [] B;
delete [] C;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*用cpu实现2个矩阵之间的加法*/
#include<iostream>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#include"hip/hip_runtime.h"
using namespace std;
#define cols 1024
#define rows 1024
int main()
{
struct timeval start, end;
int n=cols*rows;
float **A,**B,**C;
float *a,*b,*c;
A=new float* [cols];
B=new float* [cols];
C=new float* [cols];
a=new float [n];
b=new float [n];
c=new float [n];
for(int i=0;i<n;i++)
{
a[i]=2;
b[i]=2;
}
for(int i=0;i<cols;i++)
{
A[i]=a+i*rows;
B[i]=b+i*rows;
C[i]=c+i*rows;
}
gettimeofday( &start, NULL);
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
C[i][j]+=A[i][j]+B[i][j];
}
}
gettimeofday( &end, NULL );
float target=4.0;
float error=0.0;
for(int i=0;i<rows;i++)
{
for(int j=0;j<cols;j++)
{
error+=abs(C[i][j]-target);
}
}
cout<<"error is "<<error<<endl;
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
cout << "total time is " << timeuse/1000 << "ms" <<endl;
delete [] a;
delete [] b;
delete [] c;
delete [] A;
delete [] B;
delete [] C;
return 0;
} | .text
.file "add_cpp.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0xc0800000 # float -4
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r14
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r12
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r13
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rsi
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1073741824, (%r12,%rax,4) # imm = 0x40000000
movl $1073741824, (%r13,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB0_1
# %bb.2: # %.preheader66.preheader
xorl %eax, %eax
movq %r12, %rcx
movq %r13, %rdx
movq %rsi, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB0_3: # %.preheader66
# =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
movq %rdx, (%r14,%rax,8)
movq %rsi, (%r15,%rax,8)
incq %rax
addq $4096, %rsi # imm = 0x1000
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB0_3
# %bb.4:
xorl %ebp, %ebp
leaq 40(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
.p2align 4, 0x90
.LBB0_5: # %.preheader65
# =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
movq (%rbx,%rbp,8), %rax
movq (%r14,%rbp,8), %rcx
movq (%r15,%rbp,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rcx,%rsi,4), %xmm0
addss (%rdx,%rsi,4), %xmm0
movss %xmm0, (%rdx,%rsi,4)
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB0_6
# %bb.7: # in Loop: Header=BB0_5 Depth=1
incq %rbp
cmpq $1024, %rbp # imm = 0x400
jne .LBB0_5
# %bb.8:
xorl %ebp, %ebp
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm3, %xmm3
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI0_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB0_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_10 Depth 2
movq (%r15,%rbp,8), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_10: # Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
addss %xmm2, %xmm3
incq %rcx
cmpq $1024, %rcx # imm = 0x400
jne .LBB0_10
# %bb.11: # in Loop: Header=BB0_9 Depth=1
incq %rbp
cmpq $1024, %rbp # imm = 0x400
jne .LBB0_9
# %bb.12:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
movss %xmm3, 8(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB0_21
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB0_15
# %bb.14:
movzbl 67(%rbp), %ecx
jmp .LBB0_16
.LBB0_15:
movq %rbp, %rdi
movq %rax, 8(%rsp) # 8-byte Spill
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq 8(%rsp), %rax # 8-byte Reload
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 24(%rsp), %eax
subl 40(%rsp), %eax
imull $1000000, %eax, %ebp # imm = 0xF4240
addl 32(%rsp), %ebp
subl 48(%rsp), %ebp
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq %ebp, %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $_ZSt4cout, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbp
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbp, %rdi
movq (%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .LBB0_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%rbp)
je .LBB0_19
# %bb.18:
movzbl 67(%rbp), %eax
jmp .LBB0_20
.LBB0_19:
movq %rdi, 8(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movq 8(%rsp), %rdi # 8-byte Reload
.LBB0_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r12, %rdi
callq _ZdaPv
movq %r13, %rdi
callq _ZdaPv
movq 16(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_21:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error is "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "total time is "
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ms"
.size .L.str.2, 3
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009370d_00000000-6_add_cpp.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "error is "
.LC5:
.string "total time is "
.LC6:
.string "ms"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $8192, %edi
call _Znam@PLT
movq %rax, %r12
movl $8192, %edi
call _Znam@PLT
movq %rax, %rbp
movl $8192, %edi
call _Znam@PLT
movq %rax, %rbx
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r14
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r13
movl $4194304, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $0, %eax
movss .LC1(%rip), %xmm0
.L4:
movss %xmm0, (%r14,%rax)
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L4
movq %r14, %rsi
movq %r13, %rcx
movq 8(%rsp), %rdx
movl $0, %eax
.L5:
movq %rsi, (%r12,%rax)
movq %rcx, 0(%rbp,%rax)
movq %rdx, (%rbx,%rax)
addq $4096, %rsi
addq $4096, %rcx
addq $4096, %rdx
addq $8, %rax
cmpq $8192, %rax
jne .L5
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %edi
.L6:
movq (%rbx,%rdi), %rdx
movq (%r12,%rdi), %rsi
movq 0(%rbp,%rdi), %rcx
movl $0, %eax
.L7:
movss (%rsi,%rax), %xmm0
addss (%rcx,%rax), %xmm0
addss (%rdx,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4096, %rax
jne .L7
addq $8, %rdi
cmpq $8192, %rdi
jne .L6
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq %rbx, %rcx
leaq 8192(%rbx), %rsi
movl $0x00000000, 4(%rsp)
movss .LC2(%rip), %xmm2
movss .LC3(%rip), %xmm1
.L9:
movq (%rcx), %rax
leaq 4096(%rax), %rdx
.L10:
movss (%rax), %xmm0
subss %xmm2, %xmm0
andps %xmm1, %xmm0
addss 4(%rsp), %xmm0
movss %xmm0, 4(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L10
addq $8, %rcx
cmpq %rsi, %rcx
jne .L9
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %r15
subq 16(%rsp), %r15
imull $1000000, %r15d, %r15d
subl 24(%rsp), %r15d
addl 40(%rsp), %r15d
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movslq %r15d, %rsi
imulq $274877907, %rsi, %rsi
sarq $38, %rsi
sarl $31, %r15d
subl %r15d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1073741824
.align 4
.LC2:
.long 1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_cpp.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0xc0800000 # float -4
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %rbx
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r14
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r12
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r13
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rsi
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1073741824, (%r12,%rax,4) # imm = 0x40000000
movl $1073741824, (%r13,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB0_1
# %bb.2: # %.preheader66.preheader
xorl %eax, %eax
movq %r12, %rcx
movq %r13, %rdx
movq %rsi, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB0_3: # %.preheader66
# =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
movq %rdx, (%r14,%rax,8)
movq %rsi, (%r15,%rax,8)
incq %rax
addq $4096, %rsi # imm = 0x1000
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB0_3
# %bb.4:
xorl %ebp, %ebp
leaq 40(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
.p2align 4, 0x90
.LBB0_5: # %.preheader65
# =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
movq (%rbx,%rbp,8), %rax
movq (%r14,%rbp,8), %rcx
movq (%r15,%rbp,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rcx,%rsi,4), %xmm0
addss (%rdx,%rsi,4), %xmm0
movss %xmm0, (%rdx,%rsi,4)
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB0_6
# %bb.7: # in Loop: Header=BB0_5 Depth=1
incq %rbp
cmpq $1024, %rbp # imm = 0x400
jne .LBB0_5
# %bb.8:
xorl %ebp, %ebp
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm3, %xmm3
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI0_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB0_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_10 Depth 2
movq (%r15,%rbp,8), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_10: # Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
addss %xmm2, %xmm3
incq %rcx
cmpq $1024, %rcx # imm = 0x400
jne .LBB0_10
# %bb.11: # in Loop: Header=BB0_9 Depth=1
incq %rbp
cmpq $1024, %rbp # imm = 0x400
jne .LBB0_9
# %bb.12:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
movss %xmm3, 8(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB0_21
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB0_15
# %bb.14:
movzbl 67(%rbp), %ecx
jmp .LBB0_16
.LBB0_15:
movq %rbp, %rdi
movq %rax, 8(%rsp) # 8-byte Spill
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq 8(%rsp), %rax # 8-byte Reload
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 24(%rsp), %eax
subl 40(%rsp), %eax
imull $1000000, %eax, %ebp # imm = 0xF4240
addl 32(%rsp), %ebp
subl 48(%rsp), %ebp
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq %ebp, %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $_ZSt4cout, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbp
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbp, %rdi
movq (%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .LBB0_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%rbp)
je .LBB0_19
# %bb.18:
movzbl 67(%rbp), %eax
jmp .LBB0_20
.LBB0_19:
movq %rdi, 8(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movq 8(%rsp), %rdi # 8-byte Reload
.LBB0_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r12, %rdi
callq _ZdaPv
movq %r13, %rdi
callq _ZdaPv
movq 16(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_21:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error is "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "total time is "
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ms"
.size .L.str.2, 3
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
using namespace std;
__global__ void add_vector(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * 96 + threadIdx.x;
if (id<size)
{
c[id] = a[id] + b[id];
}
}
int main()
{
int v1, v2;
cout << "First value ? " << endl;
cin >> v1;
cout << "Second value ? " << endl;
cin >> v2;
cout << "v1 = " << v1 << endl;
cout << "v2 = " << v2 << endl;
const int size = 20000;
int *a = new int[size];
int *b = new int[size];
int *c = new int[size];
for (int i=0; i<size; ++i)
{
a[i] = v1;
b[i] = v2;
}
int *a_dev, *b_dev, *c_dev;
if (cudaSuccess != cudaMalloc((void**)&a_dev, sizeof(int) * size))
{
cerr << "error allocation a_dev" << endl;
}
if (cudaSuccess != cudaMalloc((void**)&b_dev, sizeof(int) * size))
{
cerr << "error allocation b_dev" << endl;
}
if (cudaSuccess != cudaMalloc((void**)&c_dev, sizeof(int) * size))
{
cerr << "error allocation c_dev" << endl;
}
if (cudaSuccess != cudaMemcpy(a_dev, a, sizeof(int) * size, cudaMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
if (cudaSuccess != cudaMemcpy(b_dev, b, sizeof(int) * size, cudaMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
// dim3 block_dim(1, 1, 1);
// dim3 threads_per_block(size, 1, 1);
int nb_blocks = size / 96;
add_vector<<<nb_blocks+1, 96>>>(a_dev, b_dev, c_dev, size);
if (cudaSuccess != cudaMemcpy(c, c_dev, sizeof(int) * size, cudaMemcpyDeviceToHost))
{
cerr << "error cuda mem copy back" << endl;
}
for (int i=0; i<size; ++i)
{
cout << c[i] << " ";
}
cout << endl;
delete[] a;
delete[] b;
delete[] c;
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
return 0;
} | code for sm_80
Function : _Z10add_vectorPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, 0x60, R3 ; /* 0x0000006006067824 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
using namespace std;
__global__ void add_vector(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * 96 + threadIdx.x;
if (id<size)
{
c[id] = a[id] + b[id];
}
}
int main()
{
int v1, v2;
cout << "First value ? " << endl;
cin >> v1;
cout << "Second value ? " << endl;
cin >> v2;
cout << "v1 = " << v1 << endl;
cout << "v2 = " << v2 << endl;
const int size = 20000;
int *a = new int[size];
int *b = new int[size];
int *c = new int[size];
for (int i=0; i<size; ++i)
{
a[i] = v1;
b[i] = v2;
}
int *a_dev, *b_dev, *c_dev;
if (cudaSuccess != cudaMalloc((void**)&a_dev, sizeof(int) * size))
{
cerr << "error allocation a_dev" << endl;
}
if (cudaSuccess != cudaMalloc((void**)&b_dev, sizeof(int) * size))
{
cerr << "error allocation b_dev" << endl;
}
if (cudaSuccess != cudaMalloc((void**)&c_dev, sizeof(int) * size))
{
cerr << "error allocation c_dev" << endl;
}
if (cudaSuccess != cudaMemcpy(a_dev, a, sizeof(int) * size, cudaMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
if (cudaSuccess != cudaMemcpy(b_dev, b, sizeof(int) * size, cudaMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
// dim3 block_dim(1, 1, 1);
// dim3 threads_per_block(size, 1, 1);
int nb_blocks = size / 96;
add_vector<<<nb_blocks+1, 96>>>(a_dev, b_dev, c_dev, size);
if (cudaSuccess != cudaMemcpy(c, c_dev, sizeof(int) * size, cudaMemcpyDeviceToHost))
{
cerr << "error cuda mem copy back" << endl;
}
for (int i=0; i<size; ++i)
{
cout << c[i] << " ";
}
cout << endl;
delete[] a;
delete[] b;
delete[] c;
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
return 0;
} | .file "tmpxft_001ae659_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_vectorPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i
.globl _Z10add_vectorPiS_S_i
.type _Z10add_vectorPiS_S_i, @function
_Z10add_vectorPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z10add_vectorPiS_S_i, .-_Z10add_vectorPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "First value ? "
.LC1:
.string "Second value ? "
.LC2:
.string "v1 = "
.LC3:
.string "v2 = "
.LC4:
.string "error allocation a_dev"
.LC5:
.string "error allocation b_dev"
.LC6:
.string "error allocation c_dev"
.LC7:
.string "error cuda mem copy"
.LC8:
.string "error cuda mem copy back"
.LC9:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rsi
leaq _ZSt3cin(%rip), %rbp
movq %rbp, %rdi
call _ZNSirsERi@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 20(%rsp), %rsi
movq %rbp, %rdi
call _ZNSirsERi@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 16(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 20(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $80000, %edi
call _Znam@PLT
movq %rax, %r12
movl $80000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $80000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl 16(%rsp), %ecx
movl 20(%rsp), %edx
movl $0, %eax
.L12:
movl %ecx, (%r12,%rax)
movl %edx, 0(%rbp,%rax)
addq $4, %rax
cmpq $80000, %rax
jne .L12
leaq 24(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L25
.L13:
leaq 32(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
.L14:
leaq 40(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
.L15:
movl $1, %ecx
movl $80000, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L28
.L16:
movl $1, %ecx
movl $80000, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
.L17:
movl $96, 60(%rsp)
movl $1, 64(%rsp)
movl $209, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L18:
movl $2, %ecx
movl $80000, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L31
.L19:
movq 8(%rsp), %rax
movq %rax, %rbx
leaq 80000(%rax), %r15
leaq _ZSt4cout(%rip), %r14
leaq .LC9(%rip), %r13
.L20:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r15
jne .L20
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC4(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L13
.L26:
leaq .LC5(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L14
.L27:
leaq .LC6(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L28:
leaq .LC7(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L16
.L29:
leaq .LC7(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L17
.L30:
movl $20000, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i
jmp .L18
.L31:
leaq .LC8(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L19
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10add_vectorPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_vectorPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
using namespace std;
__global__ void add_vector(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * 96 + threadIdx.x;
if (id<size)
{
c[id] = a[id] + b[id];
}
}
int main()
{
int v1, v2;
cout << "First value ? " << endl;
cin >> v1;
cout << "Second value ? " << endl;
cin >> v2;
cout << "v1 = " << v1 << endl;
cout << "v2 = " << v2 << endl;
const int size = 20000;
int *a = new int[size];
int *b = new int[size];
int *c = new int[size];
for (int i=0; i<size; ++i)
{
a[i] = v1;
b[i] = v2;
}
int *a_dev, *b_dev, *c_dev;
if (cudaSuccess != cudaMalloc((void**)&a_dev, sizeof(int) * size))
{
cerr << "error allocation a_dev" << endl;
}
if (cudaSuccess != cudaMalloc((void**)&b_dev, sizeof(int) * size))
{
cerr << "error allocation b_dev" << endl;
}
if (cudaSuccess != cudaMalloc((void**)&c_dev, sizeof(int) * size))
{
cerr << "error allocation c_dev" << endl;
}
if (cudaSuccess != cudaMemcpy(a_dev, a, sizeof(int) * size, cudaMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
if (cudaSuccess != cudaMemcpy(b_dev, b, sizeof(int) * size, cudaMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
// dim3 block_dim(1, 1, 1);
// dim3 threads_per_block(size, 1, 1);
int nb_blocks = size / 96;
add_vector<<<nb_blocks+1, 96>>>(a_dev, b_dev, c_dev, size);
if (cudaSuccess != cudaMemcpy(c, c_dev, sizeof(int) * size, cudaMemcpyDeviceToHost))
{
cerr << "error cuda mem copy back" << endl;
}
for (int i=0; i<size; ++i)
{
cout << c[i] << " ";
}
cout << endl;
delete[] a;
delete[] b;
delete[] c;
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
using namespace std;
__global__ void add_vector(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * 96 + threadIdx.x;
if (id<size)
{
c[id] = a[id] + b[id];
}
}
int main()
{
int v1, v2;
cout << "First value ? " << endl;
cin >> v1;
cout << "Second value ? " << endl;
cin >> v2;
cout << "v1 = " << v1 << endl;
cout << "v2 = " << v2 << endl;
const int size = 20000;
int *a = new int[size];
int *b = new int[size];
int *c = new int[size];
for (int i=0; i<size; ++i)
{
a[i] = v1;
b[i] = v2;
}
int *a_dev, *b_dev, *c_dev;
if (hipSuccess != hipMalloc((void**)&a_dev, sizeof(int) * size))
{
cerr << "error allocation a_dev" << endl;
}
if (hipSuccess != hipMalloc((void**)&b_dev, sizeof(int) * size))
{
cerr << "error allocation b_dev" << endl;
}
if (hipSuccess != hipMalloc((void**)&c_dev, sizeof(int) * size))
{
cerr << "error allocation c_dev" << endl;
}
if (hipSuccess != hipMemcpy(a_dev, a, sizeof(int) * size, hipMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
if (hipSuccess != hipMemcpy(b_dev, b, sizeof(int) * size, hipMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
// dim3 block_dim(1, 1, 1);
// dim3 threads_per_block(size, 1, 1);
int nb_blocks = size / 96;
add_vector<<<nb_blocks+1, 96>>>(a_dev, b_dev, c_dev, size);
if (hipSuccess != hipMemcpy(c, c_dev, sizeof(int) * size, hipMemcpyDeviceToHost))
{
cerr << "error cuda mem copy back" << endl;
}
for (int i=0; i<size; ++i)
{
cout << c[i] << " ";
}
cout << endl;
delete[] a;
delete[] b;
delete[] c;
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
using namespace std;
__global__ void add_vector(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * 96 + threadIdx.x;
if (id<size)
{
c[id] = a[id] + b[id];
}
}
int main()
{
int v1, v2;
cout << "First value ? " << endl;
cin >> v1;
cout << "Second value ? " << endl;
cin >> v2;
cout << "v1 = " << v1 << endl;
cout << "v2 = " << v2 << endl;
const int size = 20000;
int *a = new int[size];
int *b = new int[size];
int *c = new int[size];
for (int i=0; i<size; ++i)
{
a[i] = v1;
b[i] = v2;
}
int *a_dev, *b_dev, *c_dev;
if (hipSuccess != hipMalloc((void**)&a_dev, sizeof(int) * size))
{
cerr << "error allocation a_dev" << endl;
}
if (hipSuccess != hipMalloc((void**)&b_dev, sizeof(int) * size))
{
cerr << "error allocation b_dev" << endl;
}
if (hipSuccess != hipMalloc((void**)&c_dev, sizeof(int) * size))
{
cerr << "error allocation c_dev" << endl;
}
if (hipSuccess != hipMemcpy(a_dev, a, sizeof(int) * size, hipMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
if (hipSuccess != hipMemcpy(b_dev, b, sizeof(int) * size, hipMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
// dim3 block_dim(1, 1, 1);
// dim3 threads_per_block(size, 1, 1);
int nb_blocks = size / 96;
add_vector<<<nb_blocks+1, 96>>>(a_dev, b_dev, c_dev, size);
if (hipSuccess != hipMemcpy(c, c_dev, sizeof(int) * size, hipMemcpyDeviceToHost))
{
cerr << "error cuda mem copy back" << endl;
}
for (int i=0; i<size; ++i)
{
cout << c[i] << " ";
}
cout << endl;
delete[] a;
delete[] b;
delete[] c;
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_vectorPiS_S_i
.globl _Z10add_vectorPiS_S_i
.p2align 8
.type _Z10add_vectorPiS_S_i,@function
_Z10add_vectorPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_mad_u64_u32 v[1:2], null, s15, 0x60, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_vectorPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_vectorPiS_S_i, .Lfunc_end0-_Z10add_vectorPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_vectorPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_vectorPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
using namespace std;
__global__ void add_vector(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * 96 + threadIdx.x;
if (id<size)
{
c[id] = a[id] + b[id];
}
}
int main()
{
int v1, v2;
cout << "First value ? " << endl;
cin >> v1;
cout << "Second value ? " << endl;
cin >> v2;
cout << "v1 = " << v1 << endl;
cout << "v2 = " << v2 << endl;
const int size = 20000;
int *a = new int[size];
int *b = new int[size];
int *c = new int[size];
for (int i=0; i<size; ++i)
{
a[i] = v1;
b[i] = v2;
}
int *a_dev, *b_dev, *c_dev;
if (hipSuccess != hipMalloc((void**)&a_dev, sizeof(int) * size))
{
cerr << "error allocation a_dev" << endl;
}
if (hipSuccess != hipMalloc((void**)&b_dev, sizeof(int) * size))
{
cerr << "error allocation b_dev" << endl;
}
if (hipSuccess != hipMalloc((void**)&c_dev, sizeof(int) * size))
{
cerr << "error allocation c_dev" << endl;
}
if (hipSuccess != hipMemcpy(a_dev, a, sizeof(int) * size, hipMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
if (hipSuccess != hipMemcpy(b_dev, b, sizeof(int) * size, hipMemcpyHostToDevice))
{
cerr << "error cuda mem copy" << endl;
}
// dim3 block_dim(1, 1, 1);
// dim3 threads_per_block(size, 1, 1);
int nb_blocks = size / 96;
add_vector<<<nb_blocks+1, 96>>>(a_dev, b_dev, c_dev, size);
if (hipSuccess != hipMemcpy(c, c_dev, sizeof(int) * size, hipMemcpyDeviceToHost))
{
cerr << "error cuda mem copy back" << endl;
}
for (int i=0; i<size; ++i)
{
cout << c[i] << " ";
}
cout << endl;
delete[] a;
delete[] b;
delete[] c;
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__add_vectorPiS_S_i # -- Begin function _Z25__device_stub__add_vectorPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__add_vectorPiS_S_i,@function
_Z25__device_stub__add_vectorPiS_S_i: # @_Z25__device_stub__add_vectorPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_vectorPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__add_vectorPiS_S_i, .Lfunc_end0-_Z25__device_stub__add_vectorPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_63
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_63
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_63
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_63
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %rbx
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %r14
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %r15
movl 4(%rsp), %eax
xorl %ecx, %ecx
movl (%rsp), %edx
.p2align 4, 0x90
.LBB1_17: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rcx,4)
movl %edx, (%r14,%rcx,4)
incq %rcx
cmpq $20000, %rcx # imm = 0x4E20
jne .LBB1_17
# %bb.18:
leaq 24(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
je .LBB1_24
# %bb.19:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
cmpb $0, 56(%r12)
je .LBB1_22
# %bb.21:
movzbl 67(%r12), %eax
jmp .LBB1_23
.LBB1_22:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_24:
leaq 16(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
je .LBB1_30
# %bb.25:
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%r12)
je .LBB1_28
# %bb.27:
movzbl 67(%r12), %eax
jmp .LBB1_29
.LBB1_28:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_30:
leaq 8(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
je .LBB1_36
# %bb.31:
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.32: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r12)
je .LBB1_34
# %bb.33:
movzbl 67(%r12), %eax
jmp .LBB1_35
.LBB1_34:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_35: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_36:
movq 24(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_42
# %bb.37:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.38: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r12)
je .LBB1_40
# %bb.39:
movzbl 67(%r12), %eax
jmp .LBB1_41
.LBB1_40:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_41: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_42:
movq 16(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_48
# %bb.43:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.44: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%r12)
je .LBB1_46
# %bb.45:
movzbl 67(%r12), %eax
jmp .LBB1_47
.LBB1_46:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_47: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_48:
movabsq $4294967392, %rdx # imm = 0x100000060
leaq 113(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_50
# %bb.49:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $20000, 36(%rsp) # imm = 0x4E20
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10add_vectorPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_50:
movq 8(%rsp), %rsi
movl $80000, %edx # imm = 0x13880
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_51
# %bb.56:
movl $_ZSt4cerr, %edi
movl $.L.str.8, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.57: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%r12)
je .LBB1_59
# %bb.58:
movzbl 67(%r12), %eax
jmp .LBB1_60
.LBB1_59:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_60: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_51: # %.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_52: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.9, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $20000, %r12 # imm = 0x4E20
jne .LBB1_52
# %bb.53:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i71
cmpb $0, 56(%r12)
je .LBB1_61
# %bb.55:
movzbl 67(%r12), %eax
jmp .LBB1_62
.LBB1_61:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_62: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit74
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_63:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_vectorPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10add_vectorPiS_S_i,@object # @_Z10add_vectorPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10add_vectorPiS_S_i
.p2align 3, 0x0
_Z10add_vectorPiS_S_i:
.quad _Z25__device_stub__add_vectorPiS_S_i
.size _Z10add_vectorPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "First value ? "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Second value ? "
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "v1 = "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "v2 = "
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "error allocation a_dev"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "error allocation b_dev"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "error allocation c_dev"
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "error cuda mem copy"
.size .L.str.7, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "error cuda mem copy back"
.size .L.str.8, 25
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " "
.size .L.str.9, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_vectorPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_vectorPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_vectorPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10add_vectorPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, 0x60, R3 ; /* 0x0000006006067824 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_vectorPiS_S_i
.globl _Z10add_vectorPiS_S_i
.p2align 8
.type _Z10add_vectorPiS_S_i,@function
_Z10add_vectorPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_mad_u64_u32 v[1:2], null, s15, 0x60, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_vectorPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_vectorPiS_S_i, .Lfunc_end0-_Z10add_vectorPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_vectorPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_vectorPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ae659_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_vectorPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i
.globl _Z10add_vectorPiS_S_i
.type _Z10add_vectorPiS_S_i, @function
_Z10add_vectorPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z10add_vectorPiS_S_i, .-_Z10add_vectorPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "First value ? "
.LC1:
.string "Second value ? "
.LC2:
.string "v1 = "
.LC3:
.string "v2 = "
.LC4:
.string "error allocation a_dev"
.LC5:
.string "error allocation b_dev"
.LC6:
.string "error allocation c_dev"
.LC7:
.string "error cuda mem copy"
.LC8:
.string "error cuda mem copy back"
.LC9:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rsi
leaq _ZSt3cin(%rip), %rbp
movq %rbp, %rdi
call _ZNSirsERi@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 20(%rsp), %rsi
movq %rbp, %rdi
call _ZNSirsERi@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 16(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 20(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $80000, %edi
call _Znam@PLT
movq %rax, %r12
movl $80000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $80000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl 16(%rsp), %ecx
movl 20(%rsp), %edx
movl $0, %eax
.L12:
movl %ecx, (%r12,%rax)
movl %edx, 0(%rbp,%rax)
addq $4, %rax
cmpq $80000, %rax
jne .L12
leaq 24(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L25
.L13:
leaq 32(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
.L14:
leaq 40(%rsp), %rdi
movl $80000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
.L15:
movl $1, %ecx
movl $80000, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L28
.L16:
movl $1, %ecx
movl $80000, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
.L17:
movl $96, 60(%rsp)
movl $1, 64(%rsp)
movl $209, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L18:
movl $2, %ecx
movl $80000, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L31
.L19:
movq 8(%rsp), %rax
movq %rax, %rbx
leaq 80000(%rax), %r15
leaq _ZSt4cout(%rip), %r14
leaq .LC9(%rip), %r13
.L20:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r15
jne .L20
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC4(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L13
.L26:
leaq .LC5(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L14
.L27:
leaq .LC6(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L15
.L28:
leaq .LC7(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L16
.L29:
leaq .LC7(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L17
.L30:
movl $20000, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z10add_vectorPiS_S_iPiS_S_i
jmp .L18
.L31:
leaq .LC8(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L19
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10add_vectorPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_vectorPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__add_vectorPiS_S_i # -- Begin function _Z25__device_stub__add_vectorPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__add_vectorPiS_S_i,@function
_Z25__device_stub__add_vectorPiS_S_i: # @_Z25__device_stub__add_vectorPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_vectorPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__add_vectorPiS_S_i, .Lfunc_end0-_Z25__device_stub__add_vectorPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_63
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_63
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%rbx)
je .LBB1_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB1_8
.LBB1_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_63
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
cmpb $0, 56(%rbx)
je .LBB1_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB1_12
.LBB1_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_63
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %rbx
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %r14
movl $80000, %edi # imm = 0x13880
callq _Znam
movq %rax, %r15
movl 4(%rsp), %eax
xorl %ecx, %ecx
movl (%rsp), %edx
.p2align 4, 0x90
.LBB1_17: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rcx,4)
movl %edx, (%r14,%rcx,4)
incq %rcx
cmpq $20000, %rcx # imm = 0x4E20
jne .LBB1_17
# %bb.18:
leaq 24(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
je .LBB1_24
# %bb.19:
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
cmpb $0, 56(%r12)
je .LBB1_22
# %bb.21:
movzbl 67(%r12), %eax
jmp .LBB1_23
.LBB1_22:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_24:
leaq 16(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
je .LBB1_30
# %bb.25:
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%r12)
je .LBB1_28
# %bb.27:
movzbl 67(%r12), %eax
jmp .LBB1_29
.LBB1_28:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_30:
leaq 8(%rsp), %rdi
movl $80000, %esi # imm = 0x13880
callq hipMalloc
testl %eax, %eax
je .LBB1_36
# %bb.31:
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.32: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r12)
je .LBB1_34
# %bb.33:
movzbl 67(%r12), %eax
jmp .LBB1_35
.LBB1_34:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_35: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_36:
movq 24(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_42
# %bb.37:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.38: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r12)
je .LBB1_40
# %bb.39:
movzbl 67(%r12), %eax
jmp .LBB1_41
.LBB1_40:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_41: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_42:
movq 16(%rsp), %rdi
movl $80000, %edx # imm = 0x13880
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_48
# %bb.43:
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.44: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%r12)
je .LBB1_46
# %bb.45:
movzbl 67(%r12), %eax
jmp .LBB1_47
.LBB1_46:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_47: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_48:
movabsq $4294967392, %rdx # imm = 0x100000060
leaq 113(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_50
# %bb.49:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $20000, 36(%rsp) # imm = 0x4E20
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10add_vectorPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_50:
movq 8(%rsp), %rsi
movl $80000, %edx # imm = 0x13880
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_51
# %bb.56:
movl $_ZSt4cerr, %edi
movl $.L.str.8, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.57: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%r12)
je .LBB1_59
# %bb.58:
movzbl 67(%r12), %eax
jmp .LBB1_60
.LBB1_59:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_60: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_51: # %.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_52: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.9, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $20000, %r12 # imm = 0x4E20
jne .LBB1_52
# %bb.53:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_63
# %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i71
cmpb $0, 56(%r12)
je .LBB1_61
# %bb.55:
movzbl 67(%r12), %eax
jmp .LBB1_62
.LBB1_61:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_62: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit74
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_63:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_vectorPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10add_vectorPiS_S_i,@object # @_Z10add_vectorPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10add_vectorPiS_S_i
.p2align 3, 0x0
_Z10add_vectorPiS_S_i:
.quad _Z25__device_stub__add_vectorPiS_S_i
.size _Z10add_vectorPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "First value ? "
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Second value ? "
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "v1 = "
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "v2 = "
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "error allocation a_dev"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "error allocation b_dev"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "error allocation c_dev"
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "error cuda mem copy"
.size .L.str.7, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "error cuda mem copy back"
.size .L.str.8, 25
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " "
.size .L.str.9, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_vectorPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_vectorPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_vectorPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
__global__ void heat_step(float * d_out, float * d_in)
{
// int block_x = blockIdx.x;
// int block_y = blockIdx.y;
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
d_out[location] = 0;
if (x_glob > 0)
{
d_out[location] += 0.25 * d_in[location - 1];
}
if (x_glob < (x_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + 1];
}
if (y_glob > 0)
{
d_out[location] += 0.25 * d_in[location - x_total_dim];
}
if (y_glob < (y_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + x_total_dim];
}
if (x_glob == 0)
{
d_out[location] = 1;
}
}
int main()
{
const int N=200;
const int M=200;
const int ARRAY_SIZE = N * M;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int Niter = 1000;
size_t counter = 0;
FILE * writefile;
writefile=fopen("out_laplace.txt", "w");
float h_start[ARRAY_SIZE];
for(int i=0; i<ARRAY_SIZE; i++)
{
h_start[i] = 0;
}
float h_out[ARRAY_SIZE];
float * d_in;
float * d_out;
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_out, ARRAY_BYTES);
cudaMemcpy(d_in, h_start, ARRAY_BYTES, cudaMemcpyHostToDevice);
while (counter<Niter)
{
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_in, d_out);
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_out, d_in);
counter=counter+2;
}
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
for(int i=0; i<N; i++)
{
for(int j=0; j<M; j++)
{
fprintf(writefile,"%e\t", h_out[i * M + j]);
}
fprintf(writefile, "\n");
}
fclose(writefile);
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z9heat_stepPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fe4000f8e023f */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0090*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x002fc800078e0202 */
/*00d0*/ IMAD R5, R7, UR4, R0 ; /* 0x0000000407057c24 */
/* 0x000fc8000f8e0200 */
/*00e0*/ IMAD.WIDE R2, R5, R4, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0204 */
/*00f0*/ @P0 IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b0810 */
/* 0x000fe20007ffe0ff */
/*0100*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101908 */
/*0110*/ @P0 IMAD.WIDE R10, R11, R4, c[0x0][0x168] ; /* 0x00005a000b0a0625 */
/* 0x000fca00078e0204 */
/*0120*/ @P0 LDG.E R8, [R10.64] ; /* 0x000000080a080981 */
/* 0x000ea2000c1e1900 */
/*0130*/ UIADD3 UR6, UR4, -0x1, URZ ; /* 0xffffffff04067890 */
/* 0x000fcc000fffe03f */
/*0140*/ ISETP.GE.AND P1, PT, R0, UR6, PT ; /* 0x0000000600007c0c */
/* 0x000fda000bf26270 */
/*0150*/ @!P1 IMAD.WIDE R14, R5, R4, c[0x0][0x168] ; /* 0x00005a00050e9625 */
/* 0x000fe200078e0204 */
/*0160*/ @P0 F2F.F64.F32 R8, R8 ; /* 0x0000000800080310 */
/* 0x004e240000201800 */
/*0170*/ @P0 DFMA R12, R8, 0.25, RZ ; /* 0x3fd00000080c082b */
/* 0x00106400000000ff */
/*0180*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x001fcc0000000f00 */
/*0190*/ @P0 F2F.F32.F64 R9, R12 ; /* 0x0000000c00090310 */
/* 0x002e240000301000 */
/*01a0*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0011e8000c101908 */
/*01b0*/ @!P1 LDG.E R14, [R14.64+0x4] ; /* 0x000004080e0e9981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ @!P1 F2F.F64.F32 R16, R9 ; /* 0x0000000900109310 */
/* 0x000fe20000201800 */
/*01d0*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fce0003f06270 */
/*01e0*/ @!P1 F2F.F64.F32 R10, R14 ; /* 0x0000000e000a9310 */
/* 0x004e640000201800 */
/*01f0*/ @!P1 DFMA R10, R10, 0.25, R16 ; /* 0x3fd000000a0a982b */
/* 0x0022080000000010 */
/*0200*/ @P0 IADD3 R17, R5, -UR4, RZ ; /* 0x8000000405110c10 */
/* 0x002fe4000fffe0ff */
/*0210*/ @!P1 F2F.F32.F64 R9, R10 ; /* 0x0000000a00099310 */
/* 0x001e260000301000 */
/*0220*/ @P0 IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011100625 */
/* 0x000fe200078e0204 */
/*0230*/ @!P1 STG.E [R2.64], R9 ; /* 0x0000000902009986 */
/* 0x0011ea000c101908 */
/*0240*/ @P0 LDG.E R16, [R16.64] ; /* 0x0000000810100981 */
/* 0x000ea2000c1e1900 */
/*0250*/ @P0 F2F.F64.F32 R18, R9 ; /* 0x0000000900120310 */
/* 0x000fe20000201800 */
/*0260*/ ULDC UR6, c[0x0][0x10] ; /* 0x0000040000067ab9 */
/* 0x000fc40000000800 */
/*0270*/ UIMAD UR5, UR5, UR6, -0x1 ; /* 0xffffffff050574a4 */
/* 0x000fcc000f8e0206 */
/*0280*/ ISETP.GE.AND P1, PT, R7, UR5, PT ; /* 0x0000000507007c0c */
/* 0x000fda000bf26270 */
/*0290*/ @!P1 IADD3 R5, R5, UR4, RZ ; /* 0x0000000405059c10 */
/* 0x000fca000fffe0ff */
/*02a0*/ @!P1 IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005049625 */
/* 0x000fe200078e0204 */
/*02b0*/ @P0 F2F.F64.F32 R12, R16 ; /* 0x00000010000c0310 */
/* 0x004e640000201800 */
/*02c0*/ @P0 DFMA R12, R12, 0.25, R18 ; /* 0x3fd000000c0c082b */
/* 0x002e0c0000000012 */
/*02d0*/ @P0 F2F.F32.F64 R9, R12 ; /* 0x0000000c00090310 */
/* 0x001e240000301000 */
/*02e0*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0011e8000c101908 */
/*02f0*/ @!P1 LDG.E R4, [R4.64] ; /* 0x0000000804049981 */
/* 0x000ea4000c1e1900 */
/*0300*/ @!P1 F2F.F64.F32 R10, R9 ; /* 0x00000009000a9310 */
/* 0x000fe20000201800 */
/*0310*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f05270 */
/*0320*/ @!P1 F2F.F64.F32 R6, R4 ; /* 0x0000000400069310 */
/* 0x004e640000201800 */
/*0330*/ @!P1 DFMA R6, R6, 0.25, R10 ; /* 0x3fd000000606982b */
/* 0x002e54000000000a */
/*0340*/ @!P1 F2F.F32.F64 R7, R6 ; /* 0x0000000600079310 */
/* 0x002e640000301000 */
/*0350*/ @!P1 STG.E [R2.64], R7 ; /* 0x0000000702009986 */
/* 0x0021e2000c101908 */
/*0360*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0370*/ MOV R5, 0x3f800000 ; /* 0x3f80000000057802 */
/* 0x000fca0000000f00 */
/*0380*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*0390*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03a0*/ BRA 0x3a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
__global__ void heat_step(float * d_out, float * d_in)
{
// int block_x = blockIdx.x;
// int block_y = blockIdx.y;
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
d_out[location] = 0;
if (x_glob > 0)
{
d_out[location] += 0.25 * d_in[location - 1];
}
if (x_glob < (x_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + 1];
}
if (y_glob > 0)
{
d_out[location] += 0.25 * d_in[location - x_total_dim];
}
if (y_glob < (y_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + x_total_dim];
}
if (x_glob == 0)
{
d_out[location] = 1;
}
}
int main()
{
const int N=200;
const int M=200;
const int ARRAY_SIZE = N * M;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int Niter = 1000;
size_t counter = 0;
FILE * writefile;
writefile=fopen("out_laplace.txt", "w");
float h_start[ARRAY_SIZE];
for(int i=0; i<ARRAY_SIZE; i++)
{
h_start[i] = 0;
}
float h_out[ARRAY_SIZE];
float * d_in;
float * d_out;
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_out, ARRAY_BYTES);
cudaMemcpy(d_in, h_start, ARRAY_BYTES, cudaMemcpyHostToDevice);
while (counter<Niter)
{
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_in, d_out);
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_out, d_in);
counter=counter+2;
}
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
for(int i=0; i<N; i++)
{
for(int j=0; j<M; j++)
{
fprintf(writefile,"%e\t", h_out[i * M + j]);
}
fprintf(writefile, "\n");
}
fclose(writefile);
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | .file "tmpxft_000d2aa7_00000000-6_laplace_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9heat_stepPfS_PfS_
.type _Z30__device_stub__Z9heat_stepPfS_PfS_, @function
_Z30__device_stub__Z9heat_stepPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9heat_stepPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9heat_stepPfS_PfS_, .-_Z30__device_stub__Z9heat_stepPfS_PfS_
.globl _Z9heat_stepPfS_
.type _Z9heat_stepPfS_, @function
_Z9heat_stepPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9heat_stepPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9heat_stepPfS_, .-_Z9heat_stepPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "out_laplace.txt"
.LC3:
.string "%e\t"
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -319488(%rsp), %r11
.cfi_def_cfa 11, 319544
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $584, %rsp
.cfi_def_cfa_offset 320128
movq %fs:40, %rax
movq %rax, 320056(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r12
leaq 48(%rsp), %rax
leaq 160048(%rsp), %rdx
.L12:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $160000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $160000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $160000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $500, %ebx
jmp .L15
.L25:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9heat_stepPfS_PfS_
jmp .L13
.L14:
subq $1, %rbx
je .L24
.L15:
movl $20, 36(%rsp)
movl $20, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L13:
movl $20, 36(%rsp)
movl $20, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9heat_stepPfS_PfS_
jmp .L14
.L24:
leaq 160048(%rsp), %rdi
movl $2, %ecx
movl $160000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 160848(%rsp), %rbp
leaq 320848(%rsp), %r15
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r14
.L16:
leaq -800(%rbp), %rbx
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $800, %rbp
cmpq %r15, %rbp
jne .L16
movq %r12, %rdi
call fclose@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 320056(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $320072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9heat_stepPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9heat_stepPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
__global__ void heat_step(float * d_out, float * d_in)
{
// int block_x = blockIdx.x;
// int block_y = blockIdx.y;
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
d_out[location] = 0;
if (x_glob > 0)
{
d_out[location] += 0.25 * d_in[location - 1];
}
if (x_glob < (x_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + 1];
}
if (y_glob > 0)
{
d_out[location] += 0.25 * d_in[location - x_total_dim];
}
if (y_glob < (y_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + x_total_dim];
}
if (x_glob == 0)
{
d_out[location] = 1;
}
}
int main()
{
const int N=200;
const int M=200;
const int ARRAY_SIZE = N * M;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int Niter = 1000;
size_t counter = 0;
FILE * writefile;
writefile=fopen("out_laplace.txt", "w");
float h_start[ARRAY_SIZE];
for(int i=0; i<ARRAY_SIZE; i++)
{
h_start[i] = 0;
}
float h_out[ARRAY_SIZE];
float * d_in;
float * d_out;
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_out, ARRAY_BYTES);
cudaMemcpy(d_in, h_start, ARRAY_BYTES, cudaMemcpyHostToDevice);
while (counter<Niter)
{
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_in, d_out);
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_out, d_in);
counter=counter+2;
}
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
for(int i=0; i<N; i++)
{
for(int j=0; j<M; j++)
{
fprintf(writefile,"%e\t", h_out[i * M + j]);
}
fprintf(writefile, "\n");
}
fclose(writefile);
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
__global__ void heat_step(float * d_out, float * d_in)
{
// int block_x = blockIdx.x;
// int block_y = blockIdx.y;
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
d_out[location] = 0;
if (x_glob > 0)
{
d_out[location] += 0.25 * d_in[location - 1];
}
if (x_glob < (x_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + 1];
}
if (y_glob > 0)
{
d_out[location] += 0.25 * d_in[location - x_total_dim];
}
if (y_glob < (y_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + x_total_dim];
}
if (x_glob == 0)
{
d_out[location] = 1;
}
}
int main()
{
const int N=200;
const int M=200;
const int ARRAY_SIZE = N * M;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int Niter = 1000;
size_t counter = 0;
FILE * writefile;
writefile=fopen("out_laplace.txt", "w");
float h_start[ARRAY_SIZE];
for(int i=0; i<ARRAY_SIZE; i++)
{
h_start[i] = 0;
}
float h_out[ARRAY_SIZE];
float * d_in;
float * d_out;
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_out, ARRAY_BYTES);
hipMemcpy(d_in, h_start, ARRAY_BYTES, hipMemcpyHostToDevice);
while (counter<Niter)
{
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_in, d_out);
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_out, d_in);
counter=counter+2;
}
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
for(int i=0; i<N; i++)
{
for(int j=0; j<M; j++)
{
fprintf(writefile,"%e\t", h_out[i * M + j]);
}
fprintf(writefile, "\n");
}
fclose(writefile);
hipFree(d_in);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
__global__ void heat_step(float * d_out, float * d_in)
{
// int block_x = blockIdx.x;
// int block_y = blockIdx.y;
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
d_out[location] = 0;
if (x_glob > 0)
{
d_out[location] += 0.25 * d_in[location - 1];
}
if (x_glob < (x_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + 1];
}
if (y_glob > 0)
{
d_out[location] += 0.25 * d_in[location - x_total_dim];
}
if (y_glob < (y_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + x_total_dim];
}
if (x_glob == 0)
{
d_out[location] = 1;
}
}
int main()
{
const int N=200;
const int M=200;
const int ARRAY_SIZE = N * M;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int Niter = 1000;
size_t counter = 0;
FILE * writefile;
writefile=fopen("out_laplace.txt", "w");
float h_start[ARRAY_SIZE];
for(int i=0; i<ARRAY_SIZE; i++)
{
h_start[i] = 0;
}
float h_out[ARRAY_SIZE];
float * d_in;
float * d_out;
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_out, ARRAY_BYTES);
hipMemcpy(d_in, h_start, ARRAY_BYTES, hipMemcpyHostToDevice);
while (counter<Niter)
{
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_in, d_out);
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_out, d_in);
counter=counter+2;
}
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
for(int i=0; i<N; i++)
{
for(int j=0; j<M; j++)
{
fprintf(writefile,"%e\t", h_out[i * M + j]);
}
fprintf(writefile, "\n");
}
fclose(writefile);
hipFree(d_in);
hipFree(d_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9heat_stepPfS_
.globl _Z9heat_stepPfS_
.p2align 8
.type _Z9heat_stepPfS_,@function
_Z9heat_stepPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
v_mov_b32_e32 v8, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s6, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s7, v[2:3]
v_mad_u64_u32 v[5:6], null, s15, s6, v[3:4]
s_mul_i32 s4, s4, s7
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, s4, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v7, vcc_lo
s_mov_b32 s0, exec_lo
global_store_b32 v[1:2], v8, off
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_2
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v6, v[6:7], off offset:-4
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], 0x3fd00000, 0
v_cvt_f32_f64_e32 v6, v[6:7]
global_store_b32 v[1:2], v6, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s0, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s0, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_4
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v4, v[6:7], off offset:4
global_load_b32 v8, v[1:2], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[6:7], v4
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], 0x3fd00000, v[8:9]
v_cvt_f32_f64_e32 v4, v[6:7]
global_store_b32 v[1:2], v4, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 0, v5
s_cbranch_execz .LBB0_6
v_subrev_nc_u32_e32 v6, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v4, v[6:7], off
global_load_b32 v8, v[1:2], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[6:7], v4
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], 0x3fd00000, v[8:9]
v_cvt_f32_f64_e32 v4, v[6:7]
global_store_b32 v[1:2], v4, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
s_mul_i32 s0, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, -1
v_cmp_gt_i32_e32 vcc_lo, s0, v5
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v3, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[3:4], v3
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[3:4], 0x3fd00000, v[5:6]
v_cvt_f32_f64_e32 v3, v[3:4]
global_store_b32 v[1:2], v3, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 1.0
global_store_b32 v[1:2], v0, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9heat_stepPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9heat_stepPfS_, .Lfunc_end0-_Z9heat_stepPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9heat_stepPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9heat_stepPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
__global__ void heat_step(float * d_out, float * d_in)
{
// int block_x = blockIdx.x;
// int block_y = blockIdx.y;
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
d_out[location] = 0;
if (x_glob > 0)
{
d_out[location] += 0.25 * d_in[location - 1];
}
if (x_glob < (x_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + 1];
}
if (y_glob > 0)
{
d_out[location] += 0.25 * d_in[location - x_total_dim];
}
if (y_glob < (y_total_dim - 1))
{
d_out[location] += 0.25 * d_in[location + x_total_dim];
}
if (x_glob == 0)
{
d_out[location] = 1;
}
}
int main()
{
const int N=200;
const int M=200;
const int ARRAY_SIZE = N * M;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int Niter = 1000;
size_t counter = 0;
FILE * writefile;
writefile=fopen("out_laplace.txt", "w");
float h_start[ARRAY_SIZE];
for(int i=0; i<ARRAY_SIZE; i++)
{
h_start[i] = 0;
}
float h_out[ARRAY_SIZE];
float * d_in;
float * d_out;
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_out, ARRAY_BYTES);
hipMemcpy(d_in, h_start, ARRAY_BYTES, hipMemcpyHostToDevice);
while (counter<Niter)
{
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_in, d_out);
heat_step<<<dim3(10,10), dim3(N/10,M/10)>>>(d_out, d_in);
counter=counter+2;
}
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
for(int i=0; i<N; i++)
{
for(int j=0; j<M; j++)
{
fprintf(writefile,"%e\t", h_out[i * M + j]);
}
fprintf(writefile, "\n");
}
fclose(writefile);
hipFree(d_in);
hipFree(d_out);
return 0;
} | .text
.file "laplace_cuda.hip"
.globl _Z24__device_stub__heat_stepPfS_ # -- Begin function _Z24__device_stub__heat_stepPfS_
.p2align 4, 0x90
.type _Z24__device_stub__heat_stepPfS_,@function
_Z24__device_stub__heat_stepPfS_: # @_Z24__device_stub__heat_stepPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9heat_stepPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__heat_stepPfS_, .Lfunc_end0-_Z24__device_stub__heat_stepPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $320088, %rsp # imm = 0x4E258
.cfi_def_cfa_offset 320144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $85899345940, %r15 # imm = 0x1400000014
movabsq $42949672970, %r12 # imm = 0xA0000000A
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
leaq 160080(%rsp), %r14
movl $160000, %edx # imm = 0x27100
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdi
movl $160000, %esi # imm = 0x27100
callq hipMalloc
movq %rsp, %rdi
movl $160000, %esi # imm = 0x27100
callq hipMalloc
movq 8(%rsp), %rdi
movl $160000, %edx # imm = 0x27100
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq $-2, %r13
leaq 72(%rsp), %rbp
leaq 80(%rsp), %r14
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
addq $2, %r13
cmpq $998, %r13 # imm = 0x3E6
jae .LBB1_6
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z9heat_stepPfS_, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_1 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z9heat_stepPfS_, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movq (%rsp), %rsi
movl $160000, %edx # imm = 0x27100
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $200, %r12
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incq %r15
addq $800, %r14 # imm = 0x320
cmpq $200, %r15
jne .LBB1_7
# %bb.10:
movq %rbx, %rdi
callq fclose
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $320088, %rsp # imm = 0x4E258
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9heat_stepPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9heat_stepPfS_,@object # @_Z9heat_stepPfS_
.section .rodata,"a",@progbits
.globl _Z9heat_stepPfS_
.p2align 3, 0x0
_Z9heat_stepPfS_:
.quad _Z24__device_stub__heat_stepPfS_
.size _Z9heat_stepPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "out_laplace.txt"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%e\t"
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9heat_stepPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__heat_stepPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9heat_stepPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9heat_stepPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fe4000f8e023f */
/*0070*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0090*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x002fc800078e0202 */
/*00d0*/ IMAD R5, R7, UR4, R0 ; /* 0x0000000407057c24 */
/* 0x000fc8000f8e0200 */
/*00e0*/ IMAD.WIDE R2, R5, R4, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0204 */
/*00f0*/ @P0 IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b0810 */
/* 0x000fe20007ffe0ff */
/*0100*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101908 */
/*0110*/ @P0 IMAD.WIDE R10, R11, R4, c[0x0][0x168] ; /* 0x00005a000b0a0625 */
/* 0x000fca00078e0204 */
/*0120*/ @P0 LDG.E R8, [R10.64] ; /* 0x000000080a080981 */
/* 0x000ea2000c1e1900 */
/*0130*/ UIADD3 UR6, UR4, -0x1, URZ ; /* 0xffffffff04067890 */
/* 0x000fcc000fffe03f */
/*0140*/ ISETP.GE.AND P1, PT, R0, UR6, PT ; /* 0x0000000600007c0c */
/* 0x000fda000bf26270 */
/*0150*/ @!P1 IMAD.WIDE R14, R5, R4, c[0x0][0x168] ; /* 0x00005a00050e9625 */
/* 0x000fe200078e0204 */
/*0160*/ @P0 F2F.F64.F32 R8, R8 ; /* 0x0000000800080310 */
/* 0x004e240000201800 */
/*0170*/ @P0 DFMA R12, R8, 0.25, RZ ; /* 0x3fd00000080c082b */
/* 0x00106400000000ff */
/*0180*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x001fcc0000000f00 */
/*0190*/ @P0 F2F.F32.F64 R9, R12 ; /* 0x0000000c00090310 */
/* 0x002e240000301000 */
/*01a0*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0011e8000c101908 */
/*01b0*/ @!P1 LDG.E R14, [R14.64+0x4] ; /* 0x000004080e0e9981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ @!P1 F2F.F64.F32 R16, R9 ; /* 0x0000000900109310 */
/* 0x000fe20000201800 */
/*01d0*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fce0003f06270 */
/*01e0*/ @!P1 F2F.F64.F32 R10, R14 ; /* 0x0000000e000a9310 */
/* 0x004e640000201800 */
/*01f0*/ @!P1 DFMA R10, R10, 0.25, R16 ; /* 0x3fd000000a0a982b */
/* 0x0022080000000010 */
/*0200*/ @P0 IADD3 R17, R5, -UR4, RZ ; /* 0x8000000405110c10 */
/* 0x002fe4000fffe0ff */
/*0210*/ @!P1 F2F.F32.F64 R9, R10 ; /* 0x0000000a00099310 */
/* 0x001e260000301000 */
/*0220*/ @P0 IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011100625 */
/* 0x000fe200078e0204 */
/*0230*/ @!P1 STG.E [R2.64], R9 ; /* 0x0000000902009986 */
/* 0x0011ea000c101908 */
/*0240*/ @P0 LDG.E R16, [R16.64] ; /* 0x0000000810100981 */
/* 0x000ea2000c1e1900 */
/*0250*/ @P0 F2F.F64.F32 R18, R9 ; /* 0x0000000900120310 */
/* 0x000fe20000201800 */
/*0260*/ ULDC UR6, c[0x0][0x10] ; /* 0x0000040000067ab9 */
/* 0x000fc40000000800 */
/*0270*/ UIMAD UR5, UR5, UR6, -0x1 ; /* 0xffffffff050574a4 */
/* 0x000fcc000f8e0206 */
/*0280*/ ISETP.GE.AND P1, PT, R7, UR5, PT ; /* 0x0000000507007c0c */
/* 0x000fda000bf26270 */
/*0290*/ @!P1 IADD3 R5, R5, UR4, RZ ; /* 0x0000000405059c10 */
/* 0x000fca000fffe0ff */
/*02a0*/ @!P1 IMAD.WIDE R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005049625 */
/* 0x000fe200078e0204 */
/*02b0*/ @P0 F2F.F64.F32 R12, R16 ; /* 0x00000010000c0310 */
/* 0x004e640000201800 */
/*02c0*/ @P0 DFMA R12, R12, 0.25, R18 ; /* 0x3fd000000c0c082b */
/* 0x002e0c0000000012 */
/*02d0*/ @P0 F2F.F32.F64 R9, R12 ; /* 0x0000000c00090310 */
/* 0x001e240000301000 */
/*02e0*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0011e8000c101908 */
/*02f0*/ @!P1 LDG.E R4, [R4.64] ; /* 0x0000000804049981 */
/* 0x000ea4000c1e1900 */
/*0300*/ @!P1 F2F.F64.F32 R10, R9 ; /* 0x00000009000a9310 */
/* 0x000fe20000201800 */
/*0310*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f05270 */
/*0320*/ @!P1 F2F.F64.F32 R6, R4 ; /* 0x0000000400069310 */
/* 0x004e640000201800 */
/*0330*/ @!P1 DFMA R6, R6, 0.25, R10 ; /* 0x3fd000000606982b */
/* 0x002e54000000000a */
/*0340*/ @!P1 F2F.F32.F64 R7, R6 ; /* 0x0000000600079310 */
/* 0x002e640000301000 */
/*0350*/ @!P1 STG.E [R2.64], R7 ; /* 0x0000000702009986 */
/* 0x0021e2000c101908 */
/*0360*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0370*/ MOV R5, 0x3f800000 ; /* 0x3f80000000057802 */
/* 0x000fca0000000f00 */
/*0380*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*0390*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03a0*/ BRA 0x3a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9heat_stepPfS_
.globl _Z9heat_stepPfS_
.p2align 8
.type _Z9heat_stepPfS_,@function
_Z9heat_stepPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
v_mov_b32_e32 v8, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s6, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s7, v[2:3]
v_mad_u64_u32 v[5:6], null, s15, s6, v[3:4]
s_mul_i32 s4, s4, s7
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, s4, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v7, vcc_lo
s_mov_b32 s0, exec_lo
global_store_b32 v[1:2], v8, off
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_2
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v6, v[6:7], off offset:-4
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[6:7], v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], 0x3fd00000, 0
v_cvt_f32_f64_e32 v6, v[6:7]
global_store_b32 v[1:2], v6, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s0, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s0, v0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_4
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v4, v[6:7], off offset:4
global_load_b32 v8, v[1:2], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[6:7], v4
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], 0x3fd00000, v[8:9]
v_cvt_f32_f64_e32 v4, v[6:7]
global_store_b32 v[1:2], v4, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_lt_i32_e32 0, v5
s_cbranch_execz .LBB0_6
v_subrev_nc_u32_e32 v6, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v4, v[6:7], off
global_load_b32 v8, v[1:2], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[6:7], v4
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], 0x3fd00000, v[8:9]
v_cvt_f32_f64_e32 v4, v[6:7]
global_store_b32 v[1:2], v4, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
s_mul_i32 s0, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, -1
v_cmp_gt_i32_e32 vcc_lo, s0, v5
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v3, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[3:4], v3
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[3:4], 0x3fd00000, v[5:6]
v_cvt_f32_f64_e32 v3, v[3:4]
global_store_b32 v[1:2], v3, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 1.0
global_store_b32 v[1:2], v0, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9heat_stepPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9heat_stepPfS_, .Lfunc_end0-_Z9heat_stepPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9heat_stepPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9heat_stepPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d2aa7_00000000-6_laplace_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9heat_stepPfS_PfS_
.type _Z30__device_stub__Z9heat_stepPfS_PfS_, @function
_Z30__device_stub__Z9heat_stepPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9heat_stepPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9heat_stepPfS_PfS_, .-_Z30__device_stub__Z9heat_stepPfS_PfS_
.globl _Z9heat_stepPfS_
.type _Z9heat_stepPfS_, @function
_Z9heat_stepPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9heat_stepPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9heat_stepPfS_, .-_Z9heat_stepPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "out_laplace.txt"
.LC3:
.string "%e\t"
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -319488(%rsp), %r11
.cfi_def_cfa 11, 319544
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $584, %rsp
.cfi_def_cfa_offset 320128
movq %fs:40, %rax
movq %rax, 320056(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r12
leaq 48(%rsp), %rax
leaq 160048(%rsp), %rdx
.L12:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $160000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $160000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $160000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $500, %ebx
jmp .L15
.L25:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9heat_stepPfS_PfS_
jmp .L13
.L14:
subq $1, %rbx
je .L24
.L15:
movl $20, 36(%rsp)
movl $20, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L13:
movl $20, 36(%rsp)
movl $20, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9heat_stepPfS_PfS_
jmp .L14
.L24:
leaq 160048(%rsp), %rdi
movl $2, %ecx
movl $160000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 160848(%rsp), %rbp
leaq 320848(%rsp), %r15
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r14
.L16:
leaq -800(%rbp), %rbx
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $800, %rbp
cmpq %r15, %rbp
jne .L16
movq %r12, %rdi
call fclose@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 320056(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $320072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9heat_stepPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9heat_stepPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "laplace_cuda.hip"
.globl _Z24__device_stub__heat_stepPfS_ # -- Begin function _Z24__device_stub__heat_stepPfS_
.p2align 4, 0x90
.type _Z24__device_stub__heat_stepPfS_,@function
_Z24__device_stub__heat_stepPfS_: # @_Z24__device_stub__heat_stepPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9heat_stepPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__heat_stepPfS_, .Lfunc_end0-_Z24__device_stub__heat_stepPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $320088, %rsp # imm = 0x4E258
.cfi_def_cfa_offset 320144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $85899345940, %r15 # imm = 0x1400000014
movabsq $42949672970, %r12 # imm = 0xA0000000A
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
leaq 160080(%rsp), %r14
movl $160000, %edx # imm = 0x27100
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdi
movl $160000, %esi # imm = 0x27100
callq hipMalloc
movq %rsp, %rdi
movl $160000, %esi # imm = 0x27100
callq hipMalloc
movq 8(%rsp), %rdi
movl $160000, %edx # imm = 0x27100
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq $-2, %r13
leaq 72(%rsp), %rbp
leaq 80(%rsp), %r14
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
addq $2, %r13
cmpq $998, %r13 # imm = 0x3E6
jae .LBB1_6
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z9heat_stepPfS_, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_1 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z9heat_stepPfS_, %edi
movq %r14, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movq (%rsp), %rsi
movl $160000, %edx # imm = 0x27100
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq $200, %r12
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incq %r15
addq $800, %r14 # imm = 0x320
cmpq $200, %r15
jne .LBB1_7
# %bb.10:
movq %rbx, %rdi
callq fclose
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $320088, %rsp # imm = 0x4E258
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9heat_stepPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9heat_stepPfS_,@object # @_Z9heat_stepPfS_
.section .rodata,"a",@progbits
.globl _Z9heat_stepPfS_
.p2align 3, 0x0
_Z9heat_stepPfS_:
.quad _Z24__device_stub__heat_stepPfS_
.size _Z9heat_stepPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "out_laplace.txt"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%e\t"
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9heat_stepPfS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__heat_stepPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9heat_stepPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <math.h>
#include <limits.h>
#include <float.h>
#include <iostream>
#include <sys/time.h>
#define G 6.67408E-11 //Gravitational constant
#define lvl 9 //depth of quad tree till which we'll divide plane
using namespace std;
struct vect //Structure for 2D coordinate
{
float x; //X coordinate
float y; //Y coordinate
};
struct node //Structure for each node of the quad tree
{
vect body; //centre of mass of bodies in current node
float mass; //total mass of bodies in current node
int child[4]; //children indices in nodes array
int l,r; //index limit in body array of bodies in current node
vect min, max; //min and max X and Y coordinates of bodies belonging to current node
};
//Function to calculate Gravitational force between two bodies
__device__ vect gravity (vect a, vect b, float m1, float m2)
{
float res=G*m1*m2;
float r=(a.y-b.y)*(a.y-b.y)+(a.x-b.x)*(a.x-b.x);
if (r>0) res/=r;
vect vec;
vec.y=a.y-b.y;
vec.x=a.x-b.x;
r=sqrt(r);
if (r>0) vec.y/=r, vec.x/=r;
vec.y*=res;
vec.x*=res;
return vec;
}
//part1 for kernel1 to find min-max among the n bodies
//Will find min and max of X and Y coordinates for each thread lock
//Uses reduction technique
__global__ void findMinMax(vect * body, vect * min, vect * max, int n)
{
__shared__ vect min_cache[32];
__shared__ vect max_cache[32];
int index=threadIdx.x+blockDim.x*blockIdx.x;
float xmin=FLT_MAX, ymin=FLT_MAX;
float xmax=FLT_MIN, ymax=FLT_MIN;
while (index<n) //takes care if total number greater than total threads in kernel
{
xmin=fmin(xmin, body[index].x);
ymin=fmin(ymin, body[index].y);
xmax=fmax(xmax, body[index].x);
ymax=fmax(ymax, body[index].y);
index+=(blockDim.x*gridDim.x); //incrementing index by total number of threads in kernel, to take care if total number more than total threads in kernel
}
int tid=threadIdx.x;
min_cache[tid].x=xmin;
min_cache[tid].y=ymin;
max_cache[tid].x=xmax;
max_cache[tid].y=ymax;
int active=blockDim.x>>1;
do
{
__syncthreads();
if (tid<active) //reduction
{
min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);
max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
}
active>>=1;
}while (active>0);
if (tid==0) min[blockIdx.x]=min_cache[0], max[blockIdx.x]=max_cache[0];
}
//part2 for kernel1 to find min-max among the n bodies
//Will find global min and max of X and Y coordinates from local min and max of above kernel
__global__ void findMMinMax(vect * mmin, vect *mmax, vect * min, vect * max, int n)
{
__shared__ vect min_cache[32];
__shared__ vect max_cache[32];
int index=threadIdx.x+blockDim.x*blockIdx.x;
float xmin=FLT_MAX, ymin=FLT_MAX;
float xmax=FLT_MIN, ymax=FLT_MIN;
while (index<n) //takes care if total number greater than total threads in kernel
{
xmin=fmin(xmin, min[index].x);
ymin=fmin(ymin, min[index].y);
xmax=fmax(xmax, max[index].x);
ymax=fmax(ymax, max[index].y);
index+=(blockDim.x*gridDim.x);
}
int tid=threadIdx.x;
min_cache[tid].x=xmin;
min_cache[tid].y=ymin;
max_cache[tid].x=xmax;
max_cache[tid].y=ymax;
int active=blockDim.x>>1;
do
{
__syncthreads();
if (tid<active) //reduction
{
min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);
max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
}
active>>=1;
}while (active>0);
if (tid==0) mmin[blockIdx.x]=min_cache[0], mmax[blockIdx.x]=max_cache[0];
}
//This function will construct particular level of the tree.
//Each node will be divided further into four new nodes and bodies in the array will be swapped so that bodies belonging to same node remain together in the array
//This will work as kernel 2
__global__ void construct(vect *body, float *mass, node *nodes, int level, int tot)
{
int index=blockDim.x*blockIdx.x+threadIdx.x;
int tid=index*4;
int total = 1<<(2*level); //total nodes in current level
int offset=((1<<(2*level))-1)/3; //total nodes in tree upto previous level
int off=offset+total; //total nodes in tree upto current level
while (index<total) //'while' loop will take care if total number more than total threads in kernel
{
index+=offset; //actual index in nodes array
node nd=nodes[index];
if (nodes[index].l<=nodes[index].r)
{
float xl=nd.min.x, xr=nd.max.x;
float yl=nd.min.y, yr=nd.max.y;
float xmid=xl+(xr-xl)/2;
float ymid=yl+(yr-yl)/2;
float l=nd.l, r=nd.r;
node child[4];
for (int i=0;i<4;i++)
{
child[i].min.x=child[i].min.y=FLT_MAX, child[i].max.x=child[i].max.y=FLT_MIN;
for (int j=0;j<4;j++) child[i].child[j]=-1;
}
int i=l-1;
float m=0, x=0, y=0, mm=0, xx=0, yy=0;
for (int j=l;j<=r;j++) //swapping of bodies belonging to current node based on x-coordinates creating two children
{
if (body[j].x<=xmid)
{
i++;
vect temp=body[i];
body[i]=body[j];
body[j]=temp;
float t=mass[i];
mass[i]=mass[j];
mass[j]=t;
}
}
child[2].l=l, child[2].r=i;
child[3].l=i+1, child[3].r=r;
for (int k=2;k<=3;k++)
{
m=mm=x=xx=y=yy=0;
l=child[k].l, r=child[k].r;
i=l-1;
int cnt=0;
for (int j=l;j<=r;j++) //swapping of bodies in two children created previously based on y-coordinates, each creating two new children
{
x+=body[j].x;
y+=body[j].y;
m+=mass[j];
if (body[j].y<=ymid)
{
xx+=body[j].x, yy+=body[j].y, mm+=mass[j];
cnt++;
i++;
vect temp=body[i];
body[i]=body[j];
body[j]=temp;
float t=mass[i];
mass[i]=mass[j];
mass[j]=t;
}
}
if(cnt>0) child[k].mass=mm, child[k].body.x=xx/cnt, child[k].body.y=yy/cnt;
child[k].l=l, child[k].r=i;
mm=m-mm, xx=x-xx, yy=y-yy, cnt=r-l+1-cnt;
if(cnt>0) child[k-2].mass=mm, child[k-2].body.x=xx/cnt, child[k-2].body.y=yy/cnt;
child[k-2].l=i+1, child[k-2].r=r;
}
for (int i=0;i<4;i++)
{
if (i%2) child[i].min.x=xmid, child[i].max.x=xr;
else child[i].min.x=xl, child[i].max.x=xmid;
if (i<2) child[i].min.y=ymid, child[i].max.y=yr;
else child[i].min.y=yl, child[i].max.y=ymid;
if (off+tid+i<tot) nodes[off+tid+i]=child[i];
nd.child[i]=off+tid+i;
}
}
else
{
for (int i=0;i<4;i++)
{
if (off+tid+i<tot)
{
nodes[off+tid+i].l=0;
nodes[off+tid+i].r=-1;
}
nd.child[i]=off+tid+i;
}
}
nodes[index]=nd;
index-=offset;
index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total threads.
}
}
//This is kernel 3
//This function calculates force on bodies
__global__ void calculate(vect *body, float *mass, node *nodes, vect *force, int n, float theta)
{
int index=blockDim.x*blockIdx.x+threadIdx.x;
int l=((1<<(2*(lvl-1)))-1)/3; //total nodes in tree upto max depth
while (index<n) //'while' loop takes care if total number more than total threads in kernel
{
int st[4*(lvl)]; //using array as stack
int curr=0; //variable showing current top index
st[curr]=0;
vect bd=body[index];
while (curr>=0) //for each body do DFS until reached leaf
{
int t=st[curr];
curr--;
node nd=nodes[t];
float s=fmax(nd.max.x-nd.min.x, nd.max.y-nd.min.y);
float x=bd.x-nd.body.x, y=bd.y-nd.body.y;
float dist=sqrt(x*x+y*y);
float val=FLT_MAX;
if (dist>0) val=s/dist;
if (val<theta) //Barnes-Hutt approximation
{
vect frc=gravity(nd.body, bd, nd.mass, mass[index]);
force[index].x+=frc.x;
force[index].y+=frc.y;
}
else
{
if (t>=l) //if reached leaf
{
vect frc=gravity(nd.body, bd, nd.mass, mass[index]);
force[index].x+=frc.x;
force[index].y+=frc.y;
continue;
}
for (int i=0;i<4;i++)
{
int temp=nd.child[i];
if (temp==-1 || nodes[temp].l>nodes[temp].r) continue;
st[++curr]=temp;
}
}
}
index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total number of threads in kernel
}
}
float maxx(float a, float b)
{
return (a<b?b:a);
}
float minn(float a, float b)
{
return (a<b?a:b);
}
int main()
{
int n;
printf("n : ");
scanf("%d", &n);
vect body[n];
float mass[n];
float m=0, x=0, y=0;
for (int i=0;i<n;i++)
{
body[i].x=rand()%1000000;
body[i].y=rand()%1000000;
mass[i]=rand()%1000000;
m+=mass[i], x+=body[i].x, y+=body[i].y;
}
x/=n, y/=n; //centre of mass of the whole system
vect force[n];
vect *min;
vect *max;
for (int i=0;i<n;i++) force[i].x=force[i].y=0;
vect *dforce;
vect *dbody;
float *dmass;
int s=sizeof(vect)*n;
int sz=sizeof(float)*n;
cudaMalloc(&dbody, s);
cudaMalloc(&dmass, sz);
cudaMalloc(&dforce, s);
cudaMemset(dforce, 0, s);
cudaMalloc(&min, s);
cudaMalloc(&max, s);
cudaMemcpy(dbody, body, s, cudaMemcpyHostToDevice);
cudaMemcpy(dmass, mass, sz, cudaMemcpyHostToDevice);
int val=32;
int block = val;
int grid = val;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
//This is kernel 1 which devided into 2 parts
//bassically it find minimum and maximum from
//the n bodies
findMinMax<<<grid, block>>>(dbody, min, max, n);
findMMinMax<<<1, block>>>(min, max, min, max, val);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
//milliseconds find the total kernal time in GPU
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
vect gmin;
vect gmax;
cudaMemcpy(&gmin, min, sizeof(vect), cudaMemcpyDeviceToHost);
cudaMemcpy(&gmax, max, sizeof(vect), cudaMemcpyDeviceToHost);
int curr=1;
int tot=1<<(2*lvl);
tot=(tot-1)/3;
node h_nodes[tot];
for (int i=0;i<tot;i++)
{
for (int j=0;j<4;j++) h_nodes[i].child[j]=-1;
}
vect temp;
temp.x=x, temp.y=y;
h_nodes[0].body=temp, h_nodes[0].mass=m, h_nodes[0].l=0, h_nodes[0].r=n-1, h_nodes[0].min=gmin, h_nodes[0].max=gmax;
node *d_nodes;
cudaMalloc(&d_nodes, sizeof(node)*tot);
cudaMemcpy(d_nodes, h_nodes, sizeof(node)*tot, cudaMemcpyHostToDevice);
float t;
for (int i=0;i<lvl-1;i++) //creation of tree level by level. Each thread is assigned a node in current level.
{
block = 1024;
grid=ceil((1.0*curr)/block);
grid = minn(grid, 20);
cudaEventRecord(start);
construct<<<grid, block>>>(dbody, dmass, d_nodes, i, tot);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&t, start, stop);
milliseconds+=t;
curr*=4;
}
cudaMemcpy(h_nodes, d_nodes, sizeof(node)*tot, cudaMemcpyDeviceToHost);
float theta;
printf("theta : ");
scanf("%f", &theta);
grid=minn(20, ceil((1.0*n)/block));
printf("%d\n", grid);
cudaEventRecord(start);
calculate<<<grid, block>>>(dbody, dmass, d_nodes, dforce, n, theta); //Each thread is assigned a body
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&t, start, stop);
milliseconds+=t;
cudaMemcpy(force, dforce, s, cudaMemcpyDeviceToHost);
cudaMemcpy(body, dbody, s, cudaMemcpyDeviceToHost);
cudaMemcpy(mass, dmass, sz, cudaMemcpyDeviceToHost);
x=0, y=0;
for(int i=0;i<n;i++)
{
printf("force %d : x %f y %f m %f : %.15f %.15f\n", i, body[i].x, body[i].y, mass[i], force[i].x, force[i].y);
x+=force[i].x, y+=force[i].y;
}
printf("gpu time : %f\n", milliseconds);
printf("x %f y %f\n", x, y);
} | .file "tmpxft_000d922b_00000000-6_main1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7gravity4vectS_ff
.type _Z7gravity4vectS_ff, @function
_Z7gravity4vectS_ff:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z7gravity4vectS_ff, .-_Z7gravity4vectS_ff
.globl _Z4maxxff
.type _Z4maxxff, @function
_Z4maxxff:
.LFB3670:
.cfi_startproc
endbr64
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
ret
.cfi_endproc
.LFE3670:
.size _Z4maxxff, .-_Z4maxxff
.globl _Z4minnff
.type _Z4minnff, @function
_Z4minnff:
.LFB3671:
.cfi_startproc
endbr64
minss %xmm1, %xmm0
ret
.cfi_endproc
.LFE3671:
.size _Z4minnff, .-_Z4minnff
.globl _Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i
.type _Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i, @function
_Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10findMinMaxP4vectS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i, .-_Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i
.globl _Z10findMinMaxP4vectS0_S0_i
.type _Z10findMinMaxP4vectS0_S0_i, @function
_Z10findMinMaxP4vectS0_S0_i:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z10findMinMaxP4vectS0_S0_i, .-_Z10findMinMaxP4vectS0_S0_i
.globl _Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i
.type _Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i, @function
_Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i:
.LFB3699:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11findMMinMaxP4vectS0_S0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i, .-_Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i
.globl _Z11findMMinMaxP4vectS0_S0_S0_i
.type _Z11findMMinMaxP4vectS0_S0_S0_i, @function
_Z11findMMinMaxP4vectS0_S0_S0_i:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z11findMMinMaxP4vectS0_S0_S0_i, .-_Z11findMMinMaxP4vectS0_S0_S0_i
.globl _Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii
.type _Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii, @function
_Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii:
.LFB3701:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9constructP4vectPfP4nodeii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii, .-_Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii
.globl _Z9constructP4vectPfP4nodeii
.type _Z9constructP4vectPfP4nodeii, @function
_Z9constructP4vectPfP4nodeii:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z9constructP4vectPfP4nodeii, .-_Z9constructP4vectPfP4nodeii
.globl _Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if
.type _Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if, @function
_Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if:
.LFB3703:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9calculateP4vectPfP4nodeS0_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if, .-_Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if
.globl _Z9calculateP4vectPfP4nodeS0_if
.type _Z9calculateP4vectPfP4nodeS0_if, @function
_Z9calculateP4vectPfP4nodeS0_if:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z9calculateP4vectPfP4nodeS0_if, .-_Z9calculateP4vectPfP4nodeS0_if
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "n : "
.LC3:
.string "%d"
.LC8:
.string "theta : "
.LC9:
.string "%f"
.LC10:
.string "%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "force %d : x %f y %f m %f : %.15f %.15f\n"
.section .rodata.str1.1
.LC12:
.string "gpu time : %f\n"
.LC13:
.string "x %f y %f\n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $168, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq -176(%rbp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl -176(%rbp), %ecx
movslq %ecx, %r13
leaq 0(,%r13,8), %rax
leaq 15(%rax), %rdx
movq %rdx, %rsi
andq $-16, %rsi
andq $-4096, %rdx
movq %rsp, %rdi
subq %rdx, %rdi
.L46:
cmpq %rdi, %rsp
je .L47
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L46
.L47:
movq %rsi, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L48
orq $0, -8(%rsp,%rdx)
.L48:
movq %rsp, %rbx
leaq 15(,%r13,4), %rsi
movq %rsi, %rdx
andq $-16, %rdx
andq $-4096, %rsi
movq %rsp, %rdi
subq %rsi, %rdi
.L49:
cmpq %rdi, %rsp
je .L50
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L49
.L50:
movq %rdx, %rsi
andl $4095, %esi
subq %rsi, %rsp
testq %rsi, %rsi
je .L51
orq $0, -8(%rsp,%rsi)
.L51:
movq %rsp, %r15
testl %ecx, %ecx
jle .L52
movl $0, %r12d
movl $0x00000000, %r13d
movl $0x00000000, %r14d
movl $0x00000000, -180(%rbp)
.L53:
call rand@PLT
movslq %eax, %rdx
imulq $1125899907, %rdx, %rdx
sarq $50, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%r12,8)
call rand@PLT
movslq %eax, %rdx
imulq $1125899907, %rdx, %rdx
sarq $50, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 4(%rbx,%r12,8)
call rand@PLT
movslq %eax, %rdx
imulq $1125899907, %rdx, %rdx
sarq $50, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r15,%r12,4)
addss -180(%rbp), %xmm0
movss %xmm0, -180(%rbp)
movd %r14d, %xmm5
addss (%rbx,%r12,8), %xmm5
movd %xmm5, %r14d
movd %r13d, %xmm6
addss 4(%rbx,%r12,8), %xmm6
movd %xmm6, %r13d
movl -176(%rbp), %eax
addq $1, %r12
cmpl %r12d, %eax
jg .L53
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm0, %xmm5
movd %xmm5, %r14d
divss %xmm0, %xmm6
movss %xmm6, -184(%rbp)
movslq %eax, %r13
leaq 0(,%r13,8), %rsi
leaq 15(%rsi), %rcx
movq %rcx, %rdx
andq $-16, %rdx
andq $-4096, %rcx
movq %rsp, %rdi
subq %rcx, %rdi
.L54:
cmpq %rdi, %rsp
je .L55
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L54
.L55:
movq %rdx, %rcx
andl $4095, %ecx
subq %rcx, %rsp
testq %rcx, %rcx
je .L56
orq $0, -8(%rsp,%rcx)
.L56:
movq %rsp, %rdx
movq %rdx, %r12
testl %eax, %eax
jle .L57
movq %rdx, %rax
addq %rsi, %rdx
.L58:
movl $0x00000000, 4(%rax)
movl $0x00000000, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L58
.L57:
leal 0(,%r13,8), %eax
cltq
leaq -136(%rbp), %rdi
movq %rax, -192(%rbp)
movq %rax, %rsi
call cudaMalloc@PLT
sall $2, %r13d
movslq %r13d, %rax
leaq -128(%rbp), %rdi
movq %rax, -200(%rbp)
movq %rax, %rsi
call cudaMalloc@PLT
leaq -144(%rbp), %rdi
movq -192(%rbp), %r13
movq %r13, %rsi
call cudaMalloc@PLT
movq %r13, %rdx
movl $0, %esi
movq -144(%rbp), %rdi
call cudaMemset@PLT
leaq -160(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq -152(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq -136(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq -200(%rbp), %rdx
movq %r15, %rsi
movq -128(%rbp), %rdi
call cudaMemcpy@PLT
leaq -120(%rbp), %rdi
call cudaEventCreate@PLT
leaq -112(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -120(%rbp), %rdi
call cudaEventRecord@PLT
movl $32, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $32, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L90
.L59:
movl $32, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L91
.L60:
movl $0, %esi
movq -112(%rbp), %rdi
call cudaEventRecord@PLT
movq -112(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -172(%rbp)
leaq -172(%rbp), %rdi
movq -112(%rbp), %rdx
movq -120(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq -96(%rbp), %rdi
movl $2, %ecx
movl $8, %edx
movq -160(%rbp), %rsi
call cudaMemcpy@PLT
leaq -88(%rbp), %rdi
movl $2, %ecx
movl $8, %edx
movq -152(%rbp), %rsi
call cudaMemcpy@PLT
leaq -4542464(%rsp), %rax
.L61:
cmpq %rax, %rsp
je .L62
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L61
.L90:
movl -176(%rbp), %ecx
movq -152(%rbp), %rdx
movq -160(%rbp), %rsi
movq -136(%rbp), %rdi
call _Z41__device_stub__Z10findMinMaxP4vectS0_S0_iP4vectS0_S0_i
jmp .L59
.L91:
movq -152(%rbp), %rsi
movq -160(%rbp), %rdi
movl $32, %r8d
movq %rsi, %rcx
movq %rdi, %rdx
call _Z45__device_stub__Z11findMMinMaxP4vectS0_S0_S0_iP4vectS0_S0_S0_i
jmp .L60
.L62:
subq $1360, %rsp
orq $0, 1352(%rsp)
leaq 3(%rsp), %rax
movq %rax, %rcx
shrq $2, %rcx
andq $-4, %rax
movq %rax, %rsi
movq %rax, -208(%rbp)
leaq 12(%rax), %rax
leaq 4543824(%rsi), %rdx
.L64:
movl $-1, (%rax)
movl $-1, 4(%rax)
movl $-1, 8(%rax)
movl $-1, 12(%rax)
addq $52, %rax
cmpq %rax, %rdx
jne .L64
movl %r14d, 0(,%rcx,4)
movss -184(%rbp), %xmm5
movss %xmm5, 4(,%rcx,4)
movss -180(%rbp), %xmm6
movss %xmm6, 8(,%rcx,4)
movl $0, 28(,%rcx,4)
movl -176(%rbp), %eax
subl $1, %eax
movl %eax, 32(,%rcx,4)
movq -96(%rbp), %rax
movq %rax, 36(,%rcx,4)
movq -88(%rbp), %rax
movq %rax, 44(,%rcx,4)
leaq -104(%rbp), %rdi
movl $4543812, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4543812, %edx
movq -208(%rbp), %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
movl $0, %r13d
movl $1, %r14d
jmp .L69
.L66:
movl $0, %esi
movq -120(%rbp), %rdi
call cudaEventRecord@PLT
movl $1024, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
cvttss2sil -180(%rbp), %eax
movl %eax, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L92
.L68:
movl $0, %esi
movq -112(%rbp), %rdi
call cudaEventRecord@PLT
movq -112(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -168(%rbp), %rdi
movq -112(%rbp), %rdx
movq -120(%rbp), %rsi
call cudaEventElapsedTime@PLT
movss -172(%rbp), %xmm0
addss -168(%rbp), %xmm0
movss %xmm0, -172(%rbp)
sall $2, %r14d
addl $1, %r13d
cmpl $8, %r13d
je .L93
.L69:
pxor %xmm0, %xmm0
cvtsi2sdl %r14d, %xmm0
mulsd .LC4(%rip), %xmm0
movapd %xmm0, %xmm2
movsd .LC14(%rip), %xmm1
andpd %xmm0, %xmm1
movsd .LC5(%rip), %xmm6
ucomisd %xmm1, %xmm6
jbe .L65
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm2
movsd .LC7(%rip), %xmm4
andpd %xmm4, %xmm2
addsd %xmm2, %xmm1
movsd .LC14(%rip), %xmm2
andnpd %xmm0, %xmm2
orpd %xmm1, %xmm2
.L65:
cvttsd2sil %xmm2, %eax
pxor %xmm7, %xmm7
cvtsi2ssl %eax, %xmm7
movss %xmm7, -180(%rbp)
movss .LC1(%rip), %xmm0
comiss %xmm7, %xmm0
ja .L66
movss %xmm0, -180(%rbp)
jmp .L66
.L92:
movl $87381, %r8d
movl %r13d, %ecx
movq -104(%rbp), %rdx
movq -128(%rbp), %rsi
movq -136(%rbp), %rdi
call _Z42__device_stub__Z9constructP4vectPfP4nodeiiP4vectPfP4nodeii
jmp .L68
.L93:
movl $2, %ecx
movl $4543812, %edx
movq -104(%rbp), %rsi
movq -208(%rbp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -164(%rbp), %rsi
leaq .LC9(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
pxor %xmm0, %xmm0
cvtsi2sdl -176(%rbp), %xmm0
mulsd .LC4(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LC14(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC5(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L70
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm1
movsd .LC7(%rip), %xmm4
andpd %xmm4, %xmm1
addsd %xmm2, %xmm1
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm1
.L70:
pxor %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
comiss .LC1(%rip), %xmm0
jbe .L71
movss .LC1(%rip), %xmm0
.L71:
cvttss2sil %xmm0, %r13d
movl %r13d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq -120(%rbp), %rdi
call cudaEventRecord@PLT
movl $1024, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl %r13d, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L73:
movl $0, %esi
movq -112(%rbp), %rdi
call cudaEventRecord@PLT
movq -112(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -168(%rbp), %rdi
movq -112(%rbp), %rdx
movq -120(%rbp), %rsi
call cudaEventElapsedTime@PLT
movss -172(%rbp), %xmm0
addss -168(%rbp), %xmm0
movss %xmm0, -172(%rbp)
movl $2, %ecx
movq -192(%rbp), %r14
movq %r14, %rdx
movq -144(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r14, %rdx
movq -136(%rbp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq -200(%rbp), %rdx
movq -128(%rbp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
cmpl $0, -176(%rbp)
jle .L81
movl $0, %r13d
movl $0x00000000, -192(%rbp)
movl $0x00000000, -180(%rbp)
leaq .LC11(%rip), %r14
.L75:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r13,8), %xmm0
pxor %xmm4, %xmm4
cvtss2sd 4(%r12,%r13,8), %xmm4
pxor %xmm3, %xmm3
cvtss2sd (%r12,%r13,8), %xmm3
pxor %xmm2, %xmm2
cvtss2sd (%r15,%r13,4), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 4(%rbx,%r13,8), %xmm1
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $5, %eax
call __printf_chk@PLT
movss -180(%rbp), %xmm4
addss (%r12,%r13,8), %xmm4
movss %xmm4, -180(%rbp)
movss -192(%rbp), %xmm3
addss 4(%r12,%r13,8), %xmm3
movss %xmm3, -192(%rbp)
addq $1, %r13
cmpl %r13d, -176(%rbp)
jg .L75
.L74:
pxor %xmm0, %xmm0
cvtss2sd -172(%rbp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -180(%rbp), %xmm0
pxor %xmm1, %xmm1
cvtss2sd -192(%rbp), %xmm1
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L95
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L94:
.cfi_restore_state
movss -164(%rbp), %xmm0
movl -176(%rbp), %r8d
movq -144(%rbp), %rcx
movq -104(%rbp), %rdx
movq -128(%rbp), %rsi
movq -136(%rbp), %rdi
call _Z45__device_stub__Z9calculateP4vectPfP4nodeS0_ifP4vectPfP4nodeS0_if
jmp .L73
.L81:
movl $0x00000000, -192(%rbp)
movl $0x00000000, -180(%rbp)
jmp .L74
.L52:
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
pxor %xmm1, %xmm1
divss %xmm0, %xmm1
movd %xmm1, %r14d
addq $15, %rax
movq %rax, %rdx
andq $-16, %rdx
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L76:
cmpq %rcx, %rsp
je .L77
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L76
.L77:
movq %rdx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L78
orq $0, -8(%rsp,%rax)
.L78:
movq %rsp, %r12
movl %r14d, -184(%rbp)
movl $0x00000000, -180(%rbp)
jmp .L57
.L95:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC15:
.string "_Z9calculateP4vectPfP4nodeS0_if"
.section .rodata.str1.1
.LC16:
.string "_Z9constructP4vectPfP4nodeii"
.section .rodata.str1.8
.align 8
.LC17:
.string "_Z11findMMinMaxP4vectS0_S0_S0_i"
.section .rodata.str1.1
.LC18:
.string "_Z10findMinMaxP4vectS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z9calculateP4vectPfP4nodeS0_if(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z9constructP4vectPfP4nodeii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z11findMMinMaxP4vectS0_S0_S0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z10findMinMaxP4vectS0_S0_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1101004800
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1062207488
.align 8
.LC5:
.long 0
.long 1127219200
.align 8
.LC7:
.long 0
.long 1072693248
.align 8
.LC14:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <math.h>
#include <limits.h>
#include <float.h>
#include <iostream>
#include <sys/time.h>
#define G 6.67408E-11 //Gravitational constant
#define lvl 9 //depth of quad tree till which we'll divide plane
using namespace std;
struct vect //Structure for 2D coordinate
{
float x; //X coordinate
float y; //Y coordinate
};
struct node //Structure for each node of the quad tree
{
vect body; //centre of mass of bodies in current node
float mass; //total mass of bodies in current node
int child[4]; //children indices in nodes array
int l,r; //index limit in body array of bodies in current node
vect min, max; //min and max X and Y coordinates of bodies belonging to current node
};
//Function to calculate Gravitational force between two bodies
__device__ vect gravity (vect a, vect b, float m1, float m2)
{
float res=G*m1*m2;
float r=(a.y-b.y)*(a.y-b.y)+(a.x-b.x)*(a.x-b.x);
if (r>0) res/=r;
vect vec;
vec.y=a.y-b.y;
vec.x=a.x-b.x;
r=sqrt(r);
if (r>0) vec.y/=r, vec.x/=r;
vec.y*=res;
vec.x*=res;
return vec;
}
//part1 for kernel1 to find min-max among the n bodies
//Will find min and max of X and Y coordinates for each thread lock
//Uses reduction technique
__global__ void findMinMax(vect * body, vect * min, vect * max, int n)
{
__shared__ vect min_cache[32];
__shared__ vect max_cache[32];
int index=threadIdx.x+blockDim.x*blockIdx.x;
float xmin=FLT_MAX, ymin=FLT_MAX;
float xmax=FLT_MIN, ymax=FLT_MIN;
while (index<n) //takes care if total number greater than total threads in kernel
{
xmin=fmin(xmin, body[index].x);
ymin=fmin(ymin, body[index].y);
xmax=fmax(xmax, body[index].x);
ymax=fmax(ymax, body[index].y);
index+=(blockDim.x*gridDim.x); //incrementing index by total number of threads in kernel, to take care if total number more than total threads in kernel
}
int tid=threadIdx.x;
min_cache[tid].x=xmin;
min_cache[tid].y=ymin;
max_cache[tid].x=xmax;
max_cache[tid].y=ymax;
int active=blockDim.x>>1;
do
{
__syncthreads();
if (tid<active) //reduction
{
min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);
max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
}
active>>=1;
}while (active>0);
if (tid==0) min[blockIdx.x]=min_cache[0], max[blockIdx.x]=max_cache[0];
}
//part2 for kernel1 to find min-max among the n bodies
//Will find global min and max of X and Y coordinates from local min and max of above kernel
__global__ void findMMinMax(vect * mmin, vect *mmax, vect * min, vect * max, int n)
{
__shared__ vect min_cache[32];
__shared__ vect max_cache[32];
int index=threadIdx.x+blockDim.x*blockIdx.x;
float xmin=FLT_MAX, ymin=FLT_MAX;
float xmax=FLT_MIN, ymax=FLT_MIN;
while (index<n) //takes care if total number greater than total threads in kernel
{
xmin=fmin(xmin, min[index].x);
ymin=fmin(ymin, min[index].y);
xmax=fmax(xmax, max[index].x);
ymax=fmax(ymax, max[index].y);
index+=(blockDim.x*gridDim.x);
}
int tid=threadIdx.x;
min_cache[tid].x=xmin;
min_cache[tid].y=ymin;
max_cache[tid].x=xmax;
max_cache[tid].y=ymax;
int active=blockDim.x>>1;
do
{
__syncthreads();
if (tid<active) //reduction
{
min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);
max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
}
active>>=1;
}while (active>0);
if (tid==0) mmin[blockIdx.x]=min_cache[0], mmax[blockIdx.x]=max_cache[0];
}
//This function will construct particular level of the tree.
//Each node will be divided further into four new nodes and bodies in the array will be swapped so that bodies belonging to same node remain together in the array
//This will work as kernel 2
__global__ void construct(vect *body, float *mass, node *nodes, int level, int tot)
{
int index=blockDim.x*blockIdx.x+threadIdx.x;
int tid=index*4;
int total = 1<<(2*level); //total nodes in current level
int offset=((1<<(2*level))-1)/3; //total nodes in tree upto previous level
int off=offset+total; //total nodes in tree upto current level
while (index<total) //'while' loop will take care if total number more than total threads in kernel
{
index+=offset; //actual index in nodes array
node nd=nodes[index];
if (nodes[index].l<=nodes[index].r)
{
float xl=nd.min.x, xr=nd.max.x;
float yl=nd.min.y, yr=nd.max.y;
float xmid=xl+(xr-xl)/2;
float ymid=yl+(yr-yl)/2;
float l=nd.l, r=nd.r;
node child[4];
for (int i=0;i<4;i++)
{
child[i].min.x=child[i].min.y=FLT_MAX, child[i].max.x=child[i].max.y=FLT_MIN;
for (int j=0;j<4;j++) child[i].child[j]=-1;
}
int i=l-1;
float m=0, x=0, y=0, mm=0, xx=0, yy=0;
for (int j=l;j<=r;j++) //swapping of bodies belonging to current node based on x-coordinates creating two children
{
if (body[j].x<=xmid)
{
i++;
vect temp=body[i];
body[i]=body[j];
body[j]=temp;
float t=mass[i];
mass[i]=mass[j];
mass[j]=t;
}
}
child[2].l=l, child[2].r=i;
child[3].l=i+1, child[3].r=r;
for (int k=2;k<=3;k++)
{
m=mm=x=xx=y=yy=0;
l=child[k].l, r=child[k].r;
i=l-1;
int cnt=0;
for (int j=l;j<=r;j++) //swapping of bodies in two children created previously based on y-coordinates, each creating two new children
{
x+=body[j].x;
y+=body[j].y;
m+=mass[j];
if (body[j].y<=ymid)
{
xx+=body[j].x, yy+=body[j].y, mm+=mass[j];
cnt++;
i++;
vect temp=body[i];
body[i]=body[j];
body[j]=temp;
float t=mass[i];
mass[i]=mass[j];
mass[j]=t;
}
}
if(cnt>0) child[k].mass=mm, child[k].body.x=xx/cnt, child[k].body.y=yy/cnt;
child[k].l=l, child[k].r=i;
mm=m-mm, xx=x-xx, yy=y-yy, cnt=r-l+1-cnt;
if(cnt>0) child[k-2].mass=mm, child[k-2].body.x=xx/cnt, child[k-2].body.y=yy/cnt;
child[k-2].l=i+1, child[k-2].r=r;
}
for (int i=0;i<4;i++)
{
if (i%2) child[i].min.x=xmid, child[i].max.x=xr;
else child[i].min.x=xl, child[i].max.x=xmid;
if (i<2) child[i].min.y=ymid, child[i].max.y=yr;
else child[i].min.y=yl, child[i].max.y=ymid;
if (off+tid+i<tot) nodes[off+tid+i]=child[i];
nd.child[i]=off+tid+i;
}
}
else
{
for (int i=0;i<4;i++)
{
if (off+tid+i<tot)
{
nodes[off+tid+i].l=0;
nodes[off+tid+i].r=-1;
}
nd.child[i]=off+tid+i;
}
}
nodes[index]=nd;
index-=offset;
index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total threads.
}
}
//This is kernel 3
//This function calculates force on bodies
__global__ void calculate(vect *body, float *mass, node *nodes, vect *force, int n, float theta)
{
int index=blockDim.x*blockIdx.x+threadIdx.x;
int l=((1<<(2*(lvl-1)))-1)/3; //total nodes in tree upto max depth
while (index<n) //'while' loop takes care if total number more than total threads in kernel
{
int st[4*(lvl)]; //using array as stack
int curr=0; //variable showing current top index
st[curr]=0;
vect bd=body[index];
while (curr>=0) //for each body do DFS until reached leaf
{
int t=st[curr];
curr--;
node nd=nodes[t];
float s=fmax(nd.max.x-nd.min.x, nd.max.y-nd.min.y);
float x=bd.x-nd.body.x, y=bd.y-nd.body.y;
float dist=sqrt(x*x+y*y);
float val=FLT_MAX;
if (dist>0) val=s/dist;
if (val<theta) //Barnes-Hutt approximation
{
vect frc=gravity(nd.body, bd, nd.mass, mass[index]);
force[index].x+=frc.x;
force[index].y+=frc.y;
}
else
{
if (t>=l) //if reached leaf
{
vect frc=gravity(nd.body, bd, nd.mass, mass[index]);
force[index].x+=frc.x;
force[index].y+=frc.y;
continue;
}
for (int i=0;i<4;i++)
{
int temp=nd.child[i];
if (temp==-1 || nodes[temp].l>nodes[temp].r) continue;
st[++curr]=temp;
}
}
}
index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total number of threads in kernel
}
}
float maxx(float a, float b)
{
return (a<b?b:a);
}
float minn(float a, float b)
{
return (a<b?a:b);
}
int main()
{
int n;
printf("n : ");
scanf("%d", &n);
vect body[n];
float mass[n];
float m=0, x=0, y=0;
for (int i=0;i<n;i++)
{
body[i].x=rand()%1000000;
body[i].y=rand()%1000000;
mass[i]=rand()%1000000;
m+=mass[i], x+=body[i].x, y+=body[i].y;
}
x/=n, y/=n; //centre of mass of the whole system
vect force[n];
vect *min;
vect *max;
for (int i=0;i<n;i++) force[i].x=force[i].y=0;
vect *dforce;
vect *dbody;
float *dmass;
int s=sizeof(vect)*n;
int sz=sizeof(float)*n;
cudaMalloc(&dbody, s);
cudaMalloc(&dmass, sz);
cudaMalloc(&dforce, s);
cudaMemset(dforce, 0, s);
cudaMalloc(&min, s);
cudaMalloc(&max, s);
cudaMemcpy(dbody, body, s, cudaMemcpyHostToDevice);
cudaMemcpy(dmass, mass, sz, cudaMemcpyHostToDevice);
int val=32;
int block = val;
int grid = val;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
//This is kernel 1 which devided into 2 parts
//bassically it find minimum and maximum from
//the n bodies
findMinMax<<<grid, block>>>(dbody, min, max, n);
findMMinMax<<<1, block>>>(min, max, min, max, val);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
//milliseconds find the total kernal time in GPU
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
vect gmin;
vect gmax;
cudaMemcpy(&gmin, min, sizeof(vect), cudaMemcpyDeviceToHost);
cudaMemcpy(&gmax, max, sizeof(vect), cudaMemcpyDeviceToHost);
int curr=1;
int tot=1<<(2*lvl);
tot=(tot-1)/3;
node h_nodes[tot];
for (int i=0;i<tot;i++)
{
for (int j=0;j<4;j++) h_nodes[i].child[j]=-1;
}
vect temp;
temp.x=x, temp.y=y;
h_nodes[0].body=temp, h_nodes[0].mass=m, h_nodes[0].l=0, h_nodes[0].r=n-1, h_nodes[0].min=gmin, h_nodes[0].max=gmax;
node *d_nodes;
cudaMalloc(&d_nodes, sizeof(node)*tot);
cudaMemcpy(d_nodes, h_nodes, sizeof(node)*tot, cudaMemcpyHostToDevice);
float t;
for (int i=0;i<lvl-1;i++) //creation of tree level by level. Each thread is assigned a node in current level.
{
block = 1024;
grid=ceil((1.0*curr)/block);
grid = minn(grid, 20);
cudaEventRecord(start);
construct<<<grid, block>>>(dbody, dmass, d_nodes, i, tot);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&t, start, stop);
milliseconds+=t;
curr*=4;
}
cudaMemcpy(h_nodes, d_nodes, sizeof(node)*tot, cudaMemcpyDeviceToHost);
float theta;
printf("theta : ");
scanf("%f", &theta);
grid=minn(20, ceil((1.0*n)/block));
printf("%d\n", grid);
cudaEventRecord(start);
calculate<<<grid, block>>>(dbody, dmass, d_nodes, dforce, n, theta); //Each thread is assigned a body
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&t, start, stop);
milliseconds+=t;
cudaMemcpy(force, dforce, s, cudaMemcpyDeviceToHost);
cudaMemcpy(body, dbody, s, cudaMemcpyDeviceToHost);
cudaMemcpy(mass, dmass, sz, cudaMemcpyDeviceToHost);
x=0, y=0;
for(int i=0;i<n;i++)
{
printf("force %d : x %f y %f m %f : %.15f %.15f\n", i, body[i].x, body[i].y, mass[i], force[i].x, force[i].y);
x+=force[i].x, y+=force[i].y;
}
printf("gpu time : %f\n", milliseconds);
printf("x %f y %f\n", x, y);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <limits.h>
#include <float.h>
#include <iostream>
#include <sys/time.h>
#define G 6.67408E-11 //Gravitational constant
#define lvl 9 //depth of quad tree till which we'll divide plane
using namespace std;
struct vect //Structure for 2D coordinate
{
float x; //X coordinate
float y; //Y coordinate
};
struct node //Structure for each node of the quad tree
{
vect body; //centre of mass of bodies in current node
float mass; //total mass of bodies in current node
int child[4]; //children indices in nodes array
int l,r; //index limit in body array of bodies in current node
vect min, max; //min and max X and Y coordinates of bodies belonging to current node
};
//Function to calculate Gravitational force between two bodies
__device__ vect gravity (vect a, vect b, float m1, float m2)
{
float res=G*m1*m2;
float r=(a.y-b.y)*(a.y-b.y)+(a.x-b.x)*(a.x-b.x);
if (r>0) res/=r;
vect vec;
vec.y=a.y-b.y;
vec.x=a.x-b.x;
r=sqrt(r);
if (r>0) vec.y/=r, vec.x/=r;
vec.y*=res;
vec.x*=res;
return vec;
}
//part1 for kernel1 to find min-max among the n bodies
//Will find min and max of X and Y coordinates for each thread lock
//Uses reduction technique
__global__ void findMinMax(vect * body, vect * min, vect * max, int n)
{
__shared__ vect min_cache[32];
__shared__ vect max_cache[32];
int index=threadIdx.x+blockDim.x*blockIdx.x;
float xmin=FLT_MAX, ymin=FLT_MAX;
float xmax=FLT_MIN, ymax=FLT_MIN;
while (index<n) //takes care if total number greater than total threads in kernel
{
xmin=fmin(xmin, body[index].x);
ymin=fmin(ymin, body[index].y);
xmax=fmax(xmax, body[index].x);
ymax=fmax(ymax, body[index].y);
index+=(blockDim.x*gridDim.x); //incrementing index by total number of threads in kernel, to take care if total number more than total threads in kernel
}
int tid=threadIdx.x;
min_cache[tid].x=xmin;
min_cache[tid].y=ymin;
max_cache[tid].x=xmax;
max_cache[tid].y=ymax;
int active=blockDim.x>>1;
do
{
__syncthreads();
if (tid<active) //reduction
{
min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);
max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
}
active>>=1;
}while (active>0);
if (tid==0) min[blockIdx.x]=min_cache[0], max[blockIdx.x]=max_cache[0];
}
//part2 for kernel1 to find min-max among the n bodies
//Will find global min and max of X and Y coordinates from local min and max of above kernel
__global__ void findMMinMax(vect * mmin, vect *mmax, vect * min, vect * max, int n)
{
__shared__ vect min_cache[32];
__shared__ vect max_cache[32];
int index=threadIdx.x+blockDim.x*blockIdx.x;
float xmin=FLT_MAX, ymin=FLT_MAX;
float xmax=FLT_MIN, ymax=FLT_MIN;
while (index<n) //takes care if total number greater than total threads in kernel
{
xmin=fmin(xmin, min[index].x);
ymin=fmin(ymin, min[index].y);
xmax=fmax(xmax, max[index].x);
ymax=fmax(ymax, max[index].y);
index+=(blockDim.x*gridDim.x);
}
int tid=threadIdx.x;
min_cache[tid].x=xmin;
min_cache[tid].y=ymin;
max_cache[tid].x=xmax;
max_cache[tid].y=ymax;
int active=blockDim.x>>1;
do
{
__syncthreads();
if (tid<active) //reduction
{
min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);
max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
}
active>>=1;
}while (active>0);
if (tid==0) mmin[blockIdx.x]=min_cache[0], mmax[blockIdx.x]=max_cache[0];
}
//This function will construct particular level of the tree.
//Each node will be divided further into four new nodes and bodies in the array will be swapped so that bodies belonging to same node remain together in the array
//This will work as kernel 2
__global__ void construct(vect *body, float *mass, node *nodes, int level, int tot)
{
int index=blockDim.x*blockIdx.x+threadIdx.x;
int tid=index*4;
int total = 1<<(2*level); //total nodes in current level
int offset=((1<<(2*level))-1)/3; //total nodes in tree upto previous level
int off=offset+total; //total nodes in tree upto current level
while (index<total) //'while' loop will take care if total number more than total threads in kernel
{
index+=offset; //actual index in nodes array
node nd=nodes[index];
if (nodes[index].l<=nodes[index].r)
{
float xl=nd.min.x, xr=nd.max.x;
float yl=nd.min.y, yr=nd.max.y;
float xmid=xl+(xr-xl)/2;
float ymid=yl+(yr-yl)/2;
float l=nd.l, r=nd.r;
node child[4];
for (int i=0;i<4;i++)
{
child[i].min.x=child[i].min.y=FLT_MAX, child[i].max.x=child[i].max.y=FLT_MIN;
for (int j=0;j<4;j++) child[i].child[j]=-1;
}
int i=l-1;
float m=0, x=0, y=0, mm=0, xx=0, yy=0;
for (int j=l;j<=r;j++) //swapping of bodies belonging to current node based on x-coordinates creating two children
{
if (body[j].x<=xmid)
{
i++;
vect temp=body[i];
body[i]=body[j];
body[j]=temp;
float t=mass[i];
mass[i]=mass[j];
mass[j]=t;
}
}
child[2].l=l, child[2].r=i;
child[3].l=i+1, child[3].r=r;
for (int k=2;k<=3;k++)
{
m=mm=x=xx=y=yy=0;
l=child[k].l, r=child[k].r;
i=l-1;
int cnt=0;
for (int j=l;j<=r;j++) //swapping of bodies in two children created previously based on y-coordinates, each creating two new children
{
x+=body[j].x;
y+=body[j].y;
m+=mass[j];
if (body[j].y<=ymid)
{
xx+=body[j].x, yy+=body[j].y, mm+=mass[j];
cnt++;
i++;
vect temp=body[i];
body[i]=body[j];
body[j]=temp;
float t=mass[i];
mass[i]=mass[j];
mass[j]=t;
}
}
if(cnt>0) child[k].mass=mm, child[k].body.x=xx/cnt, child[k].body.y=yy/cnt;
child[k].l=l, child[k].r=i;
mm=m-mm, xx=x-xx, yy=y-yy, cnt=r-l+1-cnt;
if(cnt>0) child[k-2].mass=mm, child[k-2].body.x=xx/cnt, child[k-2].body.y=yy/cnt;
child[k-2].l=i+1, child[k-2].r=r;
}
for (int i=0;i<4;i++)
{
if (i%2) child[i].min.x=xmid, child[i].max.x=xr;
else child[i].min.x=xl, child[i].max.x=xmid;
if (i<2) child[i].min.y=ymid, child[i].max.y=yr;
else child[i].min.y=yl, child[i].max.y=ymid;
if (off+tid+i<tot) nodes[off+tid+i]=child[i];
nd.child[i]=off+tid+i;
}
}
else
{
for (int i=0;i<4;i++)
{
if (off+tid+i<tot)
{
nodes[off+tid+i].l=0;
nodes[off+tid+i].r=-1;
}
nd.child[i]=off+tid+i;
}
}
nodes[index]=nd;
index-=offset;
index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total threads.
}
}
//This is kernel 3
//This function calculates force on bodies
__global__ void calculate(vect *body, float *mass, node *nodes, vect *force, int n, float theta)
{
int index=blockDim.x*blockIdx.x+threadIdx.x;
int l=((1<<(2*(lvl-1)))-1)/3; //total nodes in tree upto max depth
while (index<n) //'while' loop takes care if total number more than total threads in kernel
{
int st[4*(lvl)]; //using array as stack
int curr=0; //variable showing current top index
st[curr]=0;
vect bd=body[index];
while (curr>=0) //for each body do DFS until reached leaf
{
int t=st[curr];
curr--;
node nd=nodes[t];
float s=fmax(nd.max.x-nd.min.x, nd.max.y-nd.min.y);
float x=bd.x-nd.body.x, y=bd.y-nd.body.y;
float dist=sqrt(x*x+y*y);
float val=FLT_MAX;
if (dist>0) val=s/dist;
if (val<theta) //Barnes-Hutt approximation
{
vect frc=gravity(nd.body, bd, nd.mass, mass[index]);
force[index].x+=frc.x;
force[index].y+=frc.y;
}
else
{
if (t>=l) //if reached leaf
{
vect frc=gravity(nd.body, bd, nd.mass, mass[index]);
force[index].x+=frc.x;
force[index].y+=frc.y;
continue;
}
for (int i=0;i<4;i++)
{
int temp=nd.child[i];
if (temp==-1 || nodes[temp].l>nodes[temp].r) continue;
st[++curr]=temp;
}
}
}
index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total number of threads in kernel
}
}
float maxx(float a, float b)
{
return (a<b?b:a);
}
float minn(float a, float b)
{
return (a<b?a:b);
}
int main()
{
int n;
printf("n : ");
scanf("%d", &n);
vect body[n];
float mass[n];
float m=0, x=0, y=0;
for (int i=0;i<n;i++)
{
body[i].x=rand()%1000000;
body[i].y=rand()%1000000;
mass[i]=rand()%1000000;
m+=mass[i], x+=body[i].x, y+=body[i].y;
}
x/=n, y/=n; //centre of mass of the whole system
vect force[n];
vect *min;
vect *max;
for (int i=0;i<n;i++) force[i].x=force[i].y=0;
vect *dforce;
vect *dbody;
float *dmass;
int s=sizeof(vect)*n;
int sz=sizeof(float)*n;
hipMalloc(&dbody, s);
hipMalloc(&dmass, sz);
hipMalloc(&dforce, s);
hipMemset(dforce, 0, s);
hipMalloc(&min, s);
hipMalloc(&max, s);
hipMemcpy(dbody, body, s, hipMemcpyHostToDevice);
hipMemcpy(dmass, mass, sz, hipMemcpyHostToDevice);
int val=32;
int block = val;
int grid = val;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
//This is kernel 1 which devided into 2 parts
//bassically it find minimum and maximum from
//the n bodies
findMinMax<<<grid, block>>>(dbody, min, max, n);
findMMinMax<<<1, block>>>(min, max, min, max, val);
hipEventRecord(stop);
hipEventSynchronize(stop);
//milliseconds find the total kernal time in GPU
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
vect gmin;
vect gmax;
hipMemcpy(&gmin, min, sizeof(vect), hipMemcpyDeviceToHost);
hipMemcpy(&gmax, max, sizeof(vect), hipMemcpyDeviceToHost);
int curr=1;
int tot=1<<(2*lvl);
tot=(tot-1)/3;
node h_nodes[tot];
for (int i=0;i<tot;i++)
{
for (int j=0;j<4;j++) h_nodes[i].child[j]=-1;
}
vect temp;
temp.x=x, temp.y=y;
h_nodes[0].body=temp, h_nodes[0].mass=m, h_nodes[0].l=0, h_nodes[0].r=n-1, h_nodes[0].min=gmin, h_nodes[0].max=gmax;
node *d_nodes;
hipMalloc(&d_nodes, sizeof(node)*tot);
hipMemcpy(d_nodes, h_nodes, sizeof(node)*tot, hipMemcpyHostToDevice);
float t;
for (int i=0;i<lvl-1;i++) //creation of tree level by level. Each thread is assigned a node in current level.
{
block = 1024;
grid=ceil((1.0*curr)/block);
grid = minn(grid, 20);
hipEventRecord(start);
construct<<<grid, block>>>(dbody, dmass, d_nodes, i, tot);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&t, start, stop);
milliseconds+=t;
curr*=4;
}
hipMemcpy(h_nodes, d_nodes, sizeof(node)*tot, hipMemcpyDeviceToHost);
float theta;
printf("theta : ");
scanf("%f", &theta);
grid=minn(20, ceil((1.0*n)/block));
printf("%d\n", grid);
hipEventRecord(start);
calculate<<<grid, block>>>(dbody, dmass, d_nodes, dforce, n, theta); //Each thread is assigned a body
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&t, start, stop);
milliseconds+=t;
hipMemcpy(force, dforce, s, hipMemcpyDeviceToHost);
hipMemcpy(body, dbody, s, hipMemcpyDeviceToHost);
hipMemcpy(mass, dmass, sz, hipMemcpyDeviceToHost);
x=0, y=0;
for(int i=0;i<n;i++)
{
printf("force %d : x %f y %f m %f : %.15f %.15f\n", i, body[i].x, body[i].y, mass[i], force[i].x, force[i].y);
x+=force[i].x, y+=force[i].y;
}
printf("gpu time : %f\n", milliseconds);
printf("x %f y %f\n", x, y);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <limits.h>
#include <float.h>
#include <iostream>
#include <sys/time.h>
#define G 6.67408E-11 //Gravitational constant
#define lvl 9 //depth of quad tree till which we'll divide plane
using namespace std;
struct vect //Structure for 2D coordinate
{
float x; //X coordinate
float y; //Y coordinate
};
struct node //Structure for each node of the quad tree
{
vect body; //centre of mass of bodies in current node
float mass; //total mass of bodies in current node
int child[4]; //children indices in nodes array
int l,r; //index limit in body array of bodies in current node
vect min, max; //min and max X and Y coordinates of bodies belonging to current node
};
//Function to calculate Gravitational force between two bodies
__device__ vect gravity (vect a, vect b, float m1, float m2)
{
float res=G*m1*m2;
float r=(a.y-b.y)*(a.y-b.y)+(a.x-b.x)*(a.x-b.x);
if (r>0) res/=r;
vect vec;
vec.y=a.y-b.y;
vec.x=a.x-b.x;
r=sqrt(r);
if (r>0) vec.y/=r, vec.x/=r;
vec.y*=res;
vec.x*=res;
return vec;
}
//part1 for kernel1 to find min-max among the n bodies
//Will find min and max of X and Y coordinates for each thread lock
//Uses reduction technique
__global__ void findMinMax(vect * body, vect * min, vect * max, int n)
{
__shared__ vect min_cache[32];
__shared__ vect max_cache[32];
int index=threadIdx.x+blockDim.x*blockIdx.x;
float xmin=FLT_MAX, ymin=FLT_MAX;
float xmax=FLT_MIN, ymax=FLT_MIN;
while (index<n) //takes care if total number greater than total threads in kernel
{
xmin=fmin(xmin, body[index].x);
ymin=fmin(ymin, body[index].y);
xmax=fmax(xmax, body[index].x);
ymax=fmax(ymax, body[index].y);
index+=(blockDim.x*gridDim.x); //incrementing index by total number of threads in kernel, to take care if total number more than total threads in kernel
}
int tid=threadIdx.x;
min_cache[tid].x=xmin;
min_cache[tid].y=ymin;
max_cache[tid].x=xmax;
max_cache[tid].y=ymax;
int active=blockDim.x>>1;
do
{
__syncthreads();
if (tid<active) //reduction
{
min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);
max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
}
active>>=1;
}while (active>0);
if (tid==0) min[blockIdx.x]=min_cache[0], max[blockIdx.x]=max_cache[0];
}
//part2 for kernel1 to find min-max among the n bodies
//Will find global min and max of X and Y coordinates from local min and max of above kernel
__global__ void findMMinMax(vect * mmin, vect *mmax, vect * min, vect * max, int n)
{
__shared__ vect min_cache[32];
__shared__ vect max_cache[32];
int index=threadIdx.x+blockDim.x*blockIdx.x;
float xmin=FLT_MAX, ymin=FLT_MAX;
float xmax=FLT_MIN, ymax=FLT_MIN;
while (index<n) //takes care if total number greater than total threads in kernel
{
xmin=fmin(xmin, min[index].x);
ymin=fmin(ymin, min[index].y);
xmax=fmax(xmax, max[index].x);
ymax=fmax(ymax, max[index].y);
index+=(blockDim.x*gridDim.x);
}
int tid=threadIdx.x;
min_cache[tid].x=xmin;
min_cache[tid].y=ymin;
max_cache[tid].x=xmax;
max_cache[tid].y=ymax;
int active=blockDim.x>>1;
do
{
__syncthreads();
if (tid<active) //reduction
{
min_cache[tid].x=fmin(min_cache[tid].x, min_cache[tid+active].x);
min_cache[tid].y=fmin(min_cache[tid].y, min_cache[tid+active].y);
max_cache[tid].x=fmax(max_cache[tid].x, max_cache[tid+active].x);
max_cache[tid].y=fmax(max_cache[tid].y, max_cache[tid+active].y);
}
active>>=1;
}while (active>0);
if (tid==0) mmin[blockIdx.x]=min_cache[0], mmax[blockIdx.x]=max_cache[0];
}
//This function will construct particular level of the tree.
//Each node will be divided further into four new nodes and bodies in the array will be swapped so that bodies belonging to same node remain together in the array
//This will work as kernel 2
__global__ void construct(vect *body, float *mass, node *nodes, int level, int tot)
{
int index=blockDim.x*blockIdx.x+threadIdx.x;
int tid=index*4;
int total = 1<<(2*level); //total nodes in current level
int offset=((1<<(2*level))-1)/3; //total nodes in tree upto previous level
int off=offset+total; //total nodes in tree upto current level
while (index<total) //'while' loop will take care if total number more than total threads in kernel
{
index+=offset; //actual index in nodes array
node nd=nodes[index];
if (nodes[index].l<=nodes[index].r)
{
float xl=nd.min.x, xr=nd.max.x;
float yl=nd.min.y, yr=nd.max.y;
float xmid=xl+(xr-xl)/2;
float ymid=yl+(yr-yl)/2;
float l=nd.l, r=nd.r;
node child[4];
for (int i=0;i<4;i++)
{
child[i].min.x=child[i].min.y=FLT_MAX, child[i].max.x=child[i].max.y=FLT_MIN;
for (int j=0;j<4;j++) child[i].child[j]=-1;
}
int i=l-1;
float m=0, x=0, y=0, mm=0, xx=0, yy=0;
for (int j=l;j<=r;j++) //swapping of bodies belonging to current node based on x-coordinates creating two children
{
if (body[j].x<=xmid)
{
i++;
vect temp=body[i];
body[i]=body[j];
body[j]=temp;
float t=mass[i];
mass[i]=mass[j];
mass[j]=t;
}
}
child[2].l=l, child[2].r=i;
child[3].l=i+1, child[3].r=r;
for (int k=2;k<=3;k++)
{
m=mm=x=xx=y=yy=0;
l=child[k].l, r=child[k].r;
i=l-1;
int cnt=0;
for (int j=l;j<=r;j++) //swapping of bodies in two children created previously based on y-coordinates, each creating two new children
{
x+=body[j].x;
y+=body[j].y;
m+=mass[j];
if (body[j].y<=ymid)
{
xx+=body[j].x, yy+=body[j].y, mm+=mass[j];
cnt++;
i++;
vect temp=body[i];
body[i]=body[j];
body[j]=temp;
float t=mass[i];
mass[i]=mass[j];
mass[j]=t;
}
}
if(cnt>0) child[k].mass=mm, child[k].body.x=xx/cnt, child[k].body.y=yy/cnt;
child[k].l=l, child[k].r=i;
mm=m-mm, xx=x-xx, yy=y-yy, cnt=r-l+1-cnt;
if(cnt>0) child[k-2].mass=mm, child[k-2].body.x=xx/cnt, child[k-2].body.y=yy/cnt;
child[k-2].l=i+1, child[k-2].r=r;
}
for (int i=0;i<4;i++)
{
if (i%2) child[i].min.x=xmid, child[i].max.x=xr;
else child[i].min.x=xl, child[i].max.x=xmid;
if (i<2) child[i].min.y=ymid, child[i].max.y=yr;
else child[i].min.y=yl, child[i].max.y=ymid;
if (off+tid+i<tot) nodes[off+tid+i]=child[i];
nd.child[i]=off+tid+i;
}
}
else
{
for (int i=0;i<4;i++)
{
if (off+tid+i<tot)
{
nodes[off+tid+i].l=0;
nodes[off+tid+i].r=-1;
}
nd.child[i]=off+tid+i;
}
}
nodes[index]=nd;
index-=offset;
index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total threads.
}
}
//This is kernel 3
//This function calculates force on bodies
__global__ void calculate(vect *body, float *mass, node *nodes, vect *force, int n, float theta)
{
int index=blockDim.x*blockIdx.x+threadIdx.x;
int l=((1<<(2*(lvl-1)))-1)/3; //total nodes in tree upto max depth
while (index<n) //'while' loop takes care if total number more than total threads in kernel
{
int st[4*(lvl)]; //using array as stack
int curr=0; //variable showing current top index
st[curr]=0;
vect bd=body[index];
while (curr>=0) //for each body do DFS until reached leaf
{
int t=st[curr];
curr--;
node nd=nodes[t];
float s=fmax(nd.max.x-nd.min.x, nd.max.y-nd.min.y);
float x=bd.x-nd.body.x, y=bd.y-nd.body.y;
float dist=sqrt(x*x+y*y);
float val=FLT_MAX;
if (dist>0) val=s/dist;
if (val<theta) //Barnes-Hutt approximation
{
vect frc=gravity(nd.body, bd, nd.mass, mass[index]);
force[index].x+=frc.x;
force[index].y+=frc.y;
}
else
{
if (t>=l) //if reached leaf
{
vect frc=gravity(nd.body, bd, nd.mass, mass[index]);
force[index].x+=frc.x;
force[index].y+=frc.y;
continue;
}
for (int i=0;i<4;i++)
{
int temp=nd.child[i];
if (temp==-1 || nodes[temp].l>nodes[temp].r) continue;
st[++curr]=temp;
}
}
}
index+=(blockDim.x*gridDim.x); //will take care if total number more than total threads by incrementing index by total number of threads in kernel
}
}
float maxx(float a, float b)
{
return (a<b?b:a);
}
float minn(float a, float b)
{
return (a<b?a:b);
}
int main()
{
int n;
printf("n : ");
scanf("%d", &n);
vect body[n];
float mass[n];
float m=0, x=0, y=0;
for (int i=0;i<n;i++)
{
body[i].x=rand()%1000000;
body[i].y=rand()%1000000;
mass[i]=rand()%1000000;
m+=mass[i], x+=body[i].x, y+=body[i].y;
}
x/=n, y/=n; //centre of mass of the whole system
vect force[n];
vect *min;
vect *max;
for (int i=0;i<n;i++) force[i].x=force[i].y=0;
vect *dforce;
vect *dbody;
float *dmass;
int s=sizeof(vect)*n;
int sz=sizeof(float)*n;
hipMalloc(&dbody, s);
hipMalloc(&dmass, sz);
hipMalloc(&dforce, s);
hipMemset(dforce, 0, s);
hipMalloc(&min, s);
hipMalloc(&max, s);
hipMemcpy(dbody, body, s, hipMemcpyHostToDevice);
hipMemcpy(dmass, mass, sz, hipMemcpyHostToDevice);
int val=32;
int block = val;
int grid = val;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
//This is kernel 1 which devided into 2 parts
//bassically it find minimum and maximum from
//the n bodies
findMinMax<<<grid, block>>>(dbody, min, max, n);
findMMinMax<<<1, block>>>(min, max, min, max, val);
hipEventRecord(stop);
hipEventSynchronize(stop);
//milliseconds find the total kernal time in GPU
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
vect gmin;
vect gmax;
hipMemcpy(&gmin, min, sizeof(vect), hipMemcpyDeviceToHost);
hipMemcpy(&gmax, max, sizeof(vect), hipMemcpyDeviceToHost);
int curr=1;
int tot=1<<(2*lvl);
tot=(tot-1)/3;
node h_nodes[tot];
for (int i=0;i<tot;i++)
{
for (int j=0;j<4;j++) h_nodes[i].child[j]=-1;
}
vect temp;
temp.x=x, temp.y=y;
h_nodes[0].body=temp, h_nodes[0].mass=m, h_nodes[0].l=0, h_nodes[0].r=n-1, h_nodes[0].min=gmin, h_nodes[0].max=gmax;
node *d_nodes;
hipMalloc(&d_nodes, sizeof(node)*tot);
hipMemcpy(d_nodes, h_nodes, sizeof(node)*tot, hipMemcpyHostToDevice);
float t;
for (int i=0;i<lvl-1;i++) //creation of tree level by level. Each thread is assigned a node in current level.
{
block = 1024;
grid=ceil((1.0*curr)/block);
grid = minn(grid, 20);
hipEventRecord(start);
construct<<<grid, block>>>(dbody, dmass, d_nodes, i, tot);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&t, start, stop);
milliseconds+=t;
curr*=4;
}
hipMemcpy(h_nodes, d_nodes, sizeof(node)*tot, hipMemcpyDeviceToHost);
float theta;
printf("theta : ");
scanf("%f", &theta);
grid=minn(20, ceil((1.0*n)/block));
printf("%d\n", grid);
hipEventRecord(start);
calculate<<<grid, block>>>(dbody, dmass, d_nodes, dforce, n, theta); //Each thread is assigned a body
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&t, start, stop);
milliseconds+=t;
hipMemcpy(force, dforce, s, hipMemcpyDeviceToHost);
hipMemcpy(body, dbody, s, hipMemcpyDeviceToHost);
hipMemcpy(mass, dmass, sz, hipMemcpyDeviceToHost);
x=0, y=0;
for(int i=0;i<n;i++)
{
printf("force %d : x %f y %f m %f : %.15f %.15f\n", i, body[i].x, body[i].y, mass[i], force[i].x, force[i].y);
x+=force[i].x, y+=force[i].y;
}
printf("gpu time : %f\n", milliseconds);
printf("x %f y %f\n", x, y);
} | .text
.file "main1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__findMinMaxP4vectS0_S0_i # -- Begin function _Z25__device_stub__findMinMaxP4vectS0_S0_i
.p2align 4, 0x90
.type _Z25__device_stub__findMinMaxP4vectS0_S0_i,@function
_Z25__device_stub__findMinMaxP4vectS0_S0_i: # @_Z25__device_stub__findMinMaxP4vectS0_S0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10findMinMaxP4vectS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__findMinMaxP4vectS0_S0_i, .Lfunc_end0-_Z25__device_stub__findMinMaxP4vectS0_S0_i
.cfi_endproc
# -- End function
.globl _Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i # -- Begin function _Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i
.p2align 4, 0x90
.type _Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i,@function
_Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i: # @_Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11findMMinMaxP4vectS0_S0_S0_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i, .Lfunc_end1-_Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__constructP4vectPfP4nodeii # -- Begin function _Z24__device_stub__constructP4vectPfP4nodeii
.p2align 4, 0x90
.type _Z24__device_stub__constructP4vectPfP4nodeii,@function
_Z24__device_stub__constructP4vectPfP4nodeii: # @_Z24__device_stub__constructP4vectPfP4nodeii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9constructP4vectPfP4nodeii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z24__device_stub__constructP4vectPfP4nodeii, .Lfunc_end2-_Z24__device_stub__constructP4vectPfP4nodeii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__calculateP4vectPfP4nodeS0_if # -- Begin function _Z24__device_stub__calculateP4vectPfP4nodeS0_if
.p2align 4, 0x90
.type _Z24__device_stub__calculateP4vectPfP4nodeS0_if,@function
_Z24__device_stub__calculateP4vectPfP4nodeS0_if: # @_Z24__device_stub__calculateP4vectPfP4nodeS0_if
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movss %xmm0, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9calculateP4vectPfP4nodeS0_if, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z24__device_stub__calculateP4vectPfP4nodeS0_if, .Lfunc_end3-_Z24__device_stub__calculateP4vectPfP4nodeS0_if
.cfi_endproc
# -- End function
.globl _Z4maxxff # -- Begin function _Z4maxxff
.p2align 4, 0x90
.type _Z4maxxff,@function
_Z4maxxff: # @_Z4maxxff
.cfi_startproc
# %bb.0:
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end4:
.size _Z4maxxff, .Lfunc_end4-_Z4maxxff
.cfi_endproc
# -- End function
.globl _Z4minnff # -- Begin function _Z4minnff
.p2align 4, 0x90
.type _Z4minnff,@function
_Z4minnff: # @_Z4minnff
.cfi_startproc
# %bb.0:
minss %xmm1, %xmm0
retq
.Lfunc_end5:
.size _Z4minnff, .Lfunc_end5-_Z4minnff
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x3f50000000000000 # double 9.765625E-4
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI6_1:
.long 0x41a00000 # float 20
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $328, %rsp # imm = 0x148
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq -44(%rbp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movq %rsp, -352(%rbp) # 8-byte Spill
movl -44(%rbp), %eax
movq %rsp, %rbx
leaq 15(,%rax,8), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
movl -44(%rbp), %r14d
movq %rsp, %r12
leaq 15(,%r14,4), %rax
andq $-16, %rax
subq %rax, %r12
movq %r12, %rsp
xorps %xmm0, %xmm0
testl %r14d, %r14d
jle .LBB6_1
# %bb.18: # %.lr.ph.preheader
xorl %r15d, %r15d
xorps %xmm3, %xmm3
xorps %xmm2, %xmm2
.p2align 4, 0x90
.LBB6_19: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm3, -48(%rbp) # 4-byte Spill
movss %xmm2, -64(%rbp) # 4-byte Spill
movss %xmm0, -72(%rbp) # 4-byte Spill
callq rand
cltq
imulq $1125899907, %rax, %rcx # imm = 0x431BDE83
movq %rcx, %rdx
shrq $63, %rdx
sarq $50, %rcx
addl %edx, %ecx
imull $1000000, %ecx, %ecx # imm = 0xF4240
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,8)
callq rand
cltq
imulq $1125899907, %rax, %rcx # imm = 0x431BDE83
movq %rcx, %rdx
shrq $63, %rdx
sarq $50, %rcx
addl %edx, %ecx
imull $1000000, %ecx, %ecx # imm = 0xF4240
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 4(%rbx,%r15,8)
callq rand
movss -48(%rbp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss -64(%rbp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
cltq
imulq $1125899907, %rax, %rcx # imm = 0x431BDE83
movq %rcx, %rdx
shrq $63, %rdx
sarq $50, %rcx
addl %edx, %ecx
imull $1000000, %ecx, %ecx # imm = 0xF4240
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r15,4)
addss (%rbx,%r15,8), %xmm3
addss 4(%rbx,%r15,8), %xmm2
movss -72(%rbp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, -72(%rbp) # 4-byte Spill
movss -72(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
incq %r15
movslq -44(%rbp), %r14
cmpq %r14, %r15
jl .LBB6_19
# %bb.20:
movss %xmm3, -48(%rbp) # 4-byte Spill
movss %xmm2, -64(%rbp) # 4-byte Spill
jmp .LBB6_2
.LBB6_1:
movss %xmm0, -64(%rbp) # 4-byte Spill
movss %xmm0, -48(%rbp) # 4-byte Spill
movss %xmm0, -72(%rbp) # 4-byte Spill
.LBB6_2: # %._crit_edge
movl %r14d, %edx
movq %rsp, %r15
leaq 15(,%rdx,8), %rax
andq $-16, %rax
subq %rax, %r15
movq %r15, %rsp
testl %r14d, %r14d
jle .LBB6_4
# %bb.3: # %.lr.ph156.preheader
shlq $3, %rdx
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB6_4: # %._crit_edge157
movq %r15, -328(%rbp) # 8-byte Spill
leal (,%r14,8), %eax
leal (,%r14,4), %r15d
movslq %eax, %r13
leaq -184(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
movslq %r15d, %r15
leaq -200(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq -272(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
movq -272(%rbp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq hipMemset
leaq -288(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq -280(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
movq -184(%rbp), %rdi
movq %rbx, %rsi
movq %r13, -312(%rbp) # 8-byte Spill
movq %r13, %rdx
movabsq $4294967328, %r13 # imm = 0x100000020
movl $1, %ecx
callq hipMemcpy
movq -200(%rbp), %rdi
movq %r12, %rsi
movq %r15, -320(%rbp) # 8-byte Spill
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq -176(%rbp), %rdi
callq hipEventCreate
leaq -80(%rbp), %rdi
callq hipEventCreate
movq -176(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_6
# %bb.5:
movq -184(%rbp), %rax
movq -288(%rbp), %rcx
movq -280(%rbp), %rdx
movl -44(%rbp), %esi
movq %rax, -160(%rbp)
movq %rcx, -152(%rbp)
movq %rdx, -144(%rbp)
movl %esi, -88(%rbp)
leaq -160(%rbp), %rax
movq %rax, -256(%rbp)
leaq -152(%rbp), %rax
movq %rax, -248(%rbp)
leaq -144(%rbp), %rax
movq %rax, -240(%rbp)
leaq -88(%rbp), %rax
movq %rax, -232(%rbp)
leaq -128(%rbp), %rdi
leaq -112(%rbp), %rsi
leaq -136(%rbp), %rdx
leaq -96(%rbp), %rcx
callq __hipPopCallConfiguration
movq -128(%rbp), %rsi
movl -120(%rbp), %edx
movq -112(%rbp), %rcx
movl -104(%rbp), %r8d
leaq -256(%rbp), %r9
movl $_Z10findMinMaxP4vectS0_S0_i, %edi
pushq -96(%rbp)
pushq -136(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_6:
movq %r12, -336(%rbp) # 8-byte Spill
cvtsi2ss %r14d, %xmm0
movss %xmm0, -292(%rbp) # 4-byte Spill
leaq -31(%r13), %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_8
# %bb.7:
movq -288(%rbp), %rax
movq -280(%rbp), %rcx
movq %rax, -160(%rbp)
movq %rcx, -152(%rbp)
movq %rax, -144(%rbp)
movq %rcx, -136(%rbp)
movl $32, -264(%rbp)
leaq -160(%rbp), %rax
movq %rax, -256(%rbp)
leaq -152(%rbp), %rax
movq %rax, -248(%rbp)
leaq -144(%rbp), %rax
movq %rax, -240(%rbp)
leaq -136(%rbp), %rax
movq %rax, -232(%rbp)
leaq -264(%rbp), %rax
movq %rax, -224(%rbp)
leaq -128(%rbp), %rdi
leaq -112(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -88(%rbp), %rcx
callq __hipPopCallConfiguration
movq -128(%rbp), %rsi
movl -120(%rbp), %edx
movq -112(%rbp), %rcx
movl -104(%rbp), %r8d
leaq -256(%rbp), %r9
movl $_Z11findMMinMaxP4vectS0_S0_S0_i, %edi
pushq -88(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_8:
movq %rbx, -344(%rbp) # 8-byte Spill
movss -48(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss -292(%rbp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
movss %xmm0, -48(%rbp) # 4-byte Spill
movss -64(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
movss %xmm0, -64(%rbp) # 4-byte Spill
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -80(%rbp), %rdi
callq hipEventSynchronize
movl $0, -52(%rbp)
movq -176(%rbp), %rsi
movq -80(%rbp), %rdx
leaq -52(%rbp), %rdi
callq hipEventElapsedTime
movq -288(%rbp), %rsi
leaq -264(%rbp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq -280(%rbp), %rsi
leaq -360(%rbp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq %rsp, %r12
addq $-4543824, %r12 # imm = 0xFFBAAAB0
movq %r12, %rsp
movl $12, %eax
pcmpeqd %xmm0, %xmm0
.p2align 4, 0x90
.LBB6_9: # %.preheader
# =>This Inner Loop Header: Depth=1
movdqu %xmm0, (%r12,%rax)
addq $52, %rax
cmpq $4543824, %rax # imm = 0x455550
jne .LBB6_9
# %bb.10:
movss -48(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r12)
movss -64(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 4(%r12)
movss -72(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 8(%r12)
movl $0, 28(%r12)
movl -44(%rbp), %eax
decl %eax
movl %eax, 32(%r12)
movq -264(%rbp), %rax
movq %rax, 36(%r12)
movq -360(%rbp), %rax
movq %rax, 44(%r12)
leaq -192(%rbp), %rdi
movl $4543812, %esi # imm = 0x455544
callq hipMalloc
movq -192(%rbp), %rdi
movl $1, %r14d
movl $4543812, %edx # imm = 0x455544
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r15d, %r15d
addq $992, %r13 # imm = 0x3E0
jmp .LBB6_11
.p2align 4, 0x90
.LBB6_13: # in Loop: Header=BB6_11 Depth=1
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -80(%rbp), %rdi
callq hipEventSynchronize
movq -176(%rbp), %rsi
movq -80(%rbp), %rdx
leaq -164(%rbp), %rdi
callq hipEventElapsedTime
movss -164(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss -52(%rbp), %xmm0
movss %xmm0, -52(%rbp)
shll $2, %r14d
incl %r15d
cmpl $8, %r15d
je .LBB6_14
.LBB6_11: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
mulsd .LCPI6_0(%rip), %xmm0
callq ceil@PLT
cvttpd2dq %xmm0, %xmm0
cvtdq2ps %xmm0, %xmm0
minss .LCPI6_1(%rip), %xmm0
cvttss2si %xmm0, %ebx
movq -176(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967328, %rax # imm = 0x100000020
leaq (%rax,%rbx), %rdi
addq $-32, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_13
# %bb.12: # in Loop: Header=BB6_11 Depth=1
movq -184(%rbp), %rax
movq -200(%rbp), %rcx
movq -192(%rbp), %rdx
movq %rax, -160(%rbp)
movq %rcx, -152(%rbp)
movq %rdx, -144(%rbp)
movl %r15d, -88(%rbp)
movl $87381, -168(%rbp) # imm = 0x15555
leaq -160(%rbp), %rax
movq %rax, -256(%rbp)
leaq -152(%rbp), %rax
movq %rax, -248(%rbp)
leaq -144(%rbp), %rax
movq %rax, -240(%rbp)
leaq -88(%rbp), %rax
movq %rax, -232(%rbp)
leaq -168(%rbp), %rax
movq %rax, -224(%rbp)
leaq -128(%rbp), %rdi
leaq -112(%rbp), %rsi
leaq -136(%rbp), %rdx
leaq -96(%rbp), %rcx
callq __hipPopCallConfiguration
movq -128(%rbp), %rsi
movl -120(%rbp), %edx
movq -112(%rbp), %rcx
movl -104(%rbp), %r8d
movl $_Z9constructP4vectPfP4nodeii, %edi
leaq -256(%rbp), %r9
pushq -96(%rbp)
pushq -136(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB6_13
.LBB6_14:
movq -192(%rbp), %rsi
movl $4543812, %edx # imm = 0x455544
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq -296(%rbp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
xorps %xmm0, %xmm0
cvtsi2sdl -44(%rbp), %xmm0
mulsd .LCPI6_0(%rip), %xmm0
callq ceil@PLT
cvtsd2ss %xmm0, %xmm0
movss .LCPI6_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
minss %xmm0, %xmm1
cvttss2si %xmm1, %r14d
movl $.L.str.4, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq -176(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967328, %rax # imm = 0x100000020
leaq (%rax,%r14), %rdi
addq $-32, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_16
# %bb.15:
movq -184(%rbp), %rax
movq -200(%rbp), %rcx
movq -192(%rbp), %rdx
movq -272(%rbp), %rsi
movl -44(%rbp), %edi
movss -296(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, -160(%rbp)
movq %rcx, -152(%rbp)
movq %rdx, -144(%rbp)
movq %rsi, -136(%rbp)
movl %edi, -168(%rbp)
movss %xmm0, -300(%rbp)
leaq -160(%rbp), %rax
movq %rax, -256(%rbp)
leaq -152(%rbp), %rax
movq %rax, -248(%rbp)
leaq -144(%rbp), %rax
movq %rax, -240(%rbp)
leaq -136(%rbp), %rax
movq %rax, -232(%rbp)
leaq -168(%rbp), %rax
movq %rax, -224(%rbp)
leaq -300(%rbp), %rax
movq %rax, -216(%rbp)
leaq -128(%rbp), %rdi
leaq -112(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -88(%rbp), %rcx
callq __hipPopCallConfiguration
movq -128(%rbp), %rsi
movl -120(%rbp), %edx
movq -112(%rbp), %rcx
movl -104(%rbp), %r8d
leaq -256(%rbp), %r9
movl $_Z9calculateP4vectPfP4nodeS0_if, %edi
pushq -88(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB6_16:
movq -80(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -80(%rbp), %rdi
callq hipEventSynchronize
movq -176(%rbp), %rsi
movq -80(%rbp), %rdx
leaq -164(%rbp), %rdi
callq hipEventElapsedTime
movss -164(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss -52(%rbp), %xmm0
movss %xmm0, -52(%rbp)
movq -272(%rbp), %rsi
movq -328(%rbp), %r12 # 8-byte Reload
movq %r12, %rdi
movq -312(%rbp), %r14 # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq -184(%rbp), %rsi
movq -344(%rbp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq -200(%rbp), %rsi
movq -336(%rbp), %r15 # 8-byte Reload
movq %r15, %rdi
movq -320(%rbp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
cmpl $0, -44(%rbp)
jle .LBB6_17
# %bb.23: # %.lr.ph166.preheader
xorps %xmm0, %xmm0
xorl %r14d, %r14d
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB6_24: # %.lr.ph166
# =>This Inner Loop Header: Depth=1
movss %xmm1, -64(%rbp) # 4-byte Spill
movss %xmm0, -72(%rbp) # 4-byte Spill
movss (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rbx,%r14,8), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movss (%r15,%r14,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movss (%r12,%r14,8), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss 4(%r12,%r14,8), %xmm4 # xmm4 = mem[0],zero,zero,zero
cvtss2sd %xmm3, %xmm3
cvtss2sd %xmm4, %xmm4
movl $.L.str.5, %edi
movl %r14d, %esi
movb $5, %al
callq printf
movss -64(%rbp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss -72(%rbp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss (%r12,%r14,8), %xmm0
addss 4(%r12,%r14,8), %xmm1
incq %r14
movslq -44(%rbp), %rax
cmpq %rax, %r14
jl .LBB6_24
# %bb.21: # %._crit_edge167.loopexit
cvtss2sd %xmm0, %xmm0
movsd %xmm0, -64(%rbp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movsd %xmm0, -72(%rbp) # 8-byte Spill
jmp .LBB6_22
.LBB6_17:
xorps %xmm0, %xmm0
movsd %xmm0, -72(%rbp) # 8-byte Spill
movsd %xmm0, -64(%rbp) # 8-byte Spill
.LBB6_22: # %._crit_edge167
movss -52(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.7, %edi
movsd -64(%rbp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd -72(%rbp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movb $2, %al
callq printf
movq -352(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10findMinMaxP4vectS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11findMMinMaxP4vectS0_S0_S0_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9constructP4vectPfP4nodeii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9calculateP4vectPfP4nodeS0_if, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10findMinMaxP4vectS0_S0_i,@object # @_Z10findMinMaxP4vectS0_S0_i
.section .rodata,"a",@progbits
.globl _Z10findMinMaxP4vectS0_S0_i
.p2align 3, 0x0
_Z10findMinMaxP4vectS0_S0_i:
.quad _Z25__device_stub__findMinMaxP4vectS0_S0_i
.size _Z10findMinMaxP4vectS0_S0_i, 8
.type _Z11findMMinMaxP4vectS0_S0_S0_i,@object # @_Z11findMMinMaxP4vectS0_S0_S0_i
.globl _Z11findMMinMaxP4vectS0_S0_S0_i
.p2align 3, 0x0
_Z11findMMinMaxP4vectS0_S0_S0_i:
.quad _Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i
.size _Z11findMMinMaxP4vectS0_S0_S0_i, 8
.type _Z9constructP4vectPfP4nodeii,@object # @_Z9constructP4vectPfP4nodeii
.globl _Z9constructP4vectPfP4nodeii
.p2align 3, 0x0
_Z9constructP4vectPfP4nodeii:
.quad _Z24__device_stub__constructP4vectPfP4nodeii
.size _Z9constructP4vectPfP4nodeii, 8
.type _Z9calculateP4vectPfP4nodeS0_if,@object # @_Z9calculateP4vectPfP4nodeS0_if
.globl _Z9calculateP4vectPfP4nodeS0_if
.p2align 3, 0x0
_Z9calculateP4vectPfP4nodeS0_if:
.quad _Z24__device_stub__calculateP4vectPfP4nodeS0_if
.size _Z9calculateP4vectPfP4nodeS0_if, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "n : "
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "theta : "
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d\n"
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "force %d : x %f y %f m %f : %.15f %.15f\n"
.size .L.str.5, 41
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "gpu time : %f\n"
.size .L.str.6, 15
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "x %f y %f\n"
.size .L.str.7, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10findMinMaxP4vectS0_S0_i"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11findMMinMaxP4vectS0_S0_S0_i"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9constructP4vectPfP4nodeii"
.size .L__unnamed_3, 29
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z9calculateP4vectPfP4nodeS0_if"
.size .L__unnamed_4, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__findMinMaxP4vectS0_S0_i
.addrsig_sym _Z26__device_stub__findMMinMaxP4vectS0_S0_S0_i
.addrsig_sym _Z24__device_stub__constructP4vectPfP4nodeii
.addrsig_sym _Z24__device_stub__calculateP4vectPfP4nodeS0_if
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10findMinMaxP4vectS0_S0_i
.addrsig_sym _Z11findMMinMaxP4vectS0_S0_S0_i
.addrsig_sym _Z9constructP4vectPfP4nodeii
.addrsig_sym _Z9calculateP4vectPfP4nodeS0_if
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
namespace ann {
// CUDA2
}
__global__ void kernel(int n, float *arr){
volatile int idx = threadIdx.x + blockDim.x*blockIdx.x;
if(idx >= n) return;
arr[idx] *= 2.0f;
} | code for sm_80
Function : _Z6kerneliPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FADD R5, R0, R0 ; /* 0x0000000000057221 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
namespace ann {
// CUDA2
}
__global__ void kernel(int n, float *arr){
volatile int idx = threadIdx.x + blockDim.x*blockIdx.x;
if(idx >= n) return;
arr[idx] *= 2.0f;
} | .file "tmpxft_00045d3f_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kerneliPfiPf
.type _Z26__device_stub__Z6kerneliPfiPf, @function
_Z26__device_stub__Z6kerneliPfiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kerneliPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6kerneliPfiPf, .-_Z26__device_stub__Z6kerneliPfiPf
.globl _Z6kerneliPf
.type _Z6kerneliPf, @function
_Z6kerneliPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kerneliPfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kerneliPf, .-_Z6kerneliPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kerneliPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kerneliPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
namespace ann {
// CUDA2
}
__global__ void kernel(int n, float *arr){
volatile int idx = threadIdx.x + blockDim.x*blockIdx.x;
if(idx >= n) return;
arr[idx] *= 2.0f;
} | #include <hip/hip_runtime.h>
#include "includes.h"
namespace ann {
// CUDA2
}
__global__ void kernel(int n, float *arr){
volatile int idx = threadIdx.x + blockDim.x*blockIdx.x;
if(idx >= n) return;
arr[idx] *= 2.0f;
} |
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