system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void warpTest()
{
printf("BlockId: %d, ThreadId: %d\n", blockIdx.x, threadIdx.x);
}
int example2()
{
warpTest << <5, 32 >> > ();
// îæèäàåì íàæàòèÿ ëþáîé êëàâèøè
getchar();
return 0;
} | code for sm_80
Function : _Z8warpTestv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void warpTest()
{
printf("BlockId: %d, ThreadId: %d\n", blockIdx.x, threadIdx.x);
}
int example2()
{
warpTest << <5, 32 >> > ();
// îæèäàåì íàæàòèÿ ëþáîé êëàâèøè
getchar();
return 0;
} | .file "tmpxft_00097c72_00000000-6_example2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8warpTestvv
.type _Z26__device_stub__Z8warpTestvv, @function
_Z26__device_stub__Z8warpTestvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8warpTestv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8warpTestvv, .-_Z26__device_stub__Z8warpTestvv
.globl _Z8warpTestv
.type _Z8warpTestv, @function
_Z8warpTestv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8warpTestvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8warpTestv, .-_Z8warpTestv
.globl _Z8example2v
.type _Z8example2v, @function
_Z8example2v:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $5, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movq stdin(%rip), %rdi
call getc@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8warpTestvv
jmp .L12
.cfi_endproc
.LFE2057:
.size _Z8example2v, .-_Z8example2v
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8warpTestv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8warpTestv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void warpTest()
{
printf("BlockId: %d, ThreadId: %d\n", blockIdx.x, threadIdx.x);
}
int example2()
{
warpTest << <5, 32 >> > ();
// îæèäàåì íàæàòèÿ ëþáîé êëàâèøè
getchar();
return 0;
} | #ifndef example2_def
#define example2_def
int example2();
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef example2_def
#define example2_def
int example2();
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef example2_def
#define example2_def
int example2();
#endif | .text
.file "example2.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8warpTestv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00097c72_00000000-6_example2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8warpTestvv
.type _Z26__device_stub__Z8warpTestvv, @function
_Z26__device_stub__Z8warpTestvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8warpTestv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8warpTestvv, .-_Z26__device_stub__Z8warpTestvv
.globl _Z8warpTestv
.type _Z8warpTestv, @function
_Z8warpTestv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8warpTestvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8warpTestv, .-_Z8warpTestv
.globl _Z8example2v
.type _Z8example2v, @function
_Z8example2v:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $5, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movq stdin(%rip), %rdi
call getc@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8warpTestvv
jmp .L12
.cfi_endproc
.LFE2057:
.size _Z8example2v, .-_Z8example2v
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8warpTestv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8warpTestv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "example2.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Based heavily on https://developer.nvidia.com/blog/cuda-refresher-cuda-programming-model/
#include <stdio.h>
const int N = 1024; const int blocksize = 16;
__global__ void add_matrix( float *a, float *b, float *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x; // blockIdx, blockDim and threadIdx are predefined
int j = blockIdx.y * blockDim.y + threadIdx.y; // variables - initialised from meta-arguments
int index = i + j*N;
if ( i < N && j < N ) // Keep indices in range
c[index] = a[index] + b[index];
}
int main(void){
const int size = N*N*sizeof(float);
float *a ; float *b; float *c ;
float maxError = 0.0f;
cudaMallocManaged( (void**)&a, size );
cudaMallocManaged( (void**)&b, size );
cudaMallocManaged( (void**)&c, size );
for ( int i = 0; i < N*N; ++i ) {
a[i] = 1.0f; b[i] = 3.5f; }
dim3 dimBlock( blocksize, blocksize ); // dim3 structure to deal with 1D, 2D or 3D thread collections.
dim3 dimGrid( N/dimBlock.x, N/dimBlock.y); // dimBlock.x - first dimension, dimBlock.y - second dimension
// dimBlock.z for third dimension (not used)
add_matrix<<<dimGrid, dimBlock>>>( a, b, c, N); // Note meta arguments that pass information on
// Number of thread groups (Grid) and number of
// threads in each group (Block).
// Wait for GPU to finish before accessing on host - major source of errors
cudaDeviceSynchronize();
for (int j = 0; j < N; j++){
for (int i = 0; i < N;i++) {
maxError = fmax(maxError, fabs(c[i+j*N]-4.5f));
}
}
printf("Max error: %.16f\n", maxError );
cudaFree( a ); cudaFree( b ); cudaFree( c ); // CLEAN UP, RETURN
return 0;
} | code for sm_80
Function : _Z10add_matrixPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Based heavily on https://developer.nvidia.com/blog/cuda-refresher-cuda-programming-model/
#include <stdio.h>
const int N = 1024; const int blocksize = 16;
__global__ void add_matrix( float *a, float *b, float *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x; // blockIdx, blockDim and threadIdx are predefined
int j = blockIdx.y * blockDim.y + threadIdx.y; // variables - initialised from meta-arguments
int index = i + j*N;
if ( i < N && j < N ) // Keep indices in range
c[index] = a[index] + b[index];
}
int main(void){
const int size = N*N*sizeof(float);
float *a ; float *b; float *c ;
float maxError = 0.0f;
cudaMallocManaged( (void**)&a, size );
cudaMallocManaged( (void**)&b, size );
cudaMallocManaged( (void**)&c, size );
for ( int i = 0; i < N*N; ++i ) {
a[i] = 1.0f; b[i] = 3.5f; }
dim3 dimBlock( blocksize, blocksize ); // dim3 structure to deal with 1D, 2D or 3D thread collections.
dim3 dimGrid( N/dimBlock.x, N/dimBlock.y); // dimBlock.x - first dimension, dimBlock.y - second dimension
// dimBlock.z for third dimension (not used)
add_matrix<<<dimGrid, dimBlock>>>( a, b, c, N); // Note meta arguments that pass information on
// Number of thread groups (Grid) and number of
// threads in each group (Block).
// Wait for GPU to finish before accessing on host - major source of errors
cudaDeviceSynchronize();
for (int j = 0; j < N; j++){
for (int i = 0; i < N;i++) {
maxError = fmax(maxError, fabs(c[i+j*N]-4.5f));
}
}
printf("Max error: %.16f\n", maxError );
cudaFree( a ); cudaFree( b ); cudaFree( c ); // CLEAN UP, RETURN
return 0;
} | .file "tmpxft_001a3254_00000000-6_matadd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_matrixPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
.globl _Z10add_matrixPfS_S_i
.type _Z10add_matrixPfS_S_i, @function
_Z10add_matrixPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10add_matrixPfS_S_i, .-_Z10add_matrixPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: %.16f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 8(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $1, 40(%rsp)
movl $64, 44(%rsp)
movl $64, 48(%rsp)
movl $1, 52(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %r12
leaq 4096(%r12), %rbp
addq $4198400, %r12
pxor %xmm1, %xmm1
.L14:
leaq -4096(%rbp), %rbx
.L15:
movss (%rbx), %xmm2
subss .LC3(%rip), %xmm2
andps .LC4(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movaps %xmm0, %xmm1
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
addq $4096, %rbp
cmpq %r12, %rbp
jne .L14
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
jmp .L13
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z10add_matrixPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_matrixPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1080033280
.align 4
.LC3:
.long 1083179008
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Based heavily on https://developer.nvidia.com/blog/cuda-refresher-cuda-programming-model/
#include <stdio.h>
const int N = 1024; const int blocksize = 16;
__global__ void add_matrix( float *a, float *b, float *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x; // blockIdx, blockDim and threadIdx are predefined
int j = blockIdx.y * blockDim.y + threadIdx.y; // variables - initialised from meta-arguments
int index = i + j*N;
if ( i < N && j < N ) // Keep indices in range
c[index] = a[index] + b[index];
}
int main(void){
const int size = N*N*sizeof(float);
float *a ; float *b; float *c ;
float maxError = 0.0f;
cudaMallocManaged( (void**)&a, size );
cudaMallocManaged( (void**)&b, size );
cudaMallocManaged( (void**)&c, size );
for ( int i = 0; i < N*N; ++i ) {
a[i] = 1.0f; b[i] = 3.5f; }
dim3 dimBlock( blocksize, blocksize ); // dim3 structure to deal with 1D, 2D or 3D thread collections.
dim3 dimGrid( N/dimBlock.x, N/dimBlock.y); // dimBlock.x - first dimension, dimBlock.y - second dimension
// dimBlock.z for third dimension (not used)
add_matrix<<<dimGrid, dimBlock>>>( a, b, c, N); // Note meta arguments that pass information on
// Number of thread groups (Grid) and number of
// threads in each group (Block).
// Wait for GPU to finish before accessing on host - major source of errors
cudaDeviceSynchronize();
for (int j = 0; j < N; j++){
for (int i = 0; i < N;i++) {
maxError = fmax(maxError, fabs(c[i+j*N]-4.5f));
}
}
printf("Max error: %.16f\n", maxError );
cudaFree( a ); cudaFree( b ); cudaFree( c ); // CLEAN UP, RETURN
return 0;
} | // Based heavily on https://developer.nvidia.com/blog/cuda-refresher-cuda-programming-model/
#include <hip/hip_runtime.h>
#include <stdio.h>
const int N = 1024; const int blocksize = 16;
__global__ void add_matrix( float *a, float *b, float *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x; // blockIdx, blockDim and threadIdx are predefined
int j = blockIdx.y * blockDim.y + threadIdx.y; // variables - initialised from meta-arguments
int index = i + j*N;
if ( i < N && j < N ) // Keep indices in range
c[index] = a[index] + b[index];
}
int main(void){
const int size = N*N*sizeof(float);
float *a ; float *b; float *c ;
float maxError = 0.0f;
hipMallocManaged( (void**)&a, size );
hipMallocManaged( (void**)&b, size );
hipMallocManaged( (void**)&c, size );
for ( int i = 0; i < N*N; ++i ) {
a[i] = 1.0f; b[i] = 3.5f; }
dim3 dimBlock( blocksize, blocksize ); // dim3 structure to deal with 1D, 2D or 3D thread collections.
dim3 dimGrid( N/dimBlock.x, N/dimBlock.y); // dimBlock.x - first dimension, dimBlock.y - second dimension
// dimBlock.z for third dimension (not used)
add_matrix<<<dimGrid, dimBlock>>>( a, b, c, N); // Note meta arguments that pass information on
// Number of thread groups (Grid) and number of
// threads in each group (Block).
// Wait for GPU to finish before accessing on host - major source of errors
hipDeviceSynchronize();
for (int j = 0; j < N; j++){
for (int i = 0; i < N;i++) {
maxError = fmax(maxError, fabs(c[i+j*N]-4.5f));
}
}
printf("Max error: %.16f\n", maxError );
hipFree( a ); hipFree( b ); hipFree( c ); // CLEAN UP, RETURN
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Based heavily on https://developer.nvidia.com/blog/cuda-refresher-cuda-programming-model/
#include <hip/hip_runtime.h>
#include <stdio.h>
const int N = 1024; const int blocksize = 16;
__global__ void add_matrix( float *a, float *b, float *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x; // blockIdx, blockDim and threadIdx are predefined
int j = blockIdx.y * blockDim.y + threadIdx.y; // variables - initialised from meta-arguments
int index = i + j*N;
if ( i < N && j < N ) // Keep indices in range
c[index] = a[index] + b[index];
}
int main(void){
const int size = N*N*sizeof(float);
float *a ; float *b; float *c ;
float maxError = 0.0f;
hipMallocManaged( (void**)&a, size );
hipMallocManaged( (void**)&b, size );
hipMallocManaged( (void**)&c, size );
for ( int i = 0; i < N*N; ++i ) {
a[i] = 1.0f; b[i] = 3.5f; }
dim3 dimBlock( blocksize, blocksize ); // dim3 structure to deal with 1D, 2D or 3D thread collections.
dim3 dimGrid( N/dimBlock.x, N/dimBlock.y); // dimBlock.x - first dimension, dimBlock.y - second dimension
// dimBlock.z for third dimension (not used)
add_matrix<<<dimGrid, dimBlock>>>( a, b, c, N); // Note meta arguments that pass information on
// Number of thread groups (Grid) and number of
// threads in each group (Block).
// Wait for GPU to finish before accessing on host - major source of errors
hipDeviceSynchronize();
for (int j = 0; j < N; j++){
for (int i = 0; i < N;i++) {
maxError = fmax(maxError, fabs(c[i+j*N]-4.5f));
}
}
printf("Max error: %.16f\n", maxError );
hipFree( a ); hipFree( b ); hipFree( c ); // CLEAN UP, RETURN
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_matrixPfS_S_i
.globl _Z10add_matrixPfS_S_i
.p2align 8
.type _Z10add_matrixPfS_S_i,@function
_Z10add_matrixPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_matrixPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_matrixPfS_S_i, .Lfunc_end0-_Z10add_matrixPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_matrixPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_matrixPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Based heavily on https://developer.nvidia.com/blog/cuda-refresher-cuda-programming-model/
#include <hip/hip_runtime.h>
#include <stdio.h>
const int N = 1024; const int blocksize = 16;
__global__ void add_matrix( float *a, float *b, float *c, int N) {
int i = blockIdx.x * blockDim.x + threadIdx.x; // blockIdx, blockDim and threadIdx are predefined
int j = blockIdx.y * blockDim.y + threadIdx.y; // variables - initialised from meta-arguments
int index = i + j*N;
if ( i < N && j < N ) // Keep indices in range
c[index] = a[index] + b[index];
}
int main(void){
const int size = N*N*sizeof(float);
float *a ; float *b; float *c ;
float maxError = 0.0f;
hipMallocManaged( (void**)&a, size );
hipMallocManaged( (void**)&b, size );
hipMallocManaged( (void**)&c, size );
for ( int i = 0; i < N*N; ++i ) {
a[i] = 1.0f; b[i] = 3.5f; }
dim3 dimBlock( blocksize, blocksize ); // dim3 structure to deal with 1D, 2D or 3D thread collections.
dim3 dimGrid( N/dimBlock.x, N/dimBlock.y); // dimBlock.x - first dimension, dimBlock.y - second dimension
// dimBlock.z for third dimension (not used)
add_matrix<<<dimGrid, dimBlock>>>( a, b, c, N); // Note meta arguments that pass information on
// Number of thread groups (Grid) and number of
// threads in each group (Block).
// Wait for GPU to finish before accessing on host - major source of errors
hipDeviceSynchronize();
for (int j = 0; j < N; j++){
for (int i = 0; i < N;i++) {
maxError = fmax(maxError, fabs(c[i+j*N]-4.5f));
}
}
printf("Max error: %.16f\n", maxError );
hipFree( a ); hipFree( b ); hipFree( c ); // CLEAN UP, RETURN
return 0;
} | .text
.file "matadd.hip"
.globl _Z25__device_stub__add_matrixPfS_S_i # -- Begin function _Z25__device_stub__add_matrixPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__add_matrixPfS_S_i,@function
_Z25__device_stub__add_matrixPfS_S_i: # @_Z25__device_stub__add_matrixPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_matrixPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__add_matrixPfS_S_i, .Lfunc_end0-_Z25__device_stub__add_matrixPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0900000 # float -4.5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 24(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1080033280, (%rdx,%rcx,4) # imm = 0x40600000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10add_matrixPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorps %xmm0, %xmm0
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %edx, %edx
movaps %xmm0, %xmm3
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rdx,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
addss %xmm1, %xmm4
andps %xmm2, %xmm4
cmpunordss %xmm3, %xmm3
movaps %xmm3, %xmm5
andps %xmm4, %xmm5
maxss %xmm0, %xmm4
andnps %xmm4, %xmm3
orps %xmm5, %xmm3
movaps %xmm3, %xmm0
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %rax
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB1_5
# %bb.8:
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_matrixPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10add_matrixPfS_S_i,@object # @_Z10add_matrixPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10add_matrixPfS_S_i
.p2align 3, 0x0
_Z10add_matrixPfS_S_i:
.quad _Z25__device_stub__add_matrixPfS_S_i
.size _Z10add_matrixPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: %.16f\n"
.size .L.str, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_matrixPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_matrixPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_matrixPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10add_matrixPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10add_matrixPfS_S_i
.globl _Z10add_matrixPfS_S_i
.p2align 8
.type _Z10add_matrixPfS_S_i,@function
_Z10add_matrixPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_matrixPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10add_matrixPfS_S_i, .Lfunc_end0-_Z10add_matrixPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_matrixPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10add_matrixPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a3254_00000000-6_matadd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10add_matrixPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
.globl _Z10add_matrixPfS_S_i
.type _Z10add_matrixPfS_S_i, @function
_Z10add_matrixPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10add_matrixPfS_S_i, .-_Z10add_matrixPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: %.16f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 8(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $1, 40(%rsp)
movl $64, 44(%rsp)
movl $64, 48(%rsp)
movl $1, 52(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %r12
leaq 4096(%r12), %rbp
addq $4198400, %r12
pxor %xmm1, %xmm1
.L14:
leaq -4096(%rbp), %rbx
.L15:
movss (%rbx), %xmm2
subss .LC3(%rip), %xmm2
andps .LC4(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movaps %xmm0, %xmm1
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
addq $4096, %rbp
cmpq %r12, %rbp
jne .L14
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10add_matrixPfS_S_iPfS_S_i
jmp .L13
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z10add_matrixPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10add_matrixPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1080033280
.align 4
.LC3:
.long 1083179008
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matadd.hip"
.globl _Z25__device_stub__add_matrixPfS_S_i # -- Begin function _Z25__device_stub__add_matrixPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__add_matrixPfS_S_i,@function
_Z25__device_stub__add_matrixPfS_S_i: # @_Z25__device_stub__add_matrixPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10add_matrixPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__add_matrixPfS_S_i, .Lfunc_end0-_Z25__device_stub__add_matrixPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0900000 # float -4.5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 24(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1080033280, (%rdx,%rcx,4) # imm = 0x40600000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10add_matrixPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorps %xmm0, %xmm0
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
xorl %edx, %edx
movaps %xmm0, %xmm3
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rdx,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
addss %xmm1, %xmm4
andps %xmm2, %xmm4
cmpunordss %xmm3, %xmm3
movaps %xmm3, %xmm5
andps %xmm4, %xmm5
maxss %xmm0, %xmm4
andnps %xmm4, %xmm3
orps %xmm5, %xmm3
movaps %xmm3, %xmm0
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %rax
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB1_5
# %bb.8:
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10add_matrixPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10add_matrixPfS_S_i,@object # @_Z10add_matrixPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10add_matrixPfS_S_i
.p2align 3, 0x0
_Z10add_matrixPfS_S_i:
.quad _Z25__device_stub__add_matrixPfS_S_i
.size _Z10add_matrixPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: %.16f\n"
.size .L.str, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10add_matrixPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__add_matrixPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10add_matrixPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
World using CUDA
**
** The string "Hello World!" is mangled then restored using a common CUDA idiom
**
** Byron Galbraith
** 2009-02-18
*/
#include <cuda.h>
#include <stdio.h>
// Prototypes
extern "C" __global__ void helloWorld(char*);
// Host function
int
main(int argc, char** argv)
{
int i;
// desired output
char str[] = "Hello World!";
// mangle contents of output
// the null character is left intact for simplicity
for(i = 0; i < 12; i++)
str[i] -= i;
// allocate memory on the device
char *d_str;
size_t size = sizeof(str);
cudaMalloc((void**)&d_str, size);
// copy the string to the device
cudaMemcpy(d_str, str, size, cudaMemcpyHostToDevice);
// set the grid and block sizes
dim3 dimGrid(2); // one block per word
dim3 dimBlock(6); // one thread per character
// invoke the kernel
helloWorld<<< dimGrid, dimBlock >>>(d_str);
// retrieve the results from the device
cudaMemcpy(str, d_str, size, cudaMemcpyDeviceToHost);
// free up the allocated memory on the device
cudaFree(d_str);
// everyone's favorite part
printf("%s\n", str);
return 0;
}
// Device kernel
__global__ void
helloWorld(char* str)
{
// determine where in the thread grid we are
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// unmangle output
str[idx] += idx;
} | code for sm_80
Function : helloWorld
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*0060*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*0070*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1100 */
/*0080*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
World using CUDA
**
** The string "Hello World!" is mangled then restored using a common CUDA idiom
**
** Byron Galbraith
** 2009-02-18
*/
#include <cuda.h>
#include <stdio.h>
// Prototypes
extern "C" __global__ void helloWorld(char*);
// Host function
int
main(int argc, char** argv)
{
int i;
// desired output
char str[] = "Hello World!";
// mangle contents of output
// the null character is left intact for simplicity
for(i = 0; i < 12; i++)
str[i] -= i;
// allocate memory on the device
char *d_str;
size_t size = sizeof(str);
cudaMalloc((void**)&d_str, size);
// copy the string to the device
cudaMemcpy(d_str, str, size, cudaMemcpyHostToDevice);
// set the grid and block sizes
dim3 dimGrid(2); // one block per word
dim3 dimBlock(6); // one thread per character
// invoke the kernel
helloWorld<<< dimGrid, dimBlock >>>(d_str);
// retrieve the results from the device
cudaMemcpy(str, d_str, size, cudaMemcpyDeviceToHost);
// free up the allocated memory on the device
cudaFree(d_str);
// everyone's favorite part
printf("%s\n", str);
return 0;
}
// Device kernel
__global__ void
helloWorld(char* str)
{
// determine where in the thread grid we are
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// unmangle output
str[idx] += idx;
} | .file "tmpxft_000b2647_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10helloWorldPcPc
.type _Z30__device_stub__Z10helloWorldPcPc, @function
_Z30__device_stub__Z10helloWorldPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq helloWorld(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10helloWorldPcPc, .-_Z30__device_stub__Z10helloWorldPcPc
.globl helloWorld
.type helloWorld, @function
helloWorld:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10helloWorldPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size helloWorld, .-helloWorld
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $8022916924116329800, %rax
movq %rax, 43(%rsp)
movabsq $9399091170596640, %rax
movq %rax, 48(%rsp)
leaq 43(%rsp), %rdx
movl $0, %eax
.L12:
subb %al, (%rdx)
addl $1, %eax
addq $1, %rdx
cmpl $12, %eax
jne .L12
leaq 8(%rsp), %rdi
movl $13, %esi
call cudaMalloc@PLT
leaq 43(%rsp), %rsi
movl $1, %ecx
movl $13, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $6, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
leaq 43(%rsp), %rbx
movl $2, %ecx
movl $13, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z30__device_stub__Z10helloWorldPcPc
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "helloWorld"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq helloWorld(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
World using CUDA
**
** The string "Hello World!" is mangled then restored using a common CUDA idiom
**
** Byron Galbraith
** 2009-02-18
*/
#include <cuda.h>
#include <stdio.h>
// Prototypes
extern "C" __global__ void helloWorld(char*);
// Host function
int
main(int argc, char** argv)
{
int i;
// desired output
char str[] = "Hello World!";
// mangle contents of output
// the null character is left intact for simplicity
for(i = 0; i < 12; i++)
str[i] -= i;
// allocate memory on the device
char *d_str;
size_t size = sizeof(str);
cudaMalloc((void**)&d_str, size);
// copy the string to the device
cudaMemcpy(d_str, str, size, cudaMemcpyHostToDevice);
// set the grid and block sizes
dim3 dimGrid(2); // one block per word
dim3 dimBlock(6); // one thread per character
// invoke the kernel
helloWorld<<< dimGrid, dimBlock >>>(d_str);
// retrieve the results from the device
cudaMemcpy(str, d_str, size, cudaMemcpyDeviceToHost);
// free up the allocated memory on the device
cudaFree(d_str);
// everyone's favorite part
printf("%s\n", str);
return 0;
}
// Device kernel
__global__ void
helloWorld(char* str)
{
// determine where in the thread grid we are
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// unmangle output
str[idx] += idx;
} | /*
World using CUDA
**
** The string "Hello World!" is mangled then restored using a common CUDA idiom
**
** Byron Galbraith
** 2009-02-18
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
// Prototypes
extern "C" __global__ void helloWorld(char*);
// Host function
int
main(int argc, char** argv)
{
int i;
// desired output
char str[] = "Hello World!";
// mangle contents of output
// the null character is left intact for simplicity
for(i = 0; i < 12; i++)
str[i] -= i;
// allocate memory on the device
char *d_str;
size_t size = sizeof(str);
hipMalloc((void**)&d_str, size);
// copy the string to the device
hipMemcpy(d_str, str, size, hipMemcpyHostToDevice);
// set the grid and block sizes
dim3 dimGrid(2); // one block per word
dim3 dimBlock(6); // one thread per character
// invoke the kernel
helloWorld<<< dimGrid, dimBlock >>>(d_str);
// retrieve the results from the device
hipMemcpy(str, d_str, size, hipMemcpyDeviceToHost);
// free up the allocated memory on the device
hipFree(d_str);
// everyone's favorite part
printf("%s\n", str);
return 0;
}
// Device kernel
__global__ void
helloWorld(char* str)
{
// determine where in the thread grid we are
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// unmangle output
str[idx] += idx;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
World using CUDA
**
** The string "Hello World!" is mangled then restored using a common CUDA idiom
**
** Byron Galbraith
** 2009-02-18
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
// Prototypes
extern "C" __global__ void helloWorld(char*);
// Host function
int
main(int argc, char** argv)
{
int i;
// desired output
char str[] = "Hello World!";
// mangle contents of output
// the null character is left intact for simplicity
for(i = 0; i < 12; i++)
str[i] -= i;
// allocate memory on the device
char *d_str;
size_t size = sizeof(str);
hipMalloc((void**)&d_str, size);
// copy the string to the device
hipMemcpy(d_str, str, size, hipMemcpyHostToDevice);
// set the grid and block sizes
dim3 dimGrid(2); // one block per word
dim3 dimBlock(6); // one thread per character
// invoke the kernel
helloWorld<<< dimGrid, dimBlock >>>(d_str);
// retrieve the results from the device
hipMemcpy(str, d_str, size, hipMemcpyDeviceToHost);
// free up the allocated memory on the device
hipFree(d_str);
// everyone's favorite part
printf("%s\n", str);
return 0;
}
// Device kernel
__global__ void
helloWorld(char* str)
{
// determine where in the thread grid we are
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// unmangle output
str[idx] += idx;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected helloWorld
.globl helloWorld
.p2align 8
.type helloWorld,@function
helloWorld:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v0, 31, v1
v_add_co_u32 v2, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v0, vcc_lo
global_load_u8 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v0, v0, v1
global_store_b8 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel helloWorld
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size helloWorld, .Lfunc_end0-helloWorld
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: helloWorld
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: helloWorld.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
World using CUDA
**
** The string "Hello World!" is mangled then restored using a common CUDA idiom
**
** Byron Galbraith
** 2009-02-18
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
// Prototypes
extern "C" __global__ void helloWorld(char*);
// Host function
int
main(int argc, char** argv)
{
int i;
// desired output
char str[] = "Hello World!";
// mangle contents of output
// the null character is left intact for simplicity
for(i = 0; i < 12; i++)
str[i] -= i;
// allocate memory on the device
char *d_str;
size_t size = sizeof(str);
hipMalloc((void**)&d_str, size);
// copy the string to the device
hipMemcpy(d_str, str, size, hipMemcpyHostToDevice);
// set the grid and block sizes
dim3 dimGrid(2); // one block per word
dim3 dimBlock(6); // one thread per character
// invoke the kernel
helloWorld<<< dimGrid, dimBlock >>>(d_str);
// retrieve the results from the device
hipMemcpy(str, d_str, size, hipMemcpyDeviceToHost);
// free up the allocated memory on the device
hipFree(d_str);
// everyone's favorite part
printf("%s\n", str);
return 0;
}
// Device kernel
__global__ void
helloWorld(char* str)
{
// determine where in the thread grid we are
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// unmangle output
str[idx] += idx;
} | .text
.file "hello.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movabsq $8022916924116329800, %rax # imm = 0x6F57206F6C6C6548
movq %rax, 19(%rsp)
movl $560229490, 27(%rsp) # imm = 0x21646C72
movb $0, 31(%rsp)
leaq 19(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movzbl (%rax), %edx
addl %ecx, %edx
movb %dl, (%rax)
decq %rcx
incq %rax
cmpq $-12, %rcx
jne .LBB0_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $13, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 19(%rsp), %rsi
movl $13, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 32(%rsp), %r9
movl $helloWorld, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
movq 8(%rsp), %rsi
leaq 19(%rsp), %rbx
movl $13, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq puts@PLT
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl __device_stub__helloWorld # -- Begin function __device_stub__helloWorld
.p2align 4, 0x90
.type __device_stub__helloWorld,@function
__device_stub__helloWorld: # @__device_stub__helloWorld
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $helloWorld, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size __device_stub__helloWorld, .Lfunc_end1-__device_stub__helloWorld
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $helloWorld, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type helloWorld,@object # @helloWorld
.section .rodata,"a",@progbits
.globl helloWorld
.p2align 3, 0x0
helloWorld:
.quad __device_stub__helloWorld
.size helloWorld, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "helloWorld"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__helloWorld
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym helloWorld
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : helloWorld
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*0060*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*0070*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1100 */
/*0080*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected helloWorld
.globl helloWorld
.p2align 8
.type helloWorld,@function
helloWorld:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v0, 31, v1
v_add_co_u32 v2, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v0, vcc_lo
global_load_u8 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v0, v0, v1
global_store_b8 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel helloWorld
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size helloWorld, .Lfunc_end0-helloWorld
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: helloWorld
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: helloWorld.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b2647_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10helloWorldPcPc
.type _Z30__device_stub__Z10helloWorldPcPc, @function
_Z30__device_stub__Z10helloWorldPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq helloWorld(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10helloWorldPcPc, .-_Z30__device_stub__Z10helloWorldPcPc
.globl helloWorld
.type helloWorld, @function
helloWorld:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10helloWorldPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size helloWorld, .-helloWorld
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $8022916924116329800, %rax
movq %rax, 43(%rsp)
movabsq $9399091170596640, %rax
movq %rax, 48(%rsp)
leaq 43(%rsp), %rdx
movl $0, %eax
.L12:
subb %al, (%rdx)
addl $1, %eax
addq $1, %rdx
cmpl $12, %eax
jne .L12
leaq 8(%rsp), %rdi
movl $13, %esi
call cudaMalloc@PLT
leaq 43(%rsp), %rsi
movl $1, %ecx
movl $13, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $6, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
leaq 43(%rsp), %rbx
movl $2, %ecx
movl $13, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z30__device_stub__Z10helloWorldPcPc
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "helloWorld"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq helloWorld(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movabsq $8022916924116329800, %rax # imm = 0x6F57206F6C6C6548
movq %rax, 19(%rsp)
movl $560229490, 27(%rsp) # imm = 0x21646C72
movb $0, 31(%rsp)
leaq 19(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movzbl (%rax), %edx
addl %ecx, %edx
movb %dl, (%rax)
decq %rcx
incq %rax
cmpq $-12, %rcx
jne .LBB0_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $13, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 19(%rsp), %rsi
movl $13, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 32(%rsp), %r9
movl $helloWorld, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
movq 8(%rsp), %rsi
leaq 19(%rsp), %rbx
movl $13, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq puts@PLT
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl __device_stub__helloWorld # -- Begin function __device_stub__helloWorld
.p2align 4, 0x90
.type __device_stub__helloWorld,@function
__device_stub__helloWorld: # @__device_stub__helloWorld
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $helloWorld, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size __device_stub__helloWorld, .Lfunc_end1-__device_stub__helloWorld
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $helloWorld, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type helloWorld,@object # @helloWorld
.section .rodata,"a",@progbits
.globl helloWorld
.p2align 3, 0x0
helloWorld:
.quad __device_stub__helloWorld
.size helloWorld, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "helloWorld"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__helloWorld
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym helloWorld
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "device_launch_parameters.h"
#include <cuda_runtime.h>
#include<stdlib.h>
#include<iostream>
using namespace std;
#define SIZE 1024
//call from host func (like order to gpu)
__global__ void vectoradd(int* a, int* b, int* c,int n) {
int i = threadIdx.x;//to distinct thread
for (i = 0; i < n; i++)c[i] = a[i] + b[i];
//do sum of each thread
}
int main() {
int* a, * b, * c;//host variable
int* d_a, * d_b, * d_c;//device variable
//malloc to host memory
a = (int*)malloc(SIZE * sizeof(int));
b = (int*)malloc(SIZE * sizeof(int));
c = (int*)malloc(SIZE * sizeof(int));
//malloc to device memory
cudaMalloc(&d_a, SIZE * sizeof(int));
cudaMalloc(&d_b, SIZE * sizeof(int));
cudaMalloc(&d_c, SIZE * sizeof(int));
//initialize variables
for (int i = 0; i < SIZE; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
}
//memcopy to device variables
cudaMemcpy(d_a, a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, SIZE * sizeof(int), cudaMemcpyHostToDevice);
//call vectoradd func using 1 block, 1024 threads
vectoradd <<< 1, SIZE >>> (d_a, d_b, d_c, SIZE);
//memcopy to host, save device to host
cudaMemcpy(a, d_a, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(b, d_b, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(c, d_c, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
//print result of c variable
for (int i = 0; i < SIZE; i++)
cout << "c[" << i << "]=" << c[i] << "\n";
//memory free to host
free(a);
free(b);
free(c);
//memory free to device
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z9vectoraddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xb80 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*00d0*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fd400078e00ff */
/*0130*/ @!P0 BRA 0x990 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x670 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x004fca00078e020a */
/*01b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*01c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x004fca00078e020b */
/*01f0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0200*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d7824 */
/* 0x004fca00078e020d */
/*0230*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x008fca0007ffe0ff */
/*0270*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0280*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x010fca00078e020a */
/*02b0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*02c0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x010fca00078e020b */
/*02f0*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0300*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d7824 */
/* 0x010fca00078e020d */
/*0330*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x0005e8000c10190c */
/*0340*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x010fca0007ffe0ff */
/*0370*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0007e8000c10190c */
/*0380*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x20] ; /* 0x0000200c060a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x010fca00078e020a */
/*03b0*/ STG.E [R4.64+0x20], R9 ; /* 0x0000200904007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R10, [R2.64+0x24] ; /* 0x0000240c020a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R6.64+0x24] ; /* 0x0000240c060b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x010fca00078e020b */
/*03f0*/ STG.E [R4.64+0x24], R11 ; /* 0x0000240b04007986 */
/* 0x0003e8000c10190c */
/*0400*/ LDG.E R10, [R2.64+0x28] ; /* 0x0000280c020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R6.64+0x28] ; /* 0x0000280c060d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d7824 */
/* 0x010fca00078e020d */
/*0430*/ STG.E [R4.64+0x28], R13 ; /* 0x0000280d04007986 */
/* 0x0005e8000c10190c */
/*0440*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R6.64+0x2c] ; /* 0x00002c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x010fca0007ffe0ff */
/*0470*/ STG.E [R4.64+0x2c], R15 ; /* 0x00002c0f04007986 */
/* 0x0007e8000c10190c */
/*0480*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R6.64+0x30] ; /* 0x0000300c060a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x010fca00078e020a */
/*04b0*/ STG.E [R4.64+0x30], R9 ; /* 0x0000300904007986 */
/* 0x000fe8000c10190c */
/*04c0*/ LDG.E R10, [R2.64+0x34] ; /* 0x0000340c020a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R6.64+0x34] ; /* 0x0000340c060b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x010fca00078e020b */
/*04f0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0001e8000c10190c */
/*0500*/ LDG.E R10, [R2.64+0x38] ; /* 0x0000380c020a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R6.64+0x38] ; /* 0x0000380c060d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R12, P1, R2, 0x40, RZ ; /* 0x00000040020c7810 */
/* 0x000fe40007f3e0ff */
/*0530*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d7824 */
/* 0x010fca00078e020d */
/*0550*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0560*/ LDG.E R10, [R2.64+0x3c] ; /* 0x00003c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0570*/ LDG.E R15, [R6.64+0x3c] ; /* 0x00003c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0580*/ IMAD.X R11, RZ, RZ, R3, P1 ; /* 0x000000ffff0b7224 */
/* 0x001fe200008e0603 */
/*0590*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*05a0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*05b0*/ IADD3 R9, P3, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fc40007f7e0ff */
/*05c0*/ IADD3 R14, P2, R6, 0x40, RZ ; /* 0x00000040060e7810 */
/* 0x000fe20007f5e0ff */
/*05d0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe400078e000c */
/*05e0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000b */
/*05f0*/ MOV R6, R14 ; /* 0x0000000e00067202 */
/* 0x008fe20000000f00 */
/*0600*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e0607 */
/*0610*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x004fe40007ffe0ff */
/*0620*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc60001ffe4ff */
/*0630*/ STG.E [R4.64+0x3c], R15 ; /* 0x00003c0f04007986 */
/* 0x0001e4000c10190c */
/*0640*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0009 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0660*/ @P1 BRA 0x180 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x970 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ IADD3 R9, R9, R10, RZ ; /* 0x0000000a09097210 */
/* 0x004fca0007ffe0ff */
/*06c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*06d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x004fca00078e020b */
/*0700*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0710*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0730*/ IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d7824 */
/* 0x004fca00078e020d */
/*0740*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0750*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0760*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0770*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x008fca0007ffe0ff */
/*0780*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0790*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*07a0*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*07b0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x010fca00078e020a */
/*07c0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*07d0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*07f0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x010fca00078e020b */
/*0800*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0810*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0830*/ IADD3 R13, R10, R13, RZ ; /* 0x0000000d0a0d7210 */
/* 0x010fca0007ffe0ff */
/*0840*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x000fe8000c10190c */
/*0850*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000528000c1e1900 */
/*0860*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008722000c1e1900 */
/*0870*/ IADD3 R9, P3, R4, 0x20, RZ ; /* 0x0000002004097810 */
/* 0x001fe20007f7e0ff */
/*0880*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0890*/ IADD3 R11, P2, R2, 0x20, RZ ; /* 0x00000020020b7810 */
/* 0x002fc40007f5e0ff */
/*08a0*/ IADD3 R14, P1, R6, 0x20, RZ ; /* 0x00000020060e7810 */
/* 0x000fe40007f3e0ff */
/*08b0*/ IADD3.X R12, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0c7210 */
/* 0x000fe200017fe4ff */
/*08c0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x004fe200078e000b */
/*08d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*08e0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x008fe200008e0607 */
/*08f0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0900*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000e */
/*0910*/ MOV R3, R12 ; /* 0x0000000c00037202 */
/* 0x000fe20000000f00 */
/*0920*/ IMAD.IADD R15, R10, 0x1, R15 ; /* 0x000000010a0f7824 */
/* 0x010fe400078e020f */
/*0930*/ IMAD.X R10, RZ, RZ, R5, P3 ; /* 0x000000ffff0a7224 */
/* 0x000fc600018e0605 */
/*0940*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0001e4000c10190c */
/*0950*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0009 */
/*0960*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fe40000000f00 */
/*0970*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x004fca00078e020a */
/*09c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c10190c */
/*09d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x004fca00078e020b */
/*0a00*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0a10*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R12, P0, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f1e0ff */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc40007ffe0ff */
/*0a50*/ IADD3 R13, R10, R13, RZ ; /* 0x0000000d0a0d7210 */
/* 0x004fca0007ffe0ff */
/*0a60*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0a70*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0a80*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x0006a2000c1e1900 */
/*0a90*/ IMAD.X R11, RZ, RZ, R3, P0 ; /* 0x000000ffff0b7224 */
/* 0x001fe200000e0603 */
/*0aa0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0ab0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0ac0*/ IADD3 R9, P2, R4, 0x10, RZ ; /* 0x0000001004097810 */
/* 0x000fc40007f5e0ff */
/*0ad0*/ IADD3 R14, P1, R6, 0x10, RZ ; /* 0x00000010060e7810 */
/* 0x000fe20007f3e0ff */
/*0ae0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*0af0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*0b00*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x008fe20000ffe4ff */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0b20*/ IMAD.IADD R15, R10, 0x1, R15 ; /* 0x000000010a0f7824 */
/* 0x004fe400078e020f */
/*0b30*/ IMAD.X R10, RZ, RZ, R5, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fc600010e0605 */
/*0b40*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0001e4000c10190c */
/*0b50*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0009 */
/*0b60*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fe20000000f00 */
/*0b70*/ @P0 BRA 0x990 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*0b80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0b90*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ba0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0bb0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0bc0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0bd0*/ ULDC.64 UR10, c[0x0][0x160] ; /* 0x00005800000a7ab9 */
/* 0x000fe40000000a00 */
/*0be0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0bf0*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fc4000f8e0208 */
/*0c00*/ UIMAD.WIDE UR4, UR4, UR5, UR10 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e020a */
/*0c10*/ IMAD.U32 R2, RZ, RZ, UR8 ; /* 0x00000008ff027e24 */
/* 0x000fe2000f8e00ff */
/*0c20*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*0c30*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe4000f8e00ff */
/*0c40*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fc8000f8e00ff */
/*0c50*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R2, [R2.64] ; /* 0x0000000c02027981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ IMAD.U32 R6, RZ, RZ, UR6 ; /* 0x00000006ff067e24 */
/* 0x001fe2000f8e00ff */
/*0ca0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*0cb0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe4000ff1e03f */
/*0cc0*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe4000ff3e03f */
/*0cd0*/ UIADD3 UR4, UP2, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff5e03f */
/*0ce0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0cf0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fc40008ffe43f */
/*0d00*/ UIADD3.X UR5, URZ, UR5, URZ, UP2, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200097fe43f */
/*0d10*/ IMAD.IADD R9, R2, 0x1, R5 ; /* 0x0000000102097824 */
/* 0x004fca00078e0205 */
/*0d20*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190c */
/*0d30*/ @P0 BRA 0xc10 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "device_launch_parameters.h"
#include <cuda_runtime.h>
#include<stdlib.h>
#include<iostream>
using namespace std;
#define SIZE 1024
//call from host func (like order to gpu)
__global__ void vectoradd(int* a, int* b, int* c,int n) {
int i = threadIdx.x;//to distinct thread
for (i = 0; i < n; i++)c[i] = a[i] + b[i];
//do sum of each thread
}
int main() {
int* a, * b, * c;//host variable
int* d_a, * d_b, * d_c;//device variable
//malloc to host memory
a = (int*)malloc(SIZE * sizeof(int));
b = (int*)malloc(SIZE * sizeof(int));
c = (int*)malloc(SIZE * sizeof(int));
//malloc to device memory
cudaMalloc(&d_a, SIZE * sizeof(int));
cudaMalloc(&d_b, SIZE * sizeof(int));
cudaMalloc(&d_c, SIZE * sizeof(int));
//initialize variables
for (int i = 0; i < SIZE; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
}
//memcopy to device variables
cudaMemcpy(d_a, a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, SIZE * sizeof(int), cudaMemcpyHostToDevice);
//call vectoradd func using 1 block, 1024 threads
vectoradd <<< 1, SIZE >>> (d_a, d_b, d_c, SIZE);
//memcopy to host, save device to host
cudaMemcpy(a, d_a, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(b, d_b, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(c, d_c, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
//print result of c variable
for (int i = 0; i < SIZE; i++)
cout << "c[" << i << "]=" << c[i] << "\n";
//memory free to host
free(a);
free(b);
free(c);
//memory free to device
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_0003a41e_00000000-6_sum_example.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectoraddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i
.globl _Z9vectoraddPiS_S_i
.type _Z9vectoraddPiS_S_i, @function
_Z9vectoraddPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9vectoraddPiS_S_i, .-_Z9vectoraddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c["
.LC1:
.string "]="
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r14
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %r15
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%r14,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L12
movl $1, %ecx
movl $4096, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $4096, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r12
.L14:
movl $2, %edx
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r15,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $1024, %rbx
jne .L14
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9vectoraddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectoraddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "device_launch_parameters.h"
#include <cuda_runtime.h>
#include<stdlib.h>
#include<iostream>
using namespace std;
#define SIZE 1024
//call from host func (like order to gpu)
__global__ void vectoradd(int* a, int* b, int* c,int n) {
int i = threadIdx.x;//to distinct thread
for (i = 0; i < n; i++)c[i] = a[i] + b[i];
//do sum of each thread
}
int main() {
int* a, * b, * c;//host variable
int* d_a, * d_b, * d_c;//device variable
//malloc to host memory
a = (int*)malloc(SIZE * sizeof(int));
b = (int*)malloc(SIZE * sizeof(int));
c = (int*)malloc(SIZE * sizeof(int));
//malloc to device memory
cudaMalloc(&d_a, SIZE * sizeof(int));
cudaMalloc(&d_b, SIZE * sizeof(int));
cudaMalloc(&d_c, SIZE * sizeof(int));
//initialize variables
for (int i = 0; i < SIZE; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
}
//memcopy to device variables
cudaMemcpy(d_a, a, SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, SIZE * sizeof(int), cudaMemcpyHostToDevice);
//call vectoradd func using 1 block, 1024 threads
vectoradd <<< 1, SIZE >>> (d_a, d_b, d_c, SIZE);
//memcopy to host, save device to host
cudaMemcpy(a, d_a, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(b, d_b, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(c, d_c, SIZE * sizeof(int), cudaMemcpyDeviceToHost);
//print result of c variable
for (int i = 0; i < SIZE; i++)
cout << "c[" << i << "]=" << c[i] << "\n";
//memory free to host
free(a);
free(b);
free(c);
//memory free to device
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<iostream>
using namespace std;
#define SIZE 1024
//call from host func (like order to gpu)
__global__ void vectoradd(int* a, int* b, int* c,int n) {
int i = threadIdx.x;//to distinct thread
for (i = 0; i < n; i++)c[i] = a[i] + b[i];
//do sum of each thread
}
int main() {
int* a, * b, * c;//host variable
int* d_a, * d_b, * d_c;//device variable
//malloc to host memory
a = (int*)malloc(SIZE * sizeof(int));
b = (int*)malloc(SIZE * sizeof(int));
c = (int*)malloc(SIZE * sizeof(int));
//malloc to device memory
hipMalloc(&d_a, SIZE * sizeof(int));
hipMalloc(&d_b, SIZE * sizeof(int));
hipMalloc(&d_c, SIZE * sizeof(int));
//initialize variables
for (int i = 0; i < SIZE; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
}
//memcopy to device variables
hipMemcpy(d_a, a, SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, SIZE * sizeof(int), hipMemcpyHostToDevice);
//call vectoradd func using 1 block, 1024 threads
vectoradd <<< 1, SIZE >>> (d_a, d_b, d_c, SIZE);
//memcopy to host, save device to host
hipMemcpy(a, d_a, SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(b, d_b, SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(c, d_c, SIZE * sizeof(int), hipMemcpyDeviceToHost);
//print result of c variable
for (int i = 0; i < SIZE; i++)
cout << "c[" << i << "]=" << c[i] << "\n";
//memory free to host
free(a);
free(b);
free(c);
//memory free to device
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<iostream>
using namespace std;
#define SIZE 1024
//call from host func (like order to gpu)
__global__ void vectoradd(int* a, int* b, int* c,int n) {
int i = threadIdx.x;//to distinct thread
for (i = 0; i < n; i++)c[i] = a[i] + b[i];
//do sum of each thread
}
int main() {
int* a, * b, * c;//host variable
int* d_a, * d_b, * d_c;//device variable
//malloc to host memory
a = (int*)malloc(SIZE * sizeof(int));
b = (int*)malloc(SIZE * sizeof(int));
c = (int*)malloc(SIZE * sizeof(int));
//malloc to device memory
hipMalloc(&d_a, SIZE * sizeof(int));
hipMalloc(&d_b, SIZE * sizeof(int));
hipMalloc(&d_c, SIZE * sizeof(int));
//initialize variables
for (int i = 0; i < SIZE; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
}
//memcopy to device variables
hipMemcpy(d_a, a, SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, SIZE * sizeof(int), hipMemcpyHostToDevice);
//call vectoradd func using 1 block, 1024 threads
vectoradd <<< 1, SIZE >>> (d_a, d_b, d_c, SIZE);
//memcopy to host, save device to host
hipMemcpy(a, d_a, SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(b, d_b, SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(c, d_c, SIZE * sizeof(int), hipMemcpyDeviceToHost);
//print result of c variable
for (int i = 0; i < SIZE; i++)
cout << "c[" << i << "]=" << c[i] << "\n";
//memory free to host
free(a);
free(b);
free(c);
//memory free to device
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectoraddPiS_S_i
.globl _Z9vectoraddPiS_S_i
.p2align 8
.type _Z9vectoraddPiS_S_i,@function
_Z9vectoraddPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_add_i32 s2, s2, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectoraddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectoraddPiS_S_i, .Lfunc_end0-_Z9vectoraddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectoraddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9vectoraddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<iostream>
using namespace std;
#define SIZE 1024
//call from host func (like order to gpu)
__global__ void vectoradd(int* a, int* b, int* c,int n) {
int i = threadIdx.x;//to distinct thread
for (i = 0; i < n; i++)c[i] = a[i] + b[i];
//do sum of each thread
}
int main() {
int* a, * b, * c;//host variable
int* d_a, * d_b, * d_c;//device variable
//malloc to host memory
a = (int*)malloc(SIZE * sizeof(int));
b = (int*)malloc(SIZE * sizeof(int));
c = (int*)malloc(SIZE * sizeof(int));
//malloc to device memory
hipMalloc(&d_a, SIZE * sizeof(int));
hipMalloc(&d_b, SIZE * sizeof(int));
hipMalloc(&d_c, SIZE * sizeof(int));
//initialize variables
for (int i = 0; i < SIZE; i++) {
a[i] = rand() % 1000;
b[i] = rand() % 1000;
}
//memcopy to device variables
hipMemcpy(d_a, a, SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, SIZE * sizeof(int), hipMemcpyHostToDevice);
//call vectoradd func using 1 block, 1024 threads
vectoradd <<< 1, SIZE >>> (d_a, d_b, d_c, SIZE);
//memcopy to host, save device to host
hipMemcpy(a, d_a, SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(b, d_b, SIZE * sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(c, d_c, SIZE * sizeof(int), hipMemcpyDeviceToHost);
//print result of c variable
for (int i = 0; i < SIZE; i++)
cout << "c[" << i << "]=" << c[i] << "\n";
//memory free to host
free(a);
free(b);
free(c);
//memory free to device
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "sum_example.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__vectoraddPiS_S_i # -- Begin function _Z24__device_stub__vectoraddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__vectoraddPiS_S_i,@function
_Z24__device_stub__vectoraddPiS_S_i: # @_Z24__device_stub__vectoraddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectoraddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectoraddPiS_S_i, .Lfunc_end0-_Z24__device_stub__vectoraddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9vectoraddPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r15,%r12,4), %esi
movq %r13, %rdi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectoraddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectoraddPiS_S_i,@object # @_Z9vectoraddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9vectoraddPiS_S_i
.p2align 3, 0x0
_Z9vectoraddPiS_S_i:
.quad _Z24__device_stub__vectoraddPiS_S_i
.size _Z9vectoraddPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c["
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "]="
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vectoraddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectoraddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectoraddPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9vectoraddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xb80 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R8, -R0, c[0x0][0x178], RZ ; /* 0x00005e0000087a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*00d0*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fd400078e00ff */
/*0130*/ @!P0 BRA 0x990 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x670 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x004fca00078e020a */
/*01b0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*01c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x004fca00078e020b */
/*01f0*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0200*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0220*/ IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d7824 */
/* 0x004fca00078e020d */
/*0230*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x008fca0007ffe0ff */
/*0270*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0280*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*0290*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*02a0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x010fca00078e020a */
/*02b0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*02c0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*02e0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x010fca00078e020b */
/*02f0*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0300*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0320*/ IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d7824 */
/* 0x010fca00078e020d */
/*0330*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x0005e8000c10190c */
/*0340*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0350*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0360*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x010fca0007ffe0ff */
/*0370*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0007e8000c10190c */
/*0380*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200c02097981 */
/* 0x001f28000c1e1900 */
/*0390*/ LDG.E R10, [R6.64+0x20] ; /* 0x0000200c060a7981 */
/* 0x000f24000c1e1900 */
/*03a0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x010fca00078e020a */
/*03b0*/ STG.E [R4.64+0x20], R9 ; /* 0x0000200904007986 */
/* 0x0001e8000c10190c */
/*03c0*/ LDG.E R10, [R2.64+0x24] ; /* 0x0000240c020a7981 */
/* 0x000f28000c1e1900 */
/*03d0*/ LDG.E R11, [R6.64+0x24] ; /* 0x0000240c060b7981 */
/* 0x002f24000c1e1900 */
/*03e0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x010fca00078e020b */
/*03f0*/ STG.E [R4.64+0x24], R11 ; /* 0x0000240b04007986 */
/* 0x0003e8000c10190c */
/*0400*/ LDG.E R10, [R2.64+0x28] ; /* 0x0000280c020a7981 */
/* 0x000f28000c1e1900 */
/*0410*/ LDG.E R13, [R6.64+0x28] ; /* 0x0000280c060d7981 */
/* 0x004f24000c1e1900 */
/*0420*/ IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d7824 */
/* 0x010fca00078e020d */
/*0430*/ STG.E [R4.64+0x28], R13 ; /* 0x0000280d04007986 */
/* 0x0005e8000c10190c */
/*0440*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c0c020a7981 */
/* 0x000f28000c1e1900 */
/*0450*/ LDG.E R15, [R6.64+0x2c] ; /* 0x00002c0c060f7981 */
/* 0x008f24000c1e1900 */
/*0460*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x010fca0007ffe0ff */
/*0470*/ STG.E [R4.64+0x2c], R15 ; /* 0x00002c0f04007986 */
/* 0x0007e8000c10190c */
/*0480*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300c02097981 */
/* 0x001f28000c1e1900 */
/*0490*/ LDG.E R10, [R6.64+0x30] ; /* 0x0000300c060a7981 */
/* 0x000f24000c1e1900 */
/*04a0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x010fca00078e020a */
/*04b0*/ STG.E [R4.64+0x30], R9 ; /* 0x0000300904007986 */
/* 0x000fe8000c10190c */
/*04c0*/ LDG.E R10, [R2.64+0x34] ; /* 0x0000340c020a7981 */
/* 0x000f28000c1e1900 */
/*04d0*/ LDG.E R11, [R6.64+0x34] ; /* 0x0000340c060b7981 */
/* 0x002f24000c1e1900 */
/*04e0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x010fca00078e020b */
/*04f0*/ STG.E [R4.64+0x34], R11 ; /* 0x0000340b04007986 */
/* 0x0001e8000c10190c */
/*0500*/ LDG.E R10, [R2.64+0x38] ; /* 0x0000380c020a7981 */
/* 0x000f28000c1e1900 */
/*0510*/ LDG.E R13, [R6.64+0x38] ; /* 0x0000380c060d7981 */
/* 0x004f22000c1e1900 */
/*0520*/ IADD3 R12, P1, R2, 0x40, RZ ; /* 0x00000040020c7810 */
/* 0x000fe40007f3e0ff */
/*0530*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d7824 */
/* 0x010fca00078e020d */
/*0550*/ STG.E [R4.64+0x38], R13 ; /* 0x0000380d04007986 */
/* 0x000fe8000c10190c */
/*0560*/ LDG.E R10, [R2.64+0x3c] ; /* 0x00003c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0570*/ LDG.E R15, [R6.64+0x3c] ; /* 0x00003c0c060f7981 */
/* 0x0086a2000c1e1900 */
/*0580*/ IMAD.X R11, RZ, RZ, R3, P1 ; /* 0x000000ffff0b7224 */
/* 0x001fe200008e0603 */
/*0590*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*05a0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*05b0*/ IADD3 R9, P3, R4, 0x40, RZ ; /* 0x0000004004097810 */
/* 0x000fc40007f7e0ff */
/*05c0*/ IADD3 R14, P2, R6, 0x40, RZ ; /* 0x00000040060e7810 */
/* 0x000fe20007f5e0ff */
/*05d0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe400078e000c */
/*05e0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000b */
/*05f0*/ MOV R6, R14 ; /* 0x0000000e00067202 */
/* 0x008fe20000000f00 */
/*0600*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e0607 */
/*0610*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x004fe40007ffe0ff */
/*0620*/ IADD3.X R10, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff0a7210 */
/* 0x000fc60001ffe4ff */
/*0630*/ STG.E [R4.64+0x3c], R15 ; /* 0x00003c0f04007986 */
/* 0x0001e4000c10190c */
/*0640*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0009 */
/*0650*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*0660*/ @P1 BRA 0x180 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x970 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ IADD3 R9, R9, R10, RZ ; /* 0x0000000a09097210 */
/* 0x004fca0007ffe0ff */
/*06c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e8000c10190c */
/*06d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x004fca00078e020b */
/*0700*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c10190c */
/*0710*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0720*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea4000c1e1900 */
/*0730*/ IMAD.IADD R13, R10, 0x1, R13 ; /* 0x000000010a0d7824 */
/* 0x004fca00078e020d */
/*0740*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x0005e8000c10190c */
/*0750*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x000ee8000c1e1900 */
/*0760*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x000ee4000c1e1900 */
/*0770*/ IADD3 R15, R10, R15, RZ ; /* 0x0000000f0a0f7210 */
/* 0x008fca0007ffe0ff */
/*0780*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0007e8000c10190c */
/*0790*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100c02097981 */
/* 0x001f28000c1e1900 */
/*07a0*/ LDG.E R10, [R6.64+0x10] ; /* 0x0000100c060a7981 */
/* 0x000f24000c1e1900 */
/*07b0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x010fca00078e020a */
/*07c0*/ STG.E [R4.64+0x10], R9 ; /* 0x0000100904007986 */
/* 0x0001e8000c10190c */
/*07d0*/ LDG.E R10, [R2.64+0x14] ; /* 0x0000140c020a7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R11, [R6.64+0x14] ; /* 0x0000140c060b7981 */
/* 0x002f24000c1e1900 */
/*07f0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x010fca00078e020b */
/*0800*/ STG.E [R4.64+0x14], R11 ; /* 0x0000140b04007986 */
/* 0x0003e8000c10190c */
/*0810*/ LDG.E R10, [R2.64+0x18] ; /* 0x0000180c020a7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R13, [R6.64+0x18] ; /* 0x0000180c060d7981 */
/* 0x004f24000c1e1900 */
/*0830*/ IADD3 R13, R10, R13, RZ ; /* 0x0000000d0a0d7210 */
/* 0x010fca0007ffe0ff */
/*0840*/ STG.E [R4.64+0x18], R13 ; /* 0x0000180d04007986 */
/* 0x000fe8000c10190c */
/*0850*/ LDG.E R10, [R2.64+0x1c] ; /* 0x00001c0c020a7981 */
/* 0x000528000c1e1900 */
/*0860*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c0c060f7981 */
/* 0x008722000c1e1900 */
/*0870*/ IADD3 R9, P3, R4, 0x20, RZ ; /* 0x0000002004097810 */
/* 0x001fe20007f7e0ff */
/*0880*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0890*/ IADD3 R11, P2, R2, 0x20, RZ ; /* 0x00000020020b7810 */
/* 0x002fc40007f5e0ff */
/*08a0*/ IADD3 R14, P1, R6, 0x20, RZ ; /* 0x00000020060e7810 */
/* 0x000fe40007f3e0ff */
/*08b0*/ IADD3.X R12, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0c7210 */
/* 0x000fe200017fe4ff */
/*08c0*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x004fe200078e000b */
/*08d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*08e0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x008fe200008e0607 */
/*08f0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0900*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000e */
/*0910*/ MOV R3, R12 ; /* 0x0000000c00037202 */
/* 0x000fe20000000f00 */
/*0920*/ IMAD.IADD R15, R10, 0x1, R15 ; /* 0x000000010a0f7824 */
/* 0x010fe400078e020f */
/*0930*/ IMAD.X R10, RZ, RZ, R5, P3 ; /* 0x000000ffff0a7224 */
/* 0x000fc600018e0605 */
/*0940*/ STG.E [R4.64+0x1c], R15 ; /* 0x00001c0f04007986 */
/* 0x0001e4000c10190c */
/*0950*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0009 */
/*0960*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fe40000000f00 */
/*0970*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0990*/ LDG.E R9, [R2.64] ; /* 0x0000000c02097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ IMAD.IADD R9, R9, 0x1, R10 ; /* 0x0000000109097824 */
/* 0x004fca00078e020a */
/*09c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c10190c */
/*09d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040c020a7981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ IMAD.IADD R11, R10, 0x1, R11 ; /* 0x000000010a0b7824 */
/* 0x004fca00078e020b */
/*0a00*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0001e8000c10190c */
/*0a10*/ LDG.E R10, [R2.64+0x8] ; /* 0x0000080c020a7981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R13, [R6.64+0x8] ; /* 0x0000080c060d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R12, P0, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f1e0ff */
/*0a40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc40007ffe0ff */
/*0a50*/ IADD3 R13, R10, R13, RZ ; /* 0x0000000d0a0d7210 */
/* 0x004fca0007ffe0ff */
/*0a60*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c10190c */
/*0a70*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c0c020a7981 */
/* 0x0002a8000c1e1900 */
/*0a80*/ LDG.E R15, [R6.64+0xc] ; /* 0x00000c0c060f7981 */
/* 0x0006a2000c1e1900 */
/*0a90*/ IMAD.X R11, RZ, RZ, R3, P0 ; /* 0x000000ffff0b7224 */
/* 0x001fe200000e0603 */
/*0aa0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0ab0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0ac0*/ IADD3 R9, P2, R4, 0x10, RZ ; /* 0x0000001004097810 */
/* 0x000fc40007f5e0ff */
/*0ad0*/ IADD3 R14, P1, R6, 0x10, RZ ; /* 0x00000010060e7810 */
/* 0x000fe20007f3e0ff */
/*0ae0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000c */
/*0af0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*0b00*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x008fe20000ffe4ff */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000e */
/*0b20*/ IMAD.IADD R15, R10, 0x1, R15 ; /* 0x000000010a0f7824 */
/* 0x004fe400078e020f */
/*0b30*/ IMAD.X R10, RZ, RZ, R5, P2 ; /* 0x000000ffff0a7224 */
/* 0x000fc600010e0605 */
/*0b40*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x0001e4000c10190c */
/*0b50*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0009 */
/*0b60*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fe20000000f00 */
/*0b70*/ @P0 BRA 0x990 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*0b80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0b90*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ba0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0bb0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0bc0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0bd0*/ ULDC.64 UR10, c[0x0][0x160] ; /* 0x00005800000a7ab9 */
/* 0x000fe40000000a00 */
/*0be0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0bf0*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fc4000f8e0208 */
/*0c00*/ UIMAD.WIDE UR4, UR4, UR5, UR10 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e020a */
/*0c10*/ IMAD.U32 R2, RZ, RZ, UR8 ; /* 0x00000008ff027e24 */
/* 0x000fe2000f8e00ff */
/*0c20*/ MOV R4, UR4 ; /* 0x0000000400047c02 */
/* 0x000fe20008000f00 */
/*0c30*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe4000f8e00ff */
/*0c40*/ IMAD.U32 R3, RZ, RZ, UR9 ; /* 0x00000009ff037e24 */
/* 0x000fc8000f8e00ff */
/*0c50*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R2, [R2.64] ; /* 0x0000000c02027981 */
/* 0x000ea2000c1e1900 */
/*0c70*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0c80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0c90*/ IMAD.U32 R6, RZ, RZ, UR6 ; /* 0x00000006ff067e24 */
/* 0x001fe2000f8e00ff */
/*0ca0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*0cb0*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe4000ff1e03f */
/*0cc0*/ UIADD3 UR8, UP1, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe4000ff3e03f */
/*0cd0*/ UIADD3 UR4, UP2, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000ff5e03f */
/*0ce0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0cf0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fc40008ffe43f */
/*0d00*/ UIADD3.X UR5, URZ, UR5, URZ, UP2, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200097fe43f */
/*0d10*/ IMAD.IADD R9, R2, 0x1, R5 ; /* 0x0000000102097824 */
/* 0x004fca00078e0205 */
/*0d20*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c10190c */
/*0d30*/ @P0 BRA 0xc10 ; /* 0xfffffed000000947 */
/* 0x000fea000383ffff */
/*0d40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectoraddPiS_S_i
.globl _Z9vectoraddPiS_S_i
.p2align 8
.type _Z9vectoraddPiS_S_i,@function
_Z9vectoraddPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_add_i32 s2, s2, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectoraddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectoraddPiS_S_i, .Lfunc_end0-_Z9vectoraddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectoraddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9vectoraddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003a41e_00000000-6_sum_example.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectoraddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i
.globl _Z9vectoraddPiS_S_i
.type _Z9vectoraddPiS_S_i, @function
_Z9vectoraddPiS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9vectoraddPiS_S_i, .-_Z9vectoraddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c["
.LC1:
.string "]="
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r14
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %r15
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %ebx
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, (%r14,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L12
movl $1, %ecx
movl $4096, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4096, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $4096, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r12
.L14:
movl $2, %edx
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r15,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $1024, %rbx
jne .L14
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9vectoraddPiS_S_iPiS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9vectoraddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectoraddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum_example.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__vectoraddPiS_S_i # -- Begin function _Z24__device_stub__vectoraddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__vectoraddPiS_S_i,@function
_Z24__device_stub__vectoraddPiS_S_i: # @_Z24__device_stub__vectoraddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectoraddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectoraddPiS_S_i, .Lfunc_end0-_Z24__device_stub__vectoraddPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9vectoraddPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %r13
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r15,%r12,4), %esi
movq %r13, %rdi
callq _ZNSolsEi
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectoraddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectoraddPiS_S_i,@object # @_Z9vectoraddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9vectoraddPiS_S_i
.p2align 3, 0x0
_Z9vectoraddPiS_S_i:
.quad _Z24__device_stub__vectoraddPiS_S_i
.size _Z9vectoraddPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c["
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "]="
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vectoraddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectoraddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectoraddPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__ void random_matrix(int n)
{
} | code for sm_80
Function : random_matrix
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void random_matrix(int n)
{
} | .file "tmpxft_0010a30b_00000000-6_random_matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13random_matrixii
.type _Z32__device_stub__Z13random_matrixii, @function
_Z32__device_stub__Z13random_matrixii:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq random_matrix(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z13random_matrixii, .-_Z32__device_stub__Z13random_matrixii
.globl random_matrix
.type random_matrix, @function
random_matrix:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13random_matrixii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size random_matrix, .-random_matrix
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "random_matrix"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq random_matrix(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void random_matrix(int n)
{
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void random_matrix(int n)
{
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void random_matrix(int n)
{
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected random_matrix
.globl random_matrix
.p2align 8
.type random_matrix,@function
random_matrix:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel random_matrix
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 4
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size random_matrix, .Lfunc_end0-random_matrix
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 4
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: random_matrix
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: random_matrix.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void random_matrix(int n)
{
} | .text
.file "random_matrix.hip"
.globl __device_stub__random_matrix # -- Begin function __device_stub__random_matrix
.p2align 4, 0x90
.type __device_stub__random_matrix,@function
__device_stub__random_matrix: # @__device_stub__random_matrix
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $random_matrix, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__random_matrix, .Lfunc_end0-__device_stub__random_matrix
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $random_matrix, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type random_matrix,@object # @random_matrix
.section .rodata,"a",@progbits
.globl random_matrix
.p2align 3, 0x0
random_matrix:
.quad __device_stub__random_matrix
.size random_matrix, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "random_matrix"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__random_matrix
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym random_matrix
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : random_matrix
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected random_matrix
.globl random_matrix
.p2align 8
.type random_matrix,@function
random_matrix:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel random_matrix
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 4
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size random_matrix, .Lfunc_end0-random_matrix
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 4
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: random_matrix
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: random_matrix.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010a30b_00000000-6_random_matrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13random_matrixii
.type _Z32__device_stub__Z13random_matrixii, @function
_Z32__device_stub__Z13random_matrixii:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq random_matrix(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z13random_matrixii, .-_Z32__device_stub__Z13random_matrixii
.globl random_matrix
.type random_matrix, @function
random_matrix:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13random_matrixii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size random_matrix, .-random_matrix
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "random_matrix"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq random_matrix(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "random_matrix.hip"
.globl __device_stub__random_matrix # -- Begin function __device_stub__random_matrix
.p2align 4, 0x90
.type __device_stub__random_matrix,@function
__device_stub__random_matrix: # @__device_stub__random_matrix
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $random_matrix, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__random_matrix, .Lfunc_end0-__device_stub__random_matrix
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $random_matrix, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type random_matrix,@object # @random_matrix
.section .rodata,"a",@progbits
.globl random_matrix
.p2align 3, 0x0
random_matrix:
.quad __device_stub__random_matrix
.size random_matrix, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "random_matrix"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__random_matrix
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym random_matrix
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kShuffleColumns(float* source, float* target, float* indices, int width, int height){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float temp1, temp2;
unsigned int column, row, pos1, pos2;
for (unsigned int i = idx; i < height * ((width+1) / 2); i += numThreads) {
column = 2 * (i / height);
row = i % height;
if (column + 1 >= width) {
pos1 = height * (int)indices[column] + row;
target[pos1] = source[pos1];
} else {
pos1 = height * (int)indices[column] + row;
pos2 = height * (int)indices[column + 1] + row;
temp1 = source[pos1];
temp2 = source[pos2];
target[pos2] = temp1;
target[pos1] = temp2;
}
}
} | code for sm_80
Function : _Z15kShuffleColumnsPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fc8000fffe03f */
/*0060*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*0070*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc80008011404 */
/*0080*/ UIMAD UR4, UR4, UR7, URZ ; /* 0x00000007040472a4 */
/* 0x000fe2000f8e023f */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ I2F.U32.RP R6, c[0x0][0x17c] ; /* 0x00005f0000067b06 */
/* 0x000e220000209000 */
/*00d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05070 */
/*00e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R4, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff047a12 */
/* 0x000fca00078e33ff */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0150*/ IMAD R5, R5, c[0x0][0x17c], RZ ; /* 0x00005f0005057a24 */
/* 0x000fca00078e02ff */
/*0160*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fcc00078e0002 */
/*0170*/ IMAD.HI.U32 R3, R5, R0, RZ ; /* 0x0000000005037227 */
/* 0x000fe200078e00ff */
/*0180*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a03 */
/*01a0*/ IMAD R2, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007027a24 */
/* 0x000fca00078e0200 */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fda0003f26070 */
/*01c0*/ @P1 IADD3 R2, R2, -c[0x0][0x17c], RZ ; /* 0x80005f0002021a10 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P2, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fda0003f46070 */
/*01f0*/ @P2 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103032810 */
/* 0x000fc80007ffe0ff */
/*0200*/ SEL R3, R4, R3, !P0 ; /* 0x0000000304037207 */
/* 0x000fca0004000000 */
/*0210*/ IMAD.SHL.U32 R2, R3, 0x2, RZ ; /* 0x0000000203027824 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE.U32 R6, R2, R11, c[0x0][0x170] ; /* 0x00005c0002067625 */
/* 0x000fca00078e000b */
/*0230*/ LDG.E R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fe40007ffe1ff */
/*0250*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc60007ffe0ff */
/*0260*/ IMAD R9, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003097a24 */
/* 0x000fe200078e0200 */
/*0270*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fe20003f26070 */
/*0280*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x004e24000020f100 */
/*0290*/ IMAD R2, R8, c[0x0][0x17c], R9 ; /* 0x00005f0008027a24 */
/* 0x001fc800078e0209 */
/*02a0*/ IMAD.WIDE.U32 R12, R2, R11, c[0x0][0x160] ; /* 0x00005800020c7625 */
/* 0x000fcc00078e000b */
/*02b0*/ @P1 LDG.E R17, [R12.64] ; /* 0x000000060c111981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R2, R2, R11, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e000b */
/*02d0*/ @P1 STG.E [R2.64], R17 ; /* 0x0000001102001986 */
/* 0x0041e8000c101906 */
/*02e0*/ @!P1 LDG.E R6, [R6.64+0x4] ; /* 0x0000040606069981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ @!P1 LDG.E R15, [R12.64] ; /* 0x000000060c0f9981 */
/* 0x000ee2000c1e1900 */
/*0300*/ @!P1 F2I.TRUNC.NTZ R8, R6 ; /* 0x0000000600089305 */
/* 0x004e64000020f100 */
/*0310*/ @!P1 IMAD R10, R8, c[0x0][0x17c], R9 ; /* 0x00005f00080a9a24 */
/* 0x002fc800078e0209 */
/*0320*/ @!P1 IMAD.WIDE.U32 R8, R10, R11, c[0x0][0x160] ; /* 0x000058000a089625 */
/* 0x000fcc00078e000b */
/*0330*/ @!P1 LDG.E R9, [R8.64] ; /* 0x0000000608099981 */
/* 0x000ea2000c1e1900 */
/*0340*/ MOV R19, c[0x0][0x0] ; /* 0x0000000000137a02 */
/* 0x000fe20000000f00 */
/*0350*/ @!P1 IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a9625 */
/* 0x000fc800078e000b */
/*0360*/ IMAD R0, R19, c[0x0][0xc], R0 ; /* 0x0000030013007a24 */
/* 0x000fe200078e0200 */
/*0370*/ @!P1 STG.E [R10.64], R15 ; /* 0x0000000f0a009986 */
/* 0x0081e8000c101906 */
/*0380*/ @!P1 STG.E [R2.64], R9 ; /* 0x0000000902009986 */
/* 0x0041e2000c101906 */
/*0390*/ ISETP.GE.U32.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf26070 */
/*03a0*/ @!P1 BRA 0x170 ; /* 0xfffffdc000009947 */
/* 0x001fea000383ffff */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kShuffleColumns(float* source, float* target, float* indices, int width, int height){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float temp1, temp2;
unsigned int column, row, pos1, pos2;
for (unsigned int i = idx; i < height * ((width+1) / 2); i += numThreads) {
column = 2 * (i / height);
row = i % height;
if (column + 1 >= width) {
pos1 = height * (int)indices[column] + row;
target[pos1] = source[pos1];
} else {
pos1 = height * (int)indices[column] + row;
pos2 = height * (int)indices[column + 1] + row;
temp1 = source[pos1];
temp2 = source[pos2];
target[pos2] = temp1;
target[pos1] = temp2;
}
}
} | .file "tmpxft_0006bf3f_00000000-6_kShuffleColumns.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii
.type _Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii, @function
_Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15kShuffleColumnsPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii, .-_Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii
.globl _Z15kShuffleColumnsPfS_S_ii
.type _Z15kShuffleColumnsPfS_S_ii, @function
_Z15kShuffleColumnsPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15kShuffleColumnsPfS_S_ii, .-_Z15kShuffleColumnsPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15kShuffleColumnsPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kShuffleColumnsPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kShuffleColumns(float* source, float* target, float* indices, int width, int height){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float temp1, temp2;
unsigned int column, row, pos1, pos2;
for (unsigned int i = idx; i < height * ((width+1) / 2); i += numThreads) {
column = 2 * (i / height);
row = i % height;
if (column + 1 >= width) {
pos1 = height * (int)indices[column] + row;
target[pos1] = source[pos1];
} else {
pos1 = height * (int)indices[column] + row;
pos2 = height * (int)indices[column + 1] + row;
temp1 = source[pos1];
temp2 = source[pos2];
target[pos2] = temp1;
target[pos1] = temp2;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kShuffleColumns(float* source, float* target, float* indices, int width, int height){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float temp1, temp2;
unsigned int column, row, pos1, pos2;
for (unsigned int i = idx; i < height * ((width+1) / 2); i += numThreads) {
column = 2 * (i / height);
row = i % height;
if (column + 1 >= width) {
pos1 = height * (int)indices[column] + row;
target[pos1] = source[pos1];
} else {
pos1 = height * (int)indices[column] + row;
pos2 = height * (int)indices[column + 1] + row;
temp1 = source[pos1];
temp2 = source[pos2];
target[pos2] = temp1;
target[pos1] = temp2;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kShuffleColumns(float* source, float* target, float* indices, int width, int height){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float temp1, temp2;
unsigned int column, row, pos1, pos2;
for (unsigned int i = idx; i < height * ((width+1) / 2); i += numThreads) {
column = 2 * (i / height);
row = i % height;
if (column + 1 >= width) {
pos1 = height * (int)indices[column] + row;
target[pos1] = source[pos1];
} else {
pos1 = height * (int)indices[column] + row;
pos2 = height * (int)indices[column + 1] + row;
temp1 = source[pos1];
temp2 = source[pos2];
target[pos2] = temp1;
target[pos1] = temp2;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15kShuffleColumnsPfS_S_ii
.globl _Z15kShuffleColumnsPfS_S_ii
.p2align 8
.type _Z15kShuffleColumnsPfS_S_ii,@function
_Z15kShuffleColumnsPfS_S_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s6, 0xffff
s_add_i32 s6, s2, 1
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_lshr_b32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s7
s_ashr_i32 s10, s6, 1
s_mov_b32 s6, exec_lo
s_mul_i32 s10, s10, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_u32_e64 s10, v1
s_cbranch_execz .LBB0_7
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s11, 0, s3
s_load_b32 s13, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_mov_b32_e32 v3, 0
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s13, s12
s_mov_b32 s12, 0
v_mul_lo_u32 v2, s11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_u32_e32 vcc_lo, s10, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s6, v4
v_add_co_ci_u32_e64 v5, s0, s7, v5, s0
s_or_b32 s12, vcc_lo, s12
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v2, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_7
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v0
s_mov_b32 s0, exec_lo
v_mad_u64_u32 v[4:5], null, s11, v2, v[1:2]
v_not_b32_e32 v7, v2
v_add_nc_u32_e32 v8, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[5:6], null, s3, v7, v[1:2]
v_cmp_le_u32_e32 vcc_lo, s3, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
v_dual_cndmask_b32 v4, v4, v5 :: v_dual_add_nc_u32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v4
v_cndmask_b32_e32 v8, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 1, v8
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_or_b32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v4, v8
v_mad_u64_u32 v[4:5], null, s3, v7, v[1:2]
v_cmpx_le_u32_e64 s2, v6
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[4:5]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v2, v[6:7], off
.LBB0_5:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[6:7]
v_add_co_u32 v5, vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_b32 v2, v[5:6], off
v_mov_b32_e32 v5, v7
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v2, v2
v_sub_nc_u32_e32 v2, v2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, s3, v2, v[1:2]
v_mov_b32_e32 v9, v7
v_lshlrev_b64 v[6:7], 2, v[4:5]
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v9, vcc_lo
s_clause 0x1
global_load_b32 v12, v[6:7], off
global_load_b32 v2, v[10:11], off
v_add_co_u32 v6, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v9, vcc_lo
s_waitcnt vmcnt(1)
global_store_b32 v[6:7], v12, off
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15kShuffleColumnsPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15kShuffleColumnsPfS_S_ii, .Lfunc_end0-_Z15kShuffleColumnsPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15kShuffleColumnsPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15kShuffleColumnsPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kShuffleColumns(float* source, float* target, float* indices, int width, int height){
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
float temp1, temp2;
unsigned int column, row, pos1, pos2;
for (unsigned int i = idx; i < height * ((width+1) / 2); i += numThreads) {
column = 2 * (i / height);
row = i % height;
if (column + 1 >= width) {
pos1 = height * (int)indices[column] + row;
target[pos1] = source[pos1];
} else {
pos1 = height * (int)indices[column] + row;
pos2 = height * (int)indices[column + 1] + row;
temp1 = source[pos1];
temp2 = source[pos2];
target[pos2] = temp1;
target[pos1] = temp2;
}
}
} | .text
.file "kShuffleColumns.hip"
.globl _Z30__device_stub__kShuffleColumnsPfS_S_ii # -- Begin function _Z30__device_stub__kShuffleColumnsPfS_S_ii
.p2align 4, 0x90
.type _Z30__device_stub__kShuffleColumnsPfS_S_ii,@function
_Z30__device_stub__kShuffleColumnsPfS_S_ii: # @_Z30__device_stub__kShuffleColumnsPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15kShuffleColumnsPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__kShuffleColumnsPfS_S_ii, .Lfunc_end0-_Z30__device_stub__kShuffleColumnsPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kShuffleColumnsPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15kShuffleColumnsPfS_S_ii,@object # @_Z15kShuffleColumnsPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z15kShuffleColumnsPfS_S_ii
.p2align 3, 0x0
_Z15kShuffleColumnsPfS_S_ii:
.quad _Z30__device_stub__kShuffleColumnsPfS_S_ii
.size _Z15kShuffleColumnsPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15kShuffleColumnsPfS_S_ii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__kShuffleColumnsPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15kShuffleColumnsPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15kShuffleColumnsPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fc8000fffe03f */
/*0060*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fc8000f8f083f */
/*0070*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc80008011404 */
/*0080*/ UIMAD UR4, UR4, UR7, URZ ; /* 0x00000007040472a4 */
/* 0x000fe2000f8e023f */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ I2F.U32.RP R6, c[0x0][0x17c] ; /* 0x00005f0000067b06 */
/* 0x000e220000209000 */
/*00d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f05070 */
/*00e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R4, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff047a12 */
/* 0x000fca00078e33ff */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0150*/ IMAD R5, R5, c[0x0][0x17c], RZ ; /* 0x00005f0005057a24 */
/* 0x000fca00078e02ff */
/*0160*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fcc00078e0002 */
/*0170*/ IMAD.HI.U32 R3, R5, R0, RZ ; /* 0x0000000005037227 */
/* 0x000fe200078e00ff */
/*0180*/ MOV R11, 0x4 ; /* 0x00000004000b7802 */
/* 0x000fc60000000f00 */
/*0190*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a03 */
/*01a0*/ IMAD R2, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007027a24 */
/* 0x000fca00078e0200 */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fda0003f26070 */
/*01c0*/ @P1 IADD3 R2, R2, -c[0x0][0x17c], RZ ; /* 0x80005f0002021a10 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P2, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fda0003f46070 */
/*01f0*/ @P2 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103032810 */
/* 0x000fc80007ffe0ff */
/*0200*/ SEL R3, R4, R3, !P0 ; /* 0x0000000304037207 */
/* 0x000fca0004000000 */
/*0210*/ IMAD.SHL.U32 R2, R3, 0x2, RZ ; /* 0x0000000203027824 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE.U32 R6, R2, R11, c[0x0][0x170] ; /* 0x00005c0002067625 */
/* 0x000fca00078e000b */
/*0230*/ LDG.E R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fe40007ffe1ff */
/*0250*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc60007ffe0ff */
/*0260*/ IMAD R9, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003097a24 */
/* 0x000fe200078e0200 */
/*0270*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fe20003f26070 */
/*0280*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x004e24000020f100 */
/*0290*/ IMAD R2, R8, c[0x0][0x17c], R9 ; /* 0x00005f0008027a24 */
/* 0x001fc800078e0209 */
/*02a0*/ IMAD.WIDE.U32 R12, R2, R11, c[0x0][0x160] ; /* 0x00005800020c7625 */
/* 0x000fcc00078e000b */
/*02b0*/ @P1 LDG.E R17, [R12.64] ; /* 0x000000060c111981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ IMAD.WIDE.U32 R2, R2, R11, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e000b */
/*02d0*/ @P1 STG.E [R2.64], R17 ; /* 0x0000001102001986 */
/* 0x0041e8000c101906 */
/*02e0*/ @!P1 LDG.E R6, [R6.64+0x4] ; /* 0x0000040606069981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ @!P1 LDG.E R15, [R12.64] ; /* 0x000000060c0f9981 */
/* 0x000ee2000c1e1900 */
/*0300*/ @!P1 F2I.TRUNC.NTZ R8, R6 ; /* 0x0000000600089305 */
/* 0x004e64000020f100 */
/*0310*/ @!P1 IMAD R10, R8, c[0x0][0x17c], R9 ; /* 0x00005f00080a9a24 */
/* 0x002fc800078e0209 */
/*0320*/ @!P1 IMAD.WIDE.U32 R8, R10, R11, c[0x0][0x160] ; /* 0x000058000a089625 */
/* 0x000fcc00078e000b */
/*0330*/ @!P1 LDG.E R9, [R8.64] ; /* 0x0000000608099981 */
/* 0x000ea2000c1e1900 */
/*0340*/ MOV R19, c[0x0][0x0] ; /* 0x0000000000137a02 */
/* 0x000fe20000000f00 */
/*0350*/ @!P1 IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a9625 */
/* 0x000fc800078e000b */
/*0360*/ IMAD R0, R19, c[0x0][0xc], R0 ; /* 0x0000030013007a24 */
/* 0x000fe200078e0200 */
/*0370*/ @!P1 STG.E [R10.64], R15 ; /* 0x0000000f0a009986 */
/* 0x0081e8000c101906 */
/*0380*/ @!P1 STG.E [R2.64], R9 ; /* 0x0000000902009986 */
/* 0x0041e2000c101906 */
/*0390*/ ISETP.GE.U32.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf26070 */
/*03a0*/ @!P1 BRA 0x170 ; /* 0xfffffdc000009947 */
/* 0x001fea000383ffff */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15kShuffleColumnsPfS_S_ii
.globl _Z15kShuffleColumnsPfS_S_ii
.p2align 8
.type _Z15kShuffleColumnsPfS_S_ii,@function
_Z15kShuffleColumnsPfS_S_ii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s6, 0xffff
s_add_i32 s6, s2, 1
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_lshr_b32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, s7
s_ashr_i32 s10, s6, 1
s_mov_b32 s6, exec_lo
s_mul_i32 s10, s10, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_u32_e64 s10, v1
s_cbranch_execz .LBB0_7
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s11, 0, s3
s_load_b32 s13, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_mov_b32_e32 v3, 0
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s13, s12
s_mov_b32 s12, 0
v_mul_lo_u32 v2, s11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_u32_e32 vcc_lo, s10, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s6, v4
v_add_co_ci_u32_e64 v5, s0, s7, v5, s0
s_or_b32 s12, vcc_lo, s12
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v2, off
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_7
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v0
s_mov_b32 s0, exec_lo
v_mad_u64_u32 v[4:5], null, s11, v2, v[1:2]
v_not_b32_e32 v7, v2
v_add_nc_u32_e32 v8, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[5:6], null, s3, v7, v[1:2]
v_cmp_le_u32_e32 vcc_lo, s3, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v8, vcc_lo
v_dual_cndmask_b32 v4, v4, v5 :: v_dual_add_nc_u32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v4
v_cndmask_b32_e32 v8, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 1, v8
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_or_b32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v4, v8
v_mad_u64_u32 v[4:5], null, s3, v7, v[1:2]
v_cmpx_le_u32_e64 s2, v6
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[4:5]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v2, v[6:7], off
.LBB0_5:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[6:7]
v_add_co_u32 v5, vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_b32 v2, v[5:6], off
v_mov_b32_e32 v5, v7
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v2, v2
v_sub_nc_u32_e32 v2, v2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, s3, v2, v[1:2]
v_mov_b32_e32 v9, v7
v_lshlrev_b64 v[6:7], 2, v[4:5]
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v9, vcc_lo
s_clause 0x1
global_load_b32 v12, v[6:7], off
global_load_b32 v2, v[10:11], off
v_add_co_u32 v6, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v9, vcc_lo
s_waitcnt vmcnt(1)
global_store_b32 v[6:7], v12, off
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15kShuffleColumnsPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15kShuffleColumnsPfS_S_ii, .Lfunc_end0-_Z15kShuffleColumnsPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15kShuffleColumnsPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15kShuffleColumnsPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006bf3f_00000000-6_kShuffleColumns.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii
.type _Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii, @function
_Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15kShuffleColumnsPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii, .-_Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii
.globl _Z15kShuffleColumnsPfS_S_ii
.type _Z15kShuffleColumnsPfS_S_ii, @function
_Z15kShuffleColumnsPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15kShuffleColumnsPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15kShuffleColumnsPfS_S_ii, .-_Z15kShuffleColumnsPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15kShuffleColumnsPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kShuffleColumnsPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kShuffleColumns.hip"
.globl _Z30__device_stub__kShuffleColumnsPfS_S_ii # -- Begin function _Z30__device_stub__kShuffleColumnsPfS_S_ii
.p2align 4, 0x90
.type _Z30__device_stub__kShuffleColumnsPfS_S_ii,@function
_Z30__device_stub__kShuffleColumnsPfS_S_ii: # @_Z30__device_stub__kShuffleColumnsPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15kShuffleColumnsPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__kShuffleColumnsPfS_S_ii, .Lfunc_end0-_Z30__device_stub__kShuffleColumnsPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kShuffleColumnsPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15kShuffleColumnsPfS_S_ii,@object # @_Z15kShuffleColumnsPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z15kShuffleColumnsPfS_S_ii
.p2align 3, 0x0
_Z15kShuffleColumnsPfS_S_ii:
.quad _Z30__device_stub__kShuffleColumnsPfS_S_ii
.size _Z15kShuffleColumnsPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15kShuffleColumnsPfS_S_ii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__kShuffleColumnsPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15kShuffleColumnsPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<string.h>
#include<random>
#define cudaCheck(x) _cudaCheck(x, #x ,__FILE__, __LINE__)
template<typename T>
void _cudaCheck(T e, const char* func, const char* call, const int line){
if(e != cudaSuccess){
printf("\"%s\" at %d in %s\n\treturned %d\n-> %s\n", func, line, call, (int)e, cudaGetErrorString(e));
exit(EXIT_FAILURE);
}
}
// Number of elements worked by one thread
long nelem;
// Each threads work on nelem-elements in a pair of sz-long vector
__global__ void add_krnl(float *x, float *y, long sz, long nelem) {
// PARAMETER: 0 means adjacent, 1 means cyclical
int pattern = 1;
long i;
long inc = (sz + nelem-1) / nelem;
long start = blockIdx.x*1024 + threadIdx.x;
if (pattern == 0) {
start = start*nelem;
long end = start+nelem;
for(i = start; i < end && i < sz; i++) {
x[i] += y[i];
}
} else {
for (i = start; i < sz; i += inc) {
x[i] += y[i];
}
}
}
long func_add(float *x, float *y, long sz) {
long i;
// CPU Calculation
for (i = 0; i < sz; i++)
x[i] += y[i];
// GPU Calculation
float *dx, *dy;
cudaMalloc((float **) &dx, sz*sizeof(float));
cudaMalloc((float **) &dy, sz*sizeof(float));
cudaMemcpy(dx, x, sz*sizeof(float), cudaMemcpyHostToDevice);
// Timing using cudaEvent
cudaEvent_t start, stop;
float et;
cudaCheck(cudaEventCreate(&start));
cudaCheck(cudaEventCreate(&stop));
// Time event start
cudaCheck(cudaEventRecord(start));
{
long n_threads = (sz + nelem-1) / nelem;
long n_blocks = (n_threads + 1023) / 1024;
add_krnl<<<n_blocks, 1024>>>(dx, dy, sz, nelem);
}
cudaCheck(cudaGetLastError());
// Time event end
cudaCheck(cudaEventRecord(stop));
cudaCheck(cudaEventSynchronize(stop));
cudaCheck(cudaEventElapsedTime(&et, start, stop));
cudaCheck(cudaEventDestroy(start));
cudaCheck(cudaEventDestroy(stop));
printf("\t%0.3f", et);
// Copy data back to d_x and free GPU memory
float * d_x = (float *) malloc(sz * sizeof(float));
cudaMemcpy(d_x, dx, sz*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dx);
cudaFree(dy);
// Compare CPU and GPU output to see if it is within error tolerance
for (i = 0; i < sz; i++) {
if (fabsf(d_x[i] - x[i]) > 1e-5) {
free(d_x);
return 0;
}
}
free(d_x);
return 1;
}
int main(int argc, char **argv) {
float *a, *b;
long j;
long i;
std::random_device rd;
std::mt19937_64 mt(rd());
std::uniform_real_distribution<float> u(0, 1);
// Print title
printf("sz");
for (nelem = 1; nelem < 513; nelem *= 2)
printf("\t%d", nelem);
printf("\n");
for (j = 10; j <= 1000000000; j *= 10) {
a = (float *) malloc(sizeof(float) * j);
b = (float *) malloc(sizeof(float) * j);
// Initialize with random number generator
for (i = 0; i < j; i++) {
a[i] = u(mt);
b[i] = u(mt);
}
printf("%d", j);
for (nelem = 1; nelem < 513; nelem *= 2)
if (!func_add(a, b, j))
printf("failed to add\n");
printf("\n");
free(a);
free(b);
}
return 0;
} | .file "tmpxft_00174cf1_00000000-6_driver.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4146:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4146:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8add_krnlPfS_llPfS_ll
.type _Z31__device_stub__Z8add_krnlPfS_llPfS_ll, @function
_Z31__device_stub__Z8add_krnlPfS_llPfS_ll:
.LFB4168:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8add_krnlPfS_ll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4168:
.size _Z31__device_stub__Z8add_krnlPfS_llPfS_ll, .-_Z31__device_stub__Z8add_krnlPfS_llPfS_ll
.globl _Z8add_krnlPfS_ll
.type _Z8add_krnlPfS_ll, @function
_Z8add_krnlPfS_ll:
.LFB4169:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8add_krnlPfS_llPfS_ll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4169:
.size _Z8add_krnlPfS_ll, .-_Z8add_krnlPfS_ll
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8add_krnlPfS_ll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4171:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8add_krnlPfS_ll(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4171:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z10_cudaCheckI9cudaErrorEvT_PKcS3_i.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\"%s\" at %d in %s\n\treturned %d\n-> %s\n"
.section .text._Z10_cudaCheckI9cudaErrorEvT_PKcS3_i,"axG",@progbits,_Z10_cudaCheckI9cudaErrorEvT_PKcS3_i,comdat
.weak _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i
.type _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i, @function
_Z10_cudaCheckI9cudaErrorEvT_PKcS3_i:
.LFB4483:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L18
ret
.L18:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
movl %ebx, %r9d
movq %r12, %r8
movl %ebp, %ecx
movq %r13, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4483:
.size _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i, .-_Z10_cudaCheckI9cudaErrorEvT_PKcS3_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/kyledpierson/gpu-programming/master/gpu-add/driver.cu"
.section .rodata.str1.1
.LC3:
.string "cudaEventCreate(&start)"
.LC4:
.string "cudaEventCreate(&stop)"
.LC5:
.string "cudaEventRecord(start)"
.LC6:
.string "cudaGetLastError()"
.LC7:
.string "cudaEventRecord(stop)"
.LC8:
.string "cudaEventSynchronize(stop)"
.section .rodata.str1.8
.align 8
.LC9:
.string "cudaEventElapsedTime(&et, start, stop)"
.section .rodata.str1.1
.LC10:
.string "cudaEventDestroy(start)"
.LC11:
.string "cudaEventDestroy(stop)"
.LC12:
.string "\t%0.3f"
.text
.globl _Z8func_addPfS_l
.type _Z8func_addPfS_l, @function
_Z8func_addPfS_l:
.LFB4142:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbx
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
testq %rdx, %rdx
jle .L20
.L21:
movss (%rbx,%rax,4), %xmm0
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq %rax, %rbp
jne .L21
.L20:
leaq 0(,%rbp,4), %r13
movq %rsp, %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $57, %ecx
leaq .LC2(%rip), %r12
movq %r12, %rdx
leaq .LC3(%rip), %rsi
call _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %edi
movl $58, %ecx
movq %r12, %rdx
leaq .LC4(%rip), %rsi
call _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $61, %ecx
movq %r12, %rdx
leaq .LC5(%rip), %rsi
call _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i
movq nelem(%rip), %rcx
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq -1(%rcx,%rbp), %rax
cqto
idivq %rcx
leaq 2046(%rax), %rdx
addq $1023, %rax
cmovns %rax, %rdx
sarq $10, %rdx
movl %edx, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L22:
call cudaGetLastError@PLT
movl %eax, %edi
movl $70, %ecx
leaq .LC2(%rip), %r12
movq %r12, %rdx
leaq .LC6(%rip), %rsi
call _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %edi
movl $73, %ecx
movq %r12, %rdx
leaq .LC7(%rip), %rsi
call _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %edi
movl $74, %ecx
movq %r12, %rdx
leaq .LC8(%rip), %rsi
call _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %edi
movl $75, %ecx
movq %r12, %rdx
leaq .LC9(%rip), %rsi
call _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
movl $76, %ecx
movq %r12, %rdx
leaq .LC10(%rip), %rsi
call _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movl %eax, %edi
movl $77, %ecx
movq %r12, %rdx
leaq .LC11(%rip), %rsi
call _Z10_cudaCheckI9cudaErrorEvT_PKcS3_i
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
movl $2, %ecx
movq %r13, %rdx
movq (%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
testq %rbp, %rbp
jle .L23
movl $0, %eax
movss .LC13(%rip), %xmm2
movsd .LC14(%rip), %xmm1
.L27:
movss (%r12,%rax,4), %xmm0
subss (%rbx,%rax,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L35
addq $1, %rax
cmpq %rax, %rbp
jne .L27
.L23:
movq %r12, %rdi
call free@PLT
movl $1, %eax
.L19:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L36
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq nelem(%rip), %rcx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z8add_krnlPfS_llPfS_ll
jmp .L22
.L35:
movq %r12, %rdi
call free@PLT
movl $0, %eax
jmp .L19
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4142:
.size _Z8func_addPfS_l, .-_Z8func_addPfS_l
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv:
.LFB4840:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1248(%rdi), %r9
movq %rdi, %rcx
movabsq $-5403634167711393303, %r8
.L39:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 1248(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L39
leaq 1240(%rdi), %r8
movabsq $-5403634167711393303, %rsi
.L41:
movq 1248(%rdx), %rax
andq $-2147483648, %rax
movq 1256(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1248(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L41
movq 2488(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 1240(%rdi), %rdx
andl $1, %eax
movabsq $-5403634167711393303, %rcx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 2488(%rdi)
movq $0, 2496(%rdi)
ret
.cfi_endproc
.LFE4840:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
.section .text._ZSt18generate_canonicalIfLm24ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_,"axG",@progbits,_ZSt18generate_canonicalIfLm24ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_,comdat
.weak _ZSt18generate_canonicalIfLm24ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_
.type _ZSt18generate_canonicalIfLm24ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_, @function
_ZSt18generate_canonicalIfLm24ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_:
.LFB4806:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $311, 2496(%rdi)
ja .L52
.L46:
movq 2496(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 2496(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $29, %rdx
movabsq $6148914691236517205, %rcx
andq %rcx, %rdx
xorq %rdx, %rax
movq %rax, %rdx
salq $17, %rdx
movabsq $8202884508482404352, %rcx
andq %rcx, %rdx
xorq %rdx, %rax
movq %rax, %rdx
salq $37, %rdx
movabsq $-2270628950310912, %rcx
andq %rcx, %rdx
xorq %rdx, %rax
movq %rax, %rdx
shrq $43, %rdx
xorq %rdx, %rax
js .L47
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L48:
pxor %xmm1, %xmm1
addss %xmm1, %xmm0
mulss .LC17(%rip), %xmm0
comiss .LC18(%rip), %xmm0
jnb .L53
.L45:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv
jmp .L46
.L47:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L48
.L53:
movss .LC15(%rip), %xmm0
jmp .L45
.cfi_endproc
.LFE4806:
.size _ZSt18generate_canonicalIfLm24ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_, .-_ZSt18generate_canonicalIfLm24ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_
.section .rodata.str1.1
.LC19:
.string "sz"
.LC20:
.string "\t%d"
.LC21:
.string "\n"
.LC22:
.string "%d"
.LC23:
.string "failed to add\n"
.text
.globl main
.type main, @function
main:
.LFB4143:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4143
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $4096, %rsp
.cfi_def_cfa_offset 4152
orq $0, (%rsp)
subq $3432, %rsp
.cfi_def_cfa_offset 7584
movq %fs:40, %rax
movq %rax, 7512(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movl $1634100580, 16(%rsp)
movl $1953264993, 19(%rsp)
movq $7, 8(%rsp)
movb $0, 23(%rsp)
leaq 2512(%rsp), %rdi
.LEHB0:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE0:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .L55
movq 16(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L55:
leaq 2512(%rsp), %rdi
.LEHB1:
call _ZNSt13random_device9_M_getvalEv@PLT
movl %eax, %eax
movq %rax, (%rsp)
movl $1, %ecx
movabsq $6364136223846793005, %r8
movabsq $945986875574848801, %rdi
.L59:
movq -8(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $62, %rdx
xorq %rdx, %rax
imulq %r8, %rax
movq %rax, %rsi
movq %rcx, %rdx
shrq $3, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $312, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addq %rsi, %rax
movq %rax, (%rsp,%rcx,8)
addq $1, %rcx
cmpq $312, %rcx
jne .L59
movq $312, 2496(%rsp)
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE1:
jmp .L78
.L70:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 7512(%rsp), %rax
subq %fs:40, %rax
je .L58
call __stack_chk_fail@PLT
.L58:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L78:
movq $1, nelem(%rip)
movl $1, %edx
leaq .LC20(%rip), %rbx
jmp .L60
.L80:
movq nelem(%rip), %rax
leaq (%rax,%rax), %rdx
movq %rdx, nelem(%rip)
cmpq $512, %rdx
jg .L79
.L60:
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
.LEHB3:
call __printf_chk@PLT
jmp .L80
.L79:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %ebp
leaq .LC23(%rip), %r15
jmp .L65
.L85:
movq $1, nelem(%rip)
jmp .L64
.L83:
testq %rax, %rax
je .L81
.L63:
movq nelem(%rip), %rax
addq %rax, %rax
movq %rax, nelem(%rip)
cmpq $512, %rax
jg .L82
.L64:
movq %rbp, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z8func_addPfS_l
jmp .L83
.L81:
movq %r15, %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L63
.L82:
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
leaq 0(%rbp,%rbp,4), %rax
addq %rax, %rax
movq %rax, %rbp
cmpq $1000000000, %rax
jg .L84
.L65:
leaq 0(,%rbp,4), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testq %rbp, %rbp
jle .L61
movl $0, %ebx
movq %rsp, %r14
.L62:
movq %r14, %rdi
call _ZSt18generate_canonicalIfLm24ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_
pxor %xmm1, %xmm1
addss %xmm1, %xmm0
movss %xmm0, 0(%r13,%rbx,4)
movq %r14, %rdi
call _ZSt18generate_canonicalIfLm24ESt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEET_RT1_
pxor %xmm2, %xmm2
addss %xmm2, %xmm0
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L62
.L61:
movq %rbp, %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE3:
jmp .L85
.L84:
leaq 2512(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 7512(%rsp), %rax
subq %fs:40, %rax
jne .L86
movl $0, %eax
addq $7528, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 2512(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 7512(%rsp), %rax
subq %fs:40, %rax
je .L67
call __stack_chk_fail@PLT
.L67:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4143:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4143:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4143-.LLSDACSB4143
.LLSDACSB4143:
.uleb128 .LEHB0-.LFB4143
.uleb128 .LEHE0-.LEHB0
.uleb128 .L70-.LFB4143
.uleb128 0
.uleb128 .LEHB1-.LFB4143
.uleb128 .LEHE1-.LEHB1
.uleb128 .L69-.LFB4143
.uleb128 0
.uleb128 .LEHB2-.LFB4143
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4143
.uleb128 .LEHE3-.LEHB3
.uleb128 .L69-.LFB4143
.uleb128 0
.uleb128 .LEHB4-.LFB4143
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4143:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl nelem
.bss
.align 8
.type nelem, @object
.size nelem, 8
nelem:
.zero 8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC13:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC14:
.long -1998362383
.long 1055193269
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC15:
.long 1065353215
.align 4
.LC17:
.long 528482304
.align 4
.LC18:
.long 1065353216
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<string.h>
#include<random>
#define cudaCheck(x) _cudaCheck(x, #x ,__FILE__, __LINE__)
template<typename T>
void _cudaCheck(T e, const char* func, const char* call, const int line){
if(e != cudaSuccess){
printf("\"%s\" at %d in %s\n\treturned %d\n-> %s\n", func, line, call, (int)e, cudaGetErrorString(e));
exit(EXIT_FAILURE);
}
}
// Number of elements worked by one thread
long nelem;
// Each threads work on nelem-elements in a pair of sz-long vector
__global__ void add_krnl(float *x, float *y, long sz, long nelem) {
// PARAMETER: 0 means adjacent, 1 means cyclical
int pattern = 1;
long i;
long inc = (sz + nelem-1) / nelem;
long start = blockIdx.x*1024 + threadIdx.x;
if (pattern == 0) {
start = start*nelem;
long end = start+nelem;
for(i = start; i < end && i < sz; i++) {
x[i] += y[i];
}
} else {
for (i = start; i < sz; i += inc) {
x[i] += y[i];
}
}
}
long func_add(float *x, float *y, long sz) {
long i;
// CPU Calculation
for (i = 0; i < sz; i++)
x[i] += y[i];
// GPU Calculation
float *dx, *dy;
cudaMalloc((float **) &dx, sz*sizeof(float));
cudaMalloc((float **) &dy, sz*sizeof(float));
cudaMemcpy(dx, x, sz*sizeof(float), cudaMemcpyHostToDevice);
// Timing using cudaEvent
cudaEvent_t start, stop;
float et;
cudaCheck(cudaEventCreate(&start));
cudaCheck(cudaEventCreate(&stop));
// Time event start
cudaCheck(cudaEventRecord(start));
{
long n_threads = (sz + nelem-1) / nelem;
long n_blocks = (n_threads + 1023) / 1024;
add_krnl<<<n_blocks, 1024>>>(dx, dy, sz, nelem);
}
cudaCheck(cudaGetLastError());
// Time event end
cudaCheck(cudaEventRecord(stop));
cudaCheck(cudaEventSynchronize(stop));
cudaCheck(cudaEventElapsedTime(&et, start, stop));
cudaCheck(cudaEventDestroy(start));
cudaCheck(cudaEventDestroy(stop));
printf("\t%0.3f", et);
// Copy data back to d_x and free GPU memory
float * d_x = (float *) malloc(sz * sizeof(float));
cudaMemcpy(d_x, dx, sz*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dx);
cudaFree(dy);
// Compare CPU and GPU output to see if it is within error tolerance
for (i = 0; i < sz; i++) {
if (fabsf(d_x[i] - x[i]) > 1e-5) {
free(d_x);
return 0;
}
}
free(d_x);
return 1;
}
int main(int argc, char **argv) {
float *a, *b;
long j;
long i;
std::random_device rd;
std::mt19937_64 mt(rd());
std::uniform_real_distribution<float> u(0, 1);
// Print title
printf("sz");
for (nelem = 1; nelem < 513; nelem *= 2)
printf("\t%d", nelem);
printf("\n");
for (j = 10; j <= 1000000000; j *= 10) {
a = (float *) malloc(sizeof(float) * j);
b = (float *) malloc(sizeof(float) * j);
// Initialize with random number generator
for (i = 0; i < j; i++) {
a[i] = u(mt);
b[i] = u(mt);
}
printf("%d", j);
for (nelem = 1; nelem < 513; nelem *= 2)
if (!func_add(a, b, j))
printf("failed to add\n");
printf("\n");
free(a);
free(b);
}
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<string.h>
#include<random>
#define cudaCheck(x) _cudaCheck(x, #x ,__FILE__, __LINE__)
template<typename T>
void _cudaCheck(T e, const char* func, const char* call, const int line){
if(e != hipSuccess){
printf("\"%s\" at %d in %s\n\treturned %d\n-> %s\n", func, line, call, (int)e, hipGetErrorString(e));
exit(EXIT_FAILURE);
}
}
// Number of elements worked by one thread
long nelem;
// Each threads work on nelem-elements in a pair of sz-long vector
__global__ void add_krnl(float *x, float *y, long sz, long nelem) {
// PARAMETER: 0 means adjacent, 1 means cyclical
int pattern = 1;
long i;
long inc = (sz + nelem-1) / nelem;
long start = blockIdx.x*1024 + threadIdx.x;
if (pattern == 0) {
start = start*nelem;
long end = start+nelem;
for(i = start; i < end && i < sz; i++) {
x[i] += y[i];
}
} else {
for (i = start; i < sz; i += inc) {
x[i] += y[i];
}
}
}
long func_add(float *x, float *y, long sz) {
long i;
// CPU Calculation
for (i = 0; i < sz; i++)
x[i] += y[i];
// GPU Calculation
float *dx, *dy;
hipMalloc((float **) &dx, sz*sizeof(float));
hipMalloc((float **) &dy, sz*sizeof(float));
hipMemcpy(dx, x, sz*sizeof(float), hipMemcpyHostToDevice);
// Timing using cudaEvent
hipEvent_t start, stop;
float et;
cudaCheck(hipEventCreate(&start));
cudaCheck(hipEventCreate(&stop));
// Time event start
cudaCheck(hipEventRecord(start));
{
long n_threads = (sz + nelem-1) / nelem;
long n_blocks = (n_threads + 1023) / 1024;
add_krnl<<<n_blocks, 1024>>>(dx, dy, sz, nelem);
}
cudaCheck(hipGetLastError());
// Time event end
cudaCheck(hipEventRecord(stop));
cudaCheck(hipEventSynchronize(stop));
cudaCheck(hipEventElapsedTime(&et, start, stop));
cudaCheck(hipEventDestroy(start));
cudaCheck(hipEventDestroy(stop));
printf("\t%0.3f", et);
// Copy data back to d_x and free GPU memory
float * d_x = (float *) malloc(sz * sizeof(float));
hipMemcpy(d_x, dx, sz*sizeof(float), hipMemcpyDeviceToHost);
hipFree(dx);
hipFree(dy);
// Compare CPU and GPU output to see if it is within error tolerance
for (i = 0; i < sz; i++) {
if (fabsf(d_x[i] - x[i]) > 1e-5) {
free(d_x);
return 0;
}
}
free(d_x);
return 1;
}
int main(int argc, char **argv) {
float *a, *b;
long j;
long i;
std::random_device rd;
std::mt19937_64 mt(rd());
std::uniform_real_distribution<float> u(0, 1);
// Print title
printf("sz");
for (nelem = 1; nelem < 513; nelem *= 2)
printf("\t%d", nelem);
printf("\n");
for (j = 10; j <= 1000000000; j *= 10) {
a = (float *) malloc(sizeof(float) * j);
b = (float *) malloc(sizeof(float) * j);
// Initialize with random number generator
for (i = 0; i < j; i++) {
a[i] = u(mt);
b[i] = u(mt);
}
printf("%d", j);
for (nelem = 1; nelem < 513; nelem *= 2)
if (!func_add(a, b, j))
printf("failed to add\n");
printf("\n");
free(a);
free(b);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<string.h>
#include<random>
#define cudaCheck(x) _cudaCheck(x, #x ,__FILE__, __LINE__)
template<typename T>
void _cudaCheck(T e, const char* func, const char* call, const int line){
if(e != hipSuccess){
printf("\"%s\" at %d in %s\n\treturned %d\n-> %s\n", func, line, call, (int)e, hipGetErrorString(e));
exit(EXIT_FAILURE);
}
}
// Number of elements worked by one thread
long nelem;
// Each threads work on nelem-elements in a pair of sz-long vector
__global__ void add_krnl(float *x, float *y, long sz, long nelem) {
// PARAMETER: 0 means adjacent, 1 means cyclical
int pattern = 1;
long i;
long inc = (sz + nelem-1) / nelem;
long start = blockIdx.x*1024 + threadIdx.x;
if (pattern == 0) {
start = start*nelem;
long end = start+nelem;
for(i = start; i < end && i < sz; i++) {
x[i] += y[i];
}
} else {
for (i = start; i < sz; i += inc) {
x[i] += y[i];
}
}
}
long func_add(float *x, float *y, long sz) {
long i;
// CPU Calculation
for (i = 0; i < sz; i++)
x[i] += y[i];
// GPU Calculation
float *dx, *dy;
hipMalloc((float **) &dx, sz*sizeof(float));
hipMalloc((float **) &dy, sz*sizeof(float));
hipMemcpy(dx, x, sz*sizeof(float), hipMemcpyHostToDevice);
// Timing using cudaEvent
hipEvent_t start, stop;
float et;
cudaCheck(hipEventCreate(&start));
cudaCheck(hipEventCreate(&stop));
// Time event start
cudaCheck(hipEventRecord(start));
{
long n_threads = (sz + nelem-1) / nelem;
long n_blocks = (n_threads + 1023) / 1024;
add_krnl<<<n_blocks, 1024>>>(dx, dy, sz, nelem);
}
cudaCheck(hipGetLastError());
// Time event end
cudaCheck(hipEventRecord(stop));
cudaCheck(hipEventSynchronize(stop));
cudaCheck(hipEventElapsedTime(&et, start, stop));
cudaCheck(hipEventDestroy(start));
cudaCheck(hipEventDestroy(stop));
printf("\t%0.3f", et);
// Copy data back to d_x and free GPU memory
float * d_x = (float *) malloc(sz * sizeof(float));
hipMemcpy(d_x, dx, sz*sizeof(float), hipMemcpyDeviceToHost);
hipFree(dx);
hipFree(dy);
// Compare CPU and GPU output to see if it is within error tolerance
for (i = 0; i < sz; i++) {
if (fabsf(d_x[i] - x[i]) > 1e-5) {
free(d_x);
return 0;
}
}
free(d_x);
return 1;
}
int main(int argc, char **argv) {
float *a, *b;
long j;
long i;
std::random_device rd;
std::mt19937_64 mt(rd());
std::uniform_real_distribution<float> u(0, 1);
// Print title
printf("sz");
for (nelem = 1; nelem < 513; nelem *= 2)
printf("\t%d", nelem);
printf("\n");
for (j = 10; j <= 1000000000; j *= 10) {
a = (float *) malloc(sizeof(float) * j);
b = (float *) malloc(sizeof(float) * j);
// Initialize with random number generator
for (i = 0; i < j; i++) {
a[i] = u(mt);
b[i] = u(mt);
}
printf("%d", j);
for (nelem = 1; nelem < 513; nelem *= 2)
if (!func_add(a, b, j))
printf("failed to add\n");
printf("\n");
free(a);
free(b);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8add_krnlPfS_ll
.globl _Z8add_krnlPfS_ll
.p2align 8
.type _Z8add_krnlPfS_ll,@function
_Z8add_krnlPfS_ll:
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s6
s_addc_u32 s3, s5, s7
s_add_u32 s8, s2, -1
s_addc_u32 s9, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_or_b64 s[10:11], s[8:9], s[6:7]
s_mov_b32 s10, 0
s_cmp_lg_u64 s[10:11], 0
s_cbranch_scc0 .LBB0_7
s_ashr_i32 s12, s7, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s2, s6, s12
s_mov_b32 s13, s12
s_addc_u32 s3, s7, s12
s_xor_b64 s[2:3], s[2:3], s[12:13]
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s2
v_cvt_f32_u32_e32 v2, s3
s_sub_u32 s14, 0, s2
s_subb_u32 s16, 0, s3
v_fmamk_f32 v1, v2, 0x4f800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
v_mul_f32_e32 v2, 0x2f800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v2, v2
v_fmamk_f32 v1, v2, 0xcf800000, v1
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s7, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s11, v1
s_mul_i32 s17, s14, s7
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s19, s14, s11
s_mul_i32 s18, s16, s11
s_add_i32 s17, s19, s17
s_mul_i32 s20, s14, s11
s_add_i32 s17, s17, s18
s_mul_hi_u32 s19, s11, s20
s_mul_hi_u32 s21, s7, s20
s_mul_i32 s18, s7, s20
s_mul_hi_u32 s20, s11, s17
s_mul_i32 s11, s11, s17
s_mul_hi_u32 s22, s7, s17
s_add_u32 s11, s19, s11
s_addc_u32 s19, 0, s20
s_add_u32 s11, s11, s18
s_mul_i32 s17, s7, s17
s_addc_u32 s11, s19, s21
s_addc_u32 s18, s22, 0
s_add_u32 s11, s11, s17
s_addc_u32 s17, 0, s18
v_add_co_u32 v1, s11, v1, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s11, 0
s_addc_u32 s7, s7, s17
v_readfirstlane_b32 s11, v1
s_mul_i32 s17, s14, s7
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s18, s14, s11
s_mul_i32 s16, s16, s11
s_add_i32 s17, s18, s17
s_mul_i32 s14, s14, s11
s_add_i32 s17, s17, s16
s_mul_hi_u32 s18, s7, s14
s_mul_i32 s19, s7, s14
s_mul_hi_u32 s14, s11, s14
s_mul_hi_u32 s20, s11, s17
s_mul_i32 s11, s11, s17
s_mul_hi_u32 s16, s7, s17
s_add_u32 s11, s14, s11
s_addc_u32 s14, 0, s20
s_add_u32 s11, s11, s19
s_mul_i32 s17, s7, s17
s_addc_u32 s11, s14, s18
s_addc_u32 s14, s16, 0
s_add_u32 s11, s11, s17
s_addc_u32 s14, 0, s14
v_add_co_u32 v1, s11, v1, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s11, 0
s_addc_u32 s7, s7, s14
s_ashr_i32 s16, s9, 31
s_add_u32 s18, s8, s16
s_addc_u32 s19, s9, s16
v_readfirstlane_b32 s9, v1
s_mov_b32 s17, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[18:19], s[18:19], s[16:17]
s_mul_i32 s14, s18, s7
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s20, s18, s9
s_mul_hi_u32 s11, s18, s7
s_mul_hi_u32 s22, s19, s9
s_mul_i32 s9, s19, s9
s_add_u32 s14, s20, s14
s_addc_u32 s11, 0, s11
s_mul_hi_u32 s21, s19, s7
s_add_u32 s9, s14, s9
s_mul_i32 s7, s19, s7
s_addc_u32 s9, s11, s22
s_addc_u32 s11, s21, 0
s_add_u32 s7, s9, s7
s_addc_u32 s9, 0, s11
s_mul_i32 s21, s2, s7
s_mul_hi_u32 s11, s2, s7
s_mul_i32 s20, s2, s9
v_sub_co_u32 v1, s18, s18, s21
s_mul_i32 s14, s3, s7
s_add_i32 s11, s11, s20
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s11, s11, s14
v_sub_co_u32 v2, s20, v1, s2
s_sub_i32 s14, s19, s11
s_cmp_lg_u32 s18, 0
s_subb_u32 s14, s14, s3
s_cmp_lg_u32 s20, 0
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_subb_u32 s14, s14, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s14, s3
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
s_cselect_b32 s20, -1, 0
s_cmp_eq_u32 s14, s3
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s14, s7, 1
v_cndmask_b32_e32 v2, s20, v2, vcc_lo
s_addc_u32 s20, s9, 0
s_add_u32 s21, s7, 2
s_addc_u32 s22, s9, 0
v_mov_b32_e32 v3, s21
s_cmp_lg_u32 s18, 0
v_cmp_le_u32_e32 vcc_lo, s2, v1
s_subb_u32 s2, s19, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s2, s3
v_cndmask_b32_e64 v1, 0, -1, vcc_lo
s_cselect_b32 s11, -1, 0
s_cmp_eq_u32 s2, s3
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_cselect_b32 s2, -1, 0
v_mov_b32_e32 v2, s22
v_cndmask_b32_e64 v1, s11, v1, s2
s_xor_b64 s[2:3], s[16:17], s[12:13]
v_cndmask_b32_e32 v3, s14, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, s20, v2, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v1, s9, v2, vcc_lo
v_cndmask_b32_e32 v2, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v3, s3, v1
v_xor_b32_e32 v2, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_co_u32 v1, vcc_lo, v2, s2
v_subrev_co_ci_u32_e32 v2, vcc_lo, s3, v3, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_3
.LBB0_2:
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s3, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s2, s8, s2
s_mul_i32 s3, s2, s6
s_add_i32 s7, s2, 1
s_sub_i32 s3, s8, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s8, s3, s6
s_cmp_ge_u32 s3, s6
s_cselect_b32 s2, s7, s2
s_cselect_b32 s3, s8, s3
s_add_i32 s7, s2, 1
s_cmp_ge_u32 s3, s6
s_mov_b32 s3, 0
s_cselect_b32 s2, s7, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
.LBB0_3:
v_lshl_or_b32 v3, s15, 10, v0
v_mov_b32_e32 v4, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 s[4:5], v[3:4]
s_cbranch_execz .LBB0_6
s_load_b128 s[8:11], s[0:1], 0x0
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_mov_b32 s1, 0
.p2align 6
.LBB0_5:
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, v1
global_load_b32 v0, v[9:10], off
global_load_b32 v9, v[11:12], off
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v2, vcc_lo
v_add_co_u32 v5, s0, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, v6, v8, s0
v_cmp_le_i64_e32 vcc_lo, s[4:5], v[3:4]
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v9
global_store_b32 v[11:12], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_7:
s_branch .LBB0_2
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8add_krnlPfS_ll
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8add_krnlPfS_ll, .Lfunc_end0-_Z8add_krnlPfS_ll
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8add_krnlPfS_ll
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z8add_krnlPfS_ll.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<string.h>
#include<random>
#define cudaCheck(x) _cudaCheck(x, #x ,__FILE__, __LINE__)
template<typename T>
void _cudaCheck(T e, const char* func, const char* call, const int line){
if(e != hipSuccess){
printf("\"%s\" at %d in %s\n\treturned %d\n-> %s\n", func, line, call, (int)e, hipGetErrorString(e));
exit(EXIT_FAILURE);
}
}
// Number of elements worked by one thread
long nelem;
// Each threads work on nelem-elements in a pair of sz-long vector
__global__ void add_krnl(float *x, float *y, long sz, long nelem) {
// PARAMETER: 0 means adjacent, 1 means cyclical
int pattern = 1;
long i;
long inc = (sz + nelem-1) / nelem;
long start = blockIdx.x*1024 + threadIdx.x;
if (pattern == 0) {
start = start*nelem;
long end = start+nelem;
for(i = start; i < end && i < sz; i++) {
x[i] += y[i];
}
} else {
for (i = start; i < sz; i += inc) {
x[i] += y[i];
}
}
}
long func_add(float *x, float *y, long sz) {
long i;
// CPU Calculation
for (i = 0; i < sz; i++)
x[i] += y[i];
// GPU Calculation
float *dx, *dy;
hipMalloc((float **) &dx, sz*sizeof(float));
hipMalloc((float **) &dy, sz*sizeof(float));
hipMemcpy(dx, x, sz*sizeof(float), hipMemcpyHostToDevice);
// Timing using cudaEvent
hipEvent_t start, stop;
float et;
cudaCheck(hipEventCreate(&start));
cudaCheck(hipEventCreate(&stop));
// Time event start
cudaCheck(hipEventRecord(start));
{
long n_threads = (sz + nelem-1) / nelem;
long n_blocks = (n_threads + 1023) / 1024;
add_krnl<<<n_blocks, 1024>>>(dx, dy, sz, nelem);
}
cudaCheck(hipGetLastError());
// Time event end
cudaCheck(hipEventRecord(stop));
cudaCheck(hipEventSynchronize(stop));
cudaCheck(hipEventElapsedTime(&et, start, stop));
cudaCheck(hipEventDestroy(start));
cudaCheck(hipEventDestroy(stop));
printf("\t%0.3f", et);
// Copy data back to d_x and free GPU memory
float * d_x = (float *) malloc(sz * sizeof(float));
hipMemcpy(d_x, dx, sz*sizeof(float), hipMemcpyDeviceToHost);
hipFree(dx);
hipFree(dy);
// Compare CPU and GPU output to see if it is within error tolerance
for (i = 0; i < sz; i++) {
if (fabsf(d_x[i] - x[i]) > 1e-5) {
free(d_x);
return 0;
}
}
free(d_x);
return 1;
}
int main(int argc, char **argv) {
float *a, *b;
long j;
long i;
std::random_device rd;
std::mt19937_64 mt(rd());
std::uniform_real_distribution<float> u(0, 1);
// Print title
printf("sz");
for (nelem = 1; nelem < 513; nelem *= 2)
printf("\t%d", nelem);
printf("\n");
for (j = 10; j <= 1000000000; j *= 10) {
a = (float *) malloc(sizeof(float) * j);
b = (float *) malloc(sizeof(float) * j);
// Initialize with random number generator
for (i = 0; i < j; i++) {
a[i] = u(mt);
b[i] = u(mt);
}
printf("%d", j);
for (nelem = 1; nelem < 513; nelem *= 2)
if (!func_add(a, b, j))
printf("failed to add\n");
printf("\n");
free(a);
free(b);
}
return 0;
} | .text
.file "driver.hip"
.globl _Z23__device_stub__add_krnlPfS_ll # -- Begin function _Z23__device_stub__add_krnlPfS_ll
.p2align 4, 0x90
.type _Z23__device_stub__add_krnlPfS_ll,@function
_Z23__device_stub__add_krnlPfS_ll: # @_Z23__device_stub__add_krnlPfS_ll
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8add_krnlPfS_ll, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__add_krnlPfS_ll, .Lfunc_end0-_Z23__device_stub__add_krnlPfS_ll
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z8func_addPfS_l
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl _Z8func_addPfS_l
.p2align 4, 0x90
.type _Z8func_addPfS_l,@function
_Z8func_addPfS_l: # @_Z8func_addPfS_l
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rdi, %r14
testq %rdx, %rdx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq %rax, %rbx
jne .LBB1_2
.LBB1_3: # %._crit_edge
leaq (,%rbx,4), %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_4
# %bb.6: # %_Z10_cudaCheckI10hipError_tEvT_PKcS3_i.exit
movq %rsp, %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_7
# %bb.8: # %_Z10_cudaCheckI10hipError_tEvT_PKcS3_i.exit32
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_9
# %bb.10: # %_Z10_cudaCheckI10hipError_tEvT_PKcS3_i.exit34
movq nelem(%rip), %rcx
leaq (%rbx,%rcx), %rax
decq %rax
cqto
idivq %rcx
leaq 1023(%rax), %rcx
addq $2046, %rax # imm = 0x7FE
testq %rcx, %rcx
cmovnsq %rcx, %rax
shrq $10, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq nelem(%rip), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rbx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8add_krnlPfS_ll, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_13
# %bb.14: # %_Z10_cudaCheckI10hipError_tEvT_PKcS3_i.exit36
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_15
# %bb.16: # %_Z10_cudaCheckI10hipError_tEvT_PKcS3_i.exit38
movq (%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_17
# %bb.18: # %_Z10_cudaCheckI10hipError_tEvT_PKcS3_i.exit40
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_19
# %bb.20: # %_Z10_cudaCheckI10hipError_tEvT_PKcS3_i.exit42
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_21
# %bb.22: # %_Z10_cudaCheckI10hipError_tEvT_PKcS3_i.exit44
movq (%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_23
# %bb.24: # %_Z10_cudaCheckI10hipError_tEvT_PKcS3_i.exit46
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq 8(%rsp), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $1, %r15d
testq %rbx, %rbx
jle .LBB1_29
# %bb.25: # %.lr.ph52.preheader
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_27: # %.lr.ph52
# =>This Inner Loop Header: Depth=1
movss (%r12,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r14,%rax,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB1_28
# %bb.26: # in Loop: Header=BB1_27 Depth=1
incq %rax
cmpq %rax, %rbx
jne .LBB1_27
jmp .LBB1_29
.LBB1_28:
xorl %r15d, %r15d
.LBB1_29: # %._crit_edge53
movq %r12, %rdi
callq free
movq %r15, %rax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 192
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
movl $.L.str, %esi
movl $.L.str.1, %ecx
movl $59, %edx
jmp .LBB1_5
.LBB1_7:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
movl $.L.str.2, %esi
movl $.L.str.1, %ecx
movl $60, %edx
jmp .LBB1_5
.LBB1_9:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
movl $.L.str.3, %esi
movl $.L.str.1, %ecx
movl $63, %edx
jmp .LBB1_5
.LBB1_13:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
movl $.L.str.4, %esi
movl $.L.str.1, %ecx
movl $72, %edx
jmp .LBB1_5
.LBB1_15:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
movl $.L.str.5, %esi
movl $.L.str.1, %ecx
movl $75, %edx
jmp .LBB1_5
.LBB1_17:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
movl $.L.str.6, %esi
movl $.L.str.1, %ecx
movl $76, %edx
jmp .LBB1_5
.LBB1_19:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
movl $.L.str.7, %esi
movl $.L.str.1, %ecx
movl $77, %edx
jmp .LBB1_5
.LBB1_21:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
movl $.L.str.8, %esi
movl $.L.str.1, %ecx
movl $78, %edx
jmp .LBB1_5
.LBB1_23:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.19, %edi
movl $.L.str.9, %esi
movl $.L.str.1, %ecx
movl $79, %edx
.LBB1_5:
movl %ebx, %r8d
movq %rax, %r9
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z8func_addPfS_l, .Lfunc_end1-_Z8func_addPfS_l
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x5f800000 # float 1.84467441E+19
.LCPI2_1:
.long 0x40000000 # float 2
.LCPI2_2:
.long 0x5f000000 # float 9.22337203E+18
.LCPI2_3:
.long 0x3f800000 # float 1
.LCPI2_4:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $7576, %rsp # imm = 0x1D98
.cfi_def_cfa_offset 7632
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 88(%rsp), %r14
movq %r14, 72(%rsp)
movl $1634100580, 88(%rsp) # imm = 0x61666564
movl $1953264993, 91(%rsp) # imm = 0x746C7561
movq $7, 80(%rsp)
movb $0, 95(%rsp)
.Ltmp0:
leaq 2576(%rsp), %rdi
leaq 72(%rsp), %rsi
callq _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 72(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_3
# %bb.2: # %.critedge.i.i.i
callq _ZdlPv
.LBB2_3: # %_ZNSt13random_deviceC2Ev.exit
.Ltmp3:
leaq 2576(%rsp), %rdi
callq _ZNSt13random_device9_M_getvalEv
.Ltmp4:
# %bb.4: # %_ZNSt13random_deviceclEv.exit
movl %eax, %esi
movq %rsi, 72(%rsp)
movl $1, %eax
movabsq $6364136223846793005, %rcx # imm = 0x5851F42D4C957F2D
movq %rsi, %rdx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
shrq $62, %rdx
xorq %rsi, %rdx
imulq %rcx, %rdx
addq %rax, %rdx
movq %rdx, 72(%rsp,%rax,8)
incq %rax
movq %rdx, %rsi
cmpq $312, %rax # imm = 0x138
jne .LBB2_5
# %bb.6: # %_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEC2Em.exit
movq $312, 2568(%rsp) # imm = 0x138
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq $1, nelem(%rip)
movl $1, %esi
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movq nelem(%rip), %rax
leaq (%rax,%rax), %rsi
movq %rsi, nelem(%rip)
cmpq $257, %rax # imm = 0x101
jl .LBB2_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movl $10, %ebx
leaq 72(%rsp), %r14
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_38: # in Loop: Header=BB2_9 Depth=1
movl $10, %edi
callq putchar@PLT
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
leaq (%rbx,%rbx), %rax
leaq (%rax,%rax,4), %rax
cmpq $100000001, %rbx # imm = 0x5F5E101
movq %rax, %rbx
jae .LBB2_39
.LBB2_9: # =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
# Child Loop BB2_11 Depth 3
# Child Loop BB2_25 Depth 3
# Child Loop BB2_34 Depth 2
leaq (,%rbx,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %r12
cmpq $1, %rbx
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rbx, %rbp
adcq $0, %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_11 Depth 3
# Child Loop BB2_25 Depth 3
flds .LCPI2_0(%rip)
fstpt (%rsp)
callq logl
fstpt 32(%rsp) # 10-byte Folded Spill
flds .LCPI2_1(%rip)
fstpt (%rsp)
callq logl
fldt 32(%rsp) # 10-byte Folded Reload
fdivp %st, %st(1)
flds .LCPI2_2(%rip)
xorl %ecx, %ecx
fxch %st(1)
fucomi %st(1), %st
fldz
fcmovnb %st(2), %st
fstp %st(2)
fsubp %st, %st(1)
setae %cl
fnstcw 18(%rsp)
movzwl 18(%rsp), %eax
orl $3072, %eax # imm = 0xC00
movw %ax, 46(%rsp)
fldcw 46(%rsp)
fistpll 64(%rsp)
fldcw 18(%rsp)
shlq $63, %rcx
xorq 64(%rsp), %rcx
leaq 23(%rcx), %rax
xorl %edx, %edx
divq %rcx
movq %rax, %r13
cmpq $1, %rax
adcq $0, %r13
xorps %xmm0, %xmm0
movss %xmm0, 32(%rsp) # 4-byte Spill
movss .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp) # 4-byte Spill
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_20: # %.noexc
# in Loop: Header=BB2_11 Depth=3
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
.LBB2_21: # %.noexc
# in Loop: Header=BB2_11 Depth=3
movss 20(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
movss 32(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, 32(%rsp) # 4-byte Spill
mulss .LCPI2_0(%rip), %xmm2
movss %xmm2, 20(%rsp) # 4-byte Spill
decq %r13
je .LBB2_22
.LBB2_11: # Parent Loop BB2_9 Depth=1
# Parent Loop BB2_10 Depth=2
# => This Inner Loop Header: Depth=3
.Ltmp6:
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.Ltmp7:
# %bb.12: # %.noexc
# in Loop: Header=BB2_11 Depth=3
testq %rax, %rax
jns .LBB2_20
# %bb.13: # in Loop: Header=BB2_11 Depth=3
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
jmp .LBB2_21
.p2align 4, 0x90
.LBB2_22: # in Loop: Header=BB2_10 Depth=2
movss 32(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
divss 20(%rsp), %xmm2 # 4-byte Folded Reload
movss .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm2
jae .LBB2_23
.LBB2_24: # %_ZNSt25uniform_real_distributionIfEclISt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEEEfRT_.exit
# in Loop: Header=BB2_10 Depth=2
xorps %xmm1, %xmm1
xorps %xmm0, %xmm0
movss %xmm0, 32(%rsp) # 4-byte Spill
addss %xmm1, %xmm2
movss %xmm2, (%r15,%rbx,4)
flds .LCPI2_0(%rip)
fstpt (%rsp)
callq logl
fstpt 20(%rsp) # 10-byte Folded Spill
flds .LCPI2_1(%rip)
fstpt (%rsp)
callq logl
fldt 20(%rsp) # 10-byte Folded Reload
fdivp %st, %st(1)
flds .LCPI2_2(%rip)
xorl %ecx, %ecx
fxch %st(1)
fucomi %st(1), %st
fldz
fcmovnb %st(2), %st
fstp %st(2)
fsubp %st, %st(1)
setae %cl
fnstcw 16(%rsp)
movzwl 16(%rsp), %eax
orl $3072, %eax # imm = 0xC00
movw %ax, 44(%rsp)
fldcw 44(%rsp)
fistpll 56(%rsp)
fldcw 16(%rsp)
shlq $63, %rcx
xorq 56(%rsp), %rcx
leaq 23(%rcx), %rax
xorl %edx, %edx
divq %rcx
movq %rax, %r13
cmpq $1, %rax
adcq $0, %r13
movss .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp) # 4-byte Spill
jmp .LBB2_25
.p2align 4, 0x90
.LBB2_28: # %.noexc32
# in Loop: Header=BB2_25 Depth=3
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
.LBB2_29: # %.noexc32
# in Loop: Header=BB2_25 Depth=3
movss 20(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
mulss %xmm2, %xmm0
movss 32(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
addss %xmm0, %xmm1
movss %xmm1, 32(%rsp) # 4-byte Spill
mulss .LCPI2_0(%rip), %xmm2
movss %xmm2, 20(%rsp) # 4-byte Spill
decq %r13
je .LBB2_30
.LBB2_25: # Parent Loop BB2_9 Depth=1
# Parent Loop BB2_10 Depth=2
# => This Inner Loop Header: Depth=3
.Ltmp9:
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.Ltmp10:
# %bb.26: # %.noexc32
# in Loop: Header=BB2_25 Depth=3
testq %rax, %rax
jns .LBB2_28
# %bb.27: # in Loop: Header=BB2_25 Depth=3
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
jmp .LBB2_29
.p2align 4, 0x90
.LBB2_30: # in Loop: Header=BB2_10 Depth=2
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss 20(%rsp), %xmm0 # 4-byte Folded Reload
ucomiss .LCPI2_3(%rip), %xmm0
jae .LBB2_31
.LBB2_32: # %_ZNSt25uniform_real_distributionIfEclISt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEEEfRT_.exit33
# in Loop: Header=BB2_10 Depth=2
addss .LCPI2_4(%rip), %xmm0
movss %xmm0, (%r12,%rbx,4)
incq %rbx
cmpq %rbp, %rbx
jne .LBB2_10
jmp .LBB2_33
.LBB2_23: # in Loop: Header=BB2_10 Depth=2
xorps %xmm1, %xmm1
movss .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq nextafterf
movaps %xmm0, %xmm2
jmp .LBB2_24
.LBB2_31: # in Loop: Header=BB2_10 Depth=2
xorps %xmm1, %xmm1
movss .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq nextafterf
jmp .LBB2_32
.p2align 4, 0x90
.LBB2_33: # in Loop: Header=BB2_9 Depth=1
movl $.L.str.14, %edi
movq 48(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq $1, nelem(%rip)
jmp .LBB2_34
.p2align 4, 0x90
.LBB2_37: # in Loop: Header=BB2_34 Depth=2
movq nelem(%rip), %rax
leaq (%rax,%rax), %rcx
movq %rcx, nelem(%rip)
cmpq $257, %rax # imm = 0x101
jge .LBB2_38
.LBB2_34: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp12:
movq %r15, %rdi
movq %r12, %rsi
movq %rbx, %rdx
callq _Z8func_addPfS_l
.Ltmp13:
# %bb.35: # in Loop: Header=BB2_34 Depth=2
testq %rax, %rax
jne .LBB2_37
# %bb.36: # in Loop: Header=BB2_34 Depth=2
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB2_37
.LBB2_39:
.Ltmp18:
leaq 2576(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp19:
# %bb.40: # %_ZNSt13random_deviceD2Ev.exit
xorl %eax, %eax
addq $7576, %rsp # imm = 0x1D98
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_43:
.cfi_def_cfa_offset 7632
.Ltmp20:
movq %rax, %rdi
callq __clang_call_terminate
.LBB2_41:
.Ltmp5:
jmp .LBB2_42
.LBB2_14:
.Ltmp2:
movq %rax, %rbx
movq 72(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_16
# %bb.15: # %.critedge.i.i6.i
callq _ZdlPv
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB2_19: # %.loopexit.split-lp.loopexit.split-lp
.Ltmp14:
jmp .LBB2_42
.LBB2_17: # %.loopexit
.Ltmp11:
jmp .LBB2_42
.LBB2_18: # %.loopexit.split-lp.loopexit
.Ltmp8:
.LBB2_42: # %.loopexit.split-lp
movq %rax, %rbx
.Ltmp15:
leaq 2576(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp16:
.LBB2_16: # %common.resume
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB2_44:
.Ltmp17:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 1 # On action: 1
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp15-.Ltmp19 # Call between .Ltmp19 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 1 # On action: 1
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end2-.Ltmp16 # Call between .Ltmp16 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end3:
.size __clang_call_terminate, .Lfunc_end3-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv,@function
_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv: # @_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.cfi_startproc
# %bb.0:
cmpq $312, 2496(%rdi) # imm = 0x138
jb .LBB4_6
# %bb.1: # %.preheader.preheader
movabsq $-5403634167711393303, %rax # imm = 0xB5026F5AA96619E9
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 1248(%rdi,%rdx,8), %r9
andl $1, %r8d
negq %r8
andq %rax, %r8
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $156, %rsi
jne .LBB4_2
# %bb.3: # %.preheader.i.preheader
movl $157, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1256(%rdi,%rcx,8), %r9
andl $1, %r8d
negq %r8
andq %rax, %r8
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $312, %rcx # imm = 0x138
jne .LBB4_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 2488(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 1240(%rdi), %rsi
andl $1, %edx
negq %rdx
andq %rax, %rdx
xorq %rsi, %rdx
movq %rdx, 2488(%rdi)
movq $0, 2496(%rdi)
.LBB4_6:
movq 2496(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 2496(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $29, %rcx
movabsq $22906492245, %rdx # imm = 0x555555555
andq %rcx, %rdx
xorq %rax, %rdx
movq %rdx, %rax
shlq $17, %rax
movabsq $8202884508482404352, %rcx # imm = 0x71D67FFFEDA60000
andq %rax, %rcx
xorq %rdx, %rcx
movl %ecx, %edx
andl $134201207, %edx # imm = 0x7FFBF77
shlq $37, %rdx
xorq %rcx, %rdx
movq %rdx, %rax
shrq $43, %rax
xorq %rdx, %rax
retq
.Lfunc_end4:
.size _ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv, .Lfunc_end4-_ZNSt23mersenne_twister_engineImLm64ELm312ELm156ELm31ELm13043109905998158313ELm29ELm6148914691236517205ELm17ELm8202884508482404352ELm37ELm18444473444759240704ELm43ELm6364136223846793005EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8add_krnlPfS_ll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type nelem,@object # @nelem
.bss
.globl nelem
.p2align 3, 0x0
nelem:
.quad 0 # 0x0
.size nelem, 8
.type _Z8add_krnlPfS_ll,@object # @_Z8add_krnlPfS_ll
.section .rodata,"a",@progbits
.globl _Z8add_krnlPfS_ll
.p2align 3, 0x0
_Z8add_krnlPfS_ll:
.quad _Z23__device_stub__add_krnlPfS_ll
.size _Z8add_krnlPfS_ll, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipEventCreate(&start)"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/kyledpierson/gpu-programming/master/gpu-add/driver.hip"
.size .L.str.1, 112
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipEventCreate(&stop)"
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipEventRecord(start)"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipGetLastError()"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipEventRecord(stop)"
.size .L.str.5, 21
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipEventSynchronize(stop)"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipEventElapsedTime(&et, start, stop)"
.size .L.str.7, 38
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipEventDestroy(start)"
.size .L.str.8, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipEventDestroy(stop)"
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\t%0.3f"
.size .L.str.10, 7
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "sz"
.size .L.str.11, 3
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\t%d"
.size .L.str.12, 4
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%d"
.size .L.str.14, 3
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "default"
.size .L.str.16, 8
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "\"%s\" at %d in %s\n\treturned %d\n-> %s\n"
.size .L.str.19, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8add_krnlPfS_ll"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "failed to add"
.size .Lstr, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__add_krnlPfS_ll
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z8add_krnlPfS_ll
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdlib.h>
#include <iomanip>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
using namespace std;
#define MAX_ARRAY_SIZE 2048
#define RANDOM_MAX 2.0
#define RANDOM_MIN 1.0
#define TILE_WIDTH 32
#define EPSILON 0.000001
#define NUM_BLOCKS (MAX_ARRAY_SIZE/TILE_WIDTH)
float A[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
float F[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
float C[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
void serial();
void init_F();
int check();
__global__ void matrixMultiply1(float *, float *, int);
__global__ void matrixMultiply2(float *, float *, int);
__global__ void matrixMultiply3(float *, float *, int);
int main()
{
float *d_a, *d_c;
struct timeval startTime, endTime;
size_t memsize = MAX_ARRAY_SIZE * MAX_ARRAY_SIZE * sizeof(float);
cudaMalloc((void**) &d_a, memsize);
cudaMalloc((void**) &d_c, memsize);
init_F();
cudaMemcpy(d_a,A,memsize,cudaMemcpyHostToDevice);
cudaMemcpy(d_c,C,memsize,cudaMemcpyHostToDevice);
gettimeofday(&startTime, NULL);
//serial();
//dim3 dimGrid1(1,1);
//dim3 dimBlock1(MAX_ARRAY_SIZE, MAX_ARRAY_SIZE);
dim3 dimGrid2(MAX_ARRAY_SIZE/TILE_WIDTH, MAX_ARRAY_SIZE/TILE_WIDTH);
dim3 dimBlock2(TILE_WIDTH, TILE_WIDTH);
matrixMultiply1<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);
//matrixMultiply2<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);*/
//matrixMultiply3<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);
gettimeofday(&endTime, NULL);
long seconds = endTime.tv_sec - startTime.tv_sec;
long useconds = endTime.tv_usec - startTime.tv_usec;
double duration = seconds + useconds/1000000.0;
cout<<"\nTime taken for Matrix Multiplication on GPU (time in sec): "<<fixed<<setprecision(7)<<duration;
cout<<"\nPerformance Metrics (GFlops/sec):"<<fixed<<setprecision(6)<<((2 * (long)MAX_ARRAY_SIZE * MAX_ARRAY_SIZE * MAX_ARRAY_SIZE))/(1e9 * duration);
cout<<endl;
cudaMemcpy(C,d_c,memsize,cudaMemcpyDeviceToHost);
if(check() == 1) {
cout<<"\nMatrix Multiplication Successful!"<<endl;
}
cudaFree(d_a);
cudaFree(d_c);
return 0;
}
void init_F()
{
srand(time(NULL));
for (int i = 0; i < MAX_ARRAY_SIZE; i++){
for (int j = 0; j < MAX_ARRAY_SIZE; j++){
float r = ((float)rand()) / (float)RAND_MAX;
A[i][j] = RANDOM_MIN + r * (RANDOM_MAX - RANDOM_MIN);
}
}
}
__global__ void matrixMultiply1(float *A, float *C, int size) {
int Col = blockDim.y * blockIdx.y + threadIdx.y;
int Row = blockDim.x * blockIdx.x + threadIdx.x;
for(int k = 0; k < size; k++)
C[Row * size + Col] += A[k * size + Row] * A[k * size + Col];
}
__global__ void matrixMultiply2(float* A, float* C, int size)
{
float sum = 0;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
if(Col < size && Row < size) {
for (int k = 0; k < size; k++)
sum += A[k * size + Row] * A[k * size + Col];
C[Row * size + Col] = sum;
}
}
__global__ void matrixMultiply3(float* A, float* C, int size) {
float CValue = 0;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
__shared__ float As[TILE_WIDTH][TILE_WIDTH];
for (int k = 0; k < (TILE_WIDTH + size - 1)/TILE_WIDTH; k++) {
if (k * TILE_WIDTH + threadIdx.x < size && Row < size)
As[threadIdx.y][threadIdx.x] = A[Row * size + k * TILE_WIDTH + threadIdx.x];
else
As[threadIdx.y][threadIdx.x] = 0.0;
if (k * TILE_WIDTH + threadIdx.y < size && Col < size)
As[threadIdx.y][threadIdx.x] = A[(k*TILE_WIDTH + threadIdx.y) * size + Col];
else
As[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int n = 0; n < TILE_WIDTH; ++n)
CValue += As[threadIdx.y][n] * As[n][threadIdx.x];
__syncthreads();
}
if (Row < size && Col < size)
C[((blockIdx.y * blockDim.y + threadIdx.y) * size) + (blockIdx.x*blockDim.x) + threadIdx.x] = CValue;
}
void serial()
{
for (int i = 0; i < MAX_ARRAY_SIZE; i++)
for (int j = 0; j < MAX_ARRAY_SIZE; j++)
for (int k = 0; k < MAX_ARRAY_SIZE; k++)
F[i][j] += A[k][i] * A[k][j];
}
int check()
{
for (int i = 0; i < MAX_ARRAY_SIZE; i++) {
for (int j = 0; j < MAX_ARRAY_SIZE; j++) {
if(abs(C[i][j] - F[i][j]) < EPSILON){
cout<<"\nMismatch at index: ("<<i<<","<<j<<")"<<endl;
return 0;
}
}
}
return 1;
} | .file "tmpxft_0018bff2_00000000-6_kumari_sangeeta_lab4p2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6init_Fv
.type _Z6init_Fv, @function
_Z6init_Fv:
.LFB3950:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 8192+A(%rip), %rbp
leaq -8192(%rbp), %r12
addq $16785408, %r12
.L4:
leaq -8192(%rbp), %rbx
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss .LC1(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8192, %rbp
cmpq %r12, %rbp
jne .L4
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3950:
.size _Z6init_Fv, .-_Z6init_Fv
.globl _Z6serialv
.type _Z6serialv, @function
_Z6serialv:
.LFB3951:
.cfi_startproc
endbr64
leaq A(%rip), %r10
leaq 16777216(%r10), %rcx
movl $0, %r9d
leaq F(%rip), %r11
.L10:
imulq $-8196, %r9, %rsi
addq %r11, %rsi
movq %r9, %rax
negq %rax
leaq (%r10,%rax,4), %r8
movq %r9, %rdx
leaq 2048(%r9), %rdi
.L14:
movss (%rsi,%rdx,4), %xmm1
movq %r8, %rax
.L11:
movss (%rax), %xmm0
mulss (%rax,%rdx,4), %xmm0
addss %xmm0, %xmm1
addq $8192, %rax
cmpq %rcx, %rax
jne .L11
movss %xmm1, (%rsi,%rdx,4)
addq $1, %rdx
cmpq %rdi, %rdx
jne .L14
subq $1, %r9
addq $4, %rcx
cmpq $-2048, %r9
jne .L10
ret
.cfi_endproc
.LFE3951:
.size _Z6serialv, .-_Z6serialv
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "\nMismatch at index: ("
.LC6:
.string ","
.LC7:
.string ")"
.text
.globl _Z5checkv
.type _Z5checkv, @function
_Z5checkv:
.LFB3952:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq C(%rip), %rdx
leaq F(%rip), %rax
movl $0, %r12d
movss .LC3(%rip), %xmm2
movsd .LC4(%rip), %xmm1
.L17:
movl $0, %ebx
.L24:
movss (%rdx,%rbx,4), %xmm0
subss (%rax,%rbx,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm0, %xmm1
ja .L30
addq $1, %rbx
cmpq $2048, %rbx
jne .L24
addl $1, %r12d
addq $8192, %rdx
addq $8192, %rax
cmpl $2048, %r12d
jne .L17
movl $1, %eax
jmp .L16
.L30:
movl $21, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L31
cmpb $0, 56(%rbp)
je .L21
movzbl 67(%rbp), %esi
.L22:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
.L16:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L21:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.cfi_endproc
.LFE3952:
.size _Z5checkv, .-_Z5checkv
.globl _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
.type _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i, @function
_Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i:
.LFB3977:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMultiply1PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i, .-_Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
.globl _Z15matrixMultiply1PfS_i
.type _Z15matrixMultiply1PfS_i, @function
_Z15matrixMultiply1PfS_i:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z15matrixMultiply1PfS_i, .-_Z15matrixMultiply1PfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "\nTime taken for Matrix Multiplication on GPU (time in sec): "
.align 8
.LC10:
.string "\nPerformance Metrics (GFlops/sec):"
.align 8
.LC13:
.string "\nMatrix Multiplication Successful!"
.text
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $112, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
call _Z6init_Fv
movl $1, %ecx
movl $16777216, %edx
leaq A(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
leaq C(%rip), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $64, 40(%rsp)
movl $64, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 52(%rsp)
movl $32, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq %rdi, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rdx)
movq (%rdi), %rax
movq -24(%rax), %rax
movq $7, 8(%rdi,%rax)
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq %rdi, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rdx)
movq (%rdi), %rax
movq -24(%rax), %rax
movq $6, 8(%rdi,%rax)
movsd 8(%rsp), %xmm1
mulsd .LC11(%rip), %xmm1
movsd .LC12(%rip), %xmm0
divsd %xmm1, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $16777216, %edx
movq 32(%rsp), %rsi
leaq C(%rip), %rdi
call cudaMemcpy@PLT
call _Z5checkv
cmpl $1, %eax
je .L46
.L42:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl $2048, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
jmp .L41
.L46:
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.globl _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
.type _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i, @function
_Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i:
.LFB3979:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMultiply2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3979:
.size _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i, .-_Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
.globl _Z15matrixMultiply2PfS_i
.type _Z15matrixMultiply2PfS_i, @function
_Z15matrixMultiply2PfS_i:
.LFB3980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _Z15matrixMultiply2PfS_i, .-_Z15matrixMultiply2PfS_i
.globl _Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i
.type _Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i, @function
_Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i:
.LFB3981:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMultiply3PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3981:
.size _Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i, .-_Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i
.globl _Z15matrixMultiply3PfS_i
.type _Z15matrixMultiply3PfS_i, @function
_Z15matrixMultiply3PfS_i:
.LFB3982:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3982:
.size _Z15matrixMultiply3PfS_i, .-_Z15matrixMultiply3PfS_i
.section .rodata.str1.1
.LC14:
.string "_Z15matrixMultiply3PfS_i"
.LC15:
.string "_Z15matrixMultiply2PfS_i"
.LC16:
.string "_Z15matrixMultiply1PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3984:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMultiply3PfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMultiply2PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMultiply1PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3984:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl C
.bss
.align 32
.type C, @object
.size C, 16777216
C:
.zero 16777216
.globl F
.align 32
.type F, @object
.size F, 16777216
F:
.zero 16777216
.globl A
.align 32
.type A, @object
.size A, 16777216
A:
.zero 16777216
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1065353216
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -1598689907
.long 1051772663
.align 8
.LC8:
.long 0
.long 1093567616
.align 8
.LC11:
.long 0
.long 1104006501
.align 8
.LC12:
.long 0
.long 1108344832
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdlib.h>
#include <iomanip>
#include <time.h>
#include <sys/time.h>
#include <cuda.h>
using namespace std;
#define MAX_ARRAY_SIZE 2048
#define RANDOM_MAX 2.0
#define RANDOM_MIN 1.0
#define TILE_WIDTH 32
#define EPSILON 0.000001
#define NUM_BLOCKS (MAX_ARRAY_SIZE/TILE_WIDTH)
float A[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
float F[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
float C[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
void serial();
void init_F();
int check();
__global__ void matrixMultiply1(float *, float *, int);
__global__ void matrixMultiply2(float *, float *, int);
__global__ void matrixMultiply3(float *, float *, int);
int main()
{
float *d_a, *d_c;
struct timeval startTime, endTime;
size_t memsize = MAX_ARRAY_SIZE * MAX_ARRAY_SIZE * sizeof(float);
cudaMalloc((void**) &d_a, memsize);
cudaMalloc((void**) &d_c, memsize);
init_F();
cudaMemcpy(d_a,A,memsize,cudaMemcpyHostToDevice);
cudaMemcpy(d_c,C,memsize,cudaMemcpyHostToDevice);
gettimeofday(&startTime, NULL);
//serial();
//dim3 dimGrid1(1,1);
//dim3 dimBlock1(MAX_ARRAY_SIZE, MAX_ARRAY_SIZE);
dim3 dimGrid2(MAX_ARRAY_SIZE/TILE_WIDTH, MAX_ARRAY_SIZE/TILE_WIDTH);
dim3 dimBlock2(TILE_WIDTH, TILE_WIDTH);
matrixMultiply1<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);
//matrixMultiply2<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);*/
//matrixMultiply3<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);
gettimeofday(&endTime, NULL);
long seconds = endTime.tv_sec - startTime.tv_sec;
long useconds = endTime.tv_usec - startTime.tv_usec;
double duration = seconds + useconds/1000000.0;
cout<<"\nTime taken for Matrix Multiplication on GPU (time in sec): "<<fixed<<setprecision(7)<<duration;
cout<<"\nPerformance Metrics (GFlops/sec):"<<fixed<<setprecision(6)<<((2 * (long)MAX_ARRAY_SIZE * MAX_ARRAY_SIZE * MAX_ARRAY_SIZE))/(1e9 * duration);
cout<<endl;
cudaMemcpy(C,d_c,memsize,cudaMemcpyDeviceToHost);
if(check() == 1) {
cout<<"\nMatrix Multiplication Successful!"<<endl;
}
cudaFree(d_a);
cudaFree(d_c);
return 0;
}
void init_F()
{
srand(time(NULL));
for (int i = 0; i < MAX_ARRAY_SIZE; i++){
for (int j = 0; j < MAX_ARRAY_SIZE; j++){
float r = ((float)rand()) / (float)RAND_MAX;
A[i][j] = RANDOM_MIN + r * (RANDOM_MAX - RANDOM_MIN);
}
}
}
__global__ void matrixMultiply1(float *A, float *C, int size) {
int Col = blockDim.y * blockIdx.y + threadIdx.y;
int Row = blockDim.x * blockIdx.x + threadIdx.x;
for(int k = 0; k < size; k++)
C[Row * size + Col] += A[k * size + Row] * A[k * size + Col];
}
__global__ void matrixMultiply2(float* A, float* C, int size)
{
float sum = 0;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
if(Col < size && Row < size) {
for (int k = 0; k < size; k++)
sum += A[k * size + Row] * A[k * size + Col];
C[Row * size + Col] = sum;
}
}
__global__ void matrixMultiply3(float* A, float* C, int size) {
float CValue = 0;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
__shared__ float As[TILE_WIDTH][TILE_WIDTH];
for (int k = 0; k < (TILE_WIDTH + size - 1)/TILE_WIDTH; k++) {
if (k * TILE_WIDTH + threadIdx.x < size && Row < size)
As[threadIdx.y][threadIdx.x] = A[Row * size + k * TILE_WIDTH + threadIdx.x];
else
As[threadIdx.y][threadIdx.x] = 0.0;
if (k * TILE_WIDTH + threadIdx.y < size && Col < size)
As[threadIdx.y][threadIdx.x] = A[(k*TILE_WIDTH + threadIdx.y) * size + Col];
else
As[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int n = 0; n < TILE_WIDTH; ++n)
CValue += As[threadIdx.y][n] * As[n][threadIdx.x];
__syncthreads();
}
if (Row < size && Col < size)
C[((blockIdx.y * blockDim.y + threadIdx.y) * size) + (blockIdx.x*blockDim.x) + threadIdx.x] = CValue;
}
void serial()
{
for (int i = 0; i < MAX_ARRAY_SIZE; i++)
for (int j = 0; j < MAX_ARRAY_SIZE; j++)
for (int k = 0; k < MAX_ARRAY_SIZE; k++)
F[i][j] += A[k][i] * A[k][j];
}
int check()
{
for (int i = 0; i < MAX_ARRAY_SIZE; i++) {
for (int j = 0; j < MAX_ARRAY_SIZE; j++) {
if(abs(C[i][j] - F[i][j]) < EPSILON){
cout<<"\nMismatch at index: ("<<i<<","<<j<<")"<<endl;
return 0;
}
}
}
return 1;
} | #include <iostream>
#include <stdlib.h>
#include <iomanip>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
using namespace std;
#define MAX_ARRAY_SIZE 2048
#define RANDOM_MAX 2.0
#define RANDOM_MIN 1.0
#define TILE_WIDTH 32
#define EPSILON 0.000001
#define NUM_BLOCKS (MAX_ARRAY_SIZE/TILE_WIDTH)
float A[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
float F[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
float C[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
void serial();
void init_F();
int check();
__global__ void matrixMultiply1(float *, float *, int);
__global__ void matrixMultiply2(float *, float *, int);
__global__ void matrixMultiply3(float *, float *, int);
int main()
{
float *d_a, *d_c;
struct timeval startTime, endTime;
size_t memsize = MAX_ARRAY_SIZE * MAX_ARRAY_SIZE * sizeof(float);
hipMalloc((void**) &d_a, memsize);
hipMalloc((void**) &d_c, memsize);
init_F();
hipMemcpy(d_a,A,memsize,hipMemcpyHostToDevice);
hipMemcpy(d_c,C,memsize,hipMemcpyHostToDevice);
gettimeofday(&startTime, NULL);
//serial();
//dim3 dimGrid1(1,1);
//dim3 dimBlock1(MAX_ARRAY_SIZE, MAX_ARRAY_SIZE);
dim3 dimGrid2(MAX_ARRAY_SIZE/TILE_WIDTH, MAX_ARRAY_SIZE/TILE_WIDTH);
dim3 dimBlock2(TILE_WIDTH, TILE_WIDTH);
matrixMultiply1<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);
//matrixMultiply2<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);*/
//matrixMultiply3<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);
gettimeofday(&endTime, NULL);
long seconds = endTime.tv_sec - startTime.tv_sec;
long useconds = endTime.tv_usec - startTime.tv_usec;
double duration = seconds + useconds/1000000.0;
cout<<"\nTime taken for Matrix Multiplication on GPU (time in sec): "<<fixed<<setprecision(7)<<duration;
cout<<"\nPerformance Metrics (GFlops/sec):"<<fixed<<setprecision(6)<<((2 * (long)MAX_ARRAY_SIZE * MAX_ARRAY_SIZE * MAX_ARRAY_SIZE))/(1e9 * duration);
cout<<endl;
hipMemcpy(C,d_c,memsize,hipMemcpyDeviceToHost);
if(check() == 1) {
cout<<"\nMatrix Multiplication Successful!"<<endl;
}
hipFree(d_a);
hipFree(d_c);
return 0;
}
void init_F()
{
srand(time(NULL));
for (int i = 0; i < MAX_ARRAY_SIZE; i++){
for (int j = 0; j < MAX_ARRAY_SIZE; j++){
float r = ((float)rand()) / (float)RAND_MAX;
A[i][j] = RANDOM_MIN + r * (RANDOM_MAX - RANDOM_MIN);
}
}
}
__global__ void matrixMultiply1(float *A, float *C, int size) {
int Col = blockDim.y * blockIdx.y + threadIdx.y;
int Row = blockDim.x * blockIdx.x + threadIdx.x;
for(int k = 0; k < size; k++)
C[Row * size + Col] += A[k * size + Row] * A[k * size + Col];
}
__global__ void matrixMultiply2(float* A, float* C, int size)
{
float sum = 0;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
if(Col < size && Row < size) {
for (int k = 0; k < size; k++)
sum += A[k * size + Row] * A[k * size + Col];
C[Row * size + Col] = sum;
}
}
__global__ void matrixMultiply3(float* A, float* C, int size) {
float CValue = 0;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
__shared__ float As[TILE_WIDTH][TILE_WIDTH];
for (int k = 0; k < (TILE_WIDTH + size - 1)/TILE_WIDTH; k++) {
if (k * TILE_WIDTH + threadIdx.x < size && Row < size)
As[threadIdx.y][threadIdx.x] = A[Row * size + k * TILE_WIDTH + threadIdx.x];
else
As[threadIdx.y][threadIdx.x] = 0.0;
if (k * TILE_WIDTH + threadIdx.y < size && Col < size)
As[threadIdx.y][threadIdx.x] = A[(k*TILE_WIDTH + threadIdx.y) * size + Col];
else
As[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int n = 0; n < TILE_WIDTH; ++n)
CValue += As[threadIdx.y][n] * As[n][threadIdx.x];
__syncthreads();
}
if (Row < size && Col < size)
C[((blockIdx.y * blockDim.y + threadIdx.y) * size) + (blockIdx.x*blockDim.x) + threadIdx.x] = CValue;
}
void serial()
{
for (int i = 0; i < MAX_ARRAY_SIZE; i++)
for (int j = 0; j < MAX_ARRAY_SIZE; j++)
for (int k = 0; k < MAX_ARRAY_SIZE; k++)
F[i][j] += A[k][i] * A[k][j];
}
int check()
{
for (int i = 0; i < MAX_ARRAY_SIZE; i++) {
for (int j = 0; j < MAX_ARRAY_SIZE; j++) {
if(abs(C[i][j] - F[i][j]) < EPSILON){
cout<<"\nMismatch at index: ("<<i<<","<<j<<")"<<endl;
return 0;
}
}
}
return 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <stdlib.h>
#include <iomanip>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
using namespace std;
#define MAX_ARRAY_SIZE 2048
#define RANDOM_MAX 2.0
#define RANDOM_MIN 1.0
#define TILE_WIDTH 32
#define EPSILON 0.000001
#define NUM_BLOCKS (MAX_ARRAY_SIZE/TILE_WIDTH)
float A[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
float F[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
float C[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
void serial();
void init_F();
int check();
__global__ void matrixMultiply1(float *, float *, int);
__global__ void matrixMultiply2(float *, float *, int);
__global__ void matrixMultiply3(float *, float *, int);
int main()
{
float *d_a, *d_c;
struct timeval startTime, endTime;
size_t memsize = MAX_ARRAY_SIZE * MAX_ARRAY_SIZE * sizeof(float);
hipMalloc((void**) &d_a, memsize);
hipMalloc((void**) &d_c, memsize);
init_F();
hipMemcpy(d_a,A,memsize,hipMemcpyHostToDevice);
hipMemcpy(d_c,C,memsize,hipMemcpyHostToDevice);
gettimeofday(&startTime, NULL);
//serial();
//dim3 dimGrid1(1,1);
//dim3 dimBlock1(MAX_ARRAY_SIZE, MAX_ARRAY_SIZE);
dim3 dimGrid2(MAX_ARRAY_SIZE/TILE_WIDTH, MAX_ARRAY_SIZE/TILE_WIDTH);
dim3 dimBlock2(TILE_WIDTH, TILE_WIDTH);
matrixMultiply1<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);
//matrixMultiply2<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);*/
//matrixMultiply3<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);
gettimeofday(&endTime, NULL);
long seconds = endTime.tv_sec - startTime.tv_sec;
long useconds = endTime.tv_usec - startTime.tv_usec;
double duration = seconds + useconds/1000000.0;
cout<<"\nTime taken for Matrix Multiplication on GPU (time in sec): "<<fixed<<setprecision(7)<<duration;
cout<<"\nPerformance Metrics (GFlops/sec):"<<fixed<<setprecision(6)<<((2 * (long)MAX_ARRAY_SIZE * MAX_ARRAY_SIZE * MAX_ARRAY_SIZE))/(1e9 * duration);
cout<<endl;
hipMemcpy(C,d_c,memsize,hipMemcpyDeviceToHost);
if(check() == 1) {
cout<<"\nMatrix Multiplication Successful!"<<endl;
}
hipFree(d_a);
hipFree(d_c);
return 0;
}
void init_F()
{
srand(time(NULL));
for (int i = 0; i < MAX_ARRAY_SIZE; i++){
for (int j = 0; j < MAX_ARRAY_SIZE; j++){
float r = ((float)rand()) / (float)RAND_MAX;
A[i][j] = RANDOM_MIN + r * (RANDOM_MAX - RANDOM_MIN);
}
}
}
__global__ void matrixMultiply1(float *A, float *C, int size) {
int Col = blockDim.y * blockIdx.y + threadIdx.y;
int Row = blockDim.x * blockIdx.x + threadIdx.x;
for(int k = 0; k < size; k++)
C[Row * size + Col] += A[k * size + Row] * A[k * size + Col];
}
__global__ void matrixMultiply2(float* A, float* C, int size)
{
float sum = 0;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
if(Col < size && Row < size) {
for (int k = 0; k < size; k++)
sum += A[k * size + Row] * A[k * size + Col];
C[Row * size + Col] = sum;
}
}
__global__ void matrixMultiply3(float* A, float* C, int size) {
float CValue = 0;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
__shared__ float As[TILE_WIDTH][TILE_WIDTH];
for (int k = 0; k < (TILE_WIDTH + size - 1)/TILE_WIDTH; k++) {
if (k * TILE_WIDTH + threadIdx.x < size && Row < size)
As[threadIdx.y][threadIdx.x] = A[Row * size + k * TILE_WIDTH + threadIdx.x];
else
As[threadIdx.y][threadIdx.x] = 0.0;
if (k * TILE_WIDTH + threadIdx.y < size && Col < size)
As[threadIdx.y][threadIdx.x] = A[(k*TILE_WIDTH + threadIdx.y) * size + Col];
else
As[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int n = 0; n < TILE_WIDTH; ++n)
CValue += As[threadIdx.y][n] * As[n][threadIdx.x];
__syncthreads();
}
if (Row < size && Col < size)
C[((blockIdx.y * blockDim.y + threadIdx.y) * size) + (blockIdx.x*blockDim.x) + threadIdx.x] = CValue;
}
void serial()
{
for (int i = 0; i < MAX_ARRAY_SIZE; i++)
for (int j = 0; j < MAX_ARRAY_SIZE; j++)
for (int k = 0; k < MAX_ARRAY_SIZE; k++)
F[i][j] += A[k][i] * A[k][j];
}
int check()
{
for (int i = 0; i < MAX_ARRAY_SIZE; i++) {
for (int j = 0; j < MAX_ARRAY_SIZE; j++) {
if(abs(C[i][j] - F[i][j]) < EPSILON){
cout<<"\nMismatch at index: ("<<i<<","<<j<<")"<<endl;
return 0;
}
}
}
return 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixMultiply1PfS_i
.globl _Z15matrixMultiply1PfS_i
.p2align 8
.type _Z15matrixMultiply1PfS_i,@function
_Z15matrixMultiply1PfS_i:
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, s4
global_load_b32 v4, v[2:3], off
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v5, s2, v1
v_add_nc_u32_e32 v7, s2, v0
s_add_i32 s3, s3, -1
s_add_i32 s2, s2, s4
s_cmp_eq_u32 s3, 0
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[7:8], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v5, v6
global_store_b32 v[2:3], v4, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMultiply1PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixMultiply1PfS_i, .Lfunc_end0-_Z15matrixMultiply1PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15matrixMultiply2PfS_i
.globl _Z15matrixMultiply2PfS_i
.p2align 8
.type _Z15matrixMultiply2PfS_i,@function
_Z15matrixMultiply2PfS_i:
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 5, v1
v_lshl_add_u32 v1, s15, 5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB1_6
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0
s_mov_b32 s6, s4
.p2align 6
.LBB1_3:
v_add_nc_u32_e32 v3, s5, v1
v_add_nc_u32_e32 v5, s5, v0
s_add_i32 s6, s6, -1
s_add_i32 s5, s5, s4
s_cmp_eq_u32 s6, 0
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v3, v4
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
v_mov_b32_e32 v2, 0
.LBB1_5:
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMultiply2PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15matrixMultiply2PfS_i, .Lfunc_end1-_Z15matrixMultiply2PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15matrixMultiply3PfS_i
.globl _Z15matrixMultiply3PfS_i
.p2align 8
.type _Z15matrixMultiply3PfS_i,@function
_Z15matrixMultiply3PfS_i:
s_load_b32 s3, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v7, s15, 5, v1
v_lshl_add_u32 v2, s14, 5, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB2_13
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v8, 2, v0
v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v9, 7, v1
s_add_i32 s2, s3, 31
v_mad_u64_u32 v[3:4], null, v7, s3, v[0:1]
s_lshr_b32 s6, s2, 5
v_cmp_gt_i32_e32 vcc_lo, s3, v7
v_cmp_gt_i32_e64 s2, s3, v2
v_add_nc_u32_e32 v10, v9, v8
s_max_i32 s6, s6, 1
s_mov_b32 s7, 0
s_xor_b32 s8, vcc_lo, -1
s_xor_b32 s2, s2, -1
.LBB2_2:
s_lshl_b32 s9, s7, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s9, v0
v_cmp_le_u32_e32 vcc_lo, s3, v4
s_or_b32 s10, s8, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s11, s10
s_xor_b32 s10, exec_lo, s11
s_cbranch_execz .LBB2_4
ds_store_b32 v10, v5
.LBB2_4:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB2_6
v_add_nc_u32_e32 v4, s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v4, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v4
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v4, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s3, v4
s_or_b32 s9, s2, vcc_lo
s_and_saveexec_b32 s10, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s9, exec_lo, s10
s_cbranch_execz .LBB2_8
ds_store_b32 v10, v5
.LBB2_8:
s_and_not1_saveexec_b32 s9, s9
s_cbranch_execz .LBB2_10
v_mad_u64_u32 v[11:12], null, v4, s3, v[2:3]
v_mov_b32_e32 v12, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v4, v[11:12], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v4
.LBB2_10:
s_or_b32 exec_lo, exec_lo, s9
v_mov_b32_e32 v4, v8
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB2_11:
v_add_nc_u32_e32 v11, s9, v9
s_add_i32 s9, s9, 4
ds_load_b32 v12, v4
ds_load_b32 v11, v11
v_add_nc_u32_e32 v4, 0x80, v4
s_cmpk_eq_i32 s9, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v6, v11, v12
s_cbranch_scc0 .LBB2_11
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s6
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB2_2
s_branch .LBB2_14
.LBB2_13:
v_mov_b32_e32 v6, 0
.LBB2_14:
v_max_i32_e32 v2, v7, v2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB2_16
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s3
v_add3_u32 v0, s14, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB2_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMultiply3PfS_i
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15matrixMultiply3PfS_i, .Lfunc_end2-_Z15matrixMultiply3PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMultiply1PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMultiply1PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMultiply2PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMultiply2PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMultiply3PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMultiply3PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <stdlib.h>
#include <iomanip>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
using namespace std;
#define MAX_ARRAY_SIZE 2048
#define RANDOM_MAX 2.0
#define RANDOM_MIN 1.0
#define TILE_WIDTH 32
#define EPSILON 0.000001
#define NUM_BLOCKS (MAX_ARRAY_SIZE/TILE_WIDTH)
float A[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
float F[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
float C[MAX_ARRAY_SIZE][MAX_ARRAY_SIZE];
void serial();
void init_F();
int check();
__global__ void matrixMultiply1(float *, float *, int);
__global__ void matrixMultiply2(float *, float *, int);
__global__ void matrixMultiply3(float *, float *, int);
int main()
{
float *d_a, *d_c;
struct timeval startTime, endTime;
size_t memsize = MAX_ARRAY_SIZE * MAX_ARRAY_SIZE * sizeof(float);
hipMalloc((void**) &d_a, memsize);
hipMalloc((void**) &d_c, memsize);
init_F();
hipMemcpy(d_a,A,memsize,hipMemcpyHostToDevice);
hipMemcpy(d_c,C,memsize,hipMemcpyHostToDevice);
gettimeofday(&startTime, NULL);
//serial();
//dim3 dimGrid1(1,1);
//dim3 dimBlock1(MAX_ARRAY_SIZE, MAX_ARRAY_SIZE);
dim3 dimGrid2(MAX_ARRAY_SIZE/TILE_WIDTH, MAX_ARRAY_SIZE/TILE_WIDTH);
dim3 dimBlock2(TILE_WIDTH, TILE_WIDTH);
matrixMultiply1<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);
//matrixMultiply2<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);*/
//matrixMultiply3<<< dimGrid2, dimBlock2 >>>(d_a,d_c,MAX_ARRAY_SIZE);
gettimeofday(&endTime, NULL);
long seconds = endTime.tv_sec - startTime.tv_sec;
long useconds = endTime.tv_usec - startTime.tv_usec;
double duration = seconds + useconds/1000000.0;
cout<<"\nTime taken for Matrix Multiplication on GPU (time in sec): "<<fixed<<setprecision(7)<<duration;
cout<<"\nPerformance Metrics (GFlops/sec):"<<fixed<<setprecision(6)<<((2 * (long)MAX_ARRAY_SIZE * MAX_ARRAY_SIZE * MAX_ARRAY_SIZE))/(1e9 * duration);
cout<<endl;
hipMemcpy(C,d_c,memsize,hipMemcpyDeviceToHost);
if(check() == 1) {
cout<<"\nMatrix Multiplication Successful!"<<endl;
}
hipFree(d_a);
hipFree(d_c);
return 0;
}
void init_F()
{
srand(time(NULL));
for (int i = 0; i < MAX_ARRAY_SIZE; i++){
for (int j = 0; j < MAX_ARRAY_SIZE; j++){
float r = ((float)rand()) / (float)RAND_MAX;
A[i][j] = RANDOM_MIN + r * (RANDOM_MAX - RANDOM_MIN);
}
}
}
__global__ void matrixMultiply1(float *A, float *C, int size) {
int Col = blockDim.y * blockIdx.y + threadIdx.y;
int Row = blockDim.x * blockIdx.x + threadIdx.x;
for(int k = 0; k < size; k++)
C[Row * size + Col] += A[k * size + Row] * A[k * size + Col];
}
__global__ void matrixMultiply2(float* A, float* C, int size)
{
float sum = 0;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
if(Col < size && Row < size) {
for (int k = 0; k < size; k++)
sum += A[k * size + Row] * A[k * size + Col];
C[Row * size + Col] = sum;
}
}
__global__ void matrixMultiply3(float* A, float* C, int size) {
float CValue = 0;
int Row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int Col = blockIdx.x * TILE_WIDTH + threadIdx.x;
__shared__ float As[TILE_WIDTH][TILE_WIDTH];
for (int k = 0; k < (TILE_WIDTH + size - 1)/TILE_WIDTH; k++) {
if (k * TILE_WIDTH + threadIdx.x < size && Row < size)
As[threadIdx.y][threadIdx.x] = A[Row * size + k * TILE_WIDTH + threadIdx.x];
else
As[threadIdx.y][threadIdx.x] = 0.0;
if (k * TILE_WIDTH + threadIdx.y < size && Col < size)
As[threadIdx.y][threadIdx.x] = A[(k*TILE_WIDTH + threadIdx.y) * size + Col];
else
As[threadIdx.y][threadIdx.x] = 0.0;
__syncthreads();
for (int n = 0; n < TILE_WIDTH; ++n)
CValue += As[threadIdx.y][n] * As[n][threadIdx.x];
__syncthreads();
}
if (Row < size && Col < size)
C[((blockIdx.y * blockDim.y + threadIdx.y) * size) + (blockIdx.x*blockDim.x) + threadIdx.x] = CValue;
}
void serial()
{
for (int i = 0; i < MAX_ARRAY_SIZE; i++)
for (int j = 0; j < MAX_ARRAY_SIZE; j++)
for (int k = 0; k < MAX_ARRAY_SIZE; k++)
F[i][j] += A[k][i] * A[k][j];
}
int check()
{
for (int i = 0; i < MAX_ARRAY_SIZE; i++) {
for (int j = 0; j < MAX_ARRAY_SIZE; j++) {
if(abs(C[i][j] - F[i][j]) < EPSILON){
cout<<"\nMismatch at index: ("<<i<<","<<j<<")"<<endl;
return 0;
}
}
}
return 1;
} | .text
.file "kumari_sangeeta_lab4p2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_3:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI0_4:
.quad 0x4210000000000000 # double 17179869184
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $A, %r14d
.p2align 4, 0x90
.LBB0_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $2048, %r15 # imm = 0x800
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rbx
addq $8192, %r14 # imm = 0x2000
cmpq $2048, %rbx # imm = 0x800
jne .LBB0_1
# %bb.4: # %_Z6init_Fv.exit
movq 8(%rsp), %rdi
movl $A, %esi
movl $16777216, %edx # imm = 0x1000000
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $C, %esi
movl $16777216, %edx # imm = 0x1000000
movl $1, %ecx
callq hipMemcpy
leaq 128(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $2048, 20(%rsp) # imm = 0x800
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 20(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z15matrixMultiply1PfS_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 128(%rsp), %rax
subq 136(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
divsd .LCPI0_2(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $60, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movl $-261, %ebx # imm = 0xFEFB
movl _ZSt4cout+24(%rcx), %edx
andl %ebx, %edx
orl $4, %edx
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $7, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
andl _ZSt4cout+24(%rcx), %ebx
orl $4, %ebx
movl %ebx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $6, _ZSt4cout+8(%rax)
movsd 24(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI0_3(%rip), %xmm1
movsd .LCPI0_4(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_17
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB0_10
.LBB0_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rsi
movl $C, %edi
movl $16777216, %edx # imm = 0x1000000
movl $2, %ecx
callq hipMemcpy
callq _Z5checkv
cmpl $1, %eax
jne .LBB0_16
# %bb.11:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_17
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%rbx)
je .LBB0_14
# %bb.13:
movzbl 67(%rbx), %eax
jmp .LBB0_15
.LBB0_14:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB0_16:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_17:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6init_Fv
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x3f800000 # float 1
.text
.globl _Z6init_Fv
.p2align 4, 0x90
.type _Z6init_Fv,@function
_Z6init_Fv: # @_Z6init_Fv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $A, %r14d
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $2048, %r15 # imm = 0x800
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $8192, %r14 # imm = 0x2000
cmpq $2048, %rbx # imm = 0x800
jne .LBB1_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6init_Fv, .Lfunc_end1-_Z6init_Fv
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixMultiply1PfS_i # -- Begin function _Z30__device_stub__matrixMultiply1PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMultiply1PfS_i,@function
_Z30__device_stub__matrixMultiply1PfS_i: # @_Z30__device_stub__matrixMultiply1PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMultiply1PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__matrixMultiply1PfS_i, .Lfunc_end2-_Z30__device_stub__matrixMultiply1PfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z5checkv
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5checkv
.p2align 4, 0x90
.type _Z5checkv,@function
_Z5checkv: # @_Z5checkv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r12d, %r12d
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI3_1(%rip), %xmm2 # xmm2 = mem[0],zero
xorl %ebx, %ebx
xorl %r13d, %r13d
jmp .LBB3_1
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_1 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB3_1 Depth=1
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testb %bpl, %bpl
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI3_1(%rip), %xmm2 # xmm2 = mem[0],zero
je .LBB3_13
.LBB3_12: # %.critedge
# in Loop: Header=BB3_1 Depth=1
cmpq $2047, %rbx # imm = 0x7FF
leaq 1(%rbx), %rax
setae %r13b
addq $8192, %r12 # imm = 0x2000
movq %rax, %rbx
cmpq $2048, %rax # imm = 0x800
je .LBB3_13
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_11 Depth 2
movq %rbx, %rax
shlq $13, %rax
movss C(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss F(%rax), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm0, %xmm2
jbe .LBB3_10
# %bb.2: # in Loop: Header=BB3_1 Depth=1
xorl %r14d, %r14d
xorl %ebp, %ebp
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_10: # %.lr.ph.preheader
# in Loop: Header=BB3_1 Depth=1
movq $-1, %r14
.p2align 4, 0x90
.LBB3_11: # %.lr.ph
# Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $2046, %r14 # imm = 0x7FE
je .LBB3_12
# %bb.3: # in Loop: Header=BB3_11 Depth=2
movss C+8(%r12,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss F+8(%r12,%r14,4), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
incq %r14
ucomisd %xmm0, %xmm2
jbe .LBB3_11
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_1 Depth=1
cmpq $2047, %r14 # imm = 0x7FF
setae %bpl
incq %r14
.LBB3_5: # in Loop: Header=BB3_1 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_14
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_1 Depth=1
cmpb $0, 56(%r15)
je .LBB3_8
# %bb.7: # in Loop: Header=BB3_1 Depth=1
movzbl 67(%r15), %eax
jmp .LBB3_9
.LBB3_13:
movzbl %r13b, %eax
andl $1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_14:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z5checkv, .Lfunc_end3-_Z5checkv
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixMultiply2PfS_i # -- Begin function _Z30__device_stub__matrixMultiply2PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMultiply2PfS_i,@function
_Z30__device_stub__matrixMultiply2PfS_i: # @_Z30__device_stub__matrixMultiply2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMultiply2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z30__device_stub__matrixMultiply2PfS_i, .Lfunc_end4-_Z30__device_stub__matrixMultiply2PfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixMultiply3PfS_i # -- Begin function _Z30__device_stub__matrixMultiply3PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMultiply3PfS_i,@function
_Z30__device_stub__matrixMultiply3PfS_i: # @_Z30__device_stub__matrixMultiply3PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMultiply3PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z30__device_stub__matrixMultiply3PfS_i, .Lfunc_end5-_Z30__device_stub__matrixMultiply3PfS_i
.cfi_endproc
# -- End function
.globl _Z6serialv # -- Begin function _Z6serialv
.p2align 4, 0x90
.type _Z6serialv,@function
_Z6serialv: # @_Z6serialv
.cfi_startproc
# %bb.0:
movl $A, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_1: # %.preheader14
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
# Child Loop BB6_3 Depth 3
movq %rcx, %rdx
shlq $13, %rdx
movl $A, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB6_2: # %.preheader
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_3 Depth 3
leaq (%rdx,%rdi,4), %r8
addq $F, %r8
movss F(%rdx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_3: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r9), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rsi,%r9), %xmm1
addss %xmm1, %xmm0
addq $8192, %r9 # imm = 0x2000
cmpq $16777216, %r9 # imm = 0x1000000
jne .LBB6_3
# %bb.4: # in Loop: Header=BB6_2 Depth=2
movss %xmm0, (%r8)
incq %rdi
addq $4, %rsi
cmpq $2048, %rdi # imm = 0x800
jne .LBB6_2
# %bb.5: # in Loop: Header=BB6_1 Depth=1
incq %rcx
addq $4, %rax
cmpq $2048, %rcx # imm = 0x800
jne .LBB6_1
# %bb.6:
retq
.Lfunc_end6:
.size _Z6serialv, .Lfunc_end6-_Z6serialv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMultiply1PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMultiply2PfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMultiply3PfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type A,@object # @A
.bss
.globl A
.p2align 4, 0x0
A:
.zero 16777216
.size A, 16777216
.type F,@object # @F
.globl F
.p2align 4, 0x0
F:
.zero 16777216
.size F, 16777216
.type C,@object # @C
.globl C
.p2align 4, 0x0
C:
.zero 16777216
.size C, 16777216
.type _Z15matrixMultiply1PfS_i,@object # @_Z15matrixMultiply1PfS_i
.section .rodata,"a",@progbits
.globl _Z15matrixMultiply1PfS_i
.p2align 3, 0x0
_Z15matrixMultiply1PfS_i:
.quad _Z30__device_stub__matrixMultiply1PfS_i
.size _Z15matrixMultiply1PfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nTime taken for Matrix Multiplication on GPU (time in sec): "
.size .L.str, 61
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nPerformance Metrics (GFlops/sec):"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nMatrix Multiplication Successful!"
.size .L.str.2, 35
.type _Z15matrixMultiply2PfS_i,@object # @_Z15matrixMultiply2PfS_i
.section .rodata,"a",@progbits
.globl _Z15matrixMultiply2PfS_i
.p2align 3, 0x0
_Z15matrixMultiply2PfS_i:
.quad _Z30__device_stub__matrixMultiply2PfS_i
.size _Z15matrixMultiply2PfS_i, 8
.type _Z15matrixMultiply3PfS_i,@object # @_Z15matrixMultiply3PfS_i
.globl _Z15matrixMultiply3PfS_i
.p2align 3, 0x0
_Z15matrixMultiply3PfS_i:
.quad _Z30__device_stub__matrixMultiply3PfS_i
.size _Z15matrixMultiply3PfS_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "\nMismatch at index: ("
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ","
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz ")"
.size .L.str.5, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixMultiply1PfS_i"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15matrixMultiply2PfS_i"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15matrixMultiply3PfS_i"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixMultiply1PfS_i
.addrsig_sym _Z30__device_stub__matrixMultiply2PfS_i
.addrsig_sym _Z30__device_stub__matrixMultiply3PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym A
.addrsig_sym C
.addrsig_sym _Z15matrixMultiply1PfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _Z15matrixMultiply2PfS_i
.addrsig_sym _Z15matrixMultiply3PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018bff2_00000000-6_kumari_sangeeta_lab4p2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6init_Fv
.type _Z6init_Fv, @function
_Z6init_Fv:
.LFB3950:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 8192+A(%rip), %rbp
leaq -8192(%rbp), %r12
addq $16785408, %r12
.L4:
leaq -8192(%rbp), %rbx
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
addss .LC1(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8192, %rbp
cmpq %r12, %rbp
jne .L4
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3950:
.size _Z6init_Fv, .-_Z6init_Fv
.globl _Z6serialv
.type _Z6serialv, @function
_Z6serialv:
.LFB3951:
.cfi_startproc
endbr64
leaq A(%rip), %r10
leaq 16777216(%r10), %rcx
movl $0, %r9d
leaq F(%rip), %r11
.L10:
imulq $-8196, %r9, %rsi
addq %r11, %rsi
movq %r9, %rax
negq %rax
leaq (%r10,%rax,4), %r8
movq %r9, %rdx
leaq 2048(%r9), %rdi
.L14:
movss (%rsi,%rdx,4), %xmm1
movq %r8, %rax
.L11:
movss (%rax), %xmm0
mulss (%rax,%rdx,4), %xmm0
addss %xmm0, %xmm1
addq $8192, %rax
cmpq %rcx, %rax
jne .L11
movss %xmm1, (%rsi,%rdx,4)
addq $1, %rdx
cmpq %rdi, %rdx
jne .L14
subq $1, %r9
addq $4, %rcx
cmpq $-2048, %r9
jne .L10
ret
.cfi_endproc
.LFE3951:
.size _Z6serialv, .-_Z6serialv
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "\nMismatch at index: ("
.LC6:
.string ","
.LC7:
.string ")"
.text
.globl _Z5checkv
.type _Z5checkv, @function
_Z5checkv:
.LFB3952:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq C(%rip), %rdx
leaq F(%rip), %rax
movl $0, %r12d
movss .LC3(%rip), %xmm2
movsd .LC4(%rip), %xmm1
.L17:
movl $0, %ebx
.L24:
movss (%rdx,%rbx,4), %xmm0
subss (%rax,%rbx,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm0, %xmm1
ja .L30
addq $1, %rbx
cmpq $2048, %rbx
jne .L24
addl $1, %r12d
addq $8192, %rdx
addq $8192, %rax
cmpl $2048, %r12d
jne .L17
movl $1, %eax
jmp .L16
.L30:
movl $21, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L31
cmpb $0, 56(%rbp)
je .L21
movzbl 67(%rbp), %esi
.L22:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
.L16:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L21:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.cfi_endproc
.LFE3952:
.size _Z5checkv, .-_Z5checkv
.globl _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
.type _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i, @function
_Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i:
.LFB3977:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMultiply1PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i, .-_Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
.globl _Z15matrixMultiply1PfS_i
.type _Z15matrixMultiply1PfS_i, @function
_Z15matrixMultiply1PfS_i:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z15matrixMultiply1PfS_i, .-_Z15matrixMultiply1PfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "\nTime taken for Matrix Multiplication on GPU (time in sec): "
.align 8
.LC10:
.string "\nPerformance Metrics (GFlops/sec):"
.align 8
.LC13:
.string "\nMatrix Multiplication Successful!"
.text
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $112, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
call _Z6init_Fv
movl $1, %ecx
movl $16777216, %edx
leaq A(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
leaq C(%rip), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $64, 40(%rsp)
movl $64, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 52(%rsp)
movl $32, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq %rdi, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rdx)
movq (%rdi), %rax
movq -24(%rax), %rax
movq $7, 8(%rdi,%rax)
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq %rdi, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rdx)
movq (%rdi), %rax
movq -24(%rax), %rax
movq $6, 8(%rdi,%rax)
movsd 8(%rsp), %xmm1
mulsd .LC11(%rip), %xmm1
movsd .LC12(%rip), %xmm0
divsd %xmm1, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $16777216, %edx
movq 32(%rsp), %rsi
leaq C(%rip), %rdi
call cudaMemcpy@PLT
call _Z5checkv
cmpl $1, %eax
je .L46
.L42:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl $2048, %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z38__device_stub__Z15matrixMultiply1PfS_iPfS_i
jmp .L41
.L46:
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.globl _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
.type _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i, @function
_Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i:
.LFB3979:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMultiply2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3979:
.size _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i, .-_Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
.globl _Z15matrixMultiply2PfS_i
.type _Z15matrixMultiply2PfS_i, @function
_Z15matrixMultiply2PfS_i:
.LFB3980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15matrixMultiply2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _Z15matrixMultiply2PfS_i, .-_Z15matrixMultiply2PfS_i
.globl _Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i
.type _Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i, @function
_Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i:
.LFB3981:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixMultiply3PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3981:
.size _Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i, .-_Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i
.globl _Z15matrixMultiply3PfS_i
.type _Z15matrixMultiply3PfS_i, @function
_Z15matrixMultiply3PfS_i:
.LFB3982:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15matrixMultiply3PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3982:
.size _Z15matrixMultiply3PfS_i, .-_Z15matrixMultiply3PfS_i
.section .rodata.str1.1
.LC14:
.string "_Z15matrixMultiply3PfS_i"
.LC15:
.string "_Z15matrixMultiply2PfS_i"
.LC16:
.string "_Z15matrixMultiply1PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3984:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMultiply3PfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMultiply2PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMultiply1PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3984:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl C
.bss
.align 32
.type C, @object
.size C, 16777216
C:
.zero 16777216
.globl F
.align 32
.type F, @object
.size F, 16777216
F:
.zero 16777216
.globl A
.align 32
.type A, @object
.size A, 16777216
A:
.zero 16777216
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1065353216
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -1598689907
.long 1051772663
.align 8
.LC8:
.long 0
.long 1093567616
.align 8
.LC11:
.long 0
.long 1104006501
.align 8
.LC12:
.long 0
.long 1108344832
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kumari_sangeeta_lab4p2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_3:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI0_4:
.quad 0x4210000000000000 # double 17179869184
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $A, %r14d
.p2align 4, 0x90
.LBB0_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $2048, %r15 # imm = 0x800
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rbx
addq $8192, %r14 # imm = 0x2000
cmpq $2048, %rbx # imm = 0x800
jne .LBB0_1
# %bb.4: # %_Z6init_Fv.exit
movq 8(%rsp), %rdi
movl $A, %esi
movl $16777216, %edx # imm = 0x1000000
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $C, %esi
movl $16777216, %edx # imm = 0x1000000
movl $1, %ecx
callq hipMemcpy
leaq 128(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $2048, 20(%rsp) # imm = 0x800
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 20(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z15matrixMultiply1PfS_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 128(%rsp), %rax
subq 136(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
divsd .LCPI0_2(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $60, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movl $-261, %ebx # imm = 0xFEFB
movl _ZSt4cout+24(%rcx), %edx
andl %ebx, %edx
orl $4, %edx
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $7, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
andl _ZSt4cout+24(%rcx), %ebx
orl $4, %ebx
movl %ebx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $6, _ZSt4cout+8(%rax)
movsd 24(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI0_3(%rip), %xmm1
movsd .LCPI0_4(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_17
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB0_10
.LBB0_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rsi
movl $C, %edi
movl $16777216, %edx # imm = 0x1000000
movl $2, %ecx
callq hipMemcpy
callq _Z5checkv
cmpl $1, %eax
jne .LBB0_16
# %bb.11:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_17
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%rbx)
je .LBB0_14
# %bb.13:
movzbl 67(%rbx), %eax
jmp .LBB0_15
.LBB0_14:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB0_16:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_17:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6init_Fv
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x3f800000 # float 1
.text
.globl _Z6init_Fv
.p2align 4, 0x90
.type _Z6init_Fv,@function
_Z6init_Fv: # @_Z6init_Fv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $A, %r14d
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $2048, %r15 # imm = 0x800
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $8192, %r14 # imm = 0x2000
cmpq $2048, %rbx # imm = 0x800
jne .LBB1_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6init_Fv, .Lfunc_end1-_Z6init_Fv
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixMultiply1PfS_i # -- Begin function _Z30__device_stub__matrixMultiply1PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMultiply1PfS_i,@function
_Z30__device_stub__matrixMultiply1PfS_i: # @_Z30__device_stub__matrixMultiply1PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMultiply1PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__matrixMultiply1PfS_i, .Lfunc_end2-_Z30__device_stub__matrixMultiply1PfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z5checkv
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5checkv
.p2align 4, 0x90
.type _Z5checkv,@function
_Z5checkv: # @_Z5checkv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r12d, %r12d
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI3_1(%rip), %xmm2 # xmm2 = mem[0],zero
xorl %ebx, %ebx
xorl %r13d, %r13d
jmp .LBB3_1
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_1 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB3_1 Depth=1
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testb %bpl, %bpl
movaps .LCPI3_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI3_1(%rip), %xmm2 # xmm2 = mem[0],zero
je .LBB3_13
.LBB3_12: # %.critedge
# in Loop: Header=BB3_1 Depth=1
cmpq $2047, %rbx # imm = 0x7FF
leaq 1(%rbx), %rax
setae %r13b
addq $8192, %r12 # imm = 0x2000
movq %rax, %rbx
cmpq $2048, %rax # imm = 0x800
je .LBB3_13
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_11 Depth 2
movq %rbx, %rax
shlq $13, %rax
movss C(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss F(%rax), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm0, %xmm2
jbe .LBB3_10
# %bb.2: # in Loop: Header=BB3_1 Depth=1
xorl %r14d, %r14d
xorl %ebp, %ebp
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_10: # %.lr.ph.preheader
# in Loop: Header=BB3_1 Depth=1
movq $-1, %r14
.p2align 4, 0x90
.LBB3_11: # %.lr.ph
# Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq $2046, %r14 # imm = 0x7FE
je .LBB3_12
# %bb.3: # in Loop: Header=BB3_11 Depth=2
movss C+8(%r12,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss F+8(%r12,%r14,4), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
incq %r14
ucomisd %xmm0, %xmm2
jbe .LBB3_11
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_1 Depth=1
cmpq $2047, %r14 # imm = 0x7FF
setae %bpl
incq %r14
.LBB3_5: # in Loop: Header=BB3_1 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.4, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB3_14
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB3_1 Depth=1
cmpb $0, 56(%r15)
je .LBB3_8
# %bb.7: # in Loop: Header=BB3_1 Depth=1
movzbl 67(%r15), %eax
jmp .LBB3_9
.LBB3_13:
movzbl %r13b, %eax
andl $1, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_14:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z5checkv, .Lfunc_end3-_Z5checkv
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixMultiply2PfS_i # -- Begin function _Z30__device_stub__matrixMultiply2PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMultiply2PfS_i,@function
_Z30__device_stub__matrixMultiply2PfS_i: # @_Z30__device_stub__matrixMultiply2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMultiply2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z30__device_stub__matrixMultiply2PfS_i, .Lfunc_end4-_Z30__device_stub__matrixMultiply2PfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixMultiply3PfS_i # -- Begin function _Z30__device_stub__matrixMultiply3PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixMultiply3PfS_i,@function
_Z30__device_stub__matrixMultiply3PfS_i: # @_Z30__device_stub__matrixMultiply3PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixMultiply3PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z30__device_stub__matrixMultiply3PfS_i, .Lfunc_end5-_Z30__device_stub__matrixMultiply3PfS_i
.cfi_endproc
# -- End function
.globl _Z6serialv # -- Begin function _Z6serialv
.p2align 4, 0x90
.type _Z6serialv,@function
_Z6serialv: # @_Z6serialv
.cfi_startproc
# %bb.0:
movl $A, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_1: # %.preheader14
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
# Child Loop BB6_3 Depth 3
movq %rcx, %rdx
shlq $13, %rdx
movl $A, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB6_2: # %.preheader
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_3 Depth 3
leaq (%rdx,%rdi,4), %r8
addq $F, %r8
movss F(%rdx,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB6_3: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r9), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rsi,%r9), %xmm1
addss %xmm1, %xmm0
addq $8192, %r9 # imm = 0x2000
cmpq $16777216, %r9 # imm = 0x1000000
jne .LBB6_3
# %bb.4: # in Loop: Header=BB6_2 Depth=2
movss %xmm0, (%r8)
incq %rdi
addq $4, %rsi
cmpq $2048, %rdi # imm = 0x800
jne .LBB6_2
# %bb.5: # in Loop: Header=BB6_1 Depth=1
incq %rcx
addq $4, %rax
cmpq $2048, %rcx # imm = 0x800
jne .LBB6_1
# %bb.6:
retq
.Lfunc_end6:
.size _Z6serialv, .Lfunc_end6-_Z6serialv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMultiply1PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMultiply2PfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMultiply3PfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type A,@object # @A
.bss
.globl A
.p2align 4, 0x0
A:
.zero 16777216
.size A, 16777216
.type F,@object # @F
.globl F
.p2align 4, 0x0
F:
.zero 16777216
.size F, 16777216
.type C,@object # @C
.globl C
.p2align 4, 0x0
C:
.zero 16777216
.size C, 16777216
.type _Z15matrixMultiply1PfS_i,@object # @_Z15matrixMultiply1PfS_i
.section .rodata,"a",@progbits
.globl _Z15matrixMultiply1PfS_i
.p2align 3, 0x0
_Z15matrixMultiply1PfS_i:
.quad _Z30__device_stub__matrixMultiply1PfS_i
.size _Z15matrixMultiply1PfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nTime taken for Matrix Multiplication on GPU (time in sec): "
.size .L.str, 61
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nPerformance Metrics (GFlops/sec):"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nMatrix Multiplication Successful!"
.size .L.str.2, 35
.type _Z15matrixMultiply2PfS_i,@object # @_Z15matrixMultiply2PfS_i
.section .rodata,"a",@progbits
.globl _Z15matrixMultiply2PfS_i
.p2align 3, 0x0
_Z15matrixMultiply2PfS_i:
.quad _Z30__device_stub__matrixMultiply2PfS_i
.size _Z15matrixMultiply2PfS_i, 8
.type _Z15matrixMultiply3PfS_i,@object # @_Z15matrixMultiply3PfS_i
.globl _Z15matrixMultiply3PfS_i
.p2align 3, 0x0
_Z15matrixMultiply3PfS_i:
.quad _Z30__device_stub__matrixMultiply3PfS_i
.size _Z15matrixMultiply3PfS_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "\nMismatch at index: ("
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ","
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz ")"
.size .L.str.5, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixMultiply1PfS_i"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15matrixMultiply2PfS_i"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15matrixMultiply3PfS_i"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixMultiply1PfS_i
.addrsig_sym _Z30__device_stub__matrixMultiply2PfS_i
.addrsig_sym _Z30__device_stub__matrixMultiply3PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym A
.addrsig_sym C
.addrsig_sym _Z15matrixMultiply1PfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _Z15matrixMultiply2PfS_i
.addrsig_sym _Z15matrixMultiply3PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_update( float4* d_positions, float4* d_og_positions, float4* d_velocities, float* d_masses, size_t numel) {
size_t col = threadIdx.x + blockIdx.x * blockDim.x;
if (col >= numel) { return; }
float4 velocity = d_velocities[col];
float mag = sqrtf(velocity.x*velocity.x + velocity.y*velocity.y)*0.03;
float pos = min(mag, 0.50f);
d_positions[col] = make_float4(
d_og_positions[col].x,
d_og_positions[col].y,
pos, 0
);
__syncthreads();
} | code for sm_80
Function : _Z13kernel_updateP6float4S0_S0_Pfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ SHF.L.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027819 */
/* 0x000fe200000006ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ SHF.R.U32.HI R0, RZ, 0x1c, R0 ; /* 0x0000001cff007819 */
/* 0x000fe40000011600 */
/*00a0*/ IADD3 R4, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R5, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000057a10 */
/* 0x000fcc00007fe4ff */
/*00c0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ BSSY B0, 0x1e0 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*00e0*/ FMUL R3, R5, R5 ; /* 0x0000000505037220 */
/* 0x004fc80000400000 */
/*00f0*/ FFMA R3, R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x000fc80000000003 */
/*0100*/ MUFU.RSQ R6, R3 ; /* 0x0000000300067308 */
/* 0x0000620000001400 */
/*0110*/ IADD3 R7, R3, -0xd000000, RZ ; /* 0xf300000003077810 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ; /* 0x727fffff0700780c */
/* 0x000fda0003f04070 */
/*0130*/ @!P0 BRA 0x190 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0140*/ BSSY B1, 0x180 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0150*/ MOV R9, 0x170 ; /* 0x0000017000097802 */
/* 0x000fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x2d0 ; /* 0x0000016000007944 */
/* 0x000fea0003c00000 */
/*0170*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R8, R3, R6 ; /* 0x0000000603087220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R6, R6, 0.5 ; /* 0x3f00000006067820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R3, -R8, R8, R3 ; /* 0x0000000808037223 */
/* 0x000fc80000000103 */
/*01c0*/ FFMA R8, R3, R6, R8 ; /* 0x0000000603087223 */
/* 0x000fe40000000008 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R6, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002067a10 */
/* 0x000fc80007f1e0ff */
/*01f0*/ IADD3.X R7, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000077a10 */
/* 0x000fcc00007fe4ff */
/*0200*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0210*/ F2F.F64.F32 R4, R8 ; /* 0x0000000800047310 */
/* 0x000e220000201800 */
/*0220*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fe20007f1e0ff */
/*0230*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e00ff */
/*0240*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fe200007fe4ff */
/*0250*/ DMUL R4, R4, c[0x2][0x0] ; /* 0x0080000004047a28 */
/* 0x001e140000000000 */
/*0260*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */
/* 0x001e240000301000 */
/*0270*/ FMNMX R14, R4, 0.5, PT ; /* 0x3f000000040e7809 */
/* 0x001fe40003800000 */
/*0280*/ MOV R12, R6 ; /* 0x00000006000c7202 */
/* 0x004fe20000000f00 */
/*0290*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e0007 */
/*02a0*/ STG.E.128 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe8000c101d04 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*02e0*/ @!P0 MOV R4, R3 ; /* 0x0000000300048202 */
/* 0x000fe20000000f00 */
/*02f0*/ @!P0 BRA 0x400 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fda0003f1e000 */
/*0310*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff048424 */
/* 0x000fe200078e00ff */
/*0320*/ @!P0 BRA 0x400 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0330*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*0340*/ @P0 FADD.FTZ R4, R3, 1 ; /* 0x3f80000003040421 */
/* 0x000fe20000010000 */
/*0350*/ @P0 BRA 0x400 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0360*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1d200 */
/*0370*/ @P0 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003050823 */
/* 0x000fc800000000ff */
/*0380*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*0390*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*03a0*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe20000410000 */
/*03b0*/ @!P0 MOV R4, R3 ; /* 0x0000000300048202 */
/* 0x000fe20000000f00 */
/*03c0*/ @P0 FADD.FTZ R7, -R6, -RZ ; /* 0x800000ff06070221 */
/* 0x000fc80000010100 */
/*03d0*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*03e0*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*03f0*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*0400*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0410*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*0420*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0430*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffbc004007950 */
/* 0x000fea0003c3ffff */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_update( float4* d_positions, float4* d_og_positions, float4* d_velocities, float* d_masses, size_t numel) {
size_t col = threadIdx.x + blockIdx.x * blockDim.x;
if (col >= numel) { return; }
float4 velocity = d_velocities[col];
float mag = sqrtf(velocity.x*velocity.x + velocity.y*velocity.y)*0.03;
float pos = min(mag, 0.50f);
d_positions[col] = make_float4(
d_og_positions[col].x,
d_og_positions[col].y,
pos, 0
);
__syncthreads();
} | .file "tmpxft_00181d8f_00000000-6_kernel_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm
.type _Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm, @function
_Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13kernel_updateP6float4S0_S0_Pfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm, .-_Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm
.globl _Z13kernel_updateP6float4S0_S0_Pfm
.type _Z13kernel_updateP6float4S0_S0_Pfm, @function
_Z13kernel_updateP6float4S0_S0_Pfm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernel_updateP6float4S0_S0_Pfm, .-_Z13kernel_updateP6float4S0_S0_Pfm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13kernel_updateP6float4S0_S0_Pfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_updateP6float4S0_S0_Pfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_update( float4* d_positions, float4* d_og_positions, float4* d_velocities, float* d_masses, size_t numel) {
size_t col = threadIdx.x + blockIdx.x * blockDim.x;
if (col >= numel) { return; }
float4 velocity = d_velocities[col];
float mag = sqrtf(velocity.x*velocity.x + velocity.y*velocity.y)*0.03;
float pos = min(mag, 0.50f);
d_positions[col] = make_float4(
d_og_positions[col].x,
d_og_positions[col].y,
pos, 0
);
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_update( float4* d_positions, float4* d_og_positions, float4* d_velocities, float* d_masses, size_t numel) {
size_t col = threadIdx.x + blockIdx.x * blockDim.x;
if (col >= numel) { return; }
float4 velocity = d_velocities[col];
float mag = sqrtf(velocity.x*velocity.x + velocity.y*velocity.y)*0.03;
float pos = min(mag, 0.50f);
d_positions[col] = make_float4(
d_og_positions[col].x,
d_og_positions[col].y,
pos, 0
);
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_update( float4* d_positions, float4* d_og_positions, float4* d_velocities, float* d_masses, size_t numel) {
size_t col = threadIdx.x + blockIdx.x * blockDim.x;
if (col >= numel) { return; }
float4 velocity = d_velocities[col];
float mag = sqrtf(velocity.x*velocity.x + velocity.y*velocity.y)*0.03;
float pos = min(mag, 0.50f);
d_positions[col] = make_float4(
d_og_positions[col].x,
d_og_positions[col].y,
pos, 0
);
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.globl _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.p2align 8
.type _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm,@function
_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_mov_b32_e32 v3, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[4:5], 4, v[2:3]
s_mov_b32 s1, 0x3f9eb851
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
global_load_b64 v[6:7], v[0:1], off
v_add_co_u32 v0, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v6, v6
v_mul_f32_e32 v6, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_sqrt_f32_e32 v6, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, -1, v6
v_add_nc_u32_e32 v8, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v7, v6, v2
v_fma_f32 v10, -v8, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v9
v_cndmask_b32_e64 v6, v6, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v10
v_cndmask_b32_e64 v6, v6, v8, s0
s_mov_b32 s0, 0xeb851eb8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x37800000, v6
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v6, v2, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_cvt_f64_f32_e32 v[6:7], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[6:7], s[0:1]
v_cvt_f32_f64_e32 v2, v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_min_f32_e32 v2, 0.5, v2
s_waitcnt vmcnt(0)
global_store_b128 v[4:5], v[0:3], off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm, .Lfunc_end0-_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_update( float4* d_positions, float4* d_og_positions, float4* d_velocities, float* d_masses, size_t numel) {
size_t col = threadIdx.x + blockIdx.x * blockDim.x;
if (col >= numel) { return; }
float4 velocity = d_velocities[col];
float mag = sqrtf(velocity.x*velocity.x + velocity.y*velocity.y)*0.03;
float pos = min(mag, 0.50f);
d_positions[col] = make_float4(
d_og_positions[col].x,
d_og_positions[col].y,
pos, 0
);
__syncthreads();
} | .text
.file "kernel_update.hip"
.globl _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm # -- Begin function _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.p2align 4, 0x90
.type _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm,@function
_Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm: # @_Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm, .Lfunc_end0-_Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm,@object # @_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.section .rodata,"a",@progbits
.globl _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.p2align 3, 0x0
_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm:
.quad _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.size _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13kernel_updateP6float4S0_S0_Pfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ SHF.L.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027819 */
/* 0x000fe200000006ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ SHF.R.U32.HI R0, RZ, 0x1c, R0 ; /* 0x0000001cff007819 */
/* 0x000fe40000011600 */
/*00a0*/ IADD3 R4, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ IADD3.X R5, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000057a10 */
/* 0x000fcc00007fe4ff */
/*00c0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ BSSY B0, 0x1e0 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*00e0*/ FMUL R3, R5, R5 ; /* 0x0000000505037220 */
/* 0x004fc80000400000 */
/*00f0*/ FFMA R3, R4, R4, R3 ; /* 0x0000000404037223 */
/* 0x000fc80000000003 */
/*0100*/ MUFU.RSQ R6, R3 ; /* 0x0000000300067308 */
/* 0x0000620000001400 */
/*0110*/ IADD3 R7, R3, -0xd000000, RZ ; /* 0xf300000003077810 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GT.U32.AND P0, PT, R7, 0x727fffff, PT ; /* 0x727fffff0700780c */
/* 0x000fda0003f04070 */
/*0130*/ @!P0 BRA 0x190 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0140*/ BSSY B1, 0x180 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0150*/ MOV R9, 0x170 ; /* 0x0000017000097802 */
/* 0x000fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x2d0 ; /* 0x0000016000007944 */
/* 0x000fea0003c00000 */
/*0170*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x1d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0190*/ FMUL.FTZ R8, R3, R6 ; /* 0x0000000603087220 */
/* 0x003fe40000410000 */
/*01a0*/ FMUL.FTZ R6, R6, 0.5 ; /* 0x3f00000006067820 */
/* 0x000fe40000410000 */
/*01b0*/ FFMA R3, -R8, R8, R3 ; /* 0x0000000808037223 */
/* 0x000fc80000000103 */
/*01c0*/ FFMA R8, R3, R6, R8 ; /* 0x0000000603087223 */
/* 0x000fe40000000008 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R6, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002067a10 */
/* 0x000fc80007f1e0ff */
/*01f0*/ IADD3.X R7, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000077a10 */
/* 0x000fcc00007fe4ff */
/*0200*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0210*/ F2F.F64.F32 R4, R8 ; /* 0x0000000800047310 */
/* 0x000e220000201800 */
/*0220*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fe20007f1e0ff */
/*0230*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e00ff */
/*0240*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fe200007fe4ff */
/*0250*/ DMUL R4, R4, c[0x2][0x0] ; /* 0x0080000004047a28 */
/* 0x001e140000000000 */
/*0260*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */
/* 0x001e240000301000 */
/*0270*/ FMNMX R14, R4, 0.5, PT ; /* 0x3f000000040e7809 */
/* 0x001fe40003800000 */
/*0280*/ MOV R12, R6 ; /* 0x00000006000c7202 */
/* 0x004fe20000000f00 */
/*0290*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e0007 */
/*02a0*/ STG.E.128 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe8000c101d04 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*02e0*/ @!P0 MOV R4, R3 ; /* 0x0000000300048202 */
/* 0x000fe20000000f00 */
/*02f0*/ @!P0 BRA 0x400 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fda0003f1e000 */
/*0310*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff048424 */
/* 0x000fe200078e00ff */
/*0320*/ @!P0 BRA 0x400 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0330*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*0340*/ @P0 FADD.FTZ R4, R3, 1 ; /* 0x3f80000003040421 */
/* 0x000fe20000010000 */
/*0350*/ @P0 BRA 0x400 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0360*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1d200 */
/*0370*/ @P0 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003050823 */
/* 0x000fc800000000ff */
/*0380*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*0390*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*03a0*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe20000410000 */
/*03b0*/ @!P0 MOV R4, R3 ; /* 0x0000000300048202 */
/* 0x000fe20000000f00 */
/*03c0*/ @P0 FADD.FTZ R7, -R6, -RZ ; /* 0x800000ff06070221 */
/* 0x000fc80000010100 */
/*03d0*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*03e0*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*03f0*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*0400*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0410*/ MOV R4, R9 ; /* 0x0000000900047202 */
/* 0x000fe20000000f00 */
/*0420*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0430*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffbc004007950 */
/* 0x000fea0003c3ffff */
/*0440*/ BRA 0x440; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.globl _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.p2align 8
.type _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm,@function
_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_mov_b32_e32 v3, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[4:5], 4, v[2:3]
s_mov_b32 s1, 0x3f9eb851
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
global_load_b64 v[6:7], v[0:1], off
v_add_co_u32 v0, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v6, v6
v_mul_f32_e32 v6, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_sqrt_f32_e32 v6, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, -1, v6
v_add_nc_u32_e32 v8, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v7, v6, v2
v_fma_f32 v10, -v8, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v9
v_cndmask_b32_e64 v6, v6, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v10
v_cndmask_b32_e64 v6, v6, v8, s0
s_mov_b32 s0, 0xeb851eb8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x37800000, v6
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v6, v2, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_cvt_f64_f32_e32 v[6:7], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[6:7], s[0:1]
v_cvt_f32_f64_e32 v2, v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_min_f32_e32 v2, 0.5, v2
s_waitcnt vmcnt(0)
global_store_b128 v[4:5], v[0:3], off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm, .Lfunc_end0-_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00181d8f_00000000-6_kernel_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm
.type _Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm, @function
_Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13kernel_updateP6float4S0_S0_Pfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm, .-_Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm
.globl _Z13kernel_updateP6float4S0_S0_Pfm
.type _Z13kernel_updateP6float4S0_S0_Pfm, @function
_Z13kernel_updateP6float4S0_S0_Pfm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z13kernel_updateP6float4S0_S0_PfmP6float4S0_S0_Pfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernel_updateP6float4S0_S0_Pfm, .-_Z13kernel_updateP6float4S0_S0_Pfm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13kernel_updateP6float4S0_S0_Pfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_updateP6float4S0_S0_Pfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_update.hip"
.globl _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm # -- Begin function _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.p2align 4, 0x90
.type _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm,@function
_Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm: # @_Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm, .Lfunc_end0-_Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm,@object # @_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.section .rodata,"a",@progbits
.globl _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.p2align 3, 0x0
_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm:
.quad _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.size _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernel_updateP15HIP_vector_typeIfLj4EES1_S1_Pfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define NOMINMAX
const unsigned int BLOCK_SIZE = 512;
__global__ void addKernelV2(float *c, const float *a, const float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] + b[i];
} | code for sm_80
Function : _Z11addKernelV2PfPKfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define NOMINMAX
const unsigned int BLOCK_SIZE = 512;
__global__ void addKernelV2(float *c, const float *a, const float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] + b[i];
} | .file "tmpxft_00148725_00000000-6_addKernelV2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_
.type _Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_, @function
_Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11addKernelV2PfPKfS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_, .-_Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_
.globl _Z11addKernelV2PfPKfS1_
.type _Z11addKernelV2PfPKfS1_, @function
_Z11addKernelV2PfPKfS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11addKernelV2PfPKfS1_, .-_Z11addKernelV2PfPKfS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11addKernelV2PfPKfS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11addKernelV2PfPKfS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define NOMINMAX
const unsigned int BLOCK_SIZE = 512;
__global__ void addKernelV2(float *c, const float *a, const float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] + b[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define NOMINMAX
const unsigned int BLOCK_SIZE = 512;
__global__ void addKernelV2(float *c, const float *a, const float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] + b[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NOMINMAX
const unsigned int BLOCK_SIZE = 512;
__global__ void addKernelV2(float *c, const float *a, const float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] + b[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11addKernelV2PfPKfS1_
.globl _Z11addKernelV2PfPKfS1_
.p2align 8
.type _Z11addKernelV2PfPKfS1_,@function
_Z11addKernelV2PfPKfS1_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11addKernelV2PfPKfS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11addKernelV2PfPKfS1_, .Lfunc_end0-_Z11addKernelV2PfPKfS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11addKernelV2PfPKfS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11addKernelV2PfPKfS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NOMINMAX
const unsigned int BLOCK_SIZE = 512;
__global__ void addKernelV2(float *c, const float *a, const float *b)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
c[i] = a[i] + b[i];
} | .text
.file "addKernelV2.hip"
.globl _Z26__device_stub__addKernelV2PfPKfS1_ # -- Begin function _Z26__device_stub__addKernelV2PfPKfS1_
.p2align 4, 0x90
.type _Z26__device_stub__addKernelV2PfPKfS1_,@function
_Z26__device_stub__addKernelV2PfPKfS1_: # @_Z26__device_stub__addKernelV2PfPKfS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11addKernelV2PfPKfS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__addKernelV2PfPKfS1_, .Lfunc_end0-_Z26__device_stub__addKernelV2PfPKfS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11addKernelV2PfPKfS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11addKernelV2PfPKfS1_,@object # @_Z11addKernelV2PfPKfS1_
.section .rodata,"a",@progbits
.globl _Z11addKernelV2PfPKfS1_
.p2align 3, 0x0
_Z11addKernelV2PfPKfS1_:
.quad _Z26__device_stub__addKernelV2PfPKfS1_
.size _Z11addKernelV2PfPKfS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11addKernelV2PfPKfS1_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__addKernelV2PfPKfS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11addKernelV2PfPKfS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11addKernelV2PfPKfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11addKernelV2PfPKfS1_
.globl _Z11addKernelV2PfPKfS1_
.p2align 8
.type _Z11addKernelV2PfPKfS1_,@function
_Z11addKernelV2PfPKfS1_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11addKernelV2PfPKfS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11addKernelV2PfPKfS1_, .Lfunc_end0-_Z11addKernelV2PfPKfS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11addKernelV2PfPKfS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11addKernelV2PfPKfS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00148725_00000000-6_addKernelV2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_
.type _Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_, @function
_Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11addKernelV2PfPKfS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_, .-_Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_
.globl _Z11addKernelV2PfPKfS1_
.type _Z11addKernelV2PfPKfS1_, @function
_Z11addKernelV2PfPKfS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11addKernelV2PfPKfS1_PfPKfS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11addKernelV2PfPKfS1_, .-_Z11addKernelV2PfPKfS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11addKernelV2PfPKfS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11addKernelV2PfPKfS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addKernelV2.hip"
.globl _Z26__device_stub__addKernelV2PfPKfS1_ # -- Begin function _Z26__device_stub__addKernelV2PfPKfS1_
.p2align 4, 0x90
.type _Z26__device_stub__addKernelV2PfPKfS1_,@function
_Z26__device_stub__addKernelV2PfPKfS1_: # @_Z26__device_stub__addKernelV2PfPKfS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11addKernelV2PfPKfS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__addKernelV2PfPKfS1_, .Lfunc_end0-_Z26__device_stub__addKernelV2PfPKfS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11addKernelV2PfPKfS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11addKernelV2PfPKfS1_,@object # @_Z11addKernelV2PfPKfS1_
.section .rodata,"a",@progbits
.globl _Z11addKernelV2PfPKfS1_
.p2align 3, 0x0
_Z11addKernelV2PfPKfS1_:
.quad _Z26__device_stub__addKernelV2PfPKfS1_
.size _Z11addKernelV2PfPKfS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11addKernelV2PfPKfS1_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__addKernelV2PfPKfS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11addKernelV2PfPKfS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //=======================================================================================================
// Copyright 2015 Asgeir Bjorgan, Lise Lyngsnes Randeberg, Norwegian University of Science and Technology
// Distributed under the MIT License.
// (See accompanying file LICENSE or copy at
// http://opensource.org/licenses/MIT)
//=======================================================================================================
///SCA KIS
#define NUM_ITERATIONS 600
#define METHB_TRESH 1
//implementation of SCA using shared memory
template<int MAX_ENDMEMBERS, int MAX_BLOCKDIM>
__global__ void SCA(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
__shared__ float sh_x[MAX_ENDMEMBERS][MAX_BLOCKDIM];
__shared__ float sh_mu[MAX_ENDMEMBERS][MAX_BLOCKDIM];
//if (blockIdx.x == 5){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
for (int i=0; i < numEndmembers; i++){
float temp = 0;
for (int j=0; j < numBands; j++){
__shared__ float currAT;
if (threadIdx.x == 0){
currAT = AT[i*numBands + j];
}
__syncthreads();
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];
temp += currAT*inp;
}
float xstart = 0;
float mustart = -1*temp;
sh_x[i][threadIdx.x] = xstart;
sh_mu[i][threadIdx.x] = mustart;
}
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
for (int j=0; j < numEndmembers; j++){
float xprev;
float muprev;
//extract previous values
xprev = sh_x[j][threadIdx.x];
muprev = sh_mu[j][threadIdx.x];
//calculate new value
float temp = xprev - fdividef(muprev, sh_H[j][j]);
temp = (temp > 0)*temp;
//save new value to x
sh_x[j][threadIdx.x] = temp;
//calculate new mu
for (int k=0; k < numEndmembers; k++){
float addition = (temp - xprev)*sh_H[k][j];
sh_mu[k][threadIdx.x] += addition;
}
}
}
for (int i=0; i < numEndmembers; i++){
float val;
val = sh_x[i][threadIdx.x];
x[pixind + i*gridDim.x*pitch] = val;
}
}
//implementation using registers
//YOLO
#define ATmultMua(Arg) i=Arg;\
temp = 0;\
for (int j=0; j < numBands; j++){\
__shared__ float currAT;\
if (threadIdx.x == 0){\
currAT = AT[i*numBands + j];\
}\
__syncthreads();\
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];\
temp += currAT*inp;\
}\
x##Arg = 0;\
/*temp = ((i != currMethbind) || (hasMethb))*(temp);*/\
mu##Arg = -1*temp
/*mu_sh[Arg][threadIdx.x] = -1*temp*/
#define CalcX(Arg) j=Arg;\
xprev = x##Arg;\
muprev = mu##Arg;\
/*muprev = mu_sh[Arg][threadIdx.x];*/\
temp = xprev - fdividef(muprev, sh_H[j][j]);\
temp = (temp > 0)*temp;\
x##Arg = temp
#define CalcMu(Arg) k=Arg;\
addition = (temp - xprev)*sh_H[k][j];\
mu##Arg += addition
/*mu_sh[Arg][threadIdx.x] += addition*/
#define updateMu CalcMu(0);\
CalcMu(1);\
if (MAX_ENDMEMBERS >= 3)\
CalcMu(2);\
if (MAX_ENDMEMBERS >= 4)\
CalcMu(3);\
if (MAX_ENDMEMBERS >= 5)\
CalcMu(4);\
if (MAX_ENDMEMBERS >= 6)\
CalcMu(5);\
if (MAX_ENDMEMBERS >= 7)\
CalcMu(6)
//se opp for makrohelvete, dette ble skrevet for å se om det ble noe raskere om jeg brukte av registrene istedet for shared memory men DESSVERRE var det ikke mulig å opprette arrays i registrene uten like mye kuk som dette. ISRA-artikkelen lyver.
template<int MAX_ENDMEMBERS>
__global__ void SCAFast(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
float temp;
float x0, x1, x2, x3, x4, x5, x6;
float mu0, mu1, mu2, mu3, mu4, mu5, mu6;
int i;
//calculate initial coordinates
ATmultMua(0);
ATmultMua(1);
if (MAX_ENDMEMBERS >= 3)
ATmultMua(2);
if (MAX_ENDMEMBERS >= 4)
ATmultMua(3);
if (MAX_ENDMEMBERS >= 5)
ATmultMua(4);
if (MAX_ENDMEMBERS >= 6)
ATmultMua(5);
if (MAX_ENDMEMBERS >= 7)
ATmultMua(6);
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
float xprev, muprev, temp, addition;
int k,j;
CalcX(0);
updateMu;
CalcX(1);
updateMu;
if (MAX_ENDMEMBERS >= 3){
CalcX(2);
updateMu;
}
if (MAX_ENDMEMBERS >= 4){
CalcX(3);
updateMu;
}
if (MAX_ENDMEMBERS >= 5){
CalcX(4);
updateMu;
}
if (MAX_ENDMEMBERS >= 6){
CalcX(5);
updateMu;
}
if (MAX_ENDMEMBERS >= 7){
CalcX(6);
updateMu;
}
}
x[pixind + 0*gridDim.x*pitch] = x0;
x[pixind + 1*gridDim.x*pitch] = x1;
if (MAX_ENDMEMBERS >= 3)
x[pixind + 2*gridDim.x*pitch] = x2;
if (MAX_ENDMEMBERS >= 4)
x[pixind + 3*gridDim.x*pitch] = x3;
if (MAX_ENDMEMBERS >= 5)
x[pixind + 4*gridDim.x*pitch] = x4;
if (MAX_ENDMEMBERS >= 6)
x[pixind + 5*gridDim.x*pitch] = x5;
if (MAX_ENDMEMBERS >= 7)
x[pixind + 6*gridDim.x*pitch] = x6;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //=======================================================================================================
// Copyright 2015 Asgeir Bjorgan, Lise Lyngsnes Randeberg, Norwegian University of Science and Technology
// Distributed under the MIT License.
// (See accompanying file LICENSE or copy at
// http://opensource.org/licenses/MIT)
//=======================================================================================================
///SCA KIS
#define NUM_ITERATIONS 600
#define METHB_TRESH 1
//implementation of SCA using shared memory
template<int MAX_ENDMEMBERS, int MAX_BLOCKDIM>
__global__ void SCA(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
__shared__ float sh_x[MAX_ENDMEMBERS][MAX_BLOCKDIM];
__shared__ float sh_mu[MAX_ENDMEMBERS][MAX_BLOCKDIM];
//if (blockIdx.x == 5){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
for (int i=0; i < numEndmembers; i++){
float temp = 0;
for (int j=0; j < numBands; j++){
__shared__ float currAT;
if (threadIdx.x == 0){
currAT = AT[i*numBands + j];
}
__syncthreads();
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];
temp += currAT*inp;
}
float xstart = 0;
float mustart = -1*temp;
sh_x[i][threadIdx.x] = xstart;
sh_mu[i][threadIdx.x] = mustart;
}
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
for (int j=0; j < numEndmembers; j++){
float xprev;
float muprev;
//extract previous values
xprev = sh_x[j][threadIdx.x];
muprev = sh_mu[j][threadIdx.x];
//calculate new value
float temp = xprev - fdividef(muprev, sh_H[j][j]);
temp = (temp > 0)*temp;
//save new value to x
sh_x[j][threadIdx.x] = temp;
//calculate new mu
for (int k=0; k < numEndmembers; k++){
float addition = (temp - xprev)*sh_H[k][j];
sh_mu[k][threadIdx.x] += addition;
}
}
}
for (int i=0; i < numEndmembers; i++){
float val;
val = sh_x[i][threadIdx.x];
x[pixind + i*gridDim.x*pitch] = val;
}
}
//implementation using registers
//YOLO
#define ATmultMua(Arg) i=Arg;\
temp = 0;\
for (int j=0; j < numBands; j++){\
__shared__ float currAT;\
if (threadIdx.x == 0){\
currAT = AT[i*numBands + j];\
}\
__syncthreads();\
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];\
temp += currAT*inp;\
}\
x##Arg = 0;\
/*temp = ((i != currMethbind) || (hasMethb))*(temp);*/\
mu##Arg = -1*temp
/*mu_sh[Arg][threadIdx.x] = -1*temp*/
#define CalcX(Arg) j=Arg;\
xprev = x##Arg;\
muprev = mu##Arg;\
/*muprev = mu_sh[Arg][threadIdx.x];*/\
temp = xprev - fdividef(muprev, sh_H[j][j]);\
temp = (temp > 0)*temp;\
x##Arg = temp
#define CalcMu(Arg) k=Arg;\
addition = (temp - xprev)*sh_H[k][j];\
mu##Arg += addition
/*mu_sh[Arg][threadIdx.x] += addition*/
#define updateMu CalcMu(0);\
CalcMu(1);\
if (MAX_ENDMEMBERS >= 3)\
CalcMu(2);\
if (MAX_ENDMEMBERS >= 4)\
CalcMu(3);\
if (MAX_ENDMEMBERS >= 5)\
CalcMu(4);\
if (MAX_ENDMEMBERS >= 6)\
CalcMu(5);\
if (MAX_ENDMEMBERS >= 7)\
CalcMu(6)
//se opp for makrohelvete, dette ble skrevet for å se om det ble noe raskere om jeg brukte av registrene istedet for shared memory men DESSVERRE var det ikke mulig å opprette arrays i registrene uten like mye kuk som dette. ISRA-artikkelen lyver.
template<int MAX_ENDMEMBERS>
__global__ void SCAFast(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
float temp;
float x0, x1, x2, x3, x4, x5, x6;
float mu0, mu1, mu2, mu3, mu4, mu5, mu6;
int i;
//calculate initial coordinates
ATmultMua(0);
ATmultMua(1);
if (MAX_ENDMEMBERS >= 3)
ATmultMua(2);
if (MAX_ENDMEMBERS >= 4)
ATmultMua(3);
if (MAX_ENDMEMBERS >= 5)
ATmultMua(4);
if (MAX_ENDMEMBERS >= 6)
ATmultMua(5);
if (MAX_ENDMEMBERS >= 7)
ATmultMua(6);
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
float xprev, muprev, temp, addition;
int k,j;
CalcX(0);
updateMu;
CalcX(1);
updateMu;
if (MAX_ENDMEMBERS >= 3){
CalcX(2);
updateMu;
}
if (MAX_ENDMEMBERS >= 4){
CalcX(3);
updateMu;
}
if (MAX_ENDMEMBERS >= 5){
CalcX(4);
updateMu;
}
if (MAX_ENDMEMBERS >= 6){
CalcX(5);
updateMu;
}
if (MAX_ENDMEMBERS >= 7){
CalcX(6);
updateMu;
}
}
x[pixind + 0*gridDim.x*pitch] = x0;
x[pixind + 1*gridDim.x*pitch] = x1;
if (MAX_ENDMEMBERS >= 3)
x[pixind + 2*gridDim.x*pitch] = x2;
if (MAX_ENDMEMBERS >= 4)
x[pixind + 3*gridDim.x*pitch] = x3;
if (MAX_ENDMEMBERS >= 5)
x[pixind + 4*gridDim.x*pitch] = x4;
if (MAX_ENDMEMBERS >= 6)
x[pixind + 5*gridDim.x*pitch] = x5;
if (MAX_ENDMEMBERS >= 7)
x[pixind + 6*gridDim.x*pitch] = x6;
} | .file "tmpxft_000ca435_00000000-6_sca.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //=======================================================================================================
// Copyright 2015 Asgeir Bjorgan, Lise Lyngsnes Randeberg, Norwegian University of Science and Technology
// Distributed under the MIT License.
// (See accompanying file LICENSE or copy at
// http://opensource.org/licenses/MIT)
//=======================================================================================================
///SCA KIS
#define NUM_ITERATIONS 600
#define METHB_TRESH 1
//implementation of SCA using shared memory
template<int MAX_ENDMEMBERS, int MAX_BLOCKDIM>
__global__ void SCA(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
__shared__ float sh_x[MAX_ENDMEMBERS][MAX_BLOCKDIM];
__shared__ float sh_mu[MAX_ENDMEMBERS][MAX_BLOCKDIM];
//if (blockIdx.x == 5){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
for (int i=0; i < numEndmembers; i++){
float temp = 0;
for (int j=0; j < numBands; j++){
__shared__ float currAT;
if (threadIdx.x == 0){
currAT = AT[i*numBands + j];
}
__syncthreads();
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];
temp += currAT*inp;
}
float xstart = 0;
float mustart = -1*temp;
sh_x[i][threadIdx.x] = xstart;
sh_mu[i][threadIdx.x] = mustart;
}
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
for (int j=0; j < numEndmembers; j++){
float xprev;
float muprev;
//extract previous values
xprev = sh_x[j][threadIdx.x];
muprev = sh_mu[j][threadIdx.x];
//calculate new value
float temp = xprev - fdividef(muprev, sh_H[j][j]);
temp = (temp > 0)*temp;
//save new value to x
sh_x[j][threadIdx.x] = temp;
//calculate new mu
for (int k=0; k < numEndmembers; k++){
float addition = (temp - xprev)*sh_H[k][j];
sh_mu[k][threadIdx.x] += addition;
}
}
}
for (int i=0; i < numEndmembers; i++){
float val;
val = sh_x[i][threadIdx.x];
x[pixind + i*gridDim.x*pitch] = val;
}
}
//implementation using registers
//YOLO
#define ATmultMua(Arg) i=Arg;\
temp = 0;\
for (int j=0; j < numBands; j++){\
__shared__ float currAT;\
if (threadIdx.x == 0){\
currAT = AT[i*numBands + j];\
}\
__syncthreads();\
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];\
temp += currAT*inp;\
}\
x##Arg = 0;\
/*temp = ((i != currMethbind) || (hasMethb))*(temp);*/\
mu##Arg = -1*temp
/*mu_sh[Arg][threadIdx.x] = -1*temp*/
#define CalcX(Arg) j=Arg;\
xprev = x##Arg;\
muprev = mu##Arg;\
/*muprev = mu_sh[Arg][threadIdx.x];*/\
temp = xprev - fdividef(muprev, sh_H[j][j]);\
temp = (temp > 0)*temp;\
x##Arg = temp
#define CalcMu(Arg) k=Arg;\
addition = (temp - xprev)*sh_H[k][j];\
mu##Arg += addition
/*mu_sh[Arg][threadIdx.x] += addition*/
#define updateMu CalcMu(0);\
CalcMu(1);\
if (MAX_ENDMEMBERS >= 3)\
CalcMu(2);\
if (MAX_ENDMEMBERS >= 4)\
CalcMu(3);\
if (MAX_ENDMEMBERS >= 5)\
CalcMu(4);\
if (MAX_ENDMEMBERS >= 6)\
CalcMu(5);\
if (MAX_ENDMEMBERS >= 7)\
CalcMu(6)
//se opp for makrohelvete, dette ble skrevet for å se om det ble noe raskere om jeg brukte av registrene istedet for shared memory men DESSVERRE var det ikke mulig å opprette arrays i registrene uten like mye kuk som dette. ISRA-artikkelen lyver.
template<int MAX_ENDMEMBERS>
__global__ void SCAFast(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
float temp;
float x0, x1, x2, x3, x4, x5, x6;
float mu0, mu1, mu2, mu3, mu4, mu5, mu6;
int i;
//calculate initial coordinates
ATmultMua(0);
ATmultMua(1);
if (MAX_ENDMEMBERS >= 3)
ATmultMua(2);
if (MAX_ENDMEMBERS >= 4)
ATmultMua(3);
if (MAX_ENDMEMBERS >= 5)
ATmultMua(4);
if (MAX_ENDMEMBERS >= 6)
ATmultMua(5);
if (MAX_ENDMEMBERS >= 7)
ATmultMua(6);
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
float xprev, muprev, temp, addition;
int k,j;
CalcX(0);
updateMu;
CalcX(1);
updateMu;
if (MAX_ENDMEMBERS >= 3){
CalcX(2);
updateMu;
}
if (MAX_ENDMEMBERS >= 4){
CalcX(3);
updateMu;
}
if (MAX_ENDMEMBERS >= 5){
CalcX(4);
updateMu;
}
if (MAX_ENDMEMBERS >= 6){
CalcX(5);
updateMu;
}
if (MAX_ENDMEMBERS >= 7){
CalcX(6);
updateMu;
}
}
x[pixind + 0*gridDim.x*pitch] = x0;
x[pixind + 1*gridDim.x*pitch] = x1;
if (MAX_ENDMEMBERS >= 3)
x[pixind + 2*gridDim.x*pitch] = x2;
if (MAX_ENDMEMBERS >= 4)
x[pixind + 3*gridDim.x*pitch] = x3;
if (MAX_ENDMEMBERS >= 5)
x[pixind + 4*gridDim.x*pitch] = x4;
if (MAX_ENDMEMBERS >= 6)
x[pixind + 5*gridDim.x*pitch] = x5;
if (MAX_ENDMEMBERS >= 7)
x[pixind + 6*gridDim.x*pitch] = x6;
} | #include <hip/hip_runtime.h>
//=======================================================================================================
// Copyright 2015 Asgeir Bjorgan, Lise Lyngsnes Randeberg, Norwegian University of Science and Technology
// Distributed under the MIT License.
// (See accompanying file LICENSE or copy at
// http://opensource.org/licenses/MIT)
//=======================================================================================================
///SCA KIS
#define NUM_ITERATIONS 600
#define METHB_TRESH 1
//implementation of SCA using shared memory
template<int MAX_ENDMEMBERS, int MAX_BLOCKDIM>
__global__ void SCA(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
__shared__ float sh_x[MAX_ENDMEMBERS][MAX_BLOCKDIM];
__shared__ float sh_mu[MAX_ENDMEMBERS][MAX_BLOCKDIM];
//if (blockIdx.x == 5){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
for (int i=0; i < numEndmembers; i++){
float temp = 0;
for (int j=0; j < numBands; j++){
__shared__ float currAT;
if (threadIdx.x == 0){
currAT = AT[i*numBands + j];
}
__syncthreads();
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];
temp += currAT*inp;
}
float xstart = 0;
float mustart = -1*temp;
sh_x[i][threadIdx.x] = xstart;
sh_mu[i][threadIdx.x] = mustart;
}
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
for (int j=0; j < numEndmembers; j++){
float xprev;
float muprev;
//extract previous values
xprev = sh_x[j][threadIdx.x];
muprev = sh_mu[j][threadIdx.x];
//calculate new value
float temp = xprev - fdividef(muprev, sh_H[j][j]);
temp = (temp > 0)*temp;
//save new value to x
sh_x[j][threadIdx.x] = temp;
//calculate new mu
for (int k=0; k < numEndmembers; k++){
float addition = (temp - xprev)*sh_H[k][j];
sh_mu[k][threadIdx.x] += addition;
}
}
}
for (int i=0; i < numEndmembers; i++){
float val;
val = sh_x[i][threadIdx.x];
x[pixind + i*gridDim.x*pitch] = val;
}
}
//implementation using registers
//YOLO
#define ATmultMua(Arg) i=Arg;\
temp = 0;\
for (int j=0; j < numBands; j++){\
__shared__ float currAT;\
if (threadIdx.x == 0){\
currAT = AT[i*numBands + j];\
}\
__syncthreads();\
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];\
temp += currAT*inp;\
}\
x##Arg = 0;\
/*temp = ((i != currMethbind) || (hasMethb))*(temp);*/\
mu##Arg = -1*temp
/*mu_sh[Arg][threadIdx.x] = -1*temp*/
#define CalcX(Arg) j=Arg;\
xprev = x##Arg;\
muprev = mu##Arg;\
/*muprev = mu_sh[Arg][threadIdx.x];*/\
temp = xprev - fdividef(muprev, sh_H[j][j]);\
temp = (temp > 0)*temp;\
x##Arg = temp
#define CalcMu(Arg) k=Arg;\
addition = (temp - xprev)*sh_H[k][j];\
mu##Arg += addition
/*mu_sh[Arg][threadIdx.x] += addition*/
#define updateMu CalcMu(0);\
CalcMu(1);\
if (MAX_ENDMEMBERS >= 3)\
CalcMu(2);\
if (MAX_ENDMEMBERS >= 4)\
CalcMu(3);\
if (MAX_ENDMEMBERS >= 5)\
CalcMu(4);\
if (MAX_ENDMEMBERS >= 6)\
CalcMu(5);\
if (MAX_ENDMEMBERS >= 7)\
CalcMu(6)
//se opp for makrohelvete, dette ble skrevet for å se om det ble noe raskere om jeg brukte av registrene istedet for shared memory men DESSVERRE var det ikke mulig å opprette arrays i registrene uten like mye kuk som dette. ISRA-artikkelen lyver.
template<int MAX_ENDMEMBERS>
__global__ void SCAFast(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
float temp;
float x0, x1, x2, x3, x4, x5, x6;
float mu0, mu1, mu2, mu3, mu4, mu5, mu6;
int i;
//calculate initial coordinates
ATmultMua(0);
ATmultMua(1);
if (MAX_ENDMEMBERS >= 3)
ATmultMua(2);
if (MAX_ENDMEMBERS >= 4)
ATmultMua(3);
if (MAX_ENDMEMBERS >= 5)
ATmultMua(4);
if (MAX_ENDMEMBERS >= 6)
ATmultMua(5);
if (MAX_ENDMEMBERS >= 7)
ATmultMua(6);
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
float xprev, muprev, temp, addition;
int k,j;
CalcX(0);
updateMu;
CalcX(1);
updateMu;
if (MAX_ENDMEMBERS >= 3){
CalcX(2);
updateMu;
}
if (MAX_ENDMEMBERS >= 4){
CalcX(3);
updateMu;
}
if (MAX_ENDMEMBERS >= 5){
CalcX(4);
updateMu;
}
if (MAX_ENDMEMBERS >= 6){
CalcX(5);
updateMu;
}
if (MAX_ENDMEMBERS >= 7){
CalcX(6);
updateMu;
}
}
x[pixind + 0*gridDim.x*pitch] = x0;
x[pixind + 1*gridDim.x*pitch] = x1;
if (MAX_ENDMEMBERS >= 3)
x[pixind + 2*gridDim.x*pitch] = x2;
if (MAX_ENDMEMBERS >= 4)
x[pixind + 3*gridDim.x*pitch] = x3;
if (MAX_ENDMEMBERS >= 5)
x[pixind + 4*gridDim.x*pitch] = x4;
if (MAX_ENDMEMBERS >= 6)
x[pixind + 5*gridDim.x*pitch] = x5;
if (MAX_ENDMEMBERS >= 7)
x[pixind + 6*gridDim.x*pitch] = x6;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//=======================================================================================================
// Copyright 2015 Asgeir Bjorgan, Lise Lyngsnes Randeberg, Norwegian University of Science and Technology
// Distributed under the MIT License.
// (See accompanying file LICENSE or copy at
// http://opensource.org/licenses/MIT)
//=======================================================================================================
///SCA KIS
#define NUM_ITERATIONS 600
#define METHB_TRESH 1
//implementation of SCA using shared memory
template<int MAX_ENDMEMBERS, int MAX_BLOCKDIM>
__global__ void SCA(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
__shared__ float sh_x[MAX_ENDMEMBERS][MAX_BLOCKDIM];
__shared__ float sh_mu[MAX_ENDMEMBERS][MAX_BLOCKDIM];
//if (blockIdx.x == 5){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
for (int i=0; i < numEndmembers; i++){
float temp = 0;
for (int j=0; j < numBands; j++){
__shared__ float currAT;
if (threadIdx.x == 0){
currAT = AT[i*numBands + j];
}
__syncthreads();
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];
temp += currAT*inp;
}
float xstart = 0;
float mustart = -1*temp;
sh_x[i][threadIdx.x] = xstart;
sh_mu[i][threadIdx.x] = mustart;
}
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
for (int j=0; j < numEndmembers; j++){
float xprev;
float muprev;
//extract previous values
xprev = sh_x[j][threadIdx.x];
muprev = sh_mu[j][threadIdx.x];
//calculate new value
float temp = xprev - fdividef(muprev, sh_H[j][j]);
temp = (temp > 0)*temp;
//save new value to x
sh_x[j][threadIdx.x] = temp;
//calculate new mu
for (int k=0; k < numEndmembers; k++){
float addition = (temp - xprev)*sh_H[k][j];
sh_mu[k][threadIdx.x] += addition;
}
}
}
for (int i=0; i < numEndmembers; i++){
float val;
val = sh_x[i][threadIdx.x];
x[pixind + i*gridDim.x*pitch] = val;
}
}
//implementation using registers
//YOLO
#define ATmultMua(Arg) i=Arg;\
temp = 0;\
for (int j=0; j < numBands; j++){\
__shared__ float currAT;\
if (threadIdx.x == 0){\
currAT = AT[i*numBands + j];\
}\
__syncthreads();\
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];\
temp += currAT*inp;\
}\
x##Arg = 0;\
/*temp = ((i != currMethbind) || (hasMethb))*(temp);*/\
mu##Arg = -1*temp
/*mu_sh[Arg][threadIdx.x] = -1*temp*/
#define CalcX(Arg) j=Arg;\
xprev = x##Arg;\
muprev = mu##Arg;\
/*muprev = mu_sh[Arg][threadIdx.x];*/\
temp = xprev - fdividef(muprev, sh_H[j][j]);\
temp = (temp > 0)*temp;\
x##Arg = temp
#define CalcMu(Arg) k=Arg;\
addition = (temp - xprev)*sh_H[k][j];\
mu##Arg += addition
/*mu_sh[Arg][threadIdx.x] += addition*/
#define updateMu CalcMu(0);\
CalcMu(1);\
if (MAX_ENDMEMBERS >= 3)\
CalcMu(2);\
if (MAX_ENDMEMBERS >= 4)\
CalcMu(3);\
if (MAX_ENDMEMBERS >= 5)\
CalcMu(4);\
if (MAX_ENDMEMBERS >= 6)\
CalcMu(5);\
if (MAX_ENDMEMBERS >= 7)\
CalcMu(6)
//se opp for makrohelvete, dette ble skrevet for å se om det ble noe raskere om jeg brukte av registrene istedet for shared memory men DESSVERRE var det ikke mulig å opprette arrays i registrene uten like mye kuk som dette. ISRA-artikkelen lyver.
template<int MAX_ENDMEMBERS>
__global__ void SCAFast(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
float temp;
float x0, x1, x2, x3, x4, x5, x6;
float mu0, mu1, mu2, mu3, mu4, mu5, mu6;
int i;
//calculate initial coordinates
ATmultMua(0);
ATmultMua(1);
if (MAX_ENDMEMBERS >= 3)
ATmultMua(2);
if (MAX_ENDMEMBERS >= 4)
ATmultMua(3);
if (MAX_ENDMEMBERS >= 5)
ATmultMua(4);
if (MAX_ENDMEMBERS >= 6)
ATmultMua(5);
if (MAX_ENDMEMBERS >= 7)
ATmultMua(6);
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
float xprev, muprev, temp, addition;
int k,j;
CalcX(0);
updateMu;
CalcX(1);
updateMu;
if (MAX_ENDMEMBERS >= 3){
CalcX(2);
updateMu;
}
if (MAX_ENDMEMBERS >= 4){
CalcX(3);
updateMu;
}
if (MAX_ENDMEMBERS >= 5){
CalcX(4);
updateMu;
}
if (MAX_ENDMEMBERS >= 6){
CalcX(5);
updateMu;
}
if (MAX_ENDMEMBERS >= 7){
CalcX(6);
updateMu;
}
}
x[pixind + 0*gridDim.x*pitch] = x0;
x[pixind + 1*gridDim.x*pitch] = x1;
if (MAX_ENDMEMBERS >= 3)
x[pixind + 2*gridDim.x*pitch] = x2;
if (MAX_ENDMEMBERS >= 4)
x[pixind + 3*gridDim.x*pitch] = x3;
if (MAX_ENDMEMBERS >= 5)
x[pixind + 4*gridDim.x*pitch] = x4;
if (MAX_ENDMEMBERS >= 6)
x[pixind + 5*gridDim.x*pitch] = x5;
if (MAX_ENDMEMBERS >= 7)
x[pixind + 6*gridDim.x*pitch] = x6;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//=======================================================================================================
// Copyright 2015 Asgeir Bjorgan, Lise Lyngsnes Randeberg, Norwegian University of Science and Technology
// Distributed under the MIT License.
// (See accompanying file LICENSE or copy at
// http://opensource.org/licenses/MIT)
//=======================================================================================================
///SCA KIS
#define NUM_ITERATIONS 600
#define METHB_TRESH 1
//implementation of SCA using shared memory
template<int MAX_ENDMEMBERS, int MAX_BLOCKDIM>
__global__ void SCA(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
__shared__ float sh_x[MAX_ENDMEMBERS][MAX_BLOCKDIM];
__shared__ float sh_mu[MAX_ENDMEMBERS][MAX_BLOCKDIM];
//if (blockIdx.x == 5){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
for (int i=0; i < numEndmembers; i++){
float temp = 0;
for (int j=0; j < numBands; j++){
__shared__ float currAT;
if (threadIdx.x == 0){
currAT = AT[i*numBands + j];
}
__syncthreads();
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];
temp += currAT*inp;
}
float xstart = 0;
float mustart = -1*temp;
sh_x[i][threadIdx.x] = xstart;
sh_mu[i][threadIdx.x] = mustart;
}
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
for (int j=0; j < numEndmembers; j++){
float xprev;
float muprev;
//extract previous values
xprev = sh_x[j][threadIdx.x];
muprev = sh_mu[j][threadIdx.x];
//calculate new value
float temp = xprev - fdividef(muprev, sh_H[j][j]);
temp = (temp > 0)*temp;
//save new value to x
sh_x[j][threadIdx.x] = temp;
//calculate new mu
for (int k=0; k < numEndmembers; k++){
float addition = (temp - xprev)*sh_H[k][j];
sh_mu[k][threadIdx.x] += addition;
}
}
}
for (int i=0; i < numEndmembers; i++){
float val;
val = sh_x[i][threadIdx.x];
x[pixind + i*gridDim.x*pitch] = val;
}
}
//implementation using registers
//YOLO
#define ATmultMua(Arg) i=Arg;\
temp = 0;\
for (int j=0; j < numBands; j++){\
__shared__ float currAT;\
if (threadIdx.x == 0){\
currAT = AT[i*numBands + j];\
}\
__syncthreads();\
float inp = inputmua[pixind + gridDim.x*pitch*(j+startind)];\
temp += currAT*inp;\
}\
x##Arg = 0;\
/*temp = ((i != currMethbind) || (hasMethb))*(temp);*/\
mu##Arg = -1*temp
/*mu_sh[Arg][threadIdx.x] = -1*temp*/
#define CalcX(Arg) j=Arg;\
xprev = x##Arg;\
muprev = mu##Arg;\
/*muprev = mu_sh[Arg][threadIdx.x];*/\
temp = xprev - fdividef(muprev, sh_H[j][j]);\
temp = (temp > 0)*temp;\
x##Arg = temp
#define CalcMu(Arg) k=Arg;\
addition = (temp - xprev)*sh_H[k][j];\
mu##Arg += addition
/*mu_sh[Arg][threadIdx.x] += addition*/
#define updateMu CalcMu(0);\
CalcMu(1);\
if (MAX_ENDMEMBERS >= 3)\
CalcMu(2);\
if (MAX_ENDMEMBERS >= 4)\
CalcMu(3);\
if (MAX_ENDMEMBERS >= 5)\
CalcMu(4);\
if (MAX_ENDMEMBERS >= 6)\
CalcMu(5);\
if (MAX_ENDMEMBERS >= 7)\
CalcMu(6)
//se opp for makrohelvete, dette ble skrevet for å se om det ble noe raskere om jeg brukte av registrene istedet for shared memory men DESSVERRE var det ikke mulig å opprette arrays i registrene uten like mye kuk som dette. ISRA-artikkelen lyver.
template<int MAX_ENDMEMBERS>
__global__ void SCAFast(float *AT, float *H, float *inputmua, float *x, float *mu, int startind, int numBands, int numEndmembers, size_t pitch){
//calculate initial values for mu and x
int pixind = pitch*blockIdx.x + threadIdx.x;
float temp;
float x0, x1, x2, x3, x4, x5, x6;
float mu0, mu1, mu2, mu3, mu4, mu5, mu6;
int i;
//calculate initial coordinates
ATmultMua(0);
ATmultMua(1);
if (MAX_ENDMEMBERS >= 3)
ATmultMua(2);
if (MAX_ENDMEMBERS >= 4)
ATmultMua(3);
if (MAX_ENDMEMBERS >= 5)
ATmultMua(4);
if (MAX_ENDMEMBERS >= 6)
ATmultMua(5);
if (MAX_ENDMEMBERS >= 7)
ATmultMua(6);
__shared__ float sh_H[MAX_ENDMEMBERS][MAX_ENDMEMBERS];
if (threadIdx.x == 0){
for (int i=0; i < numEndmembers; i++){
for (int j=0; j < numEndmembers; j++){
sh_H[i][j] = H[i*numEndmembers + j];
}
}
}
__syncthreads();
//iterate
for (int i=0; i < NUM_ITERATIONS; i++){
float xprev, muprev, temp, addition;
int k,j;
CalcX(0);
updateMu;
CalcX(1);
updateMu;
if (MAX_ENDMEMBERS >= 3){
CalcX(2);
updateMu;
}
if (MAX_ENDMEMBERS >= 4){
CalcX(3);
updateMu;
}
if (MAX_ENDMEMBERS >= 5){
CalcX(4);
updateMu;
}
if (MAX_ENDMEMBERS >= 6){
CalcX(5);
updateMu;
}
if (MAX_ENDMEMBERS >= 7){
CalcX(6);
updateMu;
}
}
x[pixind + 0*gridDim.x*pitch] = x0;
x[pixind + 1*gridDim.x*pitch] = x1;
if (MAX_ENDMEMBERS >= 3)
x[pixind + 2*gridDim.x*pitch] = x2;
if (MAX_ENDMEMBERS >= 4)
x[pixind + 3*gridDim.x*pitch] = x3;
if (MAX_ENDMEMBERS >= 5)
x[pixind + 4*gridDim.x*pitch] = x4;
if (MAX_ENDMEMBERS >= 6)
x[pixind + 5*gridDim.x*pitch] = x5;
if (MAX_ENDMEMBERS >= 7)
x[pixind + 6*gridDim.x*pitch] = x6;
} | .text
.file "sca.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ca435_00000000-6_sca.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sca.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define MAX_VALUE 10
__global__ void saxpy(float *X, float *Y, float *Z, int A, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N){
Z[i] = A * X[i] + Y[i];
}
} | code for sm_80
Function : _Z5saxpyPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ I2F R9, c[0x0][0x178] ; /* 0x00005e0000097b06 */
/* 0x000ea20000201400 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00e0*/ FFMA R9, R2, R9, R4 ; /* 0x0000000902097223 */
/* 0x004fca0000000004 */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define MAX_VALUE 10
__global__ void saxpy(float *X, float *Y, float *Z, int A, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N){
Z[i] = A * X[i] + Y[i];
}
} | .file "tmpxft_00161736_00000000-6_saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii
.type _Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii, @function
_Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii, .-_Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii
.globl _Z5saxpyPfS_S_ii
.type _Z5saxpyPfS_S_ii, @function
_Z5saxpyPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5saxpyPfS_S_ii, .-_Z5saxpyPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5saxpyPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define MAX_VALUE 10
__global__ void saxpy(float *X, float *Y, float *Z, int A, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N){
Z[i] = A * X[i] + Y[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define MAX_VALUE 10
__global__ void saxpy(float *X, float *Y, float *Z, int A, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N){
Z[i] = A * X[i] + Y[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define MAX_VALUE 10
__global__ void saxpy(float *X, float *Y, float *Z, int A, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N){
Z[i] = A * X[i] + Y[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPfS_S_ii
.globl _Z5saxpyPfS_S_ii
.p2align 8
.type _Z5saxpyPfS_S_ii,@function
_Z5saxpyPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_cvt_f32_i32_e32 v4, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_fmac_f32_e32 v3, v2, v4
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPfS_S_ii, .Lfunc_end0-_Z5saxpyPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define MAX_VALUE 10
__global__ void saxpy(float *X, float *Y, float *Z, int A, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i<N){
Z[i] = A * X[i] + Y[i];
}
} | .text
.file "saxpy.hip"
.globl _Z20__device_stub__saxpyPfS_S_ii # -- Begin function _Z20__device_stub__saxpyPfS_S_ii
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPfS_S_ii,@function
_Z20__device_stub__saxpyPfS_S_ii: # @_Z20__device_stub__saxpyPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPfS_S_ii, .Lfunc_end0-_Z20__device_stub__saxpyPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPfS_S_ii,@object # @_Z5saxpyPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z5saxpyPfS_S_ii
.p2align 3, 0x0
_Z5saxpyPfS_S_ii:
.quad _Z20__device_stub__saxpyPfS_S_ii
.size _Z5saxpyPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5saxpyPfS_S_ii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ I2F R9, c[0x0][0x178] ; /* 0x00005e0000097b06 */
/* 0x000ea20000201400 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00e0*/ FFMA R9, R2, R9, R4 ; /* 0x0000000902097223 */
/* 0x004fca0000000004 */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPfS_S_ii
.globl _Z5saxpyPfS_S_ii
.p2align 8
.type _Z5saxpyPfS_S_ii,@function
_Z5saxpyPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_cvt_f32_i32_e32 v4, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_fmac_f32_e32 v3, v2, v4
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPfS_S_ii, .Lfunc_end0-_Z5saxpyPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00161736_00000000-6_saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii
.type _Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii, @function
_Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii, .-_Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii
.globl _Z5saxpyPfS_S_ii
.type _Z5saxpyPfS_S_ii, @function
_Z5saxpyPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5saxpyPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5saxpyPfS_S_ii, .-_Z5saxpyPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5saxpyPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy.hip"
.globl _Z20__device_stub__saxpyPfS_S_ii # -- Begin function _Z20__device_stub__saxpyPfS_S_ii
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPfS_S_ii,@function
_Z20__device_stub__saxpyPfS_S_ii: # @_Z20__device_stub__saxpyPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPfS_S_ii, .Lfunc_end0-_Z20__device_stub__saxpyPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPfS_S_ii,@object # @_Z5saxpyPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z5saxpyPfS_S_ii
.p2align 3, 0x0
_Z5saxpyPfS_S_ii:
.quad _Z20__device_stub__saxpyPfS_S_ii
.size _Z5saxpyPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5saxpyPfS_S_ii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define N 64
/*
* This CPU function already works, and will run to create a solution matrix
* against which to verify your work building out the matrixMulGPU kernel.
*/
__global__ void matrixMulGPU(int * a, int * b, int * c)
{
/*
* Build out this kernel.
*/
} | code for sm_80
Function : _Z12matrixMulGPUPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define N 64
/*
* This CPU function already works, and will run to create a solution matrix
* against which to verify your work building out the matrixMulGPU kernel.
*/
__global__ void matrixMulGPU(int * a, int * b, int * c)
{
/*
* Build out this kernel.
*/
} | .file "tmpxft_000c985c_00000000-6_matrixMulGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.type _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, @function
_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, .-_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.globl _Z12matrixMulGPUPiS_S_
.type _Z12matrixMulGPUPiS_S_, @function
_Z12matrixMulGPUPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12matrixMulGPUPiS_S_, .-_Z12matrixMulGPUPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12matrixMulGPUPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define N 64
/*
* This CPU function already works, and will run to create a solution matrix
* against which to verify your work building out the matrixMulGPU kernel.
*/
__global__ void matrixMulGPU(int * a, int * b, int * c)
{
/*
* Build out this kernel.
*/
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 64
/*
* This CPU function already works, and will run to create a solution matrix
* against which to verify your work building out the matrixMulGPU kernel.
*/
__global__ void matrixMulGPU(int * a, int * b, int * c)
{
/*
* Build out this kernel.
*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 64
/*
* This CPU function already works, and will run to create a solution matrix
* against which to verify your work building out the matrixMulGPU kernel.
*/
__global__ void matrixMulGPU(int * a, int * b, int * c)
{
/*
* Build out this kernel.
*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matrixMulGPUPiS_S_
.globl _Z12matrixMulGPUPiS_S_
.p2align 8
.type _Z12matrixMulGPUPiS_S_,@function
_Z12matrixMulGPUPiS_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matrixMulGPUPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matrixMulGPUPiS_S_, .Lfunc_end0-_Z12matrixMulGPUPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matrixMulGPUPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z12matrixMulGPUPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 64
/*
* This CPU function already works, and will run to create a solution matrix
* against which to verify your work building out the matrixMulGPU kernel.
*/
__global__ void matrixMulGPU(int * a, int * b, int * c)
{
/*
* Build out this kernel.
*/
} | .text
.file "matrixMulGPU.hip"
.globl _Z27__device_stub__matrixMulGPUPiS_S_ # -- Begin function _Z27__device_stub__matrixMulGPUPiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__matrixMulGPUPiS_S_,@function
_Z27__device_stub__matrixMulGPUPiS_S_: # @_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matrixMulGPUPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__matrixMulGPUPiS_S_, .Lfunc_end0-_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matrixMulGPUPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matrixMulGPUPiS_S_,@object # @_Z12matrixMulGPUPiS_S_
.section .rodata,"a",@progbits
.globl _Z12matrixMulGPUPiS_S_
.p2align 3, 0x0
_Z12matrixMulGPUPiS_S_:
.quad _Z27__device_stub__matrixMulGPUPiS_S_
.size _Z12matrixMulGPUPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12matrixMulGPUPiS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matrixMulGPUPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matrixMulGPUPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12matrixMulGPUPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matrixMulGPUPiS_S_
.globl _Z12matrixMulGPUPiS_S_
.p2align 8
.type _Z12matrixMulGPUPiS_S_,@function
_Z12matrixMulGPUPiS_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matrixMulGPUPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matrixMulGPUPiS_S_, .Lfunc_end0-_Z12matrixMulGPUPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matrixMulGPUPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z12matrixMulGPUPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c985c_00000000-6_matrixMulGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.type _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, @function
_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, .-_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.globl _Z12matrixMulGPUPiS_S_
.type _Z12matrixMulGPUPiS_S_, @function
_Z12matrixMulGPUPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12matrixMulGPUPiS_S_, .-_Z12matrixMulGPUPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12matrixMulGPUPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMulGPU.hip"
.globl _Z27__device_stub__matrixMulGPUPiS_S_ # -- Begin function _Z27__device_stub__matrixMulGPUPiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__matrixMulGPUPiS_S_,@function
_Z27__device_stub__matrixMulGPUPiS_S_: # @_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12matrixMulGPUPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__matrixMulGPUPiS_S_, .Lfunc_end0-_Z27__device_stub__matrixMulGPUPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matrixMulGPUPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12matrixMulGPUPiS_S_,@object # @_Z12matrixMulGPUPiS_S_
.section .rodata,"a",@progbits
.globl _Z12matrixMulGPUPiS_S_
.p2align 3, 0x0
_Z12matrixMulGPUPiS_S_:
.quad _Z27__device_stub__matrixMulGPUPiS_S_
.size _Z12matrixMulGPUPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12matrixMulGPUPiS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__matrixMulGPUPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12matrixMulGPUPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <vector>
#include <cstdio>
#include <cstdlib>
template <typename T, std::size_t capacity>
struct queue {
int size = 0;
T data[capacity];
__device__ bool insert(const T& value) {
int result = atomicAdd(&size, 1);
if (result >= capacity) {
// Queue is overflowing. Do nothing.
return false;
} else {
data[result] = value;
return true;
}
}
};
constexpr size_t queue_size = 1000;
__global__ void kernel(queue<int, queue_size>* queues, int n) {
size_t tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < n) {
for (size_t i = 0; i < n; i++) {
queues[i].insert(tid);
}
}
}
int main(int argc, char** argv) {
constexpr size_t n = queue_size;
std::vector<queue<int, n>> queues(n);
queue<int, n>* d_queues;
cudaMalloc(&d_queues, sizeof(queue<int, n>)*n);
cudaMemcpy(d_queues, queues.data(), sizeof(queue<int, n>)*n, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
size_t block_size = 256;
// ceil(grid_size / block_size)
dim3 grid((n + block_size - 1) / block_size);
dim3 block(block_size);
kernel<<<grid, block>>>(d_queues, n);
cudaMemcpy(queues.data(), d_queues, sizeof(queue<int, n>)*n, cudaMemcpyDeviceToHost);
bool success = true;
for (size_t i = 0; i < n; i++) {
queue<int, n>& queue = queues[i];
if (queue.size != n) {
success = false;
break;
}
std::vector<size_t> histogram(n, 0);
for (size_t i = 0; i < n; i++) {
if (queue.data[i] < 0 && queue.data[i] >= n) {
success = false;
break;
}
histogram[queue.data[i]] += 1;
if (histogram[queue.data[i]] != 1) {
success = false;
break;
}
}
}
if (success) {
printf("OK!\n");
} else {
printf("FAILED.\n");
}
cudaDeviceSynchronize();
cudaFree(d_queues);
return 0;
} | code for sm_80
Function : _Z6kernelP5queueIiLm1000EEi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05070 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.NE.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fe20003f05300 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0080*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f26070 */
/*0090*/ ISETP.GE.U32.OR.EX P0, PT, RZ, R5, !P0, P1 ; /* 0x00000005ff00720c */
/* 0x000fda0004706510 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, P0, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe20007f1e0ff */
/*00c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00d0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*00e0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*00f0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*0100*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0110*/ IADD3.X R2, R5, -0x1, RZ, P0, !PT ; /* 0xffffffff05027810 */
/* 0x000fe400007fe4ff */
/*0120*/ ISETP.NE.U32.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05070 */
/*0130*/ ISETP.GE.U32.AND.EX P1, PT, R2, RZ, PT, P1 ; /* 0x000000ff0200720c */
/* 0x000fc40003f26110 */
/*0140*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*0150*/ @!P1 BRA 0x550 ; /* 0x000003f000009947 */
/* 0x000fea0003800000 */
/*0160*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0170*/ IADD3 R15, P1, R4, -c[0x0][0x168], RZ ; /* 0x80005a00040f7a10 */
/* 0x000fe20007f3e0ff */
/*0180*/ UIADD3 UR5, UP0, UR6, 0x2ef0, URZ ; /* 0x00002ef006057890 */
/* 0x000fe4000ff1e03f */
/*0190*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*01a0*/ UIADD3.X UR6, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f067290 */
/* 0x000fe200087fe43f */
/*01b0*/ IMAD.X R5, RZ, RZ, ~R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0e05 */
/*01c0*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x000fe2000f8e00ff */
/*01d0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc40008000000 */
/*01e0*/ IMAD.U32 R3, RZ, RZ, UR6 ; /* 0x00000006ff037e24 */
/* 0x000fe4000f8e00ff */
/*01f0*/ S2R R7, SR_LANEID ; /* 0x0000000000077919 */
/* 0x000e220000000000 */
/*0200*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0210*/ FLO.U32 R10, UR6 ; /* 0x00000006000a7d00 */
/* 0x000e3000080e0000 */
/*0220*/ POPC R9, UR6 ; /* 0x0000000600097d09 */
/* 0x000e620008000000 */
/*0230*/ ISETP.EQ.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x001fda0003f22070 */
/*0240*/ @P1 ATOMG.E.ADD.STRONG.GPU PT, R11, [R2.64+-0x2ef0], R9 ; /* 0xffd11009020b19a8 */
/* 0x002ea200081ee1ca */
/*0250*/ FLO.U32 R14, UR6 ; /* 0x00000006000e7d00 */
/* 0x000e2600080e0000 */
/*0260*/ S2R R6, SR_LTMASK ; /* 0x0000000000067919 */
/* 0x000e6a0000003900 */
/*0270*/ POPC R13, UR6 ; /* 0x00000006000d7d09 */
/* 0x000fe20008000000 */
/*0280*/ ISETP.EQ.U32.AND P2, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x001fc40003f42070 */
/*0290*/ LOP3.LUT R12, R6, UR6, RZ, 0xc0, !PT ; /* 0x00000006060c7c12 */
/* 0x002fcc000f8ec0ff */
/*02a0*/ POPC R12, R12 ; /* 0x0000000c000c7309 */
/* 0x000e220000000000 */
/*02b0*/ SHFL.IDX PT, R11, R11, R10, 0x1f ; /* 0x00001f0a0b0b7589 */
/* 0x004e2400000e0000 */
/*02c0*/ IMAD.IADD R17, R11, 0x1, R12 ; /* 0x000000010b117824 */
/* 0x001fca00078e020c */
/*02d0*/ ISETP.GT.U32.AND P1, PT, R17, 0x3e7, PT ; /* 0x000003e71100780c */
/* 0x000fda0003f24070 */
/*02e0*/ @!P1 IMAD.WIDE R8, R17, 0x4, R2 ; /* 0x0000000411089825 */
/* 0x000fca00078e0202 */
/*02f0*/ @!P1 STG.E [R8.64+-0x2eec], R0 ; /* 0xffd1140008009986 */
/* 0x000fe8000c10190a */
/*0300*/ @P2 ATOMG.E.ADD.STRONG.GPU PT, R13, [R2.64+-0x1f4c], R13 ; /* 0xffe0b40d020d29a8 */
/* 0x000ea200081ee1ca */
/*0310*/ LOP3.LUT R10, R6, UR6, RZ, 0xc0, !PT ; /* 0x00000006060a7c12 */
/* 0x000fe2000f8ec0ff */
/*0320*/ FLO.U32 R12, UR6 ; /* 0x00000006000c7d00 */
/* 0x000e3000080e0000 */
/*0330*/ POPC R11, R10 ; /* 0x0000000a000b7309 */
/* 0x000e620000000000 */
/*0340*/ ISETP.EQ.U32.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x001fe20003f42070 */
/*0350*/ SHFL.IDX PT, R14, R13, R14, 0x1f ; /* 0x00001f0e0d0e7589 */
/* 0x004e6400000e0000 */
/*0360*/ IMAD.IADD R17, R14, 0x1, R11 ; /* 0x000000010e117824 */
/* 0x002fc800078e020b */
/*0370*/ POPC R11, UR6 ; /* 0x00000006000b7d09 */
/* 0x000e220008000000 */
/*0380*/ ISETP.GT.U32.AND P1, PT, R17, 0x3e7, PT ; /* 0x000003e71100780c */
/* 0x000fda0003f24070 */
/*0390*/ @!P1 IMAD.WIDE R8, R17, 0x4, R2 ; /* 0x0000000411089825 */
/* 0x000fca00078e0202 */
/*03a0*/ @!P1 STG.E [R8.64+-0x1f48], R0 ; /* 0xffe0b80008009986 */
/* 0x000fe8000c10190a */
/*03b0*/ @P2 ATOMG.E.ADD.STRONG.GPU PT, R11, [R2.64+-0xfa8], R11 ; /* 0xfff0580b020b29a8 */
/* 0x001ea200081ee1ca */
/*03c0*/ POPC R13, R10 ; /* 0x0000000a000d7309 */
/* 0x000ff00000000000 */
/*03d0*/ FLO.U32 R14, UR6 ; /* 0x00000006000e7d00 */
/* 0x000e2400080e0000 */
/*03e0*/ ISETP.EQ.U32.AND P2, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x001fe20003f42070 */
/*03f0*/ SHFL.IDX PT, R12, R11, R12, 0x1f ; /* 0x00001f0c0b0c7589 */
/* 0x004e2400000e0000 */
/*0400*/ IMAD.IADD R17, R12, 0x1, R13 ; /* 0x000000010c117824 */
/* 0x001fc600078e020d */
/*0410*/ POPC R13, UR6 ; /* 0x00000006000d7d09 */
/* 0x000e240008000000 */
/*0420*/ ISETP.GT.U32.AND P1, PT, R17, 0x3e7, PT ; /* 0x000003e71100780c */
/* 0x000fda0003f24070 */
/*0430*/ @!P1 IMAD.WIDE R8, R17, 0x4, R2 ; /* 0x0000000411089825 */
/* 0x000fca00078e0202 */
/*0440*/ @!P1 STG.E [R8.64+-0xfa4], R0 ; /* 0xfff05c0008009986 */
/* 0x0003e8000c10190a */
/*0450*/ @P2 ATOMG.E.ADD.STRONG.GPU PT, R13, [R2.64+-0x4], R13 ; /* 0xfffffc0d020d29a8 */
/* 0x001ea200081ee1ca */
/*0460*/ POPC R7, R10 ; /* 0x0000000a00077309 */
/* 0x000e220000000000 */
/*0470*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0480*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0490*/ IADD3 R8, P2, R15, UR4, RZ ; /* 0x000000040f087c10 */
/* 0x002fe2000ff5e0ff */
/*04a0*/ SHFL.IDX PT, R14, R13, R14, 0x1f ; /* 0x00001f0e0d0e7589 */
/* 0x004e2400000e0000 */
/*04b0*/ IMAD.IADD R7, R14, 0x1, R7 ; /* 0x000000010e077824 */
/* 0x001fca00078e0207 */
/*04c0*/ ISETP.GT.U32.AND P1, PT, R7, 0x3e7, PT ; /* 0x000003e70700780c */
/* 0x000fda0003f24070 */
/*04d0*/ @!P1 IMAD.WIDE R6, R7, 0x4, R2 ; /* 0x0000000407069825 */
/* 0x000fca00078e0202 */
/*04e0*/ @!P1 STG.E [R6.64], R0 ; /* 0x0000000006009986 */
/* 0x0001e2000c10190a */
/*04f0*/ ISETP.NE.U32.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25070 */
/*0500*/ IADD3.X R8, R5, UR5, RZ, P2, !PT ; /* 0x0000000505087c10 */
/* 0x000fe400097fe4ff */
/*0510*/ IADD3 R2, P2, R2, 0x3e90, RZ ; /* 0x00003e9002027810 */
/* 0x000fe40007f5e0ff */
/*0520*/ ISETP.NE.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fc60003f25310 */
/*0530*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fd400010e0603 */
/*0540*/ @P1 BRA 0x1f0 ; /* 0xfffffca000001947 */
/* 0x001fea000383ffff */
/*0550*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0560*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e220000000000 */
/*0570*/ UMOV UR8, 0xfa4 ; /* 0x00000fa400087882 */
/* 0x000fe20000000000 */
/*0580*/ IADD3 R9, P0, RZ, -R4, RZ ; /* 0x80000004ff097210 */
/* 0x000fe20007f1e0ff */
/*0590*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*05a0*/ S2R R12, SR_LTMASK ; /* 0x00000000000c7919 */
/* 0x000e620000003900 */
/*05b0*/ UIMAD.WIDE.U32 UR6, UR4, UR8, UR6 ; /* 0x00000008040672a5 */
/* 0x000fe4000f8e0006 */
/*05c0*/ UIMAD UR5, UR5, 0xfa4, URZ ; /* 0x00000fa4050578a4 */
/* 0x000fe2000f8e023f */
/*05d0*/ IMAD.X R10, RZ, RZ, -0x1, P0 ; /* 0xffffffffff0a7424 */
/* 0x000fe200000e06ff */
/*05e0*/ UIADD3 UR4, UP0, UR6, 0x4, URZ ; /* 0x0000000406047890 */
/* 0x000fc8000ff1e03f */
/*05f0*/ UIADD3.X UR6, UR7, UR5, URZ, UP0, !UPT ; /* 0x0000000507067290 */
/* 0x000fe400087fe43f */
/*0600*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fc8000f8e00ff */
/*0610*/ IMAD.U32 R3, RZ, RZ, UR6 ; /* 0x00000006ff037e24 */
/* 0x000fe4000f8e00ff */
/*0620*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0630*/ FLO.U32 R6, UR4 ; /* 0x0000000400067d00 */
/* 0x000eb000080e0000 */
/*0640*/ POPC R7, UR4 ; /* 0x0000000400077d09 */
/* 0x000ee20008000000 */
/*0650*/ ISETP.EQ.U32.AND P0, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x005fda0003f02070 */
/*0660*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R7, [R2.64+-0x4], R7 ; /* 0xfffffc07020709a8 */
/* 0x008ea200081ee1ca */
/*0670*/ LOP3.LUT R8, R12, UR4, RZ, 0xc0, !PT ; /* 0x000000040c087c12 */
/* 0x002fc8000f8ec0ff */
/*0680*/ POPC R5, R8 ; /* 0x0000000800057309 */
/* 0x000e220000000000 */
/*0690*/ SHFL.IDX PT, R6, R7, R6, 0x1f ; /* 0x00001f0607067589 */
/* 0x004e2400000e0000 */
/*06a0*/ IMAD.IADD R5, R6, 0x1, R5 ; /* 0x0000000106057824 */
/* 0x001fca00078e0205 */
/*06b0*/ ISETP.GT.U32.AND P0, PT, R5, 0x3e7, PT ; /* 0x000003e70500780c */
/* 0x000fda0003f04070 */
/*06c0*/ @!P0 IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405048825 */
/* 0x000fe200078e0202 */
/*06d0*/ IADD3 R2, P1, R2, 0xfa4, RZ ; /* 0x00000fa402027810 */
/* 0x000fc80007f3e0ff */
/*06e0*/ @!P0 STG.E [R4.64], R0 ; /* 0x0000000004008986 */
/* 0x0001e2000c10190a */
/*06f0*/ IADD3 R9, P0, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007f1e0ff */
/*0700*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fc800008e0603 */
/*0710*/ IMAD.X R10, RZ, RZ, R10, P0 ; /* 0x000000ffff0a7224 */
/* 0x000fe200000e060a */
/*0720*/ ISETP.NE.U32.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc80003f05070 */
/*0730*/ ISETP.NE.AND.EX P0, PT, R10, RZ, PT, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05300 */
/*0740*/ @P0 BRA 0x620 ; /* 0xfffffed000000947 */
/* 0x001fea000383ffff */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <vector>
#include <cstdio>
#include <cstdlib>
template <typename T, std::size_t capacity>
struct queue {
int size = 0;
T data[capacity];
__device__ bool insert(const T& value) {
int result = atomicAdd(&size, 1);
if (result >= capacity) {
// Queue is overflowing. Do nothing.
return false;
} else {
data[result] = value;
return true;
}
}
};
constexpr size_t queue_size = 1000;
__global__ void kernel(queue<int, queue_size>* queues, int n) {
size_t tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < n) {
for (size_t i = 0; i < n; i++) {
queues[i].insert(tid);
}
}
}
int main(int argc, char** argv) {
constexpr size_t n = queue_size;
std::vector<queue<int, n>> queues(n);
queue<int, n>* d_queues;
cudaMalloc(&d_queues, sizeof(queue<int, n>)*n);
cudaMemcpy(d_queues, queues.data(), sizeof(queue<int, n>)*n, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
size_t block_size = 256;
// ceil(grid_size / block_size)
dim3 grid((n + block_size - 1) / block_size);
dim3 block(block_size);
kernel<<<grid, block>>>(d_queues, n);
cudaMemcpy(queues.data(), d_queues, sizeof(queue<int, n>)*n, cudaMemcpyDeviceToHost);
bool success = true;
for (size_t i = 0; i < n; i++) {
queue<int, n>& queue = queues[i];
if (queue.size != n) {
success = false;
break;
}
std::vector<size_t> histogram(n, 0);
for (size_t i = 0; i < n; i++) {
if (queue.data[i] < 0 && queue.data[i] >= n) {
success = false;
break;
}
histogram[queue.data[i]] += 1;
if (histogram[queue.data[i]] != 1) {
success = false;
break;
}
}
}
if (success) {
printf("OK!\n");
} else {
printf("FAILED.\n");
}
cudaDeviceSynchronize();
cudaFree(d_queues);
return 0;
} | .file "tmpxft_0014e90a_00000000-6_queue.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2930:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2930:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi
.type _Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi, @function
_Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi:
.LFB2952:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelP5queueIiLm1000EEi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2952:
.size _Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi, .-_Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi
.globl _Z6kernelP5queueIiLm1000EEi
.type _Z6kernelP5queueIiLm1000EEi, @function
_Z6kernelP5queueIiLm1000EEi:
.LFB2953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2953:
.size _Z6kernelP5queueIiLm1000EEi, .-_Z6kernelP5queueIiLm1000EEi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelP5queueIiLm1000EEi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelP5queueIiLm1000EEi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2955:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev,"axG",@progbits,_ZNSt6vectorI5queueIiLm1000EESaIS1_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev
.type _ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev, @function
_ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev:
.LFB3013:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE3013:
.size _ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev, .-_ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev
.weak _ZNSt6vectorI5queueIiLm1000EESaIS1_EED1Ev
.set _ZNSt6vectorI5queueIiLm1000EESaIS1_EED1Ev,_ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev
.section .rodata.str1.1
.LC1:
.string "OK!\n"
.LC2:
.string "FAILED.\n"
.text
.globl main
.type main, @function
main:
.LFB2927:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2927
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4004000, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbp
movq %rax, 32(%rsp)
leaq 4004000(%rax), %r8
movq %r8, 48(%rsp)
movq %rax, %rdx
movl $0, %eax
.L20:
movq $0, (%rdx)
leaq 4004(%rdx), %rsi
movq $0, 3996(%rdx)
leaq 8(%rdx), %rdi
andq $-8, %rdi
subq %rdi, %rdx
leal 4004(%rdx), %ecx
shrl $3, %ecx
movl %ecx, %ecx
rep stosq
movq %rsi, %rdx
cmpq %r8, %rsi
jne .L20
movq %r8, 40(%rsp)
movq %rsp, %rdi
movl $4004000, %esi
.LEHB1:
call cudaMalloc@PLT
movl $1, %ecx
movl $4004000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $4, 8(%rsp)
movl $1, 12(%rsp)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L21
movl $1000, %esi
movq (%rsp), %rdi
call _Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi
.L21:
movl $2, %ecx
movl $4004000, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 4004(%rbp), %rbx
addq $4008004, %rbp
movl $1, %r12d
movl $0, %r13d
jmp .L27
.L42:
movq %rax, %rdi
leaq 8000(%rax), %rax
movq %rdi, %rdx
.L24:
movq $0, (%rdx)
addq $8, %rdx
cmpq %rax, %rdx
jne .L24
leaq -4000(%rbx), %rcx
.L26:
movl (%rcx), %edx
testl %edx, %edx
js .L32
movslq %edx, %rdx
leaq (%rdi,%rdx,8), %rsi
movq (%rsi), %rax
leaq 1(%rax), %rdx
movq %rdx, (%rsi)
cmpq $1, %rdx
jne .L33
addq $4, %rcx
cmpq %rbx, %rcx
jne .L26
jmp .L25
.L32:
movl %r13d, %r12d
.L25:
movl $8000, %esi
call _ZdlPvm@PLT
addq $4004, %rbx
cmpq %rbp, %rbx
je .L41
.L27:
cmpl $1000, -4004(%rbx)
jne .L23
movl $8000, %edi
call _Znwm@PLT
jmp .L42
.L33:
movl %r13d, %r12d
jmp .L25
.L41:
testb %r12b, %r12b
jne .L43
.L23:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L43:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L28:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
.LEHE1:
leaq 32(%rsp), %rdi
call _ZNSt6vectorI5queueIiLm1000EESaIS1_EED1Ev
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt6vectorI5queueIiLm1000EESaIS1_EED1Ev
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L30:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2927:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2927:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2927-.LLSDACSB2927
.LLSDACSB2927:
.uleb128 .LEHB0-.LFB2927
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2927
.uleb128 .LEHE1-.LEHB1
.uleb128 .L34-.LFB2927
.uleb128 0
.uleb128 .LEHB2-.LFB2927
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE2927:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <vector>
#include <cstdio>
#include <cstdlib>
template <typename T, std::size_t capacity>
struct queue {
int size = 0;
T data[capacity];
__device__ bool insert(const T& value) {
int result = atomicAdd(&size, 1);
if (result >= capacity) {
// Queue is overflowing. Do nothing.
return false;
} else {
data[result] = value;
return true;
}
}
};
constexpr size_t queue_size = 1000;
__global__ void kernel(queue<int, queue_size>* queues, int n) {
size_t tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < n) {
for (size_t i = 0; i < n; i++) {
queues[i].insert(tid);
}
}
}
int main(int argc, char** argv) {
constexpr size_t n = queue_size;
std::vector<queue<int, n>> queues(n);
queue<int, n>* d_queues;
cudaMalloc(&d_queues, sizeof(queue<int, n>)*n);
cudaMemcpy(d_queues, queues.data(), sizeof(queue<int, n>)*n, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
size_t block_size = 256;
// ceil(grid_size / block_size)
dim3 grid((n + block_size - 1) / block_size);
dim3 block(block_size);
kernel<<<grid, block>>>(d_queues, n);
cudaMemcpy(queues.data(), d_queues, sizeof(queue<int, n>)*n, cudaMemcpyDeviceToHost);
bool success = true;
for (size_t i = 0; i < n; i++) {
queue<int, n>& queue = queues[i];
if (queue.size != n) {
success = false;
break;
}
std::vector<size_t> histogram(n, 0);
for (size_t i = 0; i < n; i++) {
if (queue.data[i] < 0 && queue.data[i] >= n) {
success = false;
break;
}
histogram[queue.data[i]] += 1;
if (histogram[queue.data[i]] != 1) {
success = false;
break;
}
}
}
if (success) {
printf("OK!\n");
} else {
printf("FAILED.\n");
}
cudaDeviceSynchronize();
cudaFree(d_queues);
return 0;
} | #include <hip/hip_runtime.h>
#include <vector>
#include <cstdio>
#include <cstdlib>
template <typename T, std::size_t capacity>
struct queue {
int size = 0;
T data[capacity];
__device__ bool insert(const T& value) {
int result = atomicAdd(&size, 1);
if (result >= capacity) {
// Queue is overflowing. Do nothing.
return false;
} else {
data[result] = value;
return true;
}
}
};
constexpr size_t queue_size = 1000;
__global__ void kernel(queue<int, queue_size>* queues, int n) {
size_t tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < n) {
for (size_t i = 0; i < n; i++) {
queues[i].insert(tid);
}
}
}
int main(int argc, char** argv) {
constexpr size_t n = queue_size;
std::vector<queue<int, n>> queues(n);
queue<int, n>* d_queues;
hipMalloc(&d_queues, sizeof(queue<int, n>)*n);
hipMemcpy(d_queues, queues.data(), sizeof(queue<int, n>)*n, hipMemcpyHostToDevice);
hipDeviceSynchronize();
size_t block_size = 256;
// ceil(grid_size / block_size)
dim3 grid((n + block_size - 1) / block_size);
dim3 block(block_size);
kernel<<<grid, block>>>(d_queues, n);
hipMemcpy(queues.data(), d_queues, sizeof(queue<int, n>)*n, hipMemcpyDeviceToHost);
bool success = true;
for (size_t i = 0; i < n; i++) {
queue<int, n>& queue = queues[i];
if (queue.size != n) {
success = false;
break;
}
std::vector<size_t> histogram(n, 0);
for (size_t i = 0; i < n; i++) {
if (queue.data[i] < 0 && queue.data[i] >= n) {
success = false;
break;
}
histogram[queue.data[i]] += 1;
if (histogram[queue.data[i]] != 1) {
success = false;
break;
}
}
}
if (success) {
printf("OK!\n");
} else {
printf("FAILED.\n");
}
hipDeviceSynchronize();
hipFree(d_queues);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <vector>
#include <cstdio>
#include <cstdlib>
template <typename T, std::size_t capacity>
struct queue {
int size = 0;
T data[capacity];
__device__ bool insert(const T& value) {
int result = atomicAdd(&size, 1);
if (result >= capacity) {
// Queue is overflowing. Do nothing.
return false;
} else {
data[result] = value;
return true;
}
}
};
constexpr size_t queue_size = 1000;
__global__ void kernel(queue<int, queue_size>* queues, int n) {
size_t tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < n) {
for (size_t i = 0; i < n; i++) {
queues[i].insert(tid);
}
}
}
int main(int argc, char** argv) {
constexpr size_t n = queue_size;
std::vector<queue<int, n>> queues(n);
queue<int, n>* d_queues;
hipMalloc(&d_queues, sizeof(queue<int, n>)*n);
hipMemcpy(d_queues, queues.data(), sizeof(queue<int, n>)*n, hipMemcpyHostToDevice);
hipDeviceSynchronize();
size_t block_size = 256;
// ceil(grid_size / block_size)
dim3 grid((n + block_size - 1) / block_size);
dim3 block(block_size);
kernel<<<grid, block>>>(d_queues, n);
hipMemcpy(queues.data(), d_queues, sizeof(queue<int, n>)*n, hipMemcpyDeviceToHost);
bool success = true;
for (size_t i = 0; i < n; i++) {
queue<int, n>& queue = queues[i];
if (queue.size != n) {
success = false;
break;
}
std::vector<size_t> histogram(n, 0);
for (size_t i = 0; i < n; i++) {
if (queue.data[i] < 0 && queue.data[i] >= n) {
success = false;
break;
}
histogram[queue.data[i]] += 1;
if (histogram[queue.data[i]] != 1) {
success = false;
break;
}
}
}
if (success) {
printf("OK!\n");
} else {
printf("FAILED.\n");
}
hipDeviceSynchronize();
hipFree(d_queues);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelP5queueIiLm1000EEi
.globl _Z6kernelP5queueIiLm1000EEi
.p2align 8
.type _Z6kernelP5queueIiLm1000EEi,@function
_Z6kernelP5queueIiLm1000EEi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
v_mov_b32_e32 v1, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v3, v1
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_u64_e64 s[2:3], v[2:3]
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_add_u32 s0, s0, 0xfa4
s_addc_u32 s1, s1, 0
s_cmp_lg_u64 s[2:3], 0
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_mov_b32 s5, exec_lo
s_mov_b32 s4, exec_lo
v_mbcnt_lo_u32_b32 v0, s5, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
s_bcnt1_i32_b32 s5, s5
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v3, s5
global_atomic_add_u32 v3, v1, v3, s[0:1] offset:-4 glc
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s4, v0
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 0x3e8, v0
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[3:4], v2, off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelP5queueIiLm1000EEi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelP5queueIiLm1000EEi, .Lfunc_end0-_Z6kernelP5queueIiLm1000EEi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelP5queueIiLm1000EEi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelP5queueIiLm1000EEi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <vector>
#include <cstdio>
#include <cstdlib>
template <typename T, std::size_t capacity>
struct queue {
int size = 0;
T data[capacity];
__device__ bool insert(const T& value) {
int result = atomicAdd(&size, 1);
if (result >= capacity) {
// Queue is overflowing. Do nothing.
return false;
} else {
data[result] = value;
return true;
}
}
};
constexpr size_t queue_size = 1000;
__global__ void kernel(queue<int, queue_size>* queues, int n) {
size_t tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < n) {
for (size_t i = 0; i < n; i++) {
queues[i].insert(tid);
}
}
}
int main(int argc, char** argv) {
constexpr size_t n = queue_size;
std::vector<queue<int, n>> queues(n);
queue<int, n>* d_queues;
hipMalloc(&d_queues, sizeof(queue<int, n>)*n);
hipMemcpy(d_queues, queues.data(), sizeof(queue<int, n>)*n, hipMemcpyHostToDevice);
hipDeviceSynchronize();
size_t block_size = 256;
// ceil(grid_size / block_size)
dim3 grid((n + block_size - 1) / block_size);
dim3 block(block_size);
kernel<<<grid, block>>>(d_queues, n);
hipMemcpy(queues.data(), d_queues, sizeof(queue<int, n>)*n, hipMemcpyDeviceToHost);
bool success = true;
for (size_t i = 0; i < n; i++) {
queue<int, n>& queue = queues[i];
if (queue.size != n) {
success = false;
break;
}
std::vector<size_t> histogram(n, 0);
for (size_t i = 0; i < n; i++) {
if (queue.data[i] < 0 && queue.data[i] >= n) {
success = false;
break;
}
histogram[queue.data[i]] += 1;
if (histogram[queue.data[i]] != 1) {
success = false;
break;
}
}
}
if (success) {
printf("OK!\n");
} else {
printf("FAILED.\n");
}
hipDeviceSynchronize();
hipFree(d_queues);
return 0;
} | .text
.file "queue.hip"
.globl _Z21__device_stub__kernelP5queueIiLm1000EEi # -- Begin function _Z21__device_stub__kernelP5queueIiLm1000EEi
.p2align 4, 0x90
.type _Z21__device_stub__kernelP5queueIiLm1000EEi,@function
_Z21__device_stub__kernelP5queueIiLm1000EEi: # @_Z21__device_stub__kernelP5queueIiLm1000EEi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelP5queueIiLm1000EEi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP5queueIiLm1000EEi, .Lfunc_end0-_Z21__device_stub__kernelP5queueIiLm1000EEi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorI5queueIiLm1000EESaIS1_EEC2EmRKS2_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $4004000, %edi # imm = 0x3D18A0
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $4004000, %edx # imm = 0x3D18A0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4004000, %esi # imm = 0x3D18A0
callq hipMalloc
.Ltmp1:
# %bb.1: # %_ZL9hipMallocI5queueIiLm1000EEE10hipError_tPPT_m.exit
movq 8(%rsp), %rdi
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $4004000, %edx # imm = 0x3D18A0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp3:
# %bb.2:
.Ltmp4:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp5:
# %bb.3:
.Ltmp7:
.cfi_escape 0x2e, 0x00
movabsq $4294967300, %rdi # imm = 0x100000004
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp8:
# %bb.4:
testl %eax, %eax
jne .LBB1_7
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1000, 20(%rsp) # imm = 0x3E8
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp10:
# %bb.6: # %.noexc
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp11:
.cfi_escape 0x2e, 0x10
leaq 80(%rsp), %r9
movl $_Z6kernelP5queueIiLm1000EEi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp12:
.LBB1_7:
movq 8(%rsp), %rsi
.Ltmp13:
.cfi_escape 0x2e, 0x00
movl $4004000, %edx # imm = 0x3D18A0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp14:
# %bb.8: # %.preheader.preheader
movb $1, %bpl
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
imulq $4004, %r15, %rax # imm = 0xFA4
movl (%rbx,%rax), %r13d
cmpl $1000, %r13d # imm = 0x3E8
je .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
xorl %ebp, %ebp
cmpl $1000, %r13d # imm = 0x3E8
je .LBB1_19
jmp .LBB1_20
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
.Ltmp16:
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znwm
.Ltmp17:
# %bb.12: # %.lr.ph.i.i.i.i.i.i.i.i.i.preheader
# in Loop: Header=BB1_9 Depth=1
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1, %eax
.p2align 4, 0x90
.LBB1_14: # %_ZNSt6vectorImSaImEEC2EmRKmRKS0_.exit.preheader
# Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rax,4), %ecx
testl %ecx, %ecx
js .LBB1_16
# %bb.15: # in Loop: Header=BB1_14 Depth=2
movq (%r14,%rcx,8), %rdx
leaq 1(%rdx), %rsi
movq %rsi, (%r14,%rcx,8)
testq %rdx, %rdx
jne .LBB1_16
# %bb.13: # %_ZNSt6vectorImSaImEEC2EmRKmRKS0_.exit
# in Loop: Header=BB1_14 Depth=2
incq %rax
cmpq $1001, %rax # imm = 0x3E9
jne .LBB1_14
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_16: # in Loop: Header=BB1_9 Depth=1
xorl %ebp, %ebp
.LBB1_17: # %_ZNSt6vectorImSaImEED2Ev.exit
# in Loop: Header=BB1_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
cmpl $1000, %r13d # imm = 0x3E8
jne .LBB1_20
.LBB1_19: # in Loop: Header=BB1_9 Depth=1
incq %r15
addq $4004, %r12 # imm = 0xFA4
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB1_9
.LBB1_20:
testb $1, %bpl
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq puts@PLT
.Ltmp19:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp20:
# %bb.21:
movq 8(%rsp), %rdi
.Ltmp21:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp22:
# %bb.22: # %_ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_27:
.cfi_def_cfa_offset 160
.Ltmp23:
jmp .LBB1_24
.LBB1_25:
.Ltmp15:
jmp .LBB1_24
.LBB1_23:
.Ltmp6:
jmp .LBB1_24
.LBB1_26:
.Ltmp18:
.LBB1_24: # %_ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev.exit51
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp5-.Ltmp0 # Call between .Ltmp0 and .Ltmp5
.uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp14-.Ltmp7 # Call between .Ltmp7 and .Ltmp14
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp17-.Ltmp16 # Call between .Ltmp16 and .Ltmp17
.uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp19-.Ltmp17 # Call between .Ltmp17 and .Ltmp19
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp22-.Ltmp19 # Call between .Ltmp19 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end1-.Ltmp22 # Call between .Ltmp22 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP5queueIiLm1000EEi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP5queueIiLm1000EEi,@object # @_Z6kernelP5queueIiLm1000EEi
.section .rodata,"a",@progbits
.globl _Z6kernelP5queueIiLm1000EEi
.p2align 3, 0x0
_Z6kernelP5queueIiLm1000EEi:
.quad _Z21__device_stub__kernelP5queueIiLm1000EEi
.size _Z6kernelP5queueIiLm1000EEi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelP5queueIiLm1000EEi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "FAILED."
.size .Lstr, 8
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "OK!"
.size .Lstr.1, 4
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP5queueIiLm1000EEi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kernelP5queueIiLm1000EEi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelP5queueIiLm1000EEi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05070 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011404 */
/*0060*/ ISETP.NE.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fe20003f05300 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0080*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f26070 */
/*0090*/ ISETP.GE.U32.OR.EX P0, PT, RZ, R5, !P0, P1 ; /* 0x00000005ff00720c */
/* 0x000fda0004706510 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, P0, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe20007f1e0ff */
/*00c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00d0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*00e0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*00f0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*0100*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0110*/ IADD3.X R2, R5, -0x1, RZ, P0, !PT ; /* 0xffffffff05027810 */
/* 0x000fe400007fe4ff */
/*0120*/ ISETP.NE.U32.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05070 */
/*0130*/ ISETP.GE.U32.AND.EX P1, PT, R2, RZ, PT, P1 ; /* 0x000000ff0200720c */
/* 0x000fc40003f26110 */
/*0140*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*0150*/ @!P1 BRA 0x550 ; /* 0x000003f000009947 */
/* 0x000fea0003800000 */
/*0160*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0170*/ IADD3 R15, P1, R4, -c[0x0][0x168], RZ ; /* 0x80005a00040f7a10 */
/* 0x000fe20007f3e0ff */
/*0180*/ UIADD3 UR5, UP0, UR6, 0x2ef0, URZ ; /* 0x00002ef006057890 */
/* 0x000fe4000ff1e03f */
/*0190*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*01a0*/ UIADD3.X UR6, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f067290 */
/* 0x000fe200087fe43f */
/*01b0*/ IMAD.X R5, RZ, RZ, ~R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe400008e0e05 */
/*01c0*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x000fe2000f8e00ff */
/*01d0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc40008000000 */
/*01e0*/ IMAD.U32 R3, RZ, RZ, UR6 ; /* 0x00000006ff037e24 */
/* 0x000fe4000f8e00ff */
/*01f0*/ S2R R7, SR_LANEID ; /* 0x0000000000077919 */
/* 0x000e220000000000 */
/*0200*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0210*/ FLO.U32 R10, UR6 ; /* 0x00000006000a7d00 */
/* 0x000e3000080e0000 */
/*0220*/ POPC R9, UR6 ; /* 0x0000000600097d09 */
/* 0x000e620008000000 */
/*0230*/ ISETP.EQ.U32.AND P1, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x001fda0003f22070 */
/*0240*/ @P1 ATOMG.E.ADD.STRONG.GPU PT, R11, [R2.64+-0x2ef0], R9 ; /* 0xffd11009020b19a8 */
/* 0x002ea200081ee1ca */
/*0250*/ FLO.U32 R14, UR6 ; /* 0x00000006000e7d00 */
/* 0x000e2600080e0000 */
/*0260*/ S2R R6, SR_LTMASK ; /* 0x0000000000067919 */
/* 0x000e6a0000003900 */
/*0270*/ POPC R13, UR6 ; /* 0x00000006000d7d09 */
/* 0x000fe20008000000 */
/*0280*/ ISETP.EQ.U32.AND P2, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x001fc40003f42070 */
/*0290*/ LOP3.LUT R12, R6, UR6, RZ, 0xc0, !PT ; /* 0x00000006060c7c12 */
/* 0x002fcc000f8ec0ff */
/*02a0*/ POPC R12, R12 ; /* 0x0000000c000c7309 */
/* 0x000e220000000000 */
/*02b0*/ SHFL.IDX PT, R11, R11, R10, 0x1f ; /* 0x00001f0a0b0b7589 */
/* 0x004e2400000e0000 */
/*02c0*/ IMAD.IADD R17, R11, 0x1, R12 ; /* 0x000000010b117824 */
/* 0x001fca00078e020c */
/*02d0*/ ISETP.GT.U32.AND P1, PT, R17, 0x3e7, PT ; /* 0x000003e71100780c */
/* 0x000fda0003f24070 */
/*02e0*/ @!P1 IMAD.WIDE R8, R17, 0x4, R2 ; /* 0x0000000411089825 */
/* 0x000fca00078e0202 */
/*02f0*/ @!P1 STG.E [R8.64+-0x2eec], R0 ; /* 0xffd1140008009986 */
/* 0x000fe8000c10190a */
/*0300*/ @P2 ATOMG.E.ADD.STRONG.GPU PT, R13, [R2.64+-0x1f4c], R13 ; /* 0xffe0b40d020d29a8 */
/* 0x000ea200081ee1ca */
/*0310*/ LOP3.LUT R10, R6, UR6, RZ, 0xc0, !PT ; /* 0x00000006060a7c12 */
/* 0x000fe2000f8ec0ff */
/*0320*/ FLO.U32 R12, UR6 ; /* 0x00000006000c7d00 */
/* 0x000e3000080e0000 */
/*0330*/ POPC R11, R10 ; /* 0x0000000a000b7309 */
/* 0x000e620000000000 */
/*0340*/ ISETP.EQ.U32.AND P2, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x001fe20003f42070 */
/*0350*/ SHFL.IDX PT, R14, R13, R14, 0x1f ; /* 0x00001f0e0d0e7589 */
/* 0x004e6400000e0000 */
/*0360*/ IMAD.IADD R17, R14, 0x1, R11 ; /* 0x000000010e117824 */
/* 0x002fc800078e020b */
/*0370*/ POPC R11, UR6 ; /* 0x00000006000b7d09 */
/* 0x000e220008000000 */
/*0380*/ ISETP.GT.U32.AND P1, PT, R17, 0x3e7, PT ; /* 0x000003e71100780c */
/* 0x000fda0003f24070 */
/*0390*/ @!P1 IMAD.WIDE R8, R17, 0x4, R2 ; /* 0x0000000411089825 */
/* 0x000fca00078e0202 */
/*03a0*/ @!P1 STG.E [R8.64+-0x1f48], R0 ; /* 0xffe0b80008009986 */
/* 0x000fe8000c10190a */
/*03b0*/ @P2 ATOMG.E.ADD.STRONG.GPU PT, R11, [R2.64+-0xfa8], R11 ; /* 0xfff0580b020b29a8 */
/* 0x001ea200081ee1ca */
/*03c0*/ POPC R13, R10 ; /* 0x0000000a000d7309 */
/* 0x000ff00000000000 */
/*03d0*/ FLO.U32 R14, UR6 ; /* 0x00000006000e7d00 */
/* 0x000e2400080e0000 */
/*03e0*/ ISETP.EQ.U32.AND P2, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x001fe20003f42070 */
/*03f0*/ SHFL.IDX PT, R12, R11, R12, 0x1f ; /* 0x00001f0c0b0c7589 */
/* 0x004e2400000e0000 */
/*0400*/ IMAD.IADD R17, R12, 0x1, R13 ; /* 0x000000010c117824 */
/* 0x001fc600078e020d */
/*0410*/ POPC R13, UR6 ; /* 0x00000006000d7d09 */
/* 0x000e240008000000 */
/*0420*/ ISETP.GT.U32.AND P1, PT, R17, 0x3e7, PT ; /* 0x000003e71100780c */
/* 0x000fda0003f24070 */
/*0430*/ @!P1 IMAD.WIDE R8, R17, 0x4, R2 ; /* 0x0000000411089825 */
/* 0x000fca00078e0202 */
/*0440*/ @!P1 STG.E [R8.64+-0xfa4], R0 ; /* 0xfff05c0008009986 */
/* 0x0003e8000c10190a */
/*0450*/ @P2 ATOMG.E.ADD.STRONG.GPU PT, R13, [R2.64+-0x4], R13 ; /* 0xfffffc0d020d29a8 */
/* 0x001ea200081ee1ca */
/*0460*/ POPC R7, R10 ; /* 0x0000000a00077309 */
/* 0x000e220000000000 */
/*0470*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0480*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0490*/ IADD3 R8, P2, R15, UR4, RZ ; /* 0x000000040f087c10 */
/* 0x002fe2000ff5e0ff */
/*04a0*/ SHFL.IDX PT, R14, R13, R14, 0x1f ; /* 0x00001f0e0d0e7589 */
/* 0x004e2400000e0000 */
/*04b0*/ IMAD.IADD R7, R14, 0x1, R7 ; /* 0x000000010e077824 */
/* 0x001fca00078e0207 */
/*04c0*/ ISETP.GT.U32.AND P1, PT, R7, 0x3e7, PT ; /* 0x000003e70700780c */
/* 0x000fda0003f24070 */
/*04d0*/ @!P1 IMAD.WIDE R6, R7, 0x4, R2 ; /* 0x0000000407069825 */
/* 0x000fca00078e0202 */
/*04e0*/ @!P1 STG.E [R6.64], R0 ; /* 0x0000000006009986 */
/* 0x0001e2000c10190a */
/*04f0*/ ISETP.NE.U32.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25070 */
/*0500*/ IADD3.X R8, R5, UR5, RZ, P2, !PT ; /* 0x0000000505087c10 */
/* 0x000fe400097fe4ff */
/*0510*/ IADD3 R2, P2, R2, 0x3e90, RZ ; /* 0x00003e9002027810 */
/* 0x000fe40007f5e0ff */
/*0520*/ ISETP.NE.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fc60003f25310 */
/*0530*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fd400010e0603 */
/*0540*/ @P1 BRA 0x1f0 ; /* 0xfffffca000001947 */
/* 0x001fea000383ffff */
/*0550*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0560*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e220000000000 */
/*0570*/ UMOV UR8, 0xfa4 ; /* 0x00000fa400087882 */
/* 0x000fe20000000000 */
/*0580*/ IADD3 R9, P0, RZ, -R4, RZ ; /* 0x80000004ff097210 */
/* 0x000fe20007f1e0ff */
/*0590*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*05a0*/ S2R R12, SR_LTMASK ; /* 0x00000000000c7919 */
/* 0x000e620000003900 */
/*05b0*/ UIMAD.WIDE.U32 UR6, UR4, UR8, UR6 ; /* 0x00000008040672a5 */
/* 0x000fe4000f8e0006 */
/*05c0*/ UIMAD UR5, UR5, 0xfa4, URZ ; /* 0x00000fa4050578a4 */
/* 0x000fe2000f8e023f */
/*05d0*/ IMAD.X R10, RZ, RZ, -0x1, P0 ; /* 0xffffffffff0a7424 */
/* 0x000fe200000e06ff */
/*05e0*/ UIADD3 UR4, UP0, UR6, 0x4, URZ ; /* 0x0000000406047890 */
/* 0x000fc8000ff1e03f */
/*05f0*/ UIADD3.X UR6, UR7, UR5, URZ, UP0, !UPT ; /* 0x0000000507067290 */
/* 0x000fe400087fe43f */
/*0600*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fc8000f8e00ff */
/*0610*/ IMAD.U32 R3, RZ, RZ, UR6 ; /* 0x00000006ff037e24 */
/* 0x000fe4000f8e00ff */
/*0620*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0630*/ FLO.U32 R6, UR4 ; /* 0x0000000400067d00 */
/* 0x000eb000080e0000 */
/*0640*/ POPC R7, UR4 ; /* 0x0000000400077d09 */
/* 0x000ee20008000000 */
/*0650*/ ISETP.EQ.U32.AND P0, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x005fda0003f02070 */
/*0660*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R7, [R2.64+-0x4], R7 ; /* 0xfffffc07020709a8 */
/* 0x008ea200081ee1ca */
/*0670*/ LOP3.LUT R8, R12, UR4, RZ, 0xc0, !PT ; /* 0x000000040c087c12 */
/* 0x002fc8000f8ec0ff */
/*0680*/ POPC R5, R8 ; /* 0x0000000800057309 */
/* 0x000e220000000000 */
/*0690*/ SHFL.IDX PT, R6, R7, R6, 0x1f ; /* 0x00001f0607067589 */
/* 0x004e2400000e0000 */
/*06a0*/ IMAD.IADD R5, R6, 0x1, R5 ; /* 0x0000000106057824 */
/* 0x001fca00078e0205 */
/*06b0*/ ISETP.GT.U32.AND P0, PT, R5, 0x3e7, PT ; /* 0x000003e70500780c */
/* 0x000fda0003f04070 */
/*06c0*/ @!P0 IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405048825 */
/* 0x000fe200078e0202 */
/*06d0*/ IADD3 R2, P1, R2, 0xfa4, RZ ; /* 0x00000fa402027810 */
/* 0x000fc80007f3e0ff */
/*06e0*/ @!P0 STG.E [R4.64], R0 ; /* 0x0000000004008986 */
/* 0x0001e2000c10190a */
/*06f0*/ IADD3 R9, P0, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007f1e0ff */
/*0700*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fc800008e0603 */
/*0710*/ IMAD.X R10, RZ, RZ, R10, P0 ; /* 0x000000ffff0a7224 */
/* 0x000fe200000e060a */
/*0720*/ ISETP.NE.U32.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc80003f05070 */
/*0730*/ ISETP.NE.AND.EX P0, PT, R10, RZ, PT, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05300 */
/*0740*/ @P0 BRA 0x620 ; /* 0xfffffed000000947 */
/* 0x001fea000383ffff */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelP5queueIiLm1000EEi
.globl _Z6kernelP5queueIiLm1000EEi
.p2align 8
.type _Z6kernelP5queueIiLm1000EEi,@function
_Z6kernelP5queueIiLm1000EEi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
v_mov_b32_e32 v1, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mov_b32_e32 v3, v1
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_u64_e64 s[2:3], v[2:3]
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_add_u32 s0, s0, 0xfa4
s_addc_u32 s1, s1, 0
s_cmp_lg_u64 s[2:3], 0
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_mov_b32 s5, exec_lo
s_mov_b32 s4, exec_lo
v_mbcnt_lo_u32_b32 v0, s5, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
s_bcnt1_i32_b32 s5, s5
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v3, s5
global_atomic_add_u32 v3, v1, v3, s[0:1] offset:-4 glc
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s4, v0
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e32 0x3e8, v0
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b32 v[3:4], v2, off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelP5queueIiLm1000EEi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelP5queueIiLm1000EEi, .Lfunc_end0-_Z6kernelP5queueIiLm1000EEi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelP5queueIiLm1000EEi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelP5queueIiLm1000EEi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014e90a_00000000-6_queue.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2930:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2930:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi
.type _Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi, @function
_Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi:
.LFB2952:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelP5queueIiLm1000EEi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2952:
.size _Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi, .-_Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi
.globl _Z6kernelP5queueIiLm1000EEi
.type _Z6kernelP5queueIiLm1000EEi, @function
_Z6kernelP5queueIiLm1000EEi:
.LFB2953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2953:
.size _Z6kernelP5queueIiLm1000EEi, .-_Z6kernelP5queueIiLm1000EEi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelP5queueIiLm1000EEi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelP5queueIiLm1000EEi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2955:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev,"axG",@progbits,_ZNSt6vectorI5queueIiLm1000EESaIS1_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev
.type _ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev, @function
_ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev:
.LFB3013:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE3013:
.size _ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev, .-_ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev
.weak _ZNSt6vectorI5queueIiLm1000EESaIS1_EED1Ev
.set _ZNSt6vectorI5queueIiLm1000EESaIS1_EED1Ev,_ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev
.section .rodata.str1.1
.LC1:
.string "OK!\n"
.LC2:
.string "FAILED.\n"
.text
.globl main
.type main, @function
main:
.LFB2927:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2927
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4004000, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbp
movq %rax, 32(%rsp)
leaq 4004000(%rax), %r8
movq %r8, 48(%rsp)
movq %rax, %rdx
movl $0, %eax
.L20:
movq $0, (%rdx)
leaq 4004(%rdx), %rsi
movq $0, 3996(%rdx)
leaq 8(%rdx), %rdi
andq $-8, %rdi
subq %rdi, %rdx
leal 4004(%rdx), %ecx
shrl $3, %ecx
movl %ecx, %ecx
rep stosq
movq %rsi, %rdx
cmpq %r8, %rsi
jne .L20
movq %r8, 40(%rsp)
movq %rsp, %rdi
movl $4004000, %esi
.LEHB1:
call cudaMalloc@PLT
movl $1, %ecx
movl $4004000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $4, 8(%rsp)
movl $1, 12(%rsp)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L21
movl $1000, %esi
movq (%rsp), %rdi
call _Z41__device_stub__Z6kernelP5queueIiLm1000EEiP5queueIiLm1000EEi
.L21:
movl $2, %ecx
movl $4004000, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 4004(%rbp), %rbx
addq $4008004, %rbp
movl $1, %r12d
movl $0, %r13d
jmp .L27
.L42:
movq %rax, %rdi
leaq 8000(%rax), %rax
movq %rdi, %rdx
.L24:
movq $0, (%rdx)
addq $8, %rdx
cmpq %rax, %rdx
jne .L24
leaq -4000(%rbx), %rcx
.L26:
movl (%rcx), %edx
testl %edx, %edx
js .L32
movslq %edx, %rdx
leaq (%rdi,%rdx,8), %rsi
movq (%rsi), %rax
leaq 1(%rax), %rdx
movq %rdx, (%rsi)
cmpq $1, %rdx
jne .L33
addq $4, %rcx
cmpq %rbx, %rcx
jne .L26
jmp .L25
.L32:
movl %r13d, %r12d
.L25:
movl $8000, %esi
call _ZdlPvm@PLT
addq $4004, %rbx
cmpq %rbp, %rbx
je .L41
.L27:
cmpl $1000, -4004(%rbx)
jne .L23
movl $8000, %edi
call _Znwm@PLT
jmp .L42
.L33:
movl %r13d, %r12d
jmp .L25
.L41:
testb %r12b, %r12b
jne .L43
.L23:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L43:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L28:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
.LEHE1:
leaq 32(%rsp), %rdi
call _ZNSt6vectorI5queueIiLm1000EESaIS1_EED1Ev
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt6vectorI5queueIiLm1000EESaIS1_EED1Ev
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L30:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2927:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2927:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2927-.LLSDACSB2927
.LLSDACSB2927:
.uleb128 .LEHB0-.LFB2927
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2927
.uleb128 .LEHE1-.LEHB1
.uleb128 .L34-.LFB2927
.uleb128 0
.uleb128 .LEHB2-.LFB2927
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE2927:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "queue.hip"
.globl _Z21__device_stub__kernelP5queueIiLm1000EEi # -- Begin function _Z21__device_stub__kernelP5queueIiLm1000EEi
.p2align 4, 0x90
.type _Z21__device_stub__kernelP5queueIiLm1000EEi,@function
_Z21__device_stub__kernelP5queueIiLm1000EEi: # @_Z21__device_stub__kernelP5queueIiLm1000EEi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelP5queueIiLm1000EEi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP5queueIiLm1000EEi, .Lfunc_end0-_Z21__device_stub__kernelP5queueIiLm1000EEi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorI5queueIiLm1000EESaIS1_EEC2EmRKS2_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $4004000, %edi # imm = 0x3D18A0
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $4004000, %edx # imm = 0x3D18A0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4004000, %esi # imm = 0x3D18A0
callq hipMalloc
.Ltmp1:
# %bb.1: # %_ZL9hipMallocI5queueIiLm1000EEE10hipError_tPPT_m.exit
movq 8(%rsp), %rdi
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $4004000, %edx # imm = 0x3D18A0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp3:
# %bb.2:
.Ltmp4:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp5:
# %bb.3:
.Ltmp7:
.cfi_escape 0x2e, 0x00
movabsq $4294967300, %rdi # imm = 0x100000004
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp8:
# %bb.4:
testl %eax, %eax
jne .LBB1_7
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1000, 20(%rsp) # imm = 0x3E8
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp10:
# %bb.6: # %.noexc
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp11:
.cfi_escape 0x2e, 0x10
leaq 80(%rsp), %r9
movl $_Z6kernelP5queueIiLm1000EEi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp12:
.LBB1_7:
movq 8(%rsp), %rsi
.Ltmp13:
.cfi_escape 0x2e, 0x00
movl $4004000, %edx # imm = 0x3D18A0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp14:
# %bb.8: # %.preheader.preheader
movb $1, %bpl
xorl %r15d, %r15d
movq %rbx, %r12
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_14 Depth 2
imulq $4004, %r15, %rax # imm = 0xFA4
movl (%rbx,%rax), %r13d
cmpl $1000, %r13d # imm = 0x3E8
je .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
xorl %ebp, %ebp
cmpl $1000, %r13d # imm = 0x3E8
je .LBB1_19
jmp .LBB1_20
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
.Ltmp16:
.cfi_escape 0x2e, 0x00
movl $8000, %edi # imm = 0x1F40
callq _Znwm
.Ltmp17:
# %bb.12: # %.lr.ph.i.i.i.i.i.i.i.i.i.preheader
# in Loop: Header=BB1_9 Depth=1
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1, %eax
.p2align 4, 0x90
.LBB1_14: # %_ZNSt6vectorImSaImEEC2EmRKmRKS0_.exit.preheader
# Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rax,4), %ecx
testl %ecx, %ecx
js .LBB1_16
# %bb.15: # in Loop: Header=BB1_14 Depth=2
movq (%r14,%rcx,8), %rdx
leaq 1(%rdx), %rsi
movq %rsi, (%r14,%rcx,8)
testq %rdx, %rdx
jne .LBB1_16
# %bb.13: # %_ZNSt6vectorImSaImEEC2EmRKmRKS0_.exit
# in Loop: Header=BB1_14 Depth=2
incq %rax
cmpq $1001, %rax # imm = 0x3E9
jne .LBB1_14
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_16: # in Loop: Header=BB1_9 Depth=1
xorl %ebp, %ebp
.LBB1_17: # %_ZNSt6vectorImSaImEED2Ev.exit
# in Loop: Header=BB1_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
cmpl $1000, %r13d # imm = 0x3E8
jne .LBB1_20
.LBB1_19: # in Loop: Header=BB1_9 Depth=1
incq %r15
addq $4004, %r12 # imm = 0xFA4
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB1_9
.LBB1_20:
testb $1, %bpl
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq puts@PLT
.Ltmp19:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp20:
# %bb.21:
movq 8(%rsp), %rdi
.Ltmp21:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp22:
# %bb.22: # %_ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_27:
.cfi_def_cfa_offset 160
.Ltmp23:
jmp .LBB1_24
.LBB1_25:
.Ltmp15:
jmp .LBB1_24
.LBB1_23:
.Ltmp6:
jmp .LBB1_24
.LBB1_26:
.Ltmp18:
.LBB1_24: # %_ZNSt6vectorI5queueIiLm1000EESaIS1_EED2Ev.exit51
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp5-.Ltmp0 # Call between .Ltmp0 and .Ltmp5
.uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp14-.Ltmp7 # Call between .Ltmp7 and .Ltmp14
.uleb128 .Ltmp15-.Lfunc_begin0 # jumps to .Ltmp15
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp17-.Ltmp16 # Call between .Ltmp16 and .Ltmp17
.uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp19-.Ltmp17 # Call between .Ltmp17 and .Ltmp19
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp22-.Ltmp19 # Call between .Ltmp19 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end1-.Ltmp22 # Call between .Ltmp22 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP5queueIiLm1000EEi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP5queueIiLm1000EEi,@object # @_Z6kernelP5queueIiLm1000EEi
.section .rodata,"a",@progbits
.globl _Z6kernelP5queueIiLm1000EEi
.p2align 3, 0x0
_Z6kernelP5queueIiLm1000EEi:
.quad _Z21__device_stub__kernelP5queueIiLm1000EEi
.size _Z6kernelP5queueIiLm1000EEi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelP5queueIiLm1000EEi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "FAILED."
.size .Lstr, 8
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "OK!"
.size .Lstr.1, 4
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP5queueIiLm1000EEi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kernelP5queueIiLm1000EEi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // test.cu
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void calcEccentricity(double *r, double *v, double *m, double *ecc, int numParticles)
{
//size_t id = blockIdx.x * blockDim.x + threadIdx.x;
double L[3]; // angular momentum
double eccTemp[3]; // hold components of eccentricity vector
double mu; // standard gravitational parameter
double invdist; // inverse distance between particle and central planet
//if (id < numParticles - 1)
for (int id = 0; id < numParticles - 1; id++)
{
mu = m[0] + m[id+1];
invdist = rsqrt((r[3*(id+1)]-r[0])*(r[3*(id+1)]-r[0])+\
(r[3*(id+1)+1]-r[1])*(r[3*(id+1)+1]-r[1])+\
(r[3*(id+1)+2]-r[2])*(r[3*(id+1)+2]-r[2]));
L[0] = (r[3*(id+1)+1]-r[1])*v[3*(id+1)+2] - (r[3*(id+1)+2]-r[2])*v[3*(id+1)+1];
L[1] = (r[3*(id+1)+2]-r[2])*v[3*(id+1)] - (r[3*(id+1)]-r[0])*v[3*(id+1)+2];
L[2] = (r[3*(id+1)]-r[0])*v[3*(id+1)+1] - (r[3*(id+1)+1]-r[1])*v[3*(id+1)];
eccTemp[0] = (1./mu) * (v[3*(id+1)+1]*L[2] - v[3*(id+1)+2]*L[1]) - (r[3*(id+1)]-r[0]) * invdist;
eccTemp[1] = (1./mu) * (v[3*(id+1)+2]*L[0] - v[3*(id+1)]*L[2]) - (r[3*(id+1)+1]-r[1]) * invdist;
eccTemp[2] = (1./mu) * (v[3*(id+1)]*L[1] - v[3*(id+1)+1]*L[0]) - (r[3*(id+1)+2]-r[2]) * invdist;
ecc[id] = sqrt(eccTemp[0]*eccTemp[0] + eccTemp[1]*eccTemp[1] + eccTemp[2]*eccTemp[2]); // real eccentricity
}
}
int main()
{
int numParticles = 2;
size_t N_bytes = 3 * numParticles * sizeof(double);
double *r_h = (double*)malloc(N_bytes);
double *v_h = (double*)malloc(N_bytes);
double *m_h = (double*)malloc(N_bytes/3);
double *ecc_h = (double*)malloc(N_bytes/3);
r_h[0] = 0, r_h[1] = 0, r_h[2] = 0, r_h[3] = 0.1882315144676964, r_h[4] = 0, r_h[5] = 0;
v_h[0] = 0, v_h[1] = 0, v_h[2] = 0, v_h[3] = 0, v_h[4] = 2.2517605710860709, v_h[5] = 0;
m_h[0] = 1, m_h[1] = 0.0000002100632244;
ecc_h[0] = 0, ecc_h[1] = 0;
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
cudaMalloc((void**) &r_d, N_bytes);
cudaMalloc((void**) &v_d, N_bytes);
cudaMalloc((void**) &m_d, N_bytes/3);
cudaMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
cudaMemcpy(r_d, r_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(v_d, v_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(m_d, m_h, N_bytes/3, cudaMemcpyHostToDevice);
cudaMemcpy(ecc_d, ecc_h, N_bytes/3, cudaMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
CudaCheckError();
cudaMemcpy(ecc_h, ecc_d, N_bytes, cudaMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
cudaFree(r_d);
cudaFree(v_d);
cudaFree(m_d);
cudaFree(ecc_d);
free(r_h);
free(v_h);
free(m_h);
free(ecc_h);
return 0;
}
/*extern "C" {
void testrun(double *r_h, double *v_h, double *m_h, int numParticles, double *ecc_h)
{
size_t N_bytes = 3 * numParticles * sizeof(double);
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
cudaMalloc((void**) &r_d, N_bytes);
cudaMalloc((void**) &v_d, N_bytes);
cudaMalloc((void**) &m_d, N_bytes/3);
cudaMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
cudaMemcpy(r_d, r_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(v_d, v_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(m_d, m_h, N_bytes/3, cudaMemcpyHostToDevice);
cudaMemcpy(ecc_d, ecc_h, N_bytes/3, cudaMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
cudaDeviceSynchronize();
CudaCheckError();
cudaMemcpy(ecc_h, ecc_d, N_bytes, cudaMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
cudaFree(r_d);
cudaFree(v_d);
cudaFree(m_d);
cudaFree(ecc_d);
}
}*/ | code for sm_80
Function : _Z16calcEccentricityPdS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, 0x5 ; /* 0x00000005ff027424 */
/* 0x000fe200078e00ff */
/*0060*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0070*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*0080*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe40008000000 */
/*0090*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ IADD3 R4, R2, -0x2, RZ ; /* 0xfffffffe02047810 */
/* 0x002fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*00c0*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*00e0*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0205 */
/*0100*/ LDG.E.64 R8, [R6.64+0x8] ; /* 0x0000080a06087981 */
/* 0x001ea8000c1e1b00 */
/*0110*/ LDG.E.64 R16, [R4.64+0x8] ; /* 0x0000080a04107981 */
/* 0x000ea8000c1e1b00 */
/*0120*/ LDG.E.64 R22, [R6.64] ; /* 0x0000000a06167981 */
/* 0x000ee8000c1e1b00 */
/*0130*/ LDG.E.64 R14, [R4.64] ; /* 0x0000000a040e7981 */
/* 0x0000e8000c1e1b00 */
/*0140*/ LDG.E.64 R18, [R6.64+0x10] ; /* 0x0000100a06127981 */
/* 0x000f28000c1e1b00 */
/*0150*/ LDG.E.64 R20, [R4.64+0x10] ; /* 0x0000100a04147981 */
/* 0x000122000c1e1b00 */
/*0160*/ UIADD3 UR7, UP0, UR5, UR8, URZ ; /* 0x0000000805077290 */
/* 0x000fe2000ff1e03f */
/*0170*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0c7624 */
/* 0x000fc400078e00ff */
/*0180*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0d7624 */
/* 0x000fe200078e00ff */
/*0190*/ UIADD3.X UR8, UR6, UR9, URZ, UP0, !UPT ; /* 0x0000000906087290 */
/* 0x000fe400087fe43f */
/*01a0*/ IMAD.U32 R10, RZ, RZ, UR7 ; /* 0x00000007ff0a7e24 */
/* 0x000fc6000f8e00ff */
/*01b0*/ LDG.E.64 R12, [R12.64] ; /* 0x0000000a0c0c7981 */
/* 0x000f62000c1e1b00 */
/*01c0*/ MOV R11, UR8 ; /* 0x00000008000b7c02 */
/* 0x000fcc0008000f00 */
/*01d0*/ LDG.E.64 R10, [R10.64+0x8] ; /* 0x0000080a0a0a7981 */
/* 0x000f62000c1e1b00 */
/*01e0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*01f0*/ ISETP.LE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf03270 */
/*0200*/ DADD R8, -R8, R16 ; /* 0x0000000008087229 */
/* 0x004e0c0000000110 */
/*0210*/ DMUL R4, R8, R8 ; /* 0x0000000808047228 */
/* 0x001fc80000000000 */
/*0220*/ DADD R22, -R22, R14 ; /* 0x0000000016167229 */
/* 0x008e08000000010e */
/*0230*/ DADD R6, -R18, R20 ; /* 0x0000000012067229 */
/* 0x010fc80000000114 */
/*0240*/ DFMA R4, R22, R22, R4 ; /* 0x000000161604722b */
/* 0x001e0c0000000004 */
/*0250*/ DFMA R18, R6, R6, R4 ; /* 0x000000060612722b */
/* 0x001e0c0000000004 */
/*0260*/ MUFU.RSQ64H R5, R19 ; /* 0x0000001300057308 */
/* 0x001e220000001c00 */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0280*/ IADD3 R3, R19, -0x100000, RZ ; /* 0xfff0000013037810 */
/* 0x000fe20007ffe0ff */
/*0290*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff117424 */
/* 0x000fe200078e00ff */
/*02b0*/ ISETP.GE.U32.AND P1, PT, R3, 0x7fe00000, PT ; /* 0x7fe000000300780c */
/* 0x000fe20003f26070 */
/*02c0*/ DMUL R14, R4, R4 ; /* 0x00000004040e7228 */
/* 0x001e0c0000000000 */
/*02d0*/ DFMA R14, R18, -R14, 1 ; /* 0x3ff00000120e742b */
/* 0x001e0c000000080e */
/*02e0*/ DFMA R16, R14, R16, 0.5 ; /* 0x3fe000000e10742b */
/* 0x001fc80000000010 */
/*02f0*/ DMUL R14, R4, R14 ; /* 0x0000000e040e7228 */
/* 0x000e080000000000 */
/*0300*/ DADD R24, R10, R12 ; /* 0x000000000a187229 */
/* 0x020288000000000c */
/*0310*/ DFMA R4, R16, R14, R4 ; /* 0x0000000e1004722b */
/* 0x0012220000000004 */
/*0320*/ @!P1 BRA 0x370 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0330*/ MOV R16, 0x350 ; /* 0x0000035000107802 */
/* 0x006fca0000000f00 */
/*0340*/ CALL.REL.NOINC 0xa30 ; /* 0x000006e000007944 */
/* 0x001fea0003c00000 */
/*0350*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0003 */
/*0360*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fe40000000f00 */
/*0370*/ IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff117424 */
/* 0x006fc800078e00ff */
/*0380*/ IMAD.WIDE R16, R2, R17, c[0x0][0x168] ; /* 0x00005a0002107625 */
/* 0x000fca00078e0211 */
/*0390*/ LDG.E.64 R12, [R16.64+-0x8] ; /* 0xfffff80a100c7981 */
/* 0x000ea8000c1e1b00 */
/*03a0*/ LDG.E.64 R10, [R16.64] ; /* 0x0000000a100a7981 */
/* 0x000ee8000c1e1b00 */
/*03b0*/ LDG.E.64 R14, [R16.64+-0x10] ; /* 0xfffff00a100e7981 */
/* 0x000f22000c1e1b00 */
/*03c0*/ MUFU.RCP64H R21, R25 ; /* 0x0000001900157308 */
/* 0x000e620000001800 */
/*03d0*/ IADD3 R20, R25, 0x300402, RZ ; /* 0x0030040219147810 */
/* 0x000fcc0007ffe0ff */
/*03e0*/ DFMA R18, -R24, R20, 1 ; /* 0x3ff000001812742b */
/* 0x002e4c0000000114 */
/*03f0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x002e4c0000000012 */
/*0400*/ DFMA R18, R20, R18, R20 ; /* 0x000000121412722b */
/* 0x002e620000000014 */
/*0410*/ FSETP.GEU.AND P1, PT, |R20|, 5.8789094863358348022e-39, PT ; /* 0x004004021400780b */
/* 0x000fca0003f2e200 */
/*0420*/ DFMA R26, -R24, R18, 1 ; /* 0x3ff00000181a742b */
/* 0x002e4c0000000112 */
/*0430*/ DFMA R26, R18, R26, R18 ; /* 0x0000001a121a722b */
/* 0x002fc80000000012 */
/*0440*/ DMUL R18, R6, R12 ; /* 0x0000000c06127228 */
/* 0x004e480000000000 */
/*0450*/ DMUL R28, R22, R10 ; /* 0x0000000a161c7228 */
/* 0x008e880000000000 */
/*0460*/ DMUL R30, R8, R14 ; /* 0x0000000e081e7228 */
/* 0x010ec80000000000 */
/*0470*/ DFMA R16, R8, R10, -R18 ; /* 0x0000000a0810722b */
/* 0x0023080000000812 */
/*0480*/ DFMA R18, R6, R14, -R28 ; /* 0x0000000e0612722b */
/* 0x004288000000081c */
/*0490*/ DFMA R20, R22, R12, -R30 ; /* 0x0000000c1614722b */
/* 0x0082e2000000081e */
/*04a0*/ @P1 BRA 0x510 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*04b0*/ LOP3.LUT R30, R25, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff191e7812 */
/* 0x016fe400078ec0ff */
/*04c0*/ MOV R26, 0x4f0 ; /* 0x000004f0001a7802 */
/* 0x000fe40000000f00 */
/*04d0*/ IADD3 R30, R30, -0x100000, RZ ; /* 0xfff000001e1e7810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ CALL.REL.NOINC 0x7f0 ; /* 0x0000030000007944 */
/* 0x009fea0003c00000 */
/*04f0*/ IMAD.MOV.U32 R26, RZ, RZ, R28 ; /* 0x000000ffff1a7224 */
/* 0x003fe400078e001c */
/*0500*/ IMAD.MOV.U32 R27, RZ, RZ, R29 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e001d */
/*0510*/ DMUL R24, R14, R20 ; /* 0x000000140e187228 */
/* 0x01ce880000000000 */
/*0520*/ DMUL R22, R22, R4 ; /* 0x0000000416167228 */
/* 0x003fc80000000000 */
/*0530*/ DMUL R8, R8, R4 ; /* 0x0000000408087228 */
/* 0x000fc80000000000 */
/*0540*/ DMUL R4, R6, R4 ; /* 0x0000000406047228 */
/* 0x000fc80000000000 */
/*0550*/ DMUL R6, R10, R18 ; /* 0x000000120a067228 */
/* 0x000e080000000000 */
/*0560*/ DFMA R24, R10, R16, -R24 ; /* 0x000000100a18722b */
/* 0x004e480000000818 */
/*0570*/ DMUL R16, R12, R16 ; /* 0x000000100c107228 */
/* 0x000e880000000000 */
/*0580*/ DFMA R6, R12, R20, -R6 ; /* 0x000000140c06722b */
/* 0x001e080000000806 */
/*0590*/ DFMA R8, R24, R26, -R8 ; /* 0x0000001a1808722b */
/* 0x002e480000000808 */
/*05a0*/ DFMA R16, R14, R18, -R16 ; /* 0x000000120e10722b */
/* 0x004e880000000810 */
/*05b0*/ DFMA R6, R6, R26, -R22 ; /* 0x0000001a0606722b */
/* 0x001fc80000000816 */
/*05c0*/ DMUL R8, R8, R8 ; /* 0x0000000808087228 */
/* 0x002e080000000000 */
/*05d0*/ DFMA R4, R16, R26, -R4 ; /* 0x0000001a1004722b */
/* 0x004fc80000000804 */
/*05e0*/ DFMA R8, R6, R6, R8 ; /* 0x000000060608722b */
/* 0x001e0c0000000008 */
/*05f0*/ DFMA R10, R4, R4, R8 ; /* 0x00000004040a722b */
/* 0x0010640000000008 */
/*0600*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x001fe200078e00ff */
/*0610*/ MOV R9, 0x3fd80000 ; /* 0x3fd8000000097802 */
/* 0x000fc60000000f00 */
/*0620*/ MUFU.RSQ64H R7, R11 ; /* 0x0000000b00077308 */
/* 0x002e280000001c00 */
/*0630*/ IADD3 R6, R11, -0x3500000, RZ ; /* 0xfcb000000b067810 */
/* 0x000fc80007ffe0ff */
/*0640*/ ISETP.GE.U32.AND P1, PT, R6, 0x7ca00000, PT ; /* 0x7ca000000600780c */
/* 0x000fe40003f26070 */
/*0650*/ DMUL R4, R6, R6 ; /* 0x0000000606047228 */
/* 0x001e0c0000000000 */
/*0660*/ DFMA R4, R10, -R4, 1 ; /* 0x3ff000000a04742b */
/* 0x001e0c0000000804 */
/*0670*/ DFMA R8, R4, R8, 0.5 ; /* 0x3fe000000408742b */
/* 0x001fc80000000008 */
/*0680*/ DMUL R4, R6, R4 ; /* 0x0000000406047228 */
/* 0x000e0c0000000000 */
/*0690*/ DFMA R12, R8, R4, R6 ; /* 0x00000004080c722b */
/* 0x001e0c0000000006 */
/*06a0*/ DMUL R14, R10, R12 ; /* 0x0000000c0a0e7228 */
/* 0x001e080000000000 */
/*06b0*/ IADD3 R9, R13, -0x100000, RZ ; /* 0xfff000000d097810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000c */
/*06d0*/ DFMA R16, R14, -R14, R10 ; /* 0x8000000e0e10722b */
/* 0x001e0c000000000a */
/*06e0*/ DFMA R4, R16, R8, R14 ; /* 0x000000081004722b */
/* 0x001062000000000e */
/*06f0*/ @!P1 BRA 0x740 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0700*/ MOV R4, 0x720 ; /* 0x0000072000047802 */
/* 0x002fca0000000f00 */
/*0710*/ CALL.REL.NOINC 0xc60 ; /* 0x0000054000007944 */
/* 0x001fea0003c00000 */
/*0720*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0006 */
/*0730*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0007 */
/*0740*/ ULDC.64 UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe20000000a00 */
/*0750*/ IADD3 R2, R2, 0x3, RZ ; /* 0x0000000302027810 */
/* 0x000fe20007ffe0ff */
/*0760*/ UIADD3 UR7, UP0, UR5, UR8, URZ ; /* 0x0000000805077290 */
/* 0x000fc8000ff1e03f */
/*0770*/ UIADD3.X UR8, UR6, UR9, URZ, UP0, !UPT ; /* 0x0000000906087290 */
/* 0x000fe400087fe43f */
/*0780*/ IMAD.U32 R6, RZ, RZ, UR7 ; /* 0x00000007ff067e24 */
/* 0x000fe2000f8e00ff */
/*0790*/ UIADD3 UR5, UP0, UR5, 0x8, URZ ; /* 0x0000000805057890 */
/* 0x000fc6000ff1e03f */
/*07a0*/ MOV R7, UR8 ; /* 0x0000000800077c02 */
/* 0x000fe20008000f00 */
/*07b0*/ UIADD3.X UR6, URZ, UR6, URZ, UP0, !UPT ; /* 0x000000063f067290 */
/* 0x000fc800087fe43f */
/*07c0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0023e2000c101b0a */
/*07d0*/ @!P0 BRA 0xa0 ; /* 0xfffff8c000008947 */
/* 0x000fea000383ffff */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ DSETP.GTU.AND P1, PT, |R24|, +INF , PT ; /* 0x7ff000001800742a */
/* 0x000e1c0003f2c200 */
/*0800*/ @P1 BRA 0x9f0 ; /* 0x000001e000001947 */
/* 0x001fea0003800000 */
/*0810*/ LOP3.LUT R3, R25, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff19037812 */
/* 0x000fc800078ec0ff */
/*0820*/ IADD3 R27, R3, -0x1, RZ ; /* 0xffffffff031b7810 */
/* 0x000fc80007ffe0ff */
/*0830*/ ISETP.GE.U32.AND P1, PT, R27, 0x7fefffff, PT ; /* 0x7fefffff1b00780c */
/* 0x000fda0003f26070 */
/*0840*/ @P1 LOP3.LUT R29, R25, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff00000191d1812 */
/* 0x000fe200078e3cff */
/*0850*/ @P1 IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c1224 */
/* 0x000fe200078e00ff */
/*0860*/ @P1 BRA 0xa10 ; /* 0x000001a000001947 */
/* 0x000fea0003800000 */
/*0870*/ ISETP.GE.U32.AND P1, PT, R3, 0x1000001, PT ; /* 0x010000010300780c */
/* 0x000fda0003f26070 */
/*0880*/ @!P1 BRA 0x960 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0890*/ IADD3 R29, R25, -0x3fe00000, RZ ; /* 0xc0200000191d7810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ IMAD.MOV.U32 R28, RZ, RZ, R24 ; /* 0x000000ffff1c7224 */
/* 0x000fc600078e0018 */
/*08b0*/ MUFU.RCP64H R31, R29 ; /* 0x0000001d001f7308 */
/* 0x000e260000001800 */
/*08c0*/ DFMA R32, -R28, R30, 1 ; /* 0x3ff000001c20742b */
/* 0x001e0c000000011e */
/*08d0*/ DFMA R32, R32, R32, R32 ; /* 0x000000202020722b */
/* 0x001e0c0000000020 */
/*08e0*/ DFMA R32, R30, R32, R30 ; /* 0x000000201e20722b */
/* 0x001e0c000000001e */
/*08f0*/ DFMA R30, -R28, R32, 1 ; /* 0x3ff000001c1e742b */
/* 0x001e0c0000000120 */
/*0900*/ DFMA R30, R32, R30, R32 ; /* 0x0000001e201e722b */
/* 0x001e0c0000000020 */
/*0910*/ DMUL R30, R30, 2.2250738585072013831e-308 ; /* 0x001000001e1e7828 */
/* 0x001e0c0000000000 */
/*0920*/ DFMA R24, -R24, R30, 1 ; /* 0x3ff000001818742b */
/* 0x001e0c000000011e */
/*0930*/ DFMA R24, R24, R24, R24 ; /* 0x000000181818722b */
/* 0x001e0c0000000018 */
/*0940*/ DFMA R28, R30, R24, R30 ; /* 0x000000181e1c722b */
/* 0x001062000000001e */
/*0950*/ BRA 0xa10 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0960*/ DMUL R24, R24, 8.11296384146066816958e+31 ; /* 0x4690000018187828 */
/* 0x000e0c0000000000 */
/*0970*/ MUFU.RCP64H R31, R25 ; /* 0x00000019001f7308 */
/* 0x001e240000001800 */
/*0980*/ DFMA R28, -R24, R30, 1 ; /* 0x3ff00000181c742b */
/* 0x001e0c000000011e */
/*0990*/ DFMA R28, R28, R28, R28 ; /* 0x0000001c1c1c722b */
/* 0x001e0c000000001c */
/*09a0*/ DFMA R28, R30, R28, R30 ; /* 0x0000001c1e1c722b */
/* 0x001e0c000000001e */
/*09b0*/ DFMA R30, -R24, R28, 1 ; /* 0x3ff00000181e742b */
/* 0x001e0c000000011c */
/*09c0*/ DFMA R28, R28, R30, R28 ; /* 0x0000001e1c1c722b */
/* 0x001e0c000000001c */
/*09d0*/ DMUL R28, R28, 8.11296384146066816958e+31 ; /* 0x469000001c1c7828 */
/* 0x001e220000000000 */
/*09e0*/ BRA 0xa10 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*09f0*/ LOP3.LUT R29, R25, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000191d7812 */
/* 0x000fe200078efcff */
/*0a00*/ IMAD.MOV.U32 R28, RZ, RZ, R24 ; /* 0x000000ffff1c7224 */
/* 0x000fe400078e0018 */
/*0a10*/ IMAD.MOV.U32 R27, RZ, RZ, 0x0 ; /* 0x00000000ff1b7424 */
/* 0x000fc800078e00ff */
/*0a20*/ RET.REL.NODEC R26 0x0 ; /* 0xfffff5d01a007950 */
/* 0x000fea0003c3ffff */
/*0a30*/ MOV R10, R18 ; /* 0x00000012000a7202 */
/* 0x000fe20000000f00 */
/*0a40*/ IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0013 */
/*0a50*/ LOP3.LUT R4, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013047812 */
/* 0x000fca00078ec0ff */
/*0a60*/ DSETP.NEU.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x000e1c0003f2d000 */
/*0a70*/ @!P1 BRA 0xbf0 ; /* 0x0000017000009947 */
/* 0x001fea0003800000 */
/*0a80*/ DSETP.GTU.AND P1, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e1c0003f2c200 */
/*0a90*/ @P1 BRA 0xbd0 ; /* 0x0000013000001947 */
/* 0x001fea0003800000 */
/*0aa0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f25270 */
/*0ab0*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff041424 */
/* 0x000fe400078e00ff */
/*0ac0*/ @P1 IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff051424 */
/* 0x000fe200078e00ff */
/*0ad0*/ @P1 BRA 0xc10 ; /* 0x0000013000001947 */
/* 0x000fea0003800000 */
/*0ae0*/ DSETP.NEU.AND P1, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e1c0003f2d200 */
/*0af0*/ @!P1 CS2R R4, SRZ ; /* 0x0000000000049805 */
/* 0x001fe2000001ff00 */
/*0b00*/ @!P1 BRA 0xc10 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0b10*/ DMUL R10, R10, 1.80143985094819840000e+16 ; /* 0x435000000a0a7828 */
/* 0x000e220000000000 */
/*0b20*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0b30*/ MOV R14, 0x0 ; /* 0x00000000000e7802 */
/* 0x000fe20000000f00 */
/*0b40*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0f7424 */
/* 0x000fc600078e00ff */
/*0b50*/ MUFU.RSQ64H R5, R11 ; /* 0x0000000b00057308 */
/* 0x001e240000001c00 */
/*0b60*/ DMUL R12, R4, R4 ; /* 0x00000004040c7228 */
/* 0x001e0c0000000000 */
/*0b70*/ DFMA R12, R10, -R12, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c000000080c */
/*0b80*/ DFMA R14, R12, R14, 0.5 ; /* 0x3fe000000c0e742b */
/* 0x001fc8000000000e */
/*0b90*/ DMUL R12, R4, R12 ; /* 0x0000000c040c7228 */
/* 0x000e0c0000000000 */
/*0ba0*/ DFMA R4, R14, R12, R4 ; /* 0x0000000c0e04722b */
/* 0x001e0c0000000004 */
/*0bb0*/ DMUL R4, R4, 134217728 ; /* 0x41a0000004047828 */
/* 0x001e220000000000 */
/*0bc0*/ BRA 0xc10 ; /* 0x0000004000007947 */
/* 0x000ff20003800000 */
/*0bd0*/ DADD R4, R10, R10 ; /* 0x000000000a047229 */
/* 0x000062000000000a */
/*0be0*/ BRA 0xc10 ; /* 0x0000002000007947 */
/* 0x000ff20003800000 */
/*0bf0*/ LOP3.LUT R5, R4, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000004057812 */
/* 0x000fe200078efcff */
/*0c00*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc800078e00ff */
/*0c10*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x003fe200078e0004 */
/*0c20*/ MOV R10, R5 ; /* 0x00000005000a7202 */
/* 0x000fe20000000f00 */
/*0c30*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0010 */
/*0c40*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0c50*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff3a004007950 */
/* 0x000fea0003c3ffff */
/*0c60*/ ISETP.GE.U32.AND P1, PT, R6, -0x3400000, PT ; /* 0xfcc000000600780c */
/* 0x000fe20003f26070 */
/*0c70*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0009 */
/*0c80*/ MOV R8, R10 ; /* 0x0000000a00087202 */
/* 0x000fe20000000f00 */
/*0c90*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000b */
/*0ca0*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*0cb0*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fcc00078e0011 */
/*0cc0*/ @!P1 BRA 0xd50 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*0cd0*/ DFMA.RM R6, R6, R12, R14 ; /* 0x0000000c0606722b */
/* 0x000e14000000400e */
/*0ce0*/ IADD3 R10, P1, R6, 0x1, RZ ; /* 0x00000001060a7810 */
/* 0x001fc80007f3e0ff */
/*0cf0*/ IADD3.X R11, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0b7210 */
/* 0x000fcc0000ffe4ff */
/*0d00*/ DFMA.RP R8, -R6, R10, R8 ; /* 0x0000000a0608722b */
/* 0x000e0c0000008108 */
/*0d10*/ DSETP.GT.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800722a */
/* 0x001e0c0003f24000 */
/*0d20*/ FSEL R6, R10, R6, P1 ; /* 0x000000060a067208 */
/* 0x001fe40000800000 */
/*0d30*/ FSEL R7, R11, R7, P1 ; /* 0x000000070b077208 */
/* 0x000fe20000800000 */
/*0d40*/ BRA 0xee0 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*0d50*/ DSETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800722a */
/* 0x000e1c0003f25000 */
/*0d60*/ @!P1 BRA 0xed0 ; /* 0x0000016000009947 */
/* 0x001fea0003800000 */
/*0d70*/ ISETP.GE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f26270 */
/*0d80*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff069424 */
/* 0x000fe400078e00ff */
/*0d90*/ @!P1 IMAD.MOV.U32 R7, RZ, RZ, -0x80000 ; /* 0xfff80000ff079424 */
/* 0x000fe200078e00ff */
/*0da0*/ @!P1 BRA 0xee0 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0db0*/ ISETP.GT.AND P1, PT, R9, 0x7fefffff, PT ; /* 0x7fefffff0900780c */
/* 0x000fda0003f24270 */
/*0dc0*/ @P1 BRA 0xed0 ; /* 0x0000010000001947 */
/* 0x000fea0003800000 */
/*0dd0*/ DMUL R6, R8, 8.11296384146066816958e+31 ; /* 0x4690000008067828 */
/* 0x0000620000000000 */
/*0de0*/ MOV R12, 0x0 ; /* 0x00000000000c7802 */
/* 0x000fe20000000f00 */
/*0df0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0e00*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0d7424 */
/* 0x000fe400078e00ff */
/*0e10*/ MUFU.RSQ64H R9, R7 ; /* 0x0000000700097308 */
/* 0x002e240000001c00 */
/*0e20*/ DMUL R10, R8, R8 ; /* 0x00000008080a7228 */
/* 0x001e0c0000000000 */
/*0e30*/ DFMA R10, R6, -R10, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c000000080a */
/*0e40*/ DFMA R12, R10, R12, 0.5 ; /* 0x3fe000000a0c742b */
/* 0x001fc8000000000c */
/*0e50*/ DMUL R10, R8, R10 ; /* 0x0000000a080a7228 */
/* 0x000e0c0000000000 */
/*0e60*/ DFMA R10, R12, R10, R8 ; /* 0x0000000a0c0a722b */
/* 0x001e0c0000000008 */
/*0e70*/ DMUL R8, R6, R10 ; /* 0x0000000a06087228 */
/* 0x0010480000000000 */
/*0e80*/ IADD3 R11, R11, -0x100000, RZ ; /* 0xfff000000b0b7810 */
/* 0x001fe40007ffe0ff */
/*0e90*/ DFMA R12, R8, -R8, R6 ; /* 0x80000008080c722b */
/* 0x002e0c0000000006 */
/*0ea0*/ DFMA R6, R10, R12, R8 ; /* 0x0000000c0a06722b */
/* 0x001e140000000008 */
/*0eb0*/ IADD3 R7, R7, -0x3500000, RZ ; /* 0xfcb0000007077810 */
/* 0x001fe20007ffe0ff */
/*0ec0*/ BRA 0xee0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ed0*/ DADD R6, R8, R8 ; /* 0x0000000008067229 */
/* 0x0000480000000008 */
/*0ee0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0ef0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff10004007950 */
/* 0x000fea0003c3ffff */
/*0f00*/ BRA 0xf00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // test.cu
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void calcEccentricity(double *r, double *v, double *m, double *ecc, int numParticles)
{
//size_t id = blockIdx.x * blockDim.x + threadIdx.x;
double L[3]; // angular momentum
double eccTemp[3]; // hold components of eccentricity vector
double mu; // standard gravitational parameter
double invdist; // inverse distance between particle and central planet
//if (id < numParticles - 1)
for (int id = 0; id < numParticles - 1; id++)
{
mu = m[0] + m[id+1];
invdist = rsqrt((r[3*(id+1)]-r[0])*(r[3*(id+1)]-r[0])+\
(r[3*(id+1)+1]-r[1])*(r[3*(id+1)+1]-r[1])+\
(r[3*(id+1)+2]-r[2])*(r[3*(id+1)+2]-r[2]));
L[0] = (r[3*(id+1)+1]-r[1])*v[3*(id+1)+2] - (r[3*(id+1)+2]-r[2])*v[3*(id+1)+1];
L[1] = (r[3*(id+1)+2]-r[2])*v[3*(id+1)] - (r[3*(id+1)]-r[0])*v[3*(id+1)+2];
L[2] = (r[3*(id+1)]-r[0])*v[3*(id+1)+1] - (r[3*(id+1)+1]-r[1])*v[3*(id+1)];
eccTemp[0] = (1./mu) * (v[3*(id+1)+1]*L[2] - v[3*(id+1)+2]*L[1]) - (r[3*(id+1)]-r[0]) * invdist;
eccTemp[1] = (1./mu) * (v[3*(id+1)+2]*L[0] - v[3*(id+1)]*L[2]) - (r[3*(id+1)+1]-r[1]) * invdist;
eccTemp[2] = (1./mu) * (v[3*(id+1)]*L[1] - v[3*(id+1)+1]*L[0]) - (r[3*(id+1)+2]-r[2]) * invdist;
ecc[id] = sqrt(eccTemp[0]*eccTemp[0] + eccTemp[1]*eccTemp[1] + eccTemp[2]*eccTemp[2]); // real eccentricity
}
}
int main()
{
int numParticles = 2;
size_t N_bytes = 3 * numParticles * sizeof(double);
double *r_h = (double*)malloc(N_bytes);
double *v_h = (double*)malloc(N_bytes);
double *m_h = (double*)malloc(N_bytes/3);
double *ecc_h = (double*)malloc(N_bytes/3);
r_h[0] = 0, r_h[1] = 0, r_h[2] = 0, r_h[3] = 0.1882315144676964, r_h[4] = 0, r_h[5] = 0;
v_h[0] = 0, v_h[1] = 0, v_h[2] = 0, v_h[3] = 0, v_h[4] = 2.2517605710860709, v_h[5] = 0;
m_h[0] = 1, m_h[1] = 0.0000002100632244;
ecc_h[0] = 0, ecc_h[1] = 0;
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
cudaMalloc((void**) &r_d, N_bytes);
cudaMalloc((void**) &v_d, N_bytes);
cudaMalloc((void**) &m_d, N_bytes/3);
cudaMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
cudaMemcpy(r_d, r_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(v_d, v_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(m_d, m_h, N_bytes/3, cudaMemcpyHostToDevice);
cudaMemcpy(ecc_d, ecc_h, N_bytes/3, cudaMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
CudaCheckError();
cudaMemcpy(ecc_h, ecc_d, N_bytes, cudaMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
cudaFree(r_d);
cudaFree(v_d);
cudaFree(m_d);
cudaFree(ecc_d);
free(r_h);
free(v_h);
free(m_h);
free(ecc_h);
return 0;
}
/*extern "C" {
void testrun(double *r_h, double *v_h, double *m_h, int numParticles, double *ecc_h)
{
size_t N_bytes = 3 * numParticles * sizeof(double);
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
cudaMalloc((void**) &r_d, N_bytes);
cudaMalloc((void**) &v_d, N_bytes);
cudaMalloc((void**) &m_d, N_bytes/3);
cudaMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
cudaMemcpy(r_d, r_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(v_d, v_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(m_d, m_h, N_bytes/3, cudaMemcpyHostToDevice);
cudaMemcpy(ecc_d, ecc_h, N_bytes/3, cudaMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
cudaDeviceSynchronize();
CudaCheckError();
cudaMemcpy(ecc_h, ecc_d, N_bytes, cudaMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
cudaFree(r_d);
cudaFree(v_d);
cudaFree(m_d);
cudaFree(ecc_d);
}
}*/ | .file "tmpxft_00076772_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z16__cudaCheckErrorPKci.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaCheckError() failed at %s:%i : %s\n"
.align 8
.LC1:
.string "cudaCheckError() with sync failed at %s:%i : %s\n"
.section .text._Z16__cudaCheckErrorPKci,"axG",@progbits,_Z16__cudaCheckErrorPKci,comdat
.weak _Z16__cudaCheckErrorPKci
.type _Z16__cudaCheckErrorPKci, @function
_Z16__cudaCheckErrorPKci:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %ebp
call cudaGetLastError@PLT
testl %eax, %eax
jne .L7
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L8
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L8:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z16__cudaCheckErrorPKci, .-_Z16__cudaCheckErrorPKci
.text
.globl _Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i
.type _Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i, @function
_Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16calcEccentricityPdS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i, .-_Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i
.globl _Z16calcEccentricityPdS_S_S_i
.type _Z16calcEccentricityPdS_S_S_i, @function
_Z16calcEccentricityPdS_S_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16calcEccentricityPdS_S_S_i, .-_Z16calcEccentricityPdS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "R\n"
.LC8:
.string "%.16lf %.16lf %.16lf\n"
.LC9:
.string "V\n"
.LC10:
.string "M\n"
.LC11:
.string "%.16lf %.16lf\n"
.LC12:
.string "Initial Eccentricity Array\n"
.LC13:
.string "numParticles = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC14:
.string "/home/ubuntu/Datasets/stackv2/train-structured/exod1a/NbodySimGPU/master/test.cu"
.section .rodata.str1.1
.LC15:
.string "Updated Eccentricity\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "What the eccentricity should be\n"
.section .rodata.str1.1
.LC17:
.string "0.0455862977217524\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $48, %edi
call malloc@PLT
movq %rax, %rbp
movl $48, %edi
call malloc@PLT
movq %rax, %rbx
movl $16, %edi
call malloc@PLT
movq %rax, %r13
movl $16, %edi
call malloc@PLT
movq %rax, %r12
movq $0x000000000, 0(%rbp)
movq $0x000000000, 8(%rbp)
movq $0x000000000, 16(%rbp)
movq .LC3(%rip), %rax
movq %rax, 24(%rbp)
movq $0x000000000, 32(%rbp)
movq $0x000000000, 40(%rbp)
movq $0x000000000, (%rbx)
movq $0x000000000, 8(%rbx)
movq $0x000000000, 16(%rbx)
movq $0x000000000, 24(%rbx)
movq .LC4(%rip), %rax
movq %rax, 32(%rbx)
movq $0x000000000, 40(%rbx)
movq .LC5(%rip), %rax
movq %rax, 0(%r13)
movq .LC6(%rip), %rax
movq %rax, 8(%r13)
movq $0x000000000, (%r12)
movq $0x000000000, 8(%r12)
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 0(%rbp), %xmm0
movsd 16(%rbp), %xmm2
movsd 8(%rbp), %xmm1
leaq .LC8(%rip), %r14
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movsd 24(%rbp), %xmm0
movsd 40(%rbp), %xmm2
movsd 32(%rbp), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd (%rbx), %xmm0
movsd 16(%rbx), %xmm2
movsd 8(%rbx), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movsd 24(%rbx), %xmm0
movsd 40(%rbx), %xmm2
movsd 32(%rbx), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 0(%r13), %xmm0
movsd 8(%r13), %xmm1
leaq .LC11(%rip), %r14
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd (%r12), %xmm0
movsd 8(%r12), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $2, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $48, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $48, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $48, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $48, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
movl $130, %esi
leaq .LC14(%rip), %rdi
call _Z16__cudaCheckErrorPKci
movl $2, %ecx
movl $48, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd (%r12), %xmm0
movsd 8(%r12), %xmm1
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $2, %r8d
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z16calcEccentricityPdS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z16calcEccentricityPdS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 1666944813
.long 1070077944
.align 8
.LC4:
.long 198829386
.long 1073873819
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC6:
.long -1450121176
.long 1049375159
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // test.cu
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void calcEccentricity(double *r, double *v, double *m, double *ecc, int numParticles)
{
//size_t id = blockIdx.x * blockDim.x + threadIdx.x;
double L[3]; // angular momentum
double eccTemp[3]; // hold components of eccentricity vector
double mu; // standard gravitational parameter
double invdist; // inverse distance between particle and central planet
//if (id < numParticles - 1)
for (int id = 0; id < numParticles - 1; id++)
{
mu = m[0] + m[id+1];
invdist = rsqrt((r[3*(id+1)]-r[0])*(r[3*(id+1)]-r[0])+\
(r[3*(id+1)+1]-r[1])*(r[3*(id+1)+1]-r[1])+\
(r[3*(id+1)+2]-r[2])*(r[3*(id+1)+2]-r[2]));
L[0] = (r[3*(id+1)+1]-r[1])*v[3*(id+1)+2] - (r[3*(id+1)+2]-r[2])*v[3*(id+1)+1];
L[1] = (r[3*(id+1)+2]-r[2])*v[3*(id+1)] - (r[3*(id+1)]-r[0])*v[3*(id+1)+2];
L[2] = (r[3*(id+1)]-r[0])*v[3*(id+1)+1] - (r[3*(id+1)+1]-r[1])*v[3*(id+1)];
eccTemp[0] = (1./mu) * (v[3*(id+1)+1]*L[2] - v[3*(id+1)+2]*L[1]) - (r[3*(id+1)]-r[0]) * invdist;
eccTemp[1] = (1./mu) * (v[3*(id+1)+2]*L[0] - v[3*(id+1)]*L[2]) - (r[3*(id+1)+1]-r[1]) * invdist;
eccTemp[2] = (1./mu) * (v[3*(id+1)]*L[1] - v[3*(id+1)+1]*L[0]) - (r[3*(id+1)+2]-r[2]) * invdist;
ecc[id] = sqrt(eccTemp[0]*eccTemp[0] + eccTemp[1]*eccTemp[1] + eccTemp[2]*eccTemp[2]); // real eccentricity
}
}
int main()
{
int numParticles = 2;
size_t N_bytes = 3 * numParticles * sizeof(double);
double *r_h = (double*)malloc(N_bytes);
double *v_h = (double*)malloc(N_bytes);
double *m_h = (double*)malloc(N_bytes/3);
double *ecc_h = (double*)malloc(N_bytes/3);
r_h[0] = 0, r_h[1] = 0, r_h[2] = 0, r_h[3] = 0.1882315144676964, r_h[4] = 0, r_h[5] = 0;
v_h[0] = 0, v_h[1] = 0, v_h[2] = 0, v_h[3] = 0, v_h[4] = 2.2517605710860709, v_h[5] = 0;
m_h[0] = 1, m_h[1] = 0.0000002100632244;
ecc_h[0] = 0, ecc_h[1] = 0;
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
cudaMalloc((void**) &r_d, N_bytes);
cudaMalloc((void**) &v_d, N_bytes);
cudaMalloc((void**) &m_d, N_bytes/3);
cudaMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
cudaMemcpy(r_d, r_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(v_d, v_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(m_d, m_h, N_bytes/3, cudaMemcpyHostToDevice);
cudaMemcpy(ecc_d, ecc_h, N_bytes/3, cudaMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
CudaCheckError();
cudaMemcpy(ecc_h, ecc_d, N_bytes, cudaMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
cudaFree(r_d);
cudaFree(v_d);
cudaFree(m_d);
cudaFree(ecc_d);
free(r_h);
free(v_h);
free(m_h);
free(ecc_h);
return 0;
}
/*extern "C" {
void testrun(double *r_h, double *v_h, double *m_h, int numParticles, double *ecc_h)
{
size_t N_bytes = 3 * numParticles * sizeof(double);
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
cudaMalloc((void**) &r_d, N_bytes);
cudaMalloc((void**) &v_d, N_bytes);
cudaMalloc((void**) &m_d, N_bytes/3);
cudaMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
cudaMemcpy(r_d, r_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(v_d, v_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(m_d, m_h, N_bytes/3, cudaMemcpyHostToDevice);
cudaMemcpy(ecc_d, ecc_h, N_bytes/3, cudaMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
cudaDeviceSynchronize();
CudaCheckError();
cudaMemcpy(ecc_h, ecc_d, N_bytes, cudaMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
cudaFree(r_d);
cudaFree(v_d);
cudaFree(m_d);
cudaFree(ecc_d);
}
}*/ | // test.cu
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void calcEccentricity(double *r, double *v, double *m, double *ecc, int numParticles)
{
//size_t id = blockIdx.x * blockDim.x + threadIdx.x;
double L[3]; // angular momentum
double eccTemp[3]; // hold components of eccentricity vector
double mu; // standard gravitational parameter
double invdist; // inverse distance between particle and central planet
//if (id < numParticles - 1)
for (int id = 0; id < numParticles - 1; id++)
{
mu = m[0] + m[id+1];
invdist = rsqrt((r[3*(id+1)]-r[0])*(r[3*(id+1)]-r[0])+\
(r[3*(id+1)+1]-r[1])*(r[3*(id+1)+1]-r[1])+\
(r[3*(id+1)+2]-r[2])*(r[3*(id+1)+2]-r[2]));
L[0] = (r[3*(id+1)+1]-r[1])*v[3*(id+1)+2] - (r[3*(id+1)+2]-r[2])*v[3*(id+1)+1];
L[1] = (r[3*(id+1)+2]-r[2])*v[3*(id+1)] - (r[3*(id+1)]-r[0])*v[3*(id+1)+2];
L[2] = (r[3*(id+1)]-r[0])*v[3*(id+1)+1] - (r[3*(id+1)+1]-r[1])*v[3*(id+1)];
eccTemp[0] = (1./mu) * (v[3*(id+1)+1]*L[2] - v[3*(id+1)+2]*L[1]) - (r[3*(id+1)]-r[0]) * invdist;
eccTemp[1] = (1./mu) * (v[3*(id+1)+2]*L[0] - v[3*(id+1)]*L[2]) - (r[3*(id+1)+1]-r[1]) * invdist;
eccTemp[2] = (1./mu) * (v[3*(id+1)]*L[1] - v[3*(id+1)+1]*L[0]) - (r[3*(id+1)+2]-r[2]) * invdist;
ecc[id] = sqrt(eccTemp[0]*eccTemp[0] + eccTemp[1]*eccTemp[1] + eccTemp[2]*eccTemp[2]); // real eccentricity
}
}
int main()
{
int numParticles = 2;
size_t N_bytes = 3 * numParticles * sizeof(double);
double *r_h = (double*)malloc(N_bytes);
double *v_h = (double*)malloc(N_bytes);
double *m_h = (double*)malloc(N_bytes/3);
double *ecc_h = (double*)malloc(N_bytes/3);
r_h[0] = 0, r_h[1] = 0, r_h[2] = 0, r_h[3] = 0.1882315144676964, r_h[4] = 0, r_h[5] = 0;
v_h[0] = 0, v_h[1] = 0, v_h[2] = 0, v_h[3] = 0, v_h[4] = 2.2517605710860709, v_h[5] = 0;
m_h[0] = 1, m_h[1] = 0.0000002100632244;
ecc_h[0] = 0, ecc_h[1] = 0;
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
hipMalloc((void**) &r_d, N_bytes);
hipMalloc((void**) &v_d, N_bytes);
hipMalloc((void**) &m_d, N_bytes/3);
hipMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
hipMemcpy(r_d, r_h, N_bytes, hipMemcpyHostToDevice);
hipMemcpy(v_d, v_h, N_bytes, hipMemcpyHostToDevice);
hipMemcpy(m_d, m_h, N_bytes/3, hipMemcpyHostToDevice);
hipMemcpy(ecc_d, ecc_h, N_bytes/3, hipMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
CudaCheckError();
hipMemcpy(ecc_h, ecc_d, N_bytes, hipMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
hipFree(r_d);
hipFree(v_d);
hipFree(m_d);
hipFree(ecc_d);
free(r_h);
free(v_h);
free(m_h);
free(ecc_h);
return 0;
}
/*extern "C" {
void testrun(double *r_h, double *v_h, double *m_h, int numParticles, double *ecc_h)
{
size_t N_bytes = 3 * numParticles * sizeof(double);
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
cudaMalloc((void**) &r_d, N_bytes);
cudaMalloc((void**) &v_d, N_bytes);
cudaMalloc((void**) &m_d, N_bytes/3);
cudaMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
cudaMemcpy(r_d, r_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(v_d, v_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(m_d, m_h, N_bytes/3, cudaMemcpyHostToDevice);
cudaMemcpy(ecc_d, ecc_h, N_bytes/3, cudaMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
cudaDeviceSynchronize();
CudaCheckError();
cudaMemcpy(ecc_h, ecc_d, N_bytes, cudaMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
cudaFree(r_d);
cudaFree(v_d);
cudaFree(m_d);
cudaFree(ecc_d);
}
}*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // test.cu
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void calcEccentricity(double *r, double *v, double *m, double *ecc, int numParticles)
{
//size_t id = blockIdx.x * blockDim.x + threadIdx.x;
double L[3]; // angular momentum
double eccTemp[3]; // hold components of eccentricity vector
double mu; // standard gravitational parameter
double invdist; // inverse distance between particle and central planet
//if (id < numParticles - 1)
for (int id = 0; id < numParticles - 1; id++)
{
mu = m[0] + m[id+1];
invdist = rsqrt((r[3*(id+1)]-r[0])*(r[3*(id+1)]-r[0])+\
(r[3*(id+1)+1]-r[1])*(r[3*(id+1)+1]-r[1])+\
(r[3*(id+1)+2]-r[2])*(r[3*(id+1)+2]-r[2]));
L[0] = (r[3*(id+1)+1]-r[1])*v[3*(id+1)+2] - (r[3*(id+1)+2]-r[2])*v[3*(id+1)+1];
L[1] = (r[3*(id+1)+2]-r[2])*v[3*(id+1)] - (r[3*(id+1)]-r[0])*v[3*(id+1)+2];
L[2] = (r[3*(id+1)]-r[0])*v[3*(id+1)+1] - (r[3*(id+1)+1]-r[1])*v[3*(id+1)];
eccTemp[0] = (1./mu) * (v[3*(id+1)+1]*L[2] - v[3*(id+1)+2]*L[1]) - (r[3*(id+1)]-r[0]) * invdist;
eccTemp[1] = (1./mu) * (v[3*(id+1)+2]*L[0] - v[3*(id+1)]*L[2]) - (r[3*(id+1)+1]-r[1]) * invdist;
eccTemp[2] = (1./mu) * (v[3*(id+1)]*L[1] - v[3*(id+1)+1]*L[0]) - (r[3*(id+1)+2]-r[2]) * invdist;
ecc[id] = sqrt(eccTemp[0]*eccTemp[0] + eccTemp[1]*eccTemp[1] + eccTemp[2]*eccTemp[2]); // real eccentricity
}
}
int main()
{
int numParticles = 2;
size_t N_bytes = 3 * numParticles * sizeof(double);
double *r_h = (double*)malloc(N_bytes);
double *v_h = (double*)malloc(N_bytes);
double *m_h = (double*)malloc(N_bytes/3);
double *ecc_h = (double*)malloc(N_bytes/3);
r_h[0] = 0, r_h[1] = 0, r_h[2] = 0, r_h[3] = 0.1882315144676964, r_h[4] = 0, r_h[5] = 0;
v_h[0] = 0, v_h[1] = 0, v_h[2] = 0, v_h[3] = 0, v_h[4] = 2.2517605710860709, v_h[5] = 0;
m_h[0] = 1, m_h[1] = 0.0000002100632244;
ecc_h[0] = 0, ecc_h[1] = 0;
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
hipMalloc((void**) &r_d, N_bytes);
hipMalloc((void**) &v_d, N_bytes);
hipMalloc((void**) &m_d, N_bytes/3);
hipMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
hipMemcpy(r_d, r_h, N_bytes, hipMemcpyHostToDevice);
hipMemcpy(v_d, v_h, N_bytes, hipMemcpyHostToDevice);
hipMemcpy(m_d, m_h, N_bytes/3, hipMemcpyHostToDevice);
hipMemcpy(ecc_d, ecc_h, N_bytes/3, hipMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
CudaCheckError();
hipMemcpy(ecc_h, ecc_d, N_bytes, hipMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
hipFree(r_d);
hipFree(v_d);
hipFree(m_d);
hipFree(ecc_d);
free(r_h);
free(v_h);
free(m_h);
free(ecc_h);
return 0;
}
/*extern "C" {
void testrun(double *r_h, double *v_h, double *m_h, int numParticles, double *ecc_h)
{
size_t N_bytes = 3 * numParticles * sizeof(double);
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
cudaMalloc((void**) &r_d, N_bytes);
cudaMalloc((void**) &v_d, N_bytes);
cudaMalloc((void**) &m_d, N_bytes/3);
cudaMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
cudaMemcpy(r_d, r_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(v_d, v_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(m_d, m_h, N_bytes/3, cudaMemcpyHostToDevice);
cudaMemcpy(ecc_d, ecc_h, N_bytes/3, cudaMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
cudaDeviceSynchronize();
CudaCheckError();
cudaMemcpy(ecc_h, ecc_d, N_bytes, cudaMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
cudaFree(r_d);
cudaFree(v_d);
cudaFree(m_d);
cudaFree(ecc_d);
}
}*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16calcEccentricityPdS_S_S_i
.globl _Z16calcEccentricityPdS_S_S_i
.p2align 8
.type _Z16calcEccentricityPdS_S_S_i,@function
_Z16calcEccentricityPdS_S_S_i:
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_3
s_load_b256 s[4:11], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_add_i32 s1, s2, -1
s_mov_b64 s[2:3], 0
s_mov_b64 s[12:13], 0
s_waitcnt lgkmcnt(0)
s_add_u32 s14, s8, 8
s_addc_u32 s15, s9, 0
.LBB0_2:
s_add_u32 s16, s14, s12
s_addc_u32 s17, s15, s13
s_clause 0x2
global_load_b64 v[13:14], v0, s[8:9]
global_load_b64 v[15:16], v0, s[16:17]
global_load_b128 v[1:4], v0, s[4:5]
s_add_u32 s16, s4, s2
s_addc_u32 s17, s5, s3
s_clause 0x2
global_load_b128 v[5:8], v0, s[16:17] offset:24
global_load_b64 v[17:18], v0, s[4:5] offset:16
global_load_b64 v[19:20], v0, s[16:17] offset:40
s_add_u32 s16, s6, s2
s_addc_u32 s17, s7, s3
s_clause 0x1
global_load_b128 v[9:12], v0, s[16:17] offset:24
global_load_b64 v[21:22], v0, s[16:17] offset:40
s_waitcnt vmcnt(6)
v_add_f64 v[13:14], v[13:14], v[15:16]
s_waitcnt vmcnt(4)
v_add_f64 v[3:4], v[7:8], -v[3:4]
v_add_f64 v[1:2], v[5:6], -v[1:2]
s_waitcnt vmcnt(2)
v_add_f64 v[17:18], v[19:20], -v[17:18]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_div_scale_f64 v[7:8], null, v[13:14], v[13:14], 1.0
v_div_scale_f64 v[25:26], vcc_lo, 1.0, v[13:14], 1.0
v_mul_f64 v[5:6], v[3:4], v[3:4]
s_waitcnt vmcnt(1)
v_mul_f64 v[29:30], v[17:18], v[11:12]
s_waitcnt vmcnt(0)
v_mul_f64 v[31:32], v[1:2], v[21:22]
v_rcp_f64_e32 v[15:16], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[1:2], v[1:2], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[19:20], -v[7:8], v[15:16], 1.0
v_fma_f64 v[5:6], v[17:18], v[17:18], v[5:6]
v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[19:20], v[5:6]
v_fma_f64 v[23:24], -v[7:8], v[15:16], 1.0
s_waitcnt_depctr 0xfff
v_mul_f64 v[5:6], v[19:20], -v[5:6]
v_cmp_class_f64_e64 s0, v[19:20], 0x180
v_fma_f64 v[15:16], v[15:16], v[23:24], v[15:16]
v_mul_f64 v[23:24], v[3:4], v[9:10]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[5:6], v[5:6], v[19:20], 1.0
v_mul_f64 v[27:28], v[25:26], v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[23:24], v[1:2], v[11:12], -v[23:24]
v_mul_f64 v[33:34], v[19:20], v[5:6]
v_fma_f64 v[5:6], v[5:6], 0x3fd80000, 0.5
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[7:8], -v[7:8], v[27:28], v[25:26]
v_fma_f64 v[25:26], v[3:4], v[21:22], -v[29:30]
v_fma_f64 v[29:30], v[17:18], v[9:10], -v[31:32]
v_mul_f64 v[31:32], v[9:10], v[23:24]
v_fma_f64 v[5:6], v[33:34], v[5:6], v[19:20]
v_div_fmas_f64 v[7:8], v[7:8], v[15:16], v[27:28]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[15:16], v[21:22], v[29:30]
v_fma_f64 v[21:22], v[21:22], v[25:26], -v[31:32]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, v20, v6, s0
v_cndmask_b32_e64 v5, v19, v5, s0
v_mul_f64 v[3:4], v[3:4], v[5:6]
v_mul_f64 v[1:2], v[1:2], v[5:6]
v_mul_f64 v[5:6], v[17:18], v[5:6]
v_div_fixup_f64 v[7:8], v[7:8], v[13:14], 1.0
v_mul_f64 v[13:14], v[11:12], v[25:26]
v_fma_f64 v[11:12], v[11:12], v[23:24], -v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[3:4], v[7:8], v[21:22], -v[3:4]
v_fma_f64 v[9:10], v[9:10], v[29:30], -v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[1:2], v[7:8], v[11:12], -v[1:2]
v_mul_f64 v[3:4], v[3:4], v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[7:8], v[9:10], -v[5:6]
v_fma_f64 v[1:2], v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[1:2], v[5:6], v[5:6], v[1:2]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[1:2]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_and_b32 s0, vcc_lo, exec_lo
s_cselect_b32 s0, 0xffffff80, 0
s_add_u32 s16, s10, s12
s_addc_u32 s17, s11, s13
v_lshlrev_b32_e32 v3, 8, v3
s_add_i32 s1, s1, -1
s_add_u32 s12, s12, 8
s_addc_u32 s13, s13, 0
s_add_u32 s2, s2, 24
v_ldexp_f64 v[1:2], v[1:2], v3
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[3:4], v[1:2]
v_cmp_class_f64_e64 vcc_lo, v[1:2], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[5:6], v[1:2], v[3:4]
v_mul_f64 v[3:4], v[3:4], 0.5
v_fma_f64 v[7:8], -v[3:4], v[5:6], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_fma_f64 v[3:4], v[3:4], v[7:8], v[3:4]
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[7:8], v[3:4], v[5:6]
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[7:8], v[3:4], v[5:6]
v_ldexp_f64 v[3:4], v[3:4], s0
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v1, v3, v1
global_store_b64 v0, v[1:2], s[16:17]
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16calcEccentricityPdS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 35
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16calcEccentricityPdS_S_S_i, .Lfunc_end0-_Z16calcEccentricityPdS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16calcEccentricityPdS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z16calcEccentricityPdS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 35
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // test.cu
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
__global__ void calcEccentricity(double *r, double *v, double *m, double *ecc, int numParticles)
{
//size_t id = blockIdx.x * blockDim.x + threadIdx.x;
double L[3]; // angular momentum
double eccTemp[3]; // hold components of eccentricity vector
double mu; // standard gravitational parameter
double invdist; // inverse distance between particle and central planet
//if (id < numParticles - 1)
for (int id = 0; id < numParticles - 1; id++)
{
mu = m[0] + m[id+1];
invdist = rsqrt((r[3*(id+1)]-r[0])*(r[3*(id+1)]-r[0])+\
(r[3*(id+1)+1]-r[1])*(r[3*(id+1)+1]-r[1])+\
(r[3*(id+1)+2]-r[2])*(r[3*(id+1)+2]-r[2]));
L[0] = (r[3*(id+1)+1]-r[1])*v[3*(id+1)+2] - (r[3*(id+1)+2]-r[2])*v[3*(id+1)+1];
L[1] = (r[3*(id+1)+2]-r[2])*v[3*(id+1)] - (r[3*(id+1)]-r[0])*v[3*(id+1)+2];
L[2] = (r[3*(id+1)]-r[0])*v[3*(id+1)+1] - (r[3*(id+1)+1]-r[1])*v[3*(id+1)];
eccTemp[0] = (1./mu) * (v[3*(id+1)+1]*L[2] - v[3*(id+1)+2]*L[1]) - (r[3*(id+1)]-r[0]) * invdist;
eccTemp[1] = (1./mu) * (v[3*(id+1)+2]*L[0] - v[3*(id+1)]*L[2]) - (r[3*(id+1)+1]-r[1]) * invdist;
eccTemp[2] = (1./mu) * (v[3*(id+1)]*L[1] - v[3*(id+1)+1]*L[0]) - (r[3*(id+1)+2]-r[2]) * invdist;
ecc[id] = sqrt(eccTemp[0]*eccTemp[0] + eccTemp[1]*eccTemp[1] + eccTemp[2]*eccTemp[2]); // real eccentricity
}
}
int main()
{
int numParticles = 2;
size_t N_bytes = 3 * numParticles * sizeof(double);
double *r_h = (double*)malloc(N_bytes);
double *v_h = (double*)malloc(N_bytes);
double *m_h = (double*)malloc(N_bytes/3);
double *ecc_h = (double*)malloc(N_bytes/3);
r_h[0] = 0, r_h[1] = 0, r_h[2] = 0, r_h[3] = 0.1882315144676964, r_h[4] = 0, r_h[5] = 0;
v_h[0] = 0, v_h[1] = 0, v_h[2] = 0, v_h[3] = 0, v_h[4] = 2.2517605710860709, v_h[5] = 0;
m_h[0] = 1, m_h[1] = 0.0000002100632244;
ecc_h[0] = 0, ecc_h[1] = 0;
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
hipMalloc((void**) &r_d, N_bytes);
hipMalloc((void**) &v_d, N_bytes);
hipMalloc((void**) &m_d, N_bytes/3);
hipMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
hipMemcpy(r_d, r_h, N_bytes, hipMemcpyHostToDevice);
hipMemcpy(v_d, v_h, N_bytes, hipMemcpyHostToDevice);
hipMemcpy(m_d, m_h, N_bytes/3, hipMemcpyHostToDevice);
hipMemcpy(ecc_d, ecc_h, N_bytes/3, hipMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
CudaCheckError();
hipMemcpy(ecc_h, ecc_d, N_bytes, hipMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
hipFree(r_d);
hipFree(v_d);
hipFree(m_d);
hipFree(ecc_d);
free(r_h);
free(v_h);
free(m_h);
free(ecc_h);
return 0;
}
/*extern "C" {
void testrun(double *r_h, double *v_h, double *m_h, int numParticles, double *ecc_h)
{
size_t N_bytes = 3 * numParticles * sizeof(double);
printf("R\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", r_h[3*i], r_h[3*i+1], r_h[3*i+2]);
}
printf("V\n");
for (int i = 0; i < numParticles; i++)
{
printf("%.16lf %.16lf %.16lf\n", v_h[3*i], v_h[3*i+1], v_h[3*i+2]);
}
printf("M\n");
printf("%.16lf %.16lf\n", m_h[0], m_h[1]);
printf("Initial Eccentricity Array\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("numParticles = %d\n", numParticles);
// Allocate arrays on device
double *r_d, *v_d, *m_d, *ecc_d;
cudaMalloc((void**) &r_d, N_bytes);
cudaMalloc((void**) &v_d, N_bytes);
cudaMalloc((void**) &m_d, N_bytes/3);
cudaMalloc((void**) &ecc_d, N_bytes/3);
// Copy arrays from host to device
cudaMemcpy(r_d, r_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(v_d, v_h, N_bytes, cudaMemcpyHostToDevice);
cudaMemcpy(m_d, m_h, N_bytes/3, cudaMemcpyHostToDevice);
cudaMemcpy(ecc_d, ecc_h, N_bytes/3, cudaMemcpyHostToDevice);
calcEccentricity<<<1, 1>>>(r_d, v_d, m_d, ecc_d, numParticles);
cudaDeviceSynchronize();
CudaCheckError();
cudaMemcpy(ecc_h, ecc_d, N_bytes, cudaMemcpyDeviceToHost);
printf("Updated Eccentricity\n");
printf("%.16lf %.16lf\n", ecc_h[0], ecc_h[1]);
printf("What the eccentricity should be\n");
printf("0.0455862977217524\n");
cudaFree(r_d);
cudaFree(v_d);
cudaFree(m_d);
cudaFree(ecc_d);
}
}*/ | .text
.file "test.hip"
.globl _Z31__device_stub__calcEccentricityPdS_S_S_i # -- Begin function _Z31__device_stub__calcEccentricityPdS_S_S_i
.p2align 4, 0x90
.type _Z31__device_stub__calcEccentricityPdS_S_S_i,@function
_Z31__device_stub__calcEccentricityPdS_S_S_i: # @_Z31__device_stub__calcEccentricityPdS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16calcEccentricityPdS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z31__device_stub__calcEccentricityPdS_S_S_i, .Lfunc_end0-_Z31__device_stub__calcEccentricityPdS_S_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $48, %edi
callq malloc
movq %rax, %rbx
movl $48, %edi
callq malloc
movq %rax, %r14
movl $16, %r13d
movl $16, %edi
callq malloc
movq %rax, %r15
movl $16, %edi
callq malloc
movq %rax, %r12
xorps %xmm0, %xmm0
movups %xmm0, (%rbx)
movq $0, 16(%rbx)
movabsq $4595949775317864237, %rax # imm = 0x3FC817F8635B8F2D
movq %rax, 24(%rbx)
movups %xmm0, 32(%rbx)
movups %xmm0, 16(%r14)
movups %xmm0, (%r14)
movabsq $4612252932834452810, %rax # imm = 0x4002039B0BD9E54A
movq %rax, 32(%r14)
movq $0, 40(%r14)
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, (%r15)
movabsq $4507031991984646184, %rax # imm = 0x3E8C31B7A990E828
movq %rax, 8(%r15)
movups %xmm0, (%r12)
movl $.Lstr, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movsd -16(%rbx,%r13), %xmm0 # xmm0 = mem[0],zero
movsd -8(%rbx,%r13), %xmm1 # xmm1 = mem[0],zero
movsd (%rbx,%r13), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.1, %edi
movb $3, %al
callq printf
addq $24, %r13
cmpq $40, %r13
je .LBB1_1
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
movl $16, %r13d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movsd -16(%r14,%r13), %xmm0 # xmm0 = mem[0],zero
movsd -8(%r14,%r13), %xmm1 # xmm1 = mem[0],zero
movsd (%r14,%r13), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.1, %edi
movb $3, %al
callq printf
addq $24, %r13
cmpq $40, %r13
je .LBB1_3
# %bb.4:
movl $.Lstr.2, %edi
callq puts@PLT
movsd (%r15), %xmm0 # xmm0 = mem[0],zero
movsd 8(%r15), %xmm1 # xmm1 = mem[0],zero
movl $.L.str.4, %edi
movb $2, %al
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
movsd (%r12), %xmm0 # xmm0 = mem[0],zero
movsd 8(%r12), %xmm1 # xmm1 = mem[0],zero
movl $.L.str.4, %edi
movb $2, %al
callq printf
movl $.L.str.6, %edi
movl $2, %esi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movl $48, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $48, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movl $48, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $48, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
movl $2, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z16calcEccentricityPdS_S_S_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_7
# %bb.9:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z16__cudaCheckErrorPKci.exit
movq 8(%rsp), %rsi
movl $48, %edx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.4, %edi
callq puts@PLT
movsd (%r12), %xmm0 # xmm0 = mem[0],zero
movsd 8(%r12), %xmm1 # xmm1 = mem[0],zero
movl $.L.str.4, %edi
movb $2, %al
callq printf
movl $.Lstr.5, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
jmp .LBB1_8
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
.LBB1_8:
movl $.L.str.7, %edx
movq %rbx, %rdi
movl $130, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16calcEccentricityPdS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16calcEccentricityPdS_S_S_i,@object # @_Z16calcEccentricityPdS_S_S_i
.section .rodata,"a",@progbits
.globl _Z16calcEccentricityPdS_S_S_i
.p2align 3, 0x0
_Z16calcEccentricityPdS_S_S_i:
.quad _Z31__device_stub__calcEccentricityPdS_S_S_i
.size _Z16calcEccentricityPdS_S_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.16lf %.16lf %.16lf\n"
.size .L.str.1, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.16lf %.16lf\n"
.size .L.str.4, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "numParticles = %d\n"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/exod1a/NbodySimGPU/master/test.hip"
.size .L.str.7, 92
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "cudaCheckError() failed at %s:%i : %s\n"
.size .L.str.11, 39
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "cudaCheckError() with sync failed at %s:%i : %s\n"
.size .L.str.12, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16calcEccentricityPdS_S_S_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "R"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "V"
.size .Lstr.1, 2
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "M"
.size .Lstr.2, 2
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Initial Eccentricity Array"
.size .Lstr.3, 27
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Updated Eccentricity"
.size .Lstr.4, 21
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "What the eccentricity should be"
.size .Lstr.5, 32
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "0.0455862977217524"
.size .Lstr.6, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__calcEccentricityPdS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16calcEccentricityPdS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16calcEccentricityPdS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, 0x5 ; /* 0x00000005ff027424 */
/* 0x000fe200078e00ff */
/*0060*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0070*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*0080*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe40008000000 */
/*0090*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ IADD3 R4, R2, -0x2, RZ ; /* 0xfffffffe02047810 */
/* 0x002fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*00c0*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fe200078e00ff */
/*00e0*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc600078e0205 */
/*0100*/ LDG.E.64 R8, [R6.64+0x8] ; /* 0x0000080a06087981 */
/* 0x001ea8000c1e1b00 */
/*0110*/ LDG.E.64 R16, [R4.64+0x8] ; /* 0x0000080a04107981 */
/* 0x000ea8000c1e1b00 */
/*0120*/ LDG.E.64 R22, [R6.64] ; /* 0x0000000a06167981 */
/* 0x000ee8000c1e1b00 */
/*0130*/ LDG.E.64 R14, [R4.64] ; /* 0x0000000a040e7981 */
/* 0x0000e8000c1e1b00 */
/*0140*/ LDG.E.64 R18, [R6.64+0x10] ; /* 0x0000100a06127981 */
/* 0x000f28000c1e1b00 */
/*0150*/ LDG.E.64 R20, [R4.64+0x10] ; /* 0x0000100a04147981 */
/* 0x000122000c1e1b00 */
/*0160*/ UIADD3 UR7, UP0, UR5, UR8, URZ ; /* 0x0000000805077290 */
/* 0x000fe2000ff1e03f */
/*0170*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0c7624 */
/* 0x000fc400078e00ff */
/*0180*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0d7624 */
/* 0x000fe200078e00ff */
/*0190*/ UIADD3.X UR8, UR6, UR9, URZ, UP0, !UPT ; /* 0x0000000906087290 */
/* 0x000fe400087fe43f */
/*01a0*/ IMAD.U32 R10, RZ, RZ, UR7 ; /* 0x00000007ff0a7e24 */
/* 0x000fc6000f8e00ff */
/*01b0*/ LDG.E.64 R12, [R12.64] ; /* 0x0000000a0c0c7981 */
/* 0x000f62000c1e1b00 */
/*01c0*/ MOV R11, UR8 ; /* 0x00000008000b7c02 */
/* 0x000fcc0008000f00 */
/*01d0*/ LDG.E.64 R10, [R10.64+0x8] ; /* 0x0000080a0a0a7981 */
/* 0x000f62000c1e1b00 */
/*01e0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*01f0*/ ISETP.LE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf03270 */
/*0200*/ DADD R8, -R8, R16 ; /* 0x0000000008087229 */
/* 0x004e0c0000000110 */
/*0210*/ DMUL R4, R8, R8 ; /* 0x0000000808047228 */
/* 0x001fc80000000000 */
/*0220*/ DADD R22, -R22, R14 ; /* 0x0000000016167229 */
/* 0x008e08000000010e */
/*0230*/ DADD R6, -R18, R20 ; /* 0x0000000012067229 */
/* 0x010fc80000000114 */
/*0240*/ DFMA R4, R22, R22, R4 ; /* 0x000000161604722b */
/* 0x001e0c0000000004 */
/*0250*/ DFMA R18, R6, R6, R4 ; /* 0x000000060612722b */
/* 0x001e0c0000000004 */
/*0260*/ MUFU.RSQ64H R5, R19 ; /* 0x0000001300057308 */
/* 0x001e220000001c00 */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0280*/ IADD3 R3, R19, -0x100000, RZ ; /* 0xfff0000013037810 */
/* 0x000fe20007ffe0ff */
/*0290*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff117424 */
/* 0x000fe200078e00ff */
/*02b0*/ ISETP.GE.U32.AND P1, PT, R3, 0x7fe00000, PT ; /* 0x7fe000000300780c */
/* 0x000fe20003f26070 */
/*02c0*/ DMUL R14, R4, R4 ; /* 0x00000004040e7228 */
/* 0x001e0c0000000000 */
/*02d0*/ DFMA R14, R18, -R14, 1 ; /* 0x3ff00000120e742b */
/* 0x001e0c000000080e */
/*02e0*/ DFMA R16, R14, R16, 0.5 ; /* 0x3fe000000e10742b */
/* 0x001fc80000000010 */
/*02f0*/ DMUL R14, R4, R14 ; /* 0x0000000e040e7228 */
/* 0x000e080000000000 */
/*0300*/ DADD R24, R10, R12 ; /* 0x000000000a187229 */
/* 0x020288000000000c */
/*0310*/ DFMA R4, R16, R14, R4 ; /* 0x0000000e1004722b */
/* 0x0012220000000004 */
/*0320*/ @!P1 BRA 0x370 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0330*/ MOV R16, 0x350 ; /* 0x0000035000107802 */
/* 0x006fca0000000f00 */
/*0340*/ CALL.REL.NOINC 0xa30 ; /* 0x000006e000007944 */
/* 0x001fea0003c00000 */
/*0350*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0003 */
/*0360*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fe40000000f00 */
/*0370*/ IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff117424 */
/* 0x006fc800078e00ff */
/*0380*/ IMAD.WIDE R16, R2, R17, c[0x0][0x168] ; /* 0x00005a0002107625 */
/* 0x000fca00078e0211 */
/*0390*/ LDG.E.64 R12, [R16.64+-0x8] ; /* 0xfffff80a100c7981 */
/* 0x000ea8000c1e1b00 */
/*03a0*/ LDG.E.64 R10, [R16.64] ; /* 0x0000000a100a7981 */
/* 0x000ee8000c1e1b00 */
/*03b0*/ LDG.E.64 R14, [R16.64+-0x10] ; /* 0xfffff00a100e7981 */
/* 0x000f22000c1e1b00 */
/*03c0*/ MUFU.RCP64H R21, R25 ; /* 0x0000001900157308 */
/* 0x000e620000001800 */
/*03d0*/ IADD3 R20, R25, 0x300402, RZ ; /* 0x0030040219147810 */
/* 0x000fcc0007ffe0ff */
/*03e0*/ DFMA R18, -R24, R20, 1 ; /* 0x3ff000001812742b */
/* 0x002e4c0000000114 */
/*03f0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x002e4c0000000012 */
/*0400*/ DFMA R18, R20, R18, R20 ; /* 0x000000121412722b */
/* 0x002e620000000014 */
/*0410*/ FSETP.GEU.AND P1, PT, |R20|, 5.8789094863358348022e-39, PT ; /* 0x004004021400780b */
/* 0x000fca0003f2e200 */
/*0420*/ DFMA R26, -R24, R18, 1 ; /* 0x3ff00000181a742b */
/* 0x002e4c0000000112 */
/*0430*/ DFMA R26, R18, R26, R18 ; /* 0x0000001a121a722b */
/* 0x002fc80000000012 */
/*0440*/ DMUL R18, R6, R12 ; /* 0x0000000c06127228 */
/* 0x004e480000000000 */
/*0450*/ DMUL R28, R22, R10 ; /* 0x0000000a161c7228 */
/* 0x008e880000000000 */
/*0460*/ DMUL R30, R8, R14 ; /* 0x0000000e081e7228 */
/* 0x010ec80000000000 */
/*0470*/ DFMA R16, R8, R10, -R18 ; /* 0x0000000a0810722b */
/* 0x0023080000000812 */
/*0480*/ DFMA R18, R6, R14, -R28 ; /* 0x0000000e0612722b */
/* 0x004288000000081c */
/*0490*/ DFMA R20, R22, R12, -R30 ; /* 0x0000000c1614722b */
/* 0x0082e2000000081e */
/*04a0*/ @P1 BRA 0x510 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*04b0*/ LOP3.LUT R30, R25, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff191e7812 */
/* 0x016fe400078ec0ff */
/*04c0*/ MOV R26, 0x4f0 ; /* 0x000004f0001a7802 */
/* 0x000fe40000000f00 */
/*04d0*/ IADD3 R30, R30, -0x100000, RZ ; /* 0xfff000001e1e7810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ CALL.REL.NOINC 0x7f0 ; /* 0x0000030000007944 */
/* 0x009fea0003c00000 */
/*04f0*/ IMAD.MOV.U32 R26, RZ, RZ, R28 ; /* 0x000000ffff1a7224 */
/* 0x003fe400078e001c */
/*0500*/ IMAD.MOV.U32 R27, RZ, RZ, R29 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e001d */
/*0510*/ DMUL R24, R14, R20 ; /* 0x000000140e187228 */
/* 0x01ce880000000000 */
/*0520*/ DMUL R22, R22, R4 ; /* 0x0000000416167228 */
/* 0x003fc80000000000 */
/*0530*/ DMUL R8, R8, R4 ; /* 0x0000000408087228 */
/* 0x000fc80000000000 */
/*0540*/ DMUL R4, R6, R4 ; /* 0x0000000406047228 */
/* 0x000fc80000000000 */
/*0550*/ DMUL R6, R10, R18 ; /* 0x000000120a067228 */
/* 0x000e080000000000 */
/*0560*/ DFMA R24, R10, R16, -R24 ; /* 0x000000100a18722b */
/* 0x004e480000000818 */
/*0570*/ DMUL R16, R12, R16 ; /* 0x000000100c107228 */
/* 0x000e880000000000 */
/*0580*/ DFMA R6, R12, R20, -R6 ; /* 0x000000140c06722b */
/* 0x001e080000000806 */
/*0590*/ DFMA R8, R24, R26, -R8 ; /* 0x0000001a1808722b */
/* 0x002e480000000808 */
/*05a0*/ DFMA R16, R14, R18, -R16 ; /* 0x000000120e10722b */
/* 0x004e880000000810 */
/*05b0*/ DFMA R6, R6, R26, -R22 ; /* 0x0000001a0606722b */
/* 0x001fc80000000816 */
/*05c0*/ DMUL R8, R8, R8 ; /* 0x0000000808087228 */
/* 0x002e080000000000 */
/*05d0*/ DFMA R4, R16, R26, -R4 ; /* 0x0000001a1004722b */
/* 0x004fc80000000804 */
/*05e0*/ DFMA R8, R6, R6, R8 ; /* 0x000000060608722b */
/* 0x001e0c0000000008 */
/*05f0*/ DFMA R10, R4, R4, R8 ; /* 0x00000004040a722b */
/* 0x0010640000000008 */
/*0600*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x001fe200078e00ff */
/*0610*/ MOV R9, 0x3fd80000 ; /* 0x3fd8000000097802 */
/* 0x000fc60000000f00 */
/*0620*/ MUFU.RSQ64H R7, R11 ; /* 0x0000000b00077308 */
/* 0x002e280000001c00 */
/*0630*/ IADD3 R6, R11, -0x3500000, RZ ; /* 0xfcb000000b067810 */
/* 0x000fc80007ffe0ff */
/*0640*/ ISETP.GE.U32.AND P1, PT, R6, 0x7ca00000, PT ; /* 0x7ca000000600780c */
/* 0x000fe40003f26070 */
/*0650*/ DMUL R4, R6, R6 ; /* 0x0000000606047228 */
/* 0x001e0c0000000000 */
/*0660*/ DFMA R4, R10, -R4, 1 ; /* 0x3ff000000a04742b */
/* 0x001e0c0000000804 */
/*0670*/ DFMA R8, R4, R8, 0.5 ; /* 0x3fe000000408742b */
/* 0x001fc80000000008 */
/*0680*/ DMUL R4, R6, R4 ; /* 0x0000000406047228 */
/* 0x000e0c0000000000 */
/*0690*/ DFMA R12, R8, R4, R6 ; /* 0x00000004080c722b */
/* 0x001e0c0000000006 */
/*06a0*/ DMUL R14, R10, R12 ; /* 0x0000000c0a0e7228 */
/* 0x001e080000000000 */
/*06b0*/ IADD3 R9, R13, -0x100000, RZ ; /* 0xfff000000d097810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000c */
/*06d0*/ DFMA R16, R14, -R14, R10 ; /* 0x8000000e0e10722b */
/* 0x001e0c000000000a */
/*06e0*/ DFMA R4, R16, R8, R14 ; /* 0x000000081004722b */
/* 0x001062000000000e */
/*06f0*/ @!P1 BRA 0x740 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0700*/ MOV R4, 0x720 ; /* 0x0000072000047802 */
/* 0x002fca0000000f00 */
/*0710*/ CALL.REL.NOINC 0xc60 ; /* 0x0000054000007944 */
/* 0x001fea0003c00000 */
/*0720*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x002fe400078e0006 */
/*0730*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0007 */
/*0740*/ ULDC.64 UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe20000000a00 */
/*0750*/ IADD3 R2, R2, 0x3, RZ ; /* 0x0000000302027810 */
/* 0x000fe20007ffe0ff */
/*0760*/ UIADD3 UR7, UP0, UR5, UR8, URZ ; /* 0x0000000805077290 */
/* 0x000fc8000ff1e03f */
/*0770*/ UIADD3.X UR8, UR6, UR9, URZ, UP0, !UPT ; /* 0x0000000906087290 */
/* 0x000fe400087fe43f */
/*0780*/ IMAD.U32 R6, RZ, RZ, UR7 ; /* 0x00000007ff067e24 */
/* 0x000fe2000f8e00ff */
/*0790*/ UIADD3 UR5, UP0, UR5, 0x8, URZ ; /* 0x0000000805057890 */
/* 0x000fc6000ff1e03f */
/*07a0*/ MOV R7, UR8 ; /* 0x0000000800077c02 */
/* 0x000fe20008000f00 */
/*07b0*/ UIADD3.X UR6, URZ, UR6, URZ, UP0, !UPT ; /* 0x000000063f067290 */
/* 0x000fc800087fe43f */
/*07c0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0023e2000c101b0a */
/*07d0*/ @!P0 BRA 0xa0 ; /* 0xfffff8c000008947 */
/* 0x000fea000383ffff */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ DSETP.GTU.AND P1, PT, |R24|, +INF , PT ; /* 0x7ff000001800742a */
/* 0x000e1c0003f2c200 */
/*0800*/ @P1 BRA 0x9f0 ; /* 0x000001e000001947 */
/* 0x001fea0003800000 */
/*0810*/ LOP3.LUT R3, R25, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff19037812 */
/* 0x000fc800078ec0ff */
/*0820*/ IADD3 R27, R3, -0x1, RZ ; /* 0xffffffff031b7810 */
/* 0x000fc80007ffe0ff */
/*0830*/ ISETP.GE.U32.AND P1, PT, R27, 0x7fefffff, PT ; /* 0x7fefffff1b00780c */
/* 0x000fda0003f26070 */
/*0840*/ @P1 LOP3.LUT R29, R25, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff00000191d1812 */
/* 0x000fe200078e3cff */
/*0850*/ @P1 IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c1224 */
/* 0x000fe200078e00ff */
/*0860*/ @P1 BRA 0xa10 ; /* 0x000001a000001947 */
/* 0x000fea0003800000 */
/*0870*/ ISETP.GE.U32.AND P1, PT, R3, 0x1000001, PT ; /* 0x010000010300780c */
/* 0x000fda0003f26070 */
/*0880*/ @!P1 BRA 0x960 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0890*/ IADD3 R29, R25, -0x3fe00000, RZ ; /* 0xc0200000191d7810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ IMAD.MOV.U32 R28, RZ, RZ, R24 ; /* 0x000000ffff1c7224 */
/* 0x000fc600078e0018 */
/*08b0*/ MUFU.RCP64H R31, R29 ; /* 0x0000001d001f7308 */
/* 0x000e260000001800 */
/*08c0*/ DFMA R32, -R28, R30, 1 ; /* 0x3ff000001c20742b */
/* 0x001e0c000000011e */
/*08d0*/ DFMA R32, R32, R32, R32 ; /* 0x000000202020722b */
/* 0x001e0c0000000020 */
/*08e0*/ DFMA R32, R30, R32, R30 ; /* 0x000000201e20722b */
/* 0x001e0c000000001e */
/*08f0*/ DFMA R30, -R28, R32, 1 ; /* 0x3ff000001c1e742b */
/* 0x001e0c0000000120 */
/*0900*/ DFMA R30, R32, R30, R32 ; /* 0x0000001e201e722b */
/* 0x001e0c0000000020 */
/*0910*/ DMUL R30, R30, 2.2250738585072013831e-308 ; /* 0x001000001e1e7828 */
/* 0x001e0c0000000000 */
/*0920*/ DFMA R24, -R24, R30, 1 ; /* 0x3ff000001818742b */
/* 0x001e0c000000011e */
/*0930*/ DFMA R24, R24, R24, R24 ; /* 0x000000181818722b */
/* 0x001e0c0000000018 */
/*0940*/ DFMA R28, R30, R24, R30 ; /* 0x000000181e1c722b */
/* 0x001062000000001e */
/*0950*/ BRA 0xa10 ; /* 0x000000b000007947 */
/* 0x000fea0003800000 */
/*0960*/ DMUL R24, R24, 8.11296384146066816958e+31 ; /* 0x4690000018187828 */
/* 0x000e0c0000000000 */
/*0970*/ MUFU.RCP64H R31, R25 ; /* 0x00000019001f7308 */
/* 0x001e240000001800 */
/*0980*/ DFMA R28, -R24, R30, 1 ; /* 0x3ff00000181c742b */
/* 0x001e0c000000011e */
/*0990*/ DFMA R28, R28, R28, R28 ; /* 0x0000001c1c1c722b */
/* 0x001e0c000000001c */
/*09a0*/ DFMA R28, R30, R28, R30 ; /* 0x0000001c1e1c722b */
/* 0x001e0c000000001e */
/*09b0*/ DFMA R30, -R24, R28, 1 ; /* 0x3ff00000181e742b */
/* 0x001e0c000000011c */
/*09c0*/ DFMA R28, R28, R30, R28 ; /* 0x0000001e1c1c722b */
/* 0x001e0c000000001c */
/*09d0*/ DMUL R28, R28, 8.11296384146066816958e+31 ; /* 0x469000001c1c7828 */
/* 0x001e220000000000 */
/*09e0*/ BRA 0xa10 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*09f0*/ LOP3.LUT R29, R25, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000191d7812 */
/* 0x000fe200078efcff */
/*0a00*/ IMAD.MOV.U32 R28, RZ, RZ, R24 ; /* 0x000000ffff1c7224 */
/* 0x000fe400078e0018 */
/*0a10*/ IMAD.MOV.U32 R27, RZ, RZ, 0x0 ; /* 0x00000000ff1b7424 */
/* 0x000fc800078e00ff */
/*0a20*/ RET.REL.NODEC R26 0x0 ; /* 0xfffff5d01a007950 */
/* 0x000fea0003c3ffff */
/*0a30*/ MOV R10, R18 ; /* 0x00000012000a7202 */
/* 0x000fe20000000f00 */
/*0a40*/ IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0013 */
/*0a50*/ LOP3.LUT R4, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013047812 */
/* 0x000fca00078ec0ff */
/*0a60*/ DSETP.NEU.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x000e1c0003f2d000 */
/*0a70*/ @!P1 BRA 0xbf0 ; /* 0x0000017000009947 */
/* 0x001fea0003800000 */
/*0a80*/ DSETP.GTU.AND P1, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e1c0003f2c200 */
/*0a90*/ @P1 BRA 0xbd0 ; /* 0x0000013000001947 */
/* 0x001fea0003800000 */
/*0aa0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f25270 */
/*0ab0*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff041424 */
/* 0x000fe400078e00ff */
/*0ac0*/ @P1 IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff051424 */
/* 0x000fe200078e00ff */
/*0ad0*/ @P1 BRA 0xc10 ; /* 0x0000013000001947 */
/* 0x000fea0003800000 */
/*0ae0*/ DSETP.NEU.AND P1, PT, |R10|, +INF , PT ; /* 0x7ff000000a00742a */
/* 0x000e1c0003f2d200 */
/*0af0*/ @!P1 CS2R R4, SRZ ; /* 0x0000000000049805 */
/* 0x001fe2000001ff00 */
/*0b00*/ @!P1 BRA 0xc10 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0b10*/ DMUL R10, R10, 1.80143985094819840000e+16 ; /* 0x435000000a0a7828 */
/* 0x000e220000000000 */
/*0b20*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0b30*/ MOV R14, 0x0 ; /* 0x00000000000e7802 */
/* 0x000fe20000000f00 */
/*0b40*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0f7424 */
/* 0x000fc600078e00ff */
/*0b50*/ MUFU.RSQ64H R5, R11 ; /* 0x0000000b00057308 */
/* 0x001e240000001c00 */
/*0b60*/ DMUL R12, R4, R4 ; /* 0x00000004040c7228 */
/* 0x001e0c0000000000 */
/*0b70*/ DFMA R12, R10, -R12, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c000000080c */
/*0b80*/ DFMA R14, R12, R14, 0.5 ; /* 0x3fe000000c0e742b */
/* 0x001fc8000000000e */
/*0b90*/ DMUL R12, R4, R12 ; /* 0x0000000c040c7228 */
/* 0x000e0c0000000000 */
/*0ba0*/ DFMA R4, R14, R12, R4 ; /* 0x0000000c0e04722b */
/* 0x001e0c0000000004 */
/*0bb0*/ DMUL R4, R4, 134217728 ; /* 0x41a0000004047828 */
/* 0x001e220000000000 */
/*0bc0*/ BRA 0xc10 ; /* 0x0000004000007947 */
/* 0x000ff20003800000 */
/*0bd0*/ DADD R4, R10, R10 ; /* 0x000000000a047229 */
/* 0x000062000000000a */
/*0be0*/ BRA 0xc10 ; /* 0x0000002000007947 */
/* 0x000ff20003800000 */
/*0bf0*/ LOP3.LUT R5, R4, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000004057812 */
/* 0x000fe200078efcff */
/*0c00*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc800078e00ff */
/*0c10*/ IMAD.MOV.U32 R3, RZ, RZ, R4 ; /* 0x000000ffff037224 */
/* 0x003fe200078e0004 */
/*0c20*/ MOV R10, R5 ; /* 0x00000005000a7202 */
/* 0x000fe20000000f00 */
/*0c30*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0010 */
/*0c40*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0c50*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff3a004007950 */
/* 0x000fea0003c3ffff */
/*0c60*/ ISETP.GE.U32.AND P1, PT, R6, -0x3400000, PT ; /* 0xfcc000000600780c */
/* 0x000fe20003f26070 */
/*0c70*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0009 */
/*0c80*/ MOV R8, R10 ; /* 0x0000000a00087202 */
/* 0x000fe20000000f00 */
/*0c90*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000b */
/*0ca0*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*0cb0*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fcc00078e0011 */
/*0cc0*/ @!P1 BRA 0xd50 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*0cd0*/ DFMA.RM R6, R6, R12, R14 ; /* 0x0000000c0606722b */
/* 0x000e14000000400e */
/*0ce0*/ IADD3 R10, P1, R6, 0x1, RZ ; /* 0x00000001060a7810 */
/* 0x001fc80007f3e0ff */
/*0cf0*/ IADD3.X R11, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff0b7210 */
/* 0x000fcc0000ffe4ff */
/*0d00*/ DFMA.RP R8, -R6, R10, R8 ; /* 0x0000000a0608722b */
/* 0x000e0c0000008108 */
/*0d10*/ DSETP.GT.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800722a */
/* 0x001e0c0003f24000 */
/*0d20*/ FSEL R6, R10, R6, P1 ; /* 0x000000060a067208 */
/* 0x001fe40000800000 */
/*0d30*/ FSEL R7, R11, R7, P1 ; /* 0x000000070b077208 */
/* 0x000fe20000800000 */
/*0d40*/ BRA 0xee0 ; /* 0x0000019000007947 */
/* 0x000fea0003800000 */
/*0d50*/ DSETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800722a */
/* 0x000e1c0003f25000 */
/*0d60*/ @!P1 BRA 0xed0 ; /* 0x0000016000009947 */
/* 0x001fea0003800000 */
/*0d70*/ ISETP.GE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f26270 */
/*0d80*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff069424 */
/* 0x000fe400078e00ff */
/*0d90*/ @!P1 IMAD.MOV.U32 R7, RZ, RZ, -0x80000 ; /* 0xfff80000ff079424 */
/* 0x000fe200078e00ff */
/*0da0*/ @!P1 BRA 0xee0 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0db0*/ ISETP.GT.AND P1, PT, R9, 0x7fefffff, PT ; /* 0x7fefffff0900780c */
/* 0x000fda0003f24270 */
/*0dc0*/ @P1 BRA 0xed0 ; /* 0x0000010000001947 */
/* 0x000fea0003800000 */
/*0dd0*/ DMUL R6, R8, 8.11296384146066816958e+31 ; /* 0x4690000008067828 */
/* 0x0000620000000000 */
/*0de0*/ MOV R12, 0x0 ; /* 0x00000000000c7802 */
/* 0x000fe20000000f00 */
/*0df0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0e00*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fd80000 ; /* 0x3fd80000ff0d7424 */
/* 0x000fe400078e00ff */
/*0e10*/ MUFU.RSQ64H R9, R7 ; /* 0x0000000700097308 */
/* 0x002e240000001c00 */
/*0e20*/ DMUL R10, R8, R8 ; /* 0x00000008080a7228 */
/* 0x001e0c0000000000 */
/*0e30*/ DFMA R10, R6, -R10, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c000000080a */
/*0e40*/ DFMA R12, R10, R12, 0.5 ; /* 0x3fe000000a0c742b */
/* 0x001fc8000000000c */
/*0e50*/ DMUL R10, R8, R10 ; /* 0x0000000a080a7228 */
/* 0x000e0c0000000000 */
/*0e60*/ DFMA R10, R12, R10, R8 ; /* 0x0000000a0c0a722b */
/* 0x001e0c0000000008 */
/*0e70*/ DMUL R8, R6, R10 ; /* 0x0000000a06087228 */
/* 0x0010480000000000 */
/*0e80*/ IADD3 R11, R11, -0x100000, RZ ; /* 0xfff000000b0b7810 */
/* 0x001fe40007ffe0ff */
/*0e90*/ DFMA R12, R8, -R8, R6 ; /* 0x80000008080c722b */
/* 0x002e0c0000000006 */
/*0ea0*/ DFMA R6, R10, R12, R8 ; /* 0x0000000c0a06722b */
/* 0x001e140000000008 */
/*0eb0*/ IADD3 R7, R7, -0x3500000, RZ ; /* 0xfcb0000007077810 */
/* 0x001fe20007ffe0ff */
/*0ec0*/ BRA 0xee0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ed0*/ DADD R6, R8, R8 ; /* 0x0000000008067229 */
/* 0x0000480000000008 */
/*0ee0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0ef0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff10004007950 */
/* 0x000fea0003c3ffff */
/*0f00*/ BRA 0xf00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16calcEccentricityPdS_S_S_i
.globl _Z16calcEccentricityPdS_S_S_i
.p2align 8
.type _Z16calcEccentricityPdS_S_S_i,@function
_Z16calcEccentricityPdS_S_S_i:
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_3
s_load_b256 s[4:11], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_add_i32 s1, s2, -1
s_mov_b64 s[2:3], 0
s_mov_b64 s[12:13], 0
s_waitcnt lgkmcnt(0)
s_add_u32 s14, s8, 8
s_addc_u32 s15, s9, 0
.LBB0_2:
s_add_u32 s16, s14, s12
s_addc_u32 s17, s15, s13
s_clause 0x2
global_load_b64 v[13:14], v0, s[8:9]
global_load_b64 v[15:16], v0, s[16:17]
global_load_b128 v[1:4], v0, s[4:5]
s_add_u32 s16, s4, s2
s_addc_u32 s17, s5, s3
s_clause 0x2
global_load_b128 v[5:8], v0, s[16:17] offset:24
global_load_b64 v[17:18], v0, s[4:5] offset:16
global_load_b64 v[19:20], v0, s[16:17] offset:40
s_add_u32 s16, s6, s2
s_addc_u32 s17, s7, s3
s_clause 0x1
global_load_b128 v[9:12], v0, s[16:17] offset:24
global_load_b64 v[21:22], v0, s[16:17] offset:40
s_waitcnt vmcnt(6)
v_add_f64 v[13:14], v[13:14], v[15:16]
s_waitcnt vmcnt(4)
v_add_f64 v[3:4], v[7:8], -v[3:4]
v_add_f64 v[1:2], v[5:6], -v[1:2]
s_waitcnt vmcnt(2)
v_add_f64 v[17:18], v[19:20], -v[17:18]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_div_scale_f64 v[7:8], null, v[13:14], v[13:14], 1.0
v_div_scale_f64 v[25:26], vcc_lo, 1.0, v[13:14], 1.0
v_mul_f64 v[5:6], v[3:4], v[3:4]
s_waitcnt vmcnt(1)
v_mul_f64 v[29:30], v[17:18], v[11:12]
s_waitcnt vmcnt(0)
v_mul_f64 v[31:32], v[1:2], v[21:22]
v_rcp_f64_e32 v[15:16], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[1:2], v[1:2], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[19:20], -v[7:8], v[15:16], 1.0
v_fma_f64 v[5:6], v[17:18], v[17:18], v[5:6]
v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[19:20], v[5:6]
v_fma_f64 v[23:24], -v[7:8], v[15:16], 1.0
s_waitcnt_depctr 0xfff
v_mul_f64 v[5:6], v[19:20], -v[5:6]
v_cmp_class_f64_e64 s0, v[19:20], 0x180
v_fma_f64 v[15:16], v[15:16], v[23:24], v[15:16]
v_mul_f64 v[23:24], v[3:4], v[9:10]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[5:6], v[5:6], v[19:20], 1.0
v_mul_f64 v[27:28], v[25:26], v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[23:24], v[1:2], v[11:12], -v[23:24]
v_mul_f64 v[33:34], v[19:20], v[5:6]
v_fma_f64 v[5:6], v[5:6], 0x3fd80000, 0.5
s_delay_alu instid0(VALU_DEP_4)
v_fma_f64 v[7:8], -v[7:8], v[27:28], v[25:26]
v_fma_f64 v[25:26], v[3:4], v[21:22], -v[29:30]
v_fma_f64 v[29:30], v[17:18], v[9:10], -v[31:32]
v_mul_f64 v[31:32], v[9:10], v[23:24]
v_fma_f64 v[5:6], v[33:34], v[5:6], v[19:20]
v_div_fmas_f64 v[7:8], v[7:8], v[15:16], v[27:28]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[15:16], v[21:22], v[29:30]
v_fma_f64 v[21:22], v[21:22], v[25:26], -v[31:32]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, v20, v6, s0
v_cndmask_b32_e64 v5, v19, v5, s0
v_mul_f64 v[3:4], v[3:4], v[5:6]
v_mul_f64 v[1:2], v[1:2], v[5:6]
v_mul_f64 v[5:6], v[17:18], v[5:6]
v_div_fixup_f64 v[7:8], v[7:8], v[13:14], 1.0
v_mul_f64 v[13:14], v[11:12], v[25:26]
v_fma_f64 v[11:12], v[11:12], v[23:24], -v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[3:4], v[7:8], v[21:22], -v[3:4]
v_fma_f64 v[9:10], v[9:10], v[29:30], -v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[1:2], v[7:8], v[11:12], -v[1:2]
v_mul_f64 v[3:4], v[3:4], v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[7:8], v[9:10], -v[5:6]
v_fma_f64 v[1:2], v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[1:2], v[5:6], v[5:6], v[1:2]
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[1:2]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_and_b32 s0, vcc_lo, exec_lo
s_cselect_b32 s0, 0xffffff80, 0
s_add_u32 s16, s10, s12
s_addc_u32 s17, s11, s13
v_lshlrev_b32_e32 v3, 8, v3
s_add_i32 s1, s1, -1
s_add_u32 s12, s12, 8
s_addc_u32 s13, s13, 0
s_add_u32 s2, s2, 24
v_ldexp_f64 v[1:2], v[1:2], v3
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rsq_f64_e32 v[3:4], v[1:2]
v_cmp_class_f64_e64 vcc_lo, v[1:2], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[5:6], v[1:2], v[3:4]
v_mul_f64 v[3:4], v[3:4], 0.5
v_fma_f64 v[7:8], -v[3:4], v[5:6], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_fma_f64 v[3:4], v[3:4], v[7:8], v[3:4]
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[7:8], v[3:4], v[5:6]
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[7:8], v[3:4], v[5:6]
v_ldexp_f64 v[3:4], v[3:4], s0
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v1, v3, v1
global_store_b64 v0, v[1:2], s[16:17]
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16calcEccentricityPdS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 35
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16calcEccentricityPdS_S_S_i, .Lfunc_end0-_Z16calcEccentricityPdS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16calcEccentricityPdS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z16calcEccentricityPdS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 35
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00076772_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z16__cudaCheckErrorPKci.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaCheckError() failed at %s:%i : %s\n"
.align 8
.LC1:
.string "cudaCheckError() with sync failed at %s:%i : %s\n"
.section .text._Z16__cudaCheckErrorPKci,"axG",@progbits,_Z16__cudaCheckErrorPKci,comdat
.weak _Z16__cudaCheckErrorPKci
.type _Z16__cudaCheckErrorPKci, @function
_Z16__cudaCheckErrorPKci:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %ebp
call cudaGetLastError@PLT
testl %eax, %eax
jne .L7
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L8
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L8:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z16__cudaCheckErrorPKci, .-_Z16__cudaCheckErrorPKci
.text
.globl _Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i
.type _Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i, @function
_Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16calcEccentricityPdS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i, .-_Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i
.globl _Z16calcEccentricityPdS_S_S_i
.type _Z16calcEccentricityPdS_S_S_i, @function
_Z16calcEccentricityPdS_S_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16calcEccentricityPdS_S_S_i, .-_Z16calcEccentricityPdS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "R\n"
.LC8:
.string "%.16lf %.16lf %.16lf\n"
.LC9:
.string "V\n"
.LC10:
.string "M\n"
.LC11:
.string "%.16lf %.16lf\n"
.LC12:
.string "Initial Eccentricity Array\n"
.LC13:
.string "numParticles = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC14:
.string "/home/ubuntu/Datasets/stackv2/train-structured/exod1a/NbodySimGPU/master/test.cu"
.section .rodata.str1.1
.LC15:
.string "Updated Eccentricity\n"
.section .rodata.str1.8
.align 8
.LC16:
.string "What the eccentricity should be\n"
.section .rodata.str1.1
.LC17:
.string "0.0455862977217524\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $48, %edi
call malloc@PLT
movq %rax, %rbp
movl $48, %edi
call malloc@PLT
movq %rax, %rbx
movl $16, %edi
call malloc@PLT
movq %rax, %r13
movl $16, %edi
call malloc@PLT
movq %rax, %r12
movq $0x000000000, 0(%rbp)
movq $0x000000000, 8(%rbp)
movq $0x000000000, 16(%rbp)
movq .LC3(%rip), %rax
movq %rax, 24(%rbp)
movq $0x000000000, 32(%rbp)
movq $0x000000000, 40(%rbp)
movq $0x000000000, (%rbx)
movq $0x000000000, 8(%rbx)
movq $0x000000000, 16(%rbx)
movq $0x000000000, 24(%rbx)
movq .LC4(%rip), %rax
movq %rax, 32(%rbx)
movq $0x000000000, 40(%rbx)
movq .LC5(%rip), %rax
movq %rax, 0(%r13)
movq .LC6(%rip), %rax
movq %rax, 8(%r13)
movq $0x000000000, (%r12)
movq $0x000000000, 8(%r12)
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 0(%rbp), %xmm0
movsd 16(%rbp), %xmm2
movsd 8(%rbp), %xmm1
leaq .LC8(%rip), %r14
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movsd 24(%rbp), %xmm0
movsd 40(%rbp), %xmm2
movsd 32(%rbp), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd (%rbx), %xmm0
movsd 16(%rbx), %xmm2
movsd 8(%rbx), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movsd 24(%rbx), %xmm0
movsd 40(%rbx), %xmm2
movsd 32(%rbx), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 0(%r13), %xmm0
movsd 8(%r13), %xmm1
leaq .LC11(%rip), %r14
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd (%r12), %xmm0
movsd 8(%r12), %xmm1
movq %r14, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $2, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $48, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $48, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $48, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $48, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
movl $130, %esi
leaq .LC14(%rip), %rdi
call _Z16__cudaCheckErrorPKci
movl $2, %ecx
movl $48, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd (%r12), %xmm0
movsd 8(%r12), %xmm1
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $2, %r8d
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z43__device_stub__Z16calcEccentricityPdS_S_S_iPdS_S_S_i
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z16calcEccentricityPdS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z16calcEccentricityPdS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 1666944813
.long 1070077944
.align 8
.LC4:
.long 198829386
.long 1073873819
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC6:
.long -1450121176
.long 1049375159
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z31__device_stub__calcEccentricityPdS_S_S_i # -- Begin function _Z31__device_stub__calcEccentricityPdS_S_S_i
.p2align 4, 0x90
.type _Z31__device_stub__calcEccentricityPdS_S_S_i,@function
_Z31__device_stub__calcEccentricityPdS_S_S_i: # @_Z31__device_stub__calcEccentricityPdS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16calcEccentricityPdS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z31__device_stub__calcEccentricityPdS_S_S_i, .Lfunc_end0-_Z31__device_stub__calcEccentricityPdS_S_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $176, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $48, %edi
callq malloc
movq %rax, %rbx
movl $48, %edi
callq malloc
movq %rax, %r14
movl $16, %r13d
movl $16, %edi
callq malloc
movq %rax, %r15
movl $16, %edi
callq malloc
movq %rax, %r12
xorps %xmm0, %xmm0
movups %xmm0, (%rbx)
movq $0, 16(%rbx)
movabsq $4595949775317864237, %rax # imm = 0x3FC817F8635B8F2D
movq %rax, 24(%rbx)
movups %xmm0, 32(%rbx)
movups %xmm0, 16(%r14)
movups %xmm0, (%r14)
movabsq $4612252932834452810, %rax # imm = 0x4002039B0BD9E54A
movq %rax, 32(%r14)
movq $0, 40(%r14)
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, (%r15)
movabsq $4507031991984646184, %rax # imm = 0x3E8C31B7A990E828
movq %rax, 8(%r15)
movups %xmm0, (%r12)
movl $.Lstr, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movsd -16(%rbx,%r13), %xmm0 # xmm0 = mem[0],zero
movsd -8(%rbx,%r13), %xmm1 # xmm1 = mem[0],zero
movsd (%rbx,%r13), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.1, %edi
movb $3, %al
callq printf
addq $24, %r13
cmpq $40, %r13
je .LBB1_1
# %bb.2:
movl $.Lstr.1, %edi
callq puts@PLT
movl $16, %r13d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movsd -16(%r14,%r13), %xmm0 # xmm0 = mem[0],zero
movsd -8(%r14,%r13), %xmm1 # xmm1 = mem[0],zero
movsd (%r14,%r13), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.1, %edi
movb $3, %al
callq printf
addq $24, %r13
cmpq $40, %r13
je .LBB1_3
# %bb.4:
movl $.Lstr.2, %edi
callq puts@PLT
movsd (%r15), %xmm0 # xmm0 = mem[0],zero
movsd 8(%r15), %xmm1 # xmm1 = mem[0],zero
movl $.L.str.4, %edi
movb $2, %al
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
movsd (%r12), %xmm0 # xmm0 = mem[0],zero
movsd 8(%r12), %xmm1 # xmm1 = mem[0],zero
movl $.L.str.4, %edi
movb $2, %al
callq printf
movl $.L.str.6, %edi
movl $2, %esi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movl $48, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $48, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movl $48, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $48, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
movl $2, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z16calcEccentricityPdS_S_S_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_7
# %bb.9:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z16__cudaCheckErrorPKci.exit
movq 8(%rsp), %rsi
movl $48, %edx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.4, %edi
callq puts@PLT
movsd (%r12), %xmm0 # xmm0 = mem[0],zero
movsd 8(%r12), %xmm1 # xmm1 = mem[0],zero
movl $.L.str.4, %edi
movb $2, %al
callq printf
movl $.Lstr.5, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
jmp .LBB1_8
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
.LBB1_8:
movl $.L.str.7, %edx
movq %rbx, %rdi
movl $130, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16calcEccentricityPdS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16calcEccentricityPdS_S_S_i,@object # @_Z16calcEccentricityPdS_S_S_i
.section .rodata,"a",@progbits
.globl _Z16calcEccentricityPdS_S_S_i
.p2align 3, 0x0
_Z16calcEccentricityPdS_S_S_i:
.quad _Z31__device_stub__calcEccentricityPdS_S_S_i
.size _Z16calcEccentricityPdS_S_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.16lf %.16lf %.16lf\n"
.size .L.str.1, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.16lf %.16lf\n"
.size .L.str.4, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "numParticles = %d\n"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/exod1a/NbodySimGPU/master/test.hip"
.size .L.str.7, 92
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "cudaCheckError() failed at %s:%i : %s\n"
.size .L.str.11, 39
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "cudaCheckError() with sync failed at %s:%i : %s\n"
.size .L.str.12, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16calcEccentricityPdS_S_S_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "R"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "V"
.size .Lstr.1, 2
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "M"
.size .Lstr.2, 2
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Initial Eccentricity Array"
.size .Lstr.3, 27
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Updated Eccentricity"
.size .Lstr.4, 21
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "What the eccentricity should be"
.size .Lstr.5, 32
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "0.0455862977217524"
.size .Lstr.6, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__calcEccentricityPdS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16calcEccentricityPdS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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