system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
namespace ann {
// CUDA2
}
__global__ void kernel(int n, float *arr){
volatile int idx = threadIdx.x + blockDim.x*blockIdx.x;
if(idx >= n) return;
arr[idx] *= 2.0f;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kerneliPf
.globl _Z6kerneliPf
.p2align 8
.type _Z6kerneliPf,@function
_Z6kerneliPf:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b64 s[2:3], src_private_base
s_mov_b32 s2, 4
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
s_load_b32 s2, s[0:1], 0x0
flat_store_b32 v[2:3], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_mov_b64 s[2:3], src_private_base
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, s3
s_load_b64 s[0:1], s[0:1], 0x8
flat_load_b32 v0, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kerneliPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 8
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kerneliPf, .Lfunc_end0-_Z6kerneliPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kerneliPf
.private_segment_fixed_size: 8
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kerneliPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
namespace ann {
// CUDA2
}
__global__ void kernel(int n, float *arr){
volatile int idx = threadIdx.x + blockDim.x*blockIdx.x;
if(idx >= n) return;
arr[idx] *= 2.0f;
} | .text
.file "kernel.hip"
.globl _Z21__device_stub__kerneliPf # -- Begin function _Z21__device_stub__kerneliPf
.p2align 4, 0x90
.type _Z21__device_stub__kerneliPf,@function
_Z21__device_stub__kerneliPf: # @_Z21__device_stub__kerneliPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kerneliPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kerneliPf, .Lfunc_end0-_Z21__device_stub__kerneliPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kerneliPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kerneliPf,@object # @_Z6kerneliPf
.section .rodata,"a",@progbits
.globl _Z6kerneliPf
.p2align 3, 0x0
_Z6kerneliPf:
.quad _Z21__device_stub__kerneliPf
.size _Z6kerneliPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kerneliPf"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kerneliPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kerneliPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kerneliPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FADD R5, R0, R0 ; /* 0x0000000000057221 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kerneliPf
.globl _Z6kerneliPf
.p2align 8
.type _Z6kerneliPf,@function
_Z6kerneliPf:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b64 s[2:3], src_private_base
s_mov_b32 s2, 4
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
s_load_b32 s2, s[0:1], 0x0
flat_store_b32 v[2:3], v1 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_mov_b64 s[2:3], src_private_base
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, s3
s_load_b64 s[0:1], s[0:1], 0x8
flat_load_b32 v0, v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kerneliPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 8
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kerneliPf, .Lfunc_end0-_Z6kerneliPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kerneliPf
.private_segment_fixed_size: 8
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kerneliPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00045d3f_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kerneliPfiPf
.type _Z26__device_stub__Z6kerneliPfiPf, @function
_Z26__device_stub__Z6kerneliPfiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kerneliPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6kerneliPfiPf, .-_Z26__device_stub__Z6kerneliPfiPf
.globl _Z6kerneliPf
.type _Z6kerneliPf, @function
_Z6kerneliPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kerneliPfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6kerneliPf, .-_Z6kerneliPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kerneliPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kerneliPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z21__device_stub__kerneliPf # -- Begin function _Z21__device_stub__kerneliPf
.p2align 4, 0x90
.type _Z21__device_stub__kerneliPf,@function
_Z21__device_stub__kerneliPf: # @_Z21__device_stub__kerneliPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kerneliPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kerneliPf, .Lfunc_end0-_Z21__device_stub__kerneliPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kerneliPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kerneliPf,@object # @_Z6kerneliPf
.section .rodata,"a",@progbits
.globl _Z6kerneliPf
.p2align 3, 0x0
_Z6kerneliPf:
.quad _Z21__device_stub__kerneliPf
.size _Z6kerneliPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kerneliPf"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kerneliPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kerneliPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
int main(void){
cudaDeviceProp prop;
if(cudaGetDeviceProperties(&prop, 0) != cudaSuccess){
fprintf(stderr, "no device avalible, go a hell, man\n");
}
fprintf(stdout, "get prop success\n");
fprintf(stdout, " name: %s\n", prop.name);
fprintf(stdout, " totalGlobalMem: %lu\n", prop.totalGlobalMem);
fprintf(stdout, " sharedMemPerBlock: %lu\n", prop.sharedMemPerBlock);
fprintf(stdout, " regsPerBlock: %d\n", prop.regsPerBlock);
fprintf(stdout, " warpSize: %d\n", prop.warpSize);
fprintf(stdout, " memPitch: %lu\n", prop.memPitch);
fprintf(stdout, " maxThreadsPerBlock: %d\n", prop.maxThreadsPerBlock);
fprintf(stdout, " maxThreadsDim:\n");
fprintf(stdout, " maxThreadsDim[0]: %d\n", prop.maxThreadsDim[0]);
fprintf(stdout, " maxThreadsDim[1]: %d\n", prop.maxThreadsDim[1]);
fprintf(stdout, " maxThreadsDim[2]: %d\n", prop.maxThreadsDim[2]);
fprintf(stdout, " maxThreadsGridSize:\n");
fprintf(stdout, " maxGridSize[0]: %d\n", prop.maxGridSize[0]);
fprintf(stdout, " maxGridSize[1]: %d\n", prop.maxGridSize[1]);
fprintf(stdout, " maxGridSize[2]: %d\n", prop.maxGridSize[2]);
fprintf(stdout, " clockRate: %d\n", prop.clockRate);
fprintf(stdout, " totalConstMem: %lu\n", prop.totalConstMem);
fprintf(stdout, " major.minor: %d.%d\n", prop.major, prop.minor);
fprintf(stdout, " textureAlignment: %lu\n", prop.textureAlignment);
fprintf(stdout, " texturePitchAlignment: %lu\n", prop.texturePitchAlignment);
fprintf(stdout, " deviceOverlap: %d\n", prop.deviceOverlap);
fprintf(stdout, " multiProcessorCount: %d\n", prop.multiProcessorCount);
fprintf(stdout, " kernelExecTimeoutEnabled: %d\n", prop.kernelExecTimeoutEnabled);
fprintf(stdout, " integrated: %d\n", prop.integrated);
fprintf(stdout, " canMapHostMemory: %d\n", prop.canMapHostMemory);
fprintf(stdout, " computeMode: %d\n", prop.computeMode);
fprintf(stdout, " maxTexture1D: %d\n", prop.maxTexture1D);
fprintf(stdout, " maxTexture1DLinear: %d\n", prop.maxTexture1DLinear);
fprintf(stdout, " maxTexture2D\n");
fprintf(stdout, " maxTexture2D[0]: %d\n", prop.maxTexture2D[0]);
fprintf(stdout, " maxTexture2D[1]: %d\n", prop.maxTexture2D[1]);
fprintf(stdout, " maxTexture2DLinear\n");
fprintf(stdout, " maxTexture2DLinear[0]: %d\n", prop.maxTexture2DLinear[0]);
fprintf(stdout, " maxTexture2DLinear[1]: %d\n", prop.maxTexture2DLinear[1]);
fprintf(stdout, " maxTexture2DLinear[2]: %d\n", prop.maxTexture2DLinear[2]);
fprintf(stdout, " maxTexture2DGather\n");
fprintf(stdout, " maxTexture2DGather[0]: %d\n", prop.maxTexture2DGather[0]);
fprintf(stdout, " maxTexture2DGather[1]: %d\n", prop.maxTexture2DGather[1]);
fprintf(stdout, " maxTexture3D\n");
fprintf(stdout, " maxTexture3D[0]: %d\n", prop.maxTexture3D[0]);
fprintf(stdout, " maxTexture3D[1]: %d\n", prop.maxTexture3D[1]);
fprintf(stdout, " maxTexture3D[2]: %d\n", prop.maxTexture3D[2]);
fprintf(stdout, " maxSurface1D: %d\n", prop.maxSurface1D);
fprintf(stdout, " maxSurface2D\n");
fprintf(stdout, " maxSurface2D[0]: %d\n", prop.maxSurface2D[0]);
fprintf(stdout, " maxSurface2D[1]: %d\n", prop.maxSurface2D[1]);
fprintf(stdout, " maxSurface3D\n");
fprintf(stdout, " maxSueface3D[0]: %d\n", prop.maxSurface3D[0]);
fprintf(stdout, " maxSueface3D[1]: %d\n", prop.maxSurface3D[1]);
fprintf(stdout, " maxSueface3D[2]: %d\n", prop.maxSurface3D[2]);
fprintf(stdout, " maxSurface1DLayered\n");
fprintf(stdout, " maxSurface1DLayered[0]: %d\n", prop.maxSurface1DLayered[0]);
fprintf(stdout, " maxSurface1DLayered[1]: %d\n", prop.maxSurface1DLayered[1]);
fprintf(stdout, " maxSurface2DLayered\n");
fprintf(stdout, " maxSurface2DLayered[0]: %d\n", prop.maxSurface2DLayered[0]);
fprintf(stdout, " maxSurface2DLayered[1]: %d\n", prop.maxSurface2DLayered[1]);
fprintf(stdout, " maxSurface2DLayered[2]: %d\n", prop.maxSurface2DLayered[2]);
fprintf(stdout, " maxSurfaceCubemap: %d\n", prop.maxSurfaceCubemap);
fprintf(stdout, " maxSurfaceCubemapLayered\n");
fprintf(stdout, " maxSurfaceCubemapLayered[0]: %d\n", prop.maxSurfaceCubemapLayered[0]);
fprintf(stdout, " maxSurfaceCubemapLayered[1]: %d\n", prop.maxSurfaceCubemapLayered[1]);
fprintf(stdout, " surfaceAlignment: %ld\n", prop.surfaceAlignment);
fprintf(stdout, " concurrentKernels: %d\n", prop.concurrentKernels);
fprintf(stdout, " ECCEnabled: %d\n", prop.ECCEnabled);
fprintf(stdout, " pciBusID: %d\n", prop.pciBusID);
fprintf(stdout, " pciDeviceID: %d\n", prop.pciDeviceID);
fprintf(stdout, " pciDomainID: %d\n", prop.pciDomainID);
fprintf(stdout, " tccDriver: %d\n", prop.tccDriver);
fprintf(stdout, " asyncEngineCount: %d\n", prop.asyncEngineCount);
fprintf(stdout, " unifiedAddressing: %d\n", prop.unifiedAddressing);
fprintf(stdout, " memoryClockRate: %d\n", prop.memoryClockRate);
fprintf(stdout, " l2CacheSize: %d\n", prop.l2CacheSize);
fprintf(stdout, " maxThreadsPerMultiProcessor: %d\n", prop.maxThreadsPerMultiProcessor);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
int main(void){
cudaDeviceProp prop;
if(cudaGetDeviceProperties(&prop, 0) != cudaSuccess){
fprintf(stderr, "no device avalible, go a hell, man\n");
}
fprintf(stdout, "get prop success\n");
fprintf(stdout, " name: %s\n", prop.name);
fprintf(stdout, " totalGlobalMem: %lu\n", prop.totalGlobalMem);
fprintf(stdout, " sharedMemPerBlock: %lu\n", prop.sharedMemPerBlock);
fprintf(stdout, " regsPerBlock: %d\n", prop.regsPerBlock);
fprintf(stdout, " warpSize: %d\n", prop.warpSize);
fprintf(stdout, " memPitch: %lu\n", prop.memPitch);
fprintf(stdout, " maxThreadsPerBlock: %d\n", prop.maxThreadsPerBlock);
fprintf(stdout, " maxThreadsDim:\n");
fprintf(stdout, " maxThreadsDim[0]: %d\n", prop.maxThreadsDim[0]);
fprintf(stdout, " maxThreadsDim[1]: %d\n", prop.maxThreadsDim[1]);
fprintf(stdout, " maxThreadsDim[2]: %d\n", prop.maxThreadsDim[2]);
fprintf(stdout, " maxThreadsGridSize:\n");
fprintf(stdout, " maxGridSize[0]: %d\n", prop.maxGridSize[0]);
fprintf(stdout, " maxGridSize[1]: %d\n", prop.maxGridSize[1]);
fprintf(stdout, " maxGridSize[2]: %d\n", prop.maxGridSize[2]);
fprintf(stdout, " clockRate: %d\n", prop.clockRate);
fprintf(stdout, " totalConstMem: %lu\n", prop.totalConstMem);
fprintf(stdout, " major.minor: %d.%d\n", prop.major, prop.minor);
fprintf(stdout, " textureAlignment: %lu\n", prop.textureAlignment);
fprintf(stdout, " texturePitchAlignment: %lu\n", prop.texturePitchAlignment);
fprintf(stdout, " deviceOverlap: %d\n", prop.deviceOverlap);
fprintf(stdout, " multiProcessorCount: %d\n", prop.multiProcessorCount);
fprintf(stdout, " kernelExecTimeoutEnabled: %d\n", prop.kernelExecTimeoutEnabled);
fprintf(stdout, " integrated: %d\n", prop.integrated);
fprintf(stdout, " canMapHostMemory: %d\n", prop.canMapHostMemory);
fprintf(stdout, " computeMode: %d\n", prop.computeMode);
fprintf(stdout, " maxTexture1D: %d\n", prop.maxTexture1D);
fprintf(stdout, " maxTexture1DLinear: %d\n", prop.maxTexture1DLinear);
fprintf(stdout, " maxTexture2D\n");
fprintf(stdout, " maxTexture2D[0]: %d\n", prop.maxTexture2D[0]);
fprintf(stdout, " maxTexture2D[1]: %d\n", prop.maxTexture2D[1]);
fprintf(stdout, " maxTexture2DLinear\n");
fprintf(stdout, " maxTexture2DLinear[0]: %d\n", prop.maxTexture2DLinear[0]);
fprintf(stdout, " maxTexture2DLinear[1]: %d\n", prop.maxTexture2DLinear[1]);
fprintf(stdout, " maxTexture2DLinear[2]: %d\n", prop.maxTexture2DLinear[2]);
fprintf(stdout, " maxTexture2DGather\n");
fprintf(stdout, " maxTexture2DGather[0]: %d\n", prop.maxTexture2DGather[0]);
fprintf(stdout, " maxTexture2DGather[1]: %d\n", prop.maxTexture2DGather[1]);
fprintf(stdout, " maxTexture3D\n");
fprintf(stdout, " maxTexture3D[0]: %d\n", prop.maxTexture3D[0]);
fprintf(stdout, " maxTexture3D[1]: %d\n", prop.maxTexture3D[1]);
fprintf(stdout, " maxTexture3D[2]: %d\n", prop.maxTexture3D[2]);
fprintf(stdout, " maxSurface1D: %d\n", prop.maxSurface1D);
fprintf(stdout, " maxSurface2D\n");
fprintf(stdout, " maxSurface2D[0]: %d\n", prop.maxSurface2D[0]);
fprintf(stdout, " maxSurface2D[1]: %d\n", prop.maxSurface2D[1]);
fprintf(stdout, " maxSurface3D\n");
fprintf(stdout, " maxSueface3D[0]: %d\n", prop.maxSurface3D[0]);
fprintf(stdout, " maxSueface3D[1]: %d\n", prop.maxSurface3D[1]);
fprintf(stdout, " maxSueface3D[2]: %d\n", prop.maxSurface3D[2]);
fprintf(stdout, " maxSurface1DLayered\n");
fprintf(stdout, " maxSurface1DLayered[0]: %d\n", prop.maxSurface1DLayered[0]);
fprintf(stdout, " maxSurface1DLayered[1]: %d\n", prop.maxSurface1DLayered[1]);
fprintf(stdout, " maxSurface2DLayered\n");
fprintf(stdout, " maxSurface2DLayered[0]: %d\n", prop.maxSurface2DLayered[0]);
fprintf(stdout, " maxSurface2DLayered[1]: %d\n", prop.maxSurface2DLayered[1]);
fprintf(stdout, " maxSurface2DLayered[2]: %d\n", prop.maxSurface2DLayered[2]);
fprintf(stdout, " maxSurfaceCubemap: %d\n", prop.maxSurfaceCubemap);
fprintf(stdout, " maxSurfaceCubemapLayered\n");
fprintf(stdout, " maxSurfaceCubemapLayered[0]: %d\n", prop.maxSurfaceCubemapLayered[0]);
fprintf(stdout, " maxSurfaceCubemapLayered[1]: %d\n", prop.maxSurfaceCubemapLayered[1]);
fprintf(stdout, " surfaceAlignment: %ld\n", prop.surfaceAlignment);
fprintf(stdout, " concurrentKernels: %d\n", prop.concurrentKernels);
fprintf(stdout, " ECCEnabled: %d\n", prop.ECCEnabled);
fprintf(stdout, " pciBusID: %d\n", prop.pciBusID);
fprintf(stdout, " pciDeviceID: %d\n", prop.pciDeviceID);
fprintf(stdout, " pciDomainID: %d\n", prop.pciDomainID);
fprintf(stdout, " tccDriver: %d\n", prop.tccDriver);
fprintf(stdout, " asyncEngineCount: %d\n", prop.asyncEngineCount);
fprintf(stdout, " unifiedAddressing: %d\n", prop.unifiedAddressing);
fprintf(stdout, " memoryClockRate: %d\n", prop.memoryClockRate);
fprintf(stdout, " l2CacheSize: %d\n", prop.l2CacheSize);
fprintf(stdout, " maxThreadsPerMultiProcessor: %d\n", prop.maxThreadsPerMultiProcessor);
return 0;
} | .file "tmpxft_00031da2_00000000-6_getDeviceProp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "no device avalible, go a hell, man\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "get prop success\n"
.LC2:
.string " name: %s\n"
.LC3:
.string " totalGlobalMem: %lu\n"
.LC4:
.string " sharedMemPerBlock: %lu\n"
.LC5:
.string " regsPerBlock: %d\n"
.LC6:
.string " warpSize: %d\n"
.LC7:
.string " memPitch: %lu\n"
.LC8:
.string " maxThreadsPerBlock: %d\n"
.LC9:
.string " maxThreadsDim:\n"
.LC10:
.string " maxThreadsDim[0]: %d\n"
.LC11:
.string " maxThreadsDim[1]: %d\n"
.LC12:
.string " maxThreadsDim[2]: %d\n"
.LC13:
.string " maxThreadsGridSize:\n"
.LC14:
.string " maxGridSize[0]: %d\n"
.LC15:
.string " maxGridSize[1]: %d\n"
.LC16:
.string " maxGridSize[2]: %d\n"
.LC17:
.string " clockRate: %d\n"
.LC18:
.string " totalConstMem: %lu\n"
.LC19:
.string " major.minor: %d.%d\n"
.LC20:
.string " textureAlignment: %lu\n"
.section .rodata.str1.8
.align 8
.LC21:
.string " texturePitchAlignment: %lu\n"
.section .rodata.str1.1
.LC22:
.string " deviceOverlap: %d\n"
.LC23:
.string " multiProcessorCount: %d\n"
.section .rodata.str1.8
.align 8
.LC24:
.string " kernelExecTimeoutEnabled: %d\n"
.section .rodata.str1.1
.LC25:
.string " integrated: %d\n"
.LC26:
.string " canMapHostMemory: %d\n"
.LC27:
.string " computeMode: %d\n"
.LC28:
.string " maxTexture1D: %d\n"
.LC29:
.string " maxTexture1DLinear: %d\n"
.LC30:
.string " maxTexture2D\n"
.LC31:
.string " maxTexture2D[0]: %d\n"
.LC32:
.string " maxTexture2D[1]: %d\n"
.LC33:
.string " maxTexture2DLinear\n"
.section .rodata.str1.8
.align 8
.LC34:
.string " maxTexture2DLinear[0]: %d\n"
.align 8
.LC35:
.string " maxTexture2DLinear[1]: %d\n"
.align 8
.LC36:
.string " maxTexture2DLinear[2]: %d\n"
.section .rodata.str1.1
.LC37:
.string " maxTexture2DGather\n"
.section .rodata.str1.8
.align 8
.LC38:
.string " maxTexture2DGather[0]: %d\n"
.align 8
.LC39:
.string " maxTexture2DGather[1]: %d\n"
.section .rodata.str1.1
.LC40:
.string " maxTexture3D\n"
.LC41:
.string " maxTexture3D[0]: %d\n"
.LC42:
.string " maxTexture3D[1]: %d\n"
.LC43:
.string " maxTexture3D[2]: %d\n"
.LC44:
.string " maxSurface1D: %d\n"
.LC45:
.string " maxSurface2D\n"
.LC46:
.string " maxSurface2D[0]: %d\n"
.LC47:
.string " maxSurface2D[1]: %d\n"
.LC48:
.string " maxSurface3D\n"
.LC49:
.string " maxSueface3D[0]: %d\n"
.LC50:
.string " maxSueface3D[1]: %d\n"
.LC51:
.string " maxSueface3D[2]: %d\n"
.LC52:
.string " maxSurface1DLayered\n"
.section .rodata.str1.8
.align 8
.LC53:
.string " maxSurface1DLayered[0]: %d\n"
.align 8
.LC54:
.string " maxSurface1DLayered[1]: %d\n"
.section .rodata.str1.1
.LC55:
.string " maxSurface2DLayered\n"
.section .rodata.str1.8
.align 8
.LC56:
.string " maxSurface2DLayered[0]: %d\n"
.align 8
.LC57:
.string " maxSurface2DLayered[1]: %d\n"
.align 8
.LC58:
.string " maxSurface2DLayered[2]: %d\n"
.section .rodata.str1.1
.LC59:
.string " maxSurfaceCubemap: %d\n"
.LC60:
.string " maxSurfaceCubemapLayered\n"
.section .rodata.str1.8
.align 8
.LC61:
.string " maxSurfaceCubemapLayered[0]: %d\n"
.align 8
.LC62:
.string " maxSurfaceCubemapLayered[1]: %d\n"
.section .rodata.str1.1
.LC63:
.string " surfaceAlignment: %ld\n"
.LC64:
.string " concurrentKernels: %d\n"
.LC65:
.string " ECCEnabled: %d\n"
.LC66:
.string " pciBusID: %d\n"
.LC67:
.string " pciDeviceID: %d\n"
.LC68:
.string " pciDomainID: %d\n"
.LC69:
.string " tccDriver: %d\n"
.LC70:
.string " asyncEngineCount: %d\n"
.LC71:
.string " unifiedAddressing: %d\n"
.LC72:
.string " memoryClockRate: %d\n"
.LC73:
.string " l2CacheSize: %d\n"
.section .rodata.str1.8
.align 8
.LC74:
.string " maxThreadsPerMultiProcessor: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $1048, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L7
.L4:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rsp, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 288(%rsp), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 296(%rsp), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 304(%rsp), %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 308(%rsp), %ecx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 312(%rsp), %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 320(%rsp), %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 324(%rsp), %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 328(%rsp), %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 332(%rsp), %ecx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 336(%rsp), %ecx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 340(%rsp), %ecx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 344(%rsp), %ecx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 348(%rsp), %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 352(%rsp), %rcx
leaq .LC18(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 364(%rsp), %r8d
movl 360(%rsp), %ecx
leaq .LC19(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 368(%rsp), %rcx
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 376(%rsp), %rcx
leaq .LC21(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 384(%rsp), %ecx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 388(%rsp), %ecx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 392(%rsp), %ecx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 396(%rsp), %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 400(%rsp), %ecx
leaq .LC26(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 404(%rsp), %ecx
leaq .LC27(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 408(%rsp), %ecx
leaq .LC28(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 416(%rsp), %ecx
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC30(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 420(%rsp), %ecx
leaq .LC31(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 424(%rsp), %ecx
leaq .LC32(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC33(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 436(%rsp), %ecx
leaq .LC34(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 440(%rsp), %ecx
leaq .LC35(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 444(%rsp), %ecx
leaq .LC36(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC37(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 448(%rsp), %ecx
leaq .LC38(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 452(%rsp), %ecx
leaq .LC39(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC40(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 456(%rsp), %ecx
leaq .LC41(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 460(%rsp), %ecx
leaq .LC42(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 464(%rsp), %ecx
leaq .LC43(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 512(%rsp), %ecx
leaq .LC44(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC45(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 516(%rsp), %ecx
leaq .LC46(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 520(%rsp), %ecx
leaq .LC47(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC48(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 524(%rsp), %ecx
leaq .LC49(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 528(%rsp), %ecx
leaq .LC50(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 532(%rsp), %ecx
leaq .LC51(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC52(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 536(%rsp), %ecx
leaq .LC53(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 540(%rsp), %ecx
leaq .LC54(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC55(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 544(%rsp), %ecx
leaq .LC56(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 548(%rsp), %ecx
leaq .LC57(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 552(%rsp), %ecx
leaq .LC58(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 556(%rsp), %ecx
leaq .LC59(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC60(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 560(%rsp), %ecx
leaq .LC61(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 564(%rsp), %ecx
leaq .LC62(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 568(%rsp), %rcx
leaq .LC63(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 576(%rsp), %ecx
leaq .LC64(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 580(%rsp), %ecx
leaq .LC65(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 584(%rsp), %ecx
leaq .LC66(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 588(%rsp), %ecx
leaq .LC67(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 592(%rsp), %ecx
leaq .LC68(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 596(%rsp), %ecx
leaq .LC69(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 600(%rsp), %ecx
leaq .LC70(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 604(%rsp), %ecx
leaq .LC71(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 608(%rsp), %ecx
leaq .LC72(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 616(%rsp), %ecx
leaq .LC73(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 624(%rsp), %ecx
leaq .LC74(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
int main(void){
cudaDeviceProp prop;
if(cudaGetDeviceProperties(&prop, 0) != cudaSuccess){
fprintf(stderr, "no device avalible, go a hell, man\n");
}
fprintf(stdout, "get prop success\n");
fprintf(stdout, " name: %s\n", prop.name);
fprintf(stdout, " totalGlobalMem: %lu\n", prop.totalGlobalMem);
fprintf(stdout, " sharedMemPerBlock: %lu\n", prop.sharedMemPerBlock);
fprintf(stdout, " regsPerBlock: %d\n", prop.regsPerBlock);
fprintf(stdout, " warpSize: %d\n", prop.warpSize);
fprintf(stdout, " memPitch: %lu\n", prop.memPitch);
fprintf(stdout, " maxThreadsPerBlock: %d\n", prop.maxThreadsPerBlock);
fprintf(stdout, " maxThreadsDim:\n");
fprintf(stdout, " maxThreadsDim[0]: %d\n", prop.maxThreadsDim[0]);
fprintf(stdout, " maxThreadsDim[1]: %d\n", prop.maxThreadsDim[1]);
fprintf(stdout, " maxThreadsDim[2]: %d\n", prop.maxThreadsDim[2]);
fprintf(stdout, " maxThreadsGridSize:\n");
fprintf(stdout, " maxGridSize[0]: %d\n", prop.maxGridSize[0]);
fprintf(stdout, " maxGridSize[1]: %d\n", prop.maxGridSize[1]);
fprintf(stdout, " maxGridSize[2]: %d\n", prop.maxGridSize[2]);
fprintf(stdout, " clockRate: %d\n", prop.clockRate);
fprintf(stdout, " totalConstMem: %lu\n", prop.totalConstMem);
fprintf(stdout, " major.minor: %d.%d\n", prop.major, prop.minor);
fprintf(stdout, " textureAlignment: %lu\n", prop.textureAlignment);
fprintf(stdout, " texturePitchAlignment: %lu\n", prop.texturePitchAlignment);
fprintf(stdout, " deviceOverlap: %d\n", prop.deviceOverlap);
fprintf(stdout, " multiProcessorCount: %d\n", prop.multiProcessorCount);
fprintf(stdout, " kernelExecTimeoutEnabled: %d\n", prop.kernelExecTimeoutEnabled);
fprintf(stdout, " integrated: %d\n", prop.integrated);
fprintf(stdout, " canMapHostMemory: %d\n", prop.canMapHostMemory);
fprintf(stdout, " computeMode: %d\n", prop.computeMode);
fprintf(stdout, " maxTexture1D: %d\n", prop.maxTexture1D);
fprintf(stdout, " maxTexture1DLinear: %d\n", prop.maxTexture1DLinear);
fprintf(stdout, " maxTexture2D\n");
fprintf(stdout, " maxTexture2D[0]: %d\n", prop.maxTexture2D[0]);
fprintf(stdout, " maxTexture2D[1]: %d\n", prop.maxTexture2D[1]);
fprintf(stdout, " maxTexture2DLinear\n");
fprintf(stdout, " maxTexture2DLinear[0]: %d\n", prop.maxTexture2DLinear[0]);
fprintf(stdout, " maxTexture2DLinear[1]: %d\n", prop.maxTexture2DLinear[1]);
fprintf(stdout, " maxTexture2DLinear[2]: %d\n", prop.maxTexture2DLinear[2]);
fprintf(stdout, " maxTexture2DGather\n");
fprintf(stdout, " maxTexture2DGather[0]: %d\n", prop.maxTexture2DGather[0]);
fprintf(stdout, " maxTexture2DGather[1]: %d\n", prop.maxTexture2DGather[1]);
fprintf(stdout, " maxTexture3D\n");
fprintf(stdout, " maxTexture3D[0]: %d\n", prop.maxTexture3D[0]);
fprintf(stdout, " maxTexture3D[1]: %d\n", prop.maxTexture3D[1]);
fprintf(stdout, " maxTexture3D[2]: %d\n", prop.maxTexture3D[2]);
fprintf(stdout, " maxSurface1D: %d\n", prop.maxSurface1D);
fprintf(stdout, " maxSurface2D\n");
fprintf(stdout, " maxSurface2D[0]: %d\n", prop.maxSurface2D[0]);
fprintf(stdout, " maxSurface2D[1]: %d\n", prop.maxSurface2D[1]);
fprintf(stdout, " maxSurface3D\n");
fprintf(stdout, " maxSueface3D[0]: %d\n", prop.maxSurface3D[0]);
fprintf(stdout, " maxSueface3D[1]: %d\n", prop.maxSurface3D[1]);
fprintf(stdout, " maxSueface3D[2]: %d\n", prop.maxSurface3D[2]);
fprintf(stdout, " maxSurface1DLayered\n");
fprintf(stdout, " maxSurface1DLayered[0]: %d\n", prop.maxSurface1DLayered[0]);
fprintf(stdout, " maxSurface1DLayered[1]: %d\n", prop.maxSurface1DLayered[1]);
fprintf(stdout, " maxSurface2DLayered\n");
fprintf(stdout, " maxSurface2DLayered[0]: %d\n", prop.maxSurface2DLayered[0]);
fprintf(stdout, " maxSurface2DLayered[1]: %d\n", prop.maxSurface2DLayered[1]);
fprintf(stdout, " maxSurface2DLayered[2]: %d\n", prop.maxSurface2DLayered[2]);
fprintf(stdout, " maxSurfaceCubemap: %d\n", prop.maxSurfaceCubemap);
fprintf(stdout, " maxSurfaceCubemapLayered\n");
fprintf(stdout, " maxSurfaceCubemapLayered[0]: %d\n", prop.maxSurfaceCubemapLayered[0]);
fprintf(stdout, " maxSurfaceCubemapLayered[1]: %d\n", prop.maxSurfaceCubemapLayered[1]);
fprintf(stdout, " surfaceAlignment: %ld\n", prop.surfaceAlignment);
fprintf(stdout, " concurrentKernels: %d\n", prop.concurrentKernels);
fprintf(stdout, " ECCEnabled: %d\n", prop.ECCEnabled);
fprintf(stdout, " pciBusID: %d\n", prop.pciBusID);
fprintf(stdout, " pciDeviceID: %d\n", prop.pciDeviceID);
fprintf(stdout, " pciDomainID: %d\n", prop.pciDomainID);
fprintf(stdout, " tccDriver: %d\n", prop.tccDriver);
fprintf(stdout, " asyncEngineCount: %d\n", prop.asyncEngineCount);
fprintf(stdout, " unifiedAddressing: %d\n", prop.unifiedAddressing);
fprintf(stdout, " memoryClockRate: %d\n", prop.memoryClockRate);
fprintf(stdout, " l2CacheSize: %d\n", prop.l2CacheSize);
fprintf(stdout, " maxThreadsPerMultiProcessor: %d\n", prop.maxThreadsPerMultiProcessor);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
int main(void){
hipDeviceProp_t prop;
if(hipGetDeviceProperties(&prop, 0) != hipSuccess){
fprintf(stderr, "no device avalible, go a hell, man\n");
}
fprintf(stdout, "get prop success\n");
fprintf(stdout, " name: %s\n", prop.name);
fprintf(stdout, " totalGlobalMem: %lu\n", prop.totalGlobalMem);
fprintf(stdout, " sharedMemPerBlock: %lu\n", prop.sharedMemPerBlock);
fprintf(stdout, " regsPerBlock: %d\n", prop.regsPerBlock);
fprintf(stdout, " warpSize: %d\n", prop.warpSize);
fprintf(stdout, " memPitch: %lu\n", prop.memPitch);
fprintf(stdout, " maxThreadsPerBlock: %d\n", prop.maxThreadsPerBlock);
fprintf(stdout, " maxThreadsDim:\n");
fprintf(stdout, " maxThreadsDim[0]: %d\n", prop.maxThreadsDim[0]);
fprintf(stdout, " maxThreadsDim[1]: %d\n", prop.maxThreadsDim[1]);
fprintf(stdout, " maxThreadsDim[2]: %d\n", prop.maxThreadsDim[2]);
fprintf(stdout, " maxThreadsGridSize:\n");
fprintf(stdout, " maxGridSize[0]: %d\n", prop.maxGridSize[0]);
fprintf(stdout, " maxGridSize[1]: %d\n", prop.maxGridSize[1]);
fprintf(stdout, " maxGridSize[2]: %d\n", prop.maxGridSize[2]);
fprintf(stdout, " clockRate: %d\n", prop.clockRate);
fprintf(stdout, " totalConstMem: %lu\n", prop.totalConstMem);
fprintf(stdout, " major.minor: %d.%d\n", prop.major, prop.minor);
fprintf(stdout, " textureAlignment: %lu\n", prop.textureAlignment);
fprintf(stdout, " texturePitchAlignment: %lu\n", prop.texturePitchAlignment);
fprintf(stdout, " deviceOverlap: %d\n", prop.deviceOverlap);
fprintf(stdout, " multiProcessorCount: %d\n", prop.multiProcessorCount);
fprintf(stdout, " kernelExecTimeoutEnabled: %d\n", prop.kernelExecTimeoutEnabled);
fprintf(stdout, " integrated: %d\n", prop.integrated);
fprintf(stdout, " canMapHostMemory: %d\n", prop.canMapHostMemory);
fprintf(stdout, " computeMode: %d\n", prop.computeMode);
fprintf(stdout, " maxTexture1D: %d\n", prop.maxTexture1D);
fprintf(stdout, " maxTexture1DLinear: %d\n", prop.maxTexture1DLinear);
fprintf(stdout, " maxTexture2D\n");
fprintf(stdout, " maxTexture2D[0]: %d\n", prop.maxTexture2D[0]);
fprintf(stdout, " maxTexture2D[1]: %d\n", prop.maxTexture2D[1]);
fprintf(stdout, " maxTexture2DLinear\n");
fprintf(stdout, " maxTexture2DLinear[0]: %d\n", prop.maxTexture2DLinear[0]);
fprintf(stdout, " maxTexture2DLinear[1]: %d\n", prop.maxTexture2DLinear[1]);
fprintf(stdout, " maxTexture2DLinear[2]: %d\n", prop.maxTexture2DLinear[2]);
fprintf(stdout, " maxTexture2DGather\n");
fprintf(stdout, " maxTexture2DGather[0]: %d\n", prop.maxTexture2DGather[0]);
fprintf(stdout, " maxTexture2DGather[1]: %d\n", prop.maxTexture2DGather[1]);
fprintf(stdout, " maxTexture3D\n");
fprintf(stdout, " maxTexture3D[0]: %d\n", prop.maxTexture3D[0]);
fprintf(stdout, " maxTexture3D[1]: %d\n", prop.maxTexture3D[1]);
fprintf(stdout, " maxTexture3D[2]: %d\n", prop.maxTexture3D[2]);
fprintf(stdout, " maxSurface1D: %d\n", prop.maxSurface1D);
fprintf(stdout, " maxSurface2D\n");
fprintf(stdout, " maxSurface2D[0]: %d\n", prop.maxSurface2D[0]);
fprintf(stdout, " maxSurface2D[1]: %d\n", prop.maxSurface2D[1]);
fprintf(stdout, " maxSurface3D\n");
fprintf(stdout, " maxSueface3D[0]: %d\n", prop.maxSurface3D[0]);
fprintf(stdout, " maxSueface3D[1]: %d\n", prop.maxSurface3D[1]);
fprintf(stdout, " maxSueface3D[2]: %d\n", prop.maxSurface3D[2]);
fprintf(stdout, " maxSurface1DLayered\n");
fprintf(stdout, " maxSurface1DLayered[0]: %d\n", prop.maxSurface1DLayered[0]);
fprintf(stdout, " maxSurface1DLayered[1]: %d\n", prop.maxSurface1DLayered[1]);
fprintf(stdout, " maxSurface2DLayered\n");
fprintf(stdout, " maxSurface2DLayered[0]: %d\n", prop.maxSurface2DLayered[0]);
fprintf(stdout, " maxSurface2DLayered[1]: %d\n", prop.maxSurface2DLayered[1]);
fprintf(stdout, " maxSurface2DLayered[2]: %d\n", prop.maxSurface2DLayered[2]);
fprintf(stdout, " maxSurfaceCubemap: %d\n", prop.maxSurfaceCubemap);
fprintf(stdout, " maxSurfaceCubemapLayered\n");
fprintf(stdout, " maxSurfaceCubemapLayered[0]: %d\n", prop.maxSurfaceCubemapLayered[0]);
fprintf(stdout, " maxSurfaceCubemapLayered[1]: %d\n", prop.maxSurfaceCubemapLayered[1]);
fprintf(stdout, " surfaceAlignment: %ld\n", prop.surfaceAlignment);
fprintf(stdout, " concurrentKernels: %d\n", prop.concurrentKernels);
fprintf(stdout, " ECCEnabled: %d\n", prop.ECCEnabled);
fprintf(stdout, " pciBusID: %d\n", prop.pciBusID);
fprintf(stdout, " pciDeviceID: %d\n", prop.pciDeviceID);
fprintf(stdout, " pciDomainID: %d\n", prop.pciDomainID);
fprintf(stdout, " tccDriver: %d\n", prop.tccDriver);
fprintf(stdout, " asyncEngineCount: %d\n", prop.asyncEngineCount);
fprintf(stdout, " unifiedAddressing: %d\n", prop.unifiedAddressing);
fprintf(stdout, " memoryClockRate: %d\n", prop.memoryClockRate);
fprintf(stdout, " l2CacheSize: %d\n", prop.l2CacheSize);
fprintf(stdout, " maxThreadsPerMultiProcessor: %d\n", prop.maxThreadsPerMultiProcessor);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
int main(void){
hipDeviceProp_t prop;
if(hipGetDeviceProperties(&prop, 0) != hipSuccess){
fprintf(stderr, "no device avalible, go a hell, man\n");
}
fprintf(stdout, "get prop success\n");
fprintf(stdout, " name: %s\n", prop.name);
fprintf(stdout, " totalGlobalMem: %lu\n", prop.totalGlobalMem);
fprintf(stdout, " sharedMemPerBlock: %lu\n", prop.sharedMemPerBlock);
fprintf(stdout, " regsPerBlock: %d\n", prop.regsPerBlock);
fprintf(stdout, " warpSize: %d\n", prop.warpSize);
fprintf(stdout, " memPitch: %lu\n", prop.memPitch);
fprintf(stdout, " maxThreadsPerBlock: %d\n", prop.maxThreadsPerBlock);
fprintf(stdout, " maxThreadsDim:\n");
fprintf(stdout, " maxThreadsDim[0]: %d\n", prop.maxThreadsDim[0]);
fprintf(stdout, " maxThreadsDim[1]: %d\n", prop.maxThreadsDim[1]);
fprintf(stdout, " maxThreadsDim[2]: %d\n", prop.maxThreadsDim[2]);
fprintf(stdout, " maxThreadsGridSize:\n");
fprintf(stdout, " maxGridSize[0]: %d\n", prop.maxGridSize[0]);
fprintf(stdout, " maxGridSize[1]: %d\n", prop.maxGridSize[1]);
fprintf(stdout, " maxGridSize[2]: %d\n", prop.maxGridSize[2]);
fprintf(stdout, " clockRate: %d\n", prop.clockRate);
fprintf(stdout, " totalConstMem: %lu\n", prop.totalConstMem);
fprintf(stdout, " major.minor: %d.%d\n", prop.major, prop.minor);
fprintf(stdout, " textureAlignment: %lu\n", prop.textureAlignment);
fprintf(stdout, " texturePitchAlignment: %lu\n", prop.texturePitchAlignment);
fprintf(stdout, " deviceOverlap: %d\n", prop.deviceOverlap);
fprintf(stdout, " multiProcessorCount: %d\n", prop.multiProcessorCount);
fprintf(stdout, " kernelExecTimeoutEnabled: %d\n", prop.kernelExecTimeoutEnabled);
fprintf(stdout, " integrated: %d\n", prop.integrated);
fprintf(stdout, " canMapHostMemory: %d\n", prop.canMapHostMemory);
fprintf(stdout, " computeMode: %d\n", prop.computeMode);
fprintf(stdout, " maxTexture1D: %d\n", prop.maxTexture1D);
fprintf(stdout, " maxTexture1DLinear: %d\n", prop.maxTexture1DLinear);
fprintf(stdout, " maxTexture2D\n");
fprintf(stdout, " maxTexture2D[0]: %d\n", prop.maxTexture2D[0]);
fprintf(stdout, " maxTexture2D[1]: %d\n", prop.maxTexture2D[1]);
fprintf(stdout, " maxTexture2DLinear\n");
fprintf(stdout, " maxTexture2DLinear[0]: %d\n", prop.maxTexture2DLinear[0]);
fprintf(stdout, " maxTexture2DLinear[1]: %d\n", prop.maxTexture2DLinear[1]);
fprintf(stdout, " maxTexture2DLinear[2]: %d\n", prop.maxTexture2DLinear[2]);
fprintf(stdout, " maxTexture2DGather\n");
fprintf(stdout, " maxTexture2DGather[0]: %d\n", prop.maxTexture2DGather[0]);
fprintf(stdout, " maxTexture2DGather[1]: %d\n", prop.maxTexture2DGather[1]);
fprintf(stdout, " maxTexture3D\n");
fprintf(stdout, " maxTexture3D[0]: %d\n", prop.maxTexture3D[0]);
fprintf(stdout, " maxTexture3D[1]: %d\n", prop.maxTexture3D[1]);
fprintf(stdout, " maxTexture3D[2]: %d\n", prop.maxTexture3D[2]);
fprintf(stdout, " maxSurface1D: %d\n", prop.maxSurface1D);
fprintf(stdout, " maxSurface2D\n");
fprintf(stdout, " maxSurface2D[0]: %d\n", prop.maxSurface2D[0]);
fprintf(stdout, " maxSurface2D[1]: %d\n", prop.maxSurface2D[1]);
fprintf(stdout, " maxSurface3D\n");
fprintf(stdout, " maxSueface3D[0]: %d\n", prop.maxSurface3D[0]);
fprintf(stdout, " maxSueface3D[1]: %d\n", prop.maxSurface3D[1]);
fprintf(stdout, " maxSueface3D[2]: %d\n", prop.maxSurface3D[2]);
fprintf(stdout, " maxSurface1DLayered\n");
fprintf(stdout, " maxSurface1DLayered[0]: %d\n", prop.maxSurface1DLayered[0]);
fprintf(stdout, " maxSurface1DLayered[1]: %d\n", prop.maxSurface1DLayered[1]);
fprintf(stdout, " maxSurface2DLayered\n");
fprintf(stdout, " maxSurface2DLayered[0]: %d\n", prop.maxSurface2DLayered[0]);
fprintf(stdout, " maxSurface2DLayered[1]: %d\n", prop.maxSurface2DLayered[1]);
fprintf(stdout, " maxSurface2DLayered[2]: %d\n", prop.maxSurface2DLayered[2]);
fprintf(stdout, " maxSurfaceCubemap: %d\n", prop.maxSurfaceCubemap);
fprintf(stdout, " maxSurfaceCubemapLayered\n");
fprintf(stdout, " maxSurfaceCubemapLayered[0]: %d\n", prop.maxSurfaceCubemapLayered[0]);
fprintf(stdout, " maxSurfaceCubemapLayered[1]: %d\n", prop.maxSurfaceCubemapLayered[1]);
fprintf(stdout, " surfaceAlignment: %ld\n", prop.surfaceAlignment);
fprintf(stdout, " concurrentKernels: %d\n", prop.concurrentKernels);
fprintf(stdout, " ECCEnabled: %d\n", prop.ECCEnabled);
fprintf(stdout, " pciBusID: %d\n", prop.pciBusID);
fprintf(stdout, " pciDeviceID: %d\n", prop.pciDeviceID);
fprintf(stdout, " pciDomainID: %d\n", prop.pciDomainID);
fprintf(stdout, " tccDriver: %d\n", prop.tccDriver);
fprintf(stdout, " asyncEngineCount: %d\n", prop.asyncEngineCount);
fprintf(stdout, " unifiedAddressing: %d\n", prop.unifiedAddressing);
fprintf(stdout, " memoryClockRate: %d\n", prop.memoryClockRate);
fprintf(stdout, " l2CacheSize: %d\n", prop.l2CacheSize);
fprintf(stdout, " maxThreadsPerMultiProcessor: %d\n", prop.maxThreadsPerMultiProcessor);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
int main(void){
hipDeviceProp_t prop;
if(hipGetDeviceProperties(&prop, 0) != hipSuccess){
fprintf(stderr, "no device avalible, go a hell, man\n");
}
fprintf(stdout, "get prop success\n");
fprintf(stdout, " name: %s\n", prop.name);
fprintf(stdout, " totalGlobalMem: %lu\n", prop.totalGlobalMem);
fprintf(stdout, " sharedMemPerBlock: %lu\n", prop.sharedMemPerBlock);
fprintf(stdout, " regsPerBlock: %d\n", prop.regsPerBlock);
fprintf(stdout, " warpSize: %d\n", prop.warpSize);
fprintf(stdout, " memPitch: %lu\n", prop.memPitch);
fprintf(stdout, " maxThreadsPerBlock: %d\n", prop.maxThreadsPerBlock);
fprintf(stdout, " maxThreadsDim:\n");
fprintf(stdout, " maxThreadsDim[0]: %d\n", prop.maxThreadsDim[0]);
fprintf(stdout, " maxThreadsDim[1]: %d\n", prop.maxThreadsDim[1]);
fprintf(stdout, " maxThreadsDim[2]: %d\n", prop.maxThreadsDim[2]);
fprintf(stdout, " maxThreadsGridSize:\n");
fprintf(stdout, " maxGridSize[0]: %d\n", prop.maxGridSize[0]);
fprintf(stdout, " maxGridSize[1]: %d\n", prop.maxGridSize[1]);
fprintf(stdout, " maxGridSize[2]: %d\n", prop.maxGridSize[2]);
fprintf(stdout, " clockRate: %d\n", prop.clockRate);
fprintf(stdout, " totalConstMem: %lu\n", prop.totalConstMem);
fprintf(stdout, " major.minor: %d.%d\n", prop.major, prop.minor);
fprintf(stdout, " textureAlignment: %lu\n", prop.textureAlignment);
fprintf(stdout, " texturePitchAlignment: %lu\n", prop.texturePitchAlignment);
fprintf(stdout, " deviceOverlap: %d\n", prop.deviceOverlap);
fprintf(stdout, " multiProcessorCount: %d\n", prop.multiProcessorCount);
fprintf(stdout, " kernelExecTimeoutEnabled: %d\n", prop.kernelExecTimeoutEnabled);
fprintf(stdout, " integrated: %d\n", prop.integrated);
fprintf(stdout, " canMapHostMemory: %d\n", prop.canMapHostMemory);
fprintf(stdout, " computeMode: %d\n", prop.computeMode);
fprintf(stdout, " maxTexture1D: %d\n", prop.maxTexture1D);
fprintf(stdout, " maxTexture1DLinear: %d\n", prop.maxTexture1DLinear);
fprintf(stdout, " maxTexture2D\n");
fprintf(stdout, " maxTexture2D[0]: %d\n", prop.maxTexture2D[0]);
fprintf(stdout, " maxTexture2D[1]: %d\n", prop.maxTexture2D[1]);
fprintf(stdout, " maxTexture2DLinear\n");
fprintf(stdout, " maxTexture2DLinear[0]: %d\n", prop.maxTexture2DLinear[0]);
fprintf(stdout, " maxTexture2DLinear[1]: %d\n", prop.maxTexture2DLinear[1]);
fprintf(stdout, " maxTexture2DLinear[2]: %d\n", prop.maxTexture2DLinear[2]);
fprintf(stdout, " maxTexture2DGather\n");
fprintf(stdout, " maxTexture2DGather[0]: %d\n", prop.maxTexture2DGather[0]);
fprintf(stdout, " maxTexture2DGather[1]: %d\n", prop.maxTexture2DGather[1]);
fprintf(stdout, " maxTexture3D\n");
fprintf(stdout, " maxTexture3D[0]: %d\n", prop.maxTexture3D[0]);
fprintf(stdout, " maxTexture3D[1]: %d\n", prop.maxTexture3D[1]);
fprintf(stdout, " maxTexture3D[2]: %d\n", prop.maxTexture3D[2]);
fprintf(stdout, " maxSurface1D: %d\n", prop.maxSurface1D);
fprintf(stdout, " maxSurface2D\n");
fprintf(stdout, " maxSurface2D[0]: %d\n", prop.maxSurface2D[0]);
fprintf(stdout, " maxSurface2D[1]: %d\n", prop.maxSurface2D[1]);
fprintf(stdout, " maxSurface3D\n");
fprintf(stdout, " maxSueface3D[0]: %d\n", prop.maxSurface3D[0]);
fprintf(stdout, " maxSueface3D[1]: %d\n", prop.maxSurface3D[1]);
fprintf(stdout, " maxSueface3D[2]: %d\n", prop.maxSurface3D[2]);
fprintf(stdout, " maxSurface1DLayered\n");
fprintf(stdout, " maxSurface1DLayered[0]: %d\n", prop.maxSurface1DLayered[0]);
fprintf(stdout, " maxSurface1DLayered[1]: %d\n", prop.maxSurface1DLayered[1]);
fprintf(stdout, " maxSurface2DLayered\n");
fprintf(stdout, " maxSurface2DLayered[0]: %d\n", prop.maxSurface2DLayered[0]);
fprintf(stdout, " maxSurface2DLayered[1]: %d\n", prop.maxSurface2DLayered[1]);
fprintf(stdout, " maxSurface2DLayered[2]: %d\n", prop.maxSurface2DLayered[2]);
fprintf(stdout, " maxSurfaceCubemap: %d\n", prop.maxSurfaceCubemap);
fprintf(stdout, " maxSurfaceCubemapLayered\n");
fprintf(stdout, " maxSurfaceCubemapLayered[0]: %d\n", prop.maxSurfaceCubemapLayered[0]);
fprintf(stdout, " maxSurfaceCubemapLayered[1]: %d\n", prop.maxSurfaceCubemapLayered[1]);
fprintf(stdout, " surfaceAlignment: %ld\n", prop.surfaceAlignment);
fprintf(stdout, " concurrentKernels: %d\n", prop.concurrentKernels);
fprintf(stdout, " ECCEnabled: %d\n", prop.ECCEnabled);
fprintf(stdout, " pciBusID: %d\n", prop.pciBusID);
fprintf(stdout, " pciDeviceID: %d\n", prop.pciDeviceID);
fprintf(stdout, " pciDomainID: %d\n", prop.pciDomainID);
fprintf(stdout, " tccDriver: %d\n", prop.tccDriver);
fprintf(stdout, " asyncEngineCount: %d\n", prop.asyncEngineCount);
fprintf(stdout, " unifiedAddressing: %d\n", prop.unifiedAddressing);
fprintf(stdout, " memoryClockRate: %d\n", prop.memoryClockRate);
fprintf(stdout, " l2CacheSize: %d\n", prop.l2CacheSize);
fprintf(stdout, " maxThreadsPerMultiProcessor: %d\n", prop.maxThreadsPerMultiProcessor);
return 0;
} | .text
.file "getDeviceProp.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1488
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_1
.LBB0_2:
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
leaq 8(%rsp), %rdx
movl $.L.str.2, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 296(%rsp), %rdx
movl $.L.str.3, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 304(%rsp), %rdx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 312(%rsp), %edx
movl $.L.str.5, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 316(%rsp), %edx
movl $.L.str.6, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 320(%rsp), %rdx
movl $.L.str.7, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 328(%rsp), %edx
movl $.L.str.8, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.9, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 332(%rsp), %edx
movl $.L.str.10, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 336(%rsp), %edx
movl $.L.str.11, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 340(%rsp), %edx
movl $.L.str.12, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.13, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 344(%rsp), %edx
movl $.L.str.14, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 348(%rsp), %edx
movl $.L.str.15, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 352(%rsp), %edx
movl $.L.str.16, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 356(%rsp), %edx
movl $.L.str.17, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 360(%rsp), %rdx
movl $.L.str.18, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 368(%rsp), %edx
movl 372(%rsp), %ecx
movl $.L.str.19, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 376(%rsp), %rdx
movl $.L.str.20, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 384(%rsp), %rdx
movl $.L.str.21, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 392(%rsp), %edx
movl $.L.str.22, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 396(%rsp), %edx
movl $.L.str.23, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 400(%rsp), %edx
movl $.L.str.24, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 404(%rsp), %edx
movl $.L.str.25, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 408(%rsp), %edx
movl $.L.str.26, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 412(%rsp), %edx
movl $.L.str.27, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 416(%rsp), %edx
movl $.L.str.28, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 424(%rsp), %edx
movl $.L.str.29, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.30, %edi
movl $16, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 428(%rsp), %edx
movl $.L.str.31, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 432(%rsp), %edx
movl $.L.str.32, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.33, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 444(%rsp), %edx
movl $.L.str.34, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 448(%rsp), %edx
movl $.L.str.35, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 452(%rsp), %edx
movl $.L.str.36, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.37, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 456(%rsp), %edx
movl $.L.str.38, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 460(%rsp), %edx
movl $.L.str.39, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.40, %edi
movl $16, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 464(%rsp), %edx
movl $.L.str.41, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 468(%rsp), %edx
movl $.L.str.42, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 472(%rsp), %edx
movl $.L.str.43, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 520(%rsp), %edx
movl $.L.str.44, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.45, %edi
movl $16, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 524(%rsp), %edx
movl $.L.str.46, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 528(%rsp), %edx
movl $.L.str.47, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.48, %edi
movl $16, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 532(%rsp), %edx
movl $.L.str.49, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 536(%rsp), %edx
movl $.L.str.50, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 540(%rsp), %edx
movl $.L.str.51, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.52, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 544(%rsp), %edx
movl $.L.str.53, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 548(%rsp), %edx
movl $.L.str.54, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.55, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 552(%rsp), %edx
movl $.L.str.56, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 556(%rsp), %edx
movl $.L.str.57, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 560(%rsp), %edx
movl $.L.str.58, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 564(%rsp), %edx
movl $.L.str.59, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.60, %edi
movl $28, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 568(%rsp), %edx
movl $.L.str.61, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 572(%rsp), %edx
movl $.L.str.62, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 576(%rsp), %rdx
movl $.L.str.63, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 584(%rsp), %edx
movl $.L.str.64, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 588(%rsp), %edx
movl $.L.str.65, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 592(%rsp), %edx
movl $.L.str.66, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 596(%rsp), %edx
movl $.L.str.67, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 600(%rsp), %edx
movl $.L.str.68, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 604(%rsp), %edx
movl $.L.str.69, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 608(%rsp), %edx
movl $.L.str.70, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 612(%rsp), %edx
movl $.L.str.71, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 616(%rsp), %edx
movl $.L.str.72, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 624(%rsp), %edx
movl $.L.str.73, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 632(%rsp), %edx
movl $.L.str.74, %esi
xorl %eax, %eax
callq fprintf
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 1488
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $35, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB0_2
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "no device avalible, go a hell, man\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "get prop success\n"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " name: %s\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " totalGlobalMem: %lu\n"
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " sharedMemPerBlock: %lu\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " regsPerBlock: %d\n"
.size .L.str.5, 21
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " warpSize: %d\n"
.size .L.str.6, 17
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " memPitch: %lu\n"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " maxThreadsPerBlock: %d\n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " maxThreadsDim:\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " maxThreadsDim[0]: %d\n"
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " maxThreadsDim[1]: %d\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " maxThreadsDim[2]: %d\n"
.size .L.str.12, 29
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " maxThreadsGridSize:\n"
.size .L.str.13, 24
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " maxGridSize[0]: %d\n"
.size .L.str.14, 27
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " maxGridSize[1]: %d\n"
.size .L.str.15, 27
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " maxGridSize[2]: %d\n"
.size .L.str.16, 27
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " clockRate: %d\n"
.size .L.str.17, 18
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " totalConstMem: %lu\n"
.size .L.str.18, 23
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " major.minor: %d.%d\n"
.size .L.str.19, 23
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " textureAlignment: %lu\n"
.size .L.str.20, 26
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " texturePitchAlignment: %lu\n"
.size .L.str.21, 31
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz " deviceOverlap: %d\n"
.size .L.str.22, 22
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz " multiProcessorCount: %d\n"
.size .L.str.23, 28
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz " kernelExecTimeoutEnabled: %d\n"
.size .L.str.24, 33
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz " integrated: %d\n"
.size .L.str.25, 19
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz " canMapHostMemory: %d\n"
.size .L.str.26, 25
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz " computeMode: %d\n"
.size .L.str.27, 20
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz " maxTexture1D: %d\n"
.size .L.str.28, 21
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz " maxTexture1DLinear: %d\n"
.size .L.str.29, 27
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz " maxTexture2D\n"
.size .L.str.30, 17
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz " maxTexture2D[0]: %d\n"
.size .L.str.31, 28
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz " maxTexture2D[1]: %d\n"
.size .L.str.32, 28
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz " maxTexture2DLinear\n"
.size .L.str.33, 23
.type .L.str.34,@object # @.str.34
.L.str.34:
.asciz " maxTexture2DLinear[0]: %d\n"
.size .L.str.34, 34
.type .L.str.35,@object # @.str.35
.L.str.35:
.asciz " maxTexture2DLinear[1]: %d\n"
.size .L.str.35, 34
.type .L.str.36,@object # @.str.36
.L.str.36:
.asciz " maxTexture2DLinear[2]: %d\n"
.size .L.str.36, 34
.type .L.str.37,@object # @.str.37
.L.str.37:
.asciz " maxTexture2DGather\n"
.size .L.str.37, 23
.type .L.str.38,@object # @.str.38
.L.str.38:
.asciz " maxTexture2DGather[0]: %d\n"
.size .L.str.38, 34
.type .L.str.39,@object # @.str.39
.L.str.39:
.asciz " maxTexture2DGather[1]: %d\n"
.size .L.str.39, 34
.type .L.str.40,@object # @.str.40
.L.str.40:
.asciz " maxTexture3D\n"
.size .L.str.40, 17
.type .L.str.41,@object # @.str.41
.L.str.41:
.asciz " maxTexture3D[0]: %d\n"
.size .L.str.41, 28
.type .L.str.42,@object # @.str.42
.L.str.42:
.asciz " maxTexture3D[1]: %d\n"
.size .L.str.42, 28
.type .L.str.43,@object # @.str.43
.L.str.43:
.asciz " maxTexture3D[2]: %d\n"
.size .L.str.43, 28
.type .L.str.44,@object # @.str.44
.L.str.44:
.asciz " maxSurface1D: %d\n"
.size .L.str.44, 21
.type .L.str.45,@object # @.str.45
.L.str.45:
.asciz " maxSurface2D\n"
.size .L.str.45, 17
.type .L.str.46,@object # @.str.46
.L.str.46:
.asciz " maxSurface2D[0]: %d\n"
.size .L.str.46, 28
.type .L.str.47,@object # @.str.47
.L.str.47:
.asciz " maxSurface2D[1]: %d\n"
.size .L.str.47, 28
.type .L.str.48,@object # @.str.48
.L.str.48:
.asciz " maxSurface3D\n"
.size .L.str.48, 17
.type .L.str.49,@object # @.str.49
.L.str.49:
.asciz " maxSueface3D[0]: %d\n"
.size .L.str.49, 28
.type .L.str.50,@object # @.str.50
.L.str.50:
.asciz " maxSueface3D[1]: %d\n"
.size .L.str.50, 28
.type .L.str.51,@object # @.str.51
.L.str.51:
.asciz " maxSueface3D[2]: %d\n"
.size .L.str.51, 28
.type .L.str.52,@object # @.str.52
.L.str.52:
.asciz " maxSurface1DLayered\n"
.size .L.str.52, 24
.type .L.str.53,@object # @.str.53
.L.str.53:
.asciz " maxSurface1DLayered[0]: %d\n"
.size .L.str.53, 35
.type .L.str.54,@object # @.str.54
.L.str.54:
.asciz " maxSurface1DLayered[1]: %d\n"
.size .L.str.54, 35
.type .L.str.55,@object # @.str.55
.L.str.55:
.asciz " maxSurface2DLayered\n"
.size .L.str.55, 24
.type .L.str.56,@object # @.str.56
.L.str.56:
.asciz " maxSurface2DLayered[0]: %d\n"
.size .L.str.56, 35
.type .L.str.57,@object # @.str.57
.L.str.57:
.asciz " maxSurface2DLayered[1]: %d\n"
.size .L.str.57, 35
.type .L.str.58,@object # @.str.58
.L.str.58:
.asciz " maxSurface2DLayered[2]: %d\n"
.size .L.str.58, 35
.type .L.str.59,@object # @.str.59
.L.str.59:
.asciz " maxSurfaceCubemap: %d\n"
.size .L.str.59, 26
.type .L.str.60,@object # @.str.60
.L.str.60:
.asciz " maxSurfaceCubemapLayered\n"
.size .L.str.60, 29
.type .L.str.61,@object # @.str.61
.L.str.61:
.asciz " maxSurfaceCubemapLayered[0]: %d\n"
.size .L.str.61, 40
.type .L.str.62,@object # @.str.62
.L.str.62:
.asciz " maxSurfaceCubemapLayered[1]: %d\n"
.size .L.str.62, 40
.type .L.str.63,@object # @.str.63
.L.str.63:
.asciz " surfaceAlignment: %ld\n"
.size .L.str.63, 26
.type .L.str.64,@object # @.str.64
.L.str.64:
.asciz " concurrentKernels: %d\n"
.size .L.str.64, 26
.type .L.str.65,@object # @.str.65
.L.str.65:
.asciz " ECCEnabled: %d\n"
.size .L.str.65, 19
.type .L.str.66,@object # @.str.66
.L.str.66:
.asciz " pciBusID: %d\n"
.size .L.str.66, 17
.type .L.str.67,@object # @.str.67
.L.str.67:
.asciz " pciDeviceID: %d\n"
.size .L.str.67, 20
.type .L.str.68,@object # @.str.68
.L.str.68:
.asciz " pciDomainID: %d\n"
.size .L.str.68, 20
.type .L.str.69,@object # @.str.69
.L.str.69:
.asciz " tccDriver: %d\n"
.size .L.str.69, 18
.type .L.str.70,@object # @.str.70
.L.str.70:
.asciz " asyncEngineCount: %d\n"
.size .L.str.70, 25
.type .L.str.71,@object # @.str.71
.L.str.71:
.asciz " unifiedAddressing: %d\n"
.size .L.str.71, 26
.type .L.str.72,@object # @.str.72
.L.str.72:
.asciz " memoryClockRate: %d\n"
.size .L.str.72, 24
.type .L.str.73,@object # @.str.73
.L.str.73:
.asciz " l2CacheSize: %d\n"
.size .L.str.73, 20
.type .L.str.74,@object # @.str.74
.L.str.74:
.asciz " maxThreadsPerMultiProcessor: %d\n"
.size .L.str.74, 36
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00031da2_00000000-6_getDeviceProp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "no device avalible, go a hell, man\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "get prop success\n"
.LC2:
.string " name: %s\n"
.LC3:
.string " totalGlobalMem: %lu\n"
.LC4:
.string " sharedMemPerBlock: %lu\n"
.LC5:
.string " regsPerBlock: %d\n"
.LC6:
.string " warpSize: %d\n"
.LC7:
.string " memPitch: %lu\n"
.LC8:
.string " maxThreadsPerBlock: %d\n"
.LC9:
.string " maxThreadsDim:\n"
.LC10:
.string " maxThreadsDim[0]: %d\n"
.LC11:
.string " maxThreadsDim[1]: %d\n"
.LC12:
.string " maxThreadsDim[2]: %d\n"
.LC13:
.string " maxThreadsGridSize:\n"
.LC14:
.string " maxGridSize[0]: %d\n"
.LC15:
.string " maxGridSize[1]: %d\n"
.LC16:
.string " maxGridSize[2]: %d\n"
.LC17:
.string " clockRate: %d\n"
.LC18:
.string " totalConstMem: %lu\n"
.LC19:
.string " major.minor: %d.%d\n"
.LC20:
.string " textureAlignment: %lu\n"
.section .rodata.str1.8
.align 8
.LC21:
.string " texturePitchAlignment: %lu\n"
.section .rodata.str1.1
.LC22:
.string " deviceOverlap: %d\n"
.LC23:
.string " multiProcessorCount: %d\n"
.section .rodata.str1.8
.align 8
.LC24:
.string " kernelExecTimeoutEnabled: %d\n"
.section .rodata.str1.1
.LC25:
.string " integrated: %d\n"
.LC26:
.string " canMapHostMemory: %d\n"
.LC27:
.string " computeMode: %d\n"
.LC28:
.string " maxTexture1D: %d\n"
.LC29:
.string " maxTexture1DLinear: %d\n"
.LC30:
.string " maxTexture2D\n"
.LC31:
.string " maxTexture2D[0]: %d\n"
.LC32:
.string " maxTexture2D[1]: %d\n"
.LC33:
.string " maxTexture2DLinear\n"
.section .rodata.str1.8
.align 8
.LC34:
.string " maxTexture2DLinear[0]: %d\n"
.align 8
.LC35:
.string " maxTexture2DLinear[1]: %d\n"
.align 8
.LC36:
.string " maxTexture2DLinear[2]: %d\n"
.section .rodata.str1.1
.LC37:
.string " maxTexture2DGather\n"
.section .rodata.str1.8
.align 8
.LC38:
.string " maxTexture2DGather[0]: %d\n"
.align 8
.LC39:
.string " maxTexture2DGather[1]: %d\n"
.section .rodata.str1.1
.LC40:
.string " maxTexture3D\n"
.LC41:
.string " maxTexture3D[0]: %d\n"
.LC42:
.string " maxTexture3D[1]: %d\n"
.LC43:
.string " maxTexture3D[2]: %d\n"
.LC44:
.string " maxSurface1D: %d\n"
.LC45:
.string " maxSurface2D\n"
.LC46:
.string " maxSurface2D[0]: %d\n"
.LC47:
.string " maxSurface2D[1]: %d\n"
.LC48:
.string " maxSurface3D\n"
.LC49:
.string " maxSueface3D[0]: %d\n"
.LC50:
.string " maxSueface3D[1]: %d\n"
.LC51:
.string " maxSueface3D[2]: %d\n"
.LC52:
.string " maxSurface1DLayered\n"
.section .rodata.str1.8
.align 8
.LC53:
.string " maxSurface1DLayered[0]: %d\n"
.align 8
.LC54:
.string " maxSurface1DLayered[1]: %d\n"
.section .rodata.str1.1
.LC55:
.string " maxSurface2DLayered\n"
.section .rodata.str1.8
.align 8
.LC56:
.string " maxSurface2DLayered[0]: %d\n"
.align 8
.LC57:
.string " maxSurface2DLayered[1]: %d\n"
.align 8
.LC58:
.string " maxSurface2DLayered[2]: %d\n"
.section .rodata.str1.1
.LC59:
.string " maxSurfaceCubemap: %d\n"
.LC60:
.string " maxSurfaceCubemapLayered\n"
.section .rodata.str1.8
.align 8
.LC61:
.string " maxSurfaceCubemapLayered[0]: %d\n"
.align 8
.LC62:
.string " maxSurfaceCubemapLayered[1]: %d\n"
.section .rodata.str1.1
.LC63:
.string " surfaceAlignment: %ld\n"
.LC64:
.string " concurrentKernels: %d\n"
.LC65:
.string " ECCEnabled: %d\n"
.LC66:
.string " pciBusID: %d\n"
.LC67:
.string " pciDeviceID: %d\n"
.LC68:
.string " pciDomainID: %d\n"
.LC69:
.string " tccDriver: %d\n"
.LC70:
.string " asyncEngineCount: %d\n"
.LC71:
.string " unifiedAddressing: %d\n"
.LC72:
.string " memoryClockRate: %d\n"
.LC73:
.string " l2CacheSize: %d\n"
.section .rodata.str1.8
.align 8
.LC74:
.string " maxThreadsPerMultiProcessor: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $1048, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L7
.L4:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rsp, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 288(%rsp), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 296(%rsp), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 304(%rsp), %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 308(%rsp), %ecx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 312(%rsp), %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 320(%rsp), %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 324(%rsp), %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 328(%rsp), %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 332(%rsp), %ecx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 336(%rsp), %ecx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 340(%rsp), %ecx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 344(%rsp), %ecx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 348(%rsp), %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 352(%rsp), %rcx
leaq .LC18(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 364(%rsp), %r8d
movl 360(%rsp), %ecx
leaq .LC19(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 368(%rsp), %rcx
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 376(%rsp), %rcx
leaq .LC21(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 384(%rsp), %ecx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 388(%rsp), %ecx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 392(%rsp), %ecx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 396(%rsp), %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 400(%rsp), %ecx
leaq .LC26(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 404(%rsp), %ecx
leaq .LC27(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 408(%rsp), %ecx
leaq .LC28(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 416(%rsp), %ecx
leaq .LC29(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC30(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 420(%rsp), %ecx
leaq .LC31(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 424(%rsp), %ecx
leaq .LC32(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC33(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 436(%rsp), %ecx
leaq .LC34(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 440(%rsp), %ecx
leaq .LC35(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 444(%rsp), %ecx
leaq .LC36(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC37(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 448(%rsp), %ecx
leaq .LC38(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 452(%rsp), %ecx
leaq .LC39(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC40(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 456(%rsp), %ecx
leaq .LC41(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 460(%rsp), %ecx
leaq .LC42(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 464(%rsp), %ecx
leaq .LC43(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 512(%rsp), %ecx
leaq .LC44(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC45(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 516(%rsp), %ecx
leaq .LC46(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 520(%rsp), %ecx
leaq .LC47(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC48(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 524(%rsp), %ecx
leaq .LC49(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 528(%rsp), %ecx
leaq .LC50(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 532(%rsp), %ecx
leaq .LC51(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC52(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 536(%rsp), %ecx
leaq .LC53(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 540(%rsp), %ecx
leaq .LC54(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC55(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 544(%rsp), %ecx
leaq .LC56(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 548(%rsp), %ecx
leaq .LC57(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 552(%rsp), %ecx
leaq .LC58(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 556(%rsp), %ecx
leaq .LC59(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC60(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 560(%rsp), %ecx
leaq .LC61(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 564(%rsp), %ecx
leaq .LC62(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 568(%rsp), %rcx
leaq .LC63(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 576(%rsp), %ecx
leaq .LC64(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 580(%rsp), %ecx
leaq .LC65(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 584(%rsp), %ecx
leaq .LC66(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 588(%rsp), %ecx
leaq .LC67(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 592(%rsp), %ecx
leaq .LC68(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 596(%rsp), %ecx
leaq .LC69(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 600(%rsp), %ecx
leaq .LC70(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 604(%rsp), %ecx
leaq .LC71(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 608(%rsp), %ecx
leaq .LC72(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 616(%rsp), %ecx
leaq .LC73(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 624(%rsp), %ecx
leaq .LC74(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "getDeviceProp.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1488
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_1
.LBB0_2:
movq stdout(%rip), %rcx
movl $.L.str.1, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
leaq 8(%rsp), %rdx
movl $.L.str.2, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 296(%rsp), %rdx
movl $.L.str.3, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 304(%rsp), %rdx
movl $.L.str.4, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 312(%rsp), %edx
movl $.L.str.5, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 316(%rsp), %edx
movl $.L.str.6, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 320(%rsp), %rdx
movl $.L.str.7, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 328(%rsp), %edx
movl $.L.str.8, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.9, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 332(%rsp), %edx
movl $.L.str.10, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 336(%rsp), %edx
movl $.L.str.11, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 340(%rsp), %edx
movl $.L.str.12, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.13, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 344(%rsp), %edx
movl $.L.str.14, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 348(%rsp), %edx
movl $.L.str.15, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 352(%rsp), %edx
movl $.L.str.16, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 356(%rsp), %edx
movl $.L.str.17, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 360(%rsp), %rdx
movl $.L.str.18, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 368(%rsp), %edx
movl 372(%rsp), %ecx
movl $.L.str.19, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 376(%rsp), %rdx
movl $.L.str.20, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 384(%rsp), %rdx
movl $.L.str.21, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 392(%rsp), %edx
movl $.L.str.22, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 396(%rsp), %edx
movl $.L.str.23, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 400(%rsp), %edx
movl $.L.str.24, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 404(%rsp), %edx
movl $.L.str.25, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 408(%rsp), %edx
movl $.L.str.26, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 412(%rsp), %edx
movl $.L.str.27, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 416(%rsp), %edx
movl $.L.str.28, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 424(%rsp), %edx
movl $.L.str.29, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.30, %edi
movl $16, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 428(%rsp), %edx
movl $.L.str.31, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 432(%rsp), %edx
movl $.L.str.32, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.33, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 444(%rsp), %edx
movl $.L.str.34, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 448(%rsp), %edx
movl $.L.str.35, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 452(%rsp), %edx
movl $.L.str.36, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.37, %edi
movl $22, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 456(%rsp), %edx
movl $.L.str.38, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 460(%rsp), %edx
movl $.L.str.39, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.40, %edi
movl $16, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 464(%rsp), %edx
movl $.L.str.41, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 468(%rsp), %edx
movl $.L.str.42, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 472(%rsp), %edx
movl $.L.str.43, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 520(%rsp), %edx
movl $.L.str.44, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.45, %edi
movl $16, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 524(%rsp), %edx
movl $.L.str.46, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 528(%rsp), %edx
movl $.L.str.47, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.48, %edi
movl $16, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 532(%rsp), %edx
movl $.L.str.49, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 536(%rsp), %edx
movl $.L.str.50, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 540(%rsp), %edx
movl $.L.str.51, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.52, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 544(%rsp), %edx
movl $.L.str.53, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 548(%rsp), %edx
movl $.L.str.54, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.55, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 552(%rsp), %edx
movl $.L.str.56, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 556(%rsp), %edx
movl $.L.str.57, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 560(%rsp), %edx
movl $.L.str.58, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 564(%rsp), %edx
movl $.L.str.59, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rcx
movl $.L.str.60, %edi
movl $28, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movl 568(%rsp), %edx
movl $.L.str.61, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 572(%rsp), %edx
movl $.L.str.62, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movq 576(%rsp), %rdx
movl $.L.str.63, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 584(%rsp), %edx
movl $.L.str.64, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 588(%rsp), %edx
movl $.L.str.65, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 592(%rsp), %edx
movl $.L.str.66, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 596(%rsp), %edx
movl $.L.str.67, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 600(%rsp), %edx
movl $.L.str.68, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 604(%rsp), %edx
movl $.L.str.69, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 608(%rsp), %edx
movl $.L.str.70, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 612(%rsp), %edx
movl $.L.str.71, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 616(%rsp), %edx
movl $.L.str.72, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 624(%rsp), %edx
movl $.L.str.73, %esi
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
movl 632(%rsp), %edx
movl $.L.str.74, %esi
xorl %eax, %eax
callq fprintf
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 1488
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $35, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB0_2
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "no device avalible, go a hell, man\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "get prop success\n"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " name: %s\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " totalGlobalMem: %lu\n"
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " sharedMemPerBlock: %lu\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " regsPerBlock: %d\n"
.size .L.str.5, 21
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " warpSize: %d\n"
.size .L.str.6, 17
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " memPitch: %lu\n"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " maxThreadsPerBlock: %d\n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " maxThreadsDim:\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " maxThreadsDim[0]: %d\n"
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " maxThreadsDim[1]: %d\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " maxThreadsDim[2]: %d\n"
.size .L.str.12, 29
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " maxThreadsGridSize:\n"
.size .L.str.13, 24
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " maxGridSize[0]: %d\n"
.size .L.str.14, 27
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " maxGridSize[1]: %d\n"
.size .L.str.15, 27
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " maxGridSize[2]: %d\n"
.size .L.str.16, 27
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " clockRate: %d\n"
.size .L.str.17, 18
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " totalConstMem: %lu\n"
.size .L.str.18, 23
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " major.minor: %d.%d\n"
.size .L.str.19, 23
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " textureAlignment: %lu\n"
.size .L.str.20, 26
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " texturePitchAlignment: %lu\n"
.size .L.str.21, 31
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz " deviceOverlap: %d\n"
.size .L.str.22, 22
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz " multiProcessorCount: %d\n"
.size .L.str.23, 28
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz " kernelExecTimeoutEnabled: %d\n"
.size .L.str.24, 33
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz " integrated: %d\n"
.size .L.str.25, 19
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz " canMapHostMemory: %d\n"
.size .L.str.26, 25
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz " computeMode: %d\n"
.size .L.str.27, 20
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz " maxTexture1D: %d\n"
.size .L.str.28, 21
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz " maxTexture1DLinear: %d\n"
.size .L.str.29, 27
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz " maxTexture2D\n"
.size .L.str.30, 17
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz " maxTexture2D[0]: %d\n"
.size .L.str.31, 28
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz " maxTexture2D[1]: %d\n"
.size .L.str.32, 28
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz " maxTexture2DLinear\n"
.size .L.str.33, 23
.type .L.str.34,@object # @.str.34
.L.str.34:
.asciz " maxTexture2DLinear[0]: %d\n"
.size .L.str.34, 34
.type .L.str.35,@object # @.str.35
.L.str.35:
.asciz " maxTexture2DLinear[1]: %d\n"
.size .L.str.35, 34
.type .L.str.36,@object # @.str.36
.L.str.36:
.asciz " maxTexture2DLinear[2]: %d\n"
.size .L.str.36, 34
.type .L.str.37,@object # @.str.37
.L.str.37:
.asciz " maxTexture2DGather\n"
.size .L.str.37, 23
.type .L.str.38,@object # @.str.38
.L.str.38:
.asciz " maxTexture2DGather[0]: %d\n"
.size .L.str.38, 34
.type .L.str.39,@object # @.str.39
.L.str.39:
.asciz " maxTexture2DGather[1]: %d\n"
.size .L.str.39, 34
.type .L.str.40,@object # @.str.40
.L.str.40:
.asciz " maxTexture3D\n"
.size .L.str.40, 17
.type .L.str.41,@object # @.str.41
.L.str.41:
.asciz " maxTexture3D[0]: %d\n"
.size .L.str.41, 28
.type .L.str.42,@object # @.str.42
.L.str.42:
.asciz " maxTexture3D[1]: %d\n"
.size .L.str.42, 28
.type .L.str.43,@object # @.str.43
.L.str.43:
.asciz " maxTexture3D[2]: %d\n"
.size .L.str.43, 28
.type .L.str.44,@object # @.str.44
.L.str.44:
.asciz " maxSurface1D: %d\n"
.size .L.str.44, 21
.type .L.str.45,@object # @.str.45
.L.str.45:
.asciz " maxSurface2D\n"
.size .L.str.45, 17
.type .L.str.46,@object # @.str.46
.L.str.46:
.asciz " maxSurface2D[0]: %d\n"
.size .L.str.46, 28
.type .L.str.47,@object # @.str.47
.L.str.47:
.asciz " maxSurface2D[1]: %d\n"
.size .L.str.47, 28
.type .L.str.48,@object # @.str.48
.L.str.48:
.asciz " maxSurface3D\n"
.size .L.str.48, 17
.type .L.str.49,@object # @.str.49
.L.str.49:
.asciz " maxSueface3D[0]: %d\n"
.size .L.str.49, 28
.type .L.str.50,@object # @.str.50
.L.str.50:
.asciz " maxSueface3D[1]: %d\n"
.size .L.str.50, 28
.type .L.str.51,@object # @.str.51
.L.str.51:
.asciz " maxSueface3D[2]: %d\n"
.size .L.str.51, 28
.type .L.str.52,@object # @.str.52
.L.str.52:
.asciz " maxSurface1DLayered\n"
.size .L.str.52, 24
.type .L.str.53,@object # @.str.53
.L.str.53:
.asciz " maxSurface1DLayered[0]: %d\n"
.size .L.str.53, 35
.type .L.str.54,@object # @.str.54
.L.str.54:
.asciz " maxSurface1DLayered[1]: %d\n"
.size .L.str.54, 35
.type .L.str.55,@object # @.str.55
.L.str.55:
.asciz " maxSurface2DLayered\n"
.size .L.str.55, 24
.type .L.str.56,@object # @.str.56
.L.str.56:
.asciz " maxSurface2DLayered[0]: %d\n"
.size .L.str.56, 35
.type .L.str.57,@object # @.str.57
.L.str.57:
.asciz " maxSurface2DLayered[1]: %d\n"
.size .L.str.57, 35
.type .L.str.58,@object # @.str.58
.L.str.58:
.asciz " maxSurface2DLayered[2]: %d\n"
.size .L.str.58, 35
.type .L.str.59,@object # @.str.59
.L.str.59:
.asciz " maxSurfaceCubemap: %d\n"
.size .L.str.59, 26
.type .L.str.60,@object # @.str.60
.L.str.60:
.asciz " maxSurfaceCubemapLayered\n"
.size .L.str.60, 29
.type .L.str.61,@object # @.str.61
.L.str.61:
.asciz " maxSurfaceCubemapLayered[0]: %d\n"
.size .L.str.61, 40
.type .L.str.62,@object # @.str.62
.L.str.62:
.asciz " maxSurfaceCubemapLayered[1]: %d\n"
.size .L.str.62, 40
.type .L.str.63,@object # @.str.63
.L.str.63:
.asciz " surfaceAlignment: %ld\n"
.size .L.str.63, 26
.type .L.str.64,@object # @.str.64
.L.str.64:
.asciz " concurrentKernels: %d\n"
.size .L.str.64, 26
.type .L.str.65,@object # @.str.65
.L.str.65:
.asciz " ECCEnabled: %d\n"
.size .L.str.65, 19
.type .L.str.66,@object # @.str.66
.L.str.66:
.asciz " pciBusID: %d\n"
.size .L.str.66, 17
.type .L.str.67,@object # @.str.67
.L.str.67:
.asciz " pciDeviceID: %d\n"
.size .L.str.67, 20
.type .L.str.68,@object # @.str.68
.L.str.68:
.asciz " pciDomainID: %d\n"
.size .L.str.68, 20
.type .L.str.69,@object # @.str.69
.L.str.69:
.asciz " tccDriver: %d\n"
.size .L.str.69, 18
.type .L.str.70,@object # @.str.70
.L.str.70:
.asciz " asyncEngineCount: %d\n"
.size .L.str.70, 25
.type .L.str.71,@object # @.str.71
.L.str.71:
.asciz " unifiedAddressing: %d\n"
.size .L.str.71, 26
.type .L.str.72,@object # @.str.72
.L.str.72:
.asciz " memoryClockRate: %d\n"
.size .L.str.72, 24
.type .L.str.73,@object # @.str.73
.L.str.73:
.asciz " l2CacheSize: %d\n"
.size .L.str.73, 20
.type .L.str.74,@object # @.str.74
.L.str.74:
.asciz " maxThreadsPerMultiProcessor: %d\n"
.size .L.str.74, 36
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
__global__ void kernel(int *a)
{
a[blockIdx.x * blockDim.x + threadIdx.x ] = 0;
}
double tiempo( void )
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) (tv.tv_usec) / 1000000 + (double) (tv.tv_sec);
}
int main(int argc, char** argv)
{
double tiempoInicio;
double tiempoFin;
int n;
if (argc == 2)
{
n = atoi(argv[1]);
} else {
n = 64;
}
printf("\nElementos a reservar: %d\n\n\n", n);
int numBytes = n * sizeof(int);
int *d_a;
int *h_a;
cudaMalloc((void **) &d_a, numBytes );
h_a = (int *)malloc(numBytes);
dim3 blockSize(8);
dim3 gridSize(8);
tiempoInicio = tiempo();
kernel <<<gridSize, blockSize>>>(d_a);
cudaThreadSynchronize();
tiempoFin = tiempo();
if ( cudaSuccess != cudaGetLastError() )
printf( "Error!\n" );
printf("Tiempo de inicio Kernel: %lf\n", tiempoInicio);
printf("Tiempo de fin Kernel: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
tiempoInicio = tiempo();
cudaMemcpy (d_a, h_a, numBytes, cudaMemcpyDeviceToHost);
tiempoFin = tiempo();
printf("Tiempo de inicio Transferencia: %lf\n", tiempoInicio);
printf("Tiempo de fin Transferencia: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n", tiempoFin - tiempoInicio);
printf("Done.\n");
return 0;
} | code for sm_80
Function : _Z6kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
__global__ void kernel(int *a)
{
a[blockIdx.x * blockDim.x + threadIdx.x ] = 0;
}
double tiempo( void )
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) (tv.tv_usec) / 1000000 + (double) (tv.tv_sec);
}
int main(int argc, char** argv)
{
double tiempoInicio;
double tiempoFin;
int n;
if (argc == 2)
{
n = atoi(argv[1]);
} else {
n = 64;
}
printf("\nElementos a reservar: %d\n\n\n", n);
int numBytes = n * sizeof(int);
int *d_a;
int *h_a;
cudaMalloc((void **) &d_a, numBytes );
h_a = (int *)malloc(numBytes);
dim3 blockSize(8);
dim3 gridSize(8);
tiempoInicio = tiempo();
kernel <<<gridSize, blockSize>>>(d_a);
cudaThreadSynchronize();
tiempoFin = tiempo();
if ( cudaSuccess != cudaGetLastError() )
printf( "Error!\n" );
printf("Tiempo de inicio Kernel: %lf\n", tiempoInicio);
printf("Tiempo de fin Kernel: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
tiempoInicio = tiempo();
cudaMemcpy (d_a, h_a, numBytes, cudaMemcpyDeviceToHost);
tiempoFin = tiempo();
printf("Tiempo de inicio Transferencia: %lf\n", tiempoInicio);
printf("Tiempo de fin Transferencia: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n", tiempoFin - tiempoInicio);
printf("Done.\n");
return 0;
} | .file "tmpxft_000932d8_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6tiempov
.type _Z6tiempov, @function
_Z6tiempov:
.LFB2070:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z6tiempov, .-_Z6tiempov
.globl _Z25__device_stub__Z6kernelPiPi
.type _Z25__device_stub__Z6kernelPiPi, @function
_Z25__device_stub__Z6kernelPiPi:
.LFB2096:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z25__device_stub__Z6kernelPiPi, .-_Z25__device_stub__Z6kernelPiPi
.globl _Z6kernelPi
.type _Z6kernelPi, @function
_Z6kernelPi:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z6kernelPi, .-_Z6kernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nElementos a reservar: %d\n\n\n"
.LC2:
.string "Error!\n"
.LC3:
.string "Tiempo de inicio Kernel: %lf\n"
.LC4:
.string "Tiempo de fin Kernel: %lf\n"
.LC5:
.string "Tiempo total: %lf\n\n\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Tiempo de inicio Transferencia: %lf\n"
.align 8
.LC7:
.string "Tiempo de fin Transferencia: %lf\n"
.section .rodata.str1.1
.LC8:
.string "Tiempo total: %lf\n"
.LC9:
.string "Done.\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %ebx
cmpl $2, %edi
je .L22
.L16:
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
sall $2, %ebx
movslq %ebx, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $8, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $8, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
call _Z6tiempov
movsd %xmm0, (%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L17:
call cudaThreadSynchronize@PLT
call _Z6tiempov
movsd %xmm0, 8(%rsp)
call cudaGetLastError@PLT
testl %eax, %eax
jne .L24
.L18:
movsd (%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm1
subsd (%rsp), %xmm1
movapd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z6tiempov
movsd %xmm0, (%rsp)
movl $2, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call _Z6tiempov
movsd %xmm0, 8(%rsp)
movsd (%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm2
subsd (%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L16
.L23:
movq 24(%rsp), %rdi
call _Z25__device_stub__Z6kernelPiPi
jmp .L17
.L24:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z6kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
__global__ void kernel(int *a)
{
a[blockIdx.x * blockDim.x + threadIdx.x ] = 0;
}
double tiempo( void )
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) (tv.tv_usec) / 1000000 + (double) (tv.tv_sec);
}
int main(int argc, char** argv)
{
double tiempoInicio;
double tiempoFin;
int n;
if (argc == 2)
{
n = atoi(argv[1]);
} else {
n = 64;
}
printf("\nElementos a reservar: %d\n\n\n", n);
int numBytes = n * sizeof(int);
int *d_a;
int *h_a;
cudaMalloc((void **) &d_a, numBytes );
h_a = (int *)malloc(numBytes);
dim3 blockSize(8);
dim3 gridSize(8);
tiempoInicio = tiempo();
kernel <<<gridSize, blockSize>>>(d_a);
cudaThreadSynchronize();
tiempoFin = tiempo();
if ( cudaSuccess != cudaGetLastError() )
printf( "Error!\n" );
printf("Tiempo de inicio Kernel: %lf\n", tiempoInicio);
printf("Tiempo de fin Kernel: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
tiempoInicio = tiempo();
cudaMemcpy (d_a, h_a, numBytes, cudaMemcpyDeviceToHost);
tiempoFin = tiempo();
printf("Tiempo de inicio Transferencia: %lf\n", tiempoInicio);
printf("Tiempo de fin Transferencia: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n", tiempoFin - tiempoInicio);
printf("Done.\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
__global__ void kernel(int *a)
{
a[blockIdx.x * blockDim.x + threadIdx.x ] = 0;
}
double tiempo( void )
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) (tv.tv_usec) / 1000000 + (double) (tv.tv_sec);
}
int main(int argc, char** argv)
{
double tiempoInicio;
double tiempoFin;
int n;
if (argc == 2)
{
n = atoi(argv[1]);
} else {
n = 64;
}
printf("\nElementos a reservar: %d\n\n\n", n);
int numBytes = n * sizeof(int);
int *d_a;
int *h_a;
hipMalloc((void **) &d_a, numBytes );
h_a = (int *)malloc(numBytes);
dim3 blockSize(8);
dim3 gridSize(8);
tiempoInicio = tiempo();
kernel <<<gridSize, blockSize>>>(d_a);
hipDeviceSynchronize();
tiempoFin = tiempo();
if ( hipSuccess != hipGetLastError() )
printf( "Error!\n" );
printf("Tiempo de inicio Kernel: %lf\n", tiempoInicio);
printf("Tiempo de fin Kernel: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
tiempoInicio = tiempo();
hipMemcpy (d_a, h_a, numBytes, hipMemcpyDeviceToHost);
tiempoFin = tiempo();
printf("Tiempo de inicio Transferencia: %lf\n", tiempoInicio);
printf("Tiempo de fin Transferencia: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n", tiempoFin - tiempoInicio);
printf("Done.\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
__global__ void kernel(int *a)
{
a[blockIdx.x * blockDim.x + threadIdx.x ] = 0;
}
double tiempo( void )
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) (tv.tv_usec) / 1000000 + (double) (tv.tv_sec);
}
int main(int argc, char** argv)
{
double tiempoInicio;
double tiempoFin;
int n;
if (argc == 2)
{
n = atoi(argv[1]);
} else {
n = 64;
}
printf("\nElementos a reservar: %d\n\n\n", n);
int numBytes = n * sizeof(int);
int *d_a;
int *h_a;
hipMalloc((void **) &d_a, numBytes );
h_a = (int *)malloc(numBytes);
dim3 blockSize(8);
dim3 gridSize(8);
tiempoInicio = tiempo();
kernel <<<gridSize, blockSize>>>(d_a);
hipDeviceSynchronize();
tiempoFin = tiempo();
if ( hipSuccess != hipGetLastError() )
printf( "Error!\n" );
printf("Tiempo de inicio Kernel: %lf\n", tiempoInicio);
printf("Tiempo de fin Kernel: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
tiempoInicio = tiempo();
hipMemcpy (d_a, h_a, numBytes, hipMemcpyDeviceToHost);
tiempoFin = tiempo();
printf("Tiempo de inicio Transferencia: %lf\n", tiempoInicio);
printf("Tiempo de fin Transferencia: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n", tiempoFin - tiempoInicio);
printf("Done.\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPi, .Lfunc_end0-_Z6kernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
__global__ void kernel(int *a)
{
a[blockIdx.x * blockDim.x + threadIdx.x ] = 0;
}
double tiempo( void )
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) (tv.tv_usec) / 1000000 + (double) (tv.tv_sec);
}
int main(int argc, char** argv)
{
double tiempoInicio;
double tiempoFin;
int n;
if (argc == 2)
{
n = atoi(argv[1]);
} else {
n = 64;
}
printf("\nElementos a reservar: %d\n\n\n", n);
int numBytes = n * sizeof(int);
int *d_a;
int *h_a;
hipMalloc((void **) &d_a, numBytes );
h_a = (int *)malloc(numBytes);
dim3 blockSize(8);
dim3 gridSize(8);
tiempoInicio = tiempo();
kernel <<<gridSize, blockSize>>>(d_a);
hipDeviceSynchronize();
tiempoFin = tiempo();
if ( hipSuccess != hipGetLastError() )
printf( "Error!\n" );
printf("Tiempo de inicio Kernel: %lf\n", tiempoInicio);
printf("Tiempo de fin Kernel: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
tiempoInicio = tiempo();
hipMemcpy (d_a, h_a, numBytes, hipMemcpyDeviceToHost);
tiempoFin = tiempo();
printf("Tiempo de inicio Transferencia: %lf\n", tiempoInicio);
printf("Tiempo de fin Transferencia: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n", tiempoFin - tiempoInicio);
printf("Done.\n");
return 0;
} | .text
.file "main.hip"
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPi,@function
_Z21__device_stub__kernelPi: # @_Z21__device_stub__kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPi, .Lfunc_end0-_Z21__device_stub__kernelPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6tiempov
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z6tiempov
.p2align 4, 0x90
.type _Z6tiempov,@function
_Z6tiempov: # @_Z6tiempov
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI1_0(%rip), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6tiempov, .Lfunc_end1-_Z6tiempov
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $64, %ebx
cmpl $2, %edi
jne .LBB2_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB2_2:
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
shll $2, %ebx
movslq %ebx, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbx, %rdi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %r15
movq 16(%rsp), %r12
movabsq $4294967304, %rdi # imm = 0x100000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 40(%rsp), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 48(%rsp)
leaq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %r13
movq 16(%rsp), %rbp
callq hipGetLastError
testl %eax, %eax
je .LBB2_6
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_6:
cvtsi2sd %rbp, %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
cvtsi2sd %r13, %xmm2
divsd %xmm1, %xmm0
addsd %xmm0, %xmm2
movsd %xmm2, 24(%rsp) # 8-byte Spill
xorps %xmm2, %xmm2
cvtsi2sd %r12, %xmm2
divsd %xmm1, %xmm2
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
addsd %xmm2, %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $.L.str.3, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.4, %edi
movb $1, %al
callq printf
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 32(%rsp) # 8-byte Spill
movl $.L.str.5, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.6, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPi,@object # @_Z6kernelPi
.section .rodata,"a",@progbits
.globl _Z6kernelPi
.p2align 3, 0x0
_Z6kernelPi:
.quad _Z21__device_stub__kernelPi
.size _Z6kernelPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nElementos a reservar: %d\n\n\n"
.size .L.str, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Tiempo de inicio Kernel: %lf\n"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Tiempo de fin Kernel: %lf\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo total: %lf\n\n\n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Tiempo de inicio Transferencia: %lf\n"
.size .L.str.5, 37
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Tiempo de fin Transferencia: %lf\n"
.size .L.str.6, 34
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Tiempo total: %lf\n"
.size .L.str.7, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error!"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Done."
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPi, .Lfunc_end0-_Z6kernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000932d8_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6tiempov
.type _Z6tiempov, @function
_Z6tiempov:
.LFB2070:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z6tiempov, .-_Z6tiempov
.globl _Z25__device_stub__Z6kernelPiPi
.type _Z25__device_stub__Z6kernelPiPi, @function
_Z25__device_stub__Z6kernelPiPi:
.LFB2096:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z25__device_stub__Z6kernelPiPi, .-_Z25__device_stub__Z6kernelPiPi
.globl _Z6kernelPi
.type _Z6kernelPi, @function
_Z6kernelPi:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z6kernelPi, .-_Z6kernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nElementos a reservar: %d\n\n\n"
.LC2:
.string "Error!\n"
.LC3:
.string "Tiempo de inicio Kernel: %lf\n"
.LC4:
.string "Tiempo de fin Kernel: %lf\n"
.LC5:
.string "Tiempo total: %lf\n\n\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Tiempo de inicio Transferencia: %lf\n"
.align 8
.LC7:
.string "Tiempo de fin Transferencia: %lf\n"
.section .rodata.str1.1
.LC8:
.string "Tiempo total: %lf\n"
.LC9:
.string "Done.\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %ebx
cmpl $2, %edi
je .L22
.L16:
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
sall $2, %ebx
movslq %ebx, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $8, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $8, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
call _Z6tiempov
movsd %xmm0, (%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L17:
call cudaThreadSynchronize@PLT
call _Z6tiempov
movsd %xmm0, 8(%rsp)
call cudaGetLastError@PLT
testl %eax, %eax
jne .L24
.L18:
movsd (%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm1
subsd (%rsp), %xmm1
movapd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z6tiempov
movsd %xmm0, (%rsp)
movl $2, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call _Z6tiempov
movsd %xmm0, 8(%rsp)
movsd (%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm2
subsd (%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L16
.L23:
movq 24(%rsp), %rdi
call _Z25__device_stub__Z6kernelPiPi
jmp .L17
.L24:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z6kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPi,@function
_Z21__device_stub__kernelPi: # @_Z21__device_stub__kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPi, .Lfunc_end0-_Z21__device_stub__kernelPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6tiempov
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z6tiempov
.p2align 4, 0x90
.type _Z6tiempov,@function
_Z6tiempov: # @_Z6tiempov
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI1_0(%rip), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6tiempov, .Lfunc_end1-_Z6tiempov
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $64, %ebx
cmpl $2, %edi
jne .LBB2_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB2_2:
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
shll $2, %ebx
movslq %ebx, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbx, %rdi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %r15
movq 16(%rsp), %r12
movabsq $4294967304, %rdi # imm = 0x100000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 40(%rsp), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 48(%rsp)
leaq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %r13
movq 16(%rsp), %rbp
callq hipGetLastError
testl %eax, %eax
je .LBB2_6
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_6:
cvtsi2sd %rbp, %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
cvtsi2sd %r13, %xmm2
divsd %xmm1, %xmm0
addsd %xmm0, %xmm2
movsd %xmm2, 24(%rsp) # 8-byte Spill
xorps %xmm2, %xmm2
cvtsi2sd %r12, %xmm2
divsd %xmm1, %xmm2
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
addsd %xmm2, %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $.L.str.3, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.4, %edi
movb $1, %al
callq printf
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 32(%rsp) # 8-byte Spill
movl $.L.str.5, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.6, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPi,@object # @_Z6kernelPi
.section .rodata,"a",@progbits
.globl _Z6kernelPi
.p2align 3, 0x0
_Z6kernelPi:
.quad _Z21__device_stub__kernelPi
.size _Z6kernelPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nElementos a reservar: %d\n\n\n"
.size .L.str, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Tiempo de inicio Kernel: %lf\n"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Tiempo de fin Kernel: %lf\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo total: %lf\n\n\n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Tiempo de inicio Transferencia: %lf\n"
.size .L.str.5, 37
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Tiempo de fin Transferencia: %lf\n"
.size .L.str.6, 34
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Tiempo total: %lf\n"
.size .L.str.7, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error!"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Done."
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <iostream>
#include <iomanip>
#include <ctime>
#define N 65535
__global__ void vecadd(int *a, int *b, int *c) {
int id = blockIdx.x;
if (id < N)
c[id] = a[id] * b[id];
}
void add(int *a, int *b, int *c) {
for (int id=0; id < N; id++)
c[id] = a[id] * b[id];
}
/*
int main() {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, N *sizeof(int));
cudaMalloc(&dev_b, N *sizeof(int));
cudaMalloc(&dev_c, N *sizeof(int));
for (int i=0; i<N; ++i) {
a[i] = i + 1;
b[i] = i + 2;
}
cudaMemcpy(dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, N * sizeof(int), cudaMemcpyHostToDevice);
clock_t gpu_t = std::clock();
vecadd<<<N, 256>>>(dev_a, dev_b, dev_c);
gpu_t = std::clock() - gpu_t;
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
clock_t cpu_t = std::clock();
add(a, b, c);
cpu_t = std::clock() - cpu_t;
std::cout << std::setprecision(10) << "GPU: " << double(gpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl <<
"CPU: " << double(cpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl;
std::cout << std::setprecision(5) << double(gpu_t) / double(cpu_t) << std::endl;
return 0;
}
*/ | code for sm_80
Function : _Z6vecaddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0xfffe, PT ; /* 0x0000fffe0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <iostream>
#include <iomanip>
#include <ctime>
#define N 65535
__global__ void vecadd(int *a, int *b, int *c) {
int id = blockIdx.x;
if (id < N)
c[id] = a[id] * b[id];
}
void add(int *a, int *b, int *c) {
for (int id=0; id < N; id++)
c[id] = a[id] * b[id];
}
/*
int main() {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, N *sizeof(int));
cudaMalloc(&dev_b, N *sizeof(int));
cudaMalloc(&dev_c, N *sizeof(int));
for (int i=0; i<N; ++i) {
a[i] = i + 1;
b[i] = i + 2;
}
cudaMemcpy(dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, N * sizeof(int), cudaMemcpyHostToDevice);
clock_t gpu_t = std::clock();
vecadd<<<N, 256>>>(dev_a, dev_b, dev_c);
gpu_t = std::clock() - gpu_t;
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
clock_t cpu_t = std::clock();
add(a, b, c);
cpu_t = std::clock() - cpu_t;
std::cout << std::setprecision(10) << "GPU: " << double(gpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl <<
"CPU: " << double(cpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl;
std::cout << std::setprecision(5) << double(gpu_t) / double(cpu_t) << std::endl;
return 0;
}
*/ | .file "tmpxft_0010505f_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3949:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movl (%rdi,%rax), %ecx
imull (%rsi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq $262140, %rax
jne .L4
ret
.cfi_endproc
.LFE3949:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl _Z29__device_stub__Z6vecaddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecaddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecaddPiS_S_PiS_S_:
.LFB3974:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecaddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3974:
.size _Z29__device_stub__Z6vecaddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecaddPiS_S_PiS_S_
.globl _Z6vecaddPiS_S_
.type _Z6vecaddPiS_S_, @function
_Z6vecaddPiS_S_:
.LFB3975:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecaddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3975:
.size _Z6vecaddPiS_S_, .-_Z6vecaddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecaddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3977:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecaddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3977:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <iostream>
#include <iomanip>
#include <ctime>
#define N 65535
__global__ void vecadd(int *a, int *b, int *c) {
int id = blockIdx.x;
if (id < N)
c[id] = a[id] * b[id];
}
void add(int *a, int *b, int *c) {
for (int id=0; id < N; id++)
c[id] = a[id] * b[id];
}
/*
int main() {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, N *sizeof(int));
cudaMalloc(&dev_b, N *sizeof(int));
cudaMalloc(&dev_c, N *sizeof(int));
for (int i=0; i<N; ++i) {
a[i] = i + 1;
b[i] = i + 2;
}
cudaMemcpy(dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, N * sizeof(int), cudaMemcpyHostToDevice);
clock_t gpu_t = std::clock();
vecadd<<<N, 256>>>(dev_a, dev_b, dev_c);
gpu_t = std::clock() - gpu_t;
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
clock_t cpu_t = std::clock();
add(a, b, c);
cpu_t = std::clock() - cpu_t;
std::cout << std::setprecision(10) << "GPU: " << double(gpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl <<
"CPU: " << double(cpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl;
std::cout << std::setprecision(5) << double(gpu_t) / double(cpu_t) << std::endl;
return 0;
}
*/ | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <ctime>
#define N 65535
__global__ void vecadd(int *a, int *b, int *c) {
int id = blockIdx.x;
if (id < N)
c[id] = a[id] * b[id];
}
void add(int *a, int *b, int *c) {
for (int id=0; id < N; id++)
c[id] = a[id] * b[id];
}
/*
int main() {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, N *sizeof(int));
cudaMalloc(&dev_b, N *sizeof(int));
cudaMalloc(&dev_c, N *sizeof(int));
for (int i=0; i<N; ++i) {
a[i] = i + 1;
b[i] = i + 2;
}
cudaMemcpy(dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, N * sizeof(int), cudaMemcpyHostToDevice);
clock_t gpu_t = std::clock();
vecadd<<<N, 256>>>(dev_a, dev_b, dev_c);
gpu_t = std::clock() - gpu_t;
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
clock_t cpu_t = std::clock();
add(a, b, c);
cpu_t = std::clock() - cpu_t;
std::cout << std::setprecision(10) << "GPU: " << double(gpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl <<
"CPU: " << double(cpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl;
std::cout << std::setprecision(5) << double(gpu_t) / double(cpu_t) << std::endl;
return 0;
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <ctime>
#define N 65535
__global__ void vecadd(int *a, int *b, int *c) {
int id = blockIdx.x;
if (id < N)
c[id] = a[id] * b[id];
}
void add(int *a, int *b, int *c) {
for (int id=0; id < N; id++)
c[id] = a[id] * b[id];
}
/*
int main() {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, N *sizeof(int));
cudaMalloc(&dev_b, N *sizeof(int));
cudaMalloc(&dev_c, N *sizeof(int));
for (int i=0; i<N; ++i) {
a[i] = i + 1;
b[i] = i + 2;
}
cudaMemcpy(dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, N * sizeof(int), cudaMemcpyHostToDevice);
clock_t gpu_t = std::clock();
vecadd<<<N, 256>>>(dev_a, dev_b, dev_c);
gpu_t = std::clock() - gpu_t;
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
clock_t cpu_t = std::clock();
add(a, b, c);
cpu_t = std::clock() - cpu_t;
std::cout << std::setprecision(10) << "GPU: " << double(gpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl <<
"CPU: " << double(cpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl;
std::cout << std::setprecision(5) << double(gpu_t) / double(cpu_t) << std::endl;
return 0;
}
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecaddPiS_S_
.globl _Z6vecaddPiS_S_
.p2align 8
.type _Z6vecaddPiS_S_,@function
_Z6vecaddPiS_S_:
s_cmp_gt_i32 s15, 0xfffe
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecaddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecaddPiS_S_, .Lfunc_end0-_Z6vecaddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecaddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z6vecaddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <ctime>
#define N 65535
__global__ void vecadd(int *a, int *b, int *c) {
int id = blockIdx.x;
if (id < N)
c[id] = a[id] * b[id];
}
void add(int *a, int *b, int *c) {
for (int id=0; id < N; id++)
c[id] = a[id] * b[id];
}
/*
int main() {
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, N *sizeof(int));
cudaMalloc(&dev_b, N *sizeof(int));
cudaMalloc(&dev_c, N *sizeof(int));
for (int i=0; i<N; ++i) {
a[i] = i + 1;
b[i] = i + 2;
}
cudaMemcpy(dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, N * sizeof(int), cudaMemcpyHostToDevice);
clock_t gpu_t = std::clock();
vecadd<<<N, 256>>>(dev_a, dev_b, dev_c);
gpu_t = std::clock() - gpu_t;
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
clock_t cpu_t = std::clock();
add(a, b, c);
cpu_t = std::clock() - cpu_t;
std::cout << std::setprecision(10) << "GPU: " << double(gpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl <<
"CPU: " << double(cpu_t) / double(CLOCKS_PER_SEC) << " sec" << std::endl;
std::cout << std::setprecision(5) << double(gpu_t) / double(cpu_t) << std::endl;
return 0;
}
*/ | .text
.file "vector_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__vecaddPiS_S_ # -- Begin function _Z21__device_stub__vecaddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecaddPiS_S_,@function
_Z21__device_stub__vecaddPiS_S_: # @_Z21__device_stub__vecaddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecaddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecaddPiS_S_, .Lfunc_end0-_Z21__device_stub__vecaddPiS_S_
.cfi_endproc
# -- End function
.globl _Z3addPiS_S_ # -- Begin function _Z3addPiS_S_
.p2align 4, 0x90
.type _Z3addPiS_S_,@function
_Z3addPiS_S_: # @_Z3addPiS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl (%rsi,%rax,4), %ecx
imull (%rdi,%rax,4), %ecx
movl %ecx, (%rdx,%rax,4)
incq %rax
cmpq $65535, %rax # imm = 0xFFFF
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z3addPiS_S_, .Lfunc_end1-_Z3addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecaddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecaddPiS_S_,@object # @_Z6vecaddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecaddPiS_S_
.p2align 3, 0x0
_Z6vecaddPiS_S_:
.quad _Z21__device_stub__vecaddPiS_S_
.size _Z6vecaddPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecaddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecaddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecaddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecaddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0xfffe, PT ; /* 0x0000fffe0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecaddPiS_S_
.globl _Z6vecaddPiS_S_
.p2align 8
.type _Z6vecaddPiS_S_,@function
_Z6vecaddPiS_S_:
s_cmp_gt_i32 s15, 0xfffe
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecaddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecaddPiS_S_, .Lfunc_end0-_Z6vecaddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecaddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z6vecaddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010505f_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3949:
.cfi_startproc
endbr64
movl $0, %eax
.L4:
movl (%rdi,%rax), %ecx
imull (%rsi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq $262140, %rax
jne .L4
ret
.cfi_endproc
.LFE3949:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.globl _Z29__device_stub__Z6vecaddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecaddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecaddPiS_S_PiS_S_:
.LFB3974:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecaddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3974:
.size _Z29__device_stub__Z6vecaddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecaddPiS_S_PiS_S_
.globl _Z6vecaddPiS_S_
.type _Z6vecaddPiS_S_, @function
_Z6vecaddPiS_S_:
.LFB3975:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecaddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3975:
.size _Z6vecaddPiS_S_, .-_Z6vecaddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecaddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3977:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecaddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3977:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__vecaddPiS_S_ # -- Begin function _Z21__device_stub__vecaddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecaddPiS_S_,@function
_Z21__device_stub__vecaddPiS_S_: # @_Z21__device_stub__vecaddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecaddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecaddPiS_S_, .Lfunc_end0-_Z21__device_stub__vecaddPiS_S_
.cfi_endproc
# -- End function
.globl _Z3addPiS_S_ # -- Begin function _Z3addPiS_S_
.p2align 4, 0x90
.type _Z3addPiS_S_,@function
_Z3addPiS_S_: # @_Z3addPiS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl (%rsi,%rax,4), %ecx
imull (%rdi,%rax,4), %ecx
movl %ecx, (%rdx,%rax,4)
incq %rax
cmpq $65535, %rax # imm = 0xFFFF
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z3addPiS_S_, .Lfunc_end1-_Z3addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecaddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecaddPiS_S_,@object # @_Z6vecaddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecaddPiS_S_
.p2align 3, 0x0
_Z6vecaddPiS_S_:
.quad _Z21__device_stub__vecaddPiS_S_
.size _Z6vecaddPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecaddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecaddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecaddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define ELEMENT_SIZE 64
#define BLOCK_SIZE 16
extern "C"
__global__ void int8pack_kernel(long *ret, const unsigned char *input, const int ret0, const int ret1, const int input1) {
const int y = blockIdx.x * blockDim.x + threadIdx.x;
const int x = blockIdx.y * blockDim.y + threadIdx.y;
const int tid = threadIdx.y * blockDim.x + threadIdx.x;
const int cache1 = ELEMENT_SIZE / 8 * blockDim.x;
const int square_size = BLOCK_SIZE * BLOCK_SIZE;
const int offset_y = blockIdx.x * blockDim.x * ELEMENT_SIZE / 8;
const int offset = blockIdx.y * blockDim.y * input1 + offset_y;
__shared__ unsigned char cache[BLOCK_SIZE * BLOCK_SIZE * ELEMENT_SIZE / 8];
for (int i = 0; i < ELEMENT_SIZE / 8; i++){
const int idx = i * square_size + tid;
const int x_sub = idx / cache1;
const int y_sub = idx - x_sub * cache1;
cache[x_sub * cache1 + y_sub] = y_sub + offset_y < input1 ? input[x_sub * input1 + y_sub + offset] : 0;
}
__syncthreads();
const int y_input = threadIdx.x * ELEMENT_SIZE / 8;
if (x < ret0 && y < ret1) {
long tmp = 0;
#pragma unroll
for (int i = 0; i < ELEMENT_SIZE / 8; i++) {
tmp |= ((long) cache[threadIdx.y * cache1 + y_input + i] ) << (8 * i);
}
ret[x * ret1 + y] = tmp;
}
} | code for sm_80
Function : int8pack_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0030*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0040*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0050*/ IMAD.SHL.U32 R0, R0, 0x8, RZ ; /* 0x0000000800007824 */
/* 0x000fe200078e00ff */
/*0060*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0070*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IABS R8, R0.reuse ; /* 0x0000000000087213 */
/* 0x080fe40000000000 */
/*00a0*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fc40000000000 */
/*00b0*/ I2F.RP R2, R8 ; /* 0x0000000800027306 */
/* 0x000ea60000209400 */
/*00c0*/ IMAD.MOV R15, RZ, RZ, -R10 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0a0a */
/*00d0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x002fc8000f8e023f */
/*00e0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x004e620000001000 */
/*00f0*/ IMAD R7, R5, c[0x0][0x0], R4 ; /* 0x0000000005077a24 */
/* 0x001fe200078e0204 */
/*0100*/ USHF.L.U32 UR5, UR4, 0x3, URZ ; /* 0x0000000304057899 */
/* 0x000fc8000800063f */
/*0110*/ IABS R6, R7 ; /* 0x0000000700067213 */
/* 0x000fe20000000000 */
/*0120*/ ULOP3.LUT UR5, UR5, 0x1ffffff8, URZ, 0xc0, !UPT ; /* 0x1ffffff805057892 */
/* 0x000fe2000f8ec03f */
/*0130*/ IADD3 R19, R7.reuse, 0x300, RZ ; /* 0x0000030007137810 */
/* 0x040fe40007ffe0ff */
/*0140*/ IADD3 R17, R7, 0x400, RZ ; /* 0x0000040007117810 */
/* 0x000fe40007ffe0ff */
/*0150*/ IABS R25, R19 ; /* 0x0000001300197213 */
/* 0x000fe40000000000 */
/*0160*/ IABS R29, R17 ; /* 0x00000011001d7213 */
/* 0x000fe40000000000 */
/*0170*/ IADD3 R3, R2, 0xffffffe, RZ ; /* 0x0ffffffe02037810 */
/* 0x002fc40007ffe0ff */
/*0180*/ LOP3.LUT R10, R7.reuse, R0.reuse, RZ, 0x3c, !PT ; /* 0x00000000070a7212 */
/* 0x0c0fe400078e3cff */
/*0190*/ F2I.FTZ.U32.TRUNC.NTZ R13, R3 ; /* 0x00000003000d7305 */
/* 0x000062000021f000 */
/*01a0*/ IADD3 R27, R7, 0x500, RZ ; /* 0x00000500071b7810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f26270 */
/*01c0*/ LOP3.LUT R20, R17, R0.reuse, RZ, 0x3c, !PT ; /* 0x0000000011147212 */
/* 0x080fe400078e3cff */
/*01d0*/ LOP3.LUT R22, R27, R0, RZ, 0x3c, !PT ; /* 0x000000001b167212 */
/* 0x000fe400078e3cff */
/*01e0*/ IADD3 R3, R7, 0x200, RZ ; /* 0x0000020007037810 */
/* 0x001fc80007ffe0ff */
/*01f0*/ IABS R2, R3 ; /* 0x0000000300027213 */
/* 0x000fe20000000000 */
/*0200*/ IMAD.MOV R9, RZ, RZ, -R13 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a0d */
/*0210*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*0220*/ IMAD.HI.U32 R12, R13, R9, R12 ; /* 0x000000090d0c7227 */
/* 0x000fe200078e000c */
/*0230*/ IADD3 R13, R7, 0x100, RZ ; /* 0x00000100070d7810 */
/* 0x000fc60007ffe0ff */
/*0240*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0006 */
/*0250*/ IABS R21, R13 ; /* 0x0000000d00157213 */
/* 0x000fe20000000000 */
/*0260*/ IMAD.HI.U32 R11, R12, R2, RZ ; /* 0x000000020c0b7227 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD.HI.U32 R6, R12, R9, RZ ; /* 0x000000090c067227 */
/* 0x000fc800078e00ff */
/*0280*/ IMAD.HI.U32 R18, R12, R21, RZ ; /* 0x000000150c127227 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD R9, R6, R15.reuse, R9 ; /* 0x0000000f06097224 */
/* 0x080fe400078e0209 */
/*02a0*/ IMAD R21, R18, R15.reuse, R21 ; /* 0x0000000f12157224 */
/* 0x080fe400078e0215 */
/*02b0*/ IMAD R23, R11, R15, R2 ; /* 0x0000000f0b177224 */
/* 0x000fe200078e0202 */
/*02c0*/ ISETP.GT.U32.AND P5, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe20003fa4070 */
/*02d0*/ IMAD.HI.U32 R14, R12, R25, RZ ; /* 0x000000190c0e7227 */
/* 0x000fe200078e00ff */
/*02e0*/ ISETP.GT.U32.AND P4, PT, R8.reuse, R21, PT ; /* 0x000000150800720c */
/* 0x040fe40003f84070 */
/*02f0*/ ISETP.GT.U32.AND P3, PT, R8, R23, PT ; /* 0x000000170800720c */
/* 0x000fe20003f64070 */
/*0300*/ IMAD.HI.U32 R16, R12, R29, RZ ; /* 0x0000001d0c107227 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R2, R13, R0, RZ, 0x3c, !PT ; /* 0x000000000d027212 */
/* 0x000fc800078e3cff */
/*0320*/ ISETP.GE.AND P6, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003fc6270 */
/*0330*/ LOP3.LUT R2, R3, R0, RZ, 0x3c, !PT ; /* 0x0000000003027212 */
/* 0x000fe200078e3cff */
/*0340*/ @!P5 IMAD.IADD R9, R9, 0x1, -R8.reuse ; /* 0x000000010909d824 */
/* 0x100fe200078e0a08 */
/*0350*/ @!P5 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606d810 */
/* 0x000fe20007ffe0ff */
/*0360*/ @!P4 IMAD.IADD R21, R21, 0x1, -R8.reuse ; /* 0x000000011515c824 */
/* 0x100fe200078e0a08 */
/*0370*/ @!P4 IADD3 R18, R18, 0x1, RZ ; /* 0x000000011212c810 */
/* 0x000fe20007ffe0ff */
/*0380*/ @!P3 IMAD.IADD R23, R23, 0x1, -R8 ; /* 0x000000011717b824 */
/* 0x000fe200078e0a08 */
/*0390*/ ISETP.GE.U32.AND P2, PT, R9, R8.reuse, PT ; /* 0x000000080900720c */
/* 0x080fe20003f46070 */
/*03a0*/ IMAD R9, R14, R15.reuse, R25 ; /* 0x0000000f0e097224 */
/* 0x080fe200078e0219 */
/*03b0*/ ISETP.GE.U32.AND P0, PT, R21, R8.reuse, PT ; /* 0x000000081500720c */
/* 0x080fe20003f06070 */
/*03c0*/ IMAD R25, R16, R15, R29 ; /* 0x0000000f10197224 */
/* 0x000fe200078e021d */
/*03d0*/ ISETP.GE.U32.AND P4, PT, R23, R8, PT ; /* 0x000000081700720c */
/* 0x000fc40003f86070 */
/*03e0*/ ISETP.GT.U32.AND P5, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003fa4070 */
/*03f0*/ IABS R21, R27 ; /* 0x0000001b00157213 */
/* 0x000fe40000000000 */
/*0400*/ @!P3 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0bb810 */
/* 0x000fe40007ffe0ff */
/*0410*/ IADD3 R23, R7, 0x700, RZ ; /* 0x0000070007177810 */
/* 0x000fe40007ffe0ff */
/*0420*/ @P2 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106062810 */
/* 0x000fe40007ffe0ff */
/*0430*/ @P0 IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112120810 */
/* 0x000fc40007ffe0ff */
/*0440*/ ISETP.GT.U32.AND P0, PT, R8, R25, PT ; /* 0x000000190800720c */
/* 0x000fe20003f04070 */
/*0450*/ @!P5 IMAD.IADD R9, R9, 0x1, -R8 ; /* 0x000000010909d824 */
/* 0x000fe200078e0a08 */
/*0460*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*0470*/ @!P6 IMAD.MOV R18, RZ, RZ, -R18 ; /* 0x000000ffff12e224 */
/* 0x000fe200078e0a12 */
/*0480*/ LOP3.LUT R2, R19, R0, RZ, 0x3c, !PT ; /* 0x0000000013027212 */
/* 0x000fe200078e3cff */
/*0490*/ @!P1 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0a06 */
/*04a0*/ ISETP.GE.U32.AND P6, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x000fe40003fc6070 */
/*04b0*/ IADD3 R9, R7, 0x600, RZ ; /* 0x0000060007097810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*04d0*/ IMAD.HI.U32 R2, R12, R21, RZ ; /* 0x000000150c027227 */
/* 0x000fe200078e00ff */
/*04e0*/ IABS R10, R9 ; /* 0x00000009000a7213 */
/* 0x000fc40000000000 */
/*04f0*/ @P4 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b4810 */
/* 0x000fe20007ffe0ff */
/*0500*/ @!P0 IMAD.IADD R25, R25, 0x1, -R8 ; /* 0x0000000119198824 */
/* 0x000fe200078e0a08 */
/*0510*/ IABS R29, R23 ; /* 0x00000017001d7213 */
/* 0x000fe20000000000 */
/*0520*/ IMAD R21, R2, R15, R21 ; /* 0x0000000f02157224 */
/* 0x000fe200078e0215 */
/*0530*/ @!P5 IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0ed810 */
/* 0x000fe20007ffe0ff */
/*0540*/ @!P2 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0ba224 */
/* 0x000fe200078e0a0b */
/*0550*/ ISETP.GE.U32.AND P4, PT, R25, R8, PT ; /* 0x000000081900720c */
/* 0x000fe20003f86070 */
/*0560*/ IMAD.MOV.U32 R25, RZ, RZ, R10 ; /* 0x000000ffff197224 */
/* 0x000fe200078e000a */
/*0570*/ ISETP.GT.U32.AND P3, PT, R8, R21, PT ; /* 0x000000150800720c */
/* 0x000fe40003f64070 */
/*0580*/ ISETP.GE.AND P5, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003fa6270 */
/*0590*/ IMAD.HI.U32 R10, R12, R25, RZ ; /* 0x000000190c0a7227 */
/* 0x000fe200078e00ff */
/*05a0*/ @!P0 IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110108810 */
/* 0x000fc40007ffe0ff */
/*05b0*/ @P6 IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e6810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ IMAD.HI.U32 R12, R12, R29, RZ ; /* 0x0000001d0c0c7227 */
/* 0x000fe200078e00ff */
/*05d0*/ ISETP.GE.AND P6, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc60003fc6270 */
/*05e0*/ IMAD R29, R12, R15.reuse, R29 ; /* 0x0000000f0c1d7224 */
/* 0x080fe200078e021d */
/*05f0*/ @P4 IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110104810 */
/* 0x000fe20007ffe0ff */
/*0600*/ IMAD R20, R10, R15, R25 ; /* 0x0000000f0a147224 */
/* 0x000fe200078e0219 */
/*0610*/ LOP3.LUT R15, R9, R0, RZ, 0x3c, !PT ; /* 0x00000000090f7212 */
/* 0x000fe200078e3cff */
/*0620*/ @!P3 IMAD.IADD R21, R21, 0x1, -R8 ; /* 0x000000011515b824 */
/* 0x000fe200078e0a08 */
/*0630*/ ISETP.GT.U32.AND P2, PT, R8.reuse, R29, PT ; /* 0x0000001d0800720c */
/* 0x040fe20003f44070 */
/*0640*/ @!P5 IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff10d224 */
/* 0x000fe200078e0a10 */
/*0650*/ ISETP.GT.U32.AND P4, PT, R8, R20, PT ; /* 0x000000140800720c */
/* 0x000fe20003f84070 */
/*0660*/ @!P1 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e9224 */
/* 0x000fe200078e0a0e */
/*0670*/ ISETP.GE.U32.AND P0, PT, R21, R8, PT ; /* 0x000000081500720c */
/* 0x000fe40003f06070 */
/*0680*/ ISETP.NE.AND P5, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc40003fa5270 */
/*0690*/ LOP3.LUT R21, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff157212 */
/* 0x000fe400078e33ff */
/*06a0*/ @!P3 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202b810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ SEL R25, R21, R18, !P5 ; /* 0x0000001215197207 */
/* 0x000fe20006800000 */
/*06c0*/ @!P2 IMAD.IADD R29, R29, 0x1, -R8.reuse ; /* 0x000000011d1da824 */
/* 0x100fe200078e0a08 */
/*06d0*/ ISETP.GE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f26270 */
/*06e0*/ @!P4 IMAD.IADD R20, R20, 0x1, -R8 ; /* 0x000000011414c824 */
/* 0x000fe200078e0a08 */
/*06f0*/ @!P4 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0ac810 */
/* 0x000fe20007ffe0ff */
/*0700*/ IMAD.MOV R18, RZ, RZ, -R25 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0a19 */
/*0710*/ ISETP.GE.U32.AND P4, PT, R29, R8, PT ; /* 0x000000081d00720c */
/* 0x000fc40003f86070 */
/*0720*/ SEL R29, R21, R6, !P5 ; /* 0x00000006151d7207 */
/* 0x000fe20006800000 */
/*0730*/ IMAD R18, R0, R18, R13 ; /* 0x0000001200127224 */
/* 0x000fe200078e020d */
/*0740*/ LOP3.LUT R15, R23, R0, RZ, 0x3c, !PT ; /* 0x00000000170f7212 */
/* 0x000fe200078e3cff */
/*0750*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002600 */
/*0760*/ SEL R13, R21, R16, !P5 ; /* 0x00000010150d7207 */
/* 0x000fe20006800000 */
/*0770*/ IMAD.MOV R16, RZ, RZ, -R29 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0a1d */
/*0780*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0790*/ ISETP.GE.U32.AND P0, PT, R20, R8, PT ; /* 0x000000081400720c */
/* 0x000fe20003f06070 */
/*07a0*/ IMAD R16, R0, R16, R7 ; /* 0x0000001000107224 */
/* 0x000fe200078e0207 */
/*07b0*/ ISETP.GE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f66270 */
/*07c0*/ IMAD.MOV.U32 R20, RZ, RZ, R2 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0002 */
/*07d0*/ SEL R15, R21, R11, !P5 ; /* 0x0000000b150f7207 */
/* 0x000fc40006800000 */
/*07e0*/ SEL R11, R21.reuse, R14, !P5 ; /* 0x0000000e150b7207 */
/* 0x040fe20006800000 */
/*07f0*/ @!P6 IMAD.MOV R20, RZ, RZ, -R20 ; /* 0x000000ffff14e224 */
/* 0x000fe200078e0a14 */
/*0800*/ IADD3 R16, R16, UR5, RZ ; /* 0x0000000510107c10 */
/* 0x000fe2000fffe0ff */
/*0810*/ IMAD.MOV R14, RZ, RZ, -R15 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0f */
/*0820*/ @!P2 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0ca810 */
/* 0x000fe20007ffe0ff */
/*0830*/ IMAD.MOV R8, RZ, RZ, -R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a0b */
/*0840*/ IADD3 R2, R18, UR5, RZ ; /* 0x0000000512027c10 */
/* 0x000fe2000fffe0ff */
/*0850*/ IMAD R3, R0, R14, R3 ; /* 0x0000000e00037224 */
/* 0x000fe200078e0203 */
/*0860*/ ISETP.GE.AND P2, PT, R16, c[0x0][0x178], PT ; /* 0x00005e0010007a0c */
/* 0x000fe20003f46270 */
/*0870*/ IMAD.MOV R14, RZ, RZ, -R13 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0d */
/*0880*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fe20007ffe0ff */
/*0890*/ IMAD R8, R0, R8, R19 ; /* 0x0000000800087224 */
/* 0x000fe200078e0213 */
/*08a0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fe20003f06270 */
/*08b0*/ IMAD R14, R0, R14, R17 ; /* 0x0000000e000e7224 */
/* 0x000fe200078e0211 */
/*08c0*/ SEL R17, R21, R20, !P5 ; /* 0x0000001415117207 */
/* 0x000fe20006800000 */
/*08d0*/ @!P1 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0a0a */
/*08e0*/ @P4 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c4810 */
/* 0x000fc40007ffe0ff */
/*08f0*/ IADD3 R20, R3, UR5, RZ ; /* 0x0000000503147c10 */
/* 0x000fe2000fffe0ff */
/*0900*/ IMAD.MOV R18, RZ, RZ, -R17 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0a11 */
/*0910*/ SEL R19, R21.reuse, R10, !P5 ; /* 0x0000000a15137207 */
/* 0x040fe20006800000 */
/*0920*/ @!P2 IMAD R29, R6, c[0x0][0x4], R29 ; /* 0x00000100061daa24 */
/* 0x001fe200078e021d */
/*0930*/ ISETP.GE.AND P4, PT, R20, c[0x0][0x178], PT ; /* 0x00005e0014007a0c */
/* 0x000fe20003f86270 */
/*0940*/ @!P3 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0cb224 */
/* 0x000fe200078e0a0c */
/*0950*/ IADD3 R22, R8, UR5, RZ ; /* 0x0000000508167c10 */
/* 0x000fe2000fffe0ff */
/*0960*/ IMAD R27, R0, R18, R27 ; /* 0x00000012001b7224 */
/* 0x000fe200078e021b */
/*0970*/ IADD3 R14, R14, UR5, RZ ; /* 0x000000050e0e7c10 */
/* 0x000fe2000fffe0ff */
/*0980*/ IMAD.MOV R18, RZ, RZ, -R19 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0a13 */
/*0990*/ SEL R21, R21, R12, !P5 ; /* 0x0000000c15157207 */
/* 0x000fe20006800000 */
/*09a0*/ @!P0 IMAD R25, R6, c[0x0][0x4], R25 ; /* 0x0000010006198a24 */
/* 0x000fe200078e0219 */
/*09b0*/ ISETP.GE.AND P3, PT, R22, c[0x0][0x178], PT ; /* 0x00005e0016007a0c */
/* 0x000fe20003f66270 */
/*09c0*/ @!P2 IMAD R10, R29, c[0x0][0x178], R16 ; /* 0x00005e001d0aaa24 */
/* 0x000fc400078e0210 */
/*09d0*/ IMAD R18, R0, R18, R9 ; /* 0x0000001200127224 */
/* 0x000fe400078e0209 */
/*09e0*/ @!P0 IMAD R9, R25, c[0x0][0x178], R2 ; /* 0x00005e0019098a24 */
/* 0x000fe200078e0202 */
/*09f0*/ @!P2 IADD3 R2, P1, R10, c[0x0][0x168], RZ ; /* 0x00005a000a02aa10 */
/* 0x000fe20007f3e0ff */
/*0a00*/ IMAD.MOV R12, RZ, RZ, -R21 ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e0a15 */
/*0a10*/ @!P2 LEA.HI.X.SX32 R3, R10, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b000a03aa11 */
/* 0x000fe200008f0eff */
/*0a20*/ IMAD R16, R0, R12, R23 ; /* 0x0000000c00107224 */
/* 0x000fe200078e0217 */
/*0a30*/ ISETP.GE.AND P1, PT, R14, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x000fe20003f26270 */
/*0a40*/ @!P4 IMAD R15, R6, c[0x0][0x4], R15 ; /* 0x00000100060fca24 */
/* 0x000fe200078e020f */
/*0a50*/ @!P0 IADD3 R8, P6, R9, c[0x0][0x168], RZ ; /* 0x00005a0009088a10 */
/* 0x000fe40007fde0ff */
/*0a60*/ PRMT R10, RZ, 0x7610, R10 ; /* 0x00007610ff0a7816 */
/* 0x000fe4000000000a */
/*0a70*/ PRMT R12, RZ, 0x7610, R12 ; /* 0x00007610ff0c7816 */
/* 0x000fe2000000000c */
/*0a80*/ @!P4 IMAD R15, R15, c[0x0][0x178], R20 ; /* 0x00005e000f0fca24 */
/* 0x000fe200078e0214 */
/*0a90*/ IADD3 R27, R27, UR5, RZ ; /* 0x000000051b1b7c10 */
/* 0x000fc4000fffe0ff */
/*0aa0*/ IADD3 R18, R18, UR5, RZ ; /* 0x0000000512127c10 */
/* 0x000fe2000fffe0ff */
/*0ab0*/ @!P3 IMAD R11, R6, c[0x0][0x4], R11 ; /* 0x00000100060bba24 */
/* 0x000fe200078e020b */
/*0ac0*/ IADD3 R16, R16, UR5, RZ ; /* 0x0000000510107c10 */
/* 0x000fe2000fffe0ff */
/*0ad0*/ @!P2 LDG.E.U8 R10, [R2.64] ; /* 0x00000006020aa981 */
/* 0x0000a2000c1e1100 */
/*0ae0*/ @!P0 LEA.HI.X.SX32 R9, R9, c[0x0][0x16c], 0x1, P6 ; /* 0x00005b0009098a11 */
/* 0x000fe200030f0eff */
/*0af0*/ @!P1 IMAD R13, R6, c[0x0][0x4], R13 ; /* 0x00000100060d9a24 */
/* 0x000fe200078e020d */
/*0b00*/ ISETP.GE.AND P2, PT, R27, c[0x0][0x178], PT ; /* 0x00005e001b007a0c */
/* 0x000fe20003f46270 */
/*0b10*/ @!P3 IMAD R22, R11, c[0x0][0x178], R22 ; /* 0x00005e000b16ba24 */
/* 0x000fe200078e0216 */
/*0b20*/ ISETP.GE.AND P5, PT, R18, c[0x0][0x178], PT ; /* 0x00005e0012007a0c */
/* 0x000fe20003fa6270 */
/*0b30*/ @!P0 LDG.E.U8 R12, [R8.64] ; /* 0x00000006080c8981 */
/* 0x0002e2000c1e1100 */
/*0b40*/ ISETP.GE.AND P6, PT, R16, c[0x0][0x178], PT ; /* 0x00005e0010007a0c */
/* 0x000fe20003fc6270 */
/*0b50*/ @!P1 IMAD R11, R13, c[0x0][0x178], R14 ; /* 0x00005e000d0b9a24 */
/* 0x000fe200078e020e */
/*0b60*/ @!P4 IADD3 R2, P0, R15, c[0x0][0x168], RZ ; /* 0x00005a000f02ca10 */
/* 0x001fc80007f1e0ff */
/*0b70*/ @!P4 LEA.HI.X.SX32 R3, R15, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b000f03ca11 */
/* 0x000fe400000f0eff */
/*0b80*/ @!P3 IADD3 R14, P0, R22, c[0x0][0x168], RZ ; /* 0x00005a00160eba10 */
/* 0x000fe20007f1e0ff */
/*0b90*/ @!P2 IMAD R20, R6, c[0x0][0x4], R17 ; /* 0x000001000614aa24 */
/* 0x000fc600078e0211 */
/*0ba0*/ @!P3 LEA.HI.X.SX32 R15, R22, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b00160fba11 */
/* 0x000fe200000f0eff */
/*0bb0*/ @!P5 IMAD R19, R6.reuse, c[0x0][0x4], R19 ; /* 0x000001000613da24 */
/* 0x040fe200078e0213 */
/*0bc0*/ @!P1 IADD3 R8, P0, R11.reuse, c[0x0][0x168], RZ ; /* 0x00005a000b089a10 */
/* 0x042fe20007f1e0ff */
/*0bd0*/ @!P6 IMAD R13, R6, c[0x0][0x4], R21 ; /* 0x00000100060dea24 */
/* 0x000fe200078e0215 */
/*0be0*/ PRMT R24, RZ, 0x7610, R24 ; /* 0x00007610ff187816 */
/* 0x000fe40000000018 */
/*0bf0*/ PRMT R22, RZ, 0x7610, R22 ; /* 0x00007610ff167816 */
/* 0x000fe20000000016 */
/*0c00*/ @!P2 IMAD R27, R20, c[0x0][0x178], R27 ; /* 0x00005e00141baa24 */
/* 0x000fe200078e021b */
/*0c10*/ @!P1 LEA.HI.X.SX32 R9, R11, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b000b099a11 */
/* 0x000fe200000f0eff */
/*0c20*/ @!P5 IMAD R19, R19, c[0x0][0x178], R18 ; /* 0x00005e001313da24 */
/* 0x000fe200078e0212 */
/*0c30*/ @!P3 LDG.E.U8 R24, [R14.64] ; /* 0x000000060e18b981 */
/* 0x000f22000c1e1100 */
/*0c40*/ @!P6 IMAD R13, R13, c[0x0][0x178], R16 ; /* 0x00005e000d0dea24 */
/* 0x000fe200078e0210 */
/*0c50*/ @!P2 IADD3 R16, P0, R27, c[0x0][0x168], RZ ; /* 0x00005a001b10aa10 */
/* 0x000fc40007f1e0ff */
/*0c60*/ @!P1 LDG.E.U8 R22, [R8.64] ; /* 0x0000000608169981 */
/* 0x000f62000c1e1100 */
/*0c70*/ @!P5 IADD3 R18, P1, R19, c[0x0][0x168], RZ ; /* 0x00005a001312da10 */
/* 0x000fe40007f3e0ff */
/*0c80*/ @!P6 IADD3 R20, P3, R13, c[0x0][0x168], RZ ; /* 0x00005a000d14ea10 */
/* 0x000fe40007f7e0ff */
/*0c90*/ PRMT R26, RZ, 0x7610, R26 ; /* 0x00007610ff1a7816 */
/* 0x000fe4000000001a */
/*0ca0*/ PRMT R28, RZ, 0x7610, R28 ; /* 0x00007610ff1c7816 */
/* 0x000fe4000000001c */
/*0cb0*/ PRMT R23, RZ, 0x7610, R23 ; /* 0x00007610ff177816 */
/* 0x000fe40000000017 */
/*0cc0*/ PRMT R11, RZ, 0x7610, R11 ; /* 0x00007610ff0b7816 */
/* 0x000fe2000000000b */
/*0cd0*/ @!P4 LDG.E.U8 R26, [R2.64] ; /* 0x00000006021ac981 */
/* 0x000162000c1e1100 */
/*0ce0*/ @!P2 LEA.HI.X.SX32 R17, R27, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b001b11aa11 */
/* 0x000fc400000f0eff */
/*0cf0*/ @!P5 LEA.HI.X.SX32 R19, R19, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b001313da11 */
/* 0x000fe400008f0eff */
/*0d00*/ @!P6 LEA.HI.X.SX32 R21, R13, c[0x0][0x16c], 0x1, P3 ; /* 0x00005b000d15ea11 */
/* 0x000fe200018f0eff */
/*0d10*/ @!P2 LDG.E.U8 R28, [R16.64] ; /* 0x00000006101ca981 */
/* 0x000f68000c1e1100 */
/*0d20*/ @!P5 LDG.E.U8 R23, [R18.64] ; /* 0x000000061217d981 */
/* 0x000f68000c1e1100 */
/*0d30*/ @!P6 LDG.E.U8 R11, [R20.64] ; /* 0x00000006140be981 */
/* 0x000f62000c1e1100 */
/*0d40*/ IADD3 R2, R4, UR4, RZ ; /* 0x0000000404027c10 */
/* 0x001fe2000fffe0ff */
/*0d50*/ IMAD R3, R6, c[0x0][0x4], R5 ; /* 0x0000010006037a24 */
/* 0x000fc600078e0205 */
/*0d60*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fc80003f06270 */
/*0d70*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fe20000706670 */
/*0d80*/ STS.U8 [R7], R10 ; /* 0x0000000a07007388 */
/* 0x0041e80000000000 */
/*0d90*/ STS.U8 [R7+0x100], R12 ; /* 0x0001000c07007388 */
/* 0x0081e80000000000 */
/*0da0*/ STS.U8 [R7+0x300], R24 ; /* 0x0003001807007388 */
/* 0x0101e80000000000 */
/*0db0*/ STS.U8 [R7+0x400], R22 ; /* 0x0004001607007388 */
/* 0x0201e80000000000 */
/*0dc0*/ STS.U8 [R7+0x200], R26 ; /* 0x0002001a07007388 */
/* 0x0001e80000000000 */
/*0dd0*/ STS.U8 [R7+0x500], R28 ; /* 0x0005001c07007388 */
/* 0x0001e80000000000 */
/*0de0*/ STS.U8 [R7+0x600], R23 ; /* 0x0006001707007388 */
/* 0x0001e80000000000 */
/*0df0*/ STS.U8 [R7+0x700], R11 ; /* 0x0007000b07007388 */
/* 0x0001e80000000000 */
/*0e00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0e10*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0e20*/ IMAD.SHL.U32 R4, R4, 0x8, RZ ; /* 0x0000000804047824 */
/* 0x001fe400078e00ff */
/*0e30*/ IMAD R2, R3, c[0x0][0x174], R2 ; /* 0x00005d0003027a24 */
/* 0x000fc600078e0202 */
/*0e40*/ LOP3.LUT R4, R4, 0x1ffffff8, RZ, 0xc0, !PT ; /* 0x1ffffff804047812 */
/* 0x000fca00078ec0ff */
/*0e50*/ IMAD R0, R0, R5, R4 ; /* 0x0000000500007224 */
/* 0x000fca00078e0204 */
/*0e60*/ LDS.U8 R4, [R0+0x1] ; /* 0x0000010000047984 */
/* 0x000e280000000000 */
/*0e70*/ LDS.U8 R5, [R0+0x2] ; /* 0x0000020000057984 */
/* 0x000e680000000000 */
/*0e80*/ LDS.U8 R6, [R0+0x3] ; /* 0x0000030000067984 */
/* 0x000ea80000000000 */
/*0e90*/ LDS.U8 R10, [R0+0x5] ; /* 0x00000500000a7984 */
/* 0x000ee80000000000 */
/*0ea0*/ LDS.U8 R8, [R0] ; /* 0x0000000000087984 */
/* 0x000f280000000000 */
/*0eb0*/ LDS.U8 R11, [R0+0x6] ; /* 0x00000600000b7984 */
/* 0x000f680000000000 */
/*0ec0*/ LDS.U8 R12, [R0+0x7] ; /* 0x00000700000c7984 */
/* 0x000f680000000000 */
/*0ed0*/ LDS.U8 R9, [R0+0x4] ; /* 0x0000040000097984 */
/* 0x000f620000000000 */
/*0ee0*/ LOP3.LUT R13, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040d7812 */
/* 0x001fe200078ec0ff */
/*0ef0*/ IMAD.WIDE.U32 R4, R5, 0x10000, RZ ; /* 0x0001000005047825 */
/* 0x002fc600078e00ff */
/*0f00*/ SHF.L.U64.HI R15, R13, 0x8, RZ ; /* 0x000000080d0f7819 */
/* 0x000fe200000102ff */
/*0f10*/ IMAD.WIDE.U32 R6, R6, 0x1000000, RZ ; /* 0x0100000006067825 */
/* 0x004fc800078e00ff */
/*0f20*/ IMAD.SHL.U32 R13, R13, 0x100, RZ ; /* 0x000001000d0d7824 */
/* 0x000fe200078e00ff */
/*0f30*/ LOP3.LUT R5, R7, R5, R15, 0xfe, !PT ; /* 0x0000000507057212 */
/* 0x000fe200078efe0f */
/*0f40*/ IMAD.SHL.U32 R10, R10, 0x100, RZ ; /* 0x000001000a0a7824 */
/* 0x008fc600078e00ff */
/*0f50*/ LOP3.LUT R7, R13, 0xffff00ff, R8, 0xf8, !PT ; /* 0xffff00ff0d077812 */
/* 0x010fe200078ef808 */
/*0f60*/ IMAD.MOV.U32 R13, RZ, RZ, 0x8 ; /* 0x00000008ff0d7424 */
/* 0x000fe400078e00ff */
/*0f70*/ IMAD.U32 R11, R11, 0x10000, RZ ; /* 0x000100000b0b7824 */
/* 0x020fe200078e00ff */
/*0f80*/ LOP3.LUT R4, R6, R4, R7, 0xfe, !PT ; /* 0x0000000406047212 */
/* 0x000fe200078efe07 */
/*0f90*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e020d */
/*0fa0*/ IMAD.SHL.U32 R12, R12, 0x1000000, RZ ; /* 0x010000000c0c7824 */
/* 0x000fe200078e00ff */
/*0fb0*/ LOP3.LUT R9, R10, R9, R5, 0xfe, !PT ; /* 0x000000090a097212 */
/* 0x000fc800078efe05 */
/*0fc0*/ LOP3.LUT R5, R12, R11, R9, 0xfe, !PT ; /* 0x0000000b0c057212 */
/* 0x000fca00078efe09 */
/*0fd0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b06 */
/*0fe0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ff0*/ BRA 0xff0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define ELEMENT_SIZE 64
#define BLOCK_SIZE 16
extern "C"
__global__ void int8pack_kernel(long *ret, const unsigned char *input, const int ret0, const int ret1, const int input1) {
const int y = blockIdx.x * blockDim.x + threadIdx.x;
const int x = blockIdx.y * blockDim.y + threadIdx.y;
const int tid = threadIdx.y * blockDim.x + threadIdx.x;
const int cache1 = ELEMENT_SIZE / 8 * blockDim.x;
const int square_size = BLOCK_SIZE * BLOCK_SIZE;
const int offset_y = blockIdx.x * blockDim.x * ELEMENT_SIZE / 8;
const int offset = blockIdx.y * blockDim.y * input1 + offset_y;
__shared__ unsigned char cache[BLOCK_SIZE * BLOCK_SIZE * ELEMENT_SIZE / 8];
for (int i = 0; i < ELEMENT_SIZE / 8; i++){
const int idx = i * square_size + tid;
const int x_sub = idx / cache1;
const int y_sub = idx - x_sub * cache1;
cache[x_sub * cache1 + y_sub] = y_sub + offset_y < input1 ? input[x_sub * input1 + y_sub + offset] : 0;
}
__syncthreads();
const int y_input = threadIdx.x * ELEMENT_SIZE / 8;
if (x < ret0 && y < ret1) {
long tmp = 0;
#pragma unroll
for (int i = 0; i < ELEMENT_SIZE / 8; i++) {
tmp |= ((long) cache[threadIdx.y * cache1 + y_input + i] ) << (8 * i);
}
ret[x * ret1 + y] = tmp;
}
} | .file "tmpxft_000697cb_00000000-6_int8pack.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii
.type _Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii, @function
_Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq int8pack_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii, .-_Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii
.globl int8pack_kernel
.type int8pack_kernel, @function
int8pack_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size int8pack_kernel, .-int8pack_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "int8pack_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq int8pack_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define ELEMENT_SIZE 64
#define BLOCK_SIZE 16
extern "C"
__global__ void int8pack_kernel(long *ret, const unsigned char *input, const int ret0, const int ret1, const int input1) {
const int y = blockIdx.x * blockDim.x + threadIdx.x;
const int x = blockIdx.y * blockDim.y + threadIdx.y;
const int tid = threadIdx.y * blockDim.x + threadIdx.x;
const int cache1 = ELEMENT_SIZE / 8 * blockDim.x;
const int square_size = BLOCK_SIZE * BLOCK_SIZE;
const int offset_y = blockIdx.x * blockDim.x * ELEMENT_SIZE / 8;
const int offset = blockIdx.y * blockDim.y * input1 + offset_y;
__shared__ unsigned char cache[BLOCK_SIZE * BLOCK_SIZE * ELEMENT_SIZE / 8];
for (int i = 0; i < ELEMENT_SIZE / 8; i++){
const int idx = i * square_size + tid;
const int x_sub = idx / cache1;
const int y_sub = idx - x_sub * cache1;
cache[x_sub * cache1 + y_sub] = y_sub + offset_y < input1 ? input[x_sub * input1 + y_sub + offset] : 0;
}
__syncthreads();
const int y_input = threadIdx.x * ELEMENT_SIZE / 8;
if (x < ret0 && y < ret1) {
long tmp = 0;
#pragma unroll
for (int i = 0; i < ELEMENT_SIZE / 8; i++) {
tmp |= ((long) cache[threadIdx.y * cache1 + y_input + i] ) << (8 * i);
}
ret[x * ret1 + y] = tmp;
}
} | #include <hip/hip_runtime.h>
#define ELEMENT_SIZE 64
#define BLOCK_SIZE 16
extern "C"
__global__ void int8pack_kernel(long *ret, const unsigned char *input, const int ret0, const int ret1, const int input1) {
const int y = blockIdx.x * blockDim.x + threadIdx.x;
const int x = blockIdx.y * blockDim.y + threadIdx.y;
const int tid = threadIdx.y * blockDim.x + threadIdx.x;
const int cache1 = ELEMENT_SIZE / 8 * blockDim.x;
const int square_size = BLOCK_SIZE * BLOCK_SIZE;
const int offset_y = blockIdx.x * blockDim.x * ELEMENT_SIZE / 8;
const int offset = blockIdx.y * blockDim.y * input1 + offset_y;
__shared__ unsigned char cache[BLOCK_SIZE * BLOCK_SIZE * ELEMENT_SIZE / 8];
for (int i = 0; i < ELEMENT_SIZE / 8; i++){
const int idx = i * square_size + tid;
const int x_sub = idx / cache1;
const int y_sub = idx - x_sub * cache1;
cache[x_sub * cache1 + y_sub] = y_sub + offset_y < input1 ? input[x_sub * input1 + y_sub + offset] : 0;
}
__syncthreads();
const int y_input = threadIdx.x * ELEMENT_SIZE / 8;
if (x < ret0 && y < ret1) {
long tmp = 0;
#pragma unroll
for (int i = 0; i < ELEMENT_SIZE / 8; i++) {
tmp |= ((long) cache[threadIdx.y * cache1 + y_input + i] ) << (8 * i);
}
ret[x * ret1 + y] = tmp;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define ELEMENT_SIZE 64
#define BLOCK_SIZE 16
extern "C"
__global__ void int8pack_kernel(long *ret, const unsigned char *input, const int ret0, const int ret1, const int input1) {
const int y = blockIdx.x * blockDim.x + threadIdx.x;
const int x = blockIdx.y * blockDim.y + threadIdx.y;
const int tid = threadIdx.y * blockDim.x + threadIdx.x;
const int cache1 = ELEMENT_SIZE / 8 * blockDim.x;
const int square_size = BLOCK_SIZE * BLOCK_SIZE;
const int offset_y = blockIdx.x * blockDim.x * ELEMENT_SIZE / 8;
const int offset = blockIdx.y * blockDim.y * input1 + offset_y;
__shared__ unsigned char cache[BLOCK_SIZE * BLOCK_SIZE * ELEMENT_SIZE / 8];
for (int i = 0; i < ELEMENT_SIZE / 8; i++){
const int idx = i * square_size + tid;
const int x_sub = idx / cache1;
const int y_sub = idx - x_sub * cache1;
cache[x_sub * cache1 + y_sub] = y_sub + offset_y < input1 ? input[x_sub * input1 + y_sub + offset] : 0;
}
__syncthreads();
const int y_input = threadIdx.x * ELEMENT_SIZE / 8;
if (x < ret0 && y < ret1) {
long tmp = 0;
#pragma unroll
for (int i = 0; i < ELEMENT_SIZE / 8; i++) {
tmp |= ((long) cache[threadIdx.y * cache1 + y_input + i] ) << (8 * i);
}
ret[x * ret1 + y] = tmp;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected int8pack_kernel
.globl int8pack_kernel
.p2align 8
.type int8pack_kernel,@function
int8pack_kernel:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s7, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s8, 0xffff
s_lshr_b32 s8, s8, 16
s_lshl_b32 s4, s5, 3
s_mul_i32 s14, s14, s5
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s6, 0, s4
s_lshl_b32 s9, s14, 3
s_mul_i32 s15, s15, s8
s_and_b32 s8, s9, 0x1ffffff8
v_rcp_iflag_f32_e32 v1, v1
s_mov_b32 s9, 8
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mul_lo_u32 v1, s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v1
v_bfe_u32 v1, v0, 10, 10
v_mad_u32_u24 v0, v1, s5, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v3, v3, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt vmcnt(0)
ds_store_b8 v0, v5
v_add_nc_u32_e32 v0, 0x100, v0
s_add_i32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 0
s_cbranch_scc1 .LBB0_4
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v0, v3
v_not_b32_e32 v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, v4, s5
v_mad_u64_u32 v[4:5], null, s6, v6, v[0:1]
v_lshl_add_u32 v7, v7, 3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_dual_cndmask_b32 v4, v4, v7 :: v_dual_add_nc_u32 v5, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v6, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, 1, v5
v_cndmask_b32_e32 v4, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s6, v4
v_add3_u32 v5, s8, v0, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s7, v5
v_mov_b32_e32 v5, 0
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v5, s15, v4
v_mul_lo_u32 v4, v4, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s7
v_sub_nc_u32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, s8, v0, v4
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_u8 v5, v[4:5], off
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[2:3], s[0:1], 0x10
v_add_nc_u32_e32 v3, s15, v1
v_add_nc_u32_e32 v0, s14, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, s2, v3
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v2, 3, v2
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v3, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u32_u24 v0, s4, v1, v2
v_ashrrev_i32_e32 v5, 31, v4
ds_load_b64 v[0:1], v0
v_lshlrev_b64 v[2:3], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel int8pack_kernel
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size int8pack_kernel, .Lfunc_end0-int8pack_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: int8pack_kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: int8pack_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define ELEMENT_SIZE 64
#define BLOCK_SIZE 16
extern "C"
__global__ void int8pack_kernel(long *ret, const unsigned char *input, const int ret0, const int ret1, const int input1) {
const int y = blockIdx.x * blockDim.x + threadIdx.x;
const int x = blockIdx.y * blockDim.y + threadIdx.y;
const int tid = threadIdx.y * blockDim.x + threadIdx.x;
const int cache1 = ELEMENT_SIZE / 8 * blockDim.x;
const int square_size = BLOCK_SIZE * BLOCK_SIZE;
const int offset_y = blockIdx.x * blockDim.x * ELEMENT_SIZE / 8;
const int offset = blockIdx.y * blockDim.y * input1 + offset_y;
__shared__ unsigned char cache[BLOCK_SIZE * BLOCK_SIZE * ELEMENT_SIZE / 8];
for (int i = 0; i < ELEMENT_SIZE / 8; i++){
const int idx = i * square_size + tid;
const int x_sub = idx / cache1;
const int y_sub = idx - x_sub * cache1;
cache[x_sub * cache1 + y_sub] = y_sub + offset_y < input1 ? input[x_sub * input1 + y_sub + offset] : 0;
}
__syncthreads();
const int y_input = threadIdx.x * ELEMENT_SIZE / 8;
if (x < ret0 && y < ret1) {
long tmp = 0;
#pragma unroll
for (int i = 0; i < ELEMENT_SIZE / 8; i++) {
tmp |= ((long) cache[threadIdx.y * cache1 + y_input + i] ) << (8 * i);
}
ret[x * ret1 + y] = tmp;
}
} | .text
.file "int8pack.hip"
.globl __device_stub__int8pack_kernel # -- Begin function __device_stub__int8pack_kernel
.p2align 4, 0x90
.type __device_stub__int8pack_kernel,@function
__device_stub__int8pack_kernel: # @__device_stub__int8pack_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $int8pack_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__int8pack_kernel, .Lfunc_end0-__device_stub__int8pack_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $int8pack_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type int8pack_kernel,@object # @int8pack_kernel
.section .rodata,"a",@progbits
.globl int8pack_kernel
.p2align 3, 0x0
int8pack_kernel:
.quad __device_stub__int8pack_kernel
.size int8pack_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "int8pack_kernel"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__int8pack_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym int8pack_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : int8pack_kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0030*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0040*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0050*/ IMAD.SHL.U32 R0, R0, 0x8, RZ ; /* 0x0000000800007824 */
/* 0x000fe200078e00ff */
/*0060*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0070*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IABS R8, R0.reuse ; /* 0x0000000000087213 */
/* 0x080fe40000000000 */
/*00a0*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fc40000000000 */
/*00b0*/ I2F.RP R2, R8 ; /* 0x0000000800027306 */
/* 0x000ea60000209400 */
/*00c0*/ IMAD.MOV R15, RZ, RZ, -R10 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0a0a */
/*00d0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x002fc8000f8e023f */
/*00e0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x004e620000001000 */
/*00f0*/ IMAD R7, R5, c[0x0][0x0], R4 ; /* 0x0000000005077a24 */
/* 0x001fe200078e0204 */
/*0100*/ USHF.L.U32 UR5, UR4, 0x3, URZ ; /* 0x0000000304057899 */
/* 0x000fc8000800063f */
/*0110*/ IABS R6, R7 ; /* 0x0000000700067213 */
/* 0x000fe20000000000 */
/*0120*/ ULOP3.LUT UR5, UR5, 0x1ffffff8, URZ, 0xc0, !UPT ; /* 0x1ffffff805057892 */
/* 0x000fe2000f8ec03f */
/*0130*/ IADD3 R19, R7.reuse, 0x300, RZ ; /* 0x0000030007137810 */
/* 0x040fe40007ffe0ff */
/*0140*/ IADD3 R17, R7, 0x400, RZ ; /* 0x0000040007117810 */
/* 0x000fe40007ffe0ff */
/*0150*/ IABS R25, R19 ; /* 0x0000001300197213 */
/* 0x000fe40000000000 */
/*0160*/ IABS R29, R17 ; /* 0x00000011001d7213 */
/* 0x000fe40000000000 */
/*0170*/ IADD3 R3, R2, 0xffffffe, RZ ; /* 0x0ffffffe02037810 */
/* 0x002fc40007ffe0ff */
/*0180*/ LOP3.LUT R10, R7.reuse, R0.reuse, RZ, 0x3c, !PT ; /* 0x00000000070a7212 */
/* 0x0c0fe400078e3cff */
/*0190*/ F2I.FTZ.U32.TRUNC.NTZ R13, R3 ; /* 0x00000003000d7305 */
/* 0x000062000021f000 */
/*01a0*/ IADD3 R27, R7, 0x500, RZ ; /* 0x00000500071b7810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f26270 */
/*01c0*/ LOP3.LUT R20, R17, R0.reuse, RZ, 0x3c, !PT ; /* 0x0000000011147212 */
/* 0x080fe400078e3cff */
/*01d0*/ LOP3.LUT R22, R27, R0, RZ, 0x3c, !PT ; /* 0x000000001b167212 */
/* 0x000fe400078e3cff */
/*01e0*/ IADD3 R3, R7, 0x200, RZ ; /* 0x0000020007037810 */
/* 0x001fc80007ffe0ff */
/*01f0*/ IABS R2, R3 ; /* 0x0000000300027213 */
/* 0x000fe20000000000 */
/*0200*/ IMAD.MOV R9, RZ, RZ, -R13 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a0d */
/*0210*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*0220*/ IMAD.HI.U32 R12, R13, R9, R12 ; /* 0x000000090d0c7227 */
/* 0x000fe200078e000c */
/*0230*/ IADD3 R13, R7, 0x100, RZ ; /* 0x00000100070d7810 */
/* 0x000fc60007ffe0ff */
/*0240*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0006 */
/*0250*/ IABS R21, R13 ; /* 0x0000000d00157213 */
/* 0x000fe20000000000 */
/*0260*/ IMAD.HI.U32 R11, R12, R2, RZ ; /* 0x000000020c0b7227 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD.HI.U32 R6, R12, R9, RZ ; /* 0x000000090c067227 */
/* 0x000fc800078e00ff */
/*0280*/ IMAD.HI.U32 R18, R12, R21, RZ ; /* 0x000000150c127227 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD R9, R6, R15.reuse, R9 ; /* 0x0000000f06097224 */
/* 0x080fe400078e0209 */
/*02a0*/ IMAD R21, R18, R15.reuse, R21 ; /* 0x0000000f12157224 */
/* 0x080fe400078e0215 */
/*02b0*/ IMAD R23, R11, R15, R2 ; /* 0x0000000f0b177224 */
/* 0x000fe200078e0202 */
/*02c0*/ ISETP.GT.U32.AND P5, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe20003fa4070 */
/*02d0*/ IMAD.HI.U32 R14, R12, R25, RZ ; /* 0x000000190c0e7227 */
/* 0x000fe200078e00ff */
/*02e0*/ ISETP.GT.U32.AND P4, PT, R8.reuse, R21, PT ; /* 0x000000150800720c */
/* 0x040fe40003f84070 */
/*02f0*/ ISETP.GT.U32.AND P3, PT, R8, R23, PT ; /* 0x000000170800720c */
/* 0x000fe20003f64070 */
/*0300*/ IMAD.HI.U32 R16, R12, R29, RZ ; /* 0x0000001d0c107227 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R2, R13, R0, RZ, 0x3c, !PT ; /* 0x000000000d027212 */
/* 0x000fc800078e3cff */
/*0320*/ ISETP.GE.AND P6, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003fc6270 */
/*0330*/ LOP3.LUT R2, R3, R0, RZ, 0x3c, !PT ; /* 0x0000000003027212 */
/* 0x000fe200078e3cff */
/*0340*/ @!P5 IMAD.IADD R9, R9, 0x1, -R8.reuse ; /* 0x000000010909d824 */
/* 0x100fe200078e0a08 */
/*0350*/ @!P5 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606d810 */
/* 0x000fe20007ffe0ff */
/*0360*/ @!P4 IMAD.IADD R21, R21, 0x1, -R8.reuse ; /* 0x000000011515c824 */
/* 0x100fe200078e0a08 */
/*0370*/ @!P4 IADD3 R18, R18, 0x1, RZ ; /* 0x000000011212c810 */
/* 0x000fe20007ffe0ff */
/*0380*/ @!P3 IMAD.IADD R23, R23, 0x1, -R8 ; /* 0x000000011717b824 */
/* 0x000fe200078e0a08 */
/*0390*/ ISETP.GE.U32.AND P2, PT, R9, R8.reuse, PT ; /* 0x000000080900720c */
/* 0x080fe20003f46070 */
/*03a0*/ IMAD R9, R14, R15.reuse, R25 ; /* 0x0000000f0e097224 */
/* 0x080fe200078e0219 */
/*03b0*/ ISETP.GE.U32.AND P0, PT, R21, R8.reuse, PT ; /* 0x000000081500720c */
/* 0x080fe20003f06070 */
/*03c0*/ IMAD R25, R16, R15, R29 ; /* 0x0000000f10197224 */
/* 0x000fe200078e021d */
/*03d0*/ ISETP.GE.U32.AND P4, PT, R23, R8, PT ; /* 0x000000081700720c */
/* 0x000fc40003f86070 */
/*03e0*/ ISETP.GT.U32.AND P5, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003fa4070 */
/*03f0*/ IABS R21, R27 ; /* 0x0000001b00157213 */
/* 0x000fe40000000000 */
/*0400*/ @!P3 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0bb810 */
/* 0x000fe40007ffe0ff */
/*0410*/ IADD3 R23, R7, 0x700, RZ ; /* 0x0000070007177810 */
/* 0x000fe40007ffe0ff */
/*0420*/ @P2 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106062810 */
/* 0x000fe40007ffe0ff */
/*0430*/ @P0 IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112120810 */
/* 0x000fc40007ffe0ff */
/*0440*/ ISETP.GT.U32.AND P0, PT, R8, R25, PT ; /* 0x000000190800720c */
/* 0x000fe20003f04070 */
/*0450*/ @!P5 IMAD.IADD R9, R9, 0x1, -R8 ; /* 0x000000010909d824 */
/* 0x000fe200078e0a08 */
/*0460*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*0470*/ @!P6 IMAD.MOV R18, RZ, RZ, -R18 ; /* 0x000000ffff12e224 */
/* 0x000fe200078e0a12 */
/*0480*/ LOP3.LUT R2, R19, R0, RZ, 0x3c, !PT ; /* 0x0000000013027212 */
/* 0x000fe200078e3cff */
/*0490*/ @!P1 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0a06 */
/*04a0*/ ISETP.GE.U32.AND P6, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x000fe40003fc6070 */
/*04b0*/ IADD3 R9, R7, 0x600, RZ ; /* 0x0000060007097810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*04d0*/ IMAD.HI.U32 R2, R12, R21, RZ ; /* 0x000000150c027227 */
/* 0x000fe200078e00ff */
/*04e0*/ IABS R10, R9 ; /* 0x00000009000a7213 */
/* 0x000fc40000000000 */
/*04f0*/ @P4 IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b4810 */
/* 0x000fe20007ffe0ff */
/*0500*/ @!P0 IMAD.IADD R25, R25, 0x1, -R8 ; /* 0x0000000119198824 */
/* 0x000fe200078e0a08 */
/*0510*/ IABS R29, R23 ; /* 0x00000017001d7213 */
/* 0x000fe20000000000 */
/*0520*/ IMAD R21, R2, R15, R21 ; /* 0x0000000f02157224 */
/* 0x000fe200078e0215 */
/*0530*/ @!P5 IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0ed810 */
/* 0x000fe20007ffe0ff */
/*0540*/ @!P2 IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0ba224 */
/* 0x000fe200078e0a0b */
/*0550*/ ISETP.GE.U32.AND P4, PT, R25, R8, PT ; /* 0x000000081900720c */
/* 0x000fe20003f86070 */
/*0560*/ IMAD.MOV.U32 R25, RZ, RZ, R10 ; /* 0x000000ffff197224 */
/* 0x000fe200078e000a */
/*0570*/ ISETP.GT.U32.AND P3, PT, R8, R21, PT ; /* 0x000000150800720c */
/* 0x000fe40003f64070 */
/*0580*/ ISETP.GE.AND P5, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003fa6270 */
/*0590*/ IMAD.HI.U32 R10, R12, R25, RZ ; /* 0x000000190c0a7227 */
/* 0x000fe200078e00ff */
/*05a0*/ @!P0 IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110108810 */
/* 0x000fc40007ffe0ff */
/*05b0*/ @P6 IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e6810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ IMAD.HI.U32 R12, R12, R29, RZ ; /* 0x0000001d0c0c7227 */
/* 0x000fe200078e00ff */
/*05d0*/ ISETP.GE.AND P6, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc60003fc6270 */
/*05e0*/ IMAD R29, R12, R15.reuse, R29 ; /* 0x0000000f0c1d7224 */
/* 0x080fe200078e021d */
/*05f0*/ @P4 IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110104810 */
/* 0x000fe20007ffe0ff */
/*0600*/ IMAD R20, R10, R15, R25 ; /* 0x0000000f0a147224 */
/* 0x000fe200078e0219 */
/*0610*/ LOP3.LUT R15, R9, R0, RZ, 0x3c, !PT ; /* 0x00000000090f7212 */
/* 0x000fe200078e3cff */
/*0620*/ @!P3 IMAD.IADD R21, R21, 0x1, -R8 ; /* 0x000000011515b824 */
/* 0x000fe200078e0a08 */
/*0630*/ ISETP.GT.U32.AND P2, PT, R8.reuse, R29, PT ; /* 0x0000001d0800720c */
/* 0x040fe20003f44070 */
/*0640*/ @!P5 IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff10d224 */
/* 0x000fe200078e0a10 */
/*0650*/ ISETP.GT.U32.AND P4, PT, R8, R20, PT ; /* 0x000000140800720c */
/* 0x000fe20003f84070 */
/*0660*/ @!P1 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e9224 */
/* 0x000fe200078e0a0e */
/*0670*/ ISETP.GE.U32.AND P0, PT, R21, R8, PT ; /* 0x000000081500720c */
/* 0x000fe40003f06070 */
/*0680*/ ISETP.NE.AND P5, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc40003fa5270 */
/*0690*/ LOP3.LUT R21, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff157212 */
/* 0x000fe400078e33ff */
/*06a0*/ @!P3 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202b810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ SEL R25, R21, R18, !P5 ; /* 0x0000001215197207 */
/* 0x000fe20006800000 */
/*06c0*/ @!P2 IMAD.IADD R29, R29, 0x1, -R8.reuse ; /* 0x000000011d1da824 */
/* 0x100fe200078e0a08 */
/*06d0*/ ISETP.GE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f26270 */
/*06e0*/ @!P4 IMAD.IADD R20, R20, 0x1, -R8 ; /* 0x000000011414c824 */
/* 0x000fe200078e0a08 */
/*06f0*/ @!P4 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0ac810 */
/* 0x000fe20007ffe0ff */
/*0700*/ IMAD.MOV R18, RZ, RZ, -R25 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0a19 */
/*0710*/ ISETP.GE.U32.AND P4, PT, R29, R8, PT ; /* 0x000000081d00720c */
/* 0x000fc40003f86070 */
/*0720*/ SEL R29, R21, R6, !P5 ; /* 0x00000006151d7207 */
/* 0x000fe20006800000 */
/*0730*/ IMAD R18, R0, R18, R13 ; /* 0x0000001200127224 */
/* 0x000fe200078e020d */
/*0740*/ LOP3.LUT R15, R23, R0, RZ, 0x3c, !PT ; /* 0x00000000170f7212 */
/* 0x000fe200078e3cff */
/*0750*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e220000002600 */
/*0760*/ SEL R13, R21, R16, !P5 ; /* 0x00000010150d7207 */
/* 0x000fe20006800000 */
/*0770*/ IMAD.MOV R16, RZ, RZ, -R29 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0a1d */
/*0780*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0790*/ ISETP.GE.U32.AND P0, PT, R20, R8, PT ; /* 0x000000081400720c */
/* 0x000fe20003f06070 */
/*07a0*/ IMAD R16, R0, R16, R7 ; /* 0x0000001000107224 */
/* 0x000fe200078e0207 */
/*07b0*/ ISETP.GE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f66270 */
/*07c0*/ IMAD.MOV.U32 R20, RZ, RZ, R2 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0002 */
/*07d0*/ SEL R15, R21, R11, !P5 ; /* 0x0000000b150f7207 */
/* 0x000fc40006800000 */
/*07e0*/ SEL R11, R21.reuse, R14, !P5 ; /* 0x0000000e150b7207 */
/* 0x040fe20006800000 */
/*07f0*/ @!P6 IMAD.MOV R20, RZ, RZ, -R20 ; /* 0x000000ffff14e224 */
/* 0x000fe200078e0a14 */
/*0800*/ IADD3 R16, R16, UR5, RZ ; /* 0x0000000510107c10 */
/* 0x000fe2000fffe0ff */
/*0810*/ IMAD.MOV R14, RZ, RZ, -R15 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0f */
/*0820*/ @!P2 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0ca810 */
/* 0x000fe20007ffe0ff */
/*0830*/ IMAD.MOV R8, RZ, RZ, -R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a0b */
/*0840*/ IADD3 R2, R18, UR5, RZ ; /* 0x0000000512027c10 */
/* 0x000fe2000fffe0ff */
/*0850*/ IMAD R3, R0, R14, R3 ; /* 0x0000000e00037224 */
/* 0x000fe200078e0203 */
/*0860*/ ISETP.GE.AND P2, PT, R16, c[0x0][0x178], PT ; /* 0x00005e0010007a0c */
/* 0x000fe20003f46270 */
/*0870*/ IMAD.MOV R14, RZ, RZ, -R13 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0a0d */
/*0880*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fe20007ffe0ff */
/*0890*/ IMAD R8, R0, R8, R19 ; /* 0x0000000800087224 */
/* 0x000fe200078e0213 */
/*08a0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fe20003f06270 */
/*08b0*/ IMAD R14, R0, R14, R17 ; /* 0x0000000e000e7224 */
/* 0x000fe200078e0211 */
/*08c0*/ SEL R17, R21, R20, !P5 ; /* 0x0000001415117207 */
/* 0x000fe20006800000 */
/*08d0*/ @!P1 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0a0a */
/*08e0*/ @P4 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c4810 */
/* 0x000fc40007ffe0ff */
/*08f0*/ IADD3 R20, R3, UR5, RZ ; /* 0x0000000503147c10 */
/* 0x000fe2000fffe0ff */
/*0900*/ IMAD.MOV R18, RZ, RZ, -R17 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0a11 */
/*0910*/ SEL R19, R21.reuse, R10, !P5 ; /* 0x0000000a15137207 */
/* 0x040fe20006800000 */
/*0920*/ @!P2 IMAD R29, R6, c[0x0][0x4], R29 ; /* 0x00000100061daa24 */
/* 0x001fe200078e021d */
/*0930*/ ISETP.GE.AND P4, PT, R20, c[0x0][0x178], PT ; /* 0x00005e0014007a0c */
/* 0x000fe20003f86270 */
/*0940*/ @!P3 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0cb224 */
/* 0x000fe200078e0a0c */
/*0950*/ IADD3 R22, R8, UR5, RZ ; /* 0x0000000508167c10 */
/* 0x000fe2000fffe0ff */
/*0960*/ IMAD R27, R0, R18, R27 ; /* 0x00000012001b7224 */
/* 0x000fe200078e021b */
/*0970*/ IADD3 R14, R14, UR5, RZ ; /* 0x000000050e0e7c10 */
/* 0x000fe2000fffe0ff */
/*0980*/ IMAD.MOV R18, RZ, RZ, -R19 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0a13 */
/*0990*/ SEL R21, R21, R12, !P5 ; /* 0x0000000c15157207 */
/* 0x000fe20006800000 */
/*09a0*/ @!P0 IMAD R25, R6, c[0x0][0x4], R25 ; /* 0x0000010006198a24 */
/* 0x000fe200078e0219 */
/*09b0*/ ISETP.GE.AND P3, PT, R22, c[0x0][0x178], PT ; /* 0x00005e0016007a0c */
/* 0x000fe20003f66270 */
/*09c0*/ @!P2 IMAD R10, R29, c[0x0][0x178], R16 ; /* 0x00005e001d0aaa24 */
/* 0x000fc400078e0210 */
/*09d0*/ IMAD R18, R0, R18, R9 ; /* 0x0000001200127224 */
/* 0x000fe400078e0209 */
/*09e0*/ @!P0 IMAD R9, R25, c[0x0][0x178], R2 ; /* 0x00005e0019098a24 */
/* 0x000fe200078e0202 */
/*09f0*/ @!P2 IADD3 R2, P1, R10, c[0x0][0x168], RZ ; /* 0x00005a000a02aa10 */
/* 0x000fe20007f3e0ff */
/*0a00*/ IMAD.MOV R12, RZ, RZ, -R21 ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e0a15 */
/*0a10*/ @!P2 LEA.HI.X.SX32 R3, R10, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b000a03aa11 */
/* 0x000fe200008f0eff */
/*0a20*/ IMAD R16, R0, R12, R23 ; /* 0x0000000c00107224 */
/* 0x000fe200078e0217 */
/*0a30*/ ISETP.GE.AND P1, PT, R14, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x000fe20003f26270 */
/*0a40*/ @!P4 IMAD R15, R6, c[0x0][0x4], R15 ; /* 0x00000100060fca24 */
/* 0x000fe200078e020f */
/*0a50*/ @!P0 IADD3 R8, P6, R9, c[0x0][0x168], RZ ; /* 0x00005a0009088a10 */
/* 0x000fe40007fde0ff */
/*0a60*/ PRMT R10, RZ, 0x7610, R10 ; /* 0x00007610ff0a7816 */
/* 0x000fe4000000000a */
/*0a70*/ PRMT R12, RZ, 0x7610, R12 ; /* 0x00007610ff0c7816 */
/* 0x000fe2000000000c */
/*0a80*/ @!P4 IMAD R15, R15, c[0x0][0x178], R20 ; /* 0x00005e000f0fca24 */
/* 0x000fe200078e0214 */
/*0a90*/ IADD3 R27, R27, UR5, RZ ; /* 0x000000051b1b7c10 */
/* 0x000fc4000fffe0ff */
/*0aa0*/ IADD3 R18, R18, UR5, RZ ; /* 0x0000000512127c10 */
/* 0x000fe2000fffe0ff */
/*0ab0*/ @!P3 IMAD R11, R6, c[0x0][0x4], R11 ; /* 0x00000100060bba24 */
/* 0x000fe200078e020b */
/*0ac0*/ IADD3 R16, R16, UR5, RZ ; /* 0x0000000510107c10 */
/* 0x000fe2000fffe0ff */
/*0ad0*/ @!P2 LDG.E.U8 R10, [R2.64] ; /* 0x00000006020aa981 */
/* 0x0000a2000c1e1100 */
/*0ae0*/ @!P0 LEA.HI.X.SX32 R9, R9, c[0x0][0x16c], 0x1, P6 ; /* 0x00005b0009098a11 */
/* 0x000fe200030f0eff */
/*0af0*/ @!P1 IMAD R13, R6, c[0x0][0x4], R13 ; /* 0x00000100060d9a24 */
/* 0x000fe200078e020d */
/*0b00*/ ISETP.GE.AND P2, PT, R27, c[0x0][0x178], PT ; /* 0x00005e001b007a0c */
/* 0x000fe20003f46270 */
/*0b10*/ @!P3 IMAD R22, R11, c[0x0][0x178], R22 ; /* 0x00005e000b16ba24 */
/* 0x000fe200078e0216 */
/*0b20*/ ISETP.GE.AND P5, PT, R18, c[0x0][0x178], PT ; /* 0x00005e0012007a0c */
/* 0x000fe20003fa6270 */
/*0b30*/ @!P0 LDG.E.U8 R12, [R8.64] ; /* 0x00000006080c8981 */
/* 0x0002e2000c1e1100 */
/*0b40*/ ISETP.GE.AND P6, PT, R16, c[0x0][0x178], PT ; /* 0x00005e0010007a0c */
/* 0x000fe20003fc6270 */
/*0b50*/ @!P1 IMAD R11, R13, c[0x0][0x178], R14 ; /* 0x00005e000d0b9a24 */
/* 0x000fe200078e020e */
/*0b60*/ @!P4 IADD3 R2, P0, R15, c[0x0][0x168], RZ ; /* 0x00005a000f02ca10 */
/* 0x001fc80007f1e0ff */
/*0b70*/ @!P4 LEA.HI.X.SX32 R3, R15, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b000f03ca11 */
/* 0x000fe400000f0eff */
/*0b80*/ @!P3 IADD3 R14, P0, R22, c[0x0][0x168], RZ ; /* 0x00005a00160eba10 */
/* 0x000fe20007f1e0ff */
/*0b90*/ @!P2 IMAD R20, R6, c[0x0][0x4], R17 ; /* 0x000001000614aa24 */
/* 0x000fc600078e0211 */
/*0ba0*/ @!P3 LEA.HI.X.SX32 R15, R22, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b00160fba11 */
/* 0x000fe200000f0eff */
/*0bb0*/ @!P5 IMAD R19, R6.reuse, c[0x0][0x4], R19 ; /* 0x000001000613da24 */
/* 0x040fe200078e0213 */
/*0bc0*/ @!P1 IADD3 R8, P0, R11.reuse, c[0x0][0x168], RZ ; /* 0x00005a000b089a10 */
/* 0x042fe20007f1e0ff */
/*0bd0*/ @!P6 IMAD R13, R6, c[0x0][0x4], R21 ; /* 0x00000100060dea24 */
/* 0x000fe200078e0215 */
/*0be0*/ PRMT R24, RZ, 0x7610, R24 ; /* 0x00007610ff187816 */
/* 0x000fe40000000018 */
/*0bf0*/ PRMT R22, RZ, 0x7610, R22 ; /* 0x00007610ff167816 */
/* 0x000fe20000000016 */
/*0c00*/ @!P2 IMAD R27, R20, c[0x0][0x178], R27 ; /* 0x00005e00141baa24 */
/* 0x000fe200078e021b */
/*0c10*/ @!P1 LEA.HI.X.SX32 R9, R11, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b000b099a11 */
/* 0x000fe200000f0eff */
/*0c20*/ @!P5 IMAD R19, R19, c[0x0][0x178], R18 ; /* 0x00005e001313da24 */
/* 0x000fe200078e0212 */
/*0c30*/ @!P3 LDG.E.U8 R24, [R14.64] ; /* 0x000000060e18b981 */
/* 0x000f22000c1e1100 */
/*0c40*/ @!P6 IMAD R13, R13, c[0x0][0x178], R16 ; /* 0x00005e000d0dea24 */
/* 0x000fe200078e0210 */
/*0c50*/ @!P2 IADD3 R16, P0, R27, c[0x0][0x168], RZ ; /* 0x00005a001b10aa10 */
/* 0x000fc40007f1e0ff */
/*0c60*/ @!P1 LDG.E.U8 R22, [R8.64] ; /* 0x0000000608169981 */
/* 0x000f62000c1e1100 */
/*0c70*/ @!P5 IADD3 R18, P1, R19, c[0x0][0x168], RZ ; /* 0x00005a001312da10 */
/* 0x000fe40007f3e0ff */
/*0c80*/ @!P6 IADD3 R20, P3, R13, c[0x0][0x168], RZ ; /* 0x00005a000d14ea10 */
/* 0x000fe40007f7e0ff */
/*0c90*/ PRMT R26, RZ, 0x7610, R26 ; /* 0x00007610ff1a7816 */
/* 0x000fe4000000001a */
/*0ca0*/ PRMT R28, RZ, 0x7610, R28 ; /* 0x00007610ff1c7816 */
/* 0x000fe4000000001c */
/*0cb0*/ PRMT R23, RZ, 0x7610, R23 ; /* 0x00007610ff177816 */
/* 0x000fe40000000017 */
/*0cc0*/ PRMT R11, RZ, 0x7610, R11 ; /* 0x00007610ff0b7816 */
/* 0x000fe2000000000b */
/*0cd0*/ @!P4 LDG.E.U8 R26, [R2.64] ; /* 0x00000006021ac981 */
/* 0x000162000c1e1100 */
/*0ce0*/ @!P2 LEA.HI.X.SX32 R17, R27, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b001b11aa11 */
/* 0x000fc400000f0eff */
/*0cf0*/ @!P5 LEA.HI.X.SX32 R19, R19, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b001313da11 */
/* 0x000fe400008f0eff */
/*0d00*/ @!P6 LEA.HI.X.SX32 R21, R13, c[0x0][0x16c], 0x1, P3 ; /* 0x00005b000d15ea11 */
/* 0x000fe200018f0eff */
/*0d10*/ @!P2 LDG.E.U8 R28, [R16.64] ; /* 0x00000006101ca981 */
/* 0x000f68000c1e1100 */
/*0d20*/ @!P5 LDG.E.U8 R23, [R18.64] ; /* 0x000000061217d981 */
/* 0x000f68000c1e1100 */
/*0d30*/ @!P6 LDG.E.U8 R11, [R20.64] ; /* 0x00000006140be981 */
/* 0x000f62000c1e1100 */
/*0d40*/ IADD3 R2, R4, UR4, RZ ; /* 0x0000000404027c10 */
/* 0x001fe2000fffe0ff */
/*0d50*/ IMAD R3, R6, c[0x0][0x4], R5 ; /* 0x0000010006037a24 */
/* 0x000fc600078e0205 */
/*0d60*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fc80003f06270 */
/*0d70*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fe20000706670 */
/*0d80*/ STS.U8 [R7], R10 ; /* 0x0000000a07007388 */
/* 0x0041e80000000000 */
/*0d90*/ STS.U8 [R7+0x100], R12 ; /* 0x0001000c07007388 */
/* 0x0081e80000000000 */
/*0da0*/ STS.U8 [R7+0x300], R24 ; /* 0x0003001807007388 */
/* 0x0101e80000000000 */
/*0db0*/ STS.U8 [R7+0x400], R22 ; /* 0x0004001607007388 */
/* 0x0201e80000000000 */
/*0dc0*/ STS.U8 [R7+0x200], R26 ; /* 0x0002001a07007388 */
/* 0x0001e80000000000 */
/*0dd0*/ STS.U8 [R7+0x500], R28 ; /* 0x0005001c07007388 */
/* 0x0001e80000000000 */
/*0de0*/ STS.U8 [R7+0x600], R23 ; /* 0x0006001707007388 */
/* 0x0001e80000000000 */
/*0df0*/ STS.U8 [R7+0x700], R11 ; /* 0x0007000b07007388 */
/* 0x0001e80000000000 */
/*0e00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0e10*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0e20*/ IMAD.SHL.U32 R4, R4, 0x8, RZ ; /* 0x0000000804047824 */
/* 0x001fe400078e00ff */
/*0e30*/ IMAD R2, R3, c[0x0][0x174], R2 ; /* 0x00005d0003027a24 */
/* 0x000fc600078e0202 */
/*0e40*/ LOP3.LUT R4, R4, 0x1ffffff8, RZ, 0xc0, !PT ; /* 0x1ffffff804047812 */
/* 0x000fca00078ec0ff */
/*0e50*/ IMAD R0, R0, R5, R4 ; /* 0x0000000500007224 */
/* 0x000fca00078e0204 */
/*0e60*/ LDS.U8 R4, [R0+0x1] ; /* 0x0000010000047984 */
/* 0x000e280000000000 */
/*0e70*/ LDS.U8 R5, [R0+0x2] ; /* 0x0000020000057984 */
/* 0x000e680000000000 */
/*0e80*/ LDS.U8 R6, [R0+0x3] ; /* 0x0000030000067984 */
/* 0x000ea80000000000 */
/*0e90*/ LDS.U8 R10, [R0+0x5] ; /* 0x00000500000a7984 */
/* 0x000ee80000000000 */
/*0ea0*/ LDS.U8 R8, [R0] ; /* 0x0000000000087984 */
/* 0x000f280000000000 */
/*0eb0*/ LDS.U8 R11, [R0+0x6] ; /* 0x00000600000b7984 */
/* 0x000f680000000000 */
/*0ec0*/ LDS.U8 R12, [R0+0x7] ; /* 0x00000700000c7984 */
/* 0x000f680000000000 */
/*0ed0*/ LDS.U8 R9, [R0+0x4] ; /* 0x0000040000097984 */
/* 0x000f620000000000 */
/*0ee0*/ LOP3.LUT R13, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040d7812 */
/* 0x001fe200078ec0ff */
/*0ef0*/ IMAD.WIDE.U32 R4, R5, 0x10000, RZ ; /* 0x0001000005047825 */
/* 0x002fc600078e00ff */
/*0f00*/ SHF.L.U64.HI R15, R13, 0x8, RZ ; /* 0x000000080d0f7819 */
/* 0x000fe200000102ff */
/*0f10*/ IMAD.WIDE.U32 R6, R6, 0x1000000, RZ ; /* 0x0100000006067825 */
/* 0x004fc800078e00ff */
/*0f20*/ IMAD.SHL.U32 R13, R13, 0x100, RZ ; /* 0x000001000d0d7824 */
/* 0x000fe200078e00ff */
/*0f30*/ LOP3.LUT R5, R7, R5, R15, 0xfe, !PT ; /* 0x0000000507057212 */
/* 0x000fe200078efe0f */
/*0f40*/ IMAD.SHL.U32 R10, R10, 0x100, RZ ; /* 0x000001000a0a7824 */
/* 0x008fc600078e00ff */
/*0f50*/ LOP3.LUT R7, R13, 0xffff00ff, R8, 0xf8, !PT ; /* 0xffff00ff0d077812 */
/* 0x010fe200078ef808 */
/*0f60*/ IMAD.MOV.U32 R13, RZ, RZ, 0x8 ; /* 0x00000008ff0d7424 */
/* 0x000fe400078e00ff */
/*0f70*/ IMAD.U32 R11, R11, 0x10000, RZ ; /* 0x000100000b0b7824 */
/* 0x020fe200078e00ff */
/*0f80*/ LOP3.LUT R4, R6, R4, R7, 0xfe, !PT ; /* 0x0000000406047212 */
/* 0x000fe200078efe07 */
/*0f90*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e020d */
/*0fa0*/ IMAD.SHL.U32 R12, R12, 0x1000000, RZ ; /* 0x010000000c0c7824 */
/* 0x000fe200078e00ff */
/*0fb0*/ LOP3.LUT R9, R10, R9, R5, 0xfe, !PT ; /* 0x000000090a097212 */
/* 0x000fc800078efe05 */
/*0fc0*/ LOP3.LUT R5, R12, R11, R9, 0xfe, !PT ; /* 0x0000000b0c057212 */
/* 0x000fca00078efe09 */
/*0fd0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b06 */
/*0fe0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ff0*/ BRA 0xff0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected int8pack_kernel
.globl int8pack_kernel
.p2align 8
.type int8pack_kernel,@function
int8pack_kernel:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s7, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s8, 0xffff
s_lshr_b32 s8, s8, 16
s_lshl_b32 s4, s5, 3
s_mul_i32 s14, s14, s5
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s6, 0, s4
s_lshl_b32 s9, s14, 3
s_mul_i32 s15, s15, s8
s_and_b32 s8, s9, 0x1ffffff8
v_rcp_iflag_f32_e32 v1, v1
s_mov_b32 s9, 8
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mul_lo_u32 v1, s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v1
v_bfe_u32 v1, v0, 10, 10
v_mad_u32_u24 v0, v1, s5, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v3, v3, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt vmcnt(0)
ds_store_b8 v0, v5
v_add_nc_u32_e32 v0, 0x100, v0
s_add_i32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 0
s_cbranch_scc1 .LBB0_4
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v0, v3
v_not_b32_e32 v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, v4, s5
v_mad_u64_u32 v[4:5], null, s6, v6, v[0:1]
v_lshl_add_u32 v7, v7, 3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_dual_cndmask_b32 v4, v4, v7 :: v_dual_add_nc_u32 v5, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v6, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, 1, v5
v_cndmask_b32_e32 v4, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s6, v4
v_add3_u32 v5, s8, v0, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s7, v5
v_mov_b32_e32 v5, 0
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v5, s15, v4
v_mul_lo_u32 v4, v4, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s7
v_sub_nc_u32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, s8, v0, v4
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_u8 v5, v[4:5], off
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[2:3], s[0:1], 0x10
v_add_nc_u32_e32 v3, s15, v1
v_add_nc_u32_e32 v0, s14, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, s2, v3
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v2, 3, v2
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v3, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u32_u24 v0, s4, v1, v2
v_ashrrev_i32_e32 v5, 31, v4
ds_load_b64 v[0:1], v0
v_lshlrev_b64 v[2:3], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel int8pack_kernel
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size int8pack_kernel, .Lfunc_end0-int8pack_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: int8pack_kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: int8pack_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000697cb_00000000-6_int8pack.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii
.type _Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii, @function
_Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq int8pack_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii, .-_Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii
.globl int8pack_kernel
.type int8pack_kernel, @function
int8pack_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15int8pack_kernelPlPKhiiiPlPKhiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size int8pack_kernel, .-int8pack_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "int8pack_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq int8pack_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "int8pack.hip"
.globl __device_stub__int8pack_kernel # -- Begin function __device_stub__int8pack_kernel
.p2align 4, 0x90
.type __device_stub__int8pack_kernel,@function
__device_stub__int8pack_kernel: # @__device_stub__int8pack_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $int8pack_kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__int8pack_kernel, .Lfunc_end0-__device_stub__int8pack_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $int8pack_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type int8pack_kernel,@object # @int8pack_kernel
.section .rodata,"a",@progbits
.globl int8pack_kernel
.p2align 3, 0x0
int8pack_kernel:
.quad __device_stub__int8pack_kernel
.size int8pack_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "int8pack_kernel"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__int8pack_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym int8pack_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda.h>
__global__ void shubham(){
printf("shubham");
}
__global__ void dkernel(){
printf("hello ");
}
int main(){
dkernel<<<1,1>>>();
shubham<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z7dkernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7shubhamv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda.h>
__global__ void shubham(){
printf("shubham");
}
__global__ void dkernel(){
printf("hello ");
}
int main(){
dkernel<<<1,1>>>();
shubham<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0015759a_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z7shubhamvv
.type _Z25__device_stub__Z7shubhamvv, @function
_Z25__device_stub__Z7shubhamvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7shubhamv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z7shubhamvv, .-_Z25__device_stub__Z7shubhamvv
.globl _Z7shubhamv
.type _Z7shubhamv, @function
_Z7shubhamv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7shubhamvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7shubhamv, .-_Z7shubhamv
.globl _Z25__device_stub__Z7dkernelvv
.type _Z25__device_stub__Z7dkernelvv, @function
_Z25__device_stub__Z7dkernelvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7dkernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z25__device_stub__Z7dkernelvv, .-_Z25__device_stub__Z7dkernelvv
.globl _Z7dkernelv
.type _Z7dkernelv, @function
_Z7dkernelv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7dkernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7dkernelv, .-_Z7dkernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call _Z25__device_stub__Z7dkernelvv
jmp .L20
.L24:
call _Z25__device_stub__Z7shubhamvv
jmp .L21
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7dkernelv"
.LC1:
.string "_Z7shubhamv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7dkernelv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7shubhamv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda.h>
__global__ void shubham(){
printf("shubham");
}
__global__ void dkernel(){
printf("hello ");
}
int main(){
dkernel<<<1,1>>>();
shubham<<<1,1>>>();
cudaDeviceSynchronize();
return 0;
} | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void shubham(){
printf("shubham");
}
__global__ void dkernel(){
printf("hello ");
}
int main(){
dkernel<<<1,1>>>();
shubham<<<1,1>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void shubham(){
printf("shubham");
}
__global__ void dkernel(){
printf("hello ");
}
int main(){
dkernel<<<1,1>>>();
shubham<<<1,1>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "main.hip"
.globl _Z22__device_stub__shubhamv # -- Begin function _Z22__device_stub__shubhamv
.p2align 4, 0x90
.type _Z22__device_stub__shubhamv,@function
_Z22__device_stub__shubhamv: # @_Z22__device_stub__shubhamv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7shubhamv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z22__device_stub__shubhamv, .Lfunc_end0-_Z22__device_stub__shubhamv
.cfi_endproc
# -- End function
.globl _Z22__device_stub__dkernelv # -- Begin function _Z22__device_stub__dkernelv
.p2align 4, 0x90
.type _Z22__device_stub__dkernelv,@function
_Z22__device_stub__dkernelv: # @_Z22__device_stub__dkernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z22__device_stub__dkernelv, .Lfunc_end1-_Z22__device_stub__dkernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7shubhamv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7shubhamv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7dkernelv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7shubhamv,@object # @_Z7shubhamv
.section .rodata,"a",@progbits
.globl _Z7shubhamv
.p2align 3, 0x0
_Z7shubhamv:
.quad _Z22__device_stub__shubhamv
.size _Z7shubhamv, 8
.type _Z7dkernelv,@object # @_Z7dkernelv
.globl _Z7dkernelv
.p2align 3, 0x0
_Z7dkernelv:
.quad _Z22__device_stub__dkernelv
.size _Z7dkernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7shubhamv"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7dkernelv"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__shubhamv
.addrsig_sym _Z22__device_stub__dkernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7shubhamv
.addrsig_sym _Z7dkernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015759a_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z7shubhamvv
.type _Z25__device_stub__Z7shubhamvv, @function
_Z25__device_stub__Z7shubhamvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7shubhamv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z7shubhamvv, .-_Z25__device_stub__Z7shubhamvv
.globl _Z7shubhamv
.type _Z7shubhamv, @function
_Z7shubhamv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7shubhamvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7shubhamv, .-_Z7shubhamv
.globl _Z25__device_stub__Z7dkernelvv
.type _Z25__device_stub__Z7dkernelvv, @function
_Z25__device_stub__Z7dkernelvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7dkernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z25__device_stub__Z7dkernelvv, .-_Z25__device_stub__Z7dkernelvv
.globl _Z7dkernelv
.type _Z7dkernelv, @function
_Z7dkernelv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7dkernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7dkernelv, .-_Z7dkernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call _Z25__device_stub__Z7dkernelvv
jmp .L20
.L24:
call _Z25__device_stub__Z7shubhamvv
jmp .L21
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7dkernelv"
.LC1:
.string "_Z7shubhamv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7dkernelv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7shubhamv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z22__device_stub__shubhamv # -- Begin function _Z22__device_stub__shubhamv
.p2align 4, 0x90
.type _Z22__device_stub__shubhamv,@function
_Z22__device_stub__shubhamv: # @_Z22__device_stub__shubhamv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7shubhamv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z22__device_stub__shubhamv, .Lfunc_end0-_Z22__device_stub__shubhamv
.cfi_endproc
# -- End function
.globl _Z22__device_stub__dkernelv # -- Begin function _Z22__device_stub__dkernelv
.p2align 4, 0x90
.type _Z22__device_stub__dkernelv,@function
_Z22__device_stub__dkernelv: # @_Z22__device_stub__dkernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z22__device_stub__dkernelv, .Lfunc_end1-_Z22__device_stub__dkernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7shubhamv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7shubhamv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7dkernelv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7shubhamv,@object # @_Z7shubhamv
.section .rodata,"a",@progbits
.globl _Z7shubhamv
.p2align 3, 0x0
_Z7shubhamv:
.quad _Z22__device_stub__shubhamv
.size _Z7shubhamv, 8
.type _Z7dkernelv,@object # @_Z7dkernelv
.globl _Z7dkernelv
.p2align 3, 0x0
_Z7dkernelv:
.quad _Z22__device_stub__dkernelv
.size _Z7dkernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7shubhamv"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7dkernelv"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__shubhamv
.addrsig_sym _Z22__device_stub__dkernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7shubhamv
.addrsig_sym _Z7dkernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // =================================================================================================
// This file is part of the CLTune project, which loosely follows the Google C++ styleguide and uses
// a tab-size of two spaces and a max-width of 100 characters per line.
//
// Author: cedric.nugteren@surfsara.nl (Cedric Nugteren)
//
// This file contains an example OpenCL kernel as part of the gemm.cc example.
//
// -------------------------------------------------------------------------------------------------
//
// Copyright 2014 SURFsara
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// =================================================================================================
// Reference implementation of the matrix-matrix multiplication example. Note: this kernel assumes
// that matrix B is pre-transposed.
extern "C" __global__ void gemm_reference(const int kSizeM, const int kSizeN, const int kSizeK,
const float* mat_a,
const float* mat_b,
float* mat_c) {
// Thread identifiers
const int row = blockDim.x*blockIdx.x + threadIdx.x; // From 0 to kSizeM-1
const int col = blockDim.y*blockIdx.y + threadIdx.y; // From 0 to kSizeN-1
// Computes a single value
float result = 0.0f;
for (int k=0; k<kSizeK; k++) {
float mat_a_val = mat_a[k*kSizeM + row];
float mat_b_val = mat_b[k*kSizeN + col];
result += mat_a_val * mat_b_val;
}
// Stores the result
mat_c[col*kSizeM + row] = result;
}
// ================================================================================================= | code for sm_80
Function : gemm_reference
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xc80 ; /* 0x00000bc000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x000fe40007ffe0ff */
/*00d0*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe40000000f00 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ LOP3.LUT R2, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304027812 */
/* 0x000fe400078ec0ff */
/*0100*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xb90 ; /* 0x00000a7000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R5, -R2, c[0x0][0x168], RZ ; /* 0x00005a0002057a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0140*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fce0003f04270 */
/*0170*/ IMAD.WIDE R14, R3, R6, c[0x0][0x178] ; /* 0x00005e00030e7625 */
/* 0x000fc800078e0206 */
/*0180*/ IMAD.WIDE R16, R0, R6, c[0x0][0x170] ; /* 0x00005c0000107625 */
/* 0x000fe400078e0206 */
/*0190*/ @!P0 BRA 0xa10 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x720 ; /* 0x0000055000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x0000a8000c1e1900 */
/*01f0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002a2000c1e1900 */
/*0200*/ IMAD.WIDE R22, R6, c[0x0][0x164], R14 ; /* 0x0000590006167a25 */
/* 0x000fc800078e020e */
/*0210*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x160], R16 ; /* 0x00005800061a7a25 */
/* 0x040fe200078e0210 */
/*0220*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000728000c1e1900 */
/*0230*/ LDG.E R24, [R26.64] ; /* 0x000000041a187981 */
/* 0x000b22000c1e1900 */
/*0240*/ IMAD.WIDE R22, R6, c[0x0][0x164], R22 ; /* 0x0000590006167a25 */
/* 0x008fc800078e0216 */
/*0250*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x160], R26 ; /* 0x00005800061a7a25 */
/* 0x060fe200078e021a */
/*0260*/ LDG.E R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000766000c1e1900 */
/*0270*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x164], R22 ; /* 0x00005900060e7a25 */
/* 0x041fe200078e0216 */
/*0280*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000166000c1e1900 */
/*0290*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x160], R26 ; /* 0x00005800060c7a25 */
/* 0x040fe200078e021a */
/*02a0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x002368000c1e1900 */
/*02b0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000162000c1e1900 */
/*02c0*/ IMAD.WIDE R28, R6, c[0x0][0x160], R12 ; /* 0x00005800061c7a25 */
/* 0x000fc800078e020c */
/*02d0*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x164], R14 ; /* 0x00005900060e7a25 */
/* 0x042fe200078e020e */
/*02e0*/ LDG.E R17, [R28.64] ; /* 0x000000041c117981 */
/* 0x000368000c1e1900 */
/*02f0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x008762000c1e1900 */
/*0300*/ IMAD.WIDE R26, R6, c[0x0][0x164], R14 ; /* 0x00005900061a7a25 */
/* 0x001fc800078e020e */
/*0310*/ IMAD.WIDE R28, R6.reuse, c[0x0][0x160], R28 ; /* 0x00005800061c7a25 */
/* 0x042fe200078e021c */
/*0320*/ LDG.E R23, [R26.64] ; /* 0x000000041a177981 */
/* 0x00016a000c1e1900 */
/*0330*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x160], R28 ; /* 0x00005800060c7a25 */
/* 0x040fe400078e021c */
/*0340*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000564000c1e1900 */
/*0350*/ IMAD.WIDE R26, R6, c[0x0][0x164], R26 ; /* 0x00005900061a7a25 */
/* 0x001fc400078e021a */
/*0360*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x000168000c1e1900 */
/*0370*/ LDG.E R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x000362000c1e1900 */
/*0380*/ IMAD.WIDE R14, R6, c[0x0][0x164], R26 ; /* 0x00005900060e7a25 */
/* 0x008fc800078e021a */
/*0390*/ IMAD.WIDE R12, R6, c[0x0][0x160], R12 ; /* 0x00005800060c7a25 */
/* 0x001fc800078e020c */
/*03a0*/ FFMA R29, R20, R9, R10 ; /* 0x00000009141d7223 */
/* 0x004fe4000000000a */
/*03b0*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x0000a8000c1e1900 */
/*03c0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x0006a2000c1e1900 */
/*03d0*/ IMAD.WIDE R20, R6, c[0x0][0x160], R12 ; /* 0x0000580006147a25 */
/* 0x000fc800078e020c */
/*03e0*/ FFMA R29, R11, R24, R29 ; /* 0x000000180b1d7223 */
/* 0x010fe4000000001d */
/*03f0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0008a2000c1e1900 */
/*0400*/ IMAD.WIDE R14, R6, c[0x0][0x164], R14 ; /* 0x00005900060e7a25 */
/* 0x008fca00078e020e */
/*0410*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x0006a2000c1e1900 */
/*0420*/ IMAD.WIDE R26, R6, c[0x0][0x160], R20 ; /* 0x00005800061a7a25 */
/* 0x002fc800078e0214 */
/*0430*/ FFMA R29, R19, R18, R29 ; /* 0x00000012131d7223 */
/* 0x020fe4000000001d */
/*0440*/ IMAD.WIDE R18, R6, c[0x0][0x164], R14 ; /* 0x0000590006127a25 */
/* 0x000fc800078e020e */
/*0450*/ FFMA R16, R16, R25, R29 ; /* 0x0000001910107223 */
/* 0x000fe4000000001d */
/*0460*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000362000c1e1900 */
/*0470*/ IMAD.WIDE R12, R6, c[0x0][0x160], R26 ; /* 0x00005800060c7a25 */
/* 0x001fc600078e021a */
/*0480*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000162000c1e1900 */
/*0490*/ IMAD.WIDE R18, R6, c[0x0][0x164], R18 ; /* 0x0000590006127a25 */
/* 0x002fc800078e0212 */
/*04a0*/ FFMA R22, R22, R17, R16 ; /* 0x0000001116167223 */
/* 0x000fe20000000010 */
/*04b0*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x001162000c1e1900 */
/*04c0*/ IMAD.WIDE R14, R6, c[0x0][0x160], R12 ; /* 0x00005800060e7a25 */
/* 0x008fc600078e020c */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0004e2000c1e1900 */
/*04e0*/ IMAD.WIDE R16, R6, c[0x0][0x164], R18 ; /* 0x0000590006107a25 */
/* 0x000fc600078e0212 */
/*04f0*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x0002e2000c1e1900 */
/*0500*/ FFMA R28, R23, R28, R22 ; /* 0x0000001c171c7223 */
/* 0x000fe40000000016 */
/*0510*/ IMAD.WIDE R20, R6, c[0x0][0x160], R14 ; /* 0x0000580006147a25 */
/* 0x010fc800078e020e */
/*0520*/ IMAD.WIDE R22, R6, c[0x0][0x164], R16 ; /* 0x0000590006167a25 */
/* 0x000fe400078e0210 */
/*0530*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008e4000c1e1900 */
/*0540*/ FFMA R8, R8, R7, R28 ; /* 0x0000000708087223 */
/* 0x000fe4000000001c */
/*0550*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x160], R20 ; /* 0x00005800060e7a25 */
/* 0x042fe200078e0214 */
/*0560*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x0002e6000c1e1900 */
/*0570*/ IMAD.WIDE R18, R6, c[0x0][0x164], R22 ; /* 0x0000590006127a25 */
/* 0x001fe200078e0216 */
/*0580*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee6000c1e1900 */
/*0590*/ FFMA R13, R10, R9, R8 ; /* 0x000000090a0d7223 */
/* 0x004fc40000000008 */
/*05a0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000a2000c1e1900 */
/*05b0*/ IMAD.WIDE R8, R6, c[0x0][0x160], R14 ; /* 0x0000580006087a25 */
/* 0x000fc600078e020e */
/*05c0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x0108a2000c1e1900 */
/*05e0*/ IMAD.WIDE R18, R6, c[0x0][0x164], R18 ; /* 0x0000590006127a25 */
/* 0x001fca00078e0212 */
/*05f0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IMAD.WIDE R22, R6, c[0x0][0x164], R18 ; /* 0x0000590006167a25 */
/* 0x002fc800078e0212 */
/*0610*/ IMAD.WIDE R8, R6, c[0x0][0x160], R8 ; /* 0x0000580006087a25 */
/* 0x010fc800078e0208 */
/*0620*/ FFMA R13, R11, R24, R13 ; /* 0x000000180b0d7223 */
/* 0x000fe4000000000d */
/*0630*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000f28000c1e1900 */
/*0640*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000f22000c1e1900 */
/*0650*/ FFMA R13, R25, R26, R13 ; /* 0x0000001a190d7223 */
/* 0x020fe2000000000d */
/*0660*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0680*/ FFMA R12, R27, R12, R13 ; /* 0x0000000c1b0c7223 */
/* 0x008fc8000000000d */
/*0690*/ FFMA R12, R16, R29, R12 ; /* 0x0000001d100c7223 */
/* 0x000fc8000000000c */
/*06a0*/ FFMA R7, R7, R20, R12 ; /* 0x0000001407077223 */
/* 0x000fe2000000000c */
/*06b0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*06c0*/ FFMA R7, R10, R15, R7 ; /* 0x0000000f0a077223 */
/* 0x004fe40000000007 */
/*06d0*/ IMAD.WIDE R14, R6, c[0x0][0x164], R22 ; /* 0x00005900060e7a25 */
/* 0x000fc800078e0216 */
/*06e0*/ FFMA R7, R28, R17, R7 ; /* 0x000000111c077223 */
/* 0x000fe40000000007 */
/*06f0*/ IMAD.WIDE R16, R6, c[0x0][0x160], R8 ; /* 0x0000580006107a25 */
/* 0x000fc800078e0208 */
/*0700*/ FFMA R10, R11, R24, R7 ; /* 0x000000180b0a7223 */
/* 0x010fe20000000007 */
/*0710*/ @P1 BRA 0x1e0 ; /* 0xfffffac000001947 */
/* 0x000fea000383ffff */
/*0720*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0730*/ @!P1 BRA 0x9f0 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0740*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x0000a8000c1e1900 */
/*0750*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0002a2000c1e1900 */
/*0760*/ IMAD.WIDE R8, R6, c[0x0][0x160], R16 ; /* 0x0000580006087a25 */
/* 0x000fc800078e0210 */
/*0770*/ IMAD.WIDE R12, R6, c[0x0][0x164], R14 ; /* 0x00005900060c7a25 */
/* 0x000fc800078e020e */
/*0780*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x160], R8 ; /* 0x00005800060e7a25 */
/* 0x041fe200078e0208 */
/*0790*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x0000e6000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x164], R12 ; /* 0x0000590006127a25 */
/* 0x040fe200078e020c */
/*07b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0008e6000c1e1900 */
/*07c0*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x160], R14 ; /* 0x0000580006107a25 */
/* 0x042fe200078e020e */
/*07d0*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000366000c1e1900 */
/*07e0*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x164], R18 ; /* 0x0000590006147a25 */
/* 0x040fe200078e0212 */
/*07f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000366000c1e1900 */
/*0800*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x160], R16 ; /* 0x00005800060c7a25 */
/* 0x041fe200078e0210 */
/*0810*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000166000c1e1900 */
/*0820*/ IMAD.WIDE R22, R6, c[0x0][0x164], R20 ; /* 0x0000590006167a25 */
/* 0x000fc400078e0214 */
/*0830*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000964000c1e1900 */
/*0840*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x160], R12 ; /* 0x00005800060e7a25 */
/* 0x042fe400078e020c */
/*0850*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000364000c1e1900 */
/*0860*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x164], R22 ; /* 0x0000590006107a25 */
/* 0x041fe400078e0216 */
/*0870*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x010128000c1e1900 */
/*0880*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x164], R16 ; /* 0x0000590006127a25 */
/* 0x040fe200078e0210 */
/*0890*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000326000c1e1900 */
/*08a0*/ IMAD.WIDE R12, R6, c[0x0][0x160], R14 ; /* 0x00005800060c7a25 */
/* 0x001fc400078e020e */
/*08b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*08c0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x002122000c1e1900 */
/*08d0*/ IMAD.WIDE R22, R6, c[0x0][0x160], R12 ; /* 0x0000580006167a25 */
/* 0x000fc600078e020c */
/*08e0*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x000f22000c1e1900 */
/*08f0*/ IMAD.WIDE R18, R6, c[0x0][0x164], R18 ; /* 0x0000590006127a25 */
/* 0x001fc800078e0212 */
/*0900*/ FFMA R28, R27, R28, R10 ; /* 0x0000001c1b1c7223 */
/* 0x004fe4000000000a */
/*0910*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x000ea8000c1e1900 */
/*0920*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea2000c1e1900 */
/*0930*/ FFMA R7, R7, R8, R28 ; /* 0x0000000807077223 */
/* 0x008fc8000000001c */
/*0940*/ FFMA R7, R25, R26, R7 ; /* 0x0000001a19077223 */
/* 0x020fc80000000007 */
/*0950*/ FFMA R7, R21, R24, R7 ; /* 0x0000001815077223 */
/* 0x000fc80000000007 */
/*0960*/ FFMA R7, R11, R20, R7 ; /* 0x000000140b077223 */
/* 0x010fe20000000007 */
/*0970*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0980*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0990*/ FFMA R7, R9, R14, R7 ; /* 0x0000000e09077223 */
/* 0x000fe20000000007 */
/*09a0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*09b0*/ IMAD.WIDE R14, R6, c[0x0][0x164], R18 ; /* 0x00005900060e7a25 */
/* 0x000fc800078e0212 */
/*09c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fe40000000007 */
/*09d0*/ IMAD.WIDE R16, R6, c[0x0][0x160], R22 ; /* 0x0000580006107a25 */
/* 0x000fc800078e0216 */
/*09e0*/ FFMA R10, R10, R27, R7 ; /* 0x0000001b0a0a7223 */
/* 0x004fe40000000007 */
/*09f0*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0a00*/ @!P0 BRA 0xb90 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD.WIDE R8, R6.reuse, c[0x0][0x160], R16 ; /* 0x0000580006087a25 */
/* 0x040fe400078e0210 */
/*0a20*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1900 */
/*0a30*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x164], R14 ; /* 0x00005900060c7a25 */
/* 0x040fe400078e020e */
/*0a40*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x0000a4000c1e1900 */
/*0a50*/ IMAD.WIDE R22, R6.reuse, c[0x0][0x160], R8 ; /* 0x0000580006167a25 */
/* 0x040fe400078e0208 */
/*0a60*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1900 */
/*0a70*/ IMAD.WIDE R18, R6, c[0x0][0x164], R12 ; /* 0x0000590006127a25 */
/* 0x000fc400078e020c */
/*0a80*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee4000c1e1900 */
/*0a90*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x160], R22 ; /* 0x0000580006147a25 */
/* 0x040fe400078e0216 */
/*0aa0*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x000f24000c1e1900 */
/*0ab0*/ IMAD.WIDE R24, R6, c[0x0][0x164], R18 ; /* 0x0000590006187a25 */
/* 0x000fe400078e0212 */
/*0ac0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000f28000c1e1900 */
/*0ad0*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000f68000c1e1900 */
/*0ae0*/ LDG.E R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x001f62000c1e1900 */
/*0af0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0b10*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ FFMA R15, R15, R16, R10 ; /* 0x000000100f0f7223 */
/* 0x004fc8000000000a */
/*0b30*/ FFMA R15, R12, R8, R15 ; /* 0x000000080c0f7223 */
/* 0x008fe4000000000f */
/*0b40*/ IMAD.WIDE R16, R6, c[0x0][0x160], R20 ; /* 0x0000580006107a25 */
/* 0x000fc800078e0214 */
/*0b50*/ FFMA R7, R26, R7, R15 ; /* 0x000000071a077223 */
/* 0x010fc8000000000f */
/*0b60*/ FFMA R10, R14, R11, R7 ; /* 0x0000000b0e0a7223 */
/* 0x020fe40000000007 */
/*0b70*/ IMAD.WIDE R14, R6, c[0x0][0x164], R24 ; /* 0x00005900060e7a25 */
/* 0x000fe200078e0218 */
/*0b80*/ @P0 BRA 0xa10 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0b90*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0ba0*/ @!P0 BRA 0xc80 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0bb0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0bc0*/ IMAD R5, R4.reuse, c[0x0][0x164], R3 ; /* 0x0000590004057a24 */
/* 0x040fe400078e0203 */
/*0bd0*/ IMAD R6, R4, c[0x0][0x160], R0 ; /* 0x0000580004067a24 */
/* 0x000fce00078e0200 */
/*0be0*/ IMAD.WIDE R4, R5, R11, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fc800078e020b */
/*0bf0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e020b */
/*0c00*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0c10*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0002a2000c1e1900 */
/*0c20*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0c30*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0c40*/ IMAD.WIDE R4, R11, c[0x0][0x164], R4 ; /* 0x000059000b047a25 */
/* 0x001fc800078e0204 */
/*0c50*/ IMAD.WIDE R6, R11, c[0x0][0x160], R6 ; /* 0x000058000b067a25 */
/* 0x002fc800078e0206 */
/*0c60*/ FFMA R10, R9, R8, R10 ; /* 0x00000008090a7223 */
/* 0x004fc8000000000a */
/*0c70*/ @P0 BRA 0xc00 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0c80*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c90*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fc800078e0200 */
/*0ca0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x000fca00078e0202 */
/*0cb0*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe2000c101904 */
/*0cc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // =================================================================================================
// This file is part of the CLTune project, which loosely follows the Google C++ styleguide and uses
// a tab-size of two spaces and a max-width of 100 characters per line.
//
// Author: cedric.nugteren@surfsara.nl (Cedric Nugteren)
//
// This file contains an example OpenCL kernel as part of the gemm.cc example.
//
// -------------------------------------------------------------------------------------------------
//
// Copyright 2014 SURFsara
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// =================================================================================================
// Reference implementation of the matrix-matrix multiplication example. Note: this kernel assumes
// that matrix B is pre-transposed.
extern "C" __global__ void gemm_reference(const int kSizeM, const int kSizeN, const int kSizeK,
const float* mat_a,
const float* mat_b,
float* mat_c) {
// Thread identifiers
const int row = blockDim.x*blockIdx.x + threadIdx.x; // From 0 to kSizeM-1
const int col = blockDim.y*blockIdx.y + threadIdx.y; // From 0 to kSizeN-1
// Computes a single value
float result = 0.0f;
for (int k=0; k<kSizeK; k++) {
float mat_a_val = mat_a[k*kSizeM + row];
float mat_b_val = mat_b[k*kSizeN + col];
result += mat_a_val * mat_b_val;
}
// Stores the result
mat_c[col*kSizeM + row] = result;
}
// ================================================================================================= | .file "tmpxft_001705c2_00000000-6_ClTuneGemmReference.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf
.type _Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf, @function
_Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq gemm_reference(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf, .-_Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf
.globl gemm_reference
.type gemm_reference, @function
gemm_reference:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size gemm_reference, .-gemm_reference
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gemm_reference"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gemm_reference(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // =================================================================================================
// This file is part of the CLTune project, which loosely follows the Google C++ styleguide and uses
// a tab-size of two spaces and a max-width of 100 characters per line.
//
// Author: cedric.nugteren@surfsara.nl (Cedric Nugteren)
//
// This file contains an example OpenCL kernel as part of the gemm.cc example.
//
// -------------------------------------------------------------------------------------------------
//
// Copyright 2014 SURFsara
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// =================================================================================================
// Reference implementation of the matrix-matrix multiplication example. Note: this kernel assumes
// that matrix B is pre-transposed.
extern "C" __global__ void gemm_reference(const int kSizeM, const int kSizeN, const int kSizeK,
const float* mat_a,
const float* mat_b,
float* mat_c) {
// Thread identifiers
const int row = blockDim.x*blockIdx.x + threadIdx.x; // From 0 to kSizeM-1
const int col = blockDim.y*blockIdx.y + threadIdx.y; // From 0 to kSizeN-1
// Computes a single value
float result = 0.0f;
for (int k=0; k<kSizeK; k++) {
float mat_a_val = mat_a[k*kSizeM + row];
float mat_b_val = mat_b[k*kSizeN + col];
result += mat_a_val * mat_b_val;
}
// Stores the result
mat_c[col*kSizeM + row] = result;
}
// ================================================================================================= | #include <hip/hip_runtime.h>
// =================================================================================================
// This file is part of the CLTune project, which loosely follows the Google C++ styleguide and uses
// a tab-size of two spaces and a max-width of 100 characters per line.
//
// Author: cedric.nugteren@surfsara.nl (Cedric Nugteren)
//
// This file contains an example OpenCL kernel as part of the gemm.cc example.
//
// -------------------------------------------------------------------------------------------------
//
// Copyright 2014 SURFsara
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// =================================================================================================
// Reference implementation of the matrix-matrix multiplication example. Note: this kernel assumes
// that matrix B is pre-transposed.
extern "C" __global__ void gemm_reference(const int kSizeM, const int kSizeN, const int kSizeK,
const float* mat_a,
const float* mat_b,
float* mat_c) {
// Thread identifiers
const int row = blockDim.x*blockIdx.x + threadIdx.x; // From 0 to kSizeM-1
const int col = blockDim.y*blockIdx.y + threadIdx.y; // From 0 to kSizeN-1
// Computes a single value
float result = 0.0f;
for (int k=0; k<kSizeK; k++) {
float mat_a_val = mat_a[k*kSizeM + row];
float mat_b_val = mat_b[k*kSizeN + col];
result += mat_a_val * mat_b_val;
}
// Stores the result
mat_c[col*kSizeM + row] = result;
}
// ================================================================================================= |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// =================================================================================================
// This file is part of the CLTune project, which loosely follows the Google C++ styleguide and uses
// a tab-size of two spaces and a max-width of 100 characters per line.
//
// Author: cedric.nugteren@surfsara.nl (Cedric Nugteren)
//
// This file contains an example OpenCL kernel as part of the gemm.cc example.
//
// -------------------------------------------------------------------------------------------------
//
// Copyright 2014 SURFsara
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// =================================================================================================
// Reference implementation of the matrix-matrix multiplication example. Note: this kernel assumes
// that matrix B is pre-transposed.
extern "C" __global__ void gemm_reference(const int kSizeM, const int kSizeN, const int kSizeK,
const float* mat_a,
const float* mat_b,
float* mat_c) {
// Thread identifiers
const int row = blockDim.x*blockIdx.x + threadIdx.x; // From 0 to kSizeM-1
const int col = blockDim.y*blockIdx.y + threadIdx.y; // From 0 to kSizeN-1
// Computes a single value
float result = 0.0f;
for (int k=0; k<kSizeK; k++) {
float mat_a_val = mat_a[k*kSizeM + row];
float mat_b_val = mat_b[k*kSizeN + col];
result += mat_a_val * mat_b_val;
}
// Stores the result
mat_c[col*kSizeM + row] = result;
}
// ================================================================================================= | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gemm_reference
.globl gemm_reference
.p2align 8
.type gemm_reference,@function
gemm_reference:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b32 s8, s[0:1], 0x4
s_load_b128 s[4:7], s[0:1], 0x10
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, v0
v_mov_b32_e32 v4, v1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, s8, v4
v_add_nc_u32_e32 v2, s2, v2
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel gemm_reference
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size gemm_reference, .Lfunc_end0-gemm_reference
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: gemm_reference
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: gemm_reference.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// =================================================================================================
// This file is part of the CLTune project, which loosely follows the Google C++ styleguide and uses
// a tab-size of two spaces and a max-width of 100 characters per line.
//
// Author: cedric.nugteren@surfsara.nl (Cedric Nugteren)
//
// This file contains an example OpenCL kernel as part of the gemm.cc example.
//
// -------------------------------------------------------------------------------------------------
//
// Copyright 2014 SURFsara
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// =================================================================================================
// Reference implementation of the matrix-matrix multiplication example. Note: this kernel assumes
// that matrix B is pre-transposed.
extern "C" __global__ void gemm_reference(const int kSizeM, const int kSizeN, const int kSizeK,
const float* mat_a,
const float* mat_b,
float* mat_c) {
// Thread identifiers
const int row = blockDim.x*blockIdx.x + threadIdx.x; // From 0 to kSizeM-1
const int col = blockDim.y*blockIdx.y + threadIdx.y; // From 0 to kSizeN-1
// Computes a single value
float result = 0.0f;
for (int k=0; k<kSizeK; k++) {
float mat_a_val = mat_a[k*kSizeM + row];
float mat_b_val = mat_b[k*kSizeN + col];
result += mat_a_val * mat_b_val;
}
// Stores the result
mat_c[col*kSizeM + row] = result;
}
// ================================================================================================= | .text
.file "ClTuneGemmReference.hip"
.globl __device_stub__gemm_reference # -- Begin function __device_stub__gemm_reference
.p2align 4, 0x90
.type __device_stub__gemm_reference,@function
__device_stub__gemm_reference: # @__device_stub__gemm_reference
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $gemm_reference, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__gemm_reference, .Lfunc_end0-__device_stub__gemm_reference
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gemm_reference, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gemm_reference,@object # @gemm_reference
.section .rodata,"a",@progbits
.globl gemm_reference
.p2align 3, 0x0
gemm_reference:
.quad __device_stub__gemm_reference
.size gemm_reference, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gemm_reference"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gemm_reference
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gemm_reference
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : gemm_reference
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc600078e0205 */
/*00b0*/ @!P0 BRA 0xc80 ; /* 0x00000bc000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x000fe40007ffe0ff */
/*00d0*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe40000000f00 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00f0*/ LOP3.LUT R2, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304027812 */
/* 0x000fe400078ec0ff */
/*0100*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xb90 ; /* 0x00000a7000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R5, -R2, c[0x0][0x168], RZ ; /* 0x00005a0002057a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0140*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0160*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fce0003f04270 */
/*0170*/ IMAD.WIDE R14, R3, R6, c[0x0][0x178] ; /* 0x00005e00030e7625 */
/* 0x000fc800078e0206 */
/*0180*/ IMAD.WIDE R16, R0, R6, c[0x0][0x170] ; /* 0x00005c0000107625 */
/* 0x000fe400078e0206 */
/*0190*/ @!P0 BRA 0xa10 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x720 ; /* 0x0000055000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x0000a8000c1e1900 */
/*01f0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x0002a2000c1e1900 */
/*0200*/ IMAD.WIDE R22, R6, c[0x0][0x164], R14 ; /* 0x0000590006167a25 */
/* 0x000fc800078e020e */
/*0210*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x160], R16 ; /* 0x00005800061a7a25 */
/* 0x040fe200078e0210 */
/*0220*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000728000c1e1900 */
/*0230*/ LDG.E R24, [R26.64] ; /* 0x000000041a187981 */
/* 0x000b22000c1e1900 */
/*0240*/ IMAD.WIDE R22, R6, c[0x0][0x164], R22 ; /* 0x0000590006167a25 */
/* 0x008fc800078e0216 */
/*0250*/ IMAD.WIDE R26, R6.reuse, c[0x0][0x160], R26 ; /* 0x00005800061a7a25 */
/* 0x060fe200078e021a */
/*0260*/ LDG.E R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000766000c1e1900 */
/*0270*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x164], R22 ; /* 0x00005900060e7a25 */
/* 0x041fe200078e0216 */
/*0280*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000166000c1e1900 */
/*0290*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x160], R26 ; /* 0x00005800060c7a25 */
/* 0x040fe200078e021a */
/*02a0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x002368000c1e1900 */
/*02b0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000162000c1e1900 */
/*02c0*/ IMAD.WIDE R28, R6, c[0x0][0x160], R12 ; /* 0x00005800061c7a25 */
/* 0x000fc800078e020c */
/*02d0*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x164], R14 ; /* 0x00005900060e7a25 */
/* 0x042fe200078e020e */
/*02e0*/ LDG.E R17, [R28.64] ; /* 0x000000041c117981 */
/* 0x000368000c1e1900 */
/*02f0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x008762000c1e1900 */
/*0300*/ IMAD.WIDE R26, R6, c[0x0][0x164], R14 ; /* 0x00005900061a7a25 */
/* 0x001fc800078e020e */
/*0310*/ IMAD.WIDE R28, R6.reuse, c[0x0][0x160], R28 ; /* 0x00005800061c7a25 */
/* 0x042fe200078e021c */
/*0320*/ LDG.E R23, [R26.64] ; /* 0x000000041a177981 */
/* 0x00016a000c1e1900 */
/*0330*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x160], R28 ; /* 0x00005800060c7a25 */
/* 0x040fe400078e021c */
/*0340*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000564000c1e1900 */
/*0350*/ IMAD.WIDE R26, R6, c[0x0][0x164], R26 ; /* 0x00005900061a7a25 */
/* 0x001fc400078e021a */
/*0360*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x000168000c1e1900 */
/*0370*/ LDG.E R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x000362000c1e1900 */
/*0380*/ IMAD.WIDE R14, R6, c[0x0][0x164], R26 ; /* 0x00005900060e7a25 */
/* 0x008fc800078e021a */
/*0390*/ IMAD.WIDE R12, R6, c[0x0][0x160], R12 ; /* 0x00005800060c7a25 */
/* 0x001fc800078e020c */
/*03a0*/ FFMA R29, R20, R9, R10 ; /* 0x00000009141d7223 */
/* 0x004fe4000000000a */
/*03b0*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x0000a8000c1e1900 */
/*03c0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x0006a2000c1e1900 */
/*03d0*/ IMAD.WIDE R20, R6, c[0x0][0x160], R12 ; /* 0x0000580006147a25 */
/* 0x000fc800078e020c */
/*03e0*/ FFMA R29, R11, R24, R29 ; /* 0x000000180b1d7223 */
/* 0x010fe4000000001d */
/*03f0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0008a2000c1e1900 */
/*0400*/ IMAD.WIDE R14, R6, c[0x0][0x164], R14 ; /* 0x00005900060e7a25 */
/* 0x008fca00078e020e */
/*0410*/ LDG.E R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x0006a2000c1e1900 */
/*0420*/ IMAD.WIDE R26, R6, c[0x0][0x160], R20 ; /* 0x00005800061a7a25 */
/* 0x002fc800078e0214 */
/*0430*/ FFMA R29, R19, R18, R29 ; /* 0x00000012131d7223 */
/* 0x020fe4000000001d */
/*0440*/ IMAD.WIDE R18, R6, c[0x0][0x164], R14 ; /* 0x0000590006127a25 */
/* 0x000fc800078e020e */
/*0450*/ FFMA R16, R16, R25, R29 ; /* 0x0000001910107223 */
/* 0x000fe4000000001d */
/*0460*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000362000c1e1900 */
/*0470*/ IMAD.WIDE R12, R6, c[0x0][0x160], R26 ; /* 0x00005800060c7a25 */
/* 0x001fc600078e021a */
/*0480*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000162000c1e1900 */
/*0490*/ IMAD.WIDE R18, R6, c[0x0][0x164], R18 ; /* 0x0000590006127a25 */
/* 0x002fc800078e0212 */
/*04a0*/ FFMA R22, R22, R17, R16 ; /* 0x0000001116167223 */
/* 0x000fe20000000010 */
/*04b0*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x001162000c1e1900 */
/*04c0*/ IMAD.WIDE R14, R6, c[0x0][0x160], R12 ; /* 0x00005800060e7a25 */
/* 0x008fc600078e020c */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x0004e2000c1e1900 */
/*04e0*/ IMAD.WIDE R16, R6, c[0x0][0x164], R18 ; /* 0x0000590006107a25 */
/* 0x000fc600078e0212 */
/*04f0*/ LDG.E R29, [R14.64] ; /* 0x000000040e1d7981 */
/* 0x0002e2000c1e1900 */
/*0500*/ FFMA R28, R23, R28, R22 ; /* 0x0000001c171c7223 */
/* 0x000fe40000000016 */
/*0510*/ IMAD.WIDE R20, R6, c[0x0][0x160], R14 ; /* 0x0000580006147a25 */
/* 0x010fc800078e020e */
/*0520*/ IMAD.WIDE R22, R6, c[0x0][0x164], R16 ; /* 0x0000590006167a25 */
/* 0x000fe400078e0210 */
/*0530*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008e4000c1e1900 */
/*0540*/ FFMA R8, R8, R7, R28 ; /* 0x0000000708087223 */
/* 0x000fe4000000001c */
/*0550*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x160], R20 ; /* 0x00005800060e7a25 */
/* 0x042fe200078e0214 */
/*0560*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x0002e6000c1e1900 */
/*0570*/ IMAD.WIDE R18, R6, c[0x0][0x164], R22 ; /* 0x0000590006127a25 */
/* 0x001fe200078e0216 */
/*0580*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee6000c1e1900 */
/*0590*/ FFMA R13, R10, R9, R8 ; /* 0x000000090a0d7223 */
/* 0x004fc40000000008 */
/*05a0*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0000a2000c1e1900 */
/*05b0*/ IMAD.WIDE R8, R6, c[0x0][0x160], R14 ; /* 0x0000580006087a25 */
/* 0x000fc600078e020e */
/*05c0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x0108a2000c1e1900 */
/*05e0*/ IMAD.WIDE R18, R6, c[0x0][0x164], R18 ; /* 0x0000590006127a25 */
/* 0x001fca00078e0212 */
/*05f0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IMAD.WIDE R22, R6, c[0x0][0x164], R18 ; /* 0x0000590006167a25 */
/* 0x002fc800078e0212 */
/*0610*/ IMAD.WIDE R8, R6, c[0x0][0x160], R8 ; /* 0x0000580006087a25 */
/* 0x010fc800078e0208 */
/*0620*/ FFMA R13, R11, R24, R13 ; /* 0x000000180b0d7223 */
/* 0x000fe4000000000d */
/*0630*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000f28000c1e1900 */
/*0640*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000f22000c1e1900 */
/*0650*/ FFMA R13, R25, R26, R13 ; /* 0x0000001a190d7223 */
/* 0x020fe2000000000d */
/*0660*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0680*/ FFMA R12, R27, R12, R13 ; /* 0x0000000c1b0c7223 */
/* 0x008fc8000000000d */
/*0690*/ FFMA R12, R16, R29, R12 ; /* 0x0000001d100c7223 */
/* 0x000fc8000000000c */
/*06a0*/ FFMA R7, R7, R20, R12 ; /* 0x0000001407077223 */
/* 0x000fe2000000000c */
/*06b0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*06c0*/ FFMA R7, R10, R15, R7 ; /* 0x0000000f0a077223 */
/* 0x004fe40000000007 */
/*06d0*/ IMAD.WIDE R14, R6, c[0x0][0x164], R22 ; /* 0x00005900060e7a25 */
/* 0x000fc800078e0216 */
/*06e0*/ FFMA R7, R28, R17, R7 ; /* 0x000000111c077223 */
/* 0x000fe40000000007 */
/*06f0*/ IMAD.WIDE R16, R6, c[0x0][0x160], R8 ; /* 0x0000580006107a25 */
/* 0x000fc800078e0208 */
/*0700*/ FFMA R10, R11, R24, R7 ; /* 0x000000180b0a7223 */
/* 0x010fe20000000007 */
/*0710*/ @P1 BRA 0x1e0 ; /* 0xfffffac000001947 */
/* 0x000fea000383ffff */
/*0720*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0730*/ @!P1 BRA 0x9f0 ; /* 0x000002b000009947 */
/* 0x000fea0003800000 */
/*0740*/ LDG.E R27, [R14.64] ; /* 0x000000040e1b7981 */
/* 0x0000a8000c1e1900 */
/*0750*/ LDG.E R28, [R16.64] ; /* 0x00000004101c7981 */
/* 0x0002a2000c1e1900 */
/*0760*/ IMAD.WIDE R8, R6, c[0x0][0x160], R16 ; /* 0x0000580006087a25 */
/* 0x000fc800078e0210 */
/*0770*/ IMAD.WIDE R12, R6, c[0x0][0x164], R14 ; /* 0x00005900060c7a25 */
/* 0x000fc800078e020e */
/*0780*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x160], R8 ; /* 0x00005800060e7a25 */
/* 0x041fe200078e0208 */
/*0790*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x0000e6000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x164], R12 ; /* 0x0000590006127a25 */
/* 0x040fe200078e020c */
/*07b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0008e6000c1e1900 */
/*07c0*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x160], R14 ; /* 0x0000580006107a25 */
/* 0x042fe200078e020e */
/*07d0*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000366000c1e1900 */
/*07e0*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x164], R18 ; /* 0x0000590006147a25 */
/* 0x040fe200078e0212 */
/*07f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000366000c1e1900 */
/*0800*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x160], R16 ; /* 0x00005800060c7a25 */
/* 0x041fe200078e0210 */
/*0810*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000166000c1e1900 */
/*0820*/ IMAD.WIDE R22, R6, c[0x0][0x164], R20 ; /* 0x0000590006167a25 */
/* 0x000fc400078e0214 */
/*0830*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000964000c1e1900 */
/*0840*/ IMAD.WIDE R14, R6.reuse, c[0x0][0x160], R12 ; /* 0x00005800060e7a25 */
/* 0x042fe400078e020c */
/*0850*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x000364000c1e1900 */
/*0860*/ IMAD.WIDE R16, R6.reuse, c[0x0][0x164], R22 ; /* 0x0000590006107a25 */
/* 0x041fe400078e0216 */
/*0870*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x010128000c1e1900 */
/*0880*/ IMAD.WIDE R18, R6.reuse, c[0x0][0x164], R16 ; /* 0x0000590006127a25 */
/* 0x040fe200078e0210 */
/*0890*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000326000c1e1900 */
/*08a0*/ IMAD.WIDE R12, R6, c[0x0][0x160], R14 ; /* 0x00005800060c7a25 */
/* 0x001fc400078e020e */
/*08b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*08c0*/ LDG.E R16, [R18.64] ; /* 0x0000000412107981 */
/* 0x002122000c1e1900 */
/*08d0*/ IMAD.WIDE R22, R6, c[0x0][0x160], R12 ; /* 0x0000580006167a25 */
/* 0x000fc600078e020c */
/*08e0*/ LDG.E R29, [R12.64] ; /* 0x000000040c1d7981 */
/* 0x000f22000c1e1900 */
/*08f0*/ IMAD.WIDE R18, R6, c[0x0][0x164], R18 ; /* 0x0000590006127a25 */
/* 0x001fc800078e0212 */
/*0900*/ FFMA R28, R27, R28, R10 ; /* 0x0000001c1b1c7223 */
/* 0x004fe4000000000a */
/*0910*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x000ea8000c1e1900 */
/*0920*/ LDG.E R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x000ea2000c1e1900 */
/*0930*/ FFMA R7, R7, R8, R28 ; /* 0x0000000807077223 */
/* 0x008fc8000000001c */
/*0940*/ FFMA R7, R25, R26, R7 ; /* 0x0000001a19077223 */
/* 0x020fc80000000007 */
/*0950*/ FFMA R7, R21, R24, R7 ; /* 0x0000001815077223 */
/* 0x000fc80000000007 */
/*0960*/ FFMA R7, R11, R20, R7 ; /* 0x000000140b077223 */
/* 0x010fe20000000007 */
/*0970*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0980*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0990*/ FFMA R7, R9, R14, R7 ; /* 0x0000000e09077223 */
/* 0x000fe20000000007 */
/*09a0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*09b0*/ IMAD.WIDE R14, R6, c[0x0][0x164], R18 ; /* 0x00005900060e7a25 */
/* 0x000fc800078e0212 */
/*09c0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fe40000000007 */
/*09d0*/ IMAD.WIDE R16, R6, c[0x0][0x160], R22 ; /* 0x0000580006107a25 */
/* 0x000fc800078e0216 */
/*09e0*/ FFMA R10, R10, R27, R7 ; /* 0x0000001b0a0a7223 */
/* 0x004fe40000000007 */
/*09f0*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0a00*/ @!P0 BRA 0xb90 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD.WIDE R8, R6.reuse, c[0x0][0x160], R16 ; /* 0x0000580006087a25 */
/* 0x040fe400078e0210 */
/*0a20*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1900 */
/*0a30*/ IMAD.WIDE R12, R6.reuse, c[0x0][0x164], R14 ; /* 0x00005900060c7a25 */
/* 0x040fe400078e020e */
/*0a40*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x0000a4000c1e1900 */
/*0a50*/ IMAD.WIDE R22, R6.reuse, c[0x0][0x160], R8 ; /* 0x0000580006167a25 */
/* 0x040fe400078e0208 */
/*0a60*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1900 */
/*0a70*/ IMAD.WIDE R18, R6, c[0x0][0x164], R12 ; /* 0x0000590006127a25 */
/* 0x000fc400078e020c */
/*0a80*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee4000c1e1900 */
/*0a90*/ IMAD.WIDE R20, R6.reuse, c[0x0][0x160], R22 ; /* 0x0000580006147a25 */
/* 0x040fe400078e0216 */
/*0aa0*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x000f24000c1e1900 */
/*0ab0*/ IMAD.WIDE R24, R6, c[0x0][0x164], R18 ; /* 0x0000590006187a25 */
/* 0x000fe400078e0212 */
/*0ac0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000f28000c1e1900 */
/*0ad0*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000f68000c1e1900 */
/*0ae0*/ LDG.E R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x001f62000c1e1900 */
/*0af0*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0b10*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007ffe0ff */
/*0b20*/ FFMA R15, R15, R16, R10 ; /* 0x000000100f0f7223 */
/* 0x004fc8000000000a */
/*0b30*/ FFMA R15, R12, R8, R15 ; /* 0x000000080c0f7223 */
/* 0x008fe4000000000f */
/*0b40*/ IMAD.WIDE R16, R6, c[0x0][0x160], R20 ; /* 0x0000580006107a25 */
/* 0x000fc800078e0214 */
/*0b50*/ FFMA R7, R26, R7, R15 ; /* 0x000000071a077223 */
/* 0x010fc8000000000f */
/*0b60*/ FFMA R10, R14, R11, R7 ; /* 0x0000000b0e0a7223 */
/* 0x020fe40000000007 */
/*0b70*/ IMAD.WIDE R14, R6, c[0x0][0x164], R24 ; /* 0x00005900060e7a25 */
/* 0x000fe200078e0218 */
/*0b80*/ @P0 BRA 0xa10 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0b90*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0ba0*/ @!P0 BRA 0xc80 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0bb0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0bc0*/ IMAD R5, R4.reuse, c[0x0][0x164], R3 ; /* 0x0000590004057a24 */
/* 0x040fe400078e0203 */
/*0bd0*/ IMAD R6, R4, c[0x0][0x160], R0 ; /* 0x0000580004067a24 */
/* 0x000fce00078e0200 */
/*0be0*/ IMAD.WIDE R4, R5, R11, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fc800078e020b */
/*0bf0*/ IMAD.WIDE R6, R6, R11, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e020b */
/*0c00*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x0000a8000c1e1900 */
/*0c10*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0002a2000c1e1900 */
/*0c20*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0c30*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0c40*/ IMAD.WIDE R4, R11, c[0x0][0x164], R4 ; /* 0x000059000b047a25 */
/* 0x001fc800078e0204 */
/*0c50*/ IMAD.WIDE R6, R11, c[0x0][0x160], R6 ; /* 0x000058000b067a25 */
/* 0x002fc800078e0206 */
/*0c60*/ FFMA R10, R9, R8, R10 ; /* 0x00000008090a7223 */
/* 0x004fc8000000000a */
/*0c70*/ @P0 BRA 0xc00 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0c80*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c90*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fc800078e0200 */
/*0ca0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x000fca00078e0202 */
/*0cb0*/ STG.E [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe2000c101904 */
/*0cc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gemm_reference
.globl gemm_reference
.p2align 8
.type gemm_reference,@function
gemm_reference:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b32 s8, s[0:1], 0x4
s_load_b128 s[4:7], s[0:1], 0x10
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, v0
v_mov_b32_e32 v4, v1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, s8, v4
v_add_nc_u32_e32 v2, s2, v2
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel gemm_reference
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size gemm_reference, .Lfunc_end0-gemm_reference
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: gemm_reference
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: gemm_reference.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001705c2_00000000-6_ClTuneGemmReference.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf
.type _Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf, @function
_Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq gemm_reference(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf, .-_Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf
.globl gemm_reference
.type gemm_reference, @function
gemm_reference:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z14gemm_referenceiiiPKfS0_PfiiiPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size gemm_reference, .-gemm_reference
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gemm_reference"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gemm_reference(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ClTuneGemmReference.hip"
.globl __device_stub__gemm_reference # -- Begin function __device_stub__gemm_reference
.p2align 4, 0x90
.type __device_stub__gemm_reference,@function
__device_stub__gemm_reference: # @__device_stub__gemm_reference
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $gemm_reference, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__gemm_reference, .Lfunc_end0-__device_stub__gemm_reference
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gemm_reference, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gemm_reference,@object # @gemm_reference
.section .rodata,"a",@progbits
.globl gemm_reference
.p2align 3, 0x0
gemm_reference:
.quad __device_stub__gemm_reference
.size gemm_reference, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gemm_reference"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gemm_reference
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gemm_reference
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cstdlib>
#include <cuda_runtime_api.h>
int main(int argc, char *argv[]) {
cudaDeviceProp prop;
cudaError_t status;
int device_count;
int device_index = 0;
if (argc > 1) {
device_index = atoi(argv[1]);
}
status = cudaGetDeviceCount(&device_count);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", cudaGetErrorString(status));
return -1;
}
if (device_index >= device_count) {
fprintf(stderr, "Specified device index %d exceeds the maximum (the device count on this system is %d)\n", device_index, device_count);
return -1;
}
status = cudaGetDeviceProperties(&prop, device_index);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device device_index failed: %s\n", cudaGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
printf("%d\n", v);
printf("%d\n", prop.multiProcessorCount);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstdlib>
#include <cuda_runtime_api.h>
int main(int argc, char *argv[]) {
cudaDeviceProp prop;
cudaError_t status;
int device_count;
int device_index = 0;
if (argc > 1) {
device_index = atoi(argv[1]);
}
status = cudaGetDeviceCount(&device_count);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", cudaGetErrorString(status));
return -1;
}
if (device_index >= device_count) {
fprintf(stderr, "Specified device index %d exceeds the maximum (the device count on this system is %d)\n", device_index, device_count);
return -1;
}
status = cudaGetDeviceProperties(&prop, device_index);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device device_index failed: %s\n", cudaGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
printf("%d\n", v);
printf("%d\n", prop.multiProcessorCount);
} | .file "tmpxft_0016efc9_00000000-6_obtain_gpu_cc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaGetDeviceCount() failed: %s\n"
.align 8
.LC1:
.string "Specified device index %d exceeds the maximum (the device count on this system is %d)\n"
.align 8
.LC2:
.string "cudaGetDeviceProperties() for device device_index failed: %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1056, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, %ebx
cmpl $1, %edi
jg .L12
.L4:
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L13
movl 12(%rsp), %r8d
cmpl %ebx, %r8d
jle .L14
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L15
movl 376(%rsp), %eax
leal (%rax,%rax,4), %edx
movl 380(%rsp), %eax
leal (%rax,%rdx,2), %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L16
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L4
.L13:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L3
.L14:
movl %ebx, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L3
.L15:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L3
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstdlib>
#include <cuda_runtime_api.h>
int main(int argc, char *argv[]) {
cudaDeviceProp prop;
cudaError_t status;
int device_count;
int device_index = 0;
if (argc > 1) {
device_index = atoi(argv[1]);
}
status = cudaGetDeviceCount(&device_count);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", cudaGetErrorString(status));
return -1;
}
if (device_index >= device_count) {
fprintf(stderr, "Specified device index %d exceeds the maximum (the device count on this system is %d)\n", device_index, device_count);
return -1;
}
status = cudaGetDeviceProperties(&prop, device_index);
if (status != cudaSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device device_index failed: %s\n", cudaGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
printf("%d\n", v);
printf("%d\n", prop.multiProcessorCount);
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime_api.h>
int main(int argc, char *argv[]) {
hipDeviceProp_t prop;
hipError_t status;
int device_count;
int device_index = 0;
if (argc > 1) {
device_index = atoi(argv[1]);
}
status = hipGetDeviceCount(&device_count);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", hipGetErrorString(status));
return -1;
}
if (device_index >= device_count) {
fprintf(stderr, "Specified device index %d exceeds the maximum (the device count on this system is %d)\n", device_index, device_count);
return -1;
}
status = hipGetDeviceProperties(&prop, device_index);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device device_index failed: %s\n", hipGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
printf("%d\n", v);
printf("%d\n", prop.multiProcessorCount);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime_api.h>
int main(int argc, char *argv[]) {
hipDeviceProp_t prop;
hipError_t status;
int device_count;
int device_index = 0;
if (argc > 1) {
device_index = atoi(argv[1]);
}
status = hipGetDeviceCount(&device_count);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", hipGetErrorString(status));
return -1;
}
if (device_index >= device_count) {
fprintf(stderr, "Specified device index %d exceeds the maximum (the device count on this system is %d)\n", device_index, device_count);
return -1;
}
status = hipGetDeviceProperties(&prop, device_index);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device device_index failed: %s\n", hipGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
printf("%d\n", v);
printf("%d\n", prop.multiProcessorCount);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <hip/hip_runtime_api.h>
int main(int argc, char *argv[]) {
hipDeviceProp_t prop;
hipError_t status;
int device_count;
int device_index = 0;
if (argc > 1) {
device_index = atoi(argv[1]);
}
status = hipGetDeviceCount(&device_count);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceCount() failed: %s\n", hipGetErrorString(status));
return -1;
}
if (device_index >= device_count) {
fprintf(stderr, "Specified device index %d exceeds the maximum (the device count on this system is %d)\n", device_index, device_count);
return -1;
}
status = hipGetDeviceProperties(&prop, device_index);
if (status != hipSuccess) {
fprintf(stderr,"cudaGetDeviceProperties() for device device_index failed: %s\n", hipGetErrorString(status));
return -1;
}
int v = prop.major * 10 + prop.minor;
printf("%d\n", v);
printf("%d\n", prop.multiProcessorCount);
} | .text
.file "obtain_gpu_cc.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
xorl %ebx, %ebx
cmpl $2, %edi
jl .LBB0_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB0_2:
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_3
# %bb.5:
movl 12(%rsp), %ecx
cmpl %ecx, %ebx
jge .LBB0_6
# %bb.7:
leaq 16(%rsp), %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_8
# %bb.9:
movl 376(%rsp), %eax
leal (%rax,%rax,4), %esi
addl %esi, %esi
addl 380(%rsp), %esi
xorl %ebx, %ebx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 404(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
.LBB0_10:
movl %ebx, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 1504
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB0_4
.LBB0_6:
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
movl %ebx, %edx
xorl %eax, %eax
callq fprintf
movl $-1, %ebx
jmp .LBB0_10
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
.LBB0_4:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %ebx
jmp .LBB0_10
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaGetDeviceCount() failed: %s\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Specified device index %d exceeds the maximum (the device count on this system is %d)\n"
.size .L.str.1, 87
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaGetDeviceProperties() for device device_index failed: %s\n"
.size .L.str.2, 62
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016efc9_00000000-6_obtain_gpu_cc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaGetDeviceCount() failed: %s\n"
.align 8
.LC1:
.string "Specified device index %d exceeds the maximum (the device count on this system is %d)\n"
.align 8
.LC2:
.string "cudaGetDeviceProperties() for device device_index failed: %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1056, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, %ebx
cmpl $1, %edi
jg .L12
.L4:
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L13
movl 12(%rsp), %r8d
cmpl %ebx, %r8d
jle .L14
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L15
movl 376(%rsp), %eax
leal (%rax,%rax,4), %edx
movl 380(%rsp), %eax
leal (%rax,%rdx,2), %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L16
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L4
.L13:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L3
.L14:
movl %ebx, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L3
.L15:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L3
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "obtain_gpu_cc.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
xorl %ebx, %ebx
cmpl $2, %edi
jl .LBB0_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB0_2:
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_3
# %bb.5:
movl 12(%rsp), %ecx
cmpl %ecx, %ebx
jge .LBB0_6
# %bb.7:
leaq 16(%rsp), %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_8
# %bb.9:
movl 376(%rsp), %eax
leal (%rax,%rax,4), %esi
addl %esi, %esi
addl 380(%rsp), %esi
xorl %ebx, %ebx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 404(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
.LBB0_10:
movl %ebx, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 1504
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB0_4
.LBB0_6:
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
movl %ebx, %edx
xorl %eax, %eax
callq fprintf
movl $-1, %ebx
jmp .LBB0_10
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
.LBB0_4:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $-1, %ebx
jmp .LBB0_10
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaGetDeviceCount() failed: %s\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Specified device index %d exceeds the maximum (the device count on this system is %d)\n"
.size .L.str.1, 87
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaGetDeviceProperties() for device device_index failed: %s\n"
.size .L.str.2, 62
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void scatter(unsigned int *d_inVals, unsigned int *d_outVals, unsigned int *d_inPos, unsigned int *d_outPos, unsigned int *d_zerosScan, unsigned int *d_onesScan, unsigned int *d_zerosPredicate, unsigned int *d_onesPredicate, size_t n)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
int offset = d_zerosScan[n - 1] + d_zerosPredicate[n - 1];
if(index < n) {
int scatterIdx;
if(d_zerosPredicate[index]) {
scatterIdx = d_zerosScan[index];
} else {
scatterIdx = d_onesScan[index] + offset;
}
if(scatterIdx < n) { //sanity check
d_outVals[scatterIdx] = d_inVals[index];
d_outPos[scatterIdx] = d_inPos[index];
}
}
} | code for sm_80
Function : _Z7scatterPjS_S_S_S_S_S_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, 0x4, R3 ; /* 0x0000000400007824 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x1a0], PT ; /* 0x0000680000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x1a4], PT, P0 ; /* 0x0000690003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R12, R0.reuse, 0x4, RZ ; /* 0x00000004000c7824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x2, R3 ; /* 0x0000000200007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R2, P0, R12, c[0x0][0x190], RZ ; /* 0x000064000c027a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R3, R0, c[0x0][0x194], RZ, P0, !PT ; /* 0x0000650000037a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*00f0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff0b8624 */
/* 0x000fe200078e00ff */
/*0100*/ @P0 IADD3 R4, P2, R12.reuse, c[0x0][0x180], RZ ; /* 0x000060000c040a10 */
/* 0x040fe20007f5e0ff */
/*0110*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x2 ; /* 0x00000002ff068424 */
/* 0x000fe200078e00ff */
/*0120*/ @!P0 IADD3 R8, P1, R12, c[0x0][0x188], RZ ; /* 0x000062000c088a10 */
/* 0x000fe20007f3e0ff */
/*0130*/ @!P0 IMAD.SHL.U32 R7, R11.reuse, 0x4, RZ ; /* 0x000000040b078824 */
/* 0x040fe200078e00ff */
/*0140*/ @P0 IADD3.X R5, R0.reuse, c[0x0][0x184], RZ, P2, !PT ; /* 0x0000610000050a10 */
/* 0x040fe400017fe4ff */
/*0150*/ @!P0 IADD3.X R9, R0, c[0x0][0x18c], RZ, P1, !PT ; /* 0x0000630000098a10 */
/* 0x000fe40000ffe4ff */
/*0160*/ @!P0 SHF.L.U64.HI R11, R11, R6, c[0x0][0x1a4] ; /* 0x000069000b0b8619 */
/* 0x000fe20000010206 */
/*0170*/ @P0 LDG.E R10, [R4.64] ; /* 0x00000004040a0981 */
/* 0x000ea2000c1e1900 */
/*0180*/ @!P0 IADD3 R2, P1, R7, c[0x0][0x180], RZ ; /* 0x0000600007028a10 */
/* 0x000fc40007f3e0ff */
/*0190*/ @!P0 IADD3 R6, P2, R7, c[0x0][0x190], RZ ; /* 0x0000640007068a10 */
/* 0x000fe20007f5e0ff */
/*01a0*/ @!P0 LDG.E R8, [R8.64] ; /* 0x0000000408088981 */
/* 0x000ee2000c1e1900 */
/*01b0*/ @!P0 IADD3.X R3, R11.reuse, c[0x0][0x184], RZ, P1, !PT ; /* 0x000061000b038a10 */
/* 0x040fe40000ffe4ff */
/*01c0*/ @!P0 IADD3.X R7, R11, c[0x0][0x194], RZ, P2, !PT ; /* 0x000065000b078a10 */
/* 0x000fc800017fe4ff */
/*01d0*/ @!P0 LDG.E R3, [R2.64+-0x4] ; /* 0xfffffc0402038981 */
/* 0x000ee8000c1e1900 */
/*01e0*/ @!P0 LDG.E R6, [R6.64+-0x4] ; /* 0xfffffc0406068981 */
/* 0x000ee4000c1e1900 */
/*01f0*/ @!P0 IADD3 R10, R8, R6, R3 ; /* 0x00000006080a8210 */
/* 0x008fc80007ffe003 */
/*0200*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x1a0], PT ; /* 0x000068000a007a0c */
/* 0x004fe40003f06070 */
/*0210*/ SHF.R.S32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fc8000001140a */
/*0220*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x1a4], PT, P0 ; /* 0x000069000b007a0c */
/* 0x000fda0003f06100 */
/*0230*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R2, P0, R12, c[0x0][0x160], RZ ; /* 0x000058000c027a10 */
/* 0x000fc80007f1e0ff */
/*0250*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fcc00007fe4ff */
/*0260*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.SHL.U32 R8, R10.reuse, 0x4, RZ ; /* 0x000000040a087824 */
/* 0x040fe200078e00ff */
/*0280*/ SHF.L.U64.HI R10, R10, 0x2, R11 ; /* 0x000000020a0a7819 */
/* 0x000fe4000001020b */
/*0290*/ IADD3 R6, P1, R12, c[0x0][0x170], RZ ; /* 0x00005c000c067a10 */
/* 0x000fe40007f3e0ff */
/*02a0*/ IADD3 R4, P0, R8, c[0x0][0x168], RZ ; /* 0x00005a0008047a10 */
/* 0x000fe40007f1e0ff */
/*02b0*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000077a10 */
/* 0x000fe40000ffe4ff */
/*02c0*/ IADD3.X R5, R10, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000a057a10 */
/* 0x000fca00007fe4ff */
/*02d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe8000c101904 */
/*02e0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IADD3 R8, P0, R8, c[0x0][0x178], RZ ; /* 0x00005e0008087a10 */
/* 0x000fc80007f1e0ff */
/*0300*/ IADD3.X R9, R10, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000a097a10 */
/* 0x000fca00007fe4ff */
/*0310*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void scatter(unsigned int *d_inVals, unsigned int *d_outVals, unsigned int *d_inPos, unsigned int *d_outPos, unsigned int *d_zerosScan, unsigned int *d_onesScan, unsigned int *d_zerosPredicate, unsigned int *d_onesPredicate, size_t n)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
int offset = d_zerosScan[n - 1] + d_zerosPredicate[n - 1];
if(index < n) {
int scatterIdx;
if(d_zerosPredicate[index]) {
scatterIdx = d_zerosScan[index];
} else {
scatterIdx = d_onesScan[index] + offset;
}
if(scatterIdx < n) { //sanity check
d_outVals[scatterIdx] = d_inVals[index];
d_outPos[scatterIdx] = d_inPos[index];
}
}
} | .file "tmpxft_00017bb9_00000000-6_scatter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m
.type _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m, @function
_Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq 232(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7scatterPjS_S_S_S_S_S_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m, .-_Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m
.globl _Z7scatterPjS_S_S_S_S_S_S_m
.type _Z7scatterPjS_S_S_S_S_S_S_m, @function
_Z7scatterPjS_S_S_S_S_S_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7scatterPjS_S_S_S_S_S_S_m, .-_Z7scatterPjS_S_S_S_S_S_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7scatterPjS_S_S_S_S_S_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7scatterPjS_S_S_S_S_S_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void scatter(unsigned int *d_inVals, unsigned int *d_outVals, unsigned int *d_inPos, unsigned int *d_outPos, unsigned int *d_zerosScan, unsigned int *d_onesScan, unsigned int *d_zerosPredicate, unsigned int *d_onesPredicate, size_t n)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
int offset = d_zerosScan[n - 1] + d_zerosPredicate[n - 1];
if(index < n) {
int scatterIdx;
if(d_zerosPredicate[index]) {
scatterIdx = d_zerosScan[index];
} else {
scatterIdx = d_onesScan[index] + offset;
}
if(scatterIdx < n) { //sanity check
d_outVals[scatterIdx] = d_inVals[index];
d_outPos[scatterIdx] = d_inPos[index];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scatter(unsigned int *d_inVals, unsigned int *d_outVals, unsigned int *d_inPos, unsigned int *d_outPos, unsigned int *d_zerosScan, unsigned int *d_onesScan, unsigned int *d_zerosPredicate, unsigned int *d_onesPredicate, size_t n)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
int offset = d_zerosScan[n - 1] + d_zerosPredicate[n - 1];
if(index < n) {
int scatterIdx;
if(d_zerosPredicate[index]) {
scatterIdx = d_zerosScan[index];
} else {
scatterIdx = d_onesScan[index] + offset;
}
if(scatterIdx < n) { //sanity check
d_outVals[scatterIdx] = d_inVals[index];
d_outPos[scatterIdx] = d_inPos[index];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scatter(unsigned int *d_inVals, unsigned int *d_outVals, unsigned int *d_inPos, unsigned int *d_outPos, unsigned int *d_zerosScan, unsigned int *d_onesScan, unsigned int *d_zerosPredicate, unsigned int *d_onesPredicate, size_t n)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
int offset = d_zerosScan[n - 1] + d_zerosPredicate[n - 1];
if(index < n) {
int scatterIdx;
if(d_zerosPredicate[index]) {
scatterIdx = d_zerosScan[index];
} else {
scatterIdx = d_onesScan[index] + offset;
}
if(scatterIdx < n) { //sanity check
d_outVals[scatterIdx] = d_inVals[index];
d_outPos[scatterIdx] = d_inPos[index];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7scatterPjS_S_S_S_S_S_S_m
.globl _Z7scatterPjS_S_S_S_S_S_S_m
.p2align 8
.type _Z7scatterPjS_S_S_S_S_S_S_m,@function
_Z7scatterPjS_S_S_S_S_S_S_m:
s_load_b64 s[2:3], s[0:1], 0x40
v_lshl_add_u32 v0, s15, 2, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[2:3], v[0:1]
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x30
s_load_b64 s[6:7], s[0:1], 0x20
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_saveexec_b32 s8, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB0_3:
s_and_not1_saveexec_b32 s8, s8
s_cbranch_execz .LBB0_5
s_load_b64 s[10:11], s[0:1], 0x28
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_lshl_b64 s[10:11], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s9, s10, -4
global_load_b32 v2, v[2:3], off
s_addc_u32 s10, s11, -1
s_add_u32 s6, s6, s9
s_addc_u32 s7, s7, s10
s_add_u32 s4, s4, s9
s_addc_u32 s5, s5, s10
s_load_b32 s6, s[6:7], 0x0
s_load_b32 s4, s[4:5], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add3_u32 v2, s4, s6, v2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b256 s[0:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
global_load_b32 v6, v[4:5], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off
global_load_b32 v4, v[0:1], off
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7scatterPjS_S_S_S_S_S_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7scatterPjS_S_S_S_S_S_S_m, .Lfunc_end0-_Z7scatterPjS_S_S_S_S_S_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7scatterPjS_S_S_S_S_S_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7scatterPjS_S_S_S_S_S_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scatter(unsigned int *d_inVals, unsigned int *d_outVals, unsigned int *d_inPos, unsigned int *d_outPos, unsigned int *d_zerosScan, unsigned int *d_onesScan, unsigned int *d_zerosPredicate, unsigned int *d_onesPredicate, size_t n)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int index = BLOCK_WIDTH * bx + tx;
int offset = d_zerosScan[n - 1] + d_zerosPredicate[n - 1];
if(index < n) {
int scatterIdx;
if(d_zerosPredicate[index]) {
scatterIdx = d_zerosScan[index];
} else {
scatterIdx = d_onesScan[index] + offset;
}
if(scatterIdx < n) { //sanity check
d_outVals[scatterIdx] = d_inVals[index];
d_outPos[scatterIdx] = d_inPos[index];
}
}
} | .text
.file "scatter.hip"
.globl _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m # -- Begin function _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.p2align 4, 0x90
.type _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m,@function
_Z22__device_stub__scatterPjS_S_S_S_S_S_S_m: # @_Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7scatterPjS_S_S_S_S_S_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m, .Lfunc_end0-_Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7scatterPjS_S_S_S_S_S_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7scatterPjS_S_S_S_S_S_S_m,@object # @_Z7scatterPjS_S_S_S_S_S_S_m
.section .rodata,"a",@progbits
.globl _Z7scatterPjS_S_S_S_S_S_S_m
.p2align 3, 0x0
_Z7scatterPjS_S_S_S_S_S_S_m:
.quad _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.size _Z7scatterPjS_S_S_S_S_S_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7scatterPjS_S_S_S_S_S_S_m"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7scatterPjS_S_S_S_S_S_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7scatterPjS_S_S_S_S_S_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, 0x4, R3 ; /* 0x0000000400007824 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x1a0], PT ; /* 0x0000680000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x1a4], PT, P0 ; /* 0x0000690003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R12, R0.reuse, 0x4, RZ ; /* 0x00000004000c7824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x2, R3 ; /* 0x0000000200007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R2, P0, R12, c[0x0][0x190], RZ ; /* 0x000064000c027a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ IADD3.X R3, R0, c[0x0][0x194], RZ, P0, !PT ; /* 0x0000650000037a10 */
/* 0x000fca00007fe4ff */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*00f0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff0b8624 */
/* 0x000fe200078e00ff */
/*0100*/ @P0 IADD3 R4, P2, R12.reuse, c[0x0][0x180], RZ ; /* 0x000060000c040a10 */
/* 0x040fe20007f5e0ff */
/*0110*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x2 ; /* 0x00000002ff068424 */
/* 0x000fe200078e00ff */
/*0120*/ @!P0 IADD3 R8, P1, R12, c[0x0][0x188], RZ ; /* 0x000062000c088a10 */
/* 0x000fe20007f3e0ff */
/*0130*/ @!P0 IMAD.SHL.U32 R7, R11.reuse, 0x4, RZ ; /* 0x000000040b078824 */
/* 0x040fe200078e00ff */
/*0140*/ @P0 IADD3.X R5, R0.reuse, c[0x0][0x184], RZ, P2, !PT ; /* 0x0000610000050a10 */
/* 0x040fe400017fe4ff */
/*0150*/ @!P0 IADD3.X R9, R0, c[0x0][0x18c], RZ, P1, !PT ; /* 0x0000630000098a10 */
/* 0x000fe40000ffe4ff */
/*0160*/ @!P0 SHF.L.U64.HI R11, R11, R6, c[0x0][0x1a4] ; /* 0x000069000b0b8619 */
/* 0x000fe20000010206 */
/*0170*/ @P0 LDG.E R10, [R4.64] ; /* 0x00000004040a0981 */
/* 0x000ea2000c1e1900 */
/*0180*/ @!P0 IADD3 R2, P1, R7, c[0x0][0x180], RZ ; /* 0x0000600007028a10 */
/* 0x000fc40007f3e0ff */
/*0190*/ @!P0 IADD3 R6, P2, R7, c[0x0][0x190], RZ ; /* 0x0000640007068a10 */
/* 0x000fe20007f5e0ff */
/*01a0*/ @!P0 LDG.E R8, [R8.64] ; /* 0x0000000408088981 */
/* 0x000ee2000c1e1900 */
/*01b0*/ @!P0 IADD3.X R3, R11.reuse, c[0x0][0x184], RZ, P1, !PT ; /* 0x000061000b038a10 */
/* 0x040fe40000ffe4ff */
/*01c0*/ @!P0 IADD3.X R7, R11, c[0x0][0x194], RZ, P2, !PT ; /* 0x000065000b078a10 */
/* 0x000fc800017fe4ff */
/*01d0*/ @!P0 LDG.E R3, [R2.64+-0x4] ; /* 0xfffffc0402038981 */
/* 0x000ee8000c1e1900 */
/*01e0*/ @!P0 LDG.E R6, [R6.64+-0x4] ; /* 0xfffffc0406068981 */
/* 0x000ee4000c1e1900 */
/*01f0*/ @!P0 IADD3 R10, R8, R6, R3 ; /* 0x00000006080a8210 */
/* 0x008fc80007ffe003 */
/*0200*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x1a0], PT ; /* 0x000068000a007a0c */
/* 0x004fe40003f06070 */
/*0210*/ SHF.R.S32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fc8000001140a */
/*0220*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x1a4], PT, P0 ; /* 0x000069000b007a0c */
/* 0x000fda0003f06100 */
/*0230*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R2, P0, R12, c[0x0][0x160], RZ ; /* 0x000058000c027a10 */
/* 0x000fc80007f1e0ff */
/*0250*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fcc00007fe4ff */
/*0260*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.SHL.U32 R8, R10.reuse, 0x4, RZ ; /* 0x000000040a087824 */
/* 0x040fe200078e00ff */
/*0280*/ SHF.L.U64.HI R10, R10, 0x2, R11 ; /* 0x000000020a0a7819 */
/* 0x000fe4000001020b */
/*0290*/ IADD3 R6, P1, R12, c[0x0][0x170], RZ ; /* 0x00005c000c067a10 */
/* 0x000fe40007f3e0ff */
/*02a0*/ IADD3 R4, P0, R8, c[0x0][0x168], RZ ; /* 0x00005a0008047a10 */
/* 0x000fe40007f1e0ff */
/*02b0*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000077a10 */
/* 0x000fe40000ffe4ff */
/*02c0*/ IADD3.X R5, R10, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000a057a10 */
/* 0x000fca00007fe4ff */
/*02d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe8000c101904 */
/*02e0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IADD3 R8, P0, R8, c[0x0][0x178], RZ ; /* 0x00005e0008087a10 */
/* 0x000fc80007f1e0ff */
/*0300*/ IADD3.X R9, R10, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000a097a10 */
/* 0x000fca00007fe4ff */
/*0310*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7scatterPjS_S_S_S_S_S_S_m
.globl _Z7scatterPjS_S_S_S_S_S_S_m
.p2align 8
.type _Z7scatterPjS_S_S_S_S_S_S_m,@function
_Z7scatterPjS_S_S_S_S_S_S_m:
s_load_b64 s[2:3], s[0:1], 0x40
v_lshl_add_u32 v0, s15, 2, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u64_e64 s[2:3], v[0:1]
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x30
s_load_b64 s[6:7], s[0:1], 0x20
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_saveexec_b32 s8, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB0_3:
s_and_not1_saveexec_b32 s8, s8
s_cbranch_execz .LBB0_5
s_load_b64 s[10:11], s[0:1], 0x28
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_lshl_b64 s[10:11], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s9, s10, -4
global_load_b32 v2, v[2:3], off
s_addc_u32 s10, s11, -1
s_add_u32 s6, s6, s9
s_addc_u32 s7, s7, s10
s_add_u32 s4, s4, s9
s_addc_u32 s5, s5, s10
s_load_b32 s6, s[6:7], 0x0
s_load_b32 s4, s[4:5], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add3_u32 v2, s4, s6, v2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b256 s[0:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
global_load_b32 v6, v[4:5], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off
global_load_b32 v4, v[0:1], off
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7scatterPjS_S_S_S_S_S_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7scatterPjS_S_S_S_S_S_S_m, .Lfunc_end0-_Z7scatterPjS_S_S_S_S_S_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7scatterPjS_S_S_S_S_S_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7scatterPjS_S_S_S_S_S_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017bb9_00000000-6_scatter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m
.type _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m, @function
_Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq 232(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 240(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7scatterPjS_S_S_S_S_S_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m, .-_Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m
.globl _Z7scatterPjS_S_S_S_S_S_S_m
.type _Z7scatterPjS_S_S_S_S_S_S_m, @function
_Z7scatterPjS_S_S_S_S_S_S_m:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z41__device_stub__Z7scatterPjS_S_S_S_S_S_S_mPjS_S_S_S_S_S_S_m
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7scatterPjS_S_S_S_S_S_S_m, .-_Z7scatterPjS_S_S_S_S_S_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7scatterPjS_S_S_S_S_S_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7scatterPjS_S_S_S_S_S_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scatter.hip"
.globl _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m # -- Begin function _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.p2align 4, 0x90
.type _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m,@function
_Z22__device_stub__scatterPjS_S_S_S_S_S_S_m: # @_Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7scatterPjS_S_S_S_S_S_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m, .Lfunc_end0-_Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7scatterPjS_S_S_S_S_S_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7scatterPjS_S_S_S_S_S_S_m,@object # @_Z7scatterPjS_S_S_S_S_S_S_m
.section .rodata,"a",@progbits
.globl _Z7scatterPjS_S_S_S_S_S_S_m
.p2align 3, 0x0
_Z7scatterPjS_S_S_S_S_S_S_m:
.quad _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.size _Z7scatterPjS_S_S_S_S_S_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7scatterPjS_S_S_S_S_S_S_m"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__scatterPjS_S_S_S_S_S_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7scatterPjS_S_S_S_S_S_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__
void matrixMultiplicationKernel(double* A, double* B, double* C, long N) {
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
double tmpSum = 0.0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
}
C[ROW * N + COL] = tmpSum;
} | code for sm_80
Function : matrixMultiplicationKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R27, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff1b7624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0e7624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0060*/ BSSY B0, 0x10d0 ; /* 0x0000106000007945 */
/* 0x000fe20003800000 */
/*0070*/ ISETP.LT.U32.AND P2, PT, R27, 0x1, PT ; /* 0x000000011b00780c */
/* 0x000fe20003f41070 */
/*0080*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0090*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*00a0*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*00b0*/ IMAD R8, R8, c[0x0][0x0], R9 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0209 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fe40003f06070 */
/*00d0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fe20000011408 */
/*00e0*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fc600078e0203 */
/*00f0*/ ISETP.GE.AND.EX P0, PT, R9, c[0x0][0x17c], PT, P0 ; /* 0x00005f0009007a0c */
/* 0x000fe40003f06300 */
/*0100*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f26070 */
/*0110*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0120*/ ISETP.GE.OR.EX P0, PT, R2, c[0x0][0x17c], P0, P1 ; /* 0x00005f0002007a0c */
/* 0x000fc80000706710 */
/*0130*/ ISETP.LT.OR.EX P0, PT, R14, RZ, P0, P2 ; /* 0x000000ff0e00720c */
/* 0x000fda0000701720 */
/*0140*/ @P0 BRA 0x10c0 ; /* 0x00000f7000000947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R3, P1, R27, -0x1, RZ ; /* 0xffffffff1b037810 */
/* 0x000fe20007f3e0ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe4000001ff00 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0190*/ IADD3.X R3, R14, -0x1, RZ, P1, !PT ; /* 0xffffffff0e037810 */
/* 0x000fc80000ffe4ff */
/*01a0*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f06100 */
/*01b0*/ LOP3.LUT R3, R27, 0x3, RZ, 0xc0, !PT ; /* 0x000000031b037812 */
/* 0x000fd600078ec0ff */
/*01c0*/ @!P0 BRA 0xe80 ; /* 0x00000cb000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD R5, R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a24 */
/* 0x000fe200078e02ff */
/*01e0*/ LEA R12, P2, R8, c[0x0][0x168], 0x3 ; /* 0x00005a00080c7a11 */
/* 0x000fe200078418ff */
/*01f0*/ IMAD.WIDE.U32 R6, R0.reuse, c[0x0][0x178], RZ ; /* 0x00005e0000067a25 */
/* 0x040fe200078e00ff */
/*0200*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0210*/ SHF.L.U64.HI R25, R27, 0x3, R14 ; /* 0x000000031b197819 */
/* 0x000fe4000001020e */
/*0220*/ IMAD R11, R0, c[0x0][0x17c], R5 ; /* 0x00005f00000b7a24 */
/* 0x000fe200078e0205 */
/*0230*/ IADD3 R5, P0, R3, -c[0x0][0x178], RZ ; /* 0x80005e0003057a10 */
/* 0x000fe20007f1e0ff */
/*0240*/ IMAD.SHL.U32 R27, R27, 0x8, RZ ; /* 0x000000081b1b7824 */
/* 0x000fe200078e00ff */
/*0250*/ LEA R10, P1, R6, c[0x0][0x160], 0x3 ; /* 0x00005800060a7a11 */
/* 0x000fe200078218ff */
/*0260*/ IMAD.IADD R7, R7, 0x1, R11 ; /* 0x0000000107077824 */
/* 0x000fe200078e020b */
/*0270*/ LEA.HI.X R14, R8, c[0x0][0x16c], R9, 0x3, P2 ; /* 0x00005b00080e7a11 */
/* 0x000fe200010f1c09 */
/*0280*/ IMAD.X R4, RZ, RZ, ~c[0x0][0x17c], P0 ; /* 0x80005f00ff047624 */
/* 0x000fc600000e06ff */
/*0290*/ LEA.HI.X R7, R6, c[0x0][0x164], R7, 0x3, P1 ; /* 0x0000590006077a11 */
/* 0x000fe400008f1c07 */
/*02a0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f06270 */
/*02b0*/ IADD3 R6, P1, R10, 0x10, RZ ; /* 0x000000100a067810 */
/* 0x000fe40007f3e0ff */
/*02c0*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fc6000001ff00 */
/*02d0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fcc00008e0607 */
/*02e0*/ @P0 BRA 0xca0 ; /* 0x000009b000000947 */
/* 0x000fea0003800000 */
/*02f0*/ IADD3 R13, P0, RZ, -R5, RZ ; /* 0x80000005ff0d7210 */
/* 0x000fc80007f1e0ff */
/*0300*/ ISETP.GT.U32.AND P1, PT, R13, 0xc, PT ; /* 0x0000000c0d00780c */
/* 0x000fe20003f24070 */
/*0310*/ IMAD.X R13, RZ, RZ, ~R4, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe200000e0e04 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*0330*/ ISETP.GT.AND.EX P1, PT, R13, RZ, PT, P1 ; /* 0x000000ff0d00720c */
/* 0x000fda0003f24310 */
/*0340*/ @!P1 BRA 0x900 ; /* 0x000005b000009947 */
/* 0x000fea0003800000 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0360*/ IMAD.MOV.U32 R13, RZ, RZ, R14 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000e */
/*0370*/ LDG.E.64 R16, [R6.64+-0x10] ; /* 0xfffff00606107981 */
/* 0x000ea2000c1e1b00 */
/*0380*/ IADD3 R22, P1, R12, R27, RZ ; /* 0x0000001b0c167210 */
/* 0x000fc60007f3e0ff */
/*0390*/ LDG.E.64 R18, [R12.64] ; /* 0x000000060c127981 */
/* 0x0000a4000c1e1b00 */
/*03a0*/ IMAD.X R23, R14, 0x1, R25, P1 ; /* 0x000000010e177824 */
/* 0x000fca00008e0619 */
/*03b0*/ LDG.E.64 R14, [R22.64] ; /* 0x00000006160e7981 */
/* 0x000ee8000c1e1b00 */
/*03c0*/ LDG.E.64 R12, [R6.64+-0x8] ; /* 0xfffff806060c7981 */
/* 0x001ee2000c1e1b00 */
/*03d0*/ IADD3 R20, P1, R22, R27, RZ ; /* 0x0000001b16147210 */
/* 0x000fca0007f3e0ff */
/*03e0*/ IMAD.X R21, R23, 0x1, R25, P1 ; /* 0x0000000117157824 */
/* 0x000fe200008e0619 */
/*03f0*/ DFMA R28, R18, R16, R10 ; /* 0x00000010121c722b */
/* 0x0040e4000000000a */
/*0400*/ LDG.E.64 R16, [R6.64] ; /* 0x0000000606107981 */
/* 0x001ea2000c1e1b00 */
/*0410*/ IADD3 R18, P1, R20, R27, RZ ; /* 0x0000001b14127210 */
/* 0x000fc60007f3e0ff */
/*0420*/ LDG.E.64 R10, [R20.64] ; /* 0x00000006140a7981 */
/* 0x0006a4000c1e1b00 */
/*0430*/ IMAD.X R19, R21, 0x1, R25, P1 ; /* 0x0000000115137824 */
/* 0x000fe200008e0619 */
/*0440*/ DFMA R20, R14, R12, R28 ; /* 0x0000000c0e14722b */
/* 0x0080a4000000001c */
/*0450*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000806060e7981 */
/* 0x001ee8000c1e1b00 */
/*0460*/ LDG.E.64 R12, [R18.64] ; /* 0x00000006120c7981 */
/* 0x0004e2000c1e1b00 */
/*0470*/ IADD3 R28, P1, R18, R27, RZ ; /* 0x0000001b121c7210 */
/* 0x000fca0007f3e0ff */
/*0480*/ IMAD.X R29, R19, 0x1, R25, P1 ; /* 0x00000001131d7824 */
/* 0x000fe200008e0619 */
/*0490*/ IADD3 R22, P1, R28, R27, RZ ; /* 0x0000001b1c167210 */
/* 0x000fca0007f3e0ff */
/*04a0*/ IMAD.X R23, R29, 0x1, R25, P1 ; /* 0x000000011d177824 */
/* 0x000fe200008e0619 */
/*04b0*/ DFMA R18, R10, R16, R20 ; /* 0x000000100a12722b */
/* 0x0040e40000000014 */
/*04c0*/ LDG.E.64 R16, [R6.64+0x10] ; /* 0x0000100606107981 */
/* 0x001ea8000c1e1b00 */
/*04d0*/ LDG.E.64 R10, [R28.64] ; /* 0x000000061c0a7981 */
/* 0x0006a4000c1e1b00 */
/*04e0*/ DFMA R28, R12, R14, R18 ; /* 0x0000000e0c1c722b */
/* 0x0080a40000000012 */
/*04f0*/ LDG.E.64 R12, [R6.64+0x18] ; /* 0x00001806060c7981 */
/* 0x001ee8000c1e1b00 */
/*0500*/ LDG.E.64 R14, [R22.64] ; /* 0x00000006160e7981 */
/* 0x000ee2000c1e1b00 */
/*0510*/ IADD3 R20, P1, R22, R27, RZ ; /* 0x0000001b16147210 */
/* 0x000fca0007f3e0ff */
/*0520*/ IMAD.X R21, R23, 0x1, R25, P1 ; /* 0x0000000117157824 */
/* 0x000fe200008e0619 */
/*0530*/ IADD3 R18, P1, R20, R27, RZ ; /* 0x0000001b14127210 */
/* 0x000fca0007f3e0ff */
/*0540*/ IMAD.X R19, R21, 0x1, R25, P1 ; /* 0x0000000115137824 */
/* 0x000fe200008e0619 */
/*0550*/ DFMA R28, R10, R16, R28 ; /* 0x000000100a1c722b */
/* 0x0040e4000000001c */
/*0560*/ LDG.E.64 R10, [R6.64+0x20] ; /* 0x00002006060a7981 */
/* 0x001ea8000c1e1b00 */
/*0570*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000614107981 */
/* 0x000ea2000c1e1b00 */
/*0580*/ DFMA R28, R14, R12, R28 ; /* 0x0000000c0e1c722b */
/* 0x008086000000001c */
/*0590*/ LDG.E.64 R12, [R6.64+0x28] ; /* 0x00002806060c7981 */
/* 0x001ee8000c1e1b00 */
/*05a0*/ LDG.E.64 R14, [R18.64] ; /* 0x00000006120e7981 */
/* 0x0004e2000c1e1b00 */
/*05b0*/ IADD3 R22, P1, R18, R27, RZ ; /* 0x0000001b12167210 */
/* 0x000fca0007f3e0ff */
/*05c0*/ IMAD.X R23, R19, 0x1, R25.reuse, P1 ; /* 0x0000000113177824 */
/* 0x100fe200008e0619 */
/*05d0*/ DFMA R18, R16, R10, R28 ; /* 0x0000000a1012722b */
/* 0x0040e4000000001c */
/*05e0*/ IADD3 R28, P1, R22, R27, RZ ; /* 0x0000001b161c7210 */
/* 0x001fe20007f3e0ff */
/*05f0*/ LDG.E.64 R10, [R6.64+0x30] ; /* 0x00003006060a7981 */
/* 0x000ea8000c1e1b00 */
/*0600*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000616107981 */
/* 0x0006a2000c1e1b00 */
/*0610*/ IMAD.X R29, R23, 0x1, R25, P1 ; /* 0x00000001171d7824 */
/* 0x000fca00008e0619 */
/*0620*/ LDG.E.64 R20, [R28.64] ; /* 0x000000061c147981 */
/* 0x000f22000c1e1b00 */
/*0630*/ DFMA R22, R14, R12, R18 ; /* 0x0000000c0e16722b */
/* 0x0080860000000012 */
/*0640*/ LDG.E.64 R12, [R6.64+0x38] ; /* 0x00003806060c7981 */
/* 0x001f22000c1e1b00 */
/*0650*/ IADD3 R14, P1, R28, R27, RZ ; /* 0x0000001b1c0e7210 */
/* 0x000fca0007f3e0ff */
/*0660*/ IMAD.X R15, R29, 0x1, R25, P1 ; /* 0x000000011d0f7824 */
/* 0x000fe200008e0619 */
/*0670*/ IADD3 R18, P1, R14, R27, RZ ; /* 0x0000001b0e127210 */
/* 0x000fca0007f3e0ff */
/*0680*/ IMAD.X R19, R15, 0x1, R25, P1 ; /* 0x000000010f137824 */
/* 0x000fe200008e0619 */
/*0690*/ DFMA R22, R16, R10, R22 ; /* 0x0000000a1016722b */
/* 0x0041240000000016 */
/*06a0*/ LDG.E.64 R10, [R6.64+0x40] ; /* 0x00004006060a7981 */
/* 0x001ea8000c1e1b00 */
/*06b0*/ LDG.E.64 R16, [R14.64] ; /* 0x000000060e107981 */
/* 0x0000a2000c1e1b00 */
/*06c0*/ DFMA R20, R20, R12, R22 ; /* 0x0000000c1414722b */
/* 0x0102860000000016 */
/*06d0*/ LDG.E.64 R22, [R6.64+0x48] ; /* 0x0000480606167981 */
/* 0x002ee8000c1e1b00 */
/*06e0*/ LDG.E.64 R14, [R18.64] ; /* 0x00000006120e7981 */
/* 0x001ee2000c1e1b00 */
/*06f0*/ IADD3 R12, P1, R18, R27, RZ ; /* 0x0000001b120c7210 */
/* 0x000fca0007f3e0ff */
/*0700*/ IMAD.X R13, R19, 0x1, R25, P1 ; /* 0x00000001130d7824 */
/* 0x000fe200008e0619 */
/*0710*/ IADD3 R28, P1, R12, R27, RZ ; /* 0x0000001b0c1c7210 */
/* 0x000fca0007f3e0ff */
/*0720*/ IMAD.X R29, R13, 0x1, R25, P1 ; /* 0x000000010d1d7824 */
/* 0x000fe200008e0619 */
/*0730*/ DFMA R16, R16, R10, R20 ; /* 0x0000000a1010722b */
/* 0x0040e40000000014 */
/*0740*/ LDG.E.64 R10, [R6.64+0x50] ; /* 0x00005006060a7981 */
/* 0x001ea8000c1e1b00 */
/*0750*/ LDG.E.64 R20, [R12.64] ; /* 0x000000060c147981 */
/* 0x0000a2000c1e1b00 */
/*0760*/ DFMA R22, R14, R22, R16 ; /* 0x000000160e16722b */
/* 0x0082860000000010 */
/*0770*/ LDG.E.64 R14, [R28.64] ; /* 0x000000061c0e7981 */
/* 0x002ee8000c1e1b00 */
/*0780*/ LDG.E.64 R12, [R6.64+0x58] ; /* 0x00005806060c7981 */
/* 0x001ee2000c1e1b00 */
/*0790*/ IADD3 R16, P1, R28, R27, RZ ; /* 0x0000001b1c107210 */
/* 0x000fca0007f3e0ff */
/*07a0*/ IMAD.X R17, R29, 0x1, R25, P1 ; /* 0x000000011d117824 */
/* 0x000fe200008e0619 */
/*07b0*/ IADD3 R18, P1, R16, R27, RZ ; /* 0x0000001b10127210 */
/* 0x000fca0007f3e0ff */
/*07c0*/ IMAD.X R19, R17, 0x1, R25, P1 ; /* 0x0000000111137824 */
/* 0x000fe400008e0619 */
/*07d0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000f22000c1e1b00 */
/*07e0*/ DFMA R20, R20, R10, R22 ; /* 0x0000000a1414722b */
/* 0x0040c60000000016 */
/*07f0*/ LDG.E.64 R10, [R6.64+0x60] ; /* 0x00006006060a7981 */
/* 0x001f26000c1e1b00 */
/*0800*/ DFMA R12, R14, R12, R20 ; /* 0x0000000c0e0c722b */
/* 0x0081240000000014 */
/*0810*/ LDG.E.64 R14, [R6.64+0x68] ; /* 0x00006806060e7981 */
/* 0x0010a8000c1e1b00 */
/*0820*/ LDG.E.64 R20, [R18.64] ; /* 0x0000000612147981 */
/* 0x000ea2000c1e1b00 */
/*0830*/ IADD3 R5, P1, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fca0007f3e0ff */
/*0840*/ IMAD.X R4, RZ, RZ, R4, P1 ; /* 0x000000ffff047224 */
/* 0x000fe200008e0604 */
/*0850*/ ISETP.GE.U32.AND P1, PT, R5, -0xc, PT ; /* 0xfffffff40500780c */
/* 0x000fc80003f26070 */
/*0860*/ ISETP.GE.AND.EX P1, PT, R4, -0x1, PT, P1 ; /* 0xffffffff0400780c */
/* 0x000fe20003f26310 */
/*0870*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0880*/ DFMA R10, R16, R10, R12 ; /* 0x0000000a100a722b */
/* 0x0102a4000000000c */
/*0890*/ IADD3 R13, P2, R6, 0x80, RZ ; /* 0x00000080060d7810 */
/* 0x002fe40007f5e0ff */
/*08a0*/ IADD3 R12, P3, R18, R27, RZ ; /* 0x0000001b120c7210 */
/* 0x000fc60007f7e0ff */
/*08b0*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x001fe400010e0607 */
/*08c0*/ IMAD.MOV.U32 R6, RZ, RZ, R13 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000d */
/*08d0*/ DFMA R10, R20, R14, R10 ; /* 0x0000000e140a722b */
/* 0x004064000000000a */
/*08e0*/ IMAD.X R14, R19, 0x1, R25, P3 ; /* 0x00000001130e7824 */
/* 0x001fe200018e0619 */
/*08f0*/ @!P1 BRA 0x360 ; /* 0xfffffa6000009947 */
/* 0x002fea000383ffff */
/*0900*/ IADD3 R13, P2, RZ, -R5, RZ ; /* 0x80000005ff0d7210 */
/* 0x000fc80007f5e0ff */
/*0910*/ ISETP.GT.U32.AND P1, PT, R13, 0x4, PT ; /* 0x000000040d00780c */
/* 0x000fe20003f24070 */
/*0920*/ IMAD.X R13, RZ, RZ, ~R4, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fca00010e0e04 */
/*0930*/ ISETP.GT.AND.EX P1, PT, R13, RZ, PT, P1 ; /* 0x000000ff0d00720c */
/* 0x000fda0003f24310 */
/*0940*/ @!P1 BRA 0xc70 ; /* 0x0000032000009947 */
/* 0x000fea0003800000 */
/*0950*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000c */
/*0960*/ IADD3 R28, P0, R12, R27, RZ ; /* 0x0000001b0c1c7210 */
/* 0x000fe20007f1e0ff */
/*0970*/ IMAD.MOV.U32 R17, RZ, RZ, R14 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000e */
/*0980*/ LDG.E.64 R12, [R6.64+-0x10] ; /* 0xfffff006060c7981 */
/* 0x000ea8000c1e1b00 */
/*0990*/ LDG.E.64 R18, [R16.64] ; /* 0x0000000610127981 */
/* 0x0000a2000c1e1b00 */
/*09a0*/ IMAD.X R29, R14, 0x1, R25, P0 ; /* 0x000000010e1d7824 */
/* 0x000fc600000e0619 */
/*09b0*/ LDG.E.64 R14, [R6.64+-0x8] ; /* 0xfffff806060e7981 */
/* 0x000ee8000c1e1b00 */
/*09c0*/ LDG.E.64 R16, [R28.64] ; /* 0x000000061c107981 */
/* 0x001ee2000c1e1b00 */
/*09d0*/ IADD3 R22, P0, R28, R27, RZ ; /* 0x0000001b1c167210 */
/* 0x000fca0007f1e0ff */
/*09e0*/ IMAD.X R23, R29, 0x1, R25, P0 ; /* 0x000000011d177824 */
/* 0x000fe200000e0619 */
/*09f0*/ IADD3 R20, P0, R22, R27, RZ ; /* 0x0000001b16147210 */
/* 0x000fca0007f1e0ff */
/*0a00*/ IMAD.X R21, R23, 0x1, R25, P0 ; /* 0x0000000117157824 */
/* 0x000fe200000e0619 */
/*0a10*/ DFMA R18, R18, R12, R10 ; /* 0x0000000c1212722b */
/* 0x0040e4000000000a */
/*0a20*/ LDG.E.64 R10, [R6.64] ; /* 0x00000006060a7981 */
/* 0x001ea8000c1e1b00 */
/*0a30*/ LDG.E.64 R12, [R22.64] ; /* 0x00000006160c7981 */
/* 0x0006a4000c1e1b00 */
/*0a40*/ DFMA R22, R16, R14, R18 ; /* 0x0000000e1016722b */
/* 0x0080a40000000012 */
/*0a50*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000806060e7981 */
/* 0x001ee8000c1e1b00 */
/*0a60*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000614127981 */
/* 0x0004e2000c1e1b00 */
/*0a70*/ IADD3 R16, P0, R20, R27, RZ ; /* 0x0000001b14107210 */
/* 0x000fca0007f1e0ff */
/*0a80*/ IMAD.X R17, R21, 0x1, R25, P0 ; /* 0x0000000115117824 */
/* 0x000fe200000e0619 */
/*0a90*/ IADD3 R28, P0, R16, R27, RZ ; /* 0x0000001b101c7210 */
/* 0x000fca0007f1e0ff */
/*0aa0*/ IMAD.X R29, R17, 0x1, R25, P0 ; /* 0x00000001111d7824 */
/* 0x000fe200000e0619 */
/*0ab0*/ DFMA R20, R12, R10, R22 ; /* 0x0000000a0c14722b */
/* 0x0040e40000000016 */
/*0ac0*/ LDG.E.64 R10, [R6.64+0x10] ; /* 0x00001006060a7981 */
/* 0x001ea8000c1e1b00 */
/*0ad0*/ LDG.E.64 R12, [R16.64] ; /* 0x00000006100c7981 */
/* 0x0000a2000c1e1b00 */
/*0ae0*/ DFMA R14, R18, R14, R20 ; /* 0x0000000e120e722b */
/* 0x0082860000000014 */
/*0af0*/ LDG.E.64 R16, [R6.64+0x18] ; /* 0x0000180606107981 */
/* 0x001ee8000c1e1b00 */
/*0b00*/ LDG.E.64 R18, [R28.64] ; /* 0x000000061c127981 */
/* 0x002ee2000c1e1b00 */
/*0b10*/ IADD3 R20, P0, R28, R27, RZ ; /* 0x0000001b1c147210 */
/* 0x000fca0007f1e0ff */
/*0b20*/ IMAD.X R21, R29, 0x1, R25, P0 ; /* 0x000000011d157824 */
/* 0x000fe200000e0619 */
/*0b30*/ IADD3 R22, P0, R20, R27, RZ ; /* 0x0000001b14167210 */
/* 0x000fca0007f1e0ff */
/*0b40*/ IMAD.X R23, R21, 0x1, R25, P0 ; /* 0x0000000115177824 */
/* 0x000fe400000e0619 */
/*0b50*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000f22000c1e1b00 */
/*0b60*/ DFMA R12, R12, R10, R14 ; /* 0x0000000a0c0c722b */
/* 0x0040c6000000000e */
/*0b70*/ LDG.E.64 R10, [R6.64+0x20] ; /* 0x00002006060a7981 */
/* 0x001f28000c1e1b00 */
/*0b80*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002806060e7981 */
/* 0x0000a2000c1e1b00 */
/*0b90*/ DFMA R12, R18, R16, R12 ; /* 0x00000010120c722b */
/* 0x008306000000000c */
/*0ba0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000616107981 */
/* 0x002ea2000c1e1b00 */
/*0bb0*/ IADD3 R5, P3, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007f7e0ff */
/*0bc0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0e170 */
/*0bd0*/ IMAD.X R4, RZ, RZ, R4, P3 ; /* 0x000000ffff047224 */
/* 0x000fe200018e0604 */
/*0be0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0bf0*/ DFMA R10, R20, R10, R12 ; /* 0x0000000a140a722b */
/* 0x0102a4000000000c */
/*0c00*/ IADD3 R13, P2, R6, 0x40, RZ ; /* 0x00000040060d7810 */
/* 0x002fe40007f5e0ff */
/*0c10*/ IADD3 R12, P1, R22, R27, RZ ; /* 0x0000001b160c7210 */
/* 0x000fc60007f3e0ff */
/*0c20*/ IMAD.MOV.U32 R6, RZ, RZ, R13 ; /* 0x000000ffff067224 */
/* 0x001fe200078e000d */
/*0c30*/ DFMA R10, R16, R14, R10 ; /* 0x0000000e100a722b */
/* 0x004064000000000a */
/*0c40*/ IMAD.X R16, RZ, RZ, R7, P2 ; /* 0x000000ffff107224 */
/* 0x001fe400010e0607 */
/*0c50*/ IMAD.X R14, R23, 0x1, R25, P1 ; /* 0x00000001170e7824 */
/* 0x000fe400008e0619 */
/*0c60*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0010 */
/*0c70*/ ISETP.NE.U32.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x002fc80003f25070 */
/*0c80*/ ISETP.NE.OR.EX P0, PT, R4, RZ, P0, P1 ; /* 0x000000ff0400720c */
/* 0x000fda0000705710 */
/*0c90*/ @!P0 BRA 0xe80 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0ca0*/ IMAD.MOV.U32 R13, RZ, RZ, R14 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000e */
/*0cb0*/ IADD3 R28, P0, R12, R27, RZ ; /* 0x0000001b0c1c7210 */
/* 0x000fe20007f1e0ff */
/*0cc0*/ LDG.E.64 R20, [R6.64+-0x10] ; /* 0xfffff00606147981 */
/* 0x000ea8000c1e1b00 */
/*0cd0*/ LDG.E.64 R22, [R12.64] ; /* 0x000000060c167981 */
/* 0x0000a2000c1e1b00 */
/*0ce0*/ IMAD.X R29, R14, 0x1, R25, P0 ; /* 0x000000010e1d7824 */
/* 0x000fca00000e0619 */
/*0cf0*/ LDG.E.64 R14, [R28.64] ; /* 0x000000061c0e7981 */
/* 0x000ee8000c1e1b00 */
/*0d00*/ LDG.E.64 R12, [R6.64+-0x8] ; /* 0xfffff806060c7981 */
/* 0x001ee2000c1e1b00 */
/*0d10*/ IADD3 R16, P0, R28, R27, RZ ; /* 0x0000001b1c107210 */
/* 0x000fca0007f1e0ff */
/*0d20*/ IMAD.X R17, R29, 0x1, R25, P0 ; /* 0x000000011d117824 */
/* 0x000fe200000e0619 */
/*0d30*/ IADD3 R18, P0, R16, R27, RZ ; /* 0x0000001b10127210 */
/* 0x000fca0007f1e0ff */
/*0d40*/ IMAD.X R19, R17, 0x1, R25, P0 ; /* 0x0000000111137824 */
/* 0x000fe400000e0619 */
/*0d50*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000f22000c1e1b00 */
/*0d60*/ DFMA R20, R22, R20, R10 ; /* 0x000000141614722b */
/* 0x0040c6000000000a */
/*0d70*/ LDG.E.64 R10, [R6.64] ; /* 0x00000006060a7981 */
/* 0x001f26000c1e1b00 */
/*0d80*/ DFMA R12, R14, R12, R20 ; /* 0x0000000c0e0c722b */
/* 0x0081240000000014 */
/*0d90*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000806060e7981 */
/* 0x0010a8000c1e1b00 */
/*0da0*/ LDG.E.64 R20, [R18.64] ; /* 0x0000000612147981 */
/* 0x000ea2000c1e1b00 */
/*0db0*/ IADD3 R5, P0, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fca0007f1e0ff */
/*0dc0*/ IMAD.X R4, RZ, RZ, R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fe200000e0604 */
/*0dd0*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f05070 */
/*0de0*/ ISETP.NE.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fe20003f05300 */
/*0df0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0e00*/ DFMA R10, R16, R10, R12 ; /* 0x0000000a100a722b */
/* 0x0102a4000000000c */
/*0e10*/ IADD3 R13, P1, R6, 0x20, RZ ; /* 0x00000020060d7810 */
/* 0x002fe40007f3e0ff */
/*0e20*/ IADD3 R12, P2, R18, R27, RZ ; /* 0x0000001b120c7210 */
/* 0x000fc60007f5e0ff */
/*0e30*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x001fe400008e0607 */
/*0e40*/ IMAD.MOV.U32 R6, RZ, RZ, R13 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000d */
/*0e50*/ DFMA R10, R20, R14, R10 ; /* 0x0000000e140a722b */
/* 0x004064000000000a */
/*0e60*/ IMAD.X R14, R19, 0x1, R25, P2 ; /* 0x00000001130e7824 */
/* 0x001fe200010e0619 */
/*0e70*/ @P0 BRA 0xca0 ; /* 0xfffffe2000000947 */
/* 0x002fea000383ffff */
/*0e80*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc80003f05070 */
/*0e90*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0ea0*/ @!P0 BRA 0x10c0 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0eb0*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe20008011404 */
/*0ec0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*0ed0*/ IADD3 R12, P1, RZ, -R3, RZ ; /* 0x80000003ff0c7210 */
/* 0x000fe20007f3e0ff */
/*0ee0*/ IMAD R7, R2, c[0x0][0x178], RZ ; /* 0x00005e0002077a24 */
/* 0x000fe400078e02ff */
/*0ef0*/ IMAD.U32 R17, RZ, RZ, UR4 ; /* 0x00000004ff117e24 */
/* 0x000fe4000f8e00ff */
/*0f00*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fe4000f8e00ff */
/*0f10*/ IMAD R7, R0.reuse, c[0x0][0x17c], R7 ; /* 0x00005f0000077a24 */
/* 0x040fe400078e0207 */
/*0f20*/ IMAD.WIDE.U32 R4, R0, c[0x0][0x178], R4 ; /* 0x00005e0000047a25 */
/* 0x000fc800078e0004 */
/*0f30*/ IMAD.IADD R15, R7, 0x1, R5 ; /* 0x00000001070f7824 */
/* 0x000fe200078e0205 */
/*0f40*/ LEA R14, P0, R4.reuse, c[0x0][0x160], 0x3 ; /* 0x00005800040e7a11 */
/* 0x040fe200078018ff */
/*0f50*/ IMAD.U32 R16, RZ, RZ, UR5 ; /* 0x00000005ff107e24 */
/* 0x000fe4000f8e00ff */
/*0f60*/ IMAD.X R13, RZ, RZ, -0x1, P1 ; /* 0xffffffffff0d7424 */
/* 0x000fe200008e06ff */
/*0f70*/ LEA.HI.X R15, R4, c[0x0][0x164], R15, 0x3, P0 ; /* 0x00005900040f7a11 */
/* 0x000fe400000f1c0f */
/*0f80*/ IMAD R4, R16, c[0x0][0x178], RZ ; /* 0x00005e0010047a24 */
/* 0x001fe400078e02ff */
/*0f90*/ IMAD.WIDE.U32 R6, R17, c[0x0][0x178], R8 ; /* 0x00005e0011067a25 */
/* 0x000fc800078e0008 */
/*0fa0*/ IMAD R3, R17, c[0x0][0x17c], R4 ; /* 0x00005f0011037a24 */
/* 0x000fe200078e0204 */
/*0fb0*/ LEA R4, P0, R6, c[0x0][0x168], 0x3 ; /* 0x00005a0006047a11 */
/* 0x000fc600078018ff */
/*0fc0*/ IMAD.IADD R3, R7, 0x1, R3 ; /* 0x0000000107037824 */
/* 0x000fe400078e0203 */
/*0fd0*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fc600078e000f */
/*0fe0*/ LEA.HI.X R5, R6, c[0x0][0x16c], R3, 0x3, P0 ; /* 0x00005b0006057a11 */
/* 0x000fe200000f1c03 */
/*0ff0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fca00078e000e */
/*1000*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1b00 */
/*1010*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1b00 */
/*1020*/ IADD3 R12, P0, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fca0007f1e0ff */
/*1030*/ IMAD.X R13, RZ, RZ, R13, P0 ; /* 0x000000ffff0d7224 */
/* 0x000fe200000e060d */
/*1040*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc80003f05070 */
/*1050*/ ISETP.NE.AND.EX P0, PT, R13, RZ, PT, P0 ; /* 0x000000ff0d00720c */
/* 0x000fe40003f05300 */
/*1060*/ IADD3 R14, P2, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe40007f5e0ff */
/*1070*/ IADD3 R17, P1, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fc60007f3e0ff */
/*1080*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400010e060f */
/*1090*/ IMAD.X R16, RZ, RZ, R16, P1 ; /* 0x000000ffff107224 */
/* 0x000fe200008e0610 */
/*10a0*/ DFMA R10, R4, R6, R10 ; /* 0x00000006040a722b */
/* 0x006046000000000a */
/*10b0*/ @P0 BRA 0xf80 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*10c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*10d0*/ IMAD R5, R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a24 */
/* 0x001fe400078e02ff */
/*10e0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0008 */
/*10f0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0009 */
/*1100*/ IMAD R5, R0.reuse, c[0x0][0x17c], R5 ; /* 0x00005f0000057a24 */
/* 0x040fe400078e0205 */
/*1110*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x178], R2 ; /* 0x00005e0000027a25 */
/* 0x000fc800078e0002 */
/*1120*/ IMAD.IADD R3, R5, 0x1, R3 ; /* 0x0000000105037824 */
/* 0x000fe200078e0203 */
/*1130*/ LEA R4, P0, R2, c[0x0][0x170], 0x3 ; /* 0x00005c0002047a11 */
/* 0x000fc800078018ff */
/*1140*/ LEA.HI.X R5, R2, c[0x0][0x174], R3, 0x3, P0 ; /* 0x00005d0002057a11 */
/* 0x000fca00000f1c03 */
/*1150*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x002fe2000c101b06 */
/*1160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1170*/ BRA 0x1170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__
void matrixMultiplicationKernel(double* A, double* B, double* C, long N) {
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
double tmpSum = 0.0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
}
C[ROW * N + COL] = tmpSum;
} | .file "tmpxft_00041ae5_00000000-6_matrixMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l
.type _Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l, @function
_Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq matrixMultiplicationKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l, .-_Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l
.globl matrixMultiplicationKernel
.type matrixMultiplicationKernel, @function
matrixMultiplicationKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size matrixMultiplicationKernel, .-matrixMultiplicationKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrixMultiplicationKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq matrixMultiplicationKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__
void matrixMultiplicationKernel(double* A, double* B, double* C, long N) {
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
double tmpSum = 0.0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
}
C[ROW * N + COL] = tmpSum;
} | #include <hip/hip_runtime.h>
extern "C"
__global__
void matrixMultiplicationKernel(double* A, double* B, double* C, long N) {
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
double tmpSum = 0.0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
}
C[ROW * N + COL] = tmpSum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__
void matrixMultiplicationKernel(double* A, double* B, double* C, long N) {
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
double tmpSum = 0.0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
}
C[ROW * N + COL] = tmpSum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected matrixMultiplicationKernel
.globl matrixMultiplicationKernel
.p2align 8
.type matrixMultiplicationKernel,@function
matrixMultiplicationKernel:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[0:1], null, s14, s4, v[3:4]
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_cmpx_gt_i64_e64 s[2:3], v[2:3]
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_mov_b32 s9, exec_lo
v_cmpx_gt_i64_e64 s[2:3], v[0:1]
s_cbranch_execz .LBB0_6
v_cmp_lt_i64_e64 s4, s[2:3], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v4, v3, s2
v_mul_lo_u32 v5, v2, s3
v_mad_u64_u32 v[6:7], null, v2, s2, 0
v_lshlrev_b64 v[8:9], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v7, v7, v5, v4
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[10:11], 3, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v11, vcc_lo
s_lshl_b64 s[4:5], s[2:3], 3
s_mov_b64 s[6:7], 0
.p2align 6
.LBB0_4:
global_load_b64 v[10:11], v[8:9], off
global_load_b64 v[12:13], v[6:7], off
s_add_u32 s6, s6, 1
v_add_co_u32 v6, vcc_lo, v6, s4
s_addc_u32 s7, s7, 0
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_cmp_lt_i64_e64 s10, s[6:7], s[2:3]
v_add_co_u32 v8, vcc_lo, v8, 8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 vcc_lo, exec_lo, s10
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[10:11], v[12:13], v[4:5]
s_cbranch_vccnz .LBB0_4
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v3, v3, s2
v_mul_lo_u32 v8, v2, s3
v_mad_u64_u32 v[6:7], null, v2, s2, 0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v7, v7, v8, v3
v_lshlrev_b64 v[2:3], 3, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrixMultiplicationKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size matrixMultiplicationKernel, .Lfunc_end0-matrixMultiplicationKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrixMultiplicationKernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrixMultiplicationKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__
void matrixMultiplicationKernel(double* A, double* B, double* C, long N) {
int ROW = blockIdx.y*blockDim.y+threadIdx.y;
int COL = blockIdx.x*blockDim.x+threadIdx.x;
double tmpSum = 0.0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
}
C[ROW * N + COL] = tmpSum;
} | .text
.file "matrixMul.hip"
.globl __device_stub__matrixMultiplicationKernel # -- Begin function __device_stub__matrixMultiplicationKernel
.p2align 4, 0x90
.type __device_stub__matrixMultiplicationKernel,@function
__device_stub__matrixMultiplicationKernel: # @__device_stub__matrixMultiplicationKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrixMultiplicationKernel, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__matrixMultiplicationKernel, .Lfunc_end0-__device_stub__matrixMultiplicationKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrixMultiplicationKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type matrixMultiplicationKernel,@object # @matrixMultiplicationKernel
.section .rodata,"a",@progbits
.globl matrixMultiplicationKernel
.p2align 3, 0x0
matrixMultiplicationKernel:
.quad __device_stub__matrixMultiplicationKernel
.size matrixMultiplicationKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "matrixMultiplicationKernel"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__matrixMultiplicationKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym matrixMultiplicationKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00041ae5_00000000-6_matrixMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l
.type _Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l, @function
_Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq matrixMultiplicationKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l, .-_Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l
.globl matrixMultiplicationKernel
.type matrixMultiplicationKernel, @function
matrixMultiplicationKernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26matrixMultiplicationKernelPdS_S_lPdS_S_l
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size matrixMultiplicationKernel, .-matrixMultiplicationKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrixMultiplicationKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq matrixMultiplicationKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMul.hip"
.globl __device_stub__matrixMultiplicationKernel # -- Begin function __device_stub__matrixMultiplicationKernel
.p2align 4, 0x90
.type __device_stub__matrixMultiplicationKernel,@function
__device_stub__matrixMultiplicationKernel: # @__device_stub__matrixMultiplicationKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $matrixMultiplicationKernel, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__matrixMultiplicationKernel, .Lfunc_end0-__device_stub__matrixMultiplicationKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrixMultiplicationKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type matrixMultiplicationKernel,@object # @matrixMultiplicationKernel
.section .rodata,"a",@progbits
.globl matrixMultiplicationKernel
.p2align 3, 0x0
matrixMultiplicationKernel:
.quad __device_stub__matrixMultiplicationKernel
.size matrixMultiplicationKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "matrixMultiplicationKernel"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__matrixMultiplicationKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym matrixMultiplicationKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void vecEps(float* a,const int N){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(a[i] < EPS && i < N)
a[i] = EPS;
} | code for sm_80
Function : _Z6vecEpsPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0080*/ F2F.F64.F32 R4, R4 ; /* 0x0000000400047310 */
/* 0x004e240000201800 */
/*0090*/ DSETP.GEU.AND P0, PT, R4, c[0x2][0x0], PT ; /* 0x008000000400762a */
/* 0x001e0c0003f0e000 */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x001fda0000706670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ MOV R5, 0x257ffea4 ; /* 0x257ffea400057802 */
/* 0x000fca0000000f00 */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void vecEps(float* a,const int N){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(a[i] < EPS && i < N)
a[i] = EPS;
} | .file "tmpxft_0013d1a4_00000000-6_vecEps.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6vecEpsPfiPfi
.type _Z26__device_stub__Z6vecEpsPfiPfi, @function
_Z26__device_stub__Z6vecEpsPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6vecEpsPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6vecEpsPfiPfi, .-_Z26__device_stub__Z6vecEpsPfiPfi
.globl _Z6vecEpsPfi
.type _Z6vecEpsPfi, @function
_Z6vecEpsPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6vecEpsPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecEpsPfi, .-_Z6vecEpsPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecEpsPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecEpsPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void vecEps(float* a,const int N){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(a[i] < EPS && i < N)
a[i] = EPS;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecEps(float* a,const int N){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(a[i] < EPS && i < N)
a[i] = EPS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecEps(float* a,const int N){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(a[i] < EPS && i < N)
a[i] = EPS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecEpsPfi
.globl _Z6vecEpsPfi
.p2align 8
.type _Z6vecEpsPfi,@function
_Z6vecEpsPfi:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_load_b32 s4, s[0:1], 0x8
s_mov_b32 s1, 0x3cafffd4
s_mov_b32 s0, 0x81f97682
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[3:4], v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[3:4]
v_cmp_gt_i32_e64 s0, s4, v2
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0x257ffea4
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecEpsPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecEpsPfi, .Lfunc_end0-_Z6vecEpsPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecEpsPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecEpsPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecEps(float* a,const int N){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(a[i] < EPS && i < N)
a[i] = EPS;
} | .text
.file "vecEps.hip"
.globl _Z21__device_stub__vecEpsPfi # -- Begin function _Z21__device_stub__vecEpsPfi
.p2align 4, 0x90
.type _Z21__device_stub__vecEpsPfi,@function
_Z21__device_stub__vecEpsPfi: # @_Z21__device_stub__vecEpsPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6vecEpsPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__vecEpsPfi, .Lfunc_end0-_Z21__device_stub__vecEpsPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecEpsPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecEpsPfi,@object # @_Z6vecEpsPfi
.section .rodata,"a",@progbits
.globl _Z6vecEpsPfi
.p2align 3, 0x0
_Z6vecEpsPfi:
.quad _Z21__device_stub__vecEpsPfi
.size _Z6vecEpsPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecEpsPfi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecEpsPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecEpsPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecEpsPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0080*/ F2F.F64.F32 R4, R4 ; /* 0x0000000400047310 */
/* 0x004e240000201800 */
/*0090*/ DSETP.GEU.AND P0, PT, R4, c[0x2][0x0], PT ; /* 0x008000000400762a */
/* 0x001e0c0003f0e000 */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x001fda0000706670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ MOV R5, 0x257ffea4 ; /* 0x257ffea400057802 */
/* 0x000fca0000000f00 */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecEpsPfi
.globl _Z6vecEpsPfi
.p2align 8
.type _Z6vecEpsPfi,@function
_Z6vecEpsPfi:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_load_b32 s4, s[0:1], 0x8
s_mov_b32 s1, 0x3cafffd4
s_mov_b32 s0, 0x81f97682
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[3:4], v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[3:4]
v_cmp_gt_i32_e64 s0, s4, v2
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v2, 0x257ffea4
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecEpsPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecEpsPfi, .Lfunc_end0-_Z6vecEpsPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecEpsPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecEpsPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013d1a4_00000000-6_vecEps.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6vecEpsPfiPfi
.type _Z26__device_stub__Z6vecEpsPfiPfi, @function
_Z26__device_stub__Z6vecEpsPfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6vecEpsPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6vecEpsPfiPfi, .-_Z26__device_stub__Z6vecEpsPfiPfi
.globl _Z6vecEpsPfi
.type _Z6vecEpsPfi, @function
_Z6vecEpsPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6vecEpsPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecEpsPfi, .-_Z6vecEpsPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecEpsPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecEpsPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecEps.hip"
.globl _Z21__device_stub__vecEpsPfi # -- Begin function _Z21__device_stub__vecEpsPfi
.p2align 4, 0x90
.type _Z21__device_stub__vecEpsPfi,@function
_Z21__device_stub__vecEpsPfi: # @_Z21__device_stub__vecEpsPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6vecEpsPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__vecEpsPfi, .Lfunc_end0-_Z21__device_stub__vecEpsPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecEpsPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecEpsPfi,@object # @_Z6vecEpsPfi
.section .rodata,"a",@progbits
.globl _Z6vecEpsPfi
.p2align 3, 0x0
_Z6vecEpsPfi:
.quad _Z21__device_stub__vecEpsPfi
.size _Z6vecEpsPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecEpsPfi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecEpsPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecEpsPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void build_binary_tree(int *x, int *child, int *root, int n)
{
int bodyIndex = threadIdx.x + blockIdx.x*blockDim.x;
int stride = blockDim.x*gridDim.x;
int offset = 0;
bool newBody = true;
int rootValue = *root;
// build binary tree
int childPath;
int temp;
offset = 0;
while((bodyIndex + offset) < n){
if(newBody){
newBody = false;
temp = 0;
childPath = 0;
if(x[bodyIndex + offset] > rootValue){
childPath = 1;
}
}
int childIndex = child[temp*2 + childPath];
// traverse tree until we hit leaf node
while(childIndex >= 0){
temp = childIndex;
childPath = 0;
if(x[bodyIndex + offset] > temp){
childPath = 1;
}
childIndex = child[2*temp + childPath];
}
if(childIndex != -2){
int locked = temp*2 + childPath;
if(atomicCAS(&child[locked], childIndex, -2) == childIndex){
if(childIndex == -1){
child[locked] = x[bodyIndex + offset];
}
offset += stride;
newBody = true;
}
}
__syncthreads(); // not strictly needed
}
}
int main(){
int n = 32;
int *h_x; //host array
int *d_x; //device array
int *h_root;
int *d_root;
int *h_child;
int *d_child;
// allocate memory
h_x = (int*)malloc(n*sizeof(int));
h_root = (int*)malloc(sizeof(int));
h_child = (int*)malloc(2*(n+1)*sizeof(int));
cudaMalloc((void**)&d_root, sizeof(int));
cudaMalloc((void**)&d_x, n*sizeof(int));
cudaMalloc((void**)&d_child, 2*(n+1)*sizeof(int));
cudaMemset(d_child, -1, 2*(n+1)*sizeof(int));
// fill h_temp and h_x arrays
for(int i=0;i<n;i++){
h_x[i] = i+1;
}
// shuffling the array
for(int i=0;i<n;i++){
int j = random() % (n-i);
int temp = h_x[i];
h_x[i] = h_x[i+j];
h_x[i+j] = temp;
}
*h_root = h_x[0];
for(int i=0;i<n;i++){
printf("%d ", h_x[i]);
}
printf("\n");
// copy data to device
cudaMemcpy(d_root, h_root, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_x, h_x, n*sizeof(int), cudaMemcpyHostToDevice);
// kernel call
build_binary_tree<<< 16, 16>>>(d_x, d_child, d_root, n);
// copy from device back to host
cudaMemcpy(h_child, d_child, 2*(n+1)*sizeof(int), cudaMemcpyDeviceToHost);
// print tree
for(int i=0;i<2*(n+1);i++){
printf("%d ", h_child[i]);
}
printf("\n");
// free memory
free(h_x);
free(h_root);
free(h_child);
cudaFree(d_x);
cudaFree(d_root);
cudaFree(d_child);
} | code for sm_80
Function : _Z17build_binary_treePiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0090*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000162000c1e1900 */
/*00a0*/ HFMA2.MMA R10, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0a7435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fce00078e0000 */
/*00d0*/ LOP3.LUT P0, RZ, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0aff7812 */
/* 0x000fe2000780c0ff */
/*00e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*00f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0100*/ BSSY B0, 0x180 ; /* 0x0000007000007945 */
/* 0x000fe80003800000 */
/*0110*/ IMAD.WIDE R2, R4, R13, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e020d */
/*0120*/ @!P0 BRA 0x170 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0130*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GT.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x024fc80003f04270 */
/*0160*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IMAD R4, R12, 0x2, R11 ; /* 0x000000020c047824 */
/* 0x000fc800078e020b */
/*0190*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e020d */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ BSSY B0, 0x2b0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*01c0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f06270 */
/*01d0*/ @!P0 BRA 0x2a0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*01f0*/ BSSY B1, 0x2a0 ; /* 0x000000a000017945 */
/* 0x000fe40003800000 */
/*0200*/ ISETP.GT.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x020fe20003f04270 */
/*0210*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0004 */
/*0220*/ SHF.L.U32 R8, R4, 0x1, RZ ; /* 0x0000000104087819 */
/* 0x000fe400000006ff */
/*0230*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0240*/ LOP3.LUT R8, R8, 0xfffffffe, R11, 0xe2, !PT ; /* 0xfffffffe08087812 */
/* 0x000fca00078ee20b */
/*0250*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020d */
/*0260*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea4000c1e1900 */
/*0270*/ ISETP.GT.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fda0003f04270 */
/*0280*/ @P0 BRA 0x200 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0290*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.NE.AND P0, PT, R4, -0x2, PT ; /* 0xfffffffe0400780c */
/* 0x000fe40003f05270 */
/*02c0*/ PRMT R10, RZ, 0x7610, R10 ; /* 0x00007610ff0a7816 */
/* 0x000fd6000000000a */
/*02d0*/ @!P0 BRA 0x3b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD R8, R12, 0x2, R11 ; /* 0x000000020c087824 */
/* 0x000fe200078e020b */
/*02f0*/ MOV R5, 0xfffffffe ; /* 0xfffffffe00057802 */
/* 0x000fc60000000f00 */
/*0300*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020d */
/*0310*/ ATOMG.E.CAS.STRONG.GPU PT, R5, [R8], R4, R5 ; /* 0x00000004080573a9 */
/* 0x000ea400001ee105 */
/*0320*/ ISETP.NE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x004fda0003f05270 */
/*0330*/ @P0 BRA 0x3b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x000fe20003f05270 */
/*0350*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe400078e00ff */
/*0360*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fd400078e00ff */
/*0370*/ @P0 BRA 0x3a0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0380*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001ea8000c1e1900 */
/*0390*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x0041e4000c101904 */
/*03a0*/ IMAD R7, R4, c[0x0][0xc], R7 ; /* 0x0000030004077a24 */
/* 0x000fca00078e0207 */
/*03b0*/ IADD3 R4, R0, R7, RZ ; /* 0x0000000700047210 */
/* 0x000fe20007ffe0ff */
/*03c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*03e0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*03f0*/ @!P0 BRA 0xd0 ; /* 0xfffffcd000008947 */
/* 0x000fea000383ffff */
/*0400*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0410*/ BRA 0x410; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void build_binary_tree(int *x, int *child, int *root, int n)
{
int bodyIndex = threadIdx.x + blockIdx.x*blockDim.x;
int stride = blockDim.x*gridDim.x;
int offset = 0;
bool newBody = true;
int rootValue = *root;
// build binary tree
int childPath;
int temp;
offset = 0;
while((bodyIndex + offset) < n){
if(newBody){
newBody = false;
temp = 0;
childPath = 0;
if(x[bodyIndex + offset] > rootValue){
childPath = 1;
}
}
int childIndex = child[temp*2 + childPath];
// traverse tree until we hit leaf node
while(childIndex >= 0){
temp = childIndex;
childPath = 0;
if(x[bodyIndex + offset] > temp){
childPath = 1;
}
childIndex = child[2*temp + childPath];
}
if(childIndex != -2){
int locked = temp*2 + childPath;
if(atomicCAS(&child[locked], childIndex, -2) == childIndex){
if(childIndex == -1){
child[locked] = x[bodyIndex + offset];
}
offset += stride;
newBody = true;
}
}
__syncthreads(); // not strictly needed
}
}
int main(){
int n = 32;
int *h_x; //host array
int *d_x; //device array
int *h_root;
int *d_root;
int *h_child;
int *d_child;
// allocate memory
h_x = (int*)malloc(n*sizeof(int));
h_root = (int*)malloc(sizeof(int));
h_child = (int*)malloc(2*(n+1)*sizeof(int));
cudaMalloc((void**)&d_root, sizeof(int));
cudaMalloc((void**)&d_x, n*sizeof(int));
cudaMalloc((void**)&d_child, 2*(n+1)*sizeof(int));
cudaMemset(d_child, -1, 2*(n+1)*sizeof(int));
// fill h_temp and h_x arrays
for(int i=0;i<n;i++){
h_x[i] = i+1;
}
// shuffling the array
for(int i=0;i<n;i++){
int j = random() % (n-i);
int temp = h_x[i];
h_x[i] = h_x[i+j];
h_x[i+j] = temp;
}
*h_root = h_x[0];
for(int i=0;i<n;i++){
printf("%d ", h_x[i]);
}
printf("\n");
// copy data to device
cudaMemcpy(d_root, h_root, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_x, h_x, n*sizeof(int), cudaMemcpyHostToDevice);
// kernel call
build_binary_tree<<< 16, 16>>>(d_x, d_child, d_root, n);
// copy from device back to host
cudaMemcpy(h_child, d_child, 2*(n+1)*sizeof(int), cudaMemcpyDeviceToHost);
// print tree
for(int i=0;i<2*(n+1);i++){
printf("%d ", h_child[i]);
}
printf("\n");
// free memory
free(h_x);
free(h_root);
free(h_child);
cudaFree(d_x);
cudaFree(d_root);
cudaFree(d_child);
} | .file "tmpxft_00182bc5_00000000-6_binary_tree.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i
.type _Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i, @function
_Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17build_binary_treePiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i, .-_Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i
.globl _Z17build_binary_treePiS_S_i
.type _Z17build_binary_treePiS_S_i, @function
_Z17build_binary_treePiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z17build_binary_treePiS_S_i, .-_Z17build_binary_treePiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movl $264, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $264, %esi
call cudaMalloc@PLT
movl $264, %edx
movl $-1, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $1, %eax
.L12:
movl %eax, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $33, %rax
jne .L12
movl $0, %ebx
movl $32, %r14d
.L13:
call random@PLT
movl 0(%rbp,%rbx,4), %esi
movq %r14, %rcx
subq %rbx, %rcx
cqto
idivq %rcx
addl %ebx, %edx
movslq %edx, %rdx
leaq 0(%rbp,%rdx,4), %rax
movl (%rax), %edx
movl %edx, 0(%rbp,%rbx,4)
movl %esi, (%rax)
addq $1, %rbx
cmpq $32, %rbx
jne .L13
movl 0(%rbp), %eax
movl %eax, 0(%r13)
movq %rbp, %rbx
leaq 128(%rbp), %r15
leaq .LC0(%rip), %r14
.L14:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $128, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movl $2, %ecx
movl $264, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rbx
leaq 264(%r12), %r15
leaq .LC0(%rip), %r14
.L16:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $32, %ecx
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z17build_binary_treePiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z17build_binary_treePiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void build_binary_tree(int *x, int *child, int *root, int n)
{
int bodyIndex = threadIdx.x + blockIdx.x*blockDim.x;
int stride = blockDim.x*gridDim.x;
int offset = 0;
bool newBody = true;
int rootValue = *root;
// build binary tree
int childPath;
int temp;
offset = 0;
while((bodyIndex + offset) < n){
if(newBody){
newBody = false;
temp = 0;
childPath = 0;
if(x[bodyIndex + offset] > rootValue){
childPath = 1;
}
}
int childIndex = child[temp*2 + childPath];
// traverse tree until we hit leaf node
while(childIndex >= 0){
temp = childIndex;
childPath = 0;
if(x[bodyIndex + offset] > temp){
childPath = 1;
}
childIndex = child[2*temp + childPath];
}
if(childIndex != -2){
int locked = temp*2 + childPath;
if(atomicCAS(&child[locked], childIndex, -2) == childIndex){
if(childIndex == -1){
child[locked] = x[bodyIndex + offset];
}
offset += stride;
newBody = true;
}
}
__syncthreads(); // not strictly needed
}
}
int main(){
int n = 32;
int *h_x; //host array
int *d_x; //device array
int *h_root;
int *d_root;
int *h_child;
int *d_child;
// allocate memory
h_x = (int*)malloc(n*sizeof(int));
h_root = (int*)malloc(sizeof(int));
h_child = (int*)malloc(2*(n+1)*sizeof(int));
cudaMalloc((void**)&d_root, sizeof(int));
cudaMalloc((void**)&d_x, n*sizeof(int));
cudaMalloc((void**)&d_child, 2*(n+1)*sizeof(int));
cudaMemset(d_child, -1, 2*(n+1)*sizeof(int));
// fill h_temp and h_x arrays
for(int i=0;i<n;i++){
h_x[i] = i+1;
}
// shuffling the array
for(int i=0;i<n;i++){
int j = random() % (n-i);
int temp = h_x[i];
h_x[i] = h_x[i+j];
h_x[i+j] = temp;
}
*h_root = h_x[0];
for(int i=0;i<n;i++){
printf("%d ", h_x[i]);
}
printf("\n");
// copy data to device
cudaMemcpy(d_root, h_root, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_x, h_x, n*sizeof(int), cudaMemcpyHostToDevice);
// kernel call
build_binary_tree<<< 16, 16>>>(d_x, d_child, d_root, n);
// copy from device back to host
cudaMemcpy(h_child, d_child, 2*(n+1)*sizeof(int), cudaMemcpyDeviceToHost);
// print tree
for(int i=0;i<2*(n+1);i++){
printf("%d ", h_child[i]);
}
printf("\n");
// free memory
free(h_x);
free(h_root);
free(h_child);
cudaFree(d_x);
cudaFree(d_root);
cudaFree(d_child);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void build_binary_tree(int *x, int *child, int *root, int n)
{
int bodyIndex = threadIdx.x + blockIdx.x*blockDim.x;
int stride = blockDim.x*gridDim.x;
int offset = 0;
bool newBody = true;
int rootValue = *root;
// build binary tree
int childPath;
int temp;
offset = 0;
while((bodyIndex + offset) < n){
if(newBody){
newBody = false;
temp = 0;
childPath = 0;
if(x[bodyIndex + offset] > rootValue){
childPath = 1;
}
}
int childIndex = child[temp*2 + childPath];
// traverse tree until we hit leaf node
while(childIndex >= 0){
temp = childIndex;
childPath = 0;
if(x[bodyIndex + offset] > temp){
childPath = 1;
}
childIndex = child[2*temp + childPath];
}
if(childIndex != -2){
int locked = temp*2 + childPath;
if(atomicCAS(&child[locked], childIndex, -2) == childIndex){
if(childIndex == -1){
child[locked] = x[bodyIndex + offset];
}
offset += stride;
newBody = true;
}
}
__syncthreads(); // not strictly needed
}
}
int main(){
int n = 32;
int *h_x; //host array
int *d_x; //device array
int *h_root;
int *d_root;
int *h_child;
int *d_child;
// allocate memory
h_x = (int*)malloc(n*sizeof(int));
h_root = (int*)malloc(sizeof(int));
h_child = (int*)malloc(2*(n+1)*sizeof(int));
hipMalloc((void**)&d_root, sizeof(int));
hipMalloc((void**)&d_x, n*sizeof(int));
hipMalloc((void**)&d_child, 2*(n+1)*sizeof(int));
hipMemset(d_child, -1, 2*(n+1)*sizeof(int));
// fill h_temp and h_x arrays
for(int i=0;i<n;i++){
h_x[i] = i+1;
}
// shuffling the array
for(int i=0;i<n;i++){
int j = random() % (n-i);
int temp = h_x[i];
h_x[i] = h_x[i+j];
h_x[i+j] = temp;
}
*h_root = h_x[0];
for(int i=0;i<n;i++){
printf("%d ", h_x[i]);
}
printf("\n");
// copy data to device
hipMemcpy(d_root, h_root, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_x, h_x, n*sizeof(int), hipMemcpyHostToDevice);
// kernel call
build_binary_tree<<< 16, 16>>>(d_x, d_child, d_root, n);
// copy from device back to host
hipMemcpy(h_child, d_child, 2*(n+1)*sizeof(int), hipMemcpyDeviceToHost);
// print tree
for(int i=0;i<2*(n+1);i++){
printf("%d ", h_child[i]);
}
printf("\n");
// free memory
free(h_x);
free(h_root);
free(h_child);
hipFree(d_x);
hipFree(d_root);
hipFree(d_child);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void build_binary_tree(int *x, int *child, int *root, int n)
{
int bodyIndex = threadIdx.x + blockIdx.x*blockDim.x;
int stride = blockDim.x*gridDim.x;
int offset = 0;
bool newBody = true;
int rootValue = *root;
// build binary tree
int childPath;
int temp;
offset = 0;
while((bodyIndex + offset) < n){
if(newBody){
newBody = false;
temp = 0;
childPath = 0;
if(x[bodyIndex + offset] > rootValue){
childPath = 1;
}
}
int childIndex = child[temp*2 + childPath];
// traverse tree until we hit leaf node
while(childIndex >= 0){
temp = childIndex;
childPath = 0;
if(x[bodyIndex + offset] > temp){
childPath = 1;
}
childIndex = child[2*temp + childPath];
}
if(childIndex != -2){
int locked = temp*2 + childPath;
if(atomicCAS(&child[locked], childIndex, -2) == childIndex){
if(childIndex == -1){
child[locked] = x[bodyIndex + offset];
}
offset += stride;
newBody = true;
}
}
__syncthreads(); // not strictly needed
}
}
int main(){
int n = 32;
int *h_x; //host array
int *d_x; //device array
int *h_root;
int *d_root;
int *h_child;
int *d_child;
// allocate memory
h_x = (int*)malloc(n*sizeof(int));
h_root = (int*)malloc(sizeof(int));
h_child = (int*)malloc(2*(n+1)*sizeof(int));
hipMalloc((void**)&d_root, sizeof(int));
hipMalloc((void**)&d_x, n*sizeof(int));
hipMalloc((void**)&d_child, 2*(n+1)*sizeof(int));
hipMemset(d_child, -1, 2*(n+1)*sizeof(int));
// fill h_temp and h_x arrays
for(int i=0;i<n;i++){
h_x[i] = i+1;
}
// shuffling the array
for(int i=0;i<n;i++){
int j = random() % (n-i);
int temp = h_x[i];
h_x[i] = h_x[i+j];
h_x[i+j] = temp;
}
*h_root = h_x[0];
for(int i=0;i<n;i++){
printf("%d ", h_x[i]);
}
printf("\n");
// copy data to device
hipMemcpy(d_root, h_root, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_x, h_x, n*sizeof(int), hipMemcpyHostToDevice);
// kernel call
build_binary_tree<<< 16, 16>>>(d_x, d_child, d_root, n);
// copy from device back to host
hipMemcpy(h_child, d_child, 2*(n+1)*sizeof(int), hipMemcpyDeviceToHost);
// print tree
for(int i=0;i<2*(n+1);i++){
printf("%d ", h_child[i]);
}
printf("\n");
// free memory
free(h_x);
free(h_root);
free(h_child);
hipFree(d_x);
hipFree(d_root);
hipFree(d_child);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17build_binary_treePiS_S_i
.globl _Z17build_binary_treePiS_S_i
.p2align 8
.type _Z17build_binary_treePiS_S_i,@function
_Z17build_binary_treePiS_S_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_15
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s7, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v4, -2
v_mov_b32_e32 v6, v1
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[8:9], 0x0
s_mul_i32 s6, s7, s6
s_mov_b32 s8, -1
s_mov_b32 s7, 0
s_branch .LBB0_5
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v0, s6, v0
s_or_b32 s11, s8, exec_lo
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s8, s8, exec_lo
s_and_b32 s10, s11, exec_lo
s_or_b32 s8, s8, s10
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v6, v1, v0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmp_le_i32_e32 vcc_lo, s4, v6
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_15
.LBB0_5:
s_and_saveexec_b32 s9, s8
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v7, 31, v6
v_mov_b32_e32 v10, 0
s_and_not1_b32 s8, s8, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[6:7]
v_add_co_u32 v7, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v2, v[7:8], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, s5, v2
v_cndmask_b32_e64 v11, 0, 1, vcc_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v7, v10, 1, v11
s_mov_b32 s9, exec_lo
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 -1, v5
s_cbranch_execz .LBB0_11
v_ashrrev_i32_e32 v7, 31, v6
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[6:7]
v_add_co_u32 v7, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v7, v[7:8], off
.p2align 6
.LBB0_9:
v_mov_b32_e32 v10, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, v7, v10
v_cndmask_b32_e64 v11, 0, 1, vcc_lo
v_lshl_or_b32 v2, v10, 1, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v5, v[8:9], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 0, v5
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_9
s_or_b32 exec_lo, exec_lo, s10
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s9
s_mov_b32 s9, exec_lo
v_cmpx_ne_u32_e32 -2, v5
s_cbranch_execz .LBB0_4
v_lshl_add_u32 v7, v10, 1, v11
s_mov_b32 s11, s8
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[8:9], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_atomic_cmpswap_b32 v2, v[8:9], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v2, v5
s_cbranch_execz .LBB0_3
s_mov_b32 s11, exec_lo
v_cmpx_eq_u32_e32 -1, v5
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[6:7]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v2, off
s_branch .LBB0_2
.LBB0_15:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17build_binary_treePiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17build_binary_treePiS_S_i, .Lfunc_end0-_Z17build_binary_treePiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17build_binary_treePiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17build_binary_treePiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void build_binary_tree(int *x, int *child, int *root, int n)
{
int bodyIndex = threadIdx.x + blockIdx.x*blockDim.x;
int stride = blockDim.x*gridDim.x;
int offset = 0;
bool newBody = true;
int rootValue = *root;
// build binary tree
int childPath;
int temp;
offset = 0;
while((bodyIndex + offset) < n){
if(newBody){
newBody = false;
temp = 0;
childPath = 0;
if(x[bodyIndex + offset] > rootValue){
childPath = 1;
}
}
int childIndex = child[temp*2 + childPath];
// traverse tree until we hit leaf node
while(childIndex >= 0){
temp = childIndex;
childPath = 0;
if(x[bodyIndex + offset] > temp){
childPath = 1;
}
childIndex = child[2*temp + childPath];
}
if(childIndex != -2){
int locked = temp*2 + childPath;
if(atomicCAS(&child[locked], childIndex, -2) == childIndex){
if(childIndex == -1){
child[locked] = x[bodyIndex + offset];
}
offset += stride;
newBody = true;
}
}
__syncthreads(); // not strictly needed
}
}
int main(){
int n = 32;
int *h_x; //host array
int *d_x; //device array
int *h_root;
int *d_root;
int *h_child;
int *d_child;
// allocate memory
h_x = (int*)malloc(n*sizeof(int));
h_root = (int*)malloc(sizeof(int));
h_child = (int*)malloc(2*(n+1)*sizeof(int));
hipMalloc((void**)&d_root, sizeof(int));
hipMalloc((void**)&d_x, n*sizeof(int));
hipMalloc((void**)&d_child, 2*(n+1)*sizeof(int));
hipMemset(d_child, -1, 2*(n+1)*sizeof(int));
// fill h_temp and h_x arrays
for(int i=0;i<n;i++){
h_x[i] = i+1;
}
// shuffling the array
for(int i=0;i<n;i++){
int j = random() % (n-i);
int temp = h_x[i];
h_x[i] = h_x[i+j];
h_x[i+j] = temp;
}
*h_root = h_x[0];
for(int i=0;i<n;i++){
printf("%d ", h_x[i]);
}
printf("\n");
// copy data to device
hipMemcpy(d_root, h_root, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_x, h_x, n*sizeof(int), hipMemcpyHostToDevice);
// kernel call
build_binary_tree<<< 16, 16>>>(d_x, d_child, d_root, n);
// copy from device back to host
hipMemcpy(h_child, d_child, 2*(n+1)*sizeof(int), hipMemcpyDeviceToHost);
// print tree
for(int i=0;i<2*(n+1);i++){
printf("%d ", h_child[i]);
}
printf("\n");
// free memory
free(h_x);
free(h_root);
free(h_child);
hipFree(d_x);
hipFree(d_root);
hipFree(d_child);
} | .text
.file "binary_tree.hip"
.globl _Z32__device_stub__build_binary_treePiS_S_i # -- Begin function _Z32__device_stub__build_binary_treePiS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__build_binary_treePiS_S_i,@function
_Z32__device_stub__build_binary_treePiS_S_i: # @_Z32__device_stub__build_binary_treePiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17build_binary_treePiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__build_binary_treePiS_S_i, .Lfunc_end0-_Z32__device_stub__build_binary_treePiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $128, %edi
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
movl $264, %edi # imm = 0x108
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $264, %esi # imm = 0x108
callq hipMalloc
movq 8(%rsp), %rdi
movl $264, %edx # imm = 0x108
movl $-1, %esi
callq hipMemset
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $32, %rcx
jne .LBB1_1
# %bb.2: # %.preheader.preheader
movl $32, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
callq random
cqto
idivq %r12
movl (%rbx,%r13,4), %eax
addl %r13d, %edx
movslq %edx, %rcx
movl (%rbx,%rcx,4), %edx
movl %edx, (%rbx,%r13,4)
movl %eax, (%rbx,%rcx,4)
incq %r13
decq %r12
jne .LBB1_3
# %bb.4:
movl (%rbx), %eax
movl %eax, (%r14)
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $32, %r12
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $32, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17build_binary_treePiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
movl $264, %edx # imm = 0x108
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $66, %r12
jne .LBB1_9
# %bb.10:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17build_binary_treePiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17build_binary_treePiS_S_i,@object # @_Z17build_binary_treePiS_S_i
.section .rodata,"a",@progbits
.globl _Z17build_binary_treePiS_S_i
.p2align 3, 0x0
_Z17build_binary_treePiS_S_i:
.quad _Z32__device_stub__build_binary_treePiS_S_i
.size _Z17build_binary_treePiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17build_binary_treePiS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__build_binary_treePiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17build_binary_treePiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17build_binary_treePiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0090*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000162000c1e1900 */
/*00a0*/ HFMA2.MMA R10, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0a7435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fce00078e0000 */
/*00d0*/ LOP3.LUT P0, RZ, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0aff7812 */
/* 0x000fe2000780c0ff */
/*00e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*00f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0100*/ BSSY B0, 0x180 ; /* 0x0000007000007945 */
/* 0x000fe80003800000 */
/*0110*/ IMAD.WIDE R2, R4, R13, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e020d */
/*0120*/ @!P0 BRA 0x170 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0130*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GT.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x024fc80003f04270 */
/*0160*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IMAD R4, R12, 0x2, R11 ; /* 0x000000020c047824 */
/* 0x000fc800078e020b */
/*0190*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e020d */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ BSSY B0, 0x2b0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*01c0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f06270 */
/*01d0*/ @!P0 BRA 0x2a0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*01f0*/ BSSY B1, 0x2a0 ; /* 0x000000a000017945 */
/* 0x000fe40003800000 */
/*0200*/ ISETP.GT.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x020fe20003f04270 */
/*0210*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0004 */
/*0220*/ SHF.L.U32 R8, R4, 0x1, RZ ; /* 0x0000000104087819 */
/* 0x000fe400000006ff */
/*0230*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0240*/ LOP3.LUT R8, R8, 0xfffffffe, R11, 0xe2, !PT ; /* 0xfffffffe08087812 */
/* 0x000fca00078ee20b */
/*0250*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020d */
/*0260*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea4000c1e1900 */
/*0270*/ ISETP.GT.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fda0003f04270 */
/*0280*/ @P0 BRA 0x200 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0290*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.NE.AND P0, PT, R4, -0x2, PT ; /* 0xfffffffe0400780c */
/* 0x000fe40003f05270 */
/*02c0*/ PRMT R10, RZ, 0x7610, R10 ; /* 0x00007610ff0a7816 */
/* 0x000fd6000000000a */
/*02d0*/ @!P0 BRA 0x3b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD R8, R12, 0x2, R11 ; /* 0x000000020c087824 */
/* 0x000fe200078e020b */
/*02f0*/ MOV R5, 0xfffffffe ; /* 0xfffffffe00057802 */
/* 0x000fc60000000f00 */
/*0300*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020d */
/*0310*/ ATOMG.E.CAS.STRONG.GPU PT, R5, [R8], R4, R5 ; /* 0x00000004080573a9 */
/* 0x000ea400001ee105 */
/*0320*/ ISETP.NE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x004fda0003f05270 */
/*0330*/ @P0 BRA 0x3b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x000fe20003f05270 */
/*0350*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe400078e00ff */
/*0360*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fd400078e00ff */
/*0370*/ @P0 BRA 0x3a0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0380*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001ea8000c1e1900 */
/*0390*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x0041e4000c101904 */
/*03a0*/ IMAD R7, R4, c[0x0][0xc], R7 ; /* 0x0000030004077a24 */
/* 0x000fca00078e0207 */
/*03b0*/ IADD3 R4, R0, R7, RZ ; /* 0x0000000700047210 */
/* 0x000fe20007ffe0ff */
/*03c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*03e0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*03f0*/ @!P0 BRA 0xd0 ; /* 0xfffffcd000008947 */
/* 0x000fea000383ffff */
/*0400*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0410*/ BRA 0x410; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17build_binary_treePiS_S_i
.globl _Z17build_binary_treePiS_S_i
.p2align 8
.type _Z17build_binary_treePiS_S_i,@function
_Z17build_binary_treePiS_S_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_15
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s7, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v4, -2
v_mov_b32_e32 v6, v1
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[8:9], 0x0
s_mul_i32 s6, s7, s6
s_mov_b32 s8, -1
s_mov_b32 s7, 0
s_branch .LBB0_5
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v0, s6, v0
s_or_b32 s11, s8, exec_lo
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s8, s8, exec_lo
s_and_b32 s10, s11, exec_lo
s_or_b32 s8, s8, s10
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v6, v1, v0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmp_le_i32_e32 vcc_lo, s4, v6
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_15
.LBB0_5:
s_and_saveexec_b32 s9, s8
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v7, 31, v6
v_mov_b32_e32 v10, 0
s_and_not1_b32 s8, s8, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[6:7]
v_add_co_u32 v7, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v2, v[7:8], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, s5, v2
v_cndmask_b32_e64 v11, 0, 1, vcc_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v7, v10, 1, v11
s_mov_b32 s9, exec_lo
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 -1, v5
s_cbranch_execz .LBB0_11
v_ashrrev_i32_e32 v7, 31, v6
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[6:7]
v_add_co_u32 v7, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v7, v[7:8], off
.p2align 6
.LBB0_9:
v_mov_b32_e32 v10, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, v7, v10
v_cndmask_b32_e64 v11, 0, 1, vcc_lo
v_lshl_or_b32 v2, v10, 1, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v5, v[8:9], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 0, v5
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_9
s_or_b32 exec_lo, exec_lo, s10
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s9
s_mov_b32 s9, exec_lo
v_cmpx_ne_u32_e32 -2, v5
s_cbranch_execz .LBB0_4
v_lshl_add_u32 v7, v10, 1, v11
s_mov_b32 s11, s8
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[8:9], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_atomic_cmpswap_b32 v2, v[8:9], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v2, v5
s_cbranch_execz .LBB0_3
s_mov_b32 s11, exec_lo
v_cmpx_eq_u32_e32 -1, v5
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[6:7]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b32 v2, v[5:6], off
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v2, off
s_branch .LBB0_2
.LBB0_15:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17build_binary_treePiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17build_binary_treePiS_S_i, .Lfunc_end0-_Z17build_binary_treePiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17build_binary_treePiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17build_binary_treePiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00182bc5_00000000-6_binary_tree.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i
.type _Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i, @function
_Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17build_binary_treePiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i, .-_Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i
.globl _Z17build_binary_treePiS_S_i
.type _Z17build_binary_treePiS_S_i, @function
_Z17build_binary_treePiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z17build_binary_treePiS_S_i, .-_Z17build_binary_treePiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $128, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movl $264, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $264, %esi
call cudaMalloc@PLT
movl $264, %edx
movl $-1, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $1, %eax
.L12:
movl %eax, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $33, %rax
jne .L12
movl $0, %ebx
movl $32, %r14d
.L13:
call random@PLT
movl 0(%rbp,%rbx,4), %esi
movq %r14, %rcx
subq %rbx, %rcx
cqto
idivq %rcx
addl %ebx, %edx
movslq %edx, %rdx
leaq 0(%rbp,%rdx,4), %rax
movl (%rax), %edx
movl %edx, 0(%rbp,%rbx,4)
movl %esi, (%rax)
addq $1, %rbx
cmpq $32, %rbx
jne .L13
movl 0(%rbp), %eax
movl %eax, 0(%r13)
movq %rbp, %rbx
leaq 128(%rbp), %r15
leaq .LC0(%rip), %r14
.L14:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $128, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 44(%rsp)
movl $1, 48(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movl $2, %ecx
movl $264, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rbx
leaq 264(%r12), %r15
leaq .LC0(%rip), %r14
.L16:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $32, %ecx
movq 16(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z42__device_stub__Z17build_binary_treePiS_S_iPiS_S_i
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z17build_binary_treePiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z17build_binary_treePiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "binary_tree.hip"
.globl _Z32__device_stub__build_binary_treePiS_S_i # -- Begin function _Z32__device_stub__build_binary_treePiS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__build_binary_treePiS_S_i,@function
_Z32__device_stub__build_binary_treePiS_S_i: # @_Z32__device_stub__build_binary_treePiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17build_binary_treePiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__build_binary_treePiS_S_i, .Lfunc_end0-_Z32__device_stub__build_binary_treePiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $128, %edi
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
movl $264, %edi # imm = 0x108
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $264, %esi # imm = 0x108
callq hipMalloc
movq 8(%rsp), %rdi
movl $264, %edx # imm = 0x108
movl $-1, %esi
callq hipMemset
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $32, %rcx
jne .LBB1_1
# %bb.2: # %.preheader.preheader
movl $32, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
callq random
cqto
idivq %r12
movl (%rbx,%r13,4), %eax
addl %r13d, %edx
movslq %edx, %rcx
movl (%rbx,%rcx,4), %edx
movl %edx, (%rbx,%r13,4)
movl %eax, (%rbx,%rcx,4)
incq %r13
decq %r12
jne .LBB1_3
# %bb.4:
movl (%rbx), %eax
movl %eax, (%r14)
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $32, %r12
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 16(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967312, %rdi # imm = 0x100000010
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $32, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z17build_binary_treePiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
movl $264, %edx # imm = 0x108
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $66, %r12
jne .LBB1_9
# %bb.10:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17build_binary_treePiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17build_binary_treePiS_S_i,@object # @_Z17build_binary_treePiS_S_i
.section .rodata,"a",@progbits
.globl _Z17build_binary_treePiS_S_i
.p2align 3, 0x0
_Z17build_binary_treePiS_S_i:
.quad _Z32__device_stub__build_binary_treePiS_S_i
.size _Z17build_binary_treePiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17build_binary_treePiS_S_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__build_binary_treePiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17build_binary_treePiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime_api.h>
#include <iostream>
__global__ void HelloGPU()
{
// Print a simple message from the GPU
printf("Hello from the GPU!\n");
}
int main()
{
std::cout << "==== Sample 01 - Hello GPU ====\n" << std::endl;
// Expected output: 12x "Hello from the GPU!\n"
// Launch a kernel with 1 block that has 12 threads
HelloGPU<<<1, 12>>>();
/*
Synchronize with GPU to wait for printf to finish.
Results of printf are buffered and copied back to
the CPU for I/O after the kernel has finished.
*/
cudaDeviceSynchronize();
return 0;
}
/*
Exercises:
1) Change the message that is printed by the kernel
2) Write a different kernel (different name, different message)
3) Call the different kernels multiple times
*/ | code for sm_80
Function : _Z8HelloGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime_api.h>
#include <iostream>
__global__ void HelloGPU()
{
// Print a simple message from the GPU
printf("Hello from the GPU!\n");
}
int main()
{
std::cout << "==== Sample 01 - Hello GPU ====\n" << std::endl;
// Expected output: 12x "Hello from the GPU!\n"
// Launch a kernel with 1 block that has 12 threads
HelloGPU<<<1, 12>>>();
/*
Synchronize with GPU to wait for printf to finish.
Results of printf are buffered and copied back to
the CPU for I/O after the kernel has finished.
*/
cudaDeviceSynchronize();
return 0;
}
/*
Exercises:
1) Change the message that is printed by the kernel
2) Write a different kernel (different name, different message)
3) Call the different kernels multiple times
*/ | .file "tmpxft_000ee954_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8HelloGPUvv
.type _Z26__device_stub__Z8HelloGPUvv, @function
_Z26__device_stub__Z8HelloGPUvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8HelloGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z8HelloGPUvv, .-_Z26__device_stub__Z8HelloGPUvv
.globl _Z8HelloGPUv
.type _Z8HelloGPUv, @function
_Z8HelloGPUv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8HelloGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8HelloGPUv, .-_Z8HelloGPUv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "==== Sample 01 - Hello GPU ====\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $12, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8HelloGPUvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z8HelloGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8HelloGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime_api.h>
#include <iostream>
__global__ void HelloGPU()
{
// Print a simple message from the GPU
printf("Hello from the GPU!\n");
}
int main()
{
std::cout << "==== Sample 01 - Hello GPU ====\n" << std::endl;
// Expected output: 12x "Hello from the GPU!\n"
// Launch a kernel with 1 block that has 12 threads
HelloGPU<<<1, 12>>>();
/*
Synchronize with GPU to wait for printf to finish.
Results of printf are buffered and copied back to
the CPU for I/O after the kernel has finished.
*/
cudaDeviceSynchronize();
return 0;
}
/*
Exercises:
1) Change the message that is printed by the kernel
2) Write a different kernel (different name, different message)
3) Call the different kernels multiple times
*/ | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
__global__ void HelloGPU()
{
// Print a simple message from the GPU
printf("Hello from the GPU!\n");
}
int main()
{
std::cout << "==== Sample 01 - Hello GPU ====\n" << std::endl;
// Expected output: 12x "Hello from the GPU!\n"
// Launch a kernel with 1 block that has 12 threads
HelloGPU<<<1, 12>>>();
/*
Synchronize with GPU to wait for printf to finish.
Results of printf are buffered and copied back to
the CPU for I/O after the kernel has finished.
*/
hipDeviceSynchronize();
return 0;
}
/*
Exercises:
1) Change the message that is printed by the kernel
2) Write a different kernel (different name, different message)
3) Call the different kernels multiple times
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
__global__ void HelloGPU()
{
// Print a simple message from the GPU
printf("Hello from the GPU!\n");
}
int main()
{
std::cout << "==== Sample 01 - Hello GPU ====\n" << std::endl;
// Expected output: 12x "Hello from the GPU!\n"
// Launch a kernel with 1 block that has 12 threads
HelloGPU<<<1, 12>>>();
/*
Synchronize with GPU to wait for printf to finish.
Results of printf are buffered and copied back to
the CPU for I/O after the kernel has finished.
*/
hipDeviceSynchronize();
return 0;
}
/*
Exercises:
1) Change the message that is printed by the kernel
2) Write a different kernel (different name, different message)
3) Call the different kernels multiple times
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8HelloGPUv
.globl _Z8HelloGPUv
.p2align 8
.type _Z8HelloGPUv,@function
_Z8HelloGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 21
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8HelloGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8HelloGPUv, .Lfunc_end0-_Z8HelloGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello from the GPU!\n"
.size .str, 21
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8HelloGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z8HelloGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
__global__ void HelloGPU()
{
// Print a simple message from the GPU
printf("Hello from the GPU!\n");
}
int main()
{
std::cout << "==== Sample 01 - Hello GPU ====\n" << std::endl;
// Expected output: 12x "Hello from the GPU!\n"
// Launch a kernel with 1 block that has 12 threads
HelloGPU<<<1, 12>>>();
/*
Synchronize with GPU to wait for printf to finish.
Results of printf are buffered and copied back to
the CPU for I/O after the kernel has finished.
*/
hipDeviceSynchronize();
return 0;
}
/*
Exercises:
1) Change the message that is printed by the kernel
2) Write a different kernel (different name, different message)
3) Call the different kernels multiple times
*/ | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__HelloGPUv # -- Begin function _Z23__device_stub__HelloGPUv
.p2align 4, 0x90
.type _Z23__device_stub__HelloGPUv,@function
_Z23__device_stub__HelloGPUv: # @_Z23__device_stub__HelloGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8HelloGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__HelloGPUv, .Lfunc_end0-_Z23__device_stub__HelloGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 11(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8HelloGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8HelloGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8HelloGPUv,@object # @_Z8HelloGPUv
.section .rodata,"a",@progbits
.globl _Z8HelloGPUv
.p2align 3, 0x0
_Z8HelloGPUv:
.quad _Z23__device_stub__HelloGPUv
.size _Z8HelloGPUv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "==== Sample 01 - Hello GPU ====\n"
.size .L.str, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8HelloGPUv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__HelloGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8HelloGPUv
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8HelloGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8HelloGPUv
.globl _Z8HelloGPUv
.p2align 8
.type _Z8HelloGPUv,@function
_Z8HelloGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 21
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8HelloGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8HelloGPUv, .Lfunc_end0-_Z8HelloGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello from the GPU!\n"
.size .str, 21
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8HelloGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z8HelloGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ee954_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8HelloGPUvv
.type _Z26__device_stub__Z8HelloGPUvv, @function
_Z26__device_stub__Z8HelloGPUvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8HelloGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z8HelloGPUvv, .-_Z26__device_stub__Z8HelloGPUvv
.globl _Z8HelloGPUv
.type _Z8HelloGPUv, @function
_Z8HelloGPUv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8HelloGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8HelloGPUv, .-_Z8HelloGPUv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "==== Sample 01 - Hello GPU ====\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $12, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8HelloGPUvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z8HelloGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8HelloGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__HelloGPUv # -- Begin function _Z23__device_stub__HelloGPUv
.p2align 4, 0x90
.type _Z23__device_stub__HelloGPUv,@function
_Z23__device_stub__HelloGPUv: # @_Z23__device_stub__HelloGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8HelloGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__HelloGPUv, .Lfunc_end0-_Z23__device_stub__HelloGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 11(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8HelloGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8HelloGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8HelloGPUv,@object # @_Z8HelloGPUv
.section .rodata,"a",@progbits
.globl _Z8HelloGPUv
.p2align 3, 0x0
_Z8HelloGPUv:
.quad _Z23__device_stub__HelloGPUv
.size _Z8HelloGPUv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "==== Sample 01 - Hello GPU ====\n"
.size .L.str, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8HelloGPUv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__HelloGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8HelloGPUv
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // counting Hamilton cycle, CUDA acceleration
#include<stdio.h>
#include<stdlib.h>
#define MAX_BLOCK_SIZE 1024
#define MAX_ARRAY_SIZE (1024*8)
// any 2 <= mod <= 2^31 should work
__host__ __device__ unsigned mod_sum(unsigned a, unsigned b, unsigned mod) {
unsigned c = a+b;
return c >= mod ? c-mod : c;
}
__global__ void ha2(int n, int work, unsigned *part, int *adj, unsigned *ret, unsigned int mod) {
__shared__ unsigned qc[1024];
__shared__ unsigned ai[32];
int k = blockDim.x;
int tid = threadIdx.x;
int sha = threadIdx.y * k;
int bid = threadIdx.y + blockIdx.x * blockDim.y;
int gridSize = blockDim.y * gridDim.x;
unsigned s = part[bid];
unsigned mask = (1u<<k) - 1;
unsigned total = 0;
for (int i = tid+sha; i < n; i += blockDim.y * k) {
unsigned aa = 0;
for (int j = 0; j < n; j++) {
aa = aa | adj[i * n + j] << j;
}
ai[i] = aa;
}
__syncthreads();
for (int runs = 0; runs < work; runs += gridSize) {
// first transition
unsigned row = s;
for (int i = 0; i < tid; i++) {
row = row & (row-1);
}
unsigned at = __ffs(row)-1;
row = 0;
{
unsigned me = ai[at];
for (int i = n-2; i >= 0; i--) {
if (s>>i & 1) {
row = row + row + (me>>i & 1);
}
}
qc[tid+sha] = (me >> (n-1)) & 1;
__syncthreads();
}
// calculate each transition, uses GPU SIMD feature
for (int t = 1; t < n-1; t++) {
unsigned sum = 0;
for (int i = 0; i < k; i++) {
sum = mod_sum(sum, qc[i+sha] * (row>>i & 1), mod);
}
__syncthreads();
qc[tid+sha] = sum;
__syncthreads();
}
// last transition
{
if (!(ai[n-1] >> at & 1)) qc[tid+sha] = 0;
__syncthreads();
unsigned count = 0;
for (int i = 0; i < k; i++) {
count = mod_sum(count, qc[i+sha], mod);
}
//if (tid==0) printf("[%d:%d],", s, count);
if (runs + bid < work) {
total = mod_sum(count, total, mod);
}
}
unsigned bit = s & (-s);
s += bit;
s |= mask >> __popc(s);
__syncthreads();
}
if (tid == 0) {
// output total for this block
ret[bid] = total;
}
}
int n;
int adj[1024];
unsigned part[MAX_ARRAY_SIZE];
unsigned ret[MAX_ARRAY_SIZE];
int nCr[33][33];
unsigned getComb(int idx, int n, int r) {
unsigned ans = 0;
n -= 1;
while (r > 0) {
if (idx < nCr[n][r]) n -= 1;
else {
ans |= 1u<<(n);
idx -= nCr[n][r];
n -= 1;
r -= 1;
}
}
return ans;
}
int main() {
int *gpu_adj;
unsigned *gpu_part, *gpu_ret;
scanf("%d", &n);
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (i != j) adj[i*n+j] = rand()>>5&1;
}
}
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) scanf("%d", &adj[i*n+j]);
}
for (int i = 0; i <= 32; i++) {
nCr[i][0] = nCr[i][i] = 1;
for (int j = 1; j < i; j++) nCr[i][j] = nCr[i-1][j-1] + nCr[i-1][j];
}
cudaMalloc(&gpu_part, sizeof part);
cudaMalloc(&gpu_adj, sizeof adj);
cudaMalloc(&gpu_ret, sizeof ret);
cudaMemcpy(gpu_adj, adj, sizeof adj, cudaMemcpyHostToDevice);
unsigned ans = 0;
unsigned mod = 0;
for (int k = 1; k <= n-1; k++) {
int wo = nCr[n-1][k];
int blockSize = wo;
if (blockSize > MAX_BLOCK_SIZE / k) blockSize = MAX_BLOCK_SIZE / k;
int gridSize = wo / blockSize;
if (blockSize * gridSize > MAX_ARRAY_SIZE) gridSize = MAX_ARRAY_SIZE / blockSize;
int totSize = blockSize * gridSize;
printf("block size = (%d,%d,1) grid size = (%d,1,1)\n", k, blockSize, gridSize);
//for (int j = 0; j < wo; j++) printf("%d,", getComb(j, n-1, k));
for (int j = 0; j < totSize; j++) {
int step = wo / totSize * j;
if (j < wo % totSize) step += j;
else step += wo % totSize;
//printf("step=%d\n", step);
part[j] = getComb(step, n-1, k);
}
cudaMemcpy(gpu_part, part, sizeof(int) * totSize, cudaMemcpyHostToDevice);
ha2<<<gridSize, dim3(k, blockSize)>>>(n, wo, gpu_part, gpu_adj, gpu_ret, mod);
cudaDeviceSynchronize();
cudaMemcpy(ret, gpu_ret, sizeof(int) * totSize, cudaMemcpyDeviceToHost);
unsigned sum = 0;
for (int j = 0; j < totSize; j++) {
sum = mod_sum(sum, ret[j], 0);
}
printf("sum = %u\n", sum);
if ((n-k)%2 == 1) ans = mod_sum(ans, sum, mod);
else if (sum != 0) ans = mod_sum(ans, mod-sum, mod);
}
printf("ans = %u\n", ans);
cudaFree(gpu_ret);
cudaFree(gpu_adj);
cudaFree(gpu_part);
} | .file "tmpxft_0012cad9_00000000-6_ha2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7mod_sumjjj
.type _Z7mod_sumjjj, @function
_Z7mod_sumjjj:
.LFB2057:
.cfi_startproc
endbr64
leal (%rdi,%rsi), %eax
movl %eax, %ecx
subl %edx, %ecx
cmpl %edx, %eax
cmovnb %ecx, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z7mod_sumjjj, .-_Z7mod_sumjjj
.globl _Z7getCombiii
.type _Z7getCombiii, @function
_Z7getCombiii:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L10
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %r9d
movl %edx, %r8d
subl $2, %esi
movl $0, %r10d
leaq nCr(%rip), %r11
movl $1, %ebx
jmp .L9
.L7:
movl %ebx, %edx
sall %cl, %edx
orl %edx, %r10d
subl %eax, %r9d
subl $1, %r8d
subl $1, %esi
testl %r8d, %r8d
jle .L15
.L9:
leal 1(%rsi), %ecx
movslq %r8d, %rdx
movslq %ecx, %rdi
movq %rdi, %rax
salq $5, %rax
addq %rdi, %rax
addq %rdx, %rax
movl (%r11,%rax,4), %eax
cmpl %r9d, %eax
jle .L7
subl $1, %esi
jmp .L9
.L10:
.cfi_def_cfa_offset 8
.cfi_restore 3
movl $0, %r10d
movl %r10d, %eax
ret
.L15:
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %r10d, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7getCombiii, .-_Z7getCombiii
.globl _Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
.type _Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j, @function
_Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3ha2iiPjPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j, .-_Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
.globl _Z3ha2iiPjPiS_j
.type _Z3ha2iiPjPiS_j, @function
_Z3ha2iiPjPiS_j:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3ha2iiPjPiS_j, .-_Z3ha2iiPjPiS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "block size = (%d,%d,1) grid size = (%d,1,1)\n"
.section .rodata.str1.1
.LC2:
.string "sum = %u\n"
.LC3:
.string "ans = %u\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq n(%rip), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl $0, %ebp
leaq adj(%rip), %r12
cmpl $0, n(%rip)
jg .L25
.L26:
leaq nCr(%rip), %r10
movq %r10, %rdi
movq %r10, %r8
movl $0, %r9d
movl $0, %esi
addq $4, %r10
jmp .L37
.L70:
call rand@PLT
movl %ebp, %edx
imull n(%rip), %edx
addl %ebx, %edx
movslq %edx, %rdx
sarl $5, %eax
andl $1, %eax
movl %eax, (%r12,%rdx,4)
.L27:
addl $1, %ebx
cmpl %ebx, n(%rip)
jle .L30
.L28:
cmpl %ebx, %ebp
je .L27
jmp .L70
.L30:
addl $1, %ebp
movl n(%rip), %eax
cmpl %ebp, %eax
jle .L29
.L25:
movl $0, %ebx
cmpl $0, n(%rip)
jg .L28
jmp .L30
.L29:
testl %eax, %eax
jle .L26
movl $0, %ebp
leaq adj(%rip), %r13
leaq .LC0(%rip), %r12
jmp .L31
.L32:
imull %ebp, %eax
addl %ebx, %eax
cltq
leaq 0(%r13,%rax,4), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl n(%rip), %eax
cmpl %ebx, %eax
jg .L32
.L33:
addl $1, %ebp
cmpl %ebp, n(%rip)
jle .L26
.L31:
movl n(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L32
jmp .L33
.L39:
movl 28(%rsp), %r8d
movl %r8d, %esi
movl 36(%rsp), %ecx
imull %ecx, %esi
movl %esi, %ebx
movl %esi, 32(%rsp)
movl %r13d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L40
movl 44(%rsp), %eax
cltd
idivl %ebx
movl %eax, %r14d
movl n(%rip), %eax
subl $1, %eax
movl %eax, 24(%rsp)
leal 1(%r14), %r15d
movl %edx, %r12d
movslq %ebx, %rax
movq %rax, 16(%rsp)
movl $0, %ebp
movl $0, %ebx
movl %r13d, 12(%rsp)
movl %edx, %r13d
.L43:
cmpl %ebx, %r13d
movl %ebp, %edi
cmovle %r12d, %edi
movl 12(%rsp), %edx
movl 24(%rsp), %esi
call _Z7getCombiii
leaq part(%rip), %rcx
movl %eax, (%rcx,%rbx,4)
addq $1, %rbx
addl %r15d, %ebp
addl %r14d, %r12d
movq 16(%rsp), %rax
cmpq %rax, %rbx
jne .L43
movl 12(%rsp), %r13d
.L40:
movslq 32(%rsp), %rbx
salq $2, %rbx
movl $1, %ecx
movq %rbx, %rdx
leaq part(%rip), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 80(%rsp)
movl 36(%rsp), %eax
movl %eax, 84(%rsp)
movl 28(%rsp), %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L71
.L44:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
leaq ret(%rip), %rdi
call cudaMemcpy@PLT
cmpl $0, 32(%rsp)
jle .L57
leaq ret(%rip), %rax
addq %rax, %rbx
movl $0, %ebp
.L46:
addl (%rax), %ebp
addq $4, %rax
cmpq %rax, %rbx
jne .L46
.L45:
movl %ebp, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl n(%rip), %eax
movl %eax, %edx
subl %r13d, %edx
movl %edx, %ecx
shrl $31, %ecx
addl %ecx, %edx
andl $1, %edx
subl %ecx, %edx
movl 40(%rsp), %edi
leal (%rdi,%rbp), %ecx
subl %ebp, %edi
cmpl $1, %edx
cmovne %edi, %ecx
movl %ecx, 40(%rsp)
addl $1, %r13d
cmpl %r13d, %eax
jle .L38
.L49:
movslq %r13d, %rcx
subl $1, %eax
cltq
movq %rax, %rdx
salq $5, %rdx
addq %rdx, %rax
addq %rcx, %rax
leaq nCr(%rip), %rsi
movl (%rsi,%rax,4), %esi
movl %esi, 44(%rsp)
movl $1024, %eax
movl $0, %edx
idivl %r13d
cmpl %esi, %eax
movl %eax, %ecx
movl %esi, %eax
cmovg %esi, %ecx
movl %ecx, 36(%rsp)
cltd
idivl %ecx
movl %eax, 28(%rsp)
imull %ecx, %eax
cmpl $8192, %eax
jle .L39
movl $8192, %eax
movl $0, %edx
idivl %ecx
movl %eax, 28(%rsp)
jmp .L39
.L71:
movl $0, %r9d
movq 72(%rsp), %r8
movq 56(%rsp), %rcx
movq 64(%rsp), %rdx
movl 44(%rsp), %esi
movl n(%rip), %edi
call _Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
jmp .L44
.L57:
movl $0, %ebp
jmp .L45
.L56:
movl $0, 40(%rsp)
.L38:
movl 40(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L72
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
addl $1, %esi
addq $136, %r8
addq $132, %rdi
addq $33, %r9
.L37:
movl $1, (%r8)
movl $1, (%rdi)
cmpl $1, %esi
jle .L34
leal -2(%rsi), %eax
addq %r9, %rax
leaq (%r10,%rax,4), %rcx
movq %rdi, %rax
.L35:
movl -128(%rax), %edx
addl -132(%rax), %edx
movl %edx, 4(%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L35
addl $1, %esi
addq $136, %r8
addq $132, %rdi
addq $33, %r9
cmpl $33, %esi
jne .L37
leaq 64(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
leaq adj(%rip), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl n(%rip), %eax
cmpl $1, %eax
jle .L56
movl $1, %r13d
movl $0, 40(%rsp)
jmp .L49
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3ha2iiPjPiS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3ha2iiPjPiS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl nCr
.bss
.align 32
.type nCr, @object
.size nCr, 4356
nCr:
.zero 4356
.globl ret
.align 32
.type ret, @object
.size ret, 32768
ret:
.zero 32768
.globl part
.align 32
.type part, @object
.size part, 32768
part:
.zero 32768
.globl adj
.align 32
.type adj, @object
.size adj, 4096
adj:
.zero 4096
.globl n
.align 4
.type n, @object
.size n, 4
n:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // counting Hamilton cycle, CUDA acceleration
#include<stdio.h>
#include<stdlib.h>
#define MAX_BLOCK_SIZE 1024
#define MAX_ARRAY_SIZE (1024*8)
// any 2 <= mod <= 2^31 should work
__host__ __device__ unsigned mod_sum(unsigned a, unsigned b, unsigned mod) {
unsigned c = a+b;
return c >= mod ? c-mod : c;
}
__global__ void ha2(int n, int work, unsigned *part, int *adj, unsigned *ret, unsigned int mod) {
__shared__ unsigned qc[1024];
__shared__ unsigned ai[32];
int k = blockDim.x;
int tid = threadIdx.x;
int sha = threadIdx.y * k;
int bid = threadIdx.y + blockIdx.x * blockDim.y;
int gridSize = blockDim.y * gridDim.x;
unsigned s = part[bid];
unsigned mask = (1u<<k) - 1;
unsigned total = 0;
for (int i = tid+sha; i < n; i += blockDim.y * k) {
unsigned aa = 0;
for (int j = 0; j < n; j++) {
aa = aa | adj[i * n + j] << j;
}
ai[i] = aa;
}
__syncthreads();
for (int runs = 0; runs < work; runs += gridSize) {
// first transition
unsigned row = s;
for (int i = 0; i < tid; i++) {
row = row & (row-1);
}
unsigned at = __ffs(row)-1;
row = 0;
{
unsigned me = ai[at];
for (int i = n-2; i >= 0; i--) {
if (s>>i & 1) {
row = row + row + (me>>i & 1);
}
}
qc[tid+sha] = (me >> (n-1)) & 1;
__syncthreads();
}
// calculate each transition, uses GPU SIMD feature
for (int t = 1; t < n-1; t++) {
unsigned sum = 0;
for (int i = 0; i < k; i++) {
sum = mod_sum(sum, qc[i+sha] * (row>>i & 1), mod);
}
__syncthreads();
qc[tid+sha] = sum;
__syncthreads();
}
// last transition
{
if (!(ai[n-1] >> at & 1)) qc[tid+sha] = 0;
__syncthreads();
unsigned count = 0;
for (int i = 0; i < k; i++) {
count = mod_sum(count, qc[i+sha], mod);
}
//if (tid==0) printf("[%d:%d],", s, count);
if (runs + bid < work) {
total = mod_sum(count, total, mod);
}
}
unsigned bit = s & (-s);
s += bit;
s |= mask >> __popc(s);
__syncthreads();
}
if (tid == 0) {
// output total for this block
ret[bid] = total;
}
}
int n;
int adj[1024];
unsigned part[MAX_ARRAY_SIZE];
unsigned ret[MAX_ARRAY_SIZE];
int nCr[33][33];
unsigned getComb(int idx, int n, int r) {
unsigned ans = 0;
n -= 1;
while (r > 0) {
if (idx < nCr[n][r]) n -= 1;
else {
ans |= 1u<<(n);
idx -= nCr[n][r];
n -= 1;
r -= 1;
}
}
return ans;
}
int main() {
int *gpu_adj;
unsigned *gpu_part, *gpu_ret;
scanf("%d", &n);
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (i != j) adj[i*n+j] = rand()>>5&1;
}
}
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) scanf("%d", &adj[i*n+j]);
}
for (int i = 0; i <= 32; i++) {
nCr[i][0] = nCr[i][i] = 1;
for (int j = 1; j < i; j++) nCr[i][j] = nCr[i-1][j-1] + nCr[i-1][j];
}
cudaMalloc(&gpu_part, sizeof part);
cudaMalloc(&gpu_adj, sizeof adj);
cudaMalloc(&gpu_ret, sizeof ret);
cudaMemcpy(gpu_adj, adj, sizeof adj, cudaMemcpyHostToDevice);
unsigned ans = 0;
unsigned mod = 0;
for (int k = 1; k <= n-1; k++) {
int wo = nCr[n-1][k];
int blockSize = wo;
if (blockSize > MAX_BLOCK_SIZE / k) blockSize = MAX_BLOCK_SIZE / k;
int gridSize = wo / blockSize;
if (blockSize * gridSize > MAX_ARRAY_SIZE) gridSize = MAX_ARRAY_SIZE / blockSize;
int totSize = blockSize * gridSize;
printf("block size = (%d,%d,1) grid size = (%d,1,1)\n", k, blockSize, gridSize);
//for (int j = 0; j < wo; j++) printf("%d,", getComb(j, n-1, k));
for (int j = 0; j < totSize; j++) {
int step = wo / totSize * j;
if (j < wo % totSize) step += j;
else step += wo % totSize;
//printf("step=%d\n", step);
part[j] = getComb(step, n-1, k);
}
cudaMemcpy(gpu_part, part, sizeof(int) * totSize, cudaMemcpyHostToDevice);
ha2<<<gridSize, dim3(k, blockSize)>>>(n, wo, gpu_part, gpu_adj, gpu_ret, mod);
cudaDeviceSynchronize();
cudaMemcpy(ret, gpu_ret, sizeof(int) * totSize, cudaMemcpyDeviceToHost);
unsigned sum = 0;
for (int j = 0; j < totSize; j++) {
sum = mod_sum(sum, ret[j], 0);
}
printf("sum = %u\n", sum);
if ((n-k)%2 == 1) ans = mod_sum(ans, sum, mod);
else if (sum != 0) ans = mod_sum(ans, mod-sum, mod);
}
printf("ans = %u\n", ans);
cudaFree(gpu_ret);
cudaFree(gpu_adj);
cudaFree(gpu_part);
} | // counting Hamilton cycle, CUDA acceleration
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#define MAX_BLOCK_SIZE 1024
#define MAX_ARRAY_SIZE (1024*8)
// any 2 <= mod <= 2^31 should work
__host__ __device__ unsigned mod_sum(unsigned a, unsigned b, unsigned mod) {
unsigned c = a+b;
return c >= mod ? c-mod : c;
}
__global__ void ha2(int n, int work, unsigned *part, int *adj, unsigned *ret, unsigned int mod) {
__shared__ unsigned qc[1024];
__shared__ unsigned ai[32];
int k = blockDim.x;
int tid = threadIdx.x;
int sha = threadIdx.y * k;
int bid = threadIdx.y + blockIdx.x * blockDim.y;
int gridSize = blockDim.y * gridDim.x;
unsigned s = part[bid];
unsigned mask = (1u<<k) - 1;
unsigned total = 0;
for (int i = tid+sha; i < n; i += blockDim.y * k) {
unsigned aa = 0;
for (int j = 0; j < n; j++) {
aa = aa | adj[i * n + j] << j;
}
ai[i] = aa;
}
__syncthreads();
for (int runs = 0; runs < work; runs += gridSize) {
// first transition
unsigned row = s;
for (int i = 0; i < tid; i++) {
row = row & (row-1);
}
unsigned at = __ffs(row)-1;
row = 0;
{
unsigned me = ai[at];
for (int i = n-2; i >= 0; i--) {
if (s>>i & 1) {
row = row + row + (me>>i & 1);
}
}
qc[tid+sha] = (me >> (n-1)) & 1;
__syncthreads();
}
// calculate each transition, uses GPU SIMD feature
for (int t = 1; t < n-1; t++) {
unsigned sum = 0;
for (int i = 0; i < k; i++) {
sum = mod_sum(sum, qc[i+sha] * (row>>i & 1), mod);
}
__syncthreads();
qc[tid+sha] = sum;
__syncthreads();
}
// last transition
{
if (!(ai[n-1] >> at & 1)) qc[tid+sha] = 0;
__syncthreads();
unsigned count = 0;
for (int i = 0; i < k; i++) {
count = mod_sum(count, qc[i+sha], mod);
}
//if (tid==0) printf("[%d:%d],", s, count);
if (runs + bid < work) {
total = mod_sum(count, total, mod);
}
}
unsigned bit = s & (-s);
s += bit;
s |= mask >> __popc(s);
__syncthreads();
}
if (tid == 0) {
// output total for this block
ret[bid] = total;
}
}
int n;
int adj[1024];
unsigned part[MAX_ARRAY_SIZE];
unsigned ret[MAX_ARRAY_SIZE];
int nCr[33][33];
unsigned getComb(int idx, int n, int r) {
unsigned ans = 0;
n -= 1;
while (r > 0) {
if (idx < nCr[n][r]) n -= 1;
else {
ans |= 1u<<(n);
idx -= nCr[n][r];
n -= 1;
r -= 1;
}
}
return ans;
}
int main() {
int *gpu_adj;
unsigned *gpu_part, *gpu_ret;
scanf("%d", &n);
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (i != j) adj[i*n+j] = rand()>>5&1;
}
}
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) scanf("%d", &adj[i*n+j]);
}
for (int i = 0; i <= 32; i++) {
nCr[i][0] = nCr[i][i] = 1;
for (int j = 1; j < i; j++) nCr[i][j] = nCr[i-1][j-1] + nCr[i-1][j];
}
hipMalloc(&gpu_part, sizeof part);
hipMalloc(&gpu_adj, sizeof adj);
hipMalloc(&gpu_ret, sizeof ret);
hipMemcpy(gpu_adj, adj, sizeof adj, hipMemcpyHostToDevice);
unsigned ans = 0;
unsigned mod = 0;
for (int k = 1; k <= n-1; k++) {
int wo = nCr[n-1][k];
int blockSize = wo;
if (blockSize > MAX_BLOCK_SIZE / k) blockSize = MAX_BLOCK_SIZE / k;
int gridSize = wo / blockSize;
if (blockSize * gridSize > MAX_ARRAY_SIZE) gridSize = MAX_ARRAY_SIZE / blockSize;
int totSize = blockSize * gridSize;
printf("block size = (%d,%d,1) grid size = (%d,1,1)\n", k, blockSize, gridSize);
//for (int j = 0; j < wo; j++) printf("%d,", getComb(j, n-1, k));
for (int j = 0; j < totSize; j++) {
int step = wo / totSize * j;
if (j < wo % totSize) step += j;
else step += wo % totSize;
//printf("step=%d\n", step);
part[j] = getComb(step, n-1, k);
}
hipMemcpy(gpu_part, part, sizeof(int) * totSize, hipMemcpyHostToDevice);
ha2<<<gridSize, dim3(k, blockSize)>>>(n, wo, gpu_part, gpu_adj, gpu_ret, mod);
hipDeviceSynchronize();
hipMemcpy(ret, gpu_ret, sizeof(int) * totSize, hipMemcpyDeviceToHost);
unsigned sum = 0;
for (int j = 0; j < totSize; j++) {
sum = mod_sum(sum, ret[j], 0);
}
printf("sum = %u\n", sum);
if ((n-k)%2 == 1) ans = mod_sum(ans, sum, mod);
else if (sum != 0) ans = mod_sum(ans, mod-sum, mod);
}
printf("ans = %u\n", ans);
hipFree(gpu_ret);
hipFree(gpu_adj);
hipFree(gpu_part);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // counting Hamilton cycle, CUDA acceleration
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#define MAX_BLOCK_SIZE 1024
#define MAX_ARRAY_SIZE (1024*8)
// any 2 <= mod <= 2^31 should work
__host__ __device__ unsigned mod_sum(unsigned a, unsigned b, unsigned mod) {
unsigned c = a+b;
return c >= mod ? c-mod : c;
}
__global__ void ha2(int n, int work, unsigned *part, int *adj, unsigned *ret, unsigned int mod) {
__shared__ unsigned qc[1024];
__shared__ unsigned ai[32];
int k = blockDim.x;
int tid = threadIdx.x;
int sha = threadIdx.y * k;
int bid = threadIdx.y + blockIdx.x * blockDim.y;
int gridSize = blockDim.y * gridDim.x;
unsigned s = part[bid];
unsigned mask = (1u<<k) - 1;
unsigned total = 0;
for (int i = tid+sha; i < n; i += blockDim.y * k) {
unsigned aa = 0;
for (int j = 0; j < n; j++) {
aa = aa | adj[i * n + j] << j;
}
ai[i] = aa;
}
__syncthreads();
for (int runs = 0; runs < work; runs += gridSize) {
// first transition
unsigned row = s;
for (int i = 0; i < tid; i++) {
row = row & (row-1);
}
unsigned at = __ffs(row)-1;
row = 0;
{
unsigned me = ai[at];
for (int i = n-2; i >= 0; i--) {
if (s>>i & 1) {
row = row + row + (me>>i & 1);
}
}
qc[tid+sha] = (me >> (n-1)) & 1;
__syncthreads();
}
// calculate each transition, uses GPU SIMD feature
for (int t = 1; t < n-1; t++) {
unsigned sum = 0;
for (int i = 0; i < k; i++) {
sum = mod_sum(sum, qc[i+sha] * (row>>i & 1), mod);
}
__syncthreads();
qc[tid+sha] = sum;
__syncthreads();
}
// last transition
{
if (!(ai[n-1] >> at & 1)) qc[tid+sha] = 0;
__syncthreads();
unsigned count = 0;
for (int i = 0; i < k; i++) {
count = mod_sum(count, qc[i+sha], mod);
}
//if (tid==0) printf("[%d:%d],", s, count);
if (runs + bid < work) {
total = mod_sum(count, total, mod);
}
}
unsigned bit = s & (-s);
s += bit;
s |= mask >> __popc(s);
__syncthreads();
}
if (tid == 0) {
// output total for this block
ret[bid] = total;
}
}
int n;
int adj[1024];
unsigned part[MAX_ARRAY_SIZE];
unsigned ret[MAX_ARRAY_SIZE];
int nCr[33][33];
unsigned getComb(int idx, int n, int r) {
unsigned ans = 0;
n -= 1;
while (r > 0) {
if (idx < nCr[n][r]) n -= 1;
else {
ans |= 1u<<(n);
idx -= nCr[n][r];
n -= 1;
r -= 1;
}
}
return ans;
}
int main() {
int *gpu_adj;
unsigned *gpu_part, *gpu_ret;
scanf("%d", &n);
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (i != j) adj[i*n+j] = rand()>>5&1;
}
}
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) scanf("%d", &adj[i*n+j]);
}
for (int i = 0; i <= 32; i++) {
nCr[i][0] = nCr[i][i] = 1;
for (int j = 1; j < i; j++) nCr[i][j] = nCr[i-1][j-1] + nCr[i-1][j];
}
hipMalloc(&gpu_part, sizeof part);
hipMalloc(&gpu_adj, sizeof adj);
hipMalloc(&gpu_ret, sizeof ret);
hipMemcpy(gpu_adj, adj, sizeof adj, hipMemcpyHostToDevice);
unsigned ans = 0;
unsigned mod = 0;
for (int k = 1; k <= n-1; k++) {
int wo = nCr[n-1][k];
int blockSize = wo;
if (blockSize > MAX_BLOCK_SIZE / k) blockSize = MAX_BLOCK_SIZE / k;
int gridSize = wo / blockSize;
if (blockSize * gridSize > MAX_ARRAY_SIZE) gridSize = MAX_ARRAY_SIZE / blockSize;
int totSize = blockSize * gridSize;
printf("block size = (%d,%d,1) grid size = (%d,1,1)\n", k, blockSize, gridSize);
//for (int j = 0; j < wo; j++) printf("%d,", getComb(j, n-1, k));
for (int j = 0; j < totSize; j++) {
int step = wo / totSize * j;
if (j < wo % totSize) step += j;
else step += wo % totSize;
//printf("step=%d\n", step);
part[j] = getComb(step, n-1, k);
}
hipMemcpy(gpu_part, part, sizeof(int) * totSize, hipMemcpyHostToDevice);
ha2<<<gridSize, dim3(k, blockSize)>>>(n, wo, gpu_part, gpu_adj, gpu_ret, mod);
hipDeviceSynchronize();
hipMemcpy(ret, gpu_ret, sizeof(int) * totSize, hipMemcpyDeviceToHost);
unsigned sum = 0;
for (int j = 0; j < totSize; j++) {
sum = mod_sum(sum, ret[j], 0);
}
printf("sum = %u\n", sum);
if ((n-k)%2 == 1) ans = mod_sum(ans, sum, mod);
else if (sum != 0) ans = mod_sum(ans, mod-sum, mod);
}
printf("ans = %u\n", ans);
hipFree(gpu_ret);
hipFree(gpu_adj);
hipFree(gpu_part);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3ha2iiPjPiS_j
.globl _Z3ha2iiPjPiS_j
.p2align 8
.type _Z3ha2iiPjPiS_j,@function
_Z3ha2iiPjPiS_j:
s_clause 0x1
s_load_b32 s10, s[0:1], 0x34
s_load_b32 s13, s[0:1], 0x28
v_bfe_u32 v3, v0, 10, 10
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s9, s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s12, s10, 16
s_and_b32 s4, s10, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s12, v[3:4]
v_mad_u32_u24 v8, v3, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v7, v[4:5], off
v_cmpx_gt_i32_e64 s9, v8
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x10
v_mul_lo_u32 v4, s9, v8
v_mov_b32_e32 v9, v8
s_cmp_gt_i32 s9, 0
s_mul_i32 s7, s12, s4
s_cselect_b32 s6, -1, 0
s_mov_b32 s8, 0
s_mul_i32 s11, s7, s9
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
v_mov_b32_e32 v10, 0
.LBB0_3:
v_lshlrev_b32_e32 v5, 2, v9
v_add_nc_u32_e32 v9, s7, v9
v_add_nc_u32_e32 v4, s11, v4
ds_store_b32 v5, v10 offset:4096
v_cmp_le_i32_e32 vcc_lo, s9, v9
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_7
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_2
v_ashrrev_i32_e32 v5, 31, v4
v_mov_b32_e32 v10, 0
s_mov_b32 s14, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
.LBB0_6:
global_load_b32 v11, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_waitcnt vmcnt(0)
v_lshl_or_b32 v10, v11, s14, v10
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s14
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_load_b32 s3, s[0:1], 0x4
v_mul_u32_u24_e32 v3, s4, v3
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_28
s_load_b32 s6, s[0:1], 0x20
s_lshl_b32 s2, -1, s4
v_lshlrev_b32_e32 v4, 2, v8
s_not_b32 s5, s2
s_cmp_gt_i32 s9, 1
v_cmp_ne_u32_e64 s2, 0, v0
s_cselect_b32 s7, -1, 0
s_add_i32 s8, s9, -1
s_cmp_gt_i32 s9, 2
v_cmp_ne_u16_e64 s10, s10, 0
s_cselect_b32 s9, -1, 0
s_lshl_b32 s11, s8, 2
v_mov_b32_e32 v8, 0
s_addk_i32 s11, 0x1000
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v6, s11 :: v_dual_lshlrev_b32 v5, 2, v3
v_mov_b32_e32 v3, 0
s_cmp_lg_u32 s4, 0
s_mul_i32 s12, s13, s12
s_cselect_b32 s11, -1, 0
s_mov_b32 s13, 0
s_branch .LBB0_10
.LBB0_9:
v_sub_nc_u32_e32 v10, 0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v9, v9, v3
v_add_nc_u32_e32 v12, s13, v1
s_add_i32 s13, s13, s12
v_and_b32_e32 v10, v7, v10
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s6, v9
s_cmp_ge_i32 s13, s3
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v7, v10, v7
v_cndmask_b32_e64 v10, 0, s6, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s3, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bcnt_u32_b32 v11, v7, 0
v_sub_nc_u32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e64 v10, v11, s5
v_cndmask_b32_e32 v3, v3, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v10, v7
s_cbranch_scc1 .LBB0_29
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v9, v7
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_14
v_dual_mov_b32 v10, v0 :: v_dual_mov_b32 v9, v7
s_mov_b32 s15, 0
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, -1, v10
v_add_nc_u32_e32 v11, -1, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 0, v10
v_and_b32_e32 v9, v11, v9
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_12
s_or_b32 exec_lo, exec_lo, s15
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s14
v_ctz_i32_b32_e32 v9, v9
s_and_not1_b32 vcc_lo, exec_lo, s7
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v10, 2, v9
ds_load_b32 v11, v10 offset:4096
v_mov_b32_e32 v10, 0
s_cbranch_vccnz .LBB0_17
v_mov_b32_e32 v10, 0
s_mov_b32 s14, s8
.LBB0_16:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s14, s14, -1
v_lshlrev_b32_e32 v12, 1, v10
s_waitcnt lgkmcnt(0)
v_lshrrev_b32_e32 v13, s14, v11
v_bfe_u32 v14, v7, s14, 1
s_cmp_lt_i32 s14, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_or_b32 v12, v13, 1, v12
v_cmp_eq_u32_e32 vcc_lo, 0, v14
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v10, v12, v10, vcc_lo
s_cbranch_scc0 .LBB0_16
.LBB0_17:
s_waitcnt lgkmcnt(0)
v_bfe_u32 v11, v11, s8, 1
s_and_not1_b32 vcc_lo, exec_lo, s9
ds_store_b32 v4, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_23
s_mov_b32 s14, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_20
.p2align 6
.LBB0_19:
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, s8
s_barrier
buffer_gl0_inv
ds_store_b32 v4, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_23
.LBB0_20:
v_mov_b32_e32 v11, 0
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_19
v_mov_b32_e32 v12, v5
s_mov_b32 s15, 0
.LBB0_22:
ds_load_b32 v13, v12
v_lshrrev_b32_e32 v14, s15, v10
v_add_nc_u32_e32 v12, 4, v12
s_add_i32 s15, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s4, s15
v_and_b32_e32 v14, 1, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 1, v14
s_waitcnt lgkmcnt(0)
v_cndmask_b32_e32 v13, 0, v13, vcc_lo
v_add_nc_u32_e32 v11, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_u32_e32 vcc_lo, s6, v11
v_cndmask_b32_e64 v13, 0, s6, vcc_lo
v_sub_nc_u32_e32 v11, v11, v13
s_cbranch_scc0 .LBB0_22
s_branch .LBB0_19
.LBB0_23:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v10, v6
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
v_bfe_u32 v9, v10, v9, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v9
s_cbranch_execz .LBB0_25
ds_store_b32 v4, v8
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v9, 0
s_and_not1_b32 vcc_lo, exec_lo, s11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_9
v_mov_b32_e32 v10, v5
s_mov_b32 s14, s4
.LBB0_27:
ds_load_b32 v11, v10
v_add_nc_u32_e32 v10, 4, v10
s_add_i32 s14, s14, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s14, 0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v9, v11, v9
v_cmp_le_u32_e32 vcc_lo, s6, v9
v_cndmask_b32_e64 v11, 0, s6, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v9, v11
s_cbranch_scc0 .LBB0_27
s_branch .LBB0_9
.LBB0_28:
v_mov_b32_e32 v3, 0
.LBB0_29:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_31
s_load_b64 s[0:1], s[0:1], 0x18
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_31:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3ha2iiPjPiS_j
.amdhsa_group_segment_fixed_size 4224
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3ha2iiPjPiS_j, .Lfunc_end0-_Z3ha2iiPjPiS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4224
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3ha2iiPjPiS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3ha2iiPjPiS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // counting Hamilton cycle, CUDA acceleration
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#define MAX_BLOCK_SIZE 1024
#define MAX_ARRAY_SIZE (1024*8)
// any 2 <= mod <= 2^31 should work
__host__ __device__ unsigned mod_sum(unsigned a, unsigned b, unsigned mod) {
unsigned c = a+b;
return c >= mod ? c-mod : c;
}
__global__ void ha2(int n, int work, unsigned *part, int *adj, unsigned *ret, unsigned int mod) {
__shared__ unsigned qc[1024];
__shared__ unsigned ai[32];
int k = blockDim.x;
int tid = threadIdx.x;
int sha = threadIdx.y * k;
int bid = threadIdx.y + blockIdx.x * blockDim.y;
int gridSize = blockDim.y * gridDim.x;
unsigned s = part[bid];
unsigned mask = (1u<<k) - 1;
unsigned total = 0;
for (int i = tid+sha; i < n; i += blockDim.y * k) {
unsigned aa = 0;
for (int j = 0; j < n; j++) {
aa = aa | adj[i * n + j] << j;
}
ai[i] = aa;
}
__syncthreads();
for (int runs = 0; runs < work; runs += gridSize) {
// first transition
unsigned row = s;
for (int i = 0; i < tid; i++) {
row = row & (row-1);
}
unsigned at = __ffs(row)-1;
row = 0;
{
unsigned me = ai[at];
for (int i = n-2; i >= 0; i--) {
if (s>>i & 1) {
row = row + row + (me>>i & 1);
}
}
qc[tid+sha] = (me >> (n-1)) & 1;
__syncthreads();
}
// calculate each transition, uses GPU SIMD feature
for (int t = 1; t < n-1; t++) {
unsigned sum = 0;
for (int i = 0; i < k; i++) {
sum = mod_sum(sum, qc[i+sha] * (row>>i & 1), mod);
}
__syncthreads();
qc[tid+sha] = sum;
__syncthreads();
}
// last transition
{
if (!(ai[n-1] >> at & 1)) qc[tid+sha] = 0;
__syncthreads();
unsigned count = 0;
for (int i = 0; i < k; i++) {
count = mod_sum(count, qc[i+sha], mod);
}
//if (tid==0) printf("[%d:%d],", s, count);
if (runs + bid < work) {
total = mod_sum(count, total, mod);
}
}
unsigned bit = s & (-s);
s += bit;
s |= mask >> __popc(s);
__syncthreads();
}
if (tid == 0) {
// output total for this block
ret[bid] = total;
}
}
int n;
int adj[1024];
unsigned part[MAX_ARRAY_SIZE];
unsigned ret[MAX_ARRAY_SIZE];
int nCr[33][33];
unsigned getComb(int idx, int n, int r) {
unsigned ans = 0;
n -= 1;
while (r > 0) {
if (idx < nCr[n][r]) n -= 1;
else {
ans |= 1u<<(n);
idx -= nCr[n][r];
n -= 1;
r -= 1;
}
}
return ans;
}
int main() {
int *gpu_adj;
unsigned *gpu_part, *gpu_ret;
scanf("%d", &n);
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
if (i != j) adj[i*n+j] = rand()>>5&1;
}
}
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) scanf("%d", &adj[i*n+j]);
}
for (int i = 0; i <= 32; i++) {
nCr[i][0] = nCr[i][i] = 1;
for (int j = 1; j < i; j++) nCr[i][j] = nCr[i-1][j-1] + nCr[i-1][j];
}
hipMalloc(&gpu_part, sizeof part);
hipMalloc(&gpu_adj, sizeof adj);
hipMalloc(&gpu_ret, sizeof ret);
hipMemcpy(gpu_adj, adj, sizeof adj, hipMemcpyHostToDevice);
unsigned ans = 0;
unsigned mod = 0;
for (int k = 1; k <= n-1; k++) {
int wo = nCr[n-1][k];
int blockSize = wo;
if (blockSize > MAX_BLOCK_SIZE / k) blockSize = MAX_BLOCK_SIZE / k;
int gridSize = wo / blockSize;
if (blockSize * gridSize > MAX_ARRAY_SIZE) gridSize = MAX_ARRAY_SIZE / blockSize;
int totSize = blockSize * gridSize;
printf("block size = (%d,%d,1) grid size = (%d,1,1)\n", k, blockSize, gridSize);
//for (int j = 0; j < wo; j++) printf("%d,", getComb(j, n-1, k));
for (int j = 0; j < totSize; j++) {
int step = wo / totSize * j;
if (j < wo % totSize) step += j;
else step += wo % totSize;
//printf("step=%d\n", step);
part[j] = getComb(step, n-1, k);
}
hipMemcpy(gpu_part, part, sizeof(int) * totSize, hipMemcpyHostToDevice);
ha2<<<gridSize, dim3(k, blockSize)>>>(n, wo, gpu_part, gpu_adj, gpu_ret, mod);
hipDeviceSynchronize();
hipMemcpy(ret, gpu_ret, sizeof(int) * totSize, hipMemcpyDeviceToHost);
unsigned sum = 0;
for (int j = 0; j < totSize; j++) {
sum = mod_sum(sum, ret[j], 0);
}
printf("sum = %u\n", sum);
if ((n-k)%2 == 1) ans = mod_sum(ans, sum, mod);
else if (sum != 0) ans = mod_sum(ans, mod-sum, mod);
}
printf("ans = %u\n", ans);
hipFree(gpu_ret);
hipFree(gpu_adj);
hipFree(gpu_part);
} | .text
.file "ha2.hip"
.globl _Z7mod_sumjjj # -- Begin function _Z7mod_sumjjj
.p2align 4, 0x90
.type _Z7mod_sumjjj,@function
_Z7mod_sumjjj: # @_Z7mod_sumjjj
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
leal (%rdi,%rsi), %eax
xorl %ecx, %ecx
cmpl %edx, %eax
cmovael %edx, %ecx
subl %ecx, %eax
retq
.Lfunc_end0:
.size _Z7mod_sumjjj, .Lfunc_end0-_Z7mod_sumjjj
.cfi_endproc
# -- End function
.globl _Z18__device_stub__ha2iiPjPiS_j # -- Begin function _Z18__device_stub__ha2iiPjPiS_j
.p2align 4, 0x90
.type _Z18__device_stub__ha2iiPjPiS_j,@function
_Z18__device_stub__ha2iiPjPiS_j: # @_Z18__device_stub__ha2iiPjPiS_j
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3ha2iiPjPiS_j, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z18__device_stub__ha2iiPjPiS_j, .Lfunc_end1-_Z18__device_stub__ha2iiPjPiS_j
.cfi_endproc
# -- End function
.globl _Z7getCombiii # -- Begin function _Z7getCombiii
.p2align 4, 0x90
.type _Z7getCombiii,@function
_Z7getCombiii: # @_Z7getCombiii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_1
# %bb.3: # %.lr.ph.preheader
movslq %esi, %rcx
movq %rcx, %rax
shlq $7, %rax
leaq (%rax,%rcx,4), %rsi
addq $nCr-132, %rsi
decl %ecx
xorl %r8d, %r8d
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %edx, %r9d
movl (%rsi,%r9,4), %r9d
movl $1, %r10d
shll %cl, %r10d
xorl %r11d, %r11d
cmpl %r9d, %edi
setge %r11b
cmovll %r8d, %r9d
cmovll %r8d, %r10d
subl %r9d, %edi
subl %r11d, %edx
orl %r10d, %eax
addq $-132, %rsi
decl %ecx
testl %edx, %edx
jg .LBB2_4
# %bb.2: # %._crit_edge
retq
.LBB2_1:
xorl %eax, %eax
retq
.Lfunc_end2:
.size _Z7getCombiii, .Lfunc_end2-_Z7getCombiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $n, %esi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, n(%rip)
jle .LBB3_8
# %bb.1: # %.preheader116.preheader
xorl %ebx, %ebx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rbx
cmpl n(%rip), %ebx
jge .LBB3_8
.LBB3_2: # %.preheader116
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, n(%rip)
jle .LBB3_7
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB3_2 Depth=1
movslq %ebx, %r14
xorl %r15d, %r15d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
incq %r15
cmpl n(%rip), %r15d
jge .LBB3_7
.LBB3_4: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpl %r15d, %ebx
je .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
callq rand
shrl $5, %eax
andl $1, %eax
movslq n(%rip), %rcx
imulq %r14, %rcx
addq %r15, %rcx
movl %eax, adj(,%rcx,4)
jmp .LBB3_6
.LBB3_8: # %.preheader115
cmpl $0, n(%rip)
jle .LBB3_14
# %bb.9: # %.preheader114.preheader
xorl %ebx, %ebx
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_13: # %._crit_edge121
# in Loop: Header=BB3_10 Depth=1
incl %ebx
cmpl n(%rip), %ebx
jge .LBB3_14
.LBB3_10: # %.preheader114
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
movl n(%rip), %eax
testl %eax, %eax
jle .LBB3_13
# %bb.11: # %.lr.ph120.preheader
# in Loop: Header=BB3_10 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_12: # %.lr.ph120
# Parent Loop BB3_10 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebx, %eax
cltq
addq %r14, %rax
leaq adj(,%rax,4), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl n(%rip), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB3_12
jmp .LBB3_13
.LBB3_14: # %.preheader.preheader
leaq nCr-132(%rip), %rax
xorl %ecx, %ecx
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_18: # %._crit_edge126
# in Loop: Header=BB3_15 Depth=1
incq %rcx
addq $132, %rax
cmpq $33, %rcx
je .LBB3_19
.LBB3_15: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_17 Depth 2
movq %rcx, %rdx
shlq $7, %rdx
leaq (%rdx,%rcx,4), %rsi
movl $1, nCr(%rsi,%rcx,4)
movl $1, nCr(%rdx,%rcx,4)
cmpq $2, %rcx
jb .LBB3_18
# %bb.16: # %.lr.ph125
# in Loop: Header=BB3_15 Depth=1
movl $1, %edx
.p2align 4, 0x90
.LBB3_17: # Parent Loop BB3_15 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rax,%rdx,4), %esi
addl -4(%rax,%rdx,4), %esi
movl %esi, 132(%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_17
jmp .LBB3_18
.LBB3_19:
leaq 24(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
movq 32(%rsp), %rdi
movl $adj, %esi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movl n(%rip), %eax
xorl %esi, %esi
cmpl $2, %eax
jl .LBB3_33
# %bb.20: # %.lr.ph141
xorl %ebp, %ebp
movl $1, %ebx
xorl %esi, %esi
jmp .LBB3_21
.p2align 4, 0x90
.LBB3_31: # in Loop: Header=BB3_21 Depth=1
xorl %r14d, %r14d
.LBB3_32: # %._crit_edge136
# in Loop: Header=BB3_21 Depth=1
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movslq n(%rip), %rax
movl %eax, %ecx
subl %ebx, %ecx
andl $-2147483647, %ecx # imm = 0x80000001
movl %r14d, %edx
negl %edx
cmpl $1, %ecx
cmovel %r14d, %edx
movl 44(%rsp), %esi # 4-byte Reload
addl %edx, %esi
incq %rbx
cmpq %rax, %rbx
jge .LBB3_33
.LBB3_21: # =>This Loop Header: Depth=1
# Child Loop BB3_25 Depth 2
# Child Loop BB3_26 Depth 3
# Child Loop BB3_35 Depth 2
movl %esi, 44(%rsp) # 4-byte Spill
cltq
leaq -1(%rax), %rcx
shlq $7, %rcx
leaq (%rcx,%rax,4), %rax
addq $-4, %rax
movl nCr(%rax,%rbx,4), %ecx
movl $1024, %eax # imm = 0x400
xorl %edx, %edx
divl %ebx
movl %eax, %r8d
cmpl %eax, %ecx
cmovll %ecx, %r8d
movl %ecx, 8(%rsp) # 4-byte Spill
movl %ecx, %eax
cltd
idivl %r8d
movl %eax, %ecx
imull %r8d, %ecx
cmpl $8193, %ecx # imm = 0x2001
jl .LBB3_23
# %bb.22: # in Loop: Header=BB3_21 Depth=1
movl $8192, %eax # imm = 0x2000
xorl %edx, %edx
idivl %r8d
.LBB3_23: # in Loop: Header=BB3_21 Depth=1
movl %eax, %r14d
imull %r8d, %r14d
movl $.L.str.1, %edi
movl %ebx, %esi
movq %r8, 64(%rsp) # 8-byte Spill
movl %r8d, %edx
movl %eax, 40(%rsp) # 4-byte Spill
movl %eax, %ecx
xorl %eax, %eax
callq printf
movl %r14d, %r12d
movl %r14d, 12(%rsp) # 4-byte Spill
testl %r14d, %r14d
jle .LBB3_28
# %bb.24: # %.lr.ph130
# in Loop: Header=BB3_21 Depth=1
movl 8(%rsp), %eax # 4-byte Reload
cltd
idivl 12(%rsp) # 4-byte Folded Reload
movl %eax, 48(%rsp) # 4-byte Spill
movl n(%rip), %eax
leal -1(%rax), %ecx
movslq %ecx, %rcx
addl $-2, %eax
movq %rcx, %rdi
shlq $7, %rdi
leaq (%rdi,%rcx,4), %rdi
addq $nCr-132, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_25: # Parent Loop BB3_21 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_26 Depth 3
movq %r12, %rsi
cmpl %edx, %r8d
movl %edx, %ecx
cmovll %r8d, %ecx
movl 48(%rsp), %r9d # 4-byte Reload
imull %r8d, %r9d
addl %ecx, %r9d
xorl %r10d, %r10d
movq %rdi, %r11
movl %eax, %ecx
movq %rbx, %r15
movl %ebx, %r14d
.p2align 4, 0x90
.LBB3_26: # %.lr.ph.i
# Parent Loop BB3_21 Depth=1
# Parent Loop BB3_25 Depth=2
# => This Inner Loop Header: Depth=3
movl %r14d, %r13d
movl (%r11,%r13,4), %r13d
movl $1, %r12d
shll %cl, %r12d
xorl %ebx, %ebx
cmpl %r13d, %r9d
setge %bl
cmovll %ebp, %r13d
cmovll %ebp, %r12d
subl %r13d, %r9d
subl %ebx, %r14d
orl %r12d, %r10d
decl %ecx
addq $-132, %r11
testl %r14d, %r14d
jg .LBB3_26
# %bb.27: # %_Z7getCombiii.exit
# in Loop: Header=BB3_25 Depth=2
movl %r10d, part(,%r8,4)
incq %r8
movq %rsi, %r12
cmpq %rsi, %r8
movq %r15, %rbx
jb .LBB3_25
.LBB3_28: # %._crit_edge131
# in Loop: Header=BB3_21 Depth=1
movq 24(%rsp), %rdi
movl 12(%rsp), %r15d # 4-byte Reload
movslq %r15d, %r14
shlq $2, %r14
movl $part, %esi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl 40(%rsp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movq 64(%rsp), %rdx # 8-byte Reload
shlq $32, %rdx
orq %rbx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_30
# %bb.29: # in Loop: Header=BB3_21 Depth=1
movl n(%rip), %eax
movq 24(%rsp), %rcx
movq 32(%rsp), %rdx
movq 16(%rsp), %rsi
movl %eax, 60(%rsp)
movl 8(%rsp), %eax # 4-byte Reload
movl %eax, 56(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movq %rsi, 120(%rsp)
movl $0, 52(%rsp)
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 136(%rsp), %rax
movq %rax, 160(%rsp)
leaq 128(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z3ha2iiPjPiS_j, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_30: # in Loop: Header=BB3_21 Depth=1
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $ret, %edi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r15d, %r15d
jle .LBB3_31
# %bb.34: # %.lr.ph135.preheader
# in Loop: Header=BB3_21 Depth=1
xorl %eax, %eax
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_35: # %.lr.ph135
# Parent Loop BB3_21 Depth=1
# => This Inner Loop Header: Depth=2
addl ret(,%rax,4), %r14d
incq %rax
cmpq %r12, %rax
jb .LBB3_35
jmp .LBB3_32
.LBB3_33: # %._crit_edge142
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3ha2iiPjPiS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3ha2iiPjPiS_j,@object # @_Z3ha2iiPjPiS_j
.section .rodata,"a",@progbits
.globl _Z3ha2iiPjPiS_j
.p2align 3, 0x0
_Z3ha2iiPjPiS_j:
.quad _Z18__device_stub__ha2iiPjPiS_j
.size _Z3ha2iiPjPiS_j, 8
.type n,@object # @n
.bss
.globl n
.p2align 2, 0x0
n:
.long 0 # 0x0
.size n, 4
.type adj,@object # @adj
.globl adj
.p2align 4, 0x0
adj:
.zero 4096
.size adj, 4096
.type part,@object # @part
.globl part
.p2align 4, 0x0
part:
.zero 32768
.size part, 32768
.type ret,@object # @ret
.globl ret
.p2align 4, 0x0
ret:
.zero 32768
.size ret, 32768
.type nCr,@object # @nCr
.globl nCr
.p2align 4, 0x0
nCr:
.zero 4356
.size nCr, 4356
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "block size = (%d,%d,1) grid size = (%d,1,1)\n"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "sum = %u\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ans = %u\n"
.size .L.str.3, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3ha2iiPjPiS_j"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__ha2iiPjPiS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3ha2iiPjPiS_j
.addrsig_sym n
.addrsig_sym adj
.addrsig_sym part
.addrsig_sym ret
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012cad9_00000000-6_ha2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7mod_sumjjj
.type _Z7mod_sumjjj, @function
_Z7mod_sumjjj:
.LFB2057:
.cfi_startproc
endbr64
leal (%rdi,%rsi), %eax
movl %eax, %ecx
subl %edx, %ecx
cmpl %edx, %eax
cmovnb %ecx, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z7mod_sumjjj, .-_Z7mod_sumjjj
.globl _Z7getCombiii
.type _Z7getCombiii, @function
_Z7getCombiii:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L10
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %r9d
movl %edx, %r8d
subl $2, %esi
movl $0, %r10d
leaq nCr(%rip), %r11
movl $1, %ebx
jmp .L9
.L7:
movl %ebx, %edx
sall %cl, %edx
orl %edx, %r10d
subl %eax, %r9d
subl $1, %r8d
subl $1, %esi
testl %r8d, %r8d
jle .L15
.L9:
leal 1(%rsi), %ecx
movslq %r8d, %rdx
movslq %ecx, %rdi
movq %rdi, %rax
salq $5, %rax
addq %rdi, %rax
addq %rdx, %rax
movl (%r11,%rax,4), %eax
cmpl %r9d, %eax
jle .L7
subl $1, %esi
jmp .L9
.L10:
.cfi_def_cfa_offset 8
.cfi_restore 3
movl $0, %r10d
movl %r10d, %eax
ret
.L15:
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %r10d, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7getCombiii, .-_Z7getCombiii
.globl _Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
.type _Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j, @function
_Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3ha2iiPjPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j, .-_Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
.globl _Z3ha2iiPjPiS_j
.type _Z3ha2iiPjPiS_j, @function
_Z3ha2iiPjPiS_j:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3ha2iiPjPiS_j, .-_Z3ha2iiPjPiS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "block size = (%d,%d,1) grid size = (%d,1,1)\n"
.section .rodata.str1.1
.LC2:
.string "sum = %u\n"
.LC3:
.string "ans = %u\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq n(%rip), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl $0, %ebp
leaq adj(%rip), %r12
cmpl $0, n(%rip)
jg .L25
.L26:
leaq nCr(%rip), %r10
movq %r10, %rdi
movq %r10, %r8
movl $0, %r9d
movl $0, %esi
addq $4, %r10
jmp .L37
.L70:
call rand@PLT
movl %ebp, %edx
imull n(%rip), %edx
addl %ebx, %edx
movslq %edx, %rdx
sarl $5, %eax
andl $1, %eax
movl %eax, (%r12,%rdx,4)
.L27:
addl $1, %ebx
cmpl %ebx, n(%rip)
jle .L30
.L28:
cmpl %ebx, %ebp
je .L27
jmp .L70
.L30:
addl $1, %ebp
movl n(%rip), %eax
cmpl %ebp, %eax
jle .L29
.L25:
movl $0, %ebx
cmpl $0, n(%rip)
jg .L28
jmp .L30
.L29:
testl %eax, %eax
jle .L26
movl $0, %ebp
leaq adj(%rip), %r13
leaq .LC0(%rip), %r12
jmp .L31
.L32:
imull %ebp, %eax
addl %ebx, %eax
cltq
leaq 0(%r13,%rax,4), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl n(%rip), %eax
cmpl %ebx, %eax
jg .L32
.L33:
addl $1, %ebp
cmpl %ebp, n(%rip)
jle .L26
.L31:
movl n(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L32
jmp .L33
.L39:
movl 28(%rsp), %r8d
movl %r8d, %esi
movl 36(%rsp), %ecx
imull %ecx, %esi
movl %esi, %ebx
movl %esi, 32(%rsp)
movl %r13d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L40
movl 44(%rsp), %eax
cltd
idivl %ebx
movl %eax, %r14d
movl n(%rip), %eax
subl $1, %eax
movl %eax, 24(%rsp)
leal 1(%r14), %r15d
movl %edx, %r12d
movslq %ebx, %rax
movq %rax, 16(%rsp)
movl $0, %ebp
movl $0, %ebx
movl %r13d, 12(%rsp)
movl %edx, %r13d
.L43:
cmpl %ebx, %r13d
movl %ebp, %edi
cmovle %r12d, %edi
movl 12(%rsp), %edx
movl 24(%rsp), %esi
call _Z7getCombiii
leaq part(%rip), %rcx
movl %eax, (%rcx,%rbx,4)
addq $1, %rbx
addl %r15d, %ebp
addl %r14d, %r12d
movq 16(%rsp), %rax
cmpq %rax, %rbx
jne .L43
movl 12(%rsp), %r13d
.L40:
movslq 32(%rsp), %rbx
salq $2, %rbx
movl $1, %ecx
movq %rbx, %rdx
leaq part(%rip), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %r13d, 80(%rsp)
movl 36(%rsp), %eax
movl %eax, 84(%rsp)
movl 28(%rsp), %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L71
.L44:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
leaq ret(%rip), %rdi
call cudaMemcpy@PLT
cmpl $0, 32(%rsp)
jle .L57
leaq ret(%rip), %rax
addq %rax, %rbx
movl $0, %ebp
.L46:
addl (%rax), %ebp
addq $4, %rax
cmpq %rax, %rbx
jne .L46
.L45:
movl %ebp, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl n(%rip), %eax
movl %eax, %edx
subl %r13d, %edx
movl %edx, %ecx
shrl $31, %ecx
addl %ecx, %edx
andl $1, %edx
subl %ecx, %edx
movl 40(%rsp), %edi
leal (%rdi,%rbp), %ecx
subl %ebp, %edi
cmpl $1, %edx
cmovne %edi, %ecx
movl %ecx, 40(%rsp)
addl $1, %r13d
cmpl %r13d, %eax
jle .L38
.L49:
movslq %r13d, %rcx
subl $1, %eax
cltq
movq %rax, %rdx
salq $5, %rdx
addq %rdx, %rax
addq %rcx, %rax
leaq nCr(%rip), %rsi
movl (%rsi,%rax,4), %esi
movl %esi, 44(%rsp)
movl $1024, %eax
movl $0, %edx
idivl %r13d
cmpl %esi, %eax
movl %eax, %ecx
movl %esi, %eax
cmovg %esi, %ecx
movl %ecx, 36(%rsp)
cltd
idivl %ecx
movl %eax, 28(%rsp)
imull %ecx, %eax
cmpl $8192, %eax
jle .L39
movl $8192, %eax
movl $0, %edx
idivl %ecx
movl %eax, 28(%rsp)
jmp .L39
.L71:
movl $0, %r9d
movq 72(%rsp), %r8
movq 56(%rsp), %rcx
movq 64(%rsp), %rdx
movl 44(%rsp), %esi
movl n(%rip), %edi
call _Z29__device_stub__Z3ha2iiPjPiS_jiiPjPiS_j
jmp .L44
.L57:
movl $0, %ebp
jmp .L45
.L56:
movl $0, 40(%rsp)
.L38:
movl 40(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L72
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
addl $1, %esi
addq $136, %r8
addq $132, %rdi
addq $33, %r9
.L37:
movl $1, (%r8)
movl $1, (%rdi)
cmpl $1, %esi
jle .L34
leal -2(%rsi), %eax
addq %r9, %rax
leaq (%r10,%rax,4), %rcx
movq %rdi, %rax
.L35:
movl -128(%rax), %edx
addl -132(%rax), %edx
movl %edx, 4(%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L35
addl $1, %esi
addq $136, %r8
addq $132, %rdi
addq $33, %r9
cmpl $33, %esi
jne .L37
leaq 64(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
leaq adj(%rip), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl n(%rip), %eax
cmpl $1, %eax
jle .L56
movl $1, %r13d
movl $0, 40(%rsp)
jmp .L49
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z3ha2iiPjPiS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3ha2iiPjPiS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl nCr
.bss
.align 32
.type nCr, @object
.size nCr, 4356
nCr:
.zero 4356
.globl ret
.align 32
.type ret, @object
.size ret, 32768
ret:
.zero 32768
.globl part
.align 32
.type part, @object
.size part, 32768
part:
.zero 32768
.globl adj
.align 32
.type adj, @object
.size adj, 4096
adj:
.zero 4096
.globl n
.align 4
.type n, @object
.size n, 4
n:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ha2.hip"
.globl _Z7mod_sumjjj # -- Begin function _Z7mod_sumjjj
.p2align 4, 0x90
.type _Z7mod_sumjjj,@function
_Z7mod_sumjjj: # @_Z7mod_sumjjj
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
leal (%rdi,%rsi), %eax
xorl %ecx, %ecx
cmpl %edx, %eax
cmovael %edx, %ecx
subl %ecx, %eax
retq
.Lfunc_end0:
.size _Z7mod_sumjjj, .Lfunc_end0-_Z7mod_sumjjj
.cfi_endproc
# -- End function
.globl _Z18__device_stub__ha2iiPjPiS_j # -- Begin function _Z18__device_stub__ha2iiPjPiS_j
.p2align 4, 0x90
.type _Z18__device_stub__ha2iiPjPiS_j,@function
_Z18__device_stub__ha2iiPjPiS_j: # @_Z18__device_stub__ha2iiPjPiS_j
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3ha2iiPjPiS_j, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z18__device_stub__ha2iiPjPiS_j, .Lfunc_end1-_Z18__device_stub__ha2iiPjPiS_j
.cfi_endproc
# -- End function
.globl _Z7getCombiii # -- Begin function _Z7getCombiii
.p2align 4, 0x90
.type _Z7getCombiii,@function
_Z7getCombiii: # @_Z7getCombiii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_1
# %bb.3: # %.lr.ph.preheader
movslq %esi, %rcx
movq %rcx, %rax
shlq $7, %rax
leaq (%rax,%rcx,4), %rsi
addq $nCr-132, %rsi
decl %ecx
xorl %r8d, %r8d
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %edx, %r9d
movl (%rsi,%r9,4), %r9d
movl $1, %r10d
shll %cl, %r10d
xorl %r11d, %r11d
cmpl %r9d, %edi
setge %r11b
cmovll %r8d, %r9d
cmovll %r8d, %r10d
subl %r9d, %edi
subl %r11d, %edx
orl %r10d, %eax
addq $-132, %rsi
decl %ecx
testl %edx, %edx
jg .LBB2_4
# %bb.2: # %._crit_edge
retq
.LBB2_1:
xorl %eax, %eax
retq
.Lfunc_end2:
.size _Z7getCombiii, .Lfunc_end2-_Z7getCombiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $n, %esi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, n(%rip)
jle .LBB3_8
# %bb.1: # %.preheader116.preheader
xorl %ebx, %ebx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rbx
cmpl n(%rip), %ebx
jge .LBB3_8
.LBB3_2: # %.preheader116
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, n(%rip)
jle .LBB3_7
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB3_2 Depth=1
movslq %ebx, %r14
xorl %r15d, %r15d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
incq %r15
cmpl n(%rip), %r15d
jge .LBB3_7
.LBB3_4: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpl %r15d, %ebx
je .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
callq rand
shrl $5, %eax
andl $1, %eax
movslq n(%rip), %rcx
imulq %r14, %rcx
addq %r15, %rcx
movl %eax, adj(,%rcx,4)
jmp .LBB3_6
.LBB3_8: # %.preheader115
cmpl $0, n(%rip)
jle .LBB3_14
# %bb.9: # %.preheader114.preheader
xorl %ebx, %ebx
jmp .LBB3_10
.p2align 4, 0x90
.LBB3_13: # %._crit_edge121
# in Loop: Header=BB3_10 Depth=1
incl %ebx
cmpl n(%rip), %ebx
jge .LBB3_14
.LBB3_10: # %.preheader114
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
movl n(%rip), %eax
testl %eax, %eax
jle .LBB3_13
# %bb.11: # %.lr.ph120.preheader
# in Loop: Header=BB3_10 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_12: # %.lr.ph120
# Parent Loop BB3_10 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebx, %eax
cltq
addq %r14, %rax
leaq adj(,%rax,4), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl n(%rip), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB3_12
jmp .LBB3_13
.LBB3_14: # %.preheader.preheader
leaq nCr-132(%rip), %rax
xorl %ecx, %ecx
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_18: # %._crit_edge126
# in Loop: Header=BB3_15 Depth=1
incq %rcx
addq $132, %rax
cmpq $33, %rcx
je .LBB3_19
.LBB3_15: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_17 Depth 2
movq %rcx, %rdx
shlq $7, %rdx
leaq (%rdx,%rcx,4), %rsi
movl $1, nCr(%rsi,%rcx,4)
movl $1, nCr(%rdx,%rcx,4)
cmpq $2, %rcx
jb .LBB3_18
# %bb.16: # %.lr.ph125
# in Loop: Header=BB3_15 Depth=1
movl $1, %edx
.p2align 4, 0x90
.LBB3_17: # Parent Loop BB3_15 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rax,%rdx,4), %esi
addl -4(%rax,%rdx,4), %esi
movl %esi, 132(%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_17
jmp .LBB3_18
.LBB3_19:
leaq 24(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
movq 32(%rsp), %rdi
movl $adj, %esi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movl n(%rip), %eax
xorl %esi, %esi
cmpl $2, %eax
jl .LBB3_33
# %bb.20: # %.lr.ph141
xorl %ebp, %ebp
movl $1, %ebx
xorl %esi, %esi
jmp .LBB3_21
.p2align 4, 0x90
.LBB3_31: # in Loop: Header=BB3_21 Depth=1
xorl %r14d, %r14d
.LBB3_32: # %._crit_edge136
# in Loop: Header=BB3_21 Depth=1
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movslq n(%rip), %rax
movl %eax, %ecx
subl %ebx, %ecx
andl $-2147483647, %ecx # imm = 0x80000001
movl %r14d, %edx
negl %edx
cmpl $1, %ecx
cmovel %r14d, %edx
movl 44(%rsp), %esi # 4-byte Reload
addl %edx, %esi
incq %rbx
cmpq %rax, %rbx
jge .LBB3_33
.LBB3_21: # =>This Loop Header: Depth=1
# Child Loop BB3_25 Depth 2
# Child Loop BB3_26 Depth 3
# Child Loop BB3_35 Depth 2
movl %esi, 44(%rsp) # 4-byte Spill
cltq
leaq -1(%rax), %rcx
shlq $7, %rcx
leaq (%rcx,%rax,4), %rax
addq $-4, %rax
movl nCr(%rax,%rbx,4), %ecx
movl $1024, %eax # imm = 0x400
xorl %edx, %edx
divl %ebx
movl %eax, %r8d
cmpl %eax, %ecx
cmovll %ecx, %r8d
movl %ecx, 8(%rsp) # 4-byte Spill
movl %ecx, %eax
cltd
idivl %r8d
movl %eax, %ecx
imull %r8d, %ecx
cmpl $8193, %ecx # imm = 0x2001
jl .LBB3_23
# %bb.22: # in Loop: Header=BB3_21 Depth=1
movl $8192, %eax # imm = 0x2000
xorl %edx, %edx
idivl %r8d
.LBB3_23: # in Loop: Header=BB3_21 Depth=1
movl %eax, %r14d
imull %r8d, %r14d
movl $.L.str.1, %edi
movl %ebx, %esi
movq %r8, 64(%rsp) # 8-byte Spill
movl %r8d, %edx
movl %eax, 40(%rsp) # 4-byte Spill
movl %eax, %ecx
xorl %eax, %eax
callq printf
movl %r14d, %r12d
movl %r14d, 12(%rsp) # 4-byte Spill
testl %r14d, %r14d
jle .LBB3_28
# %bb.24: # %.lr.ph130
# in Loop: Header=BB3_21 Depth=1
movl 8(%rsp), %eax # 4-byte Reload
cltd
idivl 12(%rsp) # 4-byte Folded Reload
movl %eax, 48(%rsp) # 4-byte Spill
movl n(%rip), %eax
leal -1(%rax), %ecx
movslq %ecx, %rcx
addl $-2, %eax
movq %rcx, %rdi
shlq $7, %rdi
leaq (%rdi,%rcx,4), %rdi
addq $nCr-132, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_25: # Parent Loop BB3_21 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_26 Depth 3
movq %r12, %rsi
cmpl %edx, %r8d
movl %edx, %ecx
cmovll %r8d, %ecx
movl 48(%rsp), %r9d # 4-byte Reload
imull %r8d, %r9d
addl %ecx, %r9d
xorl %r10d, %r10d
movq %rdi, %r11
movl %eax, %ecx
movq %rbx, %r15
movl %ebx, %r14d
.p2align 4, 0x90
.LBB3_26: # %.lr.ph.i
# Parent Loop BB3_21 Depth=1
# Parent Loop BB3_25 Depth=2
# => This Inner Loop Header: Depth=3
movl %r14d, %r13d
movl (%r11,%r13,4), %r13d
movl $1, %r12d
shll %cl, %r12d
xorl %ebx, %ebx
cmpl %r13d, %r9d
setge %bl
cmovll %ebp, %r13d
cmovll %ebp, %r12d
subl %r13d, %r9d
subl %ebx, %r14d
orl %r12d, %r10d
decl %ecx
addq $-132, %r11
testl %r14d, %r14d
jg .LBB3_26
# %bb.27: # %_Z7getCombiii.exit
# in Loop: Header=BB3_25 Depth=2
movl %r10d, part(,%r8,4)
incq %r8
movq %rsi, %r12
cmpq %rsi, %r8
movq %r15, %rbx
jb .LBB3_25
.LBB3_28: # %._crit_edge131
# in Loop: Header=BB3_21 Depth=1
movq 24(%rsp), %rdi
movl 12(%rsp), %r15d # 4-byte Reload
movslq %r15d, %r14
shlq $2, %r14
movl $part, %esi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl 40(%rsp), %edi # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movq 64(%rsp), %rdx # 8-byte Reload
shlq $32, %rdx
orq %rbx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_30
# %bb.29: # in Loop: Header=BB3_21 Depth=1
movl n(%rip), %eax
movq 24(%rsp), %rcx
movq 32(%rsp), %rdx
movq 16(%rsp), %rsi
movl %eax, 60(%rsp)
movl 8(%rsp), %eax # 4-byte Reload
movl %eax, 56(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movq %rsi, 120(%rsp)
movl $0, 52(%rsp)
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 136(%rsp), %rax
movq %rax, 160(%rsp)
leaq 128(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z3ha2iiPjPiS_j, %edi
leaq 144(%rsp), %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_30: # in Loop: Header=BB3_21 Depth=1
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $ret, %edi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r15d, %r15d
jle .LBB3_31
# %bb.34: # %.lr.ph135.preheader
# in Loop: Header=BB3_21 Depth=1
xorl %eax, %eax
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_35: # %.lr.ph135
# Parent Loop BB3_21 Depth=1
# => This Inner Loop Header: Depth=2
addl ret(,%rax,4), %r14d
incq %rax
cmpq %r12, %rax
jb .LBB3_35
jmp .LBB3_32
.LBB3_33: # %._crit_edge142
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3ha2iiPjPiS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3ha2iiPjPiS_j,@object # @_Z3ha2iiPjPiS_j
.section .rodata,"a",@progbits
.globl _Z3ha2iiPjPiS_j
.p2align 3, 0x0
_Z3ha2iiPjPiS_j:
.quad _Z18__device_stub__ha2iiPjPiS_j
.size _Z3ha2iiPjPiS_j, 8
.type n,@object # @n
.bss
.globl n
.p2align 2, 0x0
n:
.long 0 # 0x0
.size n, 4
.type adj,@object # @adj
.globl adj
.p2align 4, 0x0
adj:
.zero 4096
.size adj, 4096
.type part,@object # @part
.globl part
.p2align 4, 0x0
part:
.zero 32768
.size part, 32768
.type ret,@object # @ret
.globl ret
.p2align 4, 0x0
ret:
.zero 32768
.size ret, 32768
.type nCr,@object # @nCr
.globl nCr
.p2align 4, 0x0
nCr:
.zero 4356
.size nCr, 4356
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "block size = (%d,%d,1) grid size = (%d,1,1)\n"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "sum = %u\n"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ans = %u\n"
.size .L.str.3, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3ha2iiPjPiS_j"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__ha2iiPjPiS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3ha2iiPjPiS_j
.addrsig_sym n
.addrsig_sym adj
.addrsig_sym part
.addrsig_sym ret
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void prepare(float *positions, int *usageIndexes, int count, int iterations,
float *random, float minScale, float maxScale,
float minX, float maxX, float minY)
{
int id = blockIdx.x * blockDim.x + threadIdx.x, jump = gridDim.x * blockDim.x, i,
row = iterations * 2 + 1;
float x, y, scale;
// for each snowflake
for (i = id; i < count; i += jump)
{
// reset usageIndex
usageIndexes[i] = 0;
scale = random[i] * (maxScale - minScale) + minScale;
// starting positions
x = random[i + 1] * (maxX - minX) + minX;
y = minY;
// store in positions
positions[i * row + 0] = scale;
positions[i * row + 1] = x;
positions[i * row + 2] = y;
}
}
extern "C"
__global__ void calculate(float *positions, int *usageIndexes, int count, int iterations,
float wind, float angle, float gravity, float maxX, float minX, float maxY)
{
int id = blockIdx.x * blockDim.x + threadIdx.x, jump = gridDim.x * blockDim.x, i, j, usageIndex,
row = iterations * 2 + 1;
float x, y, windX, windY, scale, sin, cos, prevX, prevY;
// trigonometrics used for wind force
sincosf(angle, &sin, &cos);
windX = wind * sin;
windY = wind * cos;
// for each snowflake
for (i = id; i < count; i += jump)
{
scale = positions[i * row + 0];
usageIndex = usageIndexes[i];
prevX = positions[i * row + 1];
prevY = positions[i * row + 2];
// starting from index 2, as <0, 2> is to be prepared earlier
for (j = 3; j < iterations * 2 + 1; j += 2)
{
x = prevX + windX;
if (x < minX)
{
x = maxX + x - minX;
}
else if (x > maxX)
{
x = minX + x - maxX;
}
y = prevY + gravity * scale + windY;
if (y > maxY && usageIndex == 0)
{
usageIndex = j;
usageIndexes[i] = usageIndex;
}
positions[i * row + j] = x;
positions[i * row + j + 1] = y;
prevX = x;
prevY = y;
}
}
} | .file "tmpxft_00015690_00000000-6_SnowflakeSimulation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff
.type _Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff, @function
_Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movq %r8, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq prepare(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff, .-_Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff
.globl prepare
.type prepare, @function
prepare:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size prepare, .-prepare
.globl _Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff
.type _Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff, @function
_Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff:
.LFB2053:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movss %xmm5, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq calculate(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff, .-_Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff
.globl calculate
.type calculate, @function
calculate:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size calculate, .-calculate
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "calculate"
.LC1:
.string "prepare"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq calculate(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq prepare(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void prepare(float *positions, int *usageIndexes, int count, int iterations,
float *random, float minScale, float maxScale,
float minX, float maxX, float minY)
{
int id = blockIdx.x * blockDim.x + threadIdx.x, jump = gridDim.x * blockDim.x, i,
row = iterations * 2 + 1;
float x, y, scale;
// for each snowflake
for (i = id; i < count; i += jump)
{
// reset usageIndex
usageIndexes[i] = 0;
scale = random[i] * (maxScale - minScale) + minScale;
// starting positions
x = random[i + 1] * (maxX - minX) + minX;
y = minY;
// store in positions
positions[i * row + 0] = scale;
positions[i * row + 1] = x;
positions[i * row + 2] = y;
}
}
extern "C"
__global__ void calculate(float *positions, int *usageIndexes, int count, int iterations,
float wind, float angle, float gravity, float maxX, float minX, float maxY)
{
int id = blockIdx.x * blockDim.x + threadIdx.x, jump = gridDim.x * blockDim.x, i, j, usageIndex,
row = iterations * 2 + 1;
float x, y, windX, windY, scale, sin, cos, prevX, prevY;
// trigonometrics used for wind force
sincosf(angle, &sin, &cos);
windX = wind * sin;
windY = wind * cos;
// for each snowflake
for (i = id; i < count; i += jump)
{
scale = positions[i * row + 0];
usageIndex = usageIndexes[i];
prevX = positions[i * row + 1];
prevY = positions[i * row + 2];
// starting from index 2, as <0, 2> is to be prepared earlier
for (j = 3; j < iterations * 2 + 1; j += 2)
{
x = prevX + windX;
if (x < minX)
{
x = maxX + x - minX;
}
else if (x > maxX)
{
x = minX + x - maxX;
}
y = prevY + gravity * scale + windY;
if (y > maxY && usageIndex == 0)
{
usageIndex = j;
usageIndexes[i] = usageIndex;
}
positions[i * row + j] = x;
positions[i * row + j + 1] = y;
prevX = x;
prevY = y;
}
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void prepare(float *positions, int *usageIndexes, int count, int iterations,
float *random, float minScale, float maxScale,
float minX, float maxX, float minY)
{
int id = blockIdx.x * blockDim.x + threadIdx.x, jump = gridDim.x * blockDim.x, i,
row = iterations * 2 + 1;
float x, y, scale;
// for each snowflake
for (i = id; i < count; i += jump)
{
// reset usageIndex
usageIndexes[i] = 0;
scale = random[i] * (maxScale - minScale) + minScale;
// starting positions
x = random[i + 1] * (maxX - minX) + minX;
y = minY;
// store in positions
positions[i * row + 0] = scale;
positions[i * row + 1] = x;
positions[i * row + 2] = y;
}
}
extern "C"
__global__ void calculate(float *positions, int *usageIndexes, int count, int iterations,
float wind, float angle, float gravity, float maxX, float minX, float maxY)
{
int id = blockIdx.x * blockDim.x + threadIdx.x, jump = gridDim.x * blockDim.x, i, j, usageIndex,
row = iterations * 2 + 1;
float x, y, windX, windY, scale, sin, cos, prevX, prevY;
// trigonometrics used for wind force
sincosf(angle, &sin, &cos);
windX = wind * sin;
windY = wind * cos;
// for each snowflake
for (i = id; i < count; i += jump)
{
scale = positions[i * row + 0];
usageIndex = usageIndexes[i];
prevX = positions[i * row + 1];
prevY = positions[i * row + 2];
// starting from index 2, as <0, 2> is to be prepared earlier
for (j = 3; j < iterations * 2 + 1; j += 2)
{
x = prevX + windX;
if (x < minX)
{
x = maxX + x - minX;
}
else if (x > maxX)
{
x = minX + x - maxX;
}
y = prevY + gravity * scale + windY;
if (y > maxY && usageIndex == 0)
{
usageIndex = j;
usageIndexes[i] = usageIndex;
}
positions[i * row + j] = x;
positions[i * row + j + 1] = y;
prevX = x;
prevY = y;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void prepare(float *positions, int *usageIndexes, int count, int iterations,
float *random, float minScale, float maxScale,
float minX, float maxX, float minY)
{
int id = blockIdx.x * blockDim.x + threadIdx.x, jump = gridDim.x * blockDim.x, i,
row = iterations * 2 + 1;
float x, y, scale;
// for each snowflake
for (i = id; i < count; i += jump)
{
// reset usageIndex
usageIndexes[i] = 0;
scale = random[i] * (maxScale - minScale) + minScale;
// starting positions
x = random[i + 1] * (maxX - minX) + minX;
y = minY;
// store in positions
positions[i * row + 0] = scale;
positions[i * row + 1] = x;
positions[i * row + 2] = y;
}
}
extern "C"
__global__ void calculate(float *positions, int *usageIndexes, int count, int iterations,
float wind, float angle, float gravity, float maxX, float minX, float maxY)
{
int id = blockIdx.x * blockDim.x + threadIdx.x, jump = gridDim.x * blockDim.x, i, j, usageIndex,
row = iterations * 2 + 1;
float x, y, windX, windY, scale, sin, cos, prevX, prevY;
// trigonometrics used for wind force
sincosf(angle, &sin, &cos);
windX = wind * sin;
windY = wind * cos;
// for each snowflake
for (i = id; i < count; i += jump)
{
scale = positions[i * row + 0];
usageIndex = usageIndexes[i];
prevX = positions[i * row + 1];
prevY = positions[i * row + 2];
// starting from index 2, as <0, 2> is to be prepared earlier
for (j = 3; j < iterations * 2 + 1; j += 2)
{
x = prevX + windX;
if (x < minX)
{
x = maxX + x - minX;
}
else if (x > maxX)
{
x = minX + x - maxX;
}
y = prevY + gravity * scale + windY;
if (y > maxY && usageIndex == 0)
{
usageIndex = j;
usageIndexes[i] = usageIndex;
}
positions[i * row + j] = x;
positions[i * row + j + 1] = y;
prevX = x;
prevY = y;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected prepare
.globl prepare
.p2align 8
.type prepare,@function
prepare:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b32 s16, s[0:1], 0x10
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[3:4], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s16, v3
s_cbranch_execz .LBB0_3
s_load_b32 s13, s[2:3], 0x0
s_clause 0x4
s_load_b32 s14, s[0:1], 0x14
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x28
s_load_b32 s15, s[0:1], 0x30
s_load_b128 s[8:11], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s13, s12
s_lshl_b32 s0, s14, 1
v_sub_f32_e64 v9, s7, s6
s_or_b32 s0, s0, 1
v_sub_f32_e64 v10, s3, s2
v_mul_lo_u32 v5, v3, s0
v_mov_b32_e32 v2, s15
s_ashr_i32 s13, s12, 31
s_mul_i32 s1, s12, s0
s_lshl_b64 s[14:15], s[12:13], 2
s_mov_b32 s3, 0
.p2align 6
.LBB0_2:
v_add_co_u32 v0, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v8, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v8, vcc_lo
global_store_b32 v[0:1], v4, off
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v3, s12, v3
global_load_b64 v[0:1], v[11:12], off
v_add_co_u32 v7, vcc_lo, v7, s14
v_lshlrev_b64 v[11:12], 2, v[5:6]
v_add_co_ci_u32_e32 v8, vcc_lo, s15, v8, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s16, v3
v_add_nc_u32_e32 v5, s1, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s0, s8, v11
v_add_co_ci_u32_e64 v12, s0, s9, v12, s0
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_fma_f32 v0, v9, v0, s6
v_fma_f32 v1, v10, v1, s2
global_store_b96 v[11:12], v[0:2], off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel prepare
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size prepare, .Lfunc_end0-prepare
.section .AMDGPU.csdata,"",@progbits
.text
.protected calculate
.globl calculate
.p2align 8
.type calculate,@function
calculate:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
v_cmp_ngt_f32_e64 s3, 0x48000000, |s2|
s_and_b32 s4, s2, 0x7fffffff
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB1_2
s_and_b32 s3, s4, 0x7fffff
s_lshr_b32 s5, s4, 23
s_bitset1_b32 s3, 23
s_addk_i32 s5, 0xff88
s_mul_hi_u32 s6, s3, 0xfe5163ab
s_mul_i32 s7, s3, 0x3c439041
s_mul_hi_u32 s8, s3, 0x3c439041
s_add_u32 s6, s6, s7
s_addc_u32 s7, 0, s8
s_mul_i32 s8, s3, 0xdb629599
s_mul_hi_u32 s9, s3, 0xdb629599
s_add_u32 s7, s7, s8
s_addc_u32 s8, 0, s9
s_mul_i32 s9, s3, 0xf534ddc0
s_mul_hi_u32 s10, s3, 0xf534ddc0
s_add_u32 s8, s8, s9
s_addc_u32 s9, 0, s10
s_mul_i32 s10, s3, 0xfc2757d1
s_mul_hi_u32 s11, s3, 0xfc2757d1
s_add_u32 s9, s9, s10
s_addc_u32 s10, 0, s11
s_mul_i32 s11, s3, 0x4e441529
s_mul_hi_u32 s12, s3, 0x4e441529
s_add_u32 s10, s10, s11
s_addc_u32 s11, 0, s12
s_cmp_gt_u32 s5, 63
s_mul_i32 s12, s3, 0xfe5163ab
s_mul_hi_u32 s13, s3, 0xa2f9836e
s_mul_i32 s3, s3, 0xa2f9836e
s_cselect_b32 s14, s7, s9
s_cselect_b32 s6, s6, s8
s_cselect_b32 s7, s12, s7
s_add_u32 s3, s11, s3
s_addc_u32 s11, 0, s13
s_cmp_gt_u32 s5, 63
s_cselect_b32 s12, 0xffffffc0, 0
s_cselect_b32 s8, s8, s10
s_cselect_b32 s3, s9, s3
s_cselect_b32 s9, s10, s11
s_add_i32 s12, s12, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s12, 31
s_cselect_b32 s5, 0xffffffe0, 0
s_cselect_b32 s10, s8, s3
s_cselect_b32 s3, s3, s9
s_cselect_b32 s8, s14, s8
s_cselect_b32 s9, s6, s14
s_cselect_b32 s6, s7, s6
s_add_i32 s5, s5, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s5, 31
s_cselect_b32 s7, 0xffffffe0, 0
s_cselect_b32 s3, s10, s3
s_cselect_b32 s10, s8, s10
s_cselect_b32 s8, s9, s8
s_cselect_b32 s6, s6, s9
s_add_i32 s7, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_i32 s5, 32, s7
s_cmp_eq_u32 s7, 0
v_mov_b32_e32 v1, s5
s_cselect_b32 s7, -1, 0
v_alignbit_b32 v2, s3, s10, v1
v_alignbit_b32 v3, s10, s8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s5, v2
v_cndmask_b32_e64 v2, v3, s10, s7
s_delay_alu instid0(VALU_DEP_2)
s_cselect_b32 s3, s3, s5
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v3, s3, v2, 30
s_bfe_u32 s5, s3, 0x1001d
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_xor_b32_e32 v3, s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v4, v3
v_min_u32_e32 v4, 32, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 23, v4
v_alignbit_b32 v1, s8, s6, v1
v_sub_nc_u32_e32 v5, 31, v4
v_cndmask_b32_e64 v1, v1, s8, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v2, v2, v1, 30
v_alignbit_b32 v1, v1, s6, 30
s_lshr_b32 s6, s3, 29
s_lshl_b32 s6, s6, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v2, s9, v2
v_xor_b32_e32 v1, s9, v1
s_or_b32 s7, s6, 0.5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v6, s7, v6
v_alignbit_b32 v3, v3, v2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v1, v2, v1, v5
v_alignbit_b32 v2, v3, v1, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v5, v2
v_min_u32_e32 v5, 32, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, 31, v5
v_alignbit_b32 v1, v2, v1, v7
v_lshrrev_b32_e32 v2, 9, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v1, 9, v1
v_or_b32_e32 v2, v2, v6
v_add_nc_u32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 23, v4
v_sub_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x3fc90fda, v2
v_add_nc_u32_e32 v1, 0x33000000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, v2, 0x3fc90fda, -v3
v_or_b32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_fmamk_f32 v2, v2, 0x33a22168, v4
s_lshr_b32 s6, s3, 30
s_mov_b32 s3, 0
s_add_i32 s6, s5, s6
v_fmac_f32_e32 v2, 0x3fc90fda, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v1, v3, v2
s_branch .LBB1_3
.LBB1_2:
s_mov_b32 s3, -1
.LBB1_3:
s_load_b32 s5, s[0:1], 0x3c
v_mov_b32_e32 v2, s6
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB1_5
v_mul_f32_e64 v1, 0x3f22f983, |s2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v2, v1
v_fma_f32 v1, v2, 0xbfc90fda, |s2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v2, 0xb3a22168, v1
v_fmamk_f32 v1, v2, 0xa7c234c4, v1
v_cvt_i32_f32_e32 v2, v2
.LBB1_5:
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s13, 0xffff, s5
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[3:4], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v3
s_cbranch_execz .LBB1_19
v_mul_f32_e32 v0, v1, v1
s_mov_b32 s5, 0xb94c1982
s_mov_b32 s6, 0x37d75334
s_clause 0x1
s_load_b64 s[14:15], s[0:1], 0x14
s_load_b32 s16, s[0:1], 0x30
v_fmaak_f32 v4, s5, v0, 0x3c0881c4
v_dual_fmaak_f32 v5, s6, v0, 0xbab64f3b :: v_dual_and_b32 v6, 1, v2
s_xor_b32 s4, s4, s2
v_lshlrev_b32_e32 v2, 30, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmaak_f32 v4, v0, v4, 0xbe2aaa9d
v_fmaak_f32 v5, v0, v5, 0x3d2aabf7
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_and_b32_e32 v2, 0x80000000, v2
v_mul_f32_e32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v5, v0, v5, 0xbf000004
v_fmac_f32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f32 v0, v0, v5, 1.0
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s16, s13
v_cndmask_b32_e32 v4, v0, v1, vcc_lo
v_cndmask_b32_e64 v0, -v1, v0, vcc_lo
v_cmp_class_f32_e64 vcc_lo, s2, 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v2, v0
v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v7, s15, v0
v_xor_b32_e32 v1, s4, v4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b128 s[8:11], s[0:1], 0x20
s_lshl_b32 s1, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s1, 1
v_xor_b32_e32 v1, v1, v2
v_mul_lo_u32 v6, v3, s2
s_cmp_gt_i32 s14, 1
s_mov_b32 s14, 0
s_cselect_b32 s12, -1, 0
v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v8, s15, v1
s_mul_i32 s15, s13, s2
s_branch .LBB1_8
.LBB1_7:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v3, s13, v3
v_add_nc_u32_e32 v6, s15, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v3
s_or_b32 s14, vcc_lo, s14
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB1_19
.LBB1_8:
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB1_7
v_mul_lo_u32 v0, v3, s2
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s16, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b96 v[0:2], v[0:1], off
global_load_b32 v9, v[4:5], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v0, s8, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_11
.p2align 6
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v10, s16, v6
s_add_i32 s16, s16, 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_le_i32 s16, s1
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
global_store_b64 v[10:11], v[1:2], off
s_cbranch_scc0 .LBB1_7
.LBB1_11:
v_add_f32_e32 v1, v8, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f32_e32 s10, v1
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB1_15
s_mov_b32 s17, exec_lo
v_cmpx_lt_f32_e32 s9, v1
v_add_f32_e32 v1, s10, v1
s_delay_alu instid0(VALU_DEP_1)
v_subrev_f32_e32 v1, s9, v1
s_or_b32 exec_lo, exec_lo, s17
.LBB1_15:
s_and_not1_saveexec_b32 s0, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, s9, v1
v_subrev_f32_e32 v1, s10, v1
s_or_b32 exec_lo, exec_lo, s0
v_add_f32_e32 v2, v0, v2
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, 0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v7, v2
v_cmp_lt_f32_e32 vcc_lo, s11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s17, vcc_lo, s0
s_and_saveexec_b32 s0, s17
s_cbranch_execz .LBB1_10
v_mov_b32_e32 v9, s16
global_store_b32 v[4:5], v9, off
s_branch .LBB1_10
.LBB1_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel calculate
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size calculate, .Lfunc_end1-calculate
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: prepare
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: prepare.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: calculate
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: calculate.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void prepare(float *positions, int *usageIndexes, int count, int iterations,
float *random, float minScale, float maxScale,
float minX, float maxX, float minY)
{
int id = blockIdx.x * blockDim.x + threadIdx.x, jump = gridDim.x * blockDim.x, i,
row = iterations * 2 + 1;
float x, y, scale;
// for each snowflake
for (i = id; i < count; i += jump)
{
// reset usageIndex
usageIndexes[i] = 0;
scale = random[i] * (maxScale - minScale) + minScale;
// starting positions
x = random[i + 1] * (maxX - minX) + minX;
y = minY;
// store in positions
positions[i * row + 0] = scale;
positions[i * row + 1] = x;
positions[i * row + 2] = y;
}
}
extern "C"
__global__ void calculate(float *positions, int *usageIndexes, int count, int iterations,
float wind, float angle, float gravity, float maxX, float minX, float maxY)
{
int id = blockIdx.x * blockDim.x + threadIdx.x, jump = gridDim.x * blockDim.x, i, j, usageIndex,
row = iterations * 2 + 1;
float x, y, windX, windY, scale, sin, cos, prevX, prevY;
// trigonometrics used for wind force
sincosf(angle, &sin, &cos);
windX = wind * sin;
windY = wind * cos;
// for each snowflake
for (i = id; i < count; i += jump)
{
scale = positions[i * row + 0];
usageIndex = usageIndexes[i];
prevX = positions[i * row + 1];
prevY = positions[i * row + 2];
// starting from index 2, as <0, 2> is to be prepared earlier
for (j = 3; j < iterations * 2 + 1; j += 2)
{
x = prevX + windX;
if (x < minX)
{
x = maxX + x - minX;
}
else if (x > maxX)
{
x = minX + x - maxX;
}
y = prevY + gravity * scale + windY;
if (y > maxY && usageIndex == 0)
{
usageIndex = j;
usageIndexes[i] = usageIndex;
}
positions[i * row + j] = x;
positions[i * row + j + 1] = y;
prevX = x;
prevY = y;
}
}
} | .text
.file "SnowflakeSimulation.hip"
.globl __device_stub__prepare # -- Begin function __device_stub__prepare
.p2align 4, 0x90
.type __device_stub__prepare,@function
__device_stub__prepare: # @__device_stub__prepare
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 88(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $prepare, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size __device_stub__prepare, .Lfunc_end0-__device_stub__prepare
.cfi_endproc
# -- End function
.globl __device_stub__calculate # -- Begin function __device_stub__calculate
.p2align 4, 0x90
.type __device_stub__calculate,@function
__device_stub__calculate: # @__device_stub__calculate
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movss %xmm5, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $calculate, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size __device_stub__calculate, .Lfunc_end1-__device_stub__calculate
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $prepare, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $calculate, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type prepare,@object # @prepare
.section .rodata,"a",@progbits
.globl prepare
.p2align 3, 0x0
prepare:
.quad __device_stub__prepare
.size prepare, 8
.type calculate,@object # @calculate
.globl calculate
.p2align 3, 0x0
calculate:
.quad __device_stub__calculate
.size calculate, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "prepare"
.size .L__unnamed_1, 8
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "calculate"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__prepare
.addrsig_sym __device_stub__calculate
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym prepare
.addrsig_sym calculate
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00015690_00000000-6_SnowflakeSimulation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff
.type _Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff, @function
_Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movq %r8, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq prepare(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff, .-_Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff
.globl prepare
.type prepare, @function
prepare:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z7preparePfPiiiS_fffffPfPiiiS_fffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size prepare, .-prepare
.globl _Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff
.type _Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff, @function
_Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff:
.LFB2053:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movss %xmm5, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq calculate(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff, .-_Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff
.globl calculate
.type calculate, @function
calculate:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9calculatePfPiiiffffffPfPiiiffffff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size calculate, .-calculate
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "calculate"
.LC1:
.string "prepare"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq calculate(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq prepare(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SnowflakeSimulation.hip"
.globl __device_stub__prepare # -- Begin function __device_stub__prepare
.p2align 4, 0x90
.type __device_stub__prepare,@function
__device_stub__prepare: # @__device_stub__prepare
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 88(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $prepare, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size __device_stub__prepare, .Lfunc_end0-__device_stub__prepare
.cfi_endproc
# -- End function
.globl __device_stub__calculate # -- Begin function __device_stub__calculate
.p2align 4, 0x90
.type __device_stub__calculate,@function
__device_stub__calculate: # @__device_stub__calculate
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, 4(%rsp)
movss %xmm5, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $calculate, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size __device_stub__calculate, .Lfunc_end1-__device_stub__calculate
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $prepare, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $calculate, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type prepare,@object # @prepare
.section .rodata,"a",@progbits
.globl prepare
.p2align 3, 0x0
prepare:
.quad __device_stub__prepare
.size prepare, 8
.type calculate,@object # @calculate
.globl calculate
.p2align 3, 0x0
calculate:
.quad __device_stub__calculate
.size calculate, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "prepare"
.size .L__unnamed_1, 8
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "calculate"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__prepare
.addrsig_sym __device_stub__calculate
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym prepare
.addrsig_sym calculate
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// Function that catches the error
void testCUDA(cudaError_t error, const char *file, int line) {
if (error != cudaSuccess) {
printf("There is an error in file %s at line %d\n", file, line);
exit(EXIT_FAILURE);
}
}
// Has to be defined in the compilation in order to get the correct value of the
// macros __FILE__ and __LINE__
#define testCUDA(error) (testCUDA(error, __FILE__ , __LINE__))
__global__ void empty_k(void){
// printf("Hello World!\n");
printf("thread idx %d, block idx %d\n", threadIdx.x, blockIdx.x);
}
int main (void){
// threads are synchronized by group of 32
empty_k<<<8,2>>>(); // <number of block, number of thread per block>
cudaDeviceSynchronize();
int deviceCount;
cudaGetDeviceCount(&deviceCount);
printf("Number of GPUs: %d\n", deviceCount);
cudaDeviceProp deviceProp;
// testCUDA(cudaGetDeviceProperties(&deviceProp, deviceCount)); // will return error
cudaGetDeviceProperties(&deviceProp, deviceCount-1);
printf("Device %d has compute capability %d.%d.\n",
deviceCount-1, deviceProp.major, deviceProp.minor);
printf("Name: %s\n", deviceProp.name);
printf("Number of processors: %d\n", 128*deviceProp.multiProcessorCount);
printf("GPU RAM size in bytes: %zd\n", deviceProp.totalGlobalMem);
printf("Shared memory per block in bytes: %zd\n", deviceProp.sharedMemPerBlock);
/*************************************************************
Once requested, replace this comment by the appropriate code
*************************************************************/
return 0;
} | code for sm_80
Function : _Z7empty_kv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// Function that catches the error
void testCUDA(cudaError_t error, const char *file, int line) {
if (error != cudaSuccess) {
printf("There is an error in file %s at line %d\n", file, line);
exit(EXIT_FAILURE);
}
}
// Has to be defined in the compilation in order to get the correct value of the
// macros __FILE__ and __LINE__
#define testCUDA(error) (testCUDA(error, __FILE__ , __LINE__))
__global__ void empty_k(void){
// printf("Hello World!\n");
printf("thread idx %d, block idx %d\n", threadIdx.x, blockIdx.x);
}
int main (void){
// threads are synchronized by group of 32
empty_k<<<8,2>>>(); // <number of block, number of thread per block>
cudaDeviceSynchronize();
int deviceCount;
cudaGetDeviceCount(&deviceCount);
printf("Number of GPUs: %d\n", deviceCount);
cudaDeviceProp deviceProp;
// testCUDA(cudaGetDeviceProperties(&deviceProp, deviceCount)); // will return error
cudaGetDeviceProperties(&deviceProp, deviceCount-1);
printf("Device %d has compute capability %d.%d.\n",
deviceCount-1, deviceProp.major, deviceProp.minor);
printf("Name: %s\n", deviceProp.name);
printf("Number of processors: %d\n", 128*deviceProp.multiProcessorCount);
printf("GPU RAM size in bytes: %zd\n", deviceProp.totalGlobalMem);
printf("Shared memory per block in bytes: %zd\n", deviceProp.sharedMemPerBlock);
/*************************************************************
Once requested, replace this comment by the appropriate code
*************************************************************/
return 0;
} | .file "tmpxft_00094720_00000000-6_DevQuery.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "There is an error in file %s at line %d\n"
.text
.globl _Z8testCUDA9cudaErrorPKci
.type _Z8testCUDA9cudaErrorPKci, @function
_Z8testCUDA9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edx, %ecx
movq %rsi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8testCUDA9cudaErrorPKci, .-_Z8testCUDA9cudaErrorPKci
.globl _Z25__device_stub__Z7empty_kvv
.type _Z25__device_stub__Z7empty_kvv, @function
_Z25__device_stub__Z7empty_kvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7empty_kv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z25__device_stub__Z7empty_kvv, .-_Z25__device_stub__Z7empty_kvv
.globl _Z7empty_kv
.type _Z7empty_kv, @function
_Z7empty_kv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7empty_kvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7empty_kv, .-_Z7empty_kv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of GPUs: %d\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "Device %d has compute capability %d.%d.\n"
.section .rodata.str1.1
.LC3:
.string "Name: %s\n"
.LC4:
.string "Number of processors: %d\n"
.LC5:
.string "GPU RAM size in bytes: %zd\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Shared memory per block in bytes: %zd\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1072, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
call cudaDeviceSynchronize@PLT
leaq 20(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 20(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 20(%rsp), %eax
leal -1(%rax), %esi
leaq 32(%rsp), %rbx
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 20(%rsp), %eax
leal -1(%rax), %edx
movl 396(%rsp), %r8d
movl 392(%rsp), %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %edx
sall $7, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $1072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call _Z25__device_stub__Z7empty_kvv
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z7empty_kv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7empty_kv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// Function that catches the error
void testCUDA(cudaError_t error, const char *file, int line) {
if (error != cudaSuccess) {
printf("There is an error in file %s at line %d\n", file, line);
exit(EXIT_FAILURE);
}
}
// Has to be defined in the compilation in order to get the correct value of the
// macros __FILE__ and __LINE__
#define testCUDA(error) (testCUDA(error, __FILE__ , __LINE__))
__global__ void empty_k(void){
// printf("Hello World!\n");
printf("thread idx %d, block idx %d\n", threadIdx.x, blockIdx.x);
}
int main (void){
// threads are synchronized by group of 32
empty_k<<<8,2>>>(); // <number of block, number of thread per block>
cudaDeviceSynchronize();
int deviceCount;
cudaGetDeviceCount(&deviceCount);
printf("Number of GPUs: %d\n", deviceCount);
cudaDeviceProp deviceProp;
// testCUDA(cudaGetDeviceProperties(&deviceProp, deviceCount)); // will return error
cudaGetDeviceProperties(&deviceProp, deviceCount-1);
printf("Device %d has compute capability %d.%d.\n",
deviceCount-1, deviceProp.major, deviceProp.minor);
printf("Name: %s\n", deviceProp.name);
printf("Number of processors: %d\n", 128*deviceProp.multiProcessorCount);
printf("GPU RAM size in bytes: %zd\n", deviceProp.totalGlobalMem);
printf("Shared memory per block in bytes: %zd\n", deviceProp.sharedMemPerBlock);
/*************************************************************
Once requested, replace this comment by the appropriate code
*************************************************************/
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// Function that catches the error
void testCUDA(hipError_t error, const char *file, int line) {
if (error != hipSuccess) {
printf("There is an error in file %s at line %d\n", file, line);
exit(EXIT_FAILURE);
}
}
// Has to be defined in the compilation in order to get the correct value of the
// macros __FILE__ and __LINE__
#define testCUDA(error) (testCUDA(error, __FILE__ , __LINE__))
__global__ void empty_k(void){
// printf("Hello World!\n");
printf("thread idx %d, block idx %d\n", threadIdx.x, blockIdx.x);
}
int main (void){
// threads are synchronized by group of 32
empty_k<<<8,2>>>(); // <number of block, number of thread per block>
hipDeviceSynchronize();
int deviceCount;
hipGetDeviceCount(&deviceCount);
printf("Number of GPUs: %d\n", deviceCount);
hipDeviceProp_t deviceProp;
// testCUDA(cudaGetDeviceProperties(&deviceProp, deviceCount)); // will return error
hipGetDeviceProperties(&deviceProp, deviceCount-1);
printf("Device %d has compute capability %d.%d.\n",
deviceCount-1, deviceProp.major, deviceProp.minor);
printf("Name: %s\n", deviceProp.name);
printf("Number of processors: %d\n", 128*deviceProp.multiProcessorCount);
printf("GPU RAM size in bytes: %zd\n", deviceProp.totalGlobalMem);
printf("Shared memory per block in bytes: %zd\n", deviceProp.sharedMemPerBlock);
/*************************************************************
Once requested, replace this comment by the appropriate code
*************************************************************/
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// Function that catches the error
void testCUDA(hipError_t error, const char *file, int line) {
if (error != hipSuccess) {
printf("There is an error in file %s at line %d\n", file, line);
exit(EXIT_FAILURE);
}
}
// Has to be defined in the compilation in order to get the correct value of the
// macros __FILE__ and __LINE__
#define testCUDA(error) (testCUDA(error, __FILE__ , __LINE__))
__global__ void empty_k(void){
// printf("Hello World!\n");
printf("thread idx %d, block idx %d\n", threadIdx.x, blockIdx.x);
}
int main (void){
// threads are synchronized by group of 32
empty_k<<<8,2>>>(); // <number of block, number of thread per block>
hipDeviceSynchronize();
int deviceCount;
hipGetDeviceCount(&deviceCount);
printf("Number of GPUs: %d\n", deviceCount);
hipDeviceProp_t deviceProp;
// testCUDA(cudaGetDeviceProperties(&deviceProp, deviceCount)); // will return error
hipGetDeviceProperties(&deviceProp, deviceCount-1);
printf("Device %d has compute capability %d.%d.\n",
deviceCount-1, deviceProp.major, deviceProp.minor);
printf("Name: %s\n", deviceProp.name);
printf("Number of processors: %d\n", 128*deviceProp.multiProcessorCount);
printf("GPU RAM size in bytes: %zd\n", deviceProp.totalGlobalMem);
printf("Shared memory per block in bytes: %zd\n", deviceProp.sharedMemPerBlock);
/*************************************************************
Once requested, replace this comment by the appropriate code
*************************************************************/
return 0;
} | .text
.file "DevQuery.hip"
.globl _Z8testCUDA10hipError_tPKci # -- Begin function _Z8testCUDA10hipError_tPKci
.p2align 4, 0x90
.type _Z8testCUDA10hipError_tPKci,@function
_Z8testCUDA10hipError_tPKci: # @_Z8testCUDA10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z8testCUDA10hipError_tPKci, .Lfunc_end0-_Z8testCUDA10hipError_tPKci
.cfi_endproc
# -- End function
.globl _Z22__device_stub__empty_kv # -- Begin function _Z22__device_stub__empty_kv
.p2align 4, 0x90
.type _Z22__device_stub__empty_kv,@function
_Z22__device_stub__empty_kv: # @_Z22__device_stub__empty_kv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7empty_kv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z22__device_stub__empty_kv, .Lfunc_end1-_Z22__device_stub__empty_kv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1520, %rsp # imm = 0x5F0
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -16
movabsq $4294967298, %rdx # imm = 0x100000002
leaq 6(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 48(%rsp), %rdi
movq %rsp, %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7empty_kv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq %rsp, %rdi
callq hipGetDeviceCount
movl (%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl (%rsp), %esi
decl %esi
leaq 48(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl (%rsp), %esi
decl %esi
movl 408(%rsp), %edx
movl 412(%rsp), %ecx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 436(%rsp), %esi
shll $7, %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 336(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 344(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1520, %rsp # imm = 0x5F0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7empty_kv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "There is an error in file %s at line %d\n"
.size .L.str, 41
.type _Z7empty_kv,@object # @_Z7empty_kv
.section .rodata,"a",@progbits
.globl _Z7empty_kv
.p2align 3, 0x0
_Z7empty_kv:
.quad _Z22__device_stub__empty_kv
.size _Z7empty_kv, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Number of GPUs: %d\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device %d has compute capability %d.%d.\n"
.size .L.str.2, 41
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Name: %s\n"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Number of processors: %d\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU RAM size in bytes: %zd\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Shared memory per block in bytes: %zd\n"
.size .L.str.6, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7empty_kv"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__empty_kv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7empty_kv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00094720_00000000-6_DevQuery.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "There is an error in file %s at line %d\n"
.text
.globl _Z8testCUDA9cudaErrorPKci
.type _Z8testCUDA9cudaErrorPKci, @function
_Z8testCUDA9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edx, %ecx
movq %rsi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8testCUDA9cudaErrorPKci, .-_Z8testCUDA9cudaErrorPKci
.globl _Z25__device_stub__Z7empty_kvv
.type _Z25__device_stub__Z7empty_kvv, @function
_Z25__device_stub__Z7empty_kvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7empty_kv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z25__device_stub__Z7empty_kvv, .-_Z25__device_stub__Z7empty_kvv
.globl _Z7empty_kv
.type _Z7empty_kv, @function
_Z7empty_kv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7empty_kvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7empty_kv, .-_Z7empty_kv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of GPUs: %d\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "Device %d has compute capability %d.%d.\n"
.section .rodata.str1.1
.LC3:
.string "Name: %s\n"
.LC4:
.string "Number of processors: %d\n"
.LC5:
.string "GPU RAM size in bytes: %zd\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Shared memory per block in bytes: %zd\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1072, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
call cudaDeviceSynchronize@PLT
leaq 20(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 20(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 20(%rsp), %eax
leal -1(%rax), %esi
leaq 32(%rsp), %rbx
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 20(%rsp), %eax
leal -1(%rax), %edx
movl 396(%rsp), %r8d
movl 392(%rsp), %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %edx
sall $7, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $1072, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call _Z25__device_stub__Z7empty_kvv
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z7empty_kv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7empty_kv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DevQuery.hip"
.globl _Z8testCUDA10hipError_tPKci # -- Begin function _Z8testCUDA10hipError_tPKci
.p2align 4, 0x90
.type _Z8testCUDA10hipError_tPKci,@function
_Z8testCUDA10hipError_tPKci: # @_Z8testCUDA10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z8testCUDA10hipError_tPKci, .Lfunc_end0-_Z8testCUDA10hipError_tPKci
.cfi_endproc
# -- End function
.globl _Z22__device_stub__empty_kv # -- Begin function _Z22__device_stub__empty_kv
.p2align 4, 0x90
.type _Z22__device_stub__empty_kv,@function
_Z22__device_stub__empty_kv: # @_Z22__device_stub__empty_kv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7empty_kv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z22__device_stub__empty_kv, .Lfunc_end1-_Z22__device_stub__empty_kv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1520, %rsp # imm = 0x5F0
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -16
movabsq $4294967298, %rdx # imm = 0x100000002
leaq 6(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 48(%rsp), %rdi
movq %rsp, %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7empty_kv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq %rsp, %rdi
callq hipGetDeviceCount
movl (%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl (%rsp), %esi
decl %esi
leaq 48(%rsp), %rbx
movq %rbx, %rdi
callq hipGetDevicePropertiesR0600
movl (%rsp), %esi
decl %esi
movl 408(%rsp), %edx
movl 412(%rsp), %ecx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 436(%rsp), %esi
shll $7, %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 336(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 344(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $1520, %rsp # imm = 0x5F0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7empty_kv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "There is an error in file %s at line %d\n"
.size .L.str, 41
.type _Z7empty_kv,@object # @_Z7empty_kv
.section .rodata,"a",@progbits
.globl _Z7empty_kv
.p2align 3, 0x0
_Z7empty_kv:
.quad _Z22__device_stub__empty_kv
.size _Z7empty_kv, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Number of GPUs: %d\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device %d has compute capability %d.%d.\n"
.size .L.str.2, 41
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Name: %s\n"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Number of processors: %d\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "GPU RAM size in bytes: %zd\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Shared memory per block in bytes: %zd\n"
.size .L.str.6, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7empty_kv"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__empty_kv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7empty_kv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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