code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SevenSegmentController #(
parameter CLOCK_DIVISIONS = 17,
parameter DIGITS = 8
) (
input wire clock,
input wire reset,
input wire [DIGITS*4 - 1 : 0] data,
input wire [ DIGITS-1 : 0] pointEnable,
output wire [ 7 : 0] segmentEnableN,
output wire [DIGITS-1 : 0] di... | 7.512435 |
module SevenSegmentController_top (
input wire clock,
input wire resetN,
input wire [15:0] switches,
input wire toggleButton,
input wire leftButton,
input wire rightButton,
output wire [7:0] segmentEnableN,
output wire [7:0] digitEnableN,
output wire [3:0] leds... | 7.512435 |
module SevenSegmentCounter (
input CLK_50, //Defining the 50MHz Clock of the Kiwi as an input
output [6:0] HEX0, //Defining the 7 Segment displays of the Kiwi as an output
output [6:0] HEX1, //Note: these definitions were made using the μLab Kiwi Project Generator.
output [6:0] HEX2
);
reg [32:0... | 7.512435 |
module SevenSegmentDays (
bcd,
leds2,
leds1,
leds0
);
input [6:0] bcd;
output reg [0:6] leds2, leds1, leds0;
always @(bcd)
case (bcd % 7) // abcdefg
0: begin //mon
leds0 = 7'b1101010;
leds1 = 7'b1100010;
leds2 = 7'b0001001;
end
1: begin //tue
... | 6.704212 |
module SevenSegmentDE1 (
input [1:0] c,
output [6:0] hex
);
assign hex[0] = c[0] | ~c[1];
assign hex[1] = c[1];
assign hex[2] = c[1];
assign hex[3] = c[0];
assign hex[4] = c[0];
assign hex[5] = c[0] | ~c[1];
assign hex[6] = c[0];
endmodule
| 6.704212 |
module SevenSegmentDecoder (
INP,
SEG
); //Module names and I/o pins are declared
input [3:0] INP; // 4 bit input which is connected to 4 switches
output [0:6] SEG; // 8 bit output which is connected to seven segment display
reg [0:6] SEG; // 7 bit register to save the seven segment code
always @(I... | 6.704212 |
module SevenSegment (
numin,
segout
);
input [3:0] numin;
output reg [6:0] segout; //segout[6] - seg_a, segout[5] - seg_b, segout[4] - seg_c,
//segout[3] - seg_d, segout[2] - seg_e, segout[1] - seg_f, segout[0] - seg_g
always @(numin) begin
case (numin)
4'b0000: sego... | 7.922915 |
module SevenSegmentDisplayDecoder (
ssOut,
nIn
);
output [6:0] ssOut;
reg [6:0] ssOut_tmp;
input [3:0] nIn;
// ssOut format {g, f, e, d, c, b, a}
always @*
case (nIn)
4'h0: ssOut_tmp = 7'b0111111;
4'h1: ssOut_tmp = 7'b0000110;
4'h2: ssOut_tmp = 7'b1011011;
4'h3: ssOut_tmp... | 6.704212 |
module int4bitToHexSSD (
in,
out
);
parameter zero = 7'b0000001, one = 7'b1001111, two = 7'b0010010;
parameter thr = 7'b0000110, four = 7'b1001100, five = 7'b0100100;
parameter six = 7'b0100000, svn = 7'b0001111, eght = 7'b0000000;
parameter nine = 7'b0000100, A = 7'b0001000, B = 7'b1100000;
parameter... | 7.843305 |
module int5bitToHexSSD_bankVer (
in,
out
);
parameter zero = 7'b0000001, one = 7'b1001111, two = 7'b0010010; //in = 0, 1, 2
parameter thr = 7'b0000110, four = 7'b1001100, five = 7'b0100100; //in = 3, 4, 5 ~ 5 = s in ssd
parameter six = 7'b0100000, svn = 7'b0001111, eght = 7'b0000000; //in = 6, 7, 8
p... | 7.05707 |
module sevenSegmentDisplayDecoder_tb;
reg [3:0] i;
wire [6:0] o;
//D.U.T. instantiation
sevenSegmentDisplayDecoder sevSegDec (
o,
i
);
//初始化
initial begin
$dumpfile("Simulation/sevenSegmentDisplayDecoder_tb.vcd");
$dumpvars;
$monitor($time, " i=%4d -> o=%7b", i, o);
i = 4'b... | 7.910175 |
module SevenSegmentDisplayDriver #(
parameter DIGITS = 8, // this parameter should NOT be changed
parameter CLK_DIV = 4095 // 4095 is fine, too small a value will cause display to overlap
) (
input wire [DIGITS * 4 - 1:0] din, // hexadecimal input data
input wire clk, // fa... | 6.704212 |
module SevenSegmentDriver (
input slow128,
input [3:0] ones,
input [3:0] tens,
output [7:0] seg,
output an,
input DISPLAY_EN
);
localparam SEG1 = 4'b1110, SEG2 = 4'b1101;
//SEG3 = 4'b1011,
//SEG4 = 4'b0111;
reg [3:0] an = SEG1;
reg [3:0] pbInt;
wire slowCLKOut;
reg [3:0] multiPle... | 6.704212 |
module CathodeDriver (
input [3:0] pbInt,
input display,
output [7:0] segInt,
input Blinker
);
localparam OUT_ZERO = 8'b11000000,
OUT_ONE = 8'b11111001,
OUT_TWO = 8'b10100100,
OUT_THREE = 8'b10110000,
OUT_FOUR = 8'b10011001,
OUT_FIVE = 8'b10010010,
OUT_S... | 7.182471 |
module written by Cameron Braun
*
* @author caustin43@gatech.edu
* @author cameronbraun@gatech.edu
* @author mlewis61@gatech.edu
* @date 2019-10-02
*
*
* @param[in] data the data to encode
* @param[in] pointEnable display the decimal point on the "seven"-segment display
*
* @param[out] segme... | 7.261751 |
module sevensegment_calculator (
A,
B,
S,
C,
out
);
input [1:0] A, B, S;
output [3:0] out;
input C;
assign out[2:0] = S[1] ? (S[0] ? A * B : (C ? A - B : A + B)) : (S[0] ? ~(A & B) : A);
assign out[3] = 0;
endmodule
| 6.752135 |
module segment7 (
bcd,
seg
);
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
always @(bcd) begin
case (bcd)
0: seg = 7'b1000000;
1: seg = 7'b1111001;
2: seg = 7'b0100100;
3: seg = 7'b0110000;
4: seg = 7'b0011001;
5: seg = 7'b0010010;
6: seg = 7'b0000010;... | 6.533074 |
module SevenSegment_LastTwo (
input CLOCK,
input [4:0] mode,
output reg [7:0] seg,
output reg [3:0] an
);
reg [7:0] seg0, seg1, seg2, seg3;
wire [7:0] segment;
wire [3:0] anode;
SevenSegDisplay display (
CLOCK,
seg0,
seg1,
seg2,
seg3,
segment,
anode
);... | 8.083551 |
module SevenSegment_LED (
output reg [6:0] display,
output reg [3:0] digit,
output reg [15:0] led,
input wire rst,
input wire clk,
input wire [4:0] led_picked,
input wire [4:0] seg7_cd,
input wire [4:0] seg7_hp
);
reg [15:0] clk_divider;
reg [ 4:0] display_num;
always @(posedge c... | 8.083551 |
module: sevenSegment
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sevenSegment_TB;
// Inputs
reg [3:0] number;
// Outputs
wire [6:0] sevenSegmentPins;
// Instantiate the U... | 7.340639 |
module SevenSegMux (
output reg [0:3] out,
input [0:3] a,
b,
c,
d,
input [0:1] sel
);
//Simple 4 to 1 Mux that inputs 4 BCD digits and muxes them into BCD to 7seg led encoder, subsequently
always @(sel, a, b, c, d)
case (sel)
0: out = a;
1: out = b;
2: out = c;
3:... | 7.625088 |
module sevensegs (
SW,
HEX0
);
input [3:0] SW;
output reg [0:6] HEX0;
always @(*) begin
case (SW)
4'b0000: HEX0 = 7'b0000001;
4'b0001: HEX0 = 7'b1001111;
4'b0010: HEX0 = 7'b0010010;
4'b0011: HEX0 = 7'b0000110;
4'b0100: HEX0 = 7'b1001100;
4'b0101: HEX0 = 7'b0100100;... | 7.728532 |
module showdigit (
input i_Clk,
input [3:0] bcd,
output [6:0] HEX0
);
reg [6:0] r_Hex_Encoding = 7'h00;
always @(posedge i_Clk) begin
case (bcd)
4'b0000: r_Hex_Encoding <= 7'h7E;
4'b0001: r_Hex_Encoding <= 7'h30;
4'b0010: r_Hex_Encoding <= 7'h6D;
4'b0011: r_Hex_Encoding <= ... | 7.464833 |
module SevenSegScoreDisplay (
// input CLOCK_50, //for test
input clk,
input [7:0] score,
output [6:0] HEX2,
HEX1,
HEX0
);
// clk: 50MHz clock signal
// score: the score won in the game
reg [3:0] dig_2;
reg [3:0] dig_1;
reg [3:0] dig_0;
always @(posedge clk) begin
dig_2 <= s... | 7.109506 |
module dec_decoder (
dec_digit,
segments
);
input [3:0] dec_digit;
output reg [6:0] segments;
always @(*)
case (dec_digit)
4'd0: segments = 7'b100_0000;
4'd1: segments = 7'b111_1001;
4'd2: segments = 7'b010_0100;
4'd3: segments = 7'b011_0000;
4'd4: segments = 7'b001_1001... | 7.220437 |
module sevenseg_controller (
input clk_scan,
input rst,
input [11:0] value,
output [7:0] sevenseg_segments,
output [2:0] sevenseg_enables
);
reg [11:0] value_reg;
reg [ 2:0] sevenseg_enables_reg;
wire [ 7:0] sevenseg_segments_pos;
assign sevenseg_enables = ~sevenseg_enables_reg;
assig... | 6.607322 |
module SevenSeg_CTRL (
iCLK,
nRST,
iSEG7,
iSEG6,
iSEG5,
iSEG4,
iSEG3,
iSEG2,
iSEG1,
iSEG0,
oS_COM,
oS_ENS
);
// I/O definition------------------------------------------
input iCLK, nRST;
input [6:0] iSEG7, iSEG6, iSEG5, iSEG4, iSEG3, iSEG2, iSEG1, iSEG0;
output [... | 7.417278 |
module sevenseg_dec (
input [3:0] data,
output reg [7:0] segments
);
always @(data) begin
case (data)
4'h0: segments = 8'b000_0001_1;
4'h1: segments = 8'b100_1111_1;
4'h2: segments = 8'b001_0010_1;
4'h3: segments = 8'b000_0110_1;
4'h4: segments = 8'b100_1100_1;
4'h... | 6.957958 |
module sevenseg_decoder (
output [6:0] out,
input EN,
input [3:0] in
);
wire [6:0] w1;
assign w1= (in==4'b0000 )? 7'b0111111:
( in==4'b0001 )? 7'b0110000:
( in==4'b0010 )? 7'b1011011:
( in==4'b0011 )? 7'b1001111:
( in==4'b0100 )? 7'b1100110:
( in==4'b0101 )? 7'b110... | 7.676521 |
module sevenseg_mux (
input btn,
input conf,
input ch_mode,
input [15:0] num_1,
input [15:0] num_2,
input [15:0] num_3,
input [15:0] num_4,
input [15:0] num_5,
input [15:0] num_6,
input [15:0] num_7,
input [15:0] num_8,
output reg [15:0] num_out
);
reg [2:0] counter;
... | 6.648729 |
module SevenSeg_next_2 (
ds1_i1
, topLet_o
);
input [1:0] ds1_i1;
output [1:0] topLet_o;
wire [1:0] altLet_0;
assign altLet_0 = ds1_i1 + 2'd1;
reg [1:0] topLet_o_reg;
always @(*) begin
case (ds1_i1)
2'd3: topLet_o_reg = 2'd0;
default: topLet_o_reg = altLet_0;
endcase
end
ass... | 6.565592 |
module sevenseg_tb (
input wire clk,
input wire [7:0] sw,
output wire [3:0] an,
output wire [7:0] sseg
);
wire [3:0] a, b;
wire [7:0] sum;
sevenseg disp_unit (
.clk(clk),
.reset(1'b0),
.hex3(sum[7:4]),
.hex2(sum[3:0]),
.hex1(b),
.hex0(a),
.dp_in(4'b1011)... | 7.687591 |
module SevenSeg_testbench (
done
);
output [0:0] done;
wire [0:0] finished;
wire system1000;
wire system1000_rstn;
wire [127:0] outputs_i1;
wire [11:0] bodyVar_o;
assign done = finished;
// pragma translate_off
always @(*) begin
if (finished == 1'b1) begin
$finish;
end
end
// pr... | 7.027292 |
module_339898704941023827.v"
module sevenseg_top (
input TINY_CLK,
input [7:0] io_in, //using io_in[0] as clk, io_in[1] as reset
output [7:0] io_out
);
// XXX: All I really want is this: assign io_in[0] = TINY_CLK;
// But yosys errors out:
// Net 'TINY_CLK' is multiply driven by cell port TINY_CLK.O and top l... | 6.660572 |
module SevenSeg_topEntity (
input_0_0
, input_0_1
, input_0_2
, input_0_3
, // clock
system1000
, // asynchronous reset: active low
system1000_rstn
, output_0_0
, output_0_1
);
input [31:0] input_0_0;
input [31:0] input_0_1;
input [31:0] input_0_2;
input [31:0] input_0_... | 7.020184 |
module SevenSeg_topEntity_0 (
outputs_i1
, // clock
system1000
, // asynchronous reset: active low
system1000_rstn
, bodyVar_o
);
input [127:0] outputs_i1;
input system1000;
input system1000_rstn;
output [11:0] bodyVar_o;
wire [3:0] x_0;
wire signed [31:0] repANF_1;
wire signed [... | 7.020184 |
module sevenToOneMux (
SW,
LEDR
);
input [9:0] SW;
output [0:0] LEDR;
reg Out;
always @(*) begin
case (SW[9:7])
3'b000: Out = SW[0];
3'b001: Out = SW[1];
3'b010: Out = SW[2];
3'b011: Out = SW[3];
3'b100: Out = SW[4];
3'b101: Out = SW[5];
3'b110: Out =... | 7.317646 |
module seven_bit_adder (
clk,
ROT_A,
ROT_B,
num,
sum,
overflow
);
input clk, ROT_A, ROT_B;
input [3:0] num;
output [6:0] sum;
output overflow;
wire [6:0] sum;
wire overflow;
reg [6:0] a, b;
wire [6:0] cout;
reg op;
wire rotation_event;
reg prev_rotation_event = 1;
reg [2:... | 6.522898 |
module: seven_bit_adder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module seven_bit_adder_top;
// Inputs
reg pb1;
reg pb2;
reg pb3;
reg pb4;
reg [3:0] y;
// Outputs
wire [6:0... | 7.205256 |
module seven_bit_add_sub (
clk,
rot_a,
rot_b,
y,
sum,
overflow
);
input clk;
input rot_a;
input rot_b;
input [3:0] y;
output [6:0] sum;
output overflow;
wire [6:0] sum;
wire overflow;
reg [6:0] a;
reg [6:0] b;
reg op;
reg [2:0] cnt = 3'b0;
wire [6:0] carry0;
wire ro... | 6.522898 |
module seven_bit_register (
output reg [6:0] out,
input [6:0] in,
input clk
);
always @(posedge clk) out <= in;
endmodule
| 7.460129 |
module seven_display (
output reg [7:0] display,
input [3:0] num,
input enable
);
always @(*) begin
if (enable == 1'b1) begin
case (num)
4'b0000: display = 8'b11111100;
4'b0001: display = 8'b01100000;
4'b0010: display = 8'b11011010;
4'b0011: displ... | 7.02946 |
module seven_display (
in,
out
);
input [3:0] in;
output reg [6:0] out;
always @(*) begin
case (in) //͵ƽЧ
0: out <= 7'b0000001;
1: out <= 7'b1001111;
2: out <= 7'b0010010;
3: out <= 7'b0000110;
4: out <= 7'b1001100;
5: out <= 7'b0100100;
6: out <= 7'b0100000;... | 7.02946 |
module seven_dis_4 #(
parameter FREQ = 1000,
INPUT_WIDTH = 4,
OUTPUT_WIDTH = 7
) (
input clean,
input clk,
input [ 3:0] twinkle_select,
input [INPUT_WIDTH-1:0] num1,
input [INPUT_WIDTH-1:0] num2,
input [INPUT_WIDTH-1:0] num3,
input [... | 6.785187 |
module seven_light (
input clk,
input en,
output [7:0] led,
output [7:0] choose
);
//在屏幕上显示HELLO
reg [ 7:0] led;
reg [ 7:0] choose;
reg [26:0] counter = 0;
reg [ 2:0] temp = 0; //用于滚动展示，提高基本要求把这个注释掉就可以
//choose:AN7-AN0
//led:CA-CG+DP
always @(posedge clk, posedge en) begin
if (en)... | 7.002038 |
module Seven_Segment_Score(i,n);
parameter bit = 4;
parameter output_bit = 7;
input [bit-1:0]i;
output [output_bit-1:0]n;
reg [output_bit-1:0]n;
always @(*) begin
if(i == 4'b0000) n<= 7'b000_1000; //A
else if(i == 4'b0001) n <= 7'b001_0000; //9
else if(i == 4'b0010) n <= ... | 7.463488 |
module Seven_Segment_Decoders (
A,
Y
);
input [3:0] A;
output [6:0] Y;
always @(*) begin
case (A)
4'b0000: Y = 7'b1111110;
4'b0001: Y = 7'b0110000;
4'b0010: Y = 7'b1101101;
4'b0011: Y = 7'b1111001;
4'b0100: Y = 7'b0110011;
4'b0101: Y = 7'b1011011;
4'b0110: Y ... | 7.463488 |
module Seven_segment_digital_tube_choose (
clk,
rst,
low_min,
low_ten_sec,
low_sec,
low_one_tenth_sec
);
input clk, rst;
output reg low_min, low_ten_sec, low_sec, low_one_tenth_sec;
reg [14:0] clk_cnt;
reg clk_div;
reg [1:0] state;
localparam min = 2'b00;
localparam ten_sec = 2'... | 7.316611 |
module Seven_Segment_Display (
input wire clk,
input wire RST_N,
input wire [15:0] Displayed_number,
output reg [3:0] Cathode,
output wire [6:0] Segment_out
);
// For modification during simulation later
parameter startRefreshCounter = 14;
parameter endRefreshCounter = 15;
wire [ 1:0] LED_... | 7.463488 |
module stimulus(
// wire CLK,
// wire [2:0] LED_CONTROL_SIGNAL_REGISTER,
// wire LED_CHANGE_TICK,
// wire [7:0] DISPLAY_BITS
// );
//
// reg [3:0] LED1 = 4'd1;
// reg [3:0] LED2 = 4'd2;
// reg [3:0] LED3 = 4'd3;
//
// seven_segment_display_controller
// s(
// .clk(CLK),
// .display_bits(DISPLAY_BITS),
// .led1_... | 7.950957 |
module Seven_Segment_Display_Top (
input wire clk,
input wire RST_N,
output wire [3:0] Cathode,
output wire [6:0] Segment_out
);
// Signal to send number to Seven_Segment_Display module
wire [15:0] Displayed_number;
// For modification during simulation later
parameter startRefreshCounter = 14... | 7.463488 |
module Seven_Segment_Display_Top_tb ();
// Test signals
reg clk = 1'b0;
reg RST_N = 1'b1;
wire [3:0] Cathode;
wire [6:0] Segment_out;
// Instantiate the top module
Seven_Segment_Display_Top #(
// Change parameters for simulation purposes, to speed up changes
.time1(2),
.startRefreshCou... | 7.463488 |
module Seven_segment_LED_Display_Controller(
// input clk, // 100 Mhz clock source on Basys 3 FPGA
// input reset, // reset
// output reg [3:0] an, // anode signals of the 7-segment LED display
// output reg [6:0] seg// cathode patterns of the 7-segment LED display
// );
// // reg [26:0] one_seco... | 7.316611 |
module Seven_Segment_Output (
CLK,
TO_OUTPUT,
ACTIVE,
ENABLE
);
input CLK; //100MHz
input [31:0] TO_OUTPUT;
output reg [7:0] ACTIVE; //8个7段数码管是否被激活的控制信号
output [6:0] ENABLE; //A-G的通断控制
/*
该模块功能是将传入的8个4位8421BCD编码对应的十进制数字显示至七段数码管上
*/
wire [3:0] thousands_1 = TO_OUTPUT[31:28];
wire [3... | 7.463488 |
module Seven_Segment_Sound (
input display_clk, //refresh rate of 380Hz
input update_volume_clk,
output reg [3:0] an = 4'b0000,
output reg [7:0] seg = 8'b00000_000,
input [11:0] volume_raw,
input [3:0] volume_level_peak,
input [3:0] volume_level_raw,
input sw00,
sw11,
input [11:... | 7.463488 |
module seven_seg_6 (
input [23:0] data,
output [ 7:0] hex0,
output [ 7:0] hex1,
output [ 7:0] hex2,
output [ 7:0] hex3,
output [ 7:0] hex4,
output [ 7:0] hex5
);
seven_seg_digit dd0 (
.dig(data[4*0+:4]),
.hex(hex0)
);
seven_seg_digit dd1 (
.dig(data[4*1+:4]),
.... | 6.512779 |
module Seg_Anode (
input [2:0] select,
output reg [7:0] anode
);
always @(*) begin
case (select)
0: anode <= 8'b11111110;
1: anode <= 8'b11111101;
2: anode <= 8'b11111011;
3: anode <= 8'b11110111;
4: anode <= 8'b11101111;
5: anode <= 8'b11011111;
6: anode <= 8'b1... | 6.758808 |
module seven_seg_decoder (
Z,
Y,
X,
W,
A,
B,
C,
D,
E,
F,
G
);
input Z, Y, X, W;
output reg A, B, C, D, E, F, G;
always @(Z or Y or X or W) begin
case ({
Z, Y, X, W
})
//truth tabling
4'b0000: {A, B, C, D, E, F, G} = 7'b0000001;
4'b0001: ... | 7.554708 |
module seven_seg_decoder_tb ();
// Signal Decleration
reg [3:0] i_i;
wire [6:0] y_o;
reg [6:0] expected;
integer i;
// Instantiation
seven_seg_decoder dut (
.i_i(i_i),
.y_o(y_o)
);
// Logic to drive inputs and check outputs
initial begin
for (i = 0; i < 16; i = i + 1) begin
... | 7.554708 |
module seven_seg_Dev_IO (
input clk, // io_clk CPU
input rst,
input GPIOe0000000_we, // = 1 0
input [31:0] point_in, // 8 4
input [31:0] blink_in, // 8 4
input [2:0] Test, // SW[7:5]
input [31:0] disp_cpudata, // 0
input [31:0] Test_data1, // 1
input [31:0] Test_data... | 6.696936 |
module seven_seg_display #(
parameter DATA_WIDTH1 = 4,
parameter DATA_WIDTH2 = 8
) (
input [DATA_WIDTH1-1:0] i_hex_en,
output [DATA_WIDTH2-1:0] o_out
);
reg [DATA_WIDTH2-1:0] o_seven_seg;
assign o_out = o_seven_seg;
always @(*) begin
case (i_hex_en)
4'h0: o_seven_seg[DATA_WIDTH2-1:0]... | 6.903527 |
module seven_seg_display_driver #(
parameter CNTR_STEP = 1
) // For simulation
(
input clk, // Clock
input [15:0] disp_buf, // Display buffer
input [ 2:0] dp, // Which segment to show the decimal point, 0 for none.
input [ 3:0] lum, // Luminosity, disp... | 6.903527 |
module seven_seg_display_driver_0 (
clk,
disp_buf,
dp,
lum,
an_mux,
seg_mux,
dp_mux
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.000" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire [15 : 0] disp_buf;
i... | 6.903527 |
module seven_seg_display_driver_0 (
clk,
disp_buf,
dp,
lum,
an_mux,
seg_mux,
dp_mux
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.000" *) input clk;
input [15:0] disp_buf;
input [2:0] dp;
... | 6.903527 |
module seven_seg_display_encoder (
input [3:0] in,
output reg [6:0] out
);
// Case statements cause timing violations.
always @(in) begin
case (in)
4'h0 : out <= 7'h3F;
4'h1 : out <= 7'h06;
4'h2 : out <= 7'h5B;
4'h3 : out <= 7'h4F;
4'h4 : out <= 7'h66;
... | 6.903527 |
module Seven_Seg_Display_Out(
output reg[7:0] 7SegOut,
input clk,
input [3:0] dataIn
);
always @(clk)
begin
case (dataIn[3:0])
4'b0000 : 7SegOut <= 8'b11000000;
4'b0001 : 7SegOut <= 8'b11111001;
4'b0010 : 7SegOut <= 8'b10100100;
4'b0011 : 7SegOut <= 8'b10110000;
4'b0100 : 7SegOut <= 8'b10011001;
4'b0101 : 7... | 7.459859 |
module seven_seg_display_v1_0 #(
// Users to add parameters here
parameter integer C_NUM_DIGITS = 4,
parameter integer C_CLK_FREQ = 100000000,
parameter integer C_SCAN_FREQ = 1000,
parameter C_CATHODE_POLARITY = "ACTIVE_LOW",
parameter C_ANODE_POLARITY = "ACTIVE_LOW",
// User parameters ends... | 6.903527 |
module seven_seg_dot (
en,
in,
seg
);
input [3:0] in;
input en;
output [7:0] seg;
reg [7:0] seg;
always @(en or in) begin
if (!en) seg = 8'b11111111;
else
case (in)
4'd0: seg = 8'b01000000;
4'd1: seg = 8'b01111001;
4'd2: seg = 8'b00100100;
4'd3: seg =... | 6.764746 |
module seven_seg_manager (
input [6:0] N_sn,
N_eo,
output [6:0] L_1,
L_2,
L_3,
L_4
);
wire [3:0] decena_eo, unidad_eo, decena_sn, unidad_sn;
digit_separator(
N_eo, decena_eo, unidad_eo
); digit_separator(
N_sn, decena_sn, unidad_sn
); seven_seg_converter(
decena_eo, ... | 7.171677 |
module seven_seg_manager_4digit (
input clk,
input reset,
input [6:0] d7s_0,
d7s_1,
d7s_2,
d7s_3,
output reg [3:0] anodo,
output reg [6:0] segments
);
//Lo ideal sera hacer un modulo _delay_ms(cuantos ms dura el delay)
reg [2:0] selector = 2'd0;
wire clock;
clk_divider_7segment(... | 7.171677 |
module seven_seg_mgmt (
input clk,
input en, // enable
input [13:0] num, // quantity
output [ 3:0] s_an, // selector segments
output [ 6:0] s_seg // segments
);
reg [1:0] display;
wire [16:0] clock_divide_max = 17'b11110000100000000;
reg [16:0] clock_divide_counter;
... | 6.654726 |
module seven_seg_mgmt_test (
input clk,
input en, // enable
input [6:0] qty_1, // quantity 1
input [6:0] qty_2, // quantity 2
output [3:0] s_an, // selector segments
output [6:0] s_seg // segments
);
reg [1:0] display;
wire [16:0] clock_divide_max = 17'b11110000100... | 6.654726 |
module seven_seg_manager (
input clk,
//input [6:0] N_sn, N_eo,
input [6:0] d7s_0,
d7s_1,
d7s_2,
d7s_3,
output reg [6:0] segments,
output reg [3:0] anodo
//output reg[6:0]seg,
//output reg[3:0]an
);
//Lo ideal sera hacer un modulo _delay_ms(cuantos ms dura el delay)
//reg [3... | 7.171677 |
module seven_seg_perpherial (
data,
address,
read,
write,
reset,
clock,
HEX0,
HEX1,
HEX2,
HEX3
);
inout [63:0] data;
input [63:0] address;
input read;
input write;
input reset;
input clock;
output [6:0] HEX0, HEX1, HEX2, HEX3;
reg [63:0] reg_value;
wire load_w... | 6.622468 |
module seven_seg_tb ();
reg clk = 0;
always #1 clk = !clk;
reg reset_in = 1;
//Seven segments
wire [6:0] segments;
wire [3:0] seg_select;
wire seg_colon;
wire seg_dot;
reg [15:0] num;
wire reset, blink;
reflet_blink reset_bootstrap (
.clk(clk),
.out(blink)
);
assign reset = reset... | 7.349385 |
module Seven_Seg_Test (
SW,
LEDG,
HEX0,
HEX1,
HEX2,
HEX3
);
input [7:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3;
output [7:0] LEDG;
wire [6:0] seven_seg_hex0;
wire [6:0] seven_seg_hex1;
wire [6:0] ones_hex2;
wire [6:0] tens_hex3;
wire [3:0] ones;
wire [3:0] tens;
wire [3:0] ... | 7.383543 |
module seven_seg_testbench ();
reg clk = 0, rst_n = 1;
wire [ 7:0] seg_tube = 0, seg_enable = 0;
reg [31:0] display_value = 0;
seven_seg_unit seven_seg_unit (
.clk (clk),
.rst_n (rst_n), // note this is a clock for tube 1ms refresh
.display_value(display_value), // ... | 8.375049 |
module seven_seg_unit (
input clk_tube,
rst_n,
input tube_enable, // from hazard_unit (show the user input on tubes)
input [`DIGIT_CNT * `DIGIT_RADIX_WIDTH - 1:0] keypad_digits, // from input_unit (digits to be displayed during user input)
input switch_enable, // from input_unit (show binar... | 7.283422 |
module seven_seg_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add po... | 6.874691 |
module seven_seg_x8 (
output reg [6:0] segments,
output [7:0] digits,
input [39:0] signal_in,
input wire clk
);
wire clock_refresh;
wire [2:0] control;
wire [4:0] digit_0 = signal_in[4:0];
wire [4:0] digit_1 = signal_in[9:5];
wire [4:0] digit_2 = signal_in[14:10];
wire [4:0] digit_3 = signa... | 6.513297 |
module : seven_stage_bypass_unit
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
*... | 7.420328 |
module Seven_Segment(i,n);
parameter bit = 4;
parameter output_bit = 7;
input [bit-1:0]i;
output [output_bit-1:0]n;
reg [output_bit-1:0]n;
always @(*) begin
if(i == 4'b0000) n<= 7'b100_0000; //0
else if(i == 4'b0001) n <= 7'b111_1001; //1
else if(i == 4'b0010) n <= 7'b01... | 7.463488 |
module seven_tube_drive (
input wire clk,
input wire rst_n,
input wire [23:0] show_data,
output reg [7:0] seven_tube_seg,
output reg [5:0] seven_tube_sel
);
localparam T_1ms = 50_000;
parameter SCAN_FREQ = 200; //scan frequency
parameter CLK_FREQ = 50000000; //clock frequency
paramete... | 7.18324 |
module sevo_track (
input [11:0] cen_x,
input clk_pwm,
input rst,
input sw_en,
input clk_servo,
output wire PWM
);
//localparam define
localparam angle_0 = 24_000;
localparam angle_5 = 778;
localparam angle_90 = 75_000;
localparam angle_180 = 126_000;
reg [31:0] anglex;
reg [31:... | 6.729784 |
module sevo_v (
input [11:0] cen_y,
input clk_pwm,
input rst,
input sw_en,
input clk_servo,
output wire PWM
);
//localparam define
localparam angle_0 = 24_000;
localparam angle_5 = 778;
localparam angle_10 = 30_555;
localparam angle_20 = 36_111;
localparam angle_45 = 50_000;
local... | 7.651779 |
module SevSeg (
Count_out,
Num
);
input [3:0] Count_out;
output reg [6:0] Num;
always @(Count_out) begin
case (Count_out)
4'b0000: Num = 7'b1000000;
4'b0001: Num = 7'b1111001;
4'b0010: Num = 7'b0100100;
4'b0011: Num = 7'b0110000;
4'b0100: Num = 7'b0011001;
4'b0101: ... | 6.906381 |
module SevSegInterface (
input cpuClock,
input periphSelect,
input [15:0] dIn,
input [3:0] regSelect,
input readEn,
input writeEn,
input reset,
input exec,
output [15:0] dOut,
output [15:0] segsOut,
output [15:0] debugOut
);
// R0: Holds the 7-seg's value
SyzFETRegister3... | 7.133654 |
module sevSeg_button_counter (
input clock_50Mhz, // 50 Mhz clock source on Altera FPGA
input button,
input reset,
output reg [3:0] Anode_Activate, // anode signals of the 7-segment LED display
output reg [6:0] LED_SEG // cathode patterns of the 7-segme... | 7.611097 |
module sev_seg_decoder (
input [3:0] number,
output [6:0] digit
);
assign digit = ~( number == 4'h0 ? 7'b0111111:
number == 4'h1 ? 7'b0000110:
number == 4'h2 ? 7'b1011011:
number == 4'h3 ? 7'b1001111:
number == 4'h4 ? 7'b1100110:
number == 4'h5 ? 7'b1101101:
numbe... | 6.970599 |
module sev_seg_disp (
input [31:0] ALUoutput,
output [ 6:0] D1,
output [ 6:0] D2,
output [ 6:0] D3,
output [ 6:0] D4
);
function [6:0] conv_to_seg(input [3:0] Digit);
case (Digit)
4'b0000: conv_to_seg = 7'h7E;
4'b0001: conv_to_seg = 7'h30;
4'b0010: conv_to_seg = 7'h6D;
... | 8.109747 |
module sev_seg_disp_test_ds (
//input [31:0] ALUoutput,
output [6:0] D1,
output D2BB0,
output D2BB1,
output D2BB2,
output D2BB3,
output D2BB4,
output D2BB5,
output D2BB6,
output D3BB0,
output D3BB1,
output D3BB2,
output D3BB3,
output D3BB4,
output D3BB5,
... | 7.844999 |
module sext (
input [ 2:0] sext_op, //ѡ͵ָķչ
input [31:0] inst, //ָ
output reg [31:0] ext //չ֮32λ
);
always @(*) begin
if (inst[31] == 'b0)
case (sext_op)
`I: begin
if (inst[14:12] == 'b001 || inst[14:12] == 'b101) ext = {27'b0, inst[24:20]};
else... | 7.258095 |
module SEXT16 (
in,
out,
en
);
input [7:0] in;
input en;
output [15:0] out;
wire [15:0] sext_out;
mux #(
.INPUTS(2),
.WIDTH (16)
) sext16_mux (
.in({{8'hff, in}, {8'h00, in}}),
.out(sext_out),
.select(in[7])
);
mux #(
.INPUTS(2),
.WIDTH (16)
) sex... | 7.8053 |
module SEXT32 (
in,
out,
en
);
input [7:0] in;
input en;
output [31:0] out;
wire [31:0] sext_out;
mux #(
.INPUTS(2),
.WIDTH (32)
) sext32_mux (
.in({{24'hffffff, in}, {24'h000000, in}}),
.out(sext_out),
.select(in[7])
);
mux #(
.INPUTS(2),
.WIDTH (3... | 8.572109 |
module SextImm (
input wire [24:0] din, // irom.inst[31:7]
input wire [ 2:0] op, // cu.sext_op
output wire [31:0] ext // SEXT.ext
);
assign ext = sext(din, op); // sext imm for i/b/j/s/u
function [31:0] sext(input [24:0] din, input [2:0] op);
begin
case (op)
3'd0: sext = {{... | 8.696522 |
module sextium_avalon_io #(
parameter READ_FIFO_ADDR = 32'h21000,
parameter WRITE_FIFO_ADDR = 32'h22000,
parameter IO_ADDR_OFFSET = 32'h20000
) (
input clk,
input reset,
output [31:0] address,
output read,
input [31:0] readdata,
input waitrequest,
output write,
output [31:... | 8.489996 |
module sextium_avalon_mem (
input clk,
input reset,
output [31:0] address,
output read,
input [15:0] readdata,
input waitrequest,
output write,
output [15:0] writedata,
input [15:0] addr_bus,
output mem_ack,
output [15:0] mem_bus_in,
input [15:0] mem_bus_out,
input ... | 8.489996 |
module sextium_core (
input clock,
input reset,
input ioack,
input mem_ack,
input frame_ack,
input [15:0] io_bus_in,
input [15:0] mem_bus_in,
input [15:0] frame_bus_in,
output [15:0] io_bus_out,
output [15:0] mem_bus_out,
output [15:0] frame_bus_out,
output [15:0] addr_bu... | 6.866968 |
module sextium_ram (
address_a,
address_b,
byteena_b,
clock_a,
clock_b,
data_a,
data_b,
enable_b,
wren_a,
wren_b,
q_a,
q_b);
input [15:0] address_a;
input [15:0] address_b;
input [1:0] byteena_b;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15:0] data_b;
input enable_b;
inp... | 7.276904 |
module sextium_ram_avalon (
input [15:0] address,
input [1:0] byteenable,
input chipselect,
input clk,
input clken,
input reset,
input reset_req,
input write,
input [15:0] writedata,
output [15:0] readdata,
output [15:0] mem_address,
output [1:0] mem_byteena,
output ... | 6.596397 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.