code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sg_list_reader_32 #(
parameter C_DATA_WIDTH = 9'd32
) (
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output V... | 7.774419 |
module sg_list_reader_64 #(
parameter C_DATA_WIDTH = 9'd64
) (
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output V... | 7.774419 |
module ch (
x,
y,
z,
o
);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
| 6.926372 |
module maj (
x,
y,
z,
o
);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
| 6.723817 |
module sha1_post_stage (
input clk,
input [31:0] a_in, // 32 bit A[i]
input [31:0] b_in, // 32 bit B[i]
input [31:0] c_in, // 32 bit C[i]
input [31:0] d_in, // 32 bit D[i]
input [31:0] p_in, // 32 bit P[i] (input from "current" stage)
output [31:0] a_out, // 32 bit A[i] (outputs to n... | 6.914788 |
module sha1_pre_stage (
input clk,
input [31:0] d_in, // 32 bit D[i-1]
input [511:0] msg_in, // 512 bit msg
output [511:0] msg_out, //
output [31:0] p_out // 32 bit P[i] (replaces E[i])
);
// Parameters to instance the stage
parameter stagen = 0; // This is our "i"
// Calculate k_i
... | 6.871485 |
module sha1_collision_top (
input CLK_100MHZ
);
// Clock Generator
wire hash_clk;
main_pll clk_blk (
.CLK_IN1 (CLK_100MHZ),
.CLK_OUT1(hash_clk)
);
// SHA1 Hashers
wire [511:0] expanded_message0, expanded_message1;
wire [159:0] hash0, hash1;
sha1 hasher0 (
.clk(hash_clk),
... | 6.916562 |
module expand_message (
input clk,
input [14*4-1:0] rx_fixed_data,
input [59:0] rx_nonce,
output reg [511:0] tx_expanded_message
);
always @(posedge clk) begin
tx_expanded_message <= {
32'd192,
32'h0,
224'h0,
32'h80000000,
rx_fixed_data[`IDX(2)],
rx_fixed_data[... | 6.690297 |
module sha1_pipeline (
input clk,
input [511:0] msg_in, // 512 bit msg
input [31:0] a_in, // 32 bit A[0] // This is the initial state for the hasher machinery
input [31:0] b_in, // 32 bit B[0]
input [31:0] c_in, // 32 bit C[0]
input [31:0] d_in, // 32 bit D[0]
input [31:0] e_in, // 3... | 6.61978 |
module sha1_top #(
parameter BITS = 32
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input ... | 8.661132 |
module sha2_round #(
parameter WORDSIZE = 0
) (
input [WORDSIZE-1:0] Kj,
Wj,
input [WORDSIZE-1:0] a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
g_in,
h_in,
input [WORDSIZE-1:0] Ch_e_f_g,
Maj_a_b_c,
S0_a,
S1_e,
output [WORDSIZE-1:0] a_out,
b_out,
c_out,
... | 6.860815 |
module Ch #(
parameter WORDSIZE = 0
) (
input wire [WORDSIZE-1:0] x,
y,
z,
output wire [WORDSIZE-1:0] Ch
);
assign Ch = ((x & y) ^ (~x & z));
endmodule
| 8.588834 |
module Maj #(
parameter WORDSIZE = 0
) (
input wire [WORDSIZE-1:0] x,
y,
z,
output wire [WORDSIZE-1:0] Maj
);
assign Maj = (x & y) ^ (x & z) ^ (y & z);
endmodule
| 8.345258 |
module sha256block (
input CLK,
input external_input_en, // select external input
input ctx_save_en, // select save into memory from context
//input save_en,
input [31:0] in,
// memory ops
input mem_wr_en,
input mem_rd_en0,
mem_rd_en1,
input [6:0] wr_addr,
rd_addr0,
r... | 7.071684 |
module sha256core #(
parameter ID = -1
) (
input CLK,
// Synchronization of several cores
input start, // asserts on cycle 0 of each sequence
output reg ready = 1, // input buffer is ready for data
input wr_en,
input [31:0] in,
input [3:0] wr_addr,
input [`BLK_OP_MSB:0] input_blk_... | 7.489564 |
module sha256core_dummy (
input CLK,
// Synchronization of several cores
input start, // asserts on cycle 0 of each sequence
output ready, // input buffer is ready for data
input wr_en,
input [31:0] in,
input [3:0] wr_addr,
input [`BLK_OP_MSB:0] input_blk_op, // registered on set_i... | 6.960795 |
module sha256ctx (
input CLK,
input S1_CH_I_rst,
S1_CH_I_en,
input S0_en,
MAJ_en,
block2ctx_en,
//input D2E_en, // enable D2->E pass-by
input en,
input [31:0] block2ctx, // loading context from mem1
input [31:0] Wt,
Kt,
input output_en,
output reg [31:0] o
//o... | 6.662847 |
module sha256ctx (
input CLK,
input S1_CH_rst,
S0_rst,
MAJ_rst,
input D2E_en,
input block2ctx_en,
T1_rst,
input [31:0] block2ctx,
input [31:0] Wt,
Kt,
output [31:0] o
);
endmodule
| 6.662847 |
module sha256_cu_tld (
CLOCK_50,
KEY,
UART_RXD,
UART_TXD,
LEDR,
LEDG
);
// I/O
input CLOCK_50, UART_RXD;
input [3:0] KEY;
output UART_TXD;
output [17:0] LEDR;
output [8:0] LEDG;
// Instantiate control module
sha256_cu(
CLOCK_50, KEY[3], UART_RXD, UART_TXD, LEDR[0], LEDG[0]... | 6.829188 |
module SHA256_e0 (
x,
y
);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0], x[31:2]} ^ {x[12:0], x[31:13]} ^ {x[21:0], x[31:22]};
endmodule
| 6.682746 |
module SHA256_e1 (
x,
y
);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0], x[31:6]} ^ {x[10:0], x[31:11]} ^ {x[24:0], x[31:25]};
endmodule
| 6.739211 |
module SHA256_ch (
x,
y,
z,
o
);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
| 6.961882 |
module SHA256_maj (
x,
y,
z,
o
);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
| 6.8912 |
module maj (
i_x,
i_y,
i_z,
o_res
);
input [31:0] i_x, i_y, i_z;
output [31:0] o_res;
assign o_res = (i_x & i_y) | (i_z & (i_x | i_y));
endmodule
| 7.085004 |
module sum0 (
i_x,
o_res
);
input [31:0] i_x;
output [31:0] o_res;
assign o_res = {i_x[1:0], i_x[31:2]} ^ {i_x[12:0], i_x[31:13]} ^ {i_x[21:0], i_x[31:22]};
endmodule
| 6.977569 |
module sigm0 (
i_x,
o_res
);
input [31:0] i_x;
output [31:0] o_res;
assign o_res[31:29] = i_x[6:4] ^ i_x[17:15];
assign o_res[28:0] = {i_x[3:0], i_x[31:7]} ^ {i_x[14:0], i_x[31:18]} ^ i_x[31:3];
endmodule
| 6.758617 |
module sha256_w_mem_for_pipeline_0to62 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [511:0] block_in,
output wire [511:0] block_out
);
wire [511:0] block_out_wire;
mem_save_block mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_out_... | 6.857997 |
module sha256_w_mem_for_pipeline_16_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [127:0] block_in,
output wire [127:0] block_out
);
wire [127:0] block_out_wire;
mem_save_block_128 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_16_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [255:0] block_in,
output wire [255:0] block_out
);
wire [255:0] block_out_wire;
mem_save_block_256 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_17_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [127:0] block_in,
output wire [127:0] block_out
);
wire [127:0] block_out_wire;
mem_save_block_128 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_17_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [255:0] block_in,
output wire [255:0] block_out
);
wire [255:0] block_out_wire;
mem_save_block_256 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_18to21_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [255:0] block_in,
output wire [255:0] block_out
);
wire [255:0] block_out_wire;
mem_save_block_256 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(blo... | 6.857997 |
module sha256_w_mem_for_pipeline_18_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [127:0] block_in,
output wire [127:0] block_out
);
wire [127:0] block_out_wire;
mem_save_block_128 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_19_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [127:0] block_in,
output wire [127:0] block_out
);
wire [127:0] block_out_wire;
mem_save_block_128 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_1to59 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [511:0] block_in,
output wire [511:0] block_out
);
wire [511:0] block_out_wire;
mem_save_block mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_out_... | 6.857997 |
module sha256_w_mem_for_pipeline_20_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [127:0] block_in,
output wire [159:0] block_out
);
wire [159:0] block_out_wire;
mem_save_block_160 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_21_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [159:0] block_in,
output wire [191:0] block_out
);
wire [191:0] block_out_wire;
mem_save_block_192 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_22_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [191:0] block_in,
output wire [223:0] block_out
);
wire [223:0] block_out_wire;
mem_save_block_224 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_22_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [255:0] block_in,
output wire [255:0] block_out
);
wire [255:0] block_out_wire;
mem_save_block_256 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_23_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [223:0] block_in,
output wire [255:0] block_out
);
wire [255:0] block_out_wire;
mem_save_block_256 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_23_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [255:0] block_in,
output wire [255:0] block_out
);
wire [255:0] block_out_wire;
mem_save_block_256 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_24_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [255:0] block_in,
output wire [287:0] block_out
);
wire [287:0] block_out_wire;
mem_save_block_288 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_24_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [255:0] block_in,
output wire [287:0] block_out
);
wire [287:0] block_out_wire;
mem_save_block_288 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_25_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [287:0] block_in,
output wire [319:0] block_out
);
wire [319:0] block_out_wire;
mem_save_block_320 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_25_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [287:0] block_in,
output wire [319:0] block_out
);
wire [319:0] block_out_wire;
mem_save_block_320 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_26_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [319:0] block_in,
output wire [351:0] block_out
);
wire [351:0] block_out_wire;
mem_save_block_352 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_26_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [319:0] block_in,
output wire [351:0] block_out
);
wire [351:0] block_out_wire;
mem_save_block_352 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_27_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [351:0] block_in,
output wire [383:0] block_out
);
wire [383:0] block_out_wire;
mem_save_block_384 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_27_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [351:0] block_in,
output wire [383:0] block_out
);
wire [383:0] block_out_wire;
mem_save_block_384 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_28_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [383:0] block_in,
output wire [415:0] block_out
);
wire [415:0] block_out_wire;
mem_save_block_416 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_28_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [383:0] block_in,
output wire [415:0] block_out
);
wire [415:0] block_out_wire;
mem_save_block_416 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_29_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [415:0] block_in,
output wire [447:0] block_out
);
wire [447:0] block_out_wire;
mem_save_block_448 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_29_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [415:0] block_in,
output wire [447:0] block_out
);
wire [447:0] block_out_wire;
mem_save_block_448 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_30_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [447:0] block_in,
output wire [479:0] block_out
);
wire [479:0] block_out_wire;
mem_save_block_480 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_30_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [447:0] block_in,
output wire [479:0] block_out
);
wire [479:0] block_out_wire;
mem_save_block_480 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_31_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [479:0] block_in,
output wire [511:0] block_out
);
wire [511:0] block_out_wire;
mem_save_block_512 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_31_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [479:0] block_in,
output wire [511:0] block_out
);
wire [511:0] block_out_wire;
mem_save_block_512 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_32to53_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [511:0] block_in,
output wire [511:0] block_out
);
wire [511:0] block_out_wire;
mem_save_block_512 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(blo... | 6.857997 |
module sha256_w_mem_for_pipeline_32to56_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [511:0] block_in,
output wire [511:0] block_out
);
wire [511:0] block_out_wire;
mem_save_block_512 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(blo... | 6.857997 |
module sha256_w_mem_for_pipeline_54_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [511:0] block_in,
output wire [479:0] block_out
);
wire [479:0] block_out_wire;
mem_save_block_480 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_55_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [479:0] block_in,
output wire [415:0] block_out
);
wire [415:0] block_out_wire;
mem_save_block_416 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_56_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [415:0] block_in,
output wire [351:0] block_out
);
wire [351:0] block_out_wire;
mem_save_block_352 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_57_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [511:0] block_in,
output wire [479:0] block_out
);
wire [479:0] block_out_wire;
mem_save_block_480 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_57_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [351:0] block_in,
output wire [287:0] block_out
);
wire [287:0] block_out_wire;
mem_save_block_288 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_58_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [479:0] block_in,
output wire [415:0] block_out
);
wire [415:0] block_out_wire;
mem_save_block_416 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_58_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [287:0] block_in,
output wire [223:0] block_out
);
wire [223:0] block_out_wire;
mem_save_block_224 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_59_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [415:0] block_in,
output wire [351:0] block_out
);
wire [351:0] block_out_wire;
mem_save_block_352 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_59_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [223:0] block_in,
output wire [159:0] block_out
);
wire [159:0] block_out_wire;
mem_save_block_160 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_60 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [511:0] block_in,
output wire [31:0] block_out
);
wire [31:0] block_out_wire;
reg [31:0] block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
... | 6.857997 |
module sha256_w_mem_for_pipeline_60_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [351:0] block_in,
output wire [287:0] block_out
);
wire [287:0] block_out_wire;
mem_save_block_288 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_60_3 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [159:0] block_in,
output wire [31:0] block_out
);
wire [31:0] block_out_wire;
reg [31:0] block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin... | 6.857997 |
module sha256_w_mem_for_pipeline_61_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [287:0] block_in,
output wire [223:0] block_out
);
wire [223:0] block_out_wire;
mem_save_block_224 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_62_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [223:0] block_in,
output wire [159:0] block_out
);
wire [159:0] block_out_wire;
mem_save_block_160 mem_b (
.CLK(CLK),
.RST(RST),
.write_en(write_en),
.block_in(block_o... | 6.857997 |
module sha256_w_mem_for_pipeline_63 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [511:0] block_in,
output wire [31:0] block_out
);
wire [31:0] block_out_wire;
reg [31:0] block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
... | 6.857997 |
module sha256_w_mem_for_pipeline_63_2 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [159:0] block_in,
output wire [31:0] block_out
);
wire [31:0] block_out_wire;
reg [31:0] block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin... | 6.857997 |
module sha256_K_machine (
input clk,
input rst,
output [31:0] K
);
reg [2047:0] rom_q;
wire [2047:0] rom_d = {rom_q[2015:0], rom_q[2047:2016]};
assign K = rom_q[2047:2016];
always @(posedge clk) begin
if (rst) begin
rom_q <= {
32'h428a2f98,
32'h71374491,
32'hb5c0... | 6.997893 |
module sha256_spi (
input i_clk,
input i_sck,
input i_rst_n,
input i_ss_n,
input i_spi_mosi,
output o_spi_miso,
output o_irq_done
);
wire [6:0] mosi_addr_7b;
wire [7:0] mem_out, mosi_data_8b;
wire [15:0] rx_frame, tx_frame;
wire we_edge, n_read_write, spi_rx_complete;
reg [2... | 6.975514 |
module Ch (
input wire [32-1:0] x,
y,
z,
output wire [32-1:0] Ch
);
assign Ch = ((x & y) ^ (~x & z));
endmodule
| 7.204832 |
module Maj (
input wire [32-1:0] x,
y,
z,
output wire [32-1:0] Maj
);
assign Maj = (x & y) ^ (x & z) ^ (y & z);
endmodule
| 7.385225 |
module sha256_K (
input clk,
input rst_n,
input input_valid,
output [31:0] K
);
reg [2047:0] rom_q;
wire [2047:0] rom_d;
reg [ 31:0] K_p;
assign rom_d = {rom_q[2015:0], 32'b0};
assign K = K_p;
wire [2047:0] rom;
assign rom = {
32'h428a2f98,
32'h71374491,
32'hb5c0fbcf,
32... | 7.4634 |
module Sha256_topEntity ( // Inputs
input clk // clock
, input rst // asynchronous reset: active high
, input [31:0] a_0_0
, input [31:0] a_0_1
, input [31:0] a_0_2
, input [31:0] a_0_3
, input [31:0] a_0_4
, input [31:0] a_0_5
, input [31:0] a_0_6
, input [31:0] a_0_7
, i... | 6.646611 |
module sha2_controller_tb;
reg rst = 0;
reg clk = 0;
wire [7:0] led;
wire line;
wire TX;
// UART signal generator
behavioral_UART_tx tx_model (.line(line));
// Unit Under Test
sha2_controller UUT (
.clk(clk),
.btn_north(rst),
.RX(line),
.TX(TX),
... | 7.531537 |
module sha2_pipelined #(
parameter N = 32
) //size word
(
input clk,
input [511:0] message,
input strobe,
output [255:0] hash_out,
output valid
);
//count rounds
reg [6:0] cnt_round;
//initialization hash values
wire [255:0] H_0 = {
32'h6A09E667,
32'hBB67AE85,
32'h3C6EF372... | 7.313888 |
module round_recount #(
parameter N = 32
) (
input [N-1:0] Kj,
Wj,
input [N-1:0] a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
g_in,
h_in,
input [N-1:0] Ch_e_f_g,
Ma_a_b_c,
S0_a,
S1_e,
output [N-1:0] a_out,
b_out,
c_out,
d_out,
e_out,
f_out,
... | 6.795313 |
module Ch #(
parameter N = 0
) (
input wire [N-1:0] x,
y,
z,
output wire [N-1:0] Ch
);
assign Ch = ((x & y) ^ (~x & z));
endmodule
| 8.588834 |
module Ma #(
parameter N = 0
) (
input wire [N-1:0] x,
y,
z,
output wire [N-1:0] Ma
);
assign Ma = (x & y) ^ (x & z) ^ (y & z);
endmodule
| 8.458284 |
module calculate_Wj #(
parameter N = 32
) (
input clk,
input [N*16-1:0] M,
input M_valid,
input [N-1:0] s1_Wtm2,
input [N-1:0] s0_Wtm15,
output [N-1:0] W_shift2,
output [N-1:0] W_shift15,
output [N-1:0] W
);
reg [N*16-1:0] W_register;
//calculate W_shift values
assign W_shift2 ... | 7.577041 |
module xor_unit (
a,
b,
xor_o
);
input [1599:0] a;
input [1599:0] b;
output [1599:0] xor_o;
assign xor_o = a ^ b;
endmodule
| 6.560956 |
module SHA3_TOP (
input ICLK,
input IRST,
input [63:0] IDATA,
input IREADY,
input ILAST,
input [2:0] IBYTE_NUM,
output OBUFFER_FULL,
output [511:0] ODATA,
output OREADY
);
keccak uut (
.iClk (ICLK),
.iRst (IRST),
.iData (IDATA),
.iReady (IREADY),
... | 7.168578 |
module SHA3_TOP_wrapper (
input clk,
input reset,
input [63:0] in,
input in_ready,
input is_last,
input [2:0] byte_num,
output buffer_full,
output [511:0] out,
output out_ready
);
SHA3_TOP U1_TOP (
.ICLK (clk),
.IRST (reset),
.IDATA (in),
.IREADY (i... | 7.320243 |
module sha3_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 10
) (
// Users to add ports ... | 6.661168 |
module sha3_wrapper (
input wire clk,
input wire rst_n,
input wire cs,
input wire we,
input wire [ 7:0] address,
input wire [31:0] write_data,
output wire [31:0] read_data
);
//
// Address Decoder
//
localparam ADDR_MSB_REGS = 1'b0;
localparam ADDR_MSB_CORE = 1'b1;
wire [ ... | 7.079688 |
module sha512_h_constants (
input wire [1 : 0] mode,
output wire [63 : 0] H0,
output wire [63 : 0] H1,
output wire [63 : 0] H2,
output wire [63 : 0] H3,
output wire [63 : 0] H4,
output wire [63 : 0] H5,
output wire [63 : 0] H6,
output wire [63 : 0] H7
);
//-----------------------... | 7.124757 |
module sha512_h_constants (
input wire [1 : 0] mode,
output wire [63 : 0] H0,
output wire [63 : 0] H1,
output wire [63 : 0] H2,
output wire [63 : 0] H3,
output wire [63 : 0] H4,
output wire [63 : 0] H5,
output wire [63 : 0] H6,
output wire [63 : 0] H7
);
//-----------------------... | 7.124757 |
module shader (
input clk,
input rst_n,
input [(32*5-1):0] values,
output reg [ 31:0] rows
);
reg [4:0] n;
always @(posedge clk) begin
if (!rst_n) n = 0;
// icarus verilog doesn't implement the generate statement.
`define pulse(i) rows[i] ... | 6.569347 |
module : shadow_board
// top module : connect6
// author : vipin k
// description : Local copy of the playing board
// revision :
// 17-8-2011 : Initial draft
//--------------------------------------------------------------------------------------------
`define empty_cell 2... | 6.523301 |
module: shadow_capture
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module shadow_capture_routing_tb;
// Inputs
reg clk;
reg rst;
reg capture_en;
reg [1180:0] din;
reg [5:0] dump_... | 6.615685 |
module: shadow_capture
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module shadow_capture_tb;
localparam DFF_BITS = 17;
localparam CHAINS_IN = 3;
localparam CHAINS_OUT = 3;
localpara... | 6.615685 |
module: shadow_capture
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module shadow_capture_v1_2_tb;
localparam DFF_BITS = 17;
localparam DISCRETE_DFFS = 3;
localparam CHAINS_IN = 3;
l... | 6.615685 |
module shadow_chain (
input clk, // System clock
input rst, // System reset
input c_en, // Capture enable
input d_en, // Data dump enable
input d_clk, // Data Clock
input [SIZE-1:0] d_in, // Data in
output reg d_out, // Data out
output reg d_ready, // Data ready
ou... | 7.459211 |
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