code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sextium_ram (
address_a,
address_b,
byteena_b,
clock_a,
clock_b,
data_a,
data_b,
enable_b,
wren_a,
wren_b,
q_a,
q_b
);
input [15:0] address_a;
input [15:0] address_b;
input [1:0] byteena_b;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15... | 7.276904 |
module sextium_ram_controller (
input clock,
input reset,
input [15:0] addr_bus,
output [15:0] mem_bus_in,
input [15:0] mem_bus_out,
input mem_read,
input mem_write,
output reg mem_ack,
input clock_b,
input [15:0] address_b,
input [15:0] data_b,
output [15:0] q_b,
inp... | 7.489286 |
module SEXT_10_0 (
input [10:0] d,
output [15:0] out
);
assign out = {{5{d[10]}}, d};
endmodule
| 6.621959 |
module SEXT_8_0 (
input [ 8:0] d,
output [15:0] out
);
assign out = {{7{d[8]}}, d};
endmodule
| 7.111458 |
module SEXT_5_0 (
input [ 5:0] d,
output [15:0] out
);
assign out = {{10{d[5]}}, d};
endmodule
| 6.762864 |
module SEXT_4_0 (
input [ 4:0] d,
output [15:0] out
);
assign out = {{11{d[4]}}, d};
endmodule
| 6.672455 |
module se_handler (
instr,
se_5,
se_8,
ze_8,
ze_5,
se_11
);
// SIGN EXTENSION HANDLER MODULE
input [15:0] instr;
output [15:0] se_5;
output [15:0] se_8;
output [15:0] ze_8;
output [15:0] ze_5;
output [15:0] se_11;
// sign extend handling
assign se_5 = {{11{instr[4]}}, instr[4... | 7.443327 |
module FU (
input [63:0] io_A,
input [63:0] io_B,
input [63:0] io_cond,
input [ 2:0] io_fu_op,
input [ 1:0] io_fu_type,
input io_signed,
output [63:0] io_out
);
wire _T_1 = io_fu_type == 2'h0; // @[FU.scala 46:21]
wire [126:0] _GEN_15 = {{63'd0}, io_A}; // @[FU.scala 48:22... | 8.210275 |
module SEOperation (
input [ 7:0] io_inst,
input [63:0] io_op1_input,
input [63:0] io_op2_input,
input [63:0] io_cond_input,
output [63:0] io_result
);
wire [7:0] decode_io_inst_in; // @[SEOperation.scala 31:28]
wire [2:0] decode_io_fu_op; // @[SEOperation.scala 31:28]
wire [1:0] decode_... | 6.8068 |
module AddRoundKey (
input [7:0] io_state_in_0,
input [7:0] io_state_in_1,
input [7:0] io_state_in_2,
input [7:0] io_state_in_3,
input [7:0] io_state_in_4,
input [7:0] io_state_in_5,
input [7:0] io_state_in_6,
input [7:0] io_state_in_7,
input [7:0] io_state_in_8,
input ... | 7.103156 |
module InvShiftRows (
input [7:0] io_state_in_0,
input [7:0] io_state_in_1,
input [7:0] io_state_in_2,
input [7:0] io_state_in_3,
input [7:0] io_state_in_4,
input [7:0] io_state_in_5,
input [7:0] io_state_in_6,
input [7:0] io_state_in_7,
input [7:0] io_state_in_8,
input ... | 7.074198 |
module ShiftRows (
input [7:0] io_state_in_0,
input [7:0] io_state_in_1,
input [7:0] io_state_in_2,
input [7:0] io_state_in_3,
input [7:0] io_state_in_4,
input [7:0] io_state_in_5,
input [7:0] io_state_in_6,
input [7:0] io_state_in_7,
input [7:0] io_state_in_8,
input [7... | 7.114324 |
module sfifo16 (
clock_i,
reset_ni,
read_i,
write_i,
data_i,
data_o,
empty_no,
full_no
);
// Default width of 16-bits, but is user specifiable.
parameter WIDTH = 16;
parameter MSB = WIDTH - 1;
input clock_i;
input reset_ni;
input read_i;
input write_i;
input [MSB:0] ... | 8.500408 |
module sfifo32 (
clock_i,
reset_i,
read_i, // Read so advance to next item
write_i, // Write input data into FIFO
data_i,
data_o,
empty_no,
full_o
);
// Default width of 16-bits, but is user specifiable.
parameter WIDTH = 8'd16;
input clock_i;
input reset_i;
input read_i... | 8.031579 |
module sfifothresh (
i_clk,
i_reset,
i_wr,
i_data,
o_full,
o_fill,
i_rd,
o_data,
o_empty,
i_threshold,
o_int
);
parameter BW = 8; // Byte/data width
parameter LGFLEN = 4;
parameter [0:0] OPT_ASYNC_READ = 1'b1;
localparam FLEN = (1 << LGFLEN);
//
//
input wire ... | 7.580135 |
module iob_sync_assim_fifo #(
parameter W_DATA_W = 8,
parameter W_ADDR_W = 7,
parameter R_ADDR_W = 6,
parameter R_DATA_W = 16
) (
input rst,
input clk,
output reg [31:0] fifo_ocupancy,
//read port
output [R_DATA_W-1:0] data_out,
output empty,
input ... | 9.325195 |
module sfifo_assim_tb;
//Inputs
reg clk;
reg reset;
reg [`W_DATA-1:0] data_in;
reg read;
reg write;
//Ouptuts
wire [`R_DATA-1:0] data_out;
wire empty_out;
wire full_out;
wire [31:0] fifo_occupancy;
integer i;
parameter clk_per = 10; // clk period = 10 timeticks
// Instantiate the Unit ... | 7.68169 |
module sfifo_tb;
//Inputs
reg clk;
reg reset;
reg [`DATA_W-1:0] data_in;
reg read;
reg write;
//Outputs
wire [`DATA_W-1:0] data_out;
wire empty_out;
wire full_out;
reg [31:0] fifo_occupancy;
integer i;
parameter clk_per = 10; // clk period = 10 timeticks
initial begin
// optional ... | 7.556711 |
module sfif_ctrl (
clk_125,
rstn,
rprst,
enable,
run,
ipg_cnt,
tx_cycles,
loop,
tx_empty,
tx_rdy,
tx_val,
tx_end,
credit_available,
tx_cr_read,
tx_d_read,
done,
sm
);
input clk_125;
input rstn;
input enable;
input run;
input [15:0] ipg_cnt;... | 7.399595 |
module sfif_rx_fifo (
wb_clk,
clk_125,
rstn,
timestamp,
rx32_data,
rden,
empty,
rx64_st,
rx64_end,
rx64_dwen,
rx64_data,
rx64_filter
);
input wb_clk;
input clk_125;
input rstn;
input [31:0] timestamp;
input rden;
output [31:0] rx32_data;
output empty;
i... | 7.459542 |
module sflash (
input wire clk,
input wire arstn, // async reset
// Flash Memory interface to spif
output reg ready, // Ready for next byte to send
input wire wr, // Flash transmit strobe
input wire [7:0] din, // Flash transmit data
input wi... | 8.039619 |
module sfp (
out,
in,
acc,
relu,
clk,
reset
);
parameter bw = 4;
parameter psum_bw = 16;
input clk;
input acc;
input relu;
input reset;
input signed [psum_bw-1:0] in;
output signed [psum_bw-1:0] out;
reg signed [psum_bw-1:0] psum_q;
always @(posedge clk) begin
if (res... | 6.743657 |
module sfp2gmii (
gmii_rx_d,
gmii_rx_dv,
gmii_rx_err,
tx_clk,
rx_clk,
readdata,
waitrequest,
txp,
reconfig_fromgxb,
led_an,
led_disp_err,
led_char_err,
led_link,
gmii_tx_d,
gmii_tx_en,
gmii_tx_err,
reset_tx_clk,
reset_rx_clk,
address,
read,... | 6.629102 |
module sfp2gmii (
gmii_rx_d,
gmii_rx_dv,
gmii_rx_err,
tx_clk,
rx_clk,
readdata,
waitrequest,
txp,
reconfig_fromgxb,
led_an,
led_disp_err,
led_char_err,
led_link,
gmii_tx_d,
gmii_tx_en,
gmii_tx_err,
reset_tx_clk,
reset_rx_clk,
address,
read,... | 6.629102 |
module sfr_mem (
clk,
addr,
data_in,
data_out,
wr_n,
rd_n
);
input clk;
input [7:0] addr;
input [7:0] data_out;
output [7:0] data_in;
input wr_n;
input rd_n;
reg [7:0] mem[255:0];
integer i;
initial begin
for (i = 0; i <= 255; i = i + 1) mem[i] = 0;
end
//ass... | 6.799651 |
module SFR_WR_EN (
IN,
OUT,
DIR,
RAM_EN,
Address,
MW
);
input [7:0] Address;
input MW;
output reg IN, OUT, DIR, RAM_EN;
always @(Address) begin
case (Address[7:0])
8'b00000001: begin //OUT
IN = 0;
OUT = MW;
DIR = 0;
RAM_EN = 0;
end
... | 6.643954 |
module SFT4A (
a,
sel,
y
);
input [15:0] a;
input [2:0] sel;
output [15:0] y;
reg [15:0] y;
parameter shftpass = 0, sftl = 1, sftr = 2, rotl = 3, rotr = 4;
always @(a or sel) begin
case (sel)
shftpass: y <= a; //数据直通
sftl: y <= {a[14:0], 1'b0}; //左移
sftr: y ... | 7.680164 |
module sftbyn (
clk8,
reset8,
frame_start,
frame_data,
sftbynum,
sftbymax,
neo_addr
);
input clk8;
input reset8;
input frame_start;
input [25:0] frame_data;
input [7:0] sftbynum;
input [7:0] sftbymax;
output [7:0] neo_addr;
reg [7:0] neo_addr;
// add the amount of shif... | 6.933051 |
module for the sfu_out_buff module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
************... | 7.092734 |
module sf_camera_clk_gen (
input clk,
input rst,
output locked,
output phy_out_clk
);
//Local parameters
//Registers/Wires
wire clkfbout_buf;
wire clkfb;
wire clkout;
wire phy_bufout;
//Submodules
DCM_SP #(
.CLKDV_DIVIDE (2.500),
.CLKFX_DIVIDE (5),
.CLKFX_M... | 6.818258 |
module sf_camera_controller (
input clk,
input rst,
//Physical Interface
output o_cam_rst,
output o_flash,
input i_flash_strobe,
output o_cam_in_clk,
//Configuration Registers
input i_auto_flash,
input i_manual_flash_on,
input i_enable,
input i_camera_reset,
outp... | 7.391504 |
module sf_dpram (
clka,
clkb,
addra,
douta,
dina,
wena,
addrb,
doutb
);
parameter aw = 8;
parameter dw = 8;
parameter sz = (32'b1 << aw) - 1;
input clka, clkb, wena;
input [aw-1:0] addra, addrb;
input [dw-1:0] dina;
output [dw-1:0] douta, doutb;
(* ram_style = "distribut... | 6.800869 |
modules take one or two 18-bit signed inputs,
// and produce a 22-bit signed output in a single clock cycle.
// Scaling comments assume each number is interpreted as in the range [-1:1],
// multiply
// r = a * b / 2
// Internally, expect to use 18-bit signed inputs to the hardware multiplier,
// matching the capabilit... | 7.175422 |
modules together, with saturating shifter
// Now the output width matches the input width of 18 bits
module sf_alu #(
parameter dw=18,
parameter mw=18 // see sf_mul
) (
input clk,
input ce, // clock enable
// input ports
input signed [dw-1:0] a,
input signed [dw-1:0] b,
input [2:0] op,
input [1:0] sv,
// re... | 6.883191 |
module sf_main #(
parameter pw = 18, // port width
parameter extra = 4, // extra guard bits that appear in registers and some arithmetic, but maybe not multiplier inputs
parameter mw = 18 // multiplier width, see sf_mul
) (
input clk,
input ce, ... | 8.010011 |
module sf_user #(
parameter pw = 18, // port width
parameter extra = 4, // see sf_main
parameter mw = 18, // multiplier width, pw + extra >= mw
parameter data_len = 6,
parameter consts_len = 4,
parameter const_aw = 2
) (
input clk,
input ce, // clock enable
input signed [pw-1:0] ... | 8.49924 |
module sf_user_pmem #(
`SF_USER_PARAM
) (
`SF_USER_PORTS
// Host port to set parameters in DPRAM
input h_clk,
input h_write,
input [const_aw-1:0] h_addr,
input signed [pw-1:0] h_data
);
wire signed [pw-1:0] rd_data;
wire ... | 8.666096 |
module sf_user_preg #(
`SF_USER_PARAM
) (
`SF_USER_PORTS
// Flattened input to parameter register bank
input [pw*consts_len-1:0] param_in
);
wire signed [pw-1:0] rd_data;
wire [const_aw-1:0] rd_addr;
reg [pw-1:0] p_regbank[consts_len-1:0];
// Register bank wr... | 7.809632 |
module Sgame (
input I_clk, //ȫʱӣ100MHz
input to_left, //ƣߵƽЧ
input to_right, //ƣߵƽЧ
output [3:0] O_blue, //ɫ
output [3:0] O_green, //ɫ
output [3:0] O_red, //ɫ
output HSync, //VGAɨź
output VSync, //VGAɨź
output [3:0] seg_select, //λѡź
output [6:0] seg_LED //źţûС
);
r... | 6.943527 |
module oper_add (
a,
b,
cin,
cout,
o
);
parameter width_a = 32;
parameter width_b = 32;
parameter width_o = 32;
parameter sgate_representation = 1;
input [width_a-1:0] a;
input [width_b-1:0] b;
input cin;
output cout;
output [width_o-1:0] o;
initial begin
// check if wid... | 8.038703 |
module oper_addsub (
a,
b,
addnsub,
o
);
parameter width_a = 32;
parameter width_b = 32;
parameter width_o = 32;
parameter sgate_representation = 0;
input [width_a-1:0] a;
input [width_b-1:0] b;
input addnsub;
output [width_o-1:0] o;
reg [width_a-1:0] not_a;
reg [width_b-1:0] no... | 7.596894 |
module mux21 (
dataa,
datab,
dataout,
outputselect
);
input dataa;
input datab;
output dataout;
input outputselect;
reg tmp_result;
integer i;
always @(dataa or datab or outputselect) begin
tmp_result = 0;
if (outputselect) begin
tmp_result = datab;
end else begin
... | 8.56211 |
module io_buf_tri (
datain,
dataout,
oe
);
input datain;
input oe;
output dataout;
reg tmp_tridata;
always @(datain or oe) begin
if (oe == 0) begin
tmp_tridata = 1'bz;
end else begin
tmp_tridata = datain;
end
end
assign dataout = tmp_tridata;
endmodule
| 6.508235 |
module io_buf_opdrn (
datain,
dataout
);
input datain;
output dataout;
reg tmp_tridata;
always @(datain) begin
if (datain == 0) begin
tmp_tridata = 1'b0;
end else begin
tmp_tridata = 1'bz;
end
end
assign dataout = tmp_tridata;
endmodule
| 6.94503 |
module oper_mult (
a,
b,
o
);
parameter width_a = 32;
parameter width_b = 32;
parameter width_o = 32;
parameter sgate_representation = 1;
input [width_a-1:0] a;
input [width_b-1:0] b;
output [width_o-1:0] o;
// local parameter
parameter width_result = (width_o >= width_a + width_b) ? w... | 7.240193 |
module tri_bus (
datain,
dataout
);
parameter width_datain = 1;
parameter width_dataout = 1;
input [(width_datain)-1:0] datain;
output [width_dataout-1:0] dataout;
reg [width_dataout-1:0] tmp_result;
integer i;
initial begin
tmp_result = 1'bz;
// check if width_a > 0
if (width_dat... | 7.234356 |
module oper_div (
a,
b,
o
);
parameter width_a = 6;
parameter width_b = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_a-1:0] a;
input [width_b-1:0] b;
output [width_o-1:0] o;
wire [width_a-1:0] tmp_result;
reg [width_o-1:0] tmp_result2;
wire [width_b-1:0] ... | 6.780191 |
module oper_left_shift (
a,
amount,
cin,
o
);
parameter width_a = 6;
parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_a-1:0] a;
input [width_amount-1:0] amount;
input cin;
output [width_o-1:0] o;
integer i;
reg [width_a-1:0] ONES;... | 7.708718 |
module oper_right_shift (
a,
amount,
cin,
o
);
parameter width_a = 6;
parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_a-1:0] a;
input [width_amount-1:0] amount;
input cin;
output [width_o-1:0] o;
integer i;
reg [width_a-1:0] ONES... | 7.898092 |
module oper_rotate_left (
amount,
a,
o
);
parameter width_a = 6;
parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_amount-1:0] amount;
input [width_a-1:0] a;
output [width_o-1:0] o;
wire [width_a-1:0] temp_result;
wire temp_direction = 1... | 7.917185 |
module oper_rotate_right (
amount,
a,
o
);
parameter width_a = 6;
parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_amount-1:0] amount;
input [width_a-1:0] a;
output [width_o-1:0] o;
wire [width_a-1:0] temp_result;
wire temp_direction = ... | 7.609079 |
module oper_less_than (
a,
b,
cin,
o
);
parameter width_a = 6;
parameter width_b = 6;
parameter sgate_representation = 0;
parameter width_max = width_a > width_b ? width_a : width_b;
input [width_a-1:0] a;
input [width_b-1:0] b;
input cin;
output o;
integer sa;
integer sb;
reg ... | 7.702289 |
module oper_mux (
sel,
data,
o
);
parameter width_sel = 6;
parameter width_data = 6;
input [width_sel-1:0] sel;
input [width_data-1:0] data;
output o;
reg temp_result;
initial begin
temp_result = 'bz;
// check if width_a > 0
if (width_data <= 0) begin
$display("Error! w... | 8.549112 |
module oper_selector (
sel,
data,
o
);
parameter width_sel = 6;
parameter width_data = 6;
input [width_sel-1:0] sel;
input [width_data-1:0] data;
output o;
reg temp_result;
reg [width_data-1:0] result;
integer i;
initial begin
// check if width_a > 0
if (width_sel <= 0) begin
... | 7.644269 |
module oper_decoder (
i,
o
);
parameter width_i = 6;
parameter width_o = 6;
input [width_i-1:0] i;
output [width_o-1:0] o;
initial begin
// check if width_i > 0
if (width_i <= 0) $display("Error! width_i must be greater than 0.\n");
if (width_o <= 0) $display("Error! width_o must be g... | 7.653646 |
module oper_bus_mux (
a,
b,
sel,
o
);
parameter width_a = 6;
parameter width_b = 6;
parameter width_o = 6;
input [width_a-1:0] a;
input [width_b-1:0] b;
input sel;
output [width_o-1:0] o;
wire [width_a+width_b-1:0] all_inps;
assign all_inps[width_a-1:0] = a[width_a-1:0];
assign ... | 7.599835 |
module oper_latch (
datain,
dataout,
latch_enable,
aclr,
preset
);
input datain, latch_enable, aclr, preset;
output dataout;
reg dataout;
always @(datain or latch_enable or aclr or preset) begin
if (aclr === 1'b1) dataout = 1'b0;
else if (preset === 1'b1) dataout = 1'b1;
else i... | 6.975748 |
module wbterm #(
parameter DWIDTH = 32,
parameter AWIDTH = 32
) (
input clk,
input rstn,
input cyc,
input stb,
input we,
input [DWIDTH/8-1:0] sel,
input [ AWIDTH-1:0] addr,
... | 8.195975 |
module sgdma_rx_command_grabber (
// inputs:
clk,
command_fifo_empty,
command_fifo_q,
m_write_waitrequest,
reset_n,
write_go,
// outputs:
command_fifo_rdreq,
generate_eop,
write_command_data,
write_command_valid
);
output command_fifo_rdreq;
output generate_eop;
o... | 7.50191 |
module sgdma_rx_command_fifo (
// inputs:
clk,
command_fifo_data,
command_fifo_rdreq,
command_fifo_wrreq,
reset,
// outputs:
command_fifo_empty,
command_fifo_full,
command_fifo_q
);
output command_fifo_empty;
output command_fifo_full;
output [103:0] command_fifo_q;
inpu... | 7.50191 |
module sgdma_rx_desc_address_fifo (
// inputs:
clk,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
reset,
// outputs:
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q
);
output desc_address_fifo_empty;
output desc_address_fifo_... | 7.6679 |
module sgdma_tx_command_grabber (
// inputs:
clk,
command_fifo_empty,
command_fifo_q,
m_read_waitrequest,
read_go,
reset_n,
// outputs:
command_fifo_rdreq,
read_command_data,
read_command_valid
);
output command_fifo_rdreq;
output [58:0] read_command_data;
output read... | 8.205705 |
module sgdma_tx_m_readfifo_m_readfifo (
// inputs:
clk,
m_readfifo_data,
m_readfifo_rdreq,
m_readfifo_wrreq,
reset,
// outputs:
m_readfifo_empty,
m_readfifo_full,
m_readfifo_q,
m_readfifo_usedw
);
output m_readfifo_empty;
output m_readfifo_full;
output [36:0] m_readfi... | 7.371457 |
module sgdma_tx_command_fifo (
// inputs:
clk,
command_fifo_data,
command_fifo_rdreq,
command_fifo_wrreq,
reset,
// outputs:
command_fifo_empty,
command_fifo_full,
command_fifo_q
);
output command_fifo_empty;
output command_fifo_full;
output [103:0] command_fifo_q;
inpu... | 8.205705 |
module sgdma_tx_desc_address_fifo (
// inputs:
clk,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
reset,
// outputs:
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q
);
output desc_address_fifo_empty;
output desc_address_fifo_... | 7.683355 |
module sgdma_tx_status_token_fifo (
// inputs:
clk,
reset,
status_token_fifo_data,
status_token_fifo_rdreq,
status_token_fifo_wrreq,
// outputs:
status_token_fifo_empty,
status_token_fifo_full,
status_token_fifo_q
);
output status_token_fifo_empty;
output status_token_fifo_... | 6.809539 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1... | 6.821676 |
module SGE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) inst1 (
.I0(inst0_O[1]),
.I1(I0[1]),
.I2(I1[1]),
.I3(1'b0),
... | 7.019438 |
module main (
input [3:0] J1,
output J3
);
wire inst0_O;
SGE2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SGE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[1]),
.I1(I0[1]),
.I2(I1[1]),
.O (inst1_O)
);
... | 7.019438 |
module SGE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[1]),
.I1(I0[1]),
.I2(I1[1]),
.O (inst1_O)
);
... | 7.019438 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(ins... | 7.507677 |
module SGE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) inst1 (
.I0(inst0_O[3]),
.I1(I0[3]),
.I2(I1[3]),
.I3(1'b0),
... | 7.148271 |
module main (
input [7:0] J1,
output J3
);
wire inst0_O;
SGE4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SGE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[3]),
.I1(I0[3]),
.I2(I1[3]),
.O (inst1_O)
);
... | 7.148271 |
module main (
input [7:0] SWITCH,
output LED
);
wire inst0_O;
SGE4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module SGE4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I0),
.I1(I1),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h71)
) inst1 (
.I0(inst0_O[3]),
.I1(I0[3]),
.I2(I1[3]),
.O (inst1_O)
);
... | 7.148271 |
module cordic_gain #(
parameter gp_mode_rot_vec = 0,
parameter gp_gain_width = 12,
parameter gp_xy_width = 8,
parameter gp_xy_owidth = gp_xy_width + $clog2(gp_gain_width)
) (
input wire signed [gp_xy_width-1 : 0] i_cordic_x,
input wire signed [gp_xy_width-1 : 0] i_cordic_y,
output... | 7.389307 |
module sgmii_fifo (
input rst_in,
input clk_in,
input clk_out,
input [8:0] fifo_in,
input push,
output full,
output [8:0] fifo_out,
input pop,
output empty
);
parameter DEPTH = 32; // max 64 (can hold DEPTH-1 before full)
parameter TRIG_DEPTH = 12; // Hold sync until push sto... | 6.727554 |
module implements a registered signed multiplier
between filter coefficients (h) and windowed pixels (x)
........................
By: Abdullah Al-Dujaili
NTU, 2012
........................
*/
module sgnd_mult
#(
parameter PIX_BIT=8,
COFCNT_BIT=16
)
(
input wire clk,reset,... | 6.904081 |
module sgn_mult_8x14 (
dataa,
datab,
result
);
input [7:0] dataa;
input [13:0] datab;
output [21:0] result;
wire [21:0] sub_wire0;
wire [21:0] result = sub_wire0[21:0];
lpm_mult lpm_mult_component (
.dataa(dataa),
.datab(datab),
.result(sub_wire0),
.aclr(1'b0),
.... | 6.514463 |
module sgn_ram (
en,
clk,
rst,
qsgn,
rsgn,
qsgn2
);
parameter D = 8;
input clk, rst, en;
input [D-1:0] qsgn;
output reg rsgn;
output reg [D-1:0] qsgn2;
always @(posedge clk) begin
if (rst) begin
rsgn <= 0;
qsgn2 <= 0;
end else if (en) begin
rsgn <= ^qsgn;... | 6.722152 |
module sgn_result (
input wire Add_Subt_i, //Operation bit
input wire sgn_X_i, //Sign bit of DATA_X
input wire sgn_Y_i, //Sign bit of DATA_Y
input wire gtXY_i, // X > Y flag from Magnitude_comparator
input wire eqXY_i, // X = Y flag from Magnitude_comparator
output wire sgn_result_o
);
a... | 7.545472 |
module sgpr_3to1_rd_port_mux (
port0_rd_en,
port0_rd_addr,
port1_rd_en,
port1_rd_addr,
port2_rd_en,
port2_rd_addr,
port_rd_data,
rd_addr,
rd_data
);
input port0_rd_en;
input [8:0] port0_rd_addr;
input port1_rd_en;
input [8:0] port1_rd_addr;
input port2_rd_en;
input... | 6.705133 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1... | 6.821676 |
module SGT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) inst1 (
.I0(inst0_O[1]),
.I1(I1[1]),
.I2(I0[1]),
.I3(1'b0),
... | 6.906196 |
module main (
input [3:0] J1,
output J3
);
wire inst0_O;
SGT2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SGT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[1]),
.I1(I1[1]),
.I2(I0[1]),
.O (inst1_O)
);
... | 6.906196 |
module SGT2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] inst0_O;
wire inst1_O;
Sub2_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[1]),
.I1(I1[1]),
.I2(I0[1]),
.O (inst1_O)
);
... | 6.906196 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add4_CIN (
input [3:0] I0,
input [3:0] I1,
input CIN,
output [3:0] O
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(ins... | 7.507677 |
module SGT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h008E)
) inst1 (
.I0(inst0_O[3]),
.I1(I1[3]),
.I2(I0[3]),
.I3(1'b0),
... | 6.987221 |
module main (
input [7:0] J1,
output J3
);
wire inst0_O;
SGT4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module SGT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[3]),
.I1(I1[3]),
.I2(I0[3]),
.O (inst1_O)
);
... | 6.987221 |
module main (
input [7:0] SWITCH,
output LED
);
wire inst0_O;
SGT4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module SGT4 (
input signed [3:0] I0,
input signed [3:0] I1,
output O
);
wire [3:0] inst0_O;
wire inst1_O;
Sub4_cin1 inst0 (
.I0(I1),
.I1(I0),
.O (inst0_O)
);
LUT3 #(
.INIT(8'h8E)
) inst1 (
.I0(inst0_O[3]),
.I1(I1[3]),
.I2(I0[3]),
.O (inst1_O)
);
... | 6.987221 |
module sg_list_reader_128 #(
parameter C_DATA_WIDTH = 9'd128
) (
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output ... | 7.774419 |
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