code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module shiftleft2_add (
in,
ena,
out
);
input [24:0] in;
input ena;
output [24:0] out;
assign out = ena ? {in[22:0], 2'b0} : in;
endmodule
| 6.919721 |
module shiftleft16_div (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {in[8:0], 16'b0} : in;
endmodule
| 7.654478 |
module shiftleft8_div (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {in[16:0], 8'b0} : in;
endmodule
| 7.057844 |
module shiftleft4_div (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {in[20:0], 4'b0} : in;
endmodule
| 7.736205 |
module shiftleft2_div (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {in[22:0], 2'b0} : in;
endmodule
| 7.716293 |
module shiftleft1_div (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {in[23:0], 1'b0} : in;
endmodule
| 6.726322 |
module shiftleft_four (
result,
data_operand
);
input [31:0] data_operand;
output [31:0] result;
assign result[0] = 1'b0;
assign result[1] = 1'b0;
assign result[2] = 1'b0;
assign result[3] = 1'b0;
assign result[4] = data_operand[0];
assign result[5] = data_operand[1];
assign result[6] ... | 7.034486 |
module shiftleft16_mult (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {in[8:0], 16'b0} : in;
endmodule
| 7.095074 |
module shiftleft4_mult (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {in[20:0], 4'b0} : in;
endmodule
| 6.698116 |
module shiftleft2_mult (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {in[22:0], 2'b0} : in;
endmodule
| 6.933418 |
module shiftleft_one (
result,
data_operand
);
input [31:0] data_operand;
output [31:0] result;
assign result[0] = 1'b0;
assign result[1] = data_operand[0];
assign result[2] = data_operand[1];
assign result[3] = data_operand[2];
assign result[4] = data_operand[3];
assign result[5] = data... | 6.567693 |
module shiftleft_two (
result,
data_operand
);
input [31:0] data_operand;
output [31:0] result;
assign result[0] = 1'b0;
assign result[1] = 1'b0;
assign result[2] = data_operand[0];
assign result[3] = data_operand[1];
assign result[4] = data_operand[2];
assign result[5] = data_operand[3]... | 6.56774 |
module shiftLL_by_5bit (
data_operandA,
ctrl_shiftamt,
shiftLL_result
);
input [31:0] data_operandA;
input [4:0] ctrl_shiftamt;
output [31:0] shiftLL_result;
wire [31:0] shiftL0, shiftL1, shiftL2, shiftL3;
// shift left 1 bit
mux_2_1 shiftL00 (
data_operandA[0],
1'b0,
ctrl_sh... | 6.914826 |
module shiftlne_tb;
// test the shiftlne module
// As it stands this will shift the bits by one place.
// Turn Load on, cycle the clock, then turn load off, cycle the clock.
// It appears only one cycle is required to shift all the bits one place.
parameter n = 8;
reg [n-1:0] R;
reg E, L, w, Clock;
wir... | 7.301962 |
module ShiftLR (
Z,
X,
S,
LEFT,
LOG
);
input [31:0] X;
input [4:0] S;
input LEFT;
input LOG;
output [31:0] Z;
// intermediate wires needed
wire [4:0] shift;
reg [62:0] mux_in;
wire [46:0] shift4;
wire [38:0] shift3;
wire [34:0] shift2;
wire [32:0] shift1;
wire [31:0] shift... | 7.251173 |
module ShiftLR (
Z,
X,
S,
LEFT,
LOG
);
input [31:0] X;
input [4:0] S;
input LEFT;
input LOG;
output [31:0] Z;
// intermediate wires needed
wire [ 4:0] shift;
wire [31:0] shift4;
wire [31:0] shift3;
wire [31:0] shift2;
wire [31:0] shift1;
wire [31:0] shift0;
// Naming conv... | 7.251173 |
module ShiftLR (
Z,
X,
S,
LEFT,
LOG
);
input signed [31:0] X;
input [4:0] S;
input LEFT;
input LOG;
output reg signed [31:0] Z;
always @(*) begin
case ({
LEFT, LOG
})
2'b00: Z <= X >>> S;
2'b01: Z <= X >> S;
2'b10: Z <= X <<< S;
2'b11: Z <= X << S;... | 7.251173 |
module ShiftLR (
Z,
X,
S,
LEFT,
LOG,
EN
);
input [31:0] X;
input [4:0] S;
input LEFT;
input LOG;
output [31:0] Z;
input EN;
// intermediate wires needed
wire [4:0] shift;
reg [62:0] mux_in;
wire [46:0] shift4;
wire [38:0] shift3;
wire [34:0] shift2;
wire [32:0] shift1;... | 7.251173 |
module ShiftLR_tb ();
// inputs to the shifter
reg signed [31:0] input_data;
reg [4:0] shift_amount;
reg left, logical;
// outputs from the shifter
wire signed [31:0] output_data;
// create a clock to control shifting
reg clk;
// instantiate the barrel shifter here
ShiftLR inst_shift (
.X(... | 8.488232 |
module ShiftLR_tb ();
// inputs to the shifter
reg signed [31:0] input_data, input_data_latch;
reg [4:0] shift_amount, shift_amount_latch;
reg left, logical, en;
// outputs from the shifter
wire signed [31:0] output_data;
// create a clock to control shifting
reg clk;
// instantiate the barrel shi... | 8.488232 |
module
// serin. Serial input
// Outputs: data. Parallel output
module shiftM(input wire clk,
input wire enable,
input wire serin,
output [M-1:0] data);
// Bit count
parameter M = 32;
// Initial value to load on register
parameter INI = 1;
reg [M-1:0] data = INI;
... | 8.637483 |
module shiftmul1_FixPt (
clk,
reset,
clk_enable,
data1,
data2,
ce_out,
Y1,
Y3
);
input clk;
input reset;
input clk_enable;
input [4:0] data1; // ufix5
input [5:0] data2; // ufix6
output ce_out;
output [7:0] Y1; // ufix8
output signed [6:0] Y3; // sfix7
wire enb;... | 6.638019 |
module ShiftNMux (
input wire [ 1:0] ShiftNCrtl,
input wire [31:0] B, //00
input wire [31:0] MemDataOut, //01
input wire [15:0] Instruction_15_0, //10
output wire [ 4:0] Data_out
);
// B ----------------|
// MemDataOut--------|-- B_MemOut --\
// ... | 7.286513 |
module ShiftNMuxTest ();
reg [31:0] B, MemDataOut;
reg [15:0] Instruction_15_0;
reg [ 1:0] ShiftNCrtl;
wire [ 4:0] Data_out;
ShiftNMux dut (
.B(B),
.Instruction_15_0(Instruction_15_0),
.MemDataOut(MemDataOut),
.ShiftNCrtl(ShiftNCrtl),
.Data_out(Data_out)
);
initial begin
... | 8.392928 |
module shiftout #(
parameter DATA_WIDTH = 16,
COUNTER_WIDTH = 5
) (
Z_parallel,
Sx,
reset,
Clk,
Z_out,
Fx
);
input [DATA_WIDTH-1:0] Z_parallel;
input Sx, reset, Clk;
output Z_out, Fx;
reg Z_out, Fx;
reg [COUNTER_WIDTH-1:0] counter;
reg new_shift_out;
always @(posedge Clk o... | 7.937957 |
module shiftRam8_128 (
clk, //
rst_n, //
clr, //useless, hahaha
din, //data input
sin, //sync signal input
dout, // data output, (delay of din)
dshift, // shift data output
sout // sync signal output
);
input clk;
input rst_n;
input clr;
input [7:0] din;
input sin; ... | 7.775054 |
module shiftRam8_256 (
clk, //
rst_n, //
clr, //useless, hahaha
din, //data input
sin, //sync signal input
dout, // data output, (delay of din)
dshift, // shift data output
sout // sync signal output
);
input clk;
input rst_n;
input clr;
input [7:0] din;
input sin; ... | 7.411483 |
module shiftRam8_32 (
clk, //
rst_n, //
clr, //useless, hahaha
din, //data input
sin, //sync signal input
dout, // data output, (delay of din)
dshift, // shift data output
sout // sync signal output
);
input clk;
input rst_n;
input clr;
input [7:0] din;
input sin; ... | 8.114113 |
module shiftRam8_512 (
clk, //
rst_n, //
clr, //useless, hahaha
din, //data input
sin, //sync signal input
dout, // data output, (delay of din)
dshift, // shift data output
sout // sync signal output
);
input clk;
input rst_n;
input clr;
input [7:0] din;
input sin; ... | 7.547348 |
module shiftRam8_64 (
clk, //
rst_n, //
clr, //useless, hahaha
din, //data input
sin, //sync signal input
dout, // data output, (delay of din)
dshift, // shift data output
sout // sync signal output
);
input clk;
input rst_n;
input clr;
input [7:0] din;
input sin; ... | 8.174252 |
module ShiftReg (
in,
en,
clock,
q
);
initial begin
$dumpfile("ShiftReg.vcd");
$dumpvars;
end
parameter n = 4;
input in, en, clock;
output [n-1:0] q;
reg [n-1:0] q;
initial q = 4'd10;
always @(posedge clock) begin
if (en) q = {in, q[n-1:1]};
end
endmodule
| 8.65434 |
module SHIFTREG1 (
output reg [7:0] data_out,
input wire [7:0] data_in,
input wire s_in,
clk,
Ld,
clr,
sft
);
always @(posedge clk) begin
if (clr) data_out <= 0;
else if (Ld) data_out <= data_in;
else if (sft) data_out <= {s_in, data_out[7:1]};
end
endmodule
| 7.715702 |
module shiftreg24b (
clk,
reset,
shift,
carrega,
in,
regout
);
input clk;
input reset, shift;
input carrega; // per carregar dades
input [24:0] in;
output regout;
reg [24:0] missatge;
assign regout = missatge[24];
always @(posedge clk) begin
if (reset == 1) missatge <= 3... | 7.890317 |
module shiftreg32b (
clk,
reset,
shift,
carrega,
in,
regout
);
input clk;
input reset, shift;
input carrega; // per carregar dades
input [31:0] in;
output regout;
reg [31:0] missatge;
assign regout = missatge[31];
always @(posedge clk) begin
if (reset == 1) missatge <= 3... | 8.425426 |
module ShiftReg32bL (
clk,
load,
S_L,
s_in,
p_in,
Q
);
input wire clk;
input wire S_L; // 并行输入命令 ~S/L; 0: Serial mode; 1: parallel mode
input wire s_in; // shift_in, 串行输入
input wire [31:0] p_in; // par_in, 并行输入数据
input wire load; // 1: write
output reg [31:0] Q; // value of all ... | 7.070546 |
module shiftreg32bsp (
clk,
reset,
shift,
in,
missatge
);
input clk;
input reset;
input shift;
input in;
output [31:0] missatge;
reg [31:0] missatge;
always @(posedge clk) begin
if (reset == 1) missatge <= 32'd0;
else if (shift) missatge <= {missatge[30:0], in};
end
endmo... | 8.1111 |
module shiftreg4_behav (
clk,
rst,
din,
dout
);
input clk;
input rst;
input din;
output dout;
wire dout;
reg q0;
reg q1;
reg q2;
reg q3;
always @(posedge clk) begin
if (rst) begin
q3 <= 1'b0;
q2 <= 1'b0;
q1 <= 1'b0;
q0 <= 1'b0;
end else begin
... | 7.77411 |
module shiftreg4 (
clk,
rst,
din,
dout
);
input clk;
input rst;
input din;
output dout;
wire dout;
reg [3:0] q;
always @(posedge clk) begin
if (rst) begin
q <= 4'b0000;
end else begin
q <= {q[2:0], din};
end
end
assign dout = q[3];
endmodule
| 7.681945 |
module shiftreg4_behav_tb ();
reg t_clk;
reg t_rst;
reg t_din;
wire t_dout;
shiftreg4_behav dut (
.clk (t_clk),
.rst (t_rst),
.din (t_din),
.dout(t_dout)
);
//Produce the clock
initial begin
t_clk = 0;
end
always #15 t_clk = ~t_clk;
//Generates a reset signal and... | 7.77411 |
module shiftreg4_struct (
clk,
rst,
din,
dout
);
input clk;
input rst;
input din;
output dout;
wire dout;
wire q0;
wire q1;
wire q2;
asyn_dff ff0 (
.clk(clk),
.rst(rst),
.d (din),
.q (q0)
);
asyn_dff ff1 (
.clk(clk),
.rst(rst),
.d (q... | 7.289955 |
module shiftreg4_struct_tb ();
reg t_clk;
reg t_rst;
reg t_din;
wire t_dout;
shiftreg4_struct dut (
.clk (t_clk),
.rst (t_rst),
.din (t_din),
.dout(t_dout)
);
//Produce the clock
initial begin
t_clk = 0;
end
always #15 t_clk = ~t_clk;
//Generates a reset signal a... | 7.289955 |
module ShiftReg65b (
clk,
operation,
shiftIn, // serial input
d,
q
);
input wire clk;
input wire [2:0] operation;
input wire shiftIn;
input wire [64:0] d;
output reg [64:0] q;
always @(posedge clk) begin
case (operation)
`ShiftReg65b_Operation_DoNothing: begin
q <= q;... | 8.047605 |
module shiftreg8 (
input [7:0] data_i, // data input
input load_i, // load data (sync)
input dir_i, // shift direction h: right, l: left
input cen, // clock enabled (shift)
input clk_i, // clock
output [7:0] data_o // data output
);
reg [7:0] data = 0;
assign... | 8.024326 |
module ShiftReg8b (
clk,
S_L,
s_in,
p_in,
Q
);
input wire clk;
input wire S_L; // 并行输入命令 ~S/L; 0: Serial mode; 1: parallel mode
input wire s_in; // shift_in, 串行输入
input wire [7:0] p_in; // par_in, 并行输入数据
output reg [7:0] Q; // value of all regs
initial begin
Q = 0;
end
wire... | 7.41223 |
module ShiftReg8b_tb ();
reg clk;
reg S_L; // 并行输入命令 ~S / L
reg s_in; // shift_in, 串行输入
reg [7:0] p_in; // par_in, 并行输入数据
wire [7:0] Q; // output
ShiftReg8b UUT (
clk,
S_L,
s_in,
p_in,
Q
);
initial begin
$dumpfile("ShiftReg8b_tb.vcd");
$dumpvars(0, ShiftReg8b... | 6.922958 |
module shiftregbidir (
input CLK,
RL,
LD,
output reg [3:0] D,
input [3:0] InP,
input InS,
Clear
);
always @(Clear) if (Clear == 0) D = 4'b0000; // Clear (asíncrono, activo cero)
always @(negedge CLK)
case ({
LD, RL, Clear
}) // Concatenar es {}
3'b001: D = {InS, ... | 7.332543 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index... | 7.124291 |
module shiftRegFIFO_2_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
assign Y = mem_1;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
end else begin
mem_1 <= mem_0;
mem_0 <= X;
end
end
... | 6.959357 |
module shiftRegFIFO_5_1 (
input [0:0] X,
output [0:0] Y,
input reset,
input clk
);
reg [0:0] mem_0;
reg [0:0] mem_1;
reg [0:0] mem_2;
reg [0:0] mem_3;
reg [0:0] mem_4;
assign Y = mem_4;
always @(posedge clk) begin
if (reset) begin
mem_0 <= 0;
mem_1 <= 0;
mem_2 <= 0;... | 6.959357 |
module shiftRegIn #(
parameter TOTAL_BIT_COUNT = 8
) (
// Input Clocks and Resets
input serclk,
input reset_n,
// SERIAL Data In from baseboard
input ser_data_in,
// Shift Control Bits
input ser_load_in_n,
// PARALLEL Output
output reg [TOTAL_BIT_COUNT-1:0] p_out
);
reg [... | 9.126591 |
module shiftRegInTB;
parameter Total = 8;
// Inputs
reg serclk = 0;
reg reset_n;
reg ser_load_in_n;
reg sdi;
// Outputs
wire [7:0] p_out;
// Instantiate the Unit Under Test (UUT)
shiftRegIn #(8) s1 (
.serclk(serclk),
.reset_n(reset_n),
.ser_load_in_n(ser_load_in_n),
.ser_da... | 6.730222 |
module testshiftregister ();
reg clk;
reg peripheralClkEdge;
reg parallelLoad;
wire [7:0] parallelDataOut;
wire serialDataOut;
reg [7:0] parallelDataIn;
reg serialDataIn;
// Instantiate with parameter width = 8
shiftregister #(8) dut (
.clk(clk),
.perip... | 6.704281 |
module shiftregister6bit (
d,
clock,
q
);
input d, clock;
output [5:0] q;
dff2 stage0 (
d,
clock,
q[0]
);
dff2 stage1 (
q[0],
clock,
q[1]
);
dff2 stage2 (
q[1],
clock,
q[2]
);
dff2 stage3 (
q[2],
clock,
q[3]
);
df... | 7.020433 |
module is used to both write data to I2C and read data from I2c
//////////////////////////////////////////////////////////////////////////////////
module ShiftRegisterI2C2015fall(SentData,Clock,Reset,ShiftIn,ShiftOrHold,WriteLoad,ReceivedData,ShiftOut,ClockI2C);
input [7:0] SentData;
input Clock;
input ClockI2C;
in... | 6.908055 |
module: ShiftRegister
//
// Dependencies: ShiftRegister
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ShiftRegisterTest;
// Inputs
reg CLK;
reg [3:0] D;
reg [1:0] S;
reg OE;
// Outputs
wire [... | 6.622345 |
module creates a Shift Register with a seperate enable signal.
This specific module creates an output that is 14-bits wide.
*/
module ShiftRegisterWEnableFourteen(clk, resetn, enable, d, q);
//Define the inputs and outputs
input clk;
input resetn;
input enable;
input d;
output [13:0] q;
D_FF_with_Enable Zer... | 7.861914 |
module creates a Shift Register with a seperate enable signal.
This specific module creates an output that is 16-bits wide.
This module uses asyncronous D Flip Flops.
It also can allow data to be inputed into the flip flops before shifting.
*/
module ShiftRegisterWEnableFourteenAsyncMuxedInput(clk, resetn, enable, sel... | 7.861914 |
module creates a Shift Register with a seperate enable signal.
This specific module creates an output that is 14-bits wide.
*/
module ShiftRegisterWEnableSixteen(clk, resetn, enable, d, q);
//Define the inputs and outputs
input clk;
input resetn;
input enable;
input d;
output [15:0] q;
D_FF_with_Enable Zero... | 7.861914 |
module creates a Shift Register with a seperate enable signal.
This specific module creates an output that is 16-bits wide.
This module uses asyncronous D Flip Flops.
It also can allow data to be inputed into the flip flops before shifting.
*/
module ShiftRegisterWEnableSixteenAsyncMuxedInput(clk, resetn, enable, sele... | 7.861914 |
module shiftregister_tb;
// wire dout;
wire [1:0] s;
reg tin, clk, reset;
integer i = 0;
shiftregister s1 (
tin,
clk,
reset,
s
);
initial begin
reset = 0;
clk = 0;
for (i = 0; i <= 2; i = i + 1) #10 clk = ~clk;
end
initial begin
$monitor("%b %b %b %b", tin, cl... | 7.020433 |
module shiftRegister_testbench;
reg clock = 0;
reg reset = 0;
reg io_in = 0;
reg io_enable = 0;
wire [7:0] io_out;
ShiftRegister uut (
.clock(clock),
.reset(reset),
.io_in(io_in),
.io_enable(io_enable),
.io_out(io_out)
);
initial begin
cl... | 8.12979 |
module shftregright (
input CLK,
SHFT,
LD,
output reg [3:0] D,
input [3:0] InP,
input InS,
Clear
);
always @(Clear) if (Clear == 0) D = 4'b0000; // Clear (asíncrono, activo cero)
always @(negedge CLK)
case ({
LD, SHFT, Clear
}) // Concatenar es {}
3'b011: D = {InS,... | 6.66805 |
module shift_register_SIPO (
paralelo
);
output wire [7:0] paralelo;
integer i;
reg [7:0] outbus;
reg [7:0] tempbus;
clockdemux clkd ();
shift_register_PISO srPISO ();
initial begin
i = 0;
end
assign paralelo = outbus;
always @(posedge clkd.saida) begin
#2;
if (i == 8) begin
... | 6.854847 |
module shiftregtest;
parameter n = 4;
reg EN, in, CLK;
wire [n-1:0] Q;
//reg [n-1:0] Q;
shiftreg shreg (
EN,
in,
CLK,
Q
);
initial begin
CLK = 0;
end
always #2 CLK = ~CLK;
initial $monitor($time, "EN=%b in= %b Q=%b\n", EN, in, Q);
initial begin
in = 0;
EN = ... | 6.774302 |
module for 4-bit shift register using
//non-blocking assignment.
module shiftreg_4bit (output reg e,
input wire a, clk, clear
);
reg b, c, d;
always @(posedge clk or negedge clear) begin
if(!clear) {b, c, d}= {1'b0, 1'b0, 1'b0}; //active low clear
else begin
e<= d;... | 9.692665 |
module shiftreg_4bit_tb ();
wire e;
reg a, clk, clear;
shiftreg_4bit s0 (
e,
a,
clk,
clear
);
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
$dumpfile("shiftreg_4bit.vcd");
$dumpvars(0, shiftreg_4bit_tb);
clear = 1'b0;
#34;
clear... | 6.928835 |
module shiftreg_data (
clken,
clock,
shiftin,
shiftout,
taps
);
input clken;
input clock;
input [31:0] shiftin;
output [31:0] shiftout;
output [31:0] taps;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`... | 7.146207 |
module shiftreg_in (
input reset,
output [7:0] data,
input serclk,
input ser_in,
input enable // active high
);
reg [7:0] shiftreg;
assign data = shiftreg;
wire inv_serclk;
assign inv_serclk = !serclk;
initial begin
shiftreg = 0;
end
always @(posedg... | 7.139773 |
module shiftReg_module (
dataRight,
dataLeft,
LoadLeft,
D,
Loadn,
clock,
reset,
Q
);
input dataRight, dataLeft, LoadLeft, D, Loadn, clock, reset;
output Q;
wire w1, w2, w3;
mux2to1 RotateDirection (
.x(dataRight),
.y(dataLeft),
.s(LoadLeft),
.m(w1)
);
... | 6.653551 |
module shiftreg_out (
input serial_clk,
output serial_out,
output busy,
input reset,
input set_enable,
input set_clk,
input [7:0] data_in
);
reg [7:0] data;
reg [7:0] shift_data;
reg [3:0] current_bit;
reg vreg;
wire valid;
reg sending;
assign busy = sending & vreg;
assign... | 7.717908 |
module shiftreg_sp (
output reg [3:0] dout,
input clk,
reset,
din
);
always @(posedge clk, posedge reset) begin
if (reset) dout <= 4'b0;
else dout <= {dout[2:0], din};
end
endmodule
| 7.842839 |
module shiftreg_ss (
output reg dout,
input clk,
reset,
din
);
reg [3:0] r;
always @(posedge clk, posedge reset) begin
if (reset) r <= 4'b0000;
else begin
r <= {r[2:0], din};
dout <= r[3];
end
end
endmodule
| 6.781484 |
module shiftReg_TB ();
reg [31:0] parallelInput;
wire masterClk;
reg serialInput;
reg clk;
reg load;
reg enableShift;
wire [31:0] parallelOutput;
wire serialOutput;
wire loaded;
reg [31:0] result;
reg [31:0] serialGen;
integer shiftIndex, shiftOutIndex, valIndex;
shiftReg #(
.WIDTH(32)... | 7.027264 |
module shiftreg_u #(
parameter N = 4
) (
output reg [N-1:0] q,
input [N-1:0] d,
input [1:0] s,
input Lin,
Rin,
input clk,
rst_n
);
always @(posedge clk) begin
if (~rst_n) q <= 0;
else
case (s)
2'b11: q <= d;
2'b10: q <= {q[N-2:0], Rin};
2'b01:... | 8.207045 |
module shiftrightby1 (
DO,
DI,
sel
);
output [23:0] DO;
input [23:0] DI;
input sel;
assign DO = sel ? {1'b0, DI[23:1]} : DI;
endmodule
| 7.24999 |
module shiftrightby2 (
DO,
DI,
sel
);
output [23:0] DO;
input [23:0] DI;
input sel;
assign DO = sel ? {2'b00, DI[23:2]} : DI;
endmodule
| 6.8298 |
module shiftrightby4 (
DO,
DI,
sel
);
output [23:0] DO;
input [23:0] DI;
input sel;
assign DO = sel ? {4'h0, DI[23:4]} : DI;
endmodule
| 6.573123 |
module shiftrightby8 (
DO,
DI,
sel
);
output [23:0] DO;
input [23:0] DI;
input sel;
assign DO = sel ? {8'h00, DI[23:8]} : DI;
endmodule
| 6.63522 |
module shiftrightby16 (
DO,
DI,
sel
);
output [23:0] DO;
input [23:0] DI;
input sel;
assign DO = sel ? {16'h0000, DI[23:16]} : DI;
endmodule
| 7.24999 |
module ShiftRight2 (
in,
shiftedOut
);
input [31:0] in;
output reg [31:0] shiftedOut;
always @(in) begin
shiftedOut <= (in - 16) >> 2;
end
endmodule
| 7.526379 |
module ShiftRight64 (
clk,
isShiftRight,
isWrite,
d,
q
);
input wire clk;
input wire isShiftRight;
input wire isWrite;
input wire [63:0] d;
output reg [63:0] q;
always @(posedge clk) begin
case ({
isShiftRight, isWrite
})
2'b00: begin
q <= q;
end
... | 8.014685 |
module. signed shift a
given input right by a specified number of bits.
*/
module shiftRightArithmetic(In, Cnt, Out);
// variable declaration
input [15:0] In;
input [3:0] Cnt;
output [15:0] Out;
wire [15:0] inter1, inter2, inter3;
assign inter1 = Cnt[3] ? {{8{In[15]}}, In[15:8]} : In;
... | 8.105592 |
module. unsigned shift a
given input right by a specified number of bits.
*/
module shiftRightLogical(In, Cnt, Out);
// variable declaration
input [15:0] In;
input [3:0] Cnt;
output [15:0] Out;
wire [15:0] inter1, inter2, inter3;
assign inter1 = Cnt[3] ? {8'b0, In[15:8]} : In;
assig... | 8.073246 |
module ShiftRightN (
from,
shamt,
to
);
input wire [31:0] from;
input wire [4:0] shamt;
output wire [31:0] to;
assign to = from >> shamt;
endmodule
| 7.231056 |
module shiftRightTest;
reg [31:0] TinA, TinB;
wire [31:0] Tout;
initial begin
$dumpfile("shiftRightTest.vcd");
$dumpvars(0, shiftRightTest);
$monitor($time,, Tout,, TinA,, TinB);
TinA = 32'hffffffff;
TinB = 32'd31;
#500;
TinB = 32'd29;
#500;
TinB = 32'd23;
#500;
end
sh... | 6.804859 |
module shiftRight_Arithmetic (
In,
Cnt,
Out
);
input [15:0] In;
input [3:0] Cnt;
output reg [15:0] Out;
wire [15:0] out;
always @(*) begin
case (Cnt)
4'b0000: assign Out = In;
4'b0001: assign Out = {{1{In[15]}}, In[15:1]};
4'b0010: assign Out = {{2{In[15]}}, In[15:2]};
... | 7.297266 |
module shiftright_four (
result,
data_operand
);
input [31:0] data_operand;
output [31:0] result;
assign result[0] = data_operand[4];
assign result[1] = data_operand[5];
assign result[2] = data_operand[6];
assign result[3] = data_operand[7];
assign result[4] = data_operand[8];
assign resu... | 7.039699 |
module shiftRight_Logical (
In,
Cnt,
Out
);
input [15:0] In;
input [3:0] Cnt;
output reg [15:0] Out;
always @(*) begin
case (Cnt)
4'b0000: assign Out = In;
4'b0001: assign Out = {1'h0, In[15:1]};
4'b0010: assign Out = {2'h0, In[15:2]};
4'b0011: assign Out = {3'h0, In[1... | 7.520955 |
module shiftRotateTB ();
reg clk = 0;
reg [2:0] shiftCnt = 2;
reg [7:0] D = 5;
reg [1:0] opt = 2'b00;
wire [7:0] rslt;
wire cshift;
initial repeat (10) #50 clk = ~clk;
initial begin
#40 #20 shiftCnt = 2;
#40 D = 8'b01001100;
opt = 2'b00;
#50 opt = 2'b10;
#30 D = 7 + 127;
#40 opt... | 7.683241 |
module shiftrows (
sr_in,
sr_out
);
input [127:0] sr_in;
output reg [127:0] sr_out;
reg [31:0] x1, x2, x3, x4;
always @(*) begin
x1 = sr_in[127:96];
x2 = sr_in[95:64];
x3 = sr_in[63:32];
x4 = sr_in[31:0];
sr_out = {
x1[31:24],
x2[23:16],
x3[15:8],
x4[7:0],
... | 6.943397 |
module ShiftRows (
input Rst,
input Clk,
input En_SHR,
output reg Ry_SHR,
input [127:0] In_SHR,
output reg [127:0] Out_SHR
);
//Registers declaration
reg [31:0] row1;
reg [31:0] row2;
reg [31:0] row3;
reg [31:0] row4;
//Signal that indicates if the
//program has finished shiftin... | 7.112025 |
module implements the shift row operation of AES cipher
algorithm. A simple rewire is used to complete the operation.
-------------------------------------------------------------------------------
-- Copyright (C) 2016 ClariPhy Argentina S.A. All rights reserved
-----------------------------------------------... | 7.842559 |
module shiftr_bram (
input en_in,
input en_out,
input clk,
input rst,
output empty,
output full,
input [7:0] data_in,
output [7:0] data_out
);
//wire rst_n, en_in_n, en_out_n;
//assign rst_n = ~rst;
//assign en_in_n = ~en_in;
//assign en_out_n = ~en_out;
/* V5 Primitive... | 6.869127 |
module shiftr_bram_tb;
reg en_in, en_out, clk, rst;
reg [7:0] data_in;
wire [7:0] data_out;
wire empty;
shiftr_bram dut (
.en_in(en_in),
.en_out(en_out),
.clk(clk),
.rst(rst),
.empty(empty),
.data_in(data_in),
.data_out(data_out)
);
initial begin
clk = 1;
... | 6.507125 |
module shiftr_tb;
reg en_in, en_out, clk, rst;
reg [7:0] data_in;
wire [7:0] data_out;
shiftr dut (
.en_in(en_in),
.en_out(en_out),
.clk(clk),
.rst(rst),
.data_in(data_in),
.data_out(data_out)
);
initial begin
clk = 1;
en_in = 0;
en_out = 0;
rst = 1;
... | 6.583535 |
module barrel_rcr_ (
input wire [31:0] a,
input wire flagc,
output wire [31:0] q,
output wire c,
input wire [4:0] shift
);
reg [31:0] rq;
reg cq; // carry is
assign q = rq;
assign c = cq;
always @(a, shift, flagc) begin
case (shift)
5'h00: {rq, cq} = {a, flagc};
5'h01: {... | 6.547043 |
module ShiftSrcMux (
input wire ShiftSrcCrtl,
input wire [31:0] B,
input wire [31:0] A,
output wire [31:0] Data_out
);
// B ---------|
// A ---------|--- Data_out --->
assign Data_out = (ShiftSrcCrtl) ? A : B;
endmodule
| 9.825528 |
module ShiftSrcMuxTest ();
reg [31:0] B, A;
reg ShiftSrcCtrl;
wire [31:0] Data_out;
ShiftSrcMux dut (
.A(A),
.B(B),
.ShiftSrcCrtl(ShiftSrcCtrl),
.Data_out(Data_out)
);
initial begin
$dumpfile("memAddrMuxTest.vcd");
$dumpvars;
end
initial begin
A = 1;
B = 2;
... | 7.571768 |
module shiftsub_divider #(
parameter WIDTH = 4
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input [2 * WIDTH - 1:0] dividend,
input [WIDTH - 1:0] divisor,
input din_valid,
output reg [2 * WIDTH - 1:0] dout,
output reg [2 * WIDTH - 1:0] remainder
);
reg [3... | 7.47976 |
module shifts 4'bxxxx once in toggle of clk
//
// Dependencies:
//
// Revision:
// Revision 1.3 - workin' review of book vers. of shift register + shiftin' 4'b data + work extra
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shifttt(
input ... | 7.710104 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.