code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Shift_Left_One_64 (
data_i,
data_o
);
//I/O ports
input [64-1:0] data_i;
output [64-1:0] data_o;
//shift left 1
endmodule
| 7.774533 |
module Shift_left_reg_r (
i_clk,
clr_R,
in_r,
en_r,
ld_r,
sl_r,
out_r
);
input i_clk;
input clr_R; ///clears the register ///
input [`WIDTH_R-1:0] in_r;
input ld_r; ///load enable //
input en_r; ///enable the data at input ///
input sl_r; ///shift_enable ///
output reg [`... | 6.702866 |
module Shift_Left_Right (
clk,
res,
shift_left_bits,
shift_right_bits,
shift_left_en,
shift_right_en,
mux_4_output,
out
);
input clk, res, shift_left_en, shift_right_en;
input [7:0] shift_left_bits, shift_right_bits;
input [27:0] mux_4_output;
output reg [27:0] out;
always @(p... | 7.204081 |
module shift_left_test;
// Inputs
reg [31:0] input_data;
// Outputs
wire [31:0] output_data;
// Instantiate the Unit Under Test (UUT)
shift_left uut (
.input_data (input_data),
.output_data(output_data)
);
initial begin
// Initialize Inputs
input_data = 0;
// Wait 100 ns fo... | 6.854565 |
module shiftlefttwice #(
parameter width = 32
) (
in,
out
);
input [width-1:0] in;
output reg [width-1:0] out;
always @(*) begin
out = in << 2;
end
endmodule
| 8.867246 |
module Shift_Left_Two_32 (
data_i,
data_o
);
//I/O ports
input [32-1:0] data_i;
output [32-1:0] data_o;
//shift left 2
assign data_o = {data_i[29:0], 2'b0};
endmodule
| 7.705663 |
module shift_lineS (
data_in,
dataoutb,
dataoutc,
clk,
clear
);
input clk, clear;
input [7:0] data_in;
//output reg [7:0] dataouta;
output reg [7:0] dataoutb;
output reg [7:0] dataoutc;
always @(posedge clk or negedge clear) begin
if (!clear) begin
dataoutb = 8'b0;
data... | 6.649739 |
module shift_line_buffer (
input wire line_clk,
input wire s_rst_n,
input wire in_line_vaild, //在有效数据提前一个周期
input wire [7:0] din,
input wire vsync, //帧同步
output wire [7:0] taps0x,
output wire [7:0] taps1x,
output wire [7:0] taps2x,
output wire ... | 8.513731 |
module shift_memory #(
parameter NB_DATA = 72,
parameter NB_ADDR = 5
) (
input wire i_clock,
input wire i_write_enb,
input wire i_read_enb, // capas no lo necesito en este nivel
input wire [NB_DATA-1 : 0] i_data,
input wire [NB_ADDR-1 : 0] i_... | 7.305474 |
module shift_merge (
input wire clk,
input wire data_hazard,
input wire [7:0] shift_in,
input wire [2:0] D0,
input wire [2:0] L_select,
input wire latch_wren,
input wire latch_address_w,
input wire latch_address_r,
output wire [15:0] data_out
);
reg [7:0] merge_in;
reg [7:0] shif... | 8.432959 |
module shift_module #(parameter data_width = 16) (
input [data_width - 1 : 0] _A,
input [3 : 0] func,
output reg [data_width - 1 : 0] _C
);
always @(*) begin
case (func)
`FUNC_LLS: begin
_C <= (_A << 1);
end
`FUNC_LRS: begi... | 8.616658 |
module arith_shift #(parameter data_width = 16) (
// input [data_width - 1 : 0] A,
// input is_right,
// output reg [data_width - 1 : 0] result,
// output offlag);
// assign offlag = 0;
// always @(*) begin
// if(is_right)begin
// result = A >>> 1;
// if(A[data_width - 1]==1) begin
// result[data_wi... | 7.326996 |
module shift_mux (
sh,
data,
shift_amount,
right,
arithmetic
);
input [31:0] data; // 32-bit data to be shifted
input [4:0] shift_amount; // shift amount(0~31 bits)
input right; // 1: shift right; 0: shift left
input arithmetic; // 1: arithmetic; 0: logical
output [31:0] sh; // shift ... | 7.730516 |
module sll_32 (
input wire [31:0] A,
input wire [31:0] B,
output reg [31:0] out
);
always @* begin
out = A << B;
end
endmodule
| 7.503281 |
module srl_32 (
input wire [31:0] A,
input wire [31:0] B,
output reg [31:0] out
);
always @* begin
out = A >> B;
end
endmodule
| 7.4394 |
module srl_64 (
input wire [63:0] A,
input wire [63:0] B,
output reg [63:0] out
);
always @* begin
out = A >> B;
end
endmodule
| 7.827853 |
module sra_32 (
input wire signed [31:0] A,
input wire [31:0] B,
output reg [31:0] out
);
always @* begin
out = A >>> B;
end
endmodule
| 7.97399 |
module sra_64 (
input wire signed [63:0] A,
input wire [63:0] B,
output reg [63:0] out
);
always @* begin
out = A >>> B;
end
endmodule
| 8.51282 |
module shift_out_reg(
shift_clk,
in_data,
load,
out_bit
);
input shift_clk;
input load;
input [31:0] in_data = 0;
//input load_shift_register;
//output reg out_bit = 0;
output out_bit;
reg [32:0] ring_counter = 0;
//???????????
(*DONT_TOUCH = "TRUE"*) reg [31:0] shift_data;
... | 7.027758 |
module shift_out_test;
// parameter
parameter WIDTH = 8;
parameter DATA_WIDTH = 8;
// test module variables
reg [DATA_WIDTH-1:0] i;
// Module Vars
reg clk, ena, rst;
wire data_out;
reg [DATA_WIDTH-1:0] data_in;
// Instantiate the Unit Under Test (UUT)
shift_out uut (
.clk(clk),
.da... | 7.020483 |
module shift_pload_sout (
// Clock for shifting
input clk,
// Select
input select,
// load tmp with data to shift out.
input aload,
// Data to load from
input [7:0] data,
// output bit from the left.
output sout
);
reg [8:0] tmp;
always @(posedge clk) begin
if (aload &&... | 7.29508 |
module Shift_P_Encoder16 (
input [3:0] Shift_base,
input [0:15] in,
output [3:0] out,
output valid
);
wire [3:0] En_out0, En_out1, En_out2, En_out3;
wire [3:0] En_out4, En_out5, En_out6, En_out7;
wire [3:0] En_out8, En_out9, En_out10, En_out11;
wire [3:0] En_out12, En_out13, En_out14, En_out15;
... | 7.598258 |
module PEncoder16 #(
parameter fix = 4'd0
) (
input [0:15] in,
output reg [3:0] Select
);
always @(*) begin
casex (in)
16'b0000_0000_0000_0001: Select = 4'd15 + fix;
16'b0000_0000_0000_001x: Select = 4'd14 + fix;
16'b0000_0000_0000_01xx: Select = 4'd13 + fix;
16'b0000_0000_0... | 6.948315 |
module Shift_P_Encoder8 (
input [2:0] Shift_base,
input [0:7] in,
output [2:0] out,
output valid
);
wire [2:0] En_out0, En_out1, En_out2, En_out3;
wire [2:0] En_out4, En_out5, En_out6, En_out7;
assign valid = |in;
Mux8 #(
.WIDTH(3)
) Mux8 (
.sel(Shift_base),
.in0(En_out0)... | 7.598258 |
module PEncoder8 #(
parameter fix = 3'd0
) (
input [0:7] in,
output reg [2:0] Select
);
always @(*) begin
casex (in)
8'b0000_0001: Select = 3'd07 + fix;
8'b0000_001x: Select = 3'd06 + fix;
8'b0000_01xx: Select = 3'd05 + fix;
8'b0000_1xxx: Select = 3'd04 + fix;
8'b0001_... | 7.469959 |
module LS_Encoder #(
parameter fix = 4'd0
) (
input [0:15] Load_req,
input [0:15] Store_req,
output [3:0] Select,
output valid
);
wire load_valid, store_valid;
reg [3:0] Store_Select, Load_Select;
assign load_valid = (Store_req < Load_req) & (|Load_req);
assign store_valid = (|Store_req) &... | 7.147905 |
module shift_R (
input [31:0] in,
output [31:0] shifted
);
assign shifted = in >> 32'b1;
endmodule
| 7.333365 |
module shift_ram1 (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [7:0] shiftin;
output [7:0] shiftout;
output [7:0] taps0x;
output [7:0] taps1x;
output [7:0] taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsys... | 6.87017 |
module shift_ram1 (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [7:0] shiftin;
output [7:0] shiftout;
output [7:0] taps0x;
output [7:0] taps1x;
output [7:0] taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsys... | 6.87017 |
module shift_ram2 (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [0:0] shiftin;
output [0:0] shiftout;
output [0:0] taps0x;
output [0:0] taps1x;
output [0:0] taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsys... | 6.889898 |
module shift_ram2 (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [0:0] shiftin;
output [0:0] shiftout;
output [0:0] taps0x;
output [0:0] taps1x;
output [0:0] taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsys... | 6.889898 |
module shift_ram_3x3_1bit (
D,
CLK,
CE,
SCLR,
Q
);
(* x_interface_info = "xilinx.com:signal:data:1.0 d_intf DATA" *) input [0:0] D;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
(* x_interface_info = "xilinx.com:signal:clockenable:1.0 ce_intf CE" *) input CE;
... | 8.499544 |
module shift_ram_3x3_1bit_c_shift_ram_v12_0_9 (
A,
D,
CLK,
CE,
SCLR,
SSET,
SINIT,
Q
);
input [3:0] A;
input [0:0] D;
input CLK;
input CE;
input SCLR;
input SSET;
input SINIT;
output [0:0] Q;
wire [3:0] A;
wire CE;
wire CLK;
wire [0:0] D;
wire [0:0] Q;
wire SC... | 8.499544 |
module shift_ram_3x3_8bits (
D,
CLK,
CE,
SCLR,
Q
);
(* x_interface_info = "xilinx.com:signal:data:1.0 d_intf DATA" *) input [7:0] D;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
(* x_interface_info = "xilinx.com:signal:clockenable:1.0 ce_intf CE" *) input CE;
... | 8.499544 |
module shift_ram_3x3_8bits_c_shift_ram_v12_0_9 (
A,
D,
CLK,
CE,
SCLR,
SSET,
SINIT,
Q
);
input [3:0] A;
input [7:0] D;
input CLK;
input CE;
input SCLR;
input SSET;
input SINIT;
output [7:0] Q;
wire [3:0] A;
wire CE;
wire CLK;
wire [7:0] D;
wire [7:0] Q;
wire S... | 8.499544 |
module shift_reg #(
parameter LEN = 0,
parameter INIT = 0
) (
input wire clk,
input wire i_rst,
input wire i_en,
input wire i_d,
output wire o_q,
output wire [LEN-2:0] o_par
);
reg [LEN-1:0] data;
assign o_q = data[0];
assign o_par = data[LEN-1:1];
always @(pos... | 9.26065 |
module shift_reg1 (
output reg [7:0] P1,
P2,
P3,
input [7:0] data,
input reset,
clk,
load
);
reg [7:0] memory1, memory2, memory3, memory4, memory5, memory6, memory7;
always @(posedge clk, posedge reset) begin
if (reset) begin
memory1 <= 0;
memory2 <= 0;
memory3 <= 0... | 7.098138 |
module shift_reg2 (
output reg [7:0] P1,
P2,
input [7:0] data,
input reset,
clk,
load
);
reg [7:0] memory1, memory2, memory3, memory4, memory5, memory6, memory7;
always @(posedge clk, posedge reset) begin
if (reset) begin
memory1 <= 0;
memory2 <= 0;
memory3 <= 0;
... | 7.168208 |
module shift_reg3 (
output reg [7:0] P1,
P2,
input [7:0] data,
input reset,
clk,
load
);
reg [7:0] memory1, memory2, memory3, memory4, memory5, memory6, memory7;
always @(posedge clk, posedge reset) begin
if (reset) begin
memory1 <= 0;
memory2 <= 0;
memory3 <= 0;
... | 7.193114 |
module shift_register (
S1,
S0,
D,
Dsl,
Dsr,
Q,
CLK,
CR
);
parameter N = 4; // 参数化位宽
input S1, S0; // 控制输入
input Dsl, Dsr; // 串行输入端
input CLK, CR; // 时钟及异步清零
input [N-1:0] D; // 并行置入端
output [N-1:0] Q; // 寄存器输出
reg [N-1:0] Q;
always @(posedge CLK or negedge CR)
... | 6.854847 |
module shift_register2 (
input sin,
clk,
rst,
output [7:0] PO
);
wire [8:0] Q;
wire [8:0] Q_BAR;
assign Q[8] = sin;
assign PO[0] = Q[0];
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : I0
DFF_MS_RST XX (
Q[i+1],
clk,
rst,
Q[i],
... | 6.854847 |
module shift_register2_TB ();
reg ssin;
reg cclk = 1'b1;
reg reset = 1'b0;
//Primary Output
wire [7:0] PPO;
shift_register2 CUT1 (
ssin,
cclk,
reset,
PPO
);
always #600 ssin = $random;
always #500 cclk = ~cclk;
initial begin
#12000 $stop;
end
endmodule
| 6.854847 |
module shift_register3 (
input sin,
clk,
rs,
output reg [7:0] PO
);
always @(posedge clk, posedge rs) begin
if (rs) PO <= 8'b0;
else PO <= {sin, PO[7:1]};
end
endmodule
| 6.854847 |
module shift_register3_TB ();
reg ssin;
reg cclk = 1'b1;
reg reset = 1'b0;
//Primary Output
wire [7:0] PPO;
shift_register3 CUT1 (
ssin,
cclk,
reset,
PPO
);
always #600 ssin = $random;
always #500 cclk = ~cclk;
initial begin
#12000 $stop;
end
endmodule
| 6.854847 |
module shift_register4 (
input clk,
input bit_in,
output wire [3:0] parallel_out,
output wire bit_out
);
reg [3:0] tmp = 4'b1110;
always @(posedge clk) begin
tmp <= {tmp[2:0], bit_in};
end
assign parallel_out = tmp[3:0];
assign bit_out = tmp[3];
endmodule
| 6.854847 |
module shift_register8 (
input wire clk,
input wire bit_in,
output wire bit_out,
output wire [7:0] parallel_out
);
wire out2in1;
shift_register4 inst1 (
.clk(clk),
.bit_in(bit_in),
.bit_out(out2in1),
.parallel_out(parallel_out[3:0])
);
shift_register4 inst2 (
.clk(c... | 6.854847 |
module shift_register8_ctrl (
input clk,
input rst_n,
input ren, //start read data
input men, // read finish, start move
input [79:0] dinre,
input [79:0] dinim,
output [9:0] doutre,
output [9:0] doutim
);
reg [9:0] sregre[0:7];
reg [9:0] sregim[0:7];
always @(posedge clk, negedg... | 6.854847 |
module shift_register8_ctrl_tb ();
reg clk;
reg rst_n;
reg ren;
reg men;
reg [9:0] dinre7, dinre6, dinre5, dinre4, dinre3, dinre2, dinre1, dinre0;
reg [9:0] dinim7, dinim6, dinim5, dinim4, dinim3, dinim2, dinim1, dinim0;
wire [9:0] doutre;
wire [9:0] doutim;
shift_register8_ctrl m0 (
.clk(clk),... | 6.854847 |
module shift_register8_op (
input clk,
input rst_n,
input ren,
input men,
input [9:0] dinre0, //from outside
input [9:0] dinre1, //from previous register
input [9:0] dinim0,
input [9:0] dinim1,
output [9:0] doutre,
output [9:0] doutim
);
reg [9:0] sregre[0:7];
reg [9:0] sr... | 6.854847 |
module shift_register8_tb ();
reg clk;
reg rst_n;
reg ren;
reg [9:0] dinre;
reg [9:0] dinim;
wire [9:0] doutre;
wire [9:0] doutim;
reg [2:0] sel;
shift_register8 m0 (
.clk(clk),
.rst_n(rst_n),
.ren(ren),
.dinre(dinre),
.dinim(dinim),
.doutre(doutre),
.sel(sel)... | 6.854847 |
module is a shift register with parameter special for Root Square solving.
* Inputs:
* clk: Clock signal
* reset: Reset signal
* Data_Input: Data to register
* enable: Enable input
* shift: Shift enable input
* snum: Number of shifting input
* op: Operation selector 0 -> Mult, 1 -> RS
* Outputs:
* Data_Ou... | 8.373232 |
module is a shift register with parameter.
* Inputs:
* clk: Clock signal
* reset: Reset signal
* Data_Input: Data to register
* enable: Enable input
* shift: Shift enable input
* Sync_Reset: Synchronus reset
* snum: Number of shifting input 0-> 1 shift, 1 -> 2 shift
* Outputs:
* Data_Output: Data to provide lache... | 8.373232 |
module shift_registers(
// clk1, rst,
// addr, din,
// LAD1, LAD2,
// data_from_RF_to_chip_output,
// addr_reg, din_reg, dout_for_chip
// );
// input clk1;
// input rst;
// i... | 6.854847 |
module shift_registers (
clk1,
rst,
addr,
din,
LAD1,
LAD2,
data_from_RF_to_chip_output,
addr_reg,
din_reg,
dout_for_chip
);
input clk1;
input rst;
input addr;
input din;
input LAD1;
input LAD2;
input [63:0] data_from_RF_to_chip_output;
output reg [9:0] addr_reg;... | 6.854847 |
module shift_registers_0 (
clk,
clken,
SI,
SO
);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
always @(posedge clk) begin
if (clken) shreg = {shreg[WIDTH-2:0], SI};
end
assign SO = shreg[WIDTH-1];
endmodule
| 6.854847 |
module shift_registers_1 (
clk,
clken,
SI,
SO
);
parameter WIDTH = 32;
input clk, clken, SI;
output SO;
reg [WIDTH-1:0] shreg;
integer i;
always @(posedge clk) begin
if (clken) begin
for (i = 0; i < WIDTH - 1; i = i + 1) shreg[i+1] <= shreg[i];
shreg[0] <= SI;
end
end
... | 6.854847 |
module shift_registers_addr (
input clk,
input clken,
input [17:0] SI,
output [17:0] SO
);
parameter LENGTH = 8;
reg [17:0] shreg[LENGTH-1:0];
integer i;
assign SO = shreg[LENGTH-1];
initial begin
for (i = 0; i < LENGTH; i = i + 1) shreg[i] <= 0;
end
always @(posedge clk) begin
... | 6.854847 |
module shift_register_bf (
input clk,
input clken,
input [15:0] SI,
output [15:0] SO
);
parameter LENGTH = 2;
(* shreg_extract = "yes" *) reg [15:0] shreg[LENGTH-1:0];
integer i;
assign SO = shreg[LENGTH-1];
initial begin
for (i = 0; i < LENGTH; i = i + 1) shreg[i] = 0;
end
always ... | 6.854847 |
module shift_register_1_var (
clk,
a,
d,
q
) /* synthesis syn_black_box syn_noprune=1 */;
input clk;
input [2 : 0] a;
input [0 : 0] d;
output [0 : 0] q;
// synthesis translate_off
wire \U0/i_synth/i_bb_inst/sinit ;
wire \U0/i_synth/i_bb_inst/ce ;
wire \U0/i_synth/i_bb_inst/output_net ... | 6.854847 |
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
wire [3:0] w = {KEY[3], LEDR[3], LEDR[2], LEDR[1]};
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin : mux
MUXDFF(
.clk(KEY[0]), .w(w[i]), .R(SW[i]), .E(KEY[1]), .L(KEY[2]), .Q(LEDR[i])
);... | 7.203305 |
module shift_register_24bits (
lsb,
msb,
control,
clock,
parallel_load,
parallel_read
);
input wire msb, clock;
input wire [1:0] control;
/* control
00 right shift
01 left shift
10 parallel load
*/
input wire [23:0] parallel_load;
output wire lsb;
output wire [23:0] parallel_... | 6.854847 |
module Shift_Register_256bits (
CLK,
ENABLE,
RESET,
RESET_VALUE,
IN,
OUT
);
input CLK;
input ENABLE;
input RESET;
input [255:0] RESET_VALUE;
input IN;
output OUT;
reg [255:0] saver = 0;
always @(posedge CLK) begin
if (RESET) begin
saver <= RESET_VALUE;
end else be... | 6.958616 |
module shift_register_3 (
clk,
din,
rst,
dout0,
dout1,
dout2
); //, dout3, dout4);
input [7:0] din;
input rst;
input clk;
output [7:0] dout0;
output [7:0] dout1;
output [7:0] dout2;
// output [7:0] dout3;
// output [7:0] dout4;
wire [7:0] dout0;
reg [7:0] dout1;
reg ... | 6.854847 |
module shift_register_32 (
data_bus,
en,
clear,
io,
clk,
is_left, //是否左移,左移为1,右移为0,不移动为z(位31在最左而位0在最右,与代码一致)
carry_bit //循环移位时, 将移位暂时溢出的一位通过carry_bit输出(并回送到另一端)
);
//双向32位循环移位寄存器, 循环移位时可输出溢出位
//除循环移位功能外, 其余与一般寄存器一致
//上升沿有可能同时发生输入(或复位,属于输入的特例)与移位两个操作,规定先输入,再对输入的值进行移位
//使能后,操作优先级:... | 6.854847 |
module Shift_Register_32bit (
clk,
reset,
mode,
sin,
p_in,
sout,
status
);
input clk, reset, mode, sin;
input [31:0] p_in;
output sout;
output [31:0] status;
reg [31:0] q;
wire [ 2:0] m;
//chaining 4, 8 bit shift registers
shift_register s0 (
clk,
reset,
... | 6.958616 |
module Shift_Register_4096bits (
CLK,
IN,
ENABLE,
OUT
);
input CLK;
input IN;
input ENABLE;
output reg [4095:0] OUT = 0;
always @(posedge CLK) begin
if (ENABLE) begin
OUT <= {OUT[4094:0], IN};
//OUT<={IN,OUT[4095:1]};
end else begin
OUT <= OUT;
end
end
endmodul... | 6.958616 |
module Shift_Register_40bits (
CLK,
IN,
ENABLE,
OUT
); //带有保持功能的移位寄存器
input CLK;
input IN;
input ENABLE;
output reg [39:0] OUT = 0;
always @(posedge CLK) begin
if (ENABLE) begin
OUT <= {OUT[38:0], IN};
end else begin
OUT <= OUT;
end
end
endmodule
| 6.958616 |
module Shift_Register_48bits (
CLK,
IN,
RESET,
RESET_VALUE,
OUT
);
input CLK;
input IN;
input RESET;
input [47:0] RESET_VALUE;
output OUT;
reg [47:0] data_saver = 0;
always @(posedge CLK) begin
if (RESET) begin
data_saver <= RESET_VALUE;
end else begin
data_saver ... | 6.958616 |
module shift_register_7 (
clk,
din,
rst,
dout0,
dout1,
dout2,
dout3,
dout4,
dout5,
dout6
);
input [7:0] din;
input rst;
input clk;
output [7:0] dout0;
output [7:0] dout1;
output [7:0] dout2;
output [7:0] dout3;
output [7:0] dout4;
output [7:0] dout5;
output [7... | 6.854847 |
module shift_register_8 ( //8位移动寄存器
input S1,
input S0,
input CP,
input CR,
input [7:0] D,
output reg [7:0] Q
);
reg flag = 1;
always @(negedge CP, negedge CR) begin
if (~CR) flag <= 1;
if (Q == 'b0000010) //notation blocking
flag <= 1;
else if (Q == 'b01000000) flag <=... | 6.854847 |
module shift_register_8b (
Din,
PL,
clk,
D
);
input [7:0] Din; //data-in
input PL; //parallel load
input clk;
output reg [7:0] D;
always @(negedge clk, negedge PL) begin
if (PL == 0) D <= Din;
else begin //will work when PL=1
D[0] <= 0;
D[1] <= D[0];
D[2] <= D[1]... | 6.854847 |
module shift_register_8b_TB ();
reg clk, PL;
reg [7:0] Din;
wire [7:0] D;
shift_register_8b dut (.*);
always #5 clk = ~clk;
initial begin
PL = 0;
clk = 0;
Din = 8'b01100101;
#5 PL = 1;
#100 $finish();
end
endmodule
| 6.854847 |
module shift_register_8bit #(
parameter DELAY = 10
) (
input DSA,
DSB,
CP,
MR_n,
output Q7,
Q6,
Q5,
Q4,
Q3,
Q2,
Q1,
Q0
);
reg [7:0] Q_r;
always @(posedge CP, negedge MR_n) begin
if (!MR_n) Q_r <= 8'b0;
else begin
Q_r = Q_r << 1;
Q_r[0] = DSA... | 6.854847 |
module Shift_Register_8bits (
CLK,
IN,
RESET,
ENABLE,
OUT
);
input CLK;
input IN;
input RESET; //有效时所有位置1
input ENABLE;
output reg [7:0] OUT = 0;
always @(posedge CLK or posedge RESET) begin
if (RESET) begin
OUT <= 8'b11111111;
end else begin
if (ENABLE) begin
... | 6.958616 |
module shift_regiter_8bit_tb ();
reg [7:0] parallel_load;
reg msb, clock;
reg [1:0] control;
wire lsb;
wire [7:0] parallel_read;
/* control
00 right shift
01 left shift
10 parallel load
*/
shift_register_8bits s1 (
.lsb(lsb),
.msb(msb),
.control(control),
.clock(clock),
... | 7.445807 |
module shift_register_BCD_6 (
output reg [3:0] BCD_5,
output reg [3:0] BCD_4,
output reg [3:0] BCD_3,
output reg [3:0] BCD_2,
output reg [3:0] BCD_1,
output reg [3:0] BCD_0,
input [3:0] d_5,
input [3:0] d_4,
input [3:0] d_3,
input [3:0] d_2,
input [3:0] d_1,
input [3:0] d... | 6.854847 |
module shift_register_enable #(
parameter N = 4
) (
input clk,
reset_n,
input SI,
input enable,
output [N - 1:0] Q //If we care about the content
//output SO
);
reg [N - 1:0] Q_reg, Q_next;
always @(posedge clk) begin
Q_reg <= Q_next;
end
// Next state logic
always... | 6.854847 |
module shift_register_er (
input clk,
input reset,
input enable,
input d,
output reg [8:0] q
);
always @(posedge reset, posedge clk) begin
if (reset) q <= 0;
else if (enable) q[8:0] <= {d, q[8:1]};
end
endmodule
| 6.854847 |
module shift_register_fifo (
clk,
rst,
data_in,
push,
pop,
empty,
full,
data_out
);
parameter WIDTH = 8, DEPTH = 8, CNTWID = $clog2(DEPTH + 1), IDXWID = $clog2(DEPTH);
input clk, rst, push, pop;
input [WIDTH-1:0] data_in;
output empty, full;
output [WIDTH-1:0] data_out;
re... | 6.854847 |
module shift_register_fifo (
clk,
rst,
data_in,
push,
pop,
empty,
full,
data_out
);
parameter WIDTH = 8, DEPTH = 8, CNTWID = $clog2(DEPTH + 1), IDXWID = $clog2(DEPTH);
input clk, rst, push, pop;
input [WIDTH-1:0] data_in;
output empty, full;
output [WIDTH-1:0] data_out;
(*... | 6.854847 |
module shift_register_group_18_16_1 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_1 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
end else if (enable) begin
shift_registers_0 <= in;
end
... | 6.854847 |
module shift_register_group_18_16_10 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
inpu... | 6.854847 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_group_18_16_14 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
inpu... | 6.854847 |
module shift_register_unit_18_14 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_group_18_16_18 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
inpu... | 6.854847 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_group_18_16_3 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_3 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
sh... | 6.854847 |
module shift_register_group_18_16_6 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input... | 6.854847 |
module shift_register_unit_18_6 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers_... | 6.854847 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_14 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_3 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
sh... | 6.854847 |
module shift_register_unit_18_6 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers_... | 6.854847 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_14 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
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