code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module shl2_32b (
d_in,
d_out
);
input [31:0] d_in;
output [31:0] d_out;
assign d_out = d_in << 2;
endmodule
| 6.886464 |
module shl32 (
input wire [31 : 0] a,
input wire carry_in,
output wire [31 : 0] amul2,
output wire carry_out
);
assign amul2 = {a[30 : 0], carry_in};
assign carry_out = a[31];
endmodule
| 7.00492 |
module shl8 (
input [7 : 0] a,
input [2 : 0] shift,
output [7 : 0] res,
output carry
);
assign {carry, res} = (shift == 3'b000) ? {1'b0, a} :
(shift == 3'b001) ? {a[7 : 0], {1'b0}}:
(shift == 3'b010) ? {a[6 : 0], {2'b0}}:
(shift =... | 6.543543 |
module shl_32_bit (
input wire [31:0] data_in,
input wire [31:0] num_shifts,
output wire [31:0] out
);
assign out[31:0] = data_in << num_shifts;
endmodule
| 7.209287 |
module
/////////////////////////////////////////////////////////////////
module shortest_path_displayer(
input clk_25MHz, // clock for memory ip
input [9:0] h_cnt,
input [9:0] v_cnt,
output [11:0] pixel_arrow,
output [9:0] query_r,
output [9:0] query_c,
input [2:0] sp_dir
);
assign query_r = ... | 6.558648 |
module shortfifo #(
parameter WIDTH = 32
) (
input clk,
input rst,
input [WIDTH-1:0] datain,
output [WIDTH-1:0] dataout,
input read,
input write,
input clear,
output reg full,
output reg empty,
output reg [4:0] space,
output reg [4:0] occupied
);
reg [3:0] a;
genvar ... | 8.123305 |
module ShouldBranch (
isBne,
isBeq,
isBranchEqual,
shouldBranch
);
input wire isBne;
input wire isBeq;
input wire isBranchEqual;
output reg shouldBranch;
always @(*) begin
if (isBeq && isBranchEqual || isBne && !isBranchEqual) begin
shouldBranch = 1;
end else begin
shouldB... | 6.641824 |
module Show (
Sel,
PC,
NextPC,
rs,
ReadData1,
rt,
ReadData2,
Result,
DB,
Out
);
input [1:0] Sel;
input [4:0] rs, rt;
input [31:0] PC, NextPC, ReadData1, ReadData2, Result, DB;
output reg [15:0] Out;
always @(*) begin
case (Sel)
0: begin
Out[15:8] = PC... | 7.785981 |
module show7segment (
input clk_100M,
input [7:0] Enable,
input [31:0] in,
output reg [7:0] an,
output reg [6:0] seg
);
reg clk_500, en;
reg [ 2:0] address;
reg [17:0] cnt;
reg [ 3:0] x;
wire [3:0] bcdin7, bcdin6, bcdin5, bcdin4, bcdin3, bcdin2, bcdin1, bcdin0;
assign {bcdin0, bcdin1, ... | 6.986589 |
module showboard_statemachine (
input rst_n
, input clk
, input display_en
, input [15:0] display_data_i
, output reg disply_r_en
, output reg [2:0] display_addr
, output reg [7:0] row_addr
, output reg [15:0] display_data_o
, output reg display_finish
);
reg [2:0] state;
reg [2:... | 7.387149 |
module ShowCnt (
input clk,
input rst_n,
input cnt_en,
output reg [7:0] cnt_data
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) //
cnt_data <= 8'h90;
else if (cnt_en) begin
if (cnt_data == 8'h99) cnt_data <= 8'h00; //990ʼ
else if (cnt_data[3:0] == 4'h9) cnt_... | 7.476807 |
module ShowCode (
input switch,
input [3:0] med,
input [3:0] low,
output reg [3:0] sel = 4'b1101,
output reg [7:0] data
);
always @(*) begin
if (switch == 1) sel <= 4'b1101;
else sel <= 4'b1110;
end
//8'b 1 1 1 1 _ 1 1 1 1;
// a b c d e f g h
always @(med or low)
if (s... | 6.547358 |
module ShowControl (
CLK,
nRST,
KEY_Value,
Value_en,
SEL,
SEG
);
input CLK;
input nRST;
input Value_en; //数码管使能端,使能信号从按键模块中来
input [3:0] KEY_Value;
output reg [7:0] SEL; //位选
output reg [7:0] SEG; //段选
reg clock_1k;
reg [14:0] cnt;
reg [3:0] data_tmp;
reg [31:0] disp_dat... | 7.767498 |
module showdigit (
clk0
, _num
//,dot_position
, digit
, DIG
, dot
);
// input & output
input clk0;
input [15:0] _num;
//input[1:0] dot_position;
output reg [7:1] digit;
output reg [3:0] DIG;
output reg dot;
// number setting
wire [3:0] num[3:0];
assign num[3] = _num[3:0];
... | 7.464833 |
module ShowDiv ( //50MHz2HzƵ
input clk, //50MHzʱ
input rst_n, //ʼ
output reg cnt_en //ź
);
reg [24:0] cnt_div; //50MHzʱ
always@(posedge clk or negedge rst_n) //clkЧrst_n½Ч
begin
if (~rst_n) cnt_div <= 25'h0;
else if (cnt_div == 25'd24_999_999) cnt_div <= 25'h0;
else c... | 7.622339 |
module shownum (
input wire [31:0] N, //ʾֵ8421
input wire Clk, //ɨʱ
output reg [ 6:0] OUT, //ʾ
output reg [ 7:0] AN, //ʾ
output wire DP //Сλ
);
reg [2:0] s; //ɨ
reg [3:0] Number; //ǰʾֵ8421
initial begin
s = 0;
Number = 0;
end
assign DP = 1; //δõСλ,Сλ... | 6.761055 |
module shownumber (
input i_Clk,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
input [32:0] num
);
wire [3:0] d0 = num % 10;
wire [3:0] d1 = (num / 10) % 10;
wire [3:0] d2 = (num / 100) % 10;
wire [3:0] d3 = (nu... | 8.019625 |
module showpic_tb ();
reg CLK100MHZ = 0;
reg BTNU = 0;
wire [3:0] VGA_R;
wire [3:0] VGA_G;
wire [3:0] VGA_B;
wire VGA_HS;
wire VGA_VS;
initial forever #1 CLK100MHZ = ~CLK100MHZ;
test1_showpic uut (
CLK100MHZ,
1,
BTNU,
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS... | 7.108377 |
module ShowView (
input clk,
input [5:0] uTot,
input [5:0] uCur,
input [5:0] uWat,
output [7:0] ySEG_,
output [7:0] yAN_
);
wire [2:0] xPos;
wire [3:0] xVal;
wire [4:0] xMem [7:0];
_disp_counter vC8 (
clk,
xPos
);
_disp_decimal vDecTot (
uTot,
xMem[7],
x... | 7.27332 |
module _disp_counter (
input clk,
output reg [2:0] yVal = 3'b000
);
always @(posedge clk) yVal <= yVal + 1;
endmodule
| 7.192933 |
module _disp_decimal (
input [5:0] uVal,
output [4:0] yE1,
output [4:0] yE2
);
assign yE1 = (uVal == 55) ? 5'h1f :
(uVal == 56) ? 8 :
(uVal == 57) ? 10 :
(uVal == 58) ? 12 :
(uVal == 59) ? 14 :
(uVal == 60) ? 15 :
... | 7.455954 |
module _disp_pattern (
input [4:0] uVal,
output reg [7:0] ySEG_
);
always @(uVal)
case (uVal)
'b00000: ySEG_ <= 'b11000000;
'b00001: ySEG_ <= 'b11111001;
'b00010: ySEG_ <= 'b10100100;
'b00011: ySEG_ <= 'b10110000;
'b00100: ySEG_ <= 'b10011001;
'b00101: ySEG_ <= 'b100100... | 6.730357 |
module _disp_position (
input [2:0] uPos,
output [7:0] yAN_
);
assign yAN_ = ~(8'b1 << uPos);
endmodule
| 7.033632 |
module show_carry (
input carry,
output reg [6:0] display
);
always @(*)
case (carry)
1'b1: display = ~7'b0000110;
1'b0: display = ~7'b0111111;
default: display = ~7'b0000000;
endcase
endmodule
| 7.591902 |
module show_carry_s (
input carry,
output reg [6:0] display,
input clock
);
//always @(*)
always @(posedge clock)
case (carry)
1'b1: display = ~7'b0000110;
1'b0: display = ~7'b0111111;
default: display = ~7'b0000000;
endcase
endmodule
| 6.89738 |
module show_mode (
input clk, //Ƶǰ
input [2:0] mode,
input [31:0] pc,
input [31:0] pc_next,
input [4:0] rs_ad,
input [31:0] rs_data,
input [4:0] rt_ad,
input [31:0] rt_data,
input [31:0] alu_result,
input [31:0] db,
input [2:0] state,
output reg [7:0] output1,
output... | 7.563526 |
module SHOW_ON_LED (
input clk,
input [5:0] inst_op,
input [31:0] alu_r,
input [15:0] button,
output [15:0] led
);
wire run;
reg [15:0] alu_result;
assign run = button[14];
assign led = run ? alu_result : button;
always @(posedge clk) alu_result <= (inst_op == 6'b0 && run == 1'b1) ? alu... | 6.721266 |
module show_score (
clk,
rst_n,
col_addr_sig,
row_addr_sig,
levelup_sig,
score_out_c
);
parameter bling = 26'd12_500_000;
input clk;
input rst_n;
input [10:0] col_addr_sig;
input [10:0] row_addr_sig;
input levelup_sig;
output score_out_c;
reg [14:0] addra; //0518
wire [17:0]... | 7.136768 |
module show_seg (
input clk,
input rst,
input [31:0] add_num,
output reg [7:0] seg_code,
output reg [3:0] an
);
parameter T100MS = 27'd10_000_000; // 0.1s
parameter T1MS = 14'd10_000;
reg [26:0] cnt;
reg [7:0] add_ge, add_shi, add_bai;
always @(posedge clk or posedge rst)
if (rst) c... | 7.101012 |
module outputs rgb of white when the current x and y coords fall between
* the x and y origin and the x and y limit (i.e. within the square delimitted by them).
*
* SW17 toggles between colors changing and a `reset` state (which is all white).
* SW16-SW14 control the speed at which the square moves accross the scre... | 10.428958 |
module shr32 (
input wire [31 : 0] a,
input wire carry_in,
output wire [31 : 0] adiv2,
output wire carry_out
);
assign adiv2 = {carry_in, a[31 : 1]};
assign carry_out = a[0];
endmodule
| 6.782365 |
module top (
input wire I,
input wire C,
output wire O
);
reg [7:0] shift_register;
always @(posedge C) shift_register <= {shift_register[6:0], I};
assign O = shift_register[7];
endmodule
| 7.233807 |
module $__SHREG_DFF_P_(input C, D, output Q);
parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
always @(posedge C)
r <= { r[DEPTH-2:0], D };
assign Q = r[DEPTH-1];
endmodule
| 7.147104 |
module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
always @(posedge C)
r <= { r[DEPTH-2:0], D };
assign Q = r[L];
endmodule
| 7.306557 |
module shreg_ff #(
parameter WIDTH = 32,
parameter DEPTH = 2, // Min. 2; adds FFs
parameter INIT = 0
) (
input CLK,
input [WIDTH-1:0] i,
input en,
rst,
output reg [WIDTH-1:0] o = INIT
);
genvar j;
wire [3:0] A = DEPTH - 2;
wire [WIDTH-1:0] shreg_out;
generate
for (j = 0... | 7.002726 |
module shr_32_bit (
input wire [31:0] data_in,
input wire [31:0] num_shifts,
output wire [31:0] out
);
assign out[31:0] = data_in >> num_shifts;
endmodule
| 7.249927 |
module wrram (
input clk,
input rst,
input Rx_done,
input debug_en_i,
input [7:0] rx_Data,
output reg req_o,
output reg wrramdone,
output reg rstflag,
output reg zflag,
output reg [31:0] w_addr,
output reg [31:0] w_data
);
//assign req_o = (rst == 1'b1 && debug_en_i == 1'... | 6.86096 |
module HOUR_BEGIN ( //㱨ʱƵ
input clk,
input CLK_1HZ,
input nCLR,
input [4:0] Hour_Audio,
output reg H_AUDIO
);
wire CLK_500HZ;
Divider_XHZ divider_500HZ (
nCLR,
clk,
CLK_500HZ
);
defparam divider_500HZ.OUT_Freq = 500;
reg [4:0] ... | 6.995828 |
module counter_10 (
input clk,
nCLR,
EN,
output reg [3:0] Q
);
always @(posedge clk or negedge nCLR or negedge EN) begin
if (~nCLR) begin
Q <= 4'b0000;
end else begin
if (~EN) Q <= Q;
else if (Q == 4'b1001) Q <= 4'b0000;
else Q <= Q + 1'b1;
end
end
endmodule
| 7.079423 |
module counter_6 (
input clk,
nCLR,
EN,
output reg [3:0] Q
);
always @(posedge clk or negedge nCLR or posedge EN) begin
if (~nCLR) begin
Q <= 4'b0000;
end else begin
if (~EN) Q <= Q;
else if (Q == 4'b0101) Q <= 4'b0000;
else Q <= Q + 1'b1;
end
end
endmodule
| 6.768667 |
module Divider_XHZ ( //Ƶʹʱ趨
input nCLR,
input CLK_100M,
output reg CLK_1HZ //Ĭ1HZƵ
);
parameter N = 27;
parameter CLK_Freq = 100000000;
parameter OUT_Freq = 1;
reg [N-1:0] Count_DIV;
always @(posedge CLK_100M or negedge nCLR) begin
if(!nCLR) //͵ƽ
begin
CLK_1HZ <= 0... | 6.943071 |
module is the logic to pop the
function stack to the output queue. Addition and subtraction are lowest
precedence, and will pop everything off the stack. Multiplication and
division will only pop off other multiplication and division operators,
stopping at the first addition or subtraction encountered. The euqual... | 7.666008 |
module show16withdps (
input CLK,
input NEWNUM,
input [15:0] NUM,
input DP3,
input DP2,
input DP1,
input DP0,
output [7:0] SEG_OUT,
output [3:0] DIGIT_OUT
);
function [6:0] HEX2LED;
input [3:0] HEX;
begin
case (HEX)
4'b0001: HEX2LED = 7'b1111001; //1
... | 7.426205 |
module performs shifting left of the mantisa by given amount
* It also reduce the width of resulting vector from the extended
* size used in mantisa addition to IEEE size. Both sizes
* are parametrized to allow flexibility
*/
module sh_logic_left(m, sh, out);
parameter WIDTH = 1;
parameter WIDTH_OUT = 1;
... | 7.187778 |
module performs right shift by given amount
* when enable bit is high
*/
module sh_logic_right(d, shamt, en, out);
input [24:0] d;
input [4:0] shamt;
input en;
output [24:0] out;
assign out = (en == 1'b1) ? d >> shamt : d;
endmodule
| 8.066004 |
module SI5324_AutoConfig #(
parameter clkFreq = 100_000_000,
parameter I2CFreq = 100_000
) (
input clk,
input rst_n,
input RECONFIG,
output scl,
inout sda
);
localparam IDLE = 3'd0;
localparam CHECK = 3'd1;
localparam START = 3'd2;
localparam WAIT_DONE = 3'd3;
localparam CLR... | 7.322242 |
module si570_controller (
iCLK, // system clock 50mhz
iRST_n, // system reset
iStart, // system set
iFREQ_MODE, //clock frequency mode 000:100Mhz, 001: 125Mhz, 010:156.25Mhz, 011:250Mhz, 100:312.5Mhz , 101:322.26Mhz , 110:644.53Mhz ,111:100Mhz
oController_Ready, // high for si570 control... | 7.066693 |
module SI571 (
input CLKN,
input CLKP,
output clkp_out,
output clkn_out
);
// pin CLKN is MGTREFCLK1N_116 bank 116 bus_bmb7_U5[0] F5
// pin CLKP is MGTREFCLK1P_116 bank 116 bus_bmb7_U5[1] F6
assign clkp_out = CLKP;
assign clkn_out = CLKN;
endmodule
| 6.59516 |
module si57x_interface_tb;
// Clock and resets
wire sys_clk;
wire sys_rstn;
clk_rst cmp_clk_rst (
.clk_sys_o (sys_clk),
.sys_rstn_o(sys_rstn)
);
// DUT
wire ext_wr = 1'b0;
wire [37:0] ext_rfreq_value = 'h0;
wire [6:0] ext_n1_value = 'h0;
wire [2:0] ext_hs_value = 'h0;
wire scl_pad_... | 6.888439 |
module sib_selector (
input [39:0] instr_buf,
input [ 2:0] sib_sel,
output [ 7:0] sib
);
wire [7:0] byte7, byte3, byte4, byte5, byte6;
wire sib_sel0, sib_sel1, sib_sel2;
wire [7:0] out1m;
assign byte3 = instr_buf[39:32];
assign byte4 = instr_buf[31:24];
assign byte5 = instr_buf[23:16];
ass... | 6.697553 |
module envelope_gen (
input clk,
input rst,
input clk_1mhz_ph1_en,
input i_gate,
input [3:0] i_attack,
input [3:0] i_decay,
input [3:0] i_sustain,
input [3:0] i_release,
output [7:0] o_envelope
);
function [16:0] map_attack;
input [3:0] value;
reg [16:0] res;
case (valu... | 6.61754 |
module shifterbit (
OUT,
IN,
LOAD,
SHIFT,
LOAD_N,
CLK,
RESET_N
);
input IN, LOAD, SHIFT, LOAD_N, CLK, RESET_N;
output OUT;
wire muxconnector, toDflip;
mux2to1 M1 (
.x(OUT),
.y(IN),
.s(SHIFT),
.m(muxconnector)
);
mux2to1 M2 (
.x(LOAD),
.y(mux... | 6.966603 |
module mux2to1 (
x,
y,
s,
m
);
input x; //selected when s is 0
input y; //selected when s is 1
input s; //select signal
output m; //output
assign m = s & y | ~s & x;
// OR
// assign m = s ? y : x;
endmodule
| 7.107199 |
module flipflop (
d,
reset_n,
clk,
q
);
input d, reset_n, clk;
output q;
reg q;
always @(posedge clk) begin
if (reset_n == 1'b0) q <= 0;
else q <= d;
end
endmodule
| 6.626138 |
module, to display score on the board
module hexdisplay(hex_digit, OUT);
input [3:0] hex_digit;
output reg [7:0] OUT;
always @(*)
begin
case(hex_digit[3:0])
4'b0000: OUT = 7'b1000000;
4'b0001: OUT = 7'b1111001;
4'b0010: OUT = 7'b0100100;
4'b0011: OUT = 7'b0110000;
4'b0100: OUT = 7'b0011001... | 8.256954 |
module sidetone (
input clock, // 122.88MHz
input [11:0] tone_freq,
input [ 7:0] sidetone_level, // 0 to 0x7F since doing signed multiply
input CW_PTT,
input [15:0] profile,
output signed [15:0] C122_sidetone
);
reg sidetone_cl... | 7.556914 |
module side_ch_counter #(
// parameter integer TSF_TIMER_WIDTH = 64, // according to 802.11 standard
// parameter integer GPIO_STATUS_WIDTH = 8,
// parameter integer RSSI_HALF_DB_WIDTH = 11,
// parameter integer C_S_AXI_DATA_WIDTH = 32,
// parameter integer IQ_DATA_WIDTH = 16,
// parameter inte... | 8.677872 |
module side_ch_counter_event_cfg #(
// parameter integer TSF_TIMER_WIDTH = 64, // according to 802.11 standard
parameter integer GPIO_STATUS_WIDTH = 8,
parameter integer RSSI_HALF_DB_WIDTH = 11,
parameter integer C_S_AXI_DATA_WIDTH = 32
// parameter integer IQ_DATA_WIDTH = 16,
// parameter int... | 8.677872 |
module template
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
`timescale 1 ns / 1 ps
module side_ch_s_axis #
(
parameter integer C_S_AXIS_TDATA_WIDTH = 64,
parameter integer MAX_NUM_DMA_SYMBOL = 8192,
parameter integer MAX_BIT_NUM_DMA_SYMBOL = 14
)
(
input wire s_axis_endless_mode,
... | 7.667682 |
module sid_bus_if #(
parameter integer AW = 5,
// auto-set
parameter integer AL = AW - 1
) (
// Pads
inout wire [AL:0] pad_a,
inout wire [ 7:0] pad_d,
inout wire pad_r_wn,
inout wire pad_csn,
inout wire pad_phi2,
// Internal bus
output wire [AL:0] bus_a... | 9.707404 |
module sid_bus_if_debounce #(
parameter integer BIDIR = 0
) (
inout wire pad,
output wire i,
input wire o,
input wire oe,
input wire clk,
input wire rst
);
wire raw_i;
reg [2:0] state;
if (BIDIR)
SB_IO #(
.PIN_TYPE (6'b1101_00), // Reg input, Reg+RegOE output
... | 7.132887 |
module pwm_sddac (
input clk_i,
input reset,
input [msbi_g:0] dac_i,
output dac_o
);
parameter msbi_g = 9;
reg [msbi_g+2 : 0] sig_in = 0;
reg dac_o_int;
always @(posedge clk_i) begin
// Disabling reset as the DC offset causes a noticable ... | 6.828612 |
module pwm_sdadc (
input clk, // main clock signal (the higher the better)
input reset,
output reg [7:0] ADC_out, // binary input of signal to be converted
input ADC_in // "analog" paddle input pin
);
// Dummy implementation (no real A/D conversion performed)
always @(posedge clk)
if (ADC_in... | 8.03027 |
module sid_filter (
input clk,
input reset,
input [3:0] resonance,
input [10:0] fc,
input [11:0] in,
input high_pass,
input low_pass,
input band_pass,
output reg [11:0] out
);
reg signed [31:0] Vbp;
reg signed [31:0] Vhp;
reg signed [31:0] Vlp;
reg signed [17:0] w0;
reg sig... | 6.524671 |
module SiEi7 (
input [ 7:0] x,
input [ 7:0] y,
output [15:0] z
);
wire [ 7:0] part1 = y & {8{x[0]}};
wire [ 7:0] part2 = (y & {8{x[1]}});
wire [ 7:0] part3 = (y & {8{x[2]}});
wire [ 7:0] part4 = (y & {8{x[3]}});
wire [ 7:0] part5 = (y & {8{x[4]}});
wire [ 7:0] part6 = (y & {8{x[5]}});
wir... | 6.652789 |
module sieteSegmentos (
input [3:0] in,
output [7:0] an,
output [6:0] a_to_g
);
//Tabla para realizar la decodificacion de hex a 7-seg.
assign a_to_g= (in==0)? 7'b000_0001:
(in==1)? 7'b100_1111:
(in==2)? 7'b001_0010:
(in==3)? 7'b000_0110:
... | 7.329612 |
module AsyncResetRegVec_w1_i0( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29390.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29391.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29392.4]
inpu... | 6.68936 |
module AsyncValidSync( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29752.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29753.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29754.4]
output io_ou... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29798.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29799.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@... | 6.605499 |
module AsyncValidSync_1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29814.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29815.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29816.4]
input io_... | 6.70336 |
module AsyncValidSync_2( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29950.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29951.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29952.4]
input io_... | 6.70336 |
module SynchronizerShiftReg_w48_d1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@30212.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@30213.4]
input [47:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@30215.4]... | 6.820992 |
module LevelGateway( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@78969.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@78970.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@78971.4]
input io_inter... | 7.384159 |
module IntSyncCrossingSource( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@110135.2]
input auto_in_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@110138.4]
output auto_out_sync_0 // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@110... | 6.689384 |
module SynchronizerShiftReg_w43_d1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@112423.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@112424.4]
input [42:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@112426... | 6.820992 |
module SynchronizerShiftReg_w55_d1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@192284.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@192285.4]
input [54:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@192287... | 6.820992 |
module SynchronizerShiftReg_w12_d1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@193779.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@193780.4]
input [11:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@193782... | 6.820992 |
module SynchronizerShiftReg_w1_d3( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@210445.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@210446.4]
input io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@210448.4]
... | 6.820992 |
module IntSyncCrossingSink( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@210461.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@210462.4]
input auto_in_sync_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@210464.4]
... | 6.689384 |
module IntSyncCrossingSink_1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@210489.2]
input auto_in_sync_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@210492.4]
input auto_in_sync_1, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fi... | 6.689384 |
module IntSyncCrossingSink_2( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@210505.2]
input auto_in_sync_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@210508.4]
output auto_out_0 // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@210... | 6.689384 |
module AsyncResetRegVec_w2_i0( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@219820.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@219821.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@219822.4]
inp... | 6.68936 |
module IntSyncCrossingSource_2( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@219853.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@219854.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@219855.4]
in... | 6.689384 |
module IntSyncCrossingSource_3( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@219910.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@219911.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@219912.4]
in... | 6.689384 |
module IsoZero ( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@231367.2]
input io_in, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@231370.4]
input io_iso, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@231370.4]
output io_out ... | 6.599484 |
module SynchronizerShiftReg_w80_d1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@233373.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@233374.4]
input [79:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@233376... | 6.820992 |
module IntSyncCrossingSource_4( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@234716.2]
input auto_in_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@234719.4]
input auto_in_1, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@234719... | 6.689384 |
module DeglitchShiftRegister( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@235016.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@235017.4]
input io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@235019.4]
ou... | 7.512449 |
module SynchronizerShiftReg_w2_d3( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@235154.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@235155.4]
input [1:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@235157.4... | 6.820992 |
module IntSyncCrossingSink_4( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@235170.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@235171.4]
input auto_in_sync_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@235173.4... | 6.689384 |
module SynchronizerShiftReg_w32_d3( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@265360.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@265361.4]
input [31:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@265363... | 6.820992 |
module SynchronizerShiftReg_w4_d3( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@275352.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@275353.4]
input [3:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@275355.4... | 6.820992 |
module IntSyncCrossingSink_12( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@280223.2]
input auto_in_sync_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@280226.4]
input auto_in_sync_1, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.f... | 6.689384 |
module AsyncResetRegVec_w1_i0( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29020.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29021.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29022.4]
inpu... | 6.68936 |
module AsyncValidSync( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29382.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29383.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29384.4]
output io_ou... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29428.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29429.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@... | 6.605499 |
module AsyncValidSync_1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29444.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29445.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29446.4]
input io_... | 6.70336 |
module AsyncValidSync_2( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29580.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29581.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29582.4]
input io_... | 6.70336 |
module SynchronizerShiftReg_w48_d1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29842.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29843.4]
input [47:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@29845.4]... | 6.820992 |
module LevelGateway( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@76444.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@76445.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@76446.4]
input io_inter... | 7.384159 |
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