code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module shift_register_unit_18_3 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
sh... | 6.854847 |
module shift_register_unit_18_6 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers_... | 6.854847 |
module shift_register_group_18_910 (
input clk,
input enable,
input [17:0] in_0,
output [17:0] out_0,
input [17:0] in_1,
output [17:0] out_1,
input [17:0] in_2,
output [17:0] out_2,
input [17:0] in_3,
output [17:0] out_3,
input [17:0] in_4,
output [17:0] out_4,
input ... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_line #(
parameter TOTAL_TAPS = 9,
parameter BITS_PER_TAP = 8,
parameter TOTAL_BITS = 9 * 8
) (
// Clock
input wire clk,
// Reset
input wire rst,
// Inputs Streaming
input wire signed [BITS_PER_TAP - 1:0] i_value,
// clock in the data
input wire i_... | 6.854847 |
module shift_register_load #(
parameter N = 4
) (
input clk,
input SI,
input [N - 1:0] I,
input load,
input reset_n,
output [N - 1:0] Q, //If we care about the content
output SO
);
reg [N - 1:0] Q_reg, Q_next;
always @(posedge clk, negedge reset_n) begin
if (!reset_n) Q_reg <=... | 6.854847 |
module Shift_Register_N_bits #(
parameter WIDTH = 16
) (
CLK,
ENABLE,
RESET,
RESET_VALUE,
IN,
OUT
);
input CLK;
input ENABLE;
input RESET;
input [WIDTH-1:0] RESET_VALUE;
input IN;
output OUT;
reg [WIDTH-1:0] saver = 0;
always @(posedge CLK) begin
if (RESET) begin
... | 6.958616 |
module shift_register_TB ();
reg ssin;
reg cclk = 1'b1;
//Primary Output
wire [7:0] PPO;
shift_register CUT1 (
ssin,
cclk,
PPO
);
always #600 ssin = $random;
always #500 cclk = ~cclk;
initial begin
#12000 $stop;
end
endmodule
| 6.854847 |
module shift_register_testbench ();
// Generate 100 MHz clock.
reg clk = 0;
always #(`CLK_PERIOD / 2) clk = ~clk;
// I/O of shift register.
reg [`SHIFT_REGISTER_WIDTH-1:0] signal_in;
reg shift_pulse;
wire [`SHIFT_REGISTER_PRODUCT-1:0] signal_out;
shift_register #(
.DEPTH(`SHIFT_REGISTER_DEPTH),
... | 6.854847 |
module shift_register_top (
clk,
rst,
start,
push,
pop,
data_in,
empty,
full,
data_out,
prop_signal
);
parameter WIDTH = `WIDTH, DEPTH = `DEPTH;
input clk, rst, start, push, pop;
input [WIDTH-1:0] data_in;
output empty, full, prop_signal;
output [WIDTH-1:0] data_out;
... | 6.854847 |
module shift_register_unit_12 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else i... | 6.854847 |
module shift_register_unit_18_1 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
end else if (enable) begin
shift_registers_0 <= in;
end
... | 6.854847 |
module shift_register_unit_18_10 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_14 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_18 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers... | 6.854847 |
module shift_register_unit_18_3 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 18'd0;
sh... | 6.854847 |
module shift_register_unit_18_6 (
input clk,
input reset,
input enable,
input [17:0] in,
output [17:0] out
);
reg [17:0] shift_registers_0;
reg [17:0] shift_registers_1;
reg [17:0] shift_registers_2;
reg [17:0] shift_registers_3;
reg [17:0] shift_registers_4;
reg [17:0] shift_registers_... | 6.854847 |
module shift_register_unit_1_2 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_registers_1 <= 1'd0;
end else ... | 6.854847 |
module shift_register_unit_1_3 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
reg [0:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_reg... | 6.854847 |
module shift_register_vector #(
parameter WIDTH = 8,
parameter DEPTH = 3
) (
input clk,
input [WIDTH-1:0] data_in,
output [WIDTH-1:0] data_out
);
reg [WIDTH*DEPTH-1:0] s_reg;
always @(posedge clk) begin
s_reg <= {s_reg[WIDTH*(DEPTH-1)-1:0], data_in};
end
assign data_out ... | 6.854847 |
module shift_reg_1024 #(
parameter size = 1023
) (
shift_in,
clk,
clr,
shift_out
);
// Port Declaration
input shift_in;
input clk;
input clr;
output shift_out;
reg [size:0] shift; // shift register
always @(posedge clk or posedge clr) begin
if (clr) shift = 0;
else shift ... | 7.951929 |
module shift_reg_128bits (
clk,
reset,
prev_data,
data_in,
len_in,
enable,
prev_len,
data_out,
data_len
);
input clk, reset;
input enable; // enable means lower half of previous is full
input [127:0] prev_data;
input [31:0] data_in;
input [5:0] len_in;
input [7:0] prev_... | 7.067863 |
module shift_reg_1440_tap3 (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [31:0] shiftin;
output [31:0] shiftout;
output [31:0] taps0x;
output [31:0] taps1x;
output [31:0] taps2x;
`ifndef ALTERA_RESERVED_QIS... | 6.685864 |
module shift_reg_1440_tap3 (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [31:0] shiftin;
output [31:0] shiftout;
output [31:0] taps0x;
output [31:0] taps1x;
output [31:0] taps2x;
`ifndef ALTERA_RESERVED_QIS... | 6.685864 |
module shift_reg_1440_tap5 (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x,
taps3x,
taps4x
);
input aclr;
input clken;
input clock;
input [31:0] shiftin;
output [31:0] shiftout;
output [31:0] taps0x;
output [31:0] taps1x;
output [31:0] taps2x;
o... | 6.685864 |
module shift_reg_1440_tap5 (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x,
taps3x,
taps4x
);
input aclr;
input clken;
input clock;
input [31:0] shiftin;
output [31:0] shiftout;
output [31:0] taps0x;
output [31:0] taps1x;
output [31:0] taps2x;
o... | 6.685864 |
module shift_reg_256bits (
clk,
reset,
prev_data,
data_in,
len_in,
enable,
prev_len,
data_out,
data_len
);
input clk, reset;
input enable; // enable means lower half of previous is full or last ones
input [255:0] prev_data;
input [31:0] data_in;
input [5:0] len_in;
inpu... | 6.790413 |
module shift_reg_4608 #(
parameter size = 4607
) (
shift_in,
clk,
clr,
shift_out
);
// Port Declaration
input shift_in;
input clk;
input clr;
output shift_out;
reg [size:0] shift; // shift register
always @(posedge clk) begin
if (clr) shift = 0;
else shift = {shift[size-1... | 8.248595 |
module shift_reg_512bits (
clk,
reset,
state,
enable,
data_in,
data_out
);
input clk, reset, enable;
input [2:0] state;
input [255:0] data_in;
output [511:0] data_out;
reg [511:0] data_out_reg;
always @(posedge clk) begin
if (reset) begin
data_out_reg <= 512'd0;
end ... | 6.808407 |
module shift_reg_576 #(
parameter size = 575
) (
shift_in,
clk,
clr,
shift_out
);
// Port Declaration
input shift_in;
input clk;
input clr;
output shift_out;
reg [size:0] shift; // shift register
always @(posedge clk or posedge clr) begin
if (clr) shift = 0;
else shift = ... | 7.960554 |
module shift_reg_8 #(
parameter size = 7
) (
shift_in,
clk,
clr,
shift_out
);
// Port Declaration
input shift_in;
input clk;
input clr;
output shift_out;
reg [size:0] shift; // shift register
always @(posedge clk or posedge clr) begin
if (clr) shift = 0;
else shift = {shi... | 7.622312 |
module shift_reg_8192 #(
parameter size = 8191
) (
shift_in,
clk,
clr,
shift_out
);
// Port Declaration
input shift_in;
input clk;
input clr;
output shift_out;
reg [size:0] shift; // shift register
always @(posedge clk) begin
if (clr) shift = 0;
else shift = {shift[size-1... | 8.502034 |
module shift_reg_8b (
input CLRb,
input [1:0] s,
input CLK,
input SDL,
input SDR,
input [7:0] D,
output [7:0] Q
);
reg [7:0] Q;
always @(posedge CLK or negedge CLRb) begin
if (!CLRb) Q <= 8'b00000000;
else begin
if (s == 2'b11) Q <= D;
else if (s == 2'b10) begin
... | 6.629743 |
module shift_reg_8bit_test;
reg CLK;
reg ENA;
reg S_in;
wire [7:0] Data_out;
shift_reg_8bit DUT2 (
.CLK(CLK),
.ENA(ENA),
.S_in(S_in),
.Data_out(Data_out)
);
initial begin
CLK = 0;
ENA = 1;
end
always #20 CLK = ~CLK;
initial begin
S_in = 1;
#200 S_in = 0;
... | 6.716095 |
module Shift_Reg_a (
A_in,
A_o,
i_clk,
ld_A,
shift_A
);
parameter N = 8;
input i_clk;
input [N-1:0] A_in;
input ld_A;
input shift_A;
output reg [N-1:0] A_o;
always @(posedge i_clk) begin
if (ld_A) begin
A_o <= A_in;
end else if (shift_A) begin
A_o <= {A_in, A_o[7:1... | 7.476916 |
module shift_reg_act (
input clk,
input rst_n,
input enable,
input [15:0] input_data,
output reg [575:0] result
);
reg state;
reg next_state;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
state <= 1'b0;
end else begin
state <=... | 7.893748 |
module Shift_Reg_b (
B_in,
B_o,
i_clk,
ld_B,
shift_B
);
parameter N2 = 8;
input i_clk;
input [N2-1:0] B_in;
input ld_B;
input shift_B;
output reg [N2-1:0] B_o;
always @(posedge i_clk) begin
if (ld_B) begin
B_o <= B_in;
end else if (shift_B) begin
B_o <= {B_in, B... | 7.307883 |
module shift_reg_en (
input clk,
input signed [255:0] D,
output reg signed [255:0] Q,
input enable
);
always @(posedge clk) begin
if (enable == 1) begin
Q <= D;
end
end
endmodule
| 7.456972 |
module shift_reg_kernel (
input clk,
input rst_n,
input enable,
input [15:0] input_data,
output reg [2495:0] result
);
reg state;
reg next_state;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
state <= 1'b0;
end else begin
stat... | 7.157604 |
module shift_reg_l4 (
input CLOCK_50,
input [0:0] SW,
input [1:0] KEY,
output [9:0] LEDR,
output reg [9:0] shift_rg_ledr,
output [7:0] LEDG,
output reg [7:0] shift_rg_ledg,
output reg flag
);
initial shift_rg_ledr = 10'b0;
initial shift_rg_ledg = 8'b0;
initial flag = 1;
alwa... | 6.86488 |
module shift_reg_l4 (
input clk,
input en,
input [0:0] sw,
input rst,
output reg [9:0] ledr
);
initial ledr = 10'b0;
always @(posedge en or posedge rst) begin
if (rst) begin
ledr <= 10'b0;
end else begin
if (en) begin
ledr <= {ledr[8:0], sw};
end else begin
... | 6.86488 |
module shift_reg_l4 (
input CLOCK_50,
input [1:0] SW,
input [1:0] KEY,
output [9:0] LEDR,
output [6:0] LEDG
);
reg [9:0] S;
reg [6:0] COUNTER;
reg EN;
reg [2:0] K;
reg [2:0] SBROS;
reg SBR;
initial S = 10'b0000000000;
initial K = 3'b000;
initial COUNTER = 7'b0000000;
always @(... | 6.86488 |
module shift_reg_l4(
input CLOCK_50,
input [1:0] KEY,
input [9:0] SW,
//input ISL,
//output reg OSL,
output [9:0] LEDG,
output [9:0] LEDR,
output reg [6:0] HEX0
//output reg [6:0] HEX1
);
reg noth_reg;
reg [9:0] LEDR_st_rg;
reg[32:0] counter;
reg[6:0] counter_;
reg[2:0] as_r;
initial HEX0 = 7'b1111111;... | 6.647231 |
module shift_reg_l4 (
input clk,
input en,
input ISL,
input rst,
output reg OSL,
output reg [3:0] shift_rg
);
initial shift_rg = 4'b0;
always @(posedge clk) begin
if (rst) begin
shift_rg <= 4'b0;
OSL <= 1'b0;
end else begin
if (en) begin
shift_rg <= {shift_... | 6.86488 |
module shift_reg_l4 (
input clk,
input en,
input rst,
output reg [7:0] counter
);
initial counter = 8'b0;
always @(posedge clk or posedge rst) begin
if (rst) counter <= 0;
else begin
if (en) counter <= counter + 1;
else counter <= counter;
end
end
endmodule
| 6.86488 |
module shift_reg_l4 (
input [7:0] d,
input clk,
input rst,
input en,
output reg [7:0] q
);
initial q <= 8'b0;
always @(posedge clk or posedge rst) begin
if (rst) q <= 7'b0;
else begin
if (en) q <= d;
else q <= q;
end
end
endmodule
| 6.86488 |
module shift_reg_l4 (
input d,
input clk,
input set,
input rst,
input en,
output reg q
);
always @(posedge clk or posedge set or posedge rst) begin
if (set) q <= 1'b1;
else begin
if (rst) q <= 1'b0;
else begin
if (en) q <= d;
else q <= q;
end
end... | 6.86488 |
module shift_reg_l4 (
input d,
input en,
output reg q
);
always @(en, d) begin
if (en) q <= d; // запись
else q <= q; // хранение
end
endmodule
| 6.86488 |
module shift_reg_l4 (
input nR,
input nS,
output Q,
output nQ
);
assign Q = ~(nS & nQ); // есои nS=0, то Q автоматом становится = 1
// =>
assign nQ = ~(nR & Q); // есои nR=0, то nQ автоматом становится = 1
endmodule
| 6.86488 |
module shift_reg_l4 (
input CLOCK_50,
input [0:0] SW,
input [1:0] KEY,
output [9:0] LEDR,
output reg [7:0] cout,
output reg [3:0] high_bit,
output reg [6:0] low_bit,
output reg [9:0] shift_rg,
output reg [6:0] HEX0,
output reg [6:0] HEX1,
output reg [6:0] HEX2,
output re... | 6.86488 |
module shift_reg_l4 (
input clk,
input en,
input [0:0] sw,
input rst,
output reg [9:0] ledr
);
initial ledr = 10'b0;
always @(posedge en or posedge rst) begin
if (rst) begin
ledr <= 10'b0;
end else begin
if (en) begin
ledr <= {ledr[8:0], sw};
end else begin
... | 6.86488 |
module shift_reg_l4 (
input CLOCK_50,
input [1:0] SW,
input [1:0] KEY,
output [9:0] LEDR,
output [6:0] LEDG
);
reg [9:0] S;
reg [6:0] COUNTER;
reg EN;
reg [2:0] K;
reg [2:0] SBROS;
reg SBR;
initial S = 10'b0000000000;
initial K = 3'b000;
initial COUNTER = 7'b0000000;
always @(... | 6.86488 |
module shift_reg_l4(
input CLOCK_50,
input [1:0] KEY,
input [9:0] SW,
//input ISL,
//output reg OSL,
output [9:0] LEDG,
output [9:0] LEDR,
output reg [6:0] HEX0
//output reg [6:0] HEX1
);
reg noth_reg;
reg [9:0] LEDR_st_rg;
reg[32:0] counter;
reg[6:0] counter_;
reg[2:0] as_r;
initial HEX0 = 7'b1111111;... | 6.647231 |
module shift_reg_l4 (
input clk,
input en,
input ISL,
input rst,
output reg OSL,
output reg [3:0] shift_rg
);
initial shift_rg = 4'b0;
always @(posedge clk) begin
if (rst) begin
shift_rg <= 4'b0;
OSL <= 1'b0;
end else begin
if (en) begin
shift_rg <= {shift_... | 6.86488 |
module shift_reg_l4 (
input clk,
input en,
input rst,
output reg [7:0] counter
);
initial counter = 8'b0;
always @(posedge clk or posedge rst) begin
if (rst) counter <= 0;
else begin
if (en) counter <= counter + 1;
else counter <= counter;
end
end
endmodule
| 6.86488 |
module shift_reg_l4 (
input [7:0] d,
input clk,
input rst,
input en,
output reg [7:0] q
);
initial q <= 8'b0;
always @(posedge clk or posedge rst) begin
if (rst) q <= 7'b0;
else begin
if (en) q <= d;
else q <= q;
end
end
endmodule
| 6.86488 |
module shift_reg_l4 (
input d,
input clk,
input set,
input rst,
input en,
output reg q
);
always @(posedge clk or posedge set or posedge rst) begin
if (set) q <= 1'b1;
else begin
if (rst) q <= 1'b0;
else begin
if (en) q <= d;
else q <= q;
end
end... | 6.86488 |
module shift_reg_l4 (
input d,
input en,
output reg q
);
always @(en, d) begin
if (en) q <= d; // запись
else q <= q; // хранение
end
endmodule
| 6.86488 |
module shift_reg_l4 (
input nR,
input nS,
output Q,
output nQ
);
assign Q = ~(nS & nQ); // есои nS=0, то Q автоматом становится = 1
// =>
assign nQ = ~(nR & Q); // есои nR=0, то nQ автоматом становится = 1
endmodule
| 6.86488 |
module param_shift_reg (
clk,
rst_n,
data_in,
data_out
);
parameter width = 8;
input clk, rst_n;
input data_in; //serial loading
output reg [width-1:0] data_out;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else begin
data_out <=... | 8.752063 |
module param_shift_reg_tb;
parameter period = 4;
parameter width = 8;
reg clk, rst_n;
reg data_in;
wire [width-1:0] data_out;
param_shift_reg #(
.width(width)
) reg_inst1 (
.clk(clk),
.rst_n(rst_n),
.data_in(data_in),
.data_out(data_out)
);
initial begin
cl... | 8.752063 |
module param_shift_reg_LR (
clk,
rst_n,
data_in,
data_out,
vector
);
parameter width = 8;
input clk, rst_n, vector;
input data_in; //serial loading
output reg [width-1:0] data_out;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else ... | 8.752063 |
module param_shift_reg_LR_tb;
parameter period = 4;
parameter width = 8;
reg clk, rst_n, vector;
reg data_in;
wire [width-1:0] data_out;
param_shift_reg #(
.width(width)
) reg_inst1 (
.clk(clk),
.vector(vector),
.rst_n(rst_n),
.data_in(data_in),
.data_out(data... | 8.752063 |
module shift_reg_out_l4 (
input CLOCK_50,
input [1:0] KEY,
input [0:0] SW,
//input ISL,
//output OSL,
output [9:0] LEDR,
output [6:0] HEX0
);
shift_reg_l4 init_1 (
CLOCK_50,
KEY[1:0],
SW[0:0],
LEDR[9:0],
HEX0[6:0]
);
endmodule
| 7.202464 |
module shift_reg_Quotient (
i_clk,
in_q,
en_q,
ld_q,
out_q,
sl_q
);
input i_clk;
input [`WIDTH_Q -1:0] in_q;
input sl_q; ///shift_left_q ///
input en_q; //enable the data //
input ld_q; //load the shifted data ///
output [`WIDTH_Q-1:0] out_q;
reg [`WIDTH_Q-1:0] temp_q;
always... | 6.790982 |
module Shift_reg_sum (
s_in,
s_out,
i_clk,
w3,
reset,
shift_s
);
parameter N3 = 8;
input i_clk;
input reset;
input [N3-1:0] s_in;
input shift_s;
input w3;
output reg [N3-1:0] s_out;
always @(posedge i_clk) begin
if (reset) begin
s_out <= s_in;
end else if (shift_... | 6.635842 |
module
`timescale 1ns/1ns
module shift_reg_tb;
localparam WIDTH=8;
reg clk;
reg rst_n;
reg shift_en;
reg data_in;
wire [7:0] data_out;
wire serial_out;
shift_reg #(.WIDTH(WIDTH)) shft
(// Outputs
.data_out ( data_out ),
.seri... | 6.608387 |
module shift_reg_with_reset (
KEY,
SW,
LEDR
);
input [1:0] KEY;
input [9:0] SW;
output [9:0] LEDR;
wire clk = KEY[0];
wire rst_n = KEY[1];
reg [9:0] shift_reg;
assign LEDR = shift_reg;
always @(posedge clk, negedge rst_n)
if (~rst_n) begin
shift_reg <= 0;
end... | 8.051687 |
module shift_reg #(parameter taps=8,parameter width=16)(
02 input clk,
03 input rst_n,
04 input [width-1:0] d_in,
05 output[width-1:0] d_out
06 );
07
08 generate
09 genvar i;
10 for(i=0; i<width; i=i+1) begin:shift_reg
11 reg [taps-1:0] r_reg;
12 wire [taps-1:0] r_next;
13 always@(posedge clk, negedge... | 7.796983 |
module shift_right_add (
in,
nshift,
out
);
input [24:0] in;
input [4:0] nshift;
output [24:0] out;
wire [23:0] temp1, temp2, temp3, temp4;
shift16_add shift_1 (
.in (in[23:0]),
.ena(nshift[4]),
.out(temp1)
);
shift8_add shift_2 (
.in (temp1),
.ena(nshift[3]),
... | 6.61057 |
module shift16_add (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {16'b0, in[23:16]} : in;
endmodule
| 6.916651 |
module shift2_add (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {2'b0, in[23:2]} : in;
endmodule
| 6.768694 |
module shift_right_logical (
out,
in,
shift_amount
);
input [15:0] in;
input [3:0] shift_amount;
output [15:0] out;
wire [15:0] p, q, r;
mux_32_to_16
mux1 (
p,
in[15:0],
{8'b0, in[15:8]},
shift_amount[3]
),
mux2 (
q,
p,... | 7.295146 |
module shift16_mult (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {16'b0, in[23:16]} : in;
endmodule
| 7.029514 |
module shift2_mult (
in,
ena,
out
);
input [23:0] in;
input ena;
output [23:0] out;
assign out = ena ? {2'b0, in[23:2]} : in;
endmodule
| 7.260561 |
module shift_right_placeholder (
input IR,
input [4:0] shift,
input [31:0] B,
output [31:0] H
);
always @(*) begin
if (IR == 1'b0) H <= B >> shift;
else H <= B >>> shift;
end
endmodule
| 7.810763 |
module shift_right_single (
input [31:0] A, //
input [ 4:0] cnt, //λ
output [31:0] B
);
reg [31:0] tmp;
always @(cnt) begin
case (cnt)
5'b00000: tmp <= {A[31:0]};
5'b00001: tmp <= {1'b0, A[31:1]};
5'b00010: tmp <= {2'b0, A[31:2]};
5'b00011: tmp <= {3'b0, A[31:3]};
... | 7.137346 |
module shift_right_var #(
parameter WORD_WIDTH = `WORD_WIDTH,
parameter SHIFT_WIDTH = `SHIFT_WIDTH
) (
input signed [ WORD_WIDTH-1:0] data_in,
input [SHIFT_WIDTH-1:0] shift_amount,
output reg signed [ WORD_WIDTH-1:0] data_out
);
integer i;
always @(*) begin
data_out = data... | 7.790565 |
module shift_right_var_test;
parameter WORD_WIDTH = `WORD_WIDTH;
parameter SHIFT_WIDTH = `SHIFT_WIDTH;
parameter clock_period = `CLOCK_PERIOD;
reg signed [ WORD_WIDTH-1:0] data_in;
reg [SHIFT_WIDTH-1:0] shift_amount;
wire signed [ WORD_WIDTH-1:0] data_out;
//-----instance of shift_right_var mo... | 7.790565 |
module shift_rot_32 (
input [31:0] in_x,
input [31:0] in_y,
input in_left,
in_rot,
output reg [31:0] out
);
// in_left = 1 -> shift/rot left
// in_left = 0 -> shift/rot right
// in_rot = 1 -> rotate
// in_rot = 0 -> shift
wire [ 4:0] w_rot_ammount;
wire [31:0] w_rot_left;
wire [31:0]... | 7.186904 |
module shift_round_position (
do_shift,
in,
in_round_bits,
in_sticky,
out,
out_round_bits,
out_sticky
);
parameter DATA_WIDTH = 32;
parameter SHIFT_BITS = 16;
input do_shift;
input [DATA_WIDTH-1:0] in; // The LSB is 1/2 digit.
input [DATA_WIDTH-1:0] in_round_bits;
input in_stic... | 8.230269 |
module shift_rows (
//OUTPUTS
output [127 : 0] data_out_enc, // Result after Shift Rows operation - enc
output [127 : 0] data_out_dec, // Result after Shift Rows operation - dec
//INPUTS
input [127 : 0] data_in // Input Bus
);
localparam integer BUS_WIDTH = 128; // Bus Width
localpar... | 6.667518 |
module Shift_Rows_Dec (
input [127:0] i_Din, // Data input to be transformed
output [127:0] o_Dout
);
assign o_Dout[007:000] = i_Din[103:096];
assign o_Dout[015:008] = i_Din[079:072];
assign o_Dout[023:016] = i_Din[055:048];
assign o_Dout[031:024] = i_Din[031:024];
assign o_Dout[039:032] = i_Din[007... | 7.359598 |
module Shift_Rows_Enc (
input [127:0] i_Din, // Data input to be transformed
output [127:0] o_Dout
);
assign o_Dout[007:000] = i_Din[039:032]; // As the high data are put into the situation of 0//
assign o_Dout[015:008] = i_Din[079:072]; // So o_Dout[127:120] represent for 0 byte which is in the poly.//
... | 8.281366 |
module SHIFT_ROWS_mem (
clk,
rst,
addr,
in,
wr,
out
);
input clk, rst, wr;
input [3:0] addr;
input [7:0] in;
output reg [7:0] out;
reg [7:0] ram[0:15];
integer i;
always @(posedge clk or negedge rst) begin
if (!rst) begin
out <= 0;
for (i = 0; i <= 15; i = i + 1) r... | 6.775448 |
module SHIFT_ROWS_state (
clk,
rst,
start,
data_in,
count,
out,
done,
MIX_COL_start,
MIX_COL_addr,
ADD_ROUND_start,
ADD_ROUND_addr
);
input wire clk, rst, start, MIX_COL_start, ADD_ROUND_start;
input wire [7:0] data_in;
input wire [3:0] count, MIX_COL_addr, ADD_ROUND_a... | 7.199224 |
module shift_row_l1 (
input clk,
input [15:0] data_in,
output [15:0] data_out
);
// Debug
// (1) n-k = 197, (2) Multiply (n-k) by 6 because kernel is 3*3*3*6
parameter DEPTH = 1182;
//parameter DEPTH = 197;
reg [DEPTH-1:0] holding_register0;
reg [DEPTH-1:0] holding_register1;
reg [DEPTH-1:0] ... | 6.717686 |
module shift_row_testbench ();
reg clk, reset;
reg [31:0] sb1;
reg [31:0] sb2;
reg [31:0] sb3;
reg [31:0] sb4;
wire [31:0] sr1;
wire [31:0] sr2;
wire [31:0] sr3;
wire [31:0] sr4;
shift_row DUT (
.clk (clk),
.reset(reset),
.SB1 (sb1),
.SB2 (sb2),
.SB3 (sb3),
... | 6.657761 |
module shift_selector #(
parameter EXP_SIZE = `EXP_SIZE,
parameter MANTIS_SIZE = `MANTIS_SIZE
) (
comp_code,
exp_A,
exp_B,
mantis_A,
mantis_B,
exp_shift,
exp_out,
mantis_shift,
mantis_out
);
// Inputs
input comp_code; // input code of comparator
input [EXP_SIZE ... | 7.621678 |
module shift_signals (
left,
noshift,
right,
A,
left_right,
left_right_n
);
output left, noshift, right;
input A, left_right, left_right_n;
specify
specparam CDS_LIBNAME = "ece555_projectlib";
specparam CDS_CELLNAME = "shift_signals";
specparam CDS_VIEWNAME = "schematic";
... | 6.618791 |
module shift_sign_extender (
output reg [31:0] out,
output reg carry_out,
input [31:0] instruction,
Rm
);
integer i = 0;
reg [31:0] temp;
always @(instruction, Rm) begin
case (instruction[27:25])
// Shift by Immediate Shifter Operand
3'b000: begin
if (instruction[4] == 0... | 9.478398 |
modules/data_path/shift_sign_extender.v"
module shift_sign_extender_test();
wire[31:0] out;
wire carry_out;
reg[31:0] instruction, Rm;
shift_sign_extender sse(out, carry_out, instruction, Rm);
initial #100 $finish;
initial begin
// Shift by immediate shifter ope... | 8.681555 |
module shift_sin_pout (
// clock input
input clk,
// select line
input select,
// latch data to expose internal shifter.
input le,
// input
input din,
// output
output [0:7] dout,
// parity signal
output parity
);
reg [0:7] latch_q;
reg [0:7] shift_q;
always @(pos... | 7.08874 |
module shift_top (
input clk,
input rst_n,
input uart_rx,
input signal,
//decode
output uart_tx
);
wire trans_ready;
wire [3:0] decode_out;
wire clk_valid;
decoder decoder_inst (
.clk(clk),
.rst_n(rst_n),
.signal(signal),
.t_valid(clk_... | 7.812354 |
module shift_unit #(
parameter WIDTH = 4,
parameter SHIFT_NUM = 0
) (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input shift_valid,
input shift_mask,
input [WIDTH - 1:0] shift_din,
output reg [2 * WIDTH - 1:0] shift_dout
);
wire [2 * WIDTH - 1:0] shift_din_ex... | 8.079455 |
module tb_Shif_reg4 ();
reg Data_In, reset;
reg clock = 0;
wire Data_out;
Shif_reg4 DUT (
Data_out,
Data_In,
clock,
reset
);
always #5 clock = ~clock; // clock declaration
initial begin
Data_In = 1'b0;
reset = 0; // apply serial input
#10 reset = 1'b1;
#10 Dat... | 6.608219 |
module shiftB (
q,
clock,
d
);
output [1:0] q;
input clock;
input d;
reg [1:0] q;
always @(posedge clock) begin
q[0] <= d;
q[1] <= q[0];
end
endmodule
| 7.373073 |
module SHL2 (
input [31:0] a,
input [31:0] pcn,
output [31:0] b
); //no <<2and combine
reg [31:0] an;
always @(*) begin
an[25:0] = a[25:0];
an[31:26] = pcn[31:26];
end
assign b = an;
endmodule
| 6.502957 |
module SHL26bit (
inp,
out
);
input [25:0] inp;
output reg [27:0] out;
always @(inp) out = {inp, 2'b00};
endmodule
| 6.543386 |
module shl2_26b (
d_in,
d_out
);
input [25:0] d_in;
output [27:0] d_out;
assign d_out = {d_in, 2'b00};
endmodule
| 6.592565 |
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