code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module IntSyncCrossingSource( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@107490.2]
input auto_in_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@107493.4]
output auto_out_sync_0 // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@107... | 6.689384 |
module SynchronizerShiftReg_w43_d1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@109778.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@109779.4]
input [42:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@109781... | 6.820992 |
module SynchronizerShiftReg_w55_d1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@189639.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@189640.4]
input [54:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@189642... | 6.820992 |
module SynchronizerShiftReg_w12_d1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@191134.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@191135.4]
input [11:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@191137... | 6.820992 |
module SynchronizerShiftReg_w1_d3( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@207612.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@207613.4]
input io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@207615.4]
... | 6.820992 |
module IntSyncCrossingSink( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@207628.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@207629.4]
input auto_in_sync_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@207631.4]
... | 6.689384 |
module IntSyncCrossingSink_1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@207656.2]
input auto_in_sync_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@207659.4]
input auto_in_sync_1, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fi... | 6.689384 |
module IntSyncCrossingSink_2( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@207672.2]
input auto_in_sync_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@207675.4]
output auto_out_0 // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@207... | 6.689384 |
module AsyncResetRegVec_w2_i0( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@216981.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@216982.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@216983.4]
inp... | 6.68936 |
module IntSyncCrossingSource_2( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@217014.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@217015.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@217016.4]
in... | 6.689384 |
module IntSyncCrossingSource_3( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@217071.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@217072.4]
input reset, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@217073.4]
in... | 6.689384 |
module IsoZero ( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@228528.2]
input io_in, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@228531.4]
input io_iso, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@228531.4]
output io_out ... | 6.599484 |
module SynchronizerShiftReg_w80_d1( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@230534.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@230535.4]
input [79:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@230537... | 6.820992 |
module IntSyncCrossingSource_4( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@231877.2]
input auto_in_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@231880.4]
input auto_in_1, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@231880... | 6.689384 |
module DeglitchShiftRegister( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@232177.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@232178.4]
input io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@232180.4]
ou... | 7.512449 |
module SynchronizerShiftReg_w2_d3( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@232315.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@232316.4]
input [1:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@232318.4... | 6.820992 |
module IntSyncCrossingSink_4( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@232331.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@232332.4]
input auto_in_sync_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@232334.4... | 6.689384 |
module SynchronizerShiftReg_w32_d3( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@259558.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@259559.4]
input [31:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@259561... | 6.820992 |
module SynchronizerShiftReg_w4_d3( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@269550.2]
input clock, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@269551.4]
input [3:0] io_d, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@269553.4... | 6.820992 |
module IntSyncCrossingSink_11( // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@274421.2]
input auto_in_sync_0, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@274424.4]
input auto_in_sync_1, // @[:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.f... | 6.689384 |
module SIFT_Detection_FIFO (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [0:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [0:0] q;
output [14:0] usedw;
wire [14:0] sub_wire0;
wire sub_wire1;
... | 6.604658 |
module SIFT_Detection_FIFO_Controller (
input iclk,
input ireset,
input iwrite_en,
input iread_en,
input idata,
output reg odata_en,
output odata,
output [14:0] ousedw
);
wire write_request;
wire read_... | 6.604658 |
module sift_top (
input clk_sys,
input wire flag_read, // 1时写入新图像，处理模块复位
input wire [7:0] img,
output wire [17:0] addr_sift, // 从FIFO读数据
output wire out_feat_en,
output wire [5:0] sift_dir,
output wire [7:0] sift_mag,
output wire kp,
output wire [17:0] kp_addr,
output wi... | 6.646376 |
module sirv_sim_ram #(
parameter DP = 512,
parameter FORCE_X2ZERO = 0,
parameter DW = 32,
parameter MW = 4,
parameter AW = 32
) (
input clk,
input [DW-1 : 0] din,
input [AW-1 : 0] addr,
input cs,
input we,
input [ MW-1:0] wem,
outpu... | 8.126046 |
module sif_addsub_bfe_fixedp #(
parameter WIDTH_A = 16, // input a data width, 8,16, 20, 28
parameter WIDTH_B = 16, // input b data width, 16, 20, 28
parameter WIDTH_S = 17,
parameter IS_SUB = 1
) (
input clk,
input rst_n,
input is_sub,
inp... | 8.892998 |
module sif_add_complex #(
parameter WIDTH_A = 16, // input a data width, 8,16, 20, 28
parameter WIDTH_B = 16, // input b data width, 16, 20, 28
parameter WIDTH_S = 17,
parameter IS_SUB = 1
) (
input clk,
input rst_n,
input is_sub,
input ... | 8.623294 |
module sif_add_half_fp (
input clk,
input A_vld,
input [16-1:0] A_dat,
output A_rdy,
input B_vld,
input [16-1:0] B_dat,
output B_rdy,
output S_vld,
output [16-1:0] S_dat,
input S_rdy
);
half_fp_add u_half_fp_... | 6.510453 |
module sif_div_half_fp (
input clk,
input A_vld,
input [16-1:0] A_dat,
output A_rdy,
input B_vld,
input [16-1:0] B_dat,
output B_rdy,
output P_vld,
output [16-1:0] P_dat,
input P_rdy
);
half_fp_div u_half_fp_... | 6.576125 |
module sif_fifo #(
parameter w = 16,
parameter d = 1024
) (
input clk,
input rst_n,
input up_vld,
input [w-1:0] up_dat,
output up_rdy,
output dn_vld,
output [w-1:0] dn_dat,
input dn_rdy
); // sif_fifo
localparam half_fp_bits... | 7.867385 |
module sif_recip_square_half_fp (
input clk,
input A_vld,
input [16-1:0] A_dat,
output A_rdy,
output P_vld,
output [16-1:0] P_dat,
input P_rdy
);
half_fp_recip_square u_half_fp_recip_square (
.aclk (clk), // input wi... | 7.231053 |
module sif_sub_half_fp (
input clk,
input is_sub,
input A_vld,
input [16-1:0] A_dat,
output A_rdy,
input B_vld,
input [16-1:0] B_dat,
output B_rdy,
output S_vld,
output [16-1:0] S_dat,
input S_rdy
... | 6.591108 |
module SigCIC (
rst,
clk,
din,
rdy,
dout
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟，频率为200kHz
input signed [9:0] din; //数据输入频率为200kHZ
output rdy; //输出数据有效指示信号
output signed [12:0] dout; //滤波后的输出数据,5倍抽取后的数据,频率为40kHZ
reg rdy_tem;
reg [2:0] c;
reg signed [12:0] tem;
reg ... | 7.038686 |
module sigen_trigger (
clock,
reset,
trigger_input,
trigger_output
);
input clock, reset, trigger_input;
output reg trigger_output;
reg [15:0] clock_counter;
reg trigger_flag;
always @(posedge clock or negedge reset or posedge trigger_input) begin
if (~reset) begin
trigger_output <... | 6.662986 |
module Extend (
input [15:0] Inst15_0,
output reg [31:0] out
);
always @(Inst15_0) begin
out <= {{16{Inst15_0[15]}}, Inst15_0[15:0]};
end
endmodule
| 7.48595 |
module EXT5T32 (
X,
Y
);
input [4:0] X;
output [31:0] Y;
parameter z = 27'b0;
assign Y = {z, X};
endmodule
| 7.886355 |
module siggen_tb;
reg clk;
reg reset;
wire [15:0] test_signal;
siggen siggen_inst (
.clk(clk),
.reset(reset),
.signal(test_signal)
);
initial begin
clk = 0;
reset = 1;
end
always #5 begin
clk = !clk;
reset = 0;
end
endmodule
| 7.826923 |
module sigin (
data,
address
);
input [7:0] address;
output [7:0] data;
reg [7:0] data;
// an arbitrary data source here
always @(address) data = address + 1; //这里通过该式子完成数据的初始化
endmodule
| 6.525495 |
module signalinput (
input [1:0] testmode, // 00, 01, 10, 11 分别代表4种频率,
// 分别为 3125, 250, 50, 12500Hz, 使用 SW1~SW0 来控制
input sysclk, // 系统时钟100M
output sigin1 // 输出待测信号
);
reg [20:0] state;
reg [20:0] divide;
reg sigin;
assign sigin1 = sigin;
initial begin
sigin ... | 7.817968 |
module digit_dislpay (
input wire clk_100M,
input wire clr,
input wire [31:0] x,
output reg [6:0] a_to_g,
output reg [3:0] an
);
wire [ 1:0] s;
reg [ 7:0] digit;
reg [20:0] clkdiv;
always @(posedge clk_100M or posedge clr) begin
if (clr) clkdiv <= 0;
else clkdiv <= clkdiv + 1;
en... | 7.667234 |
module sigmaDelta2ndOrder #(
parameter WIDTH = 16,
parameter GROWTH = 2
) (
input clk,
input rst,
input en,
input signed [WIDTH-1:0] in,
output sdOut
);
// For 2nd order sigma-delta modulators, signal to noise ratio (SNR) must be
// balanced against stability. Choosing a GAIN of one w... | 7.761775 |
module sigmadelta_adc (
clk,
rstn,
digital_out,
analog_cmp,
analog_out,
sample_rdy
);
parameter ADC_WIDTH = 8, // ADC Convertor Bit Precision
ACCUM_BITS = 10, // 2^ACCUM_BITS is decimation rate of accumulator
LPF_DEPTH_BITS = 3; // 2^LPF_DEPTH_BITS is decimation rate of averager
//i... | 6.661028 |
module SigmaPC (
sprimo,
rdyin,
op,
esito_ma,
ackinc,
opoutc,
esitoc,
ackinm,
opoutm,
esitom,
stato
);
input [1:0] stato;
input rdyin;
input [1:0] op;
input esito_ma;
input ackinc;
input [1:0] opoutc;
input esitoc;
input ackinm;
input [1:0] opoutm;
input ... | 6.558501 |
module sigma_16p_tb;
reg clk, res;
reg [ 7:0] data_in;
reg syn_in;
wire [11:0] data_out;
wire syn_out;
sigma_16p sigma_16p (
.clk(clk),
.res(res),
.data_in(data_in),
.syn_in(syn_in),
.data_out(data_out),
.syn_out(syn_out)
);
initial begin
//clk <= ... | 7.159913 |
module sigma_dac #(
parameter [31:0] NBITS = 16
) (
input clk_i,
input rst_i,
input [NBITS-1:0] din_i,
output dout_o
);
//-----------------------------------------------------------------
// Implementation: Described in Xilinx xapp154.pdf
//--------------------------------------... | 7.32056 |
module sigma_delta (
input wire [15:0] DATA,
input wire CLK,
input wire RST,
output reg OUT
);
reg [15:0] delayed_input;
wire [15:0] extended_output;
DDC_1 SignExtend_DDC (
.IN (OUT),
.OUT(extended_output)
);
always @(posedge CLK or negedge RST) begin
if (RST == 1'b0) begi... | 6.717586 |
module is a third order delta/sigma modulator
// It uses no multiply only shifts by 1, 2 or 13
// There are only 7 adders used, it takes around 110 LUTs
//
// Borrowed from Mark Watson's Atari 800 repo - common/components/hq_dac.v
// Copyright status and origin is unclear since it's not mentioned
// in his COPYRIGHT_NO... | 7.533665 |
module sigma_delta_tb ();
reg [15:0] data_in;
reg clock;
reg reset;
wire data_out;
reg [15:0] data[255:0];
integer i;
integer index;
initial begin
i = 0;
index = 0;
$readmemh("C:/Users/13400002/Documents/SigDel/data.txt", data);
clock <= 1'b1;
reset <= 1'b1;
data_in <= 16'h... | 6.831523 |
module mid_val (
in,
out
);
parameter DWIDTH = 32;
input [2:0] in;
output reg signed [DWIDTH-1:0] out;
always @(in) begin
case (in)
0: out = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
1: out = 32'b0000_0001_1000_0000_0000_0000_0000_0000;
2: out = 32'b0000_0010_1000_0000_0000_0... | 6.987096 |
module mult_3in (
A,
B,
C,
Out
);
parameter DWIDTH = 32;
parameter frac = 24;
input signed [DWIDTH-1:0] A, B, C;
output signed [DWIDTH-1:0] Out;
wire signed [4*DWIDTH-1:0] temp;
assign temp = A * B * C;
assign Out = temp[((4*DWIDTH-1)-(3*DWIDTH)+(2*frac)):2*frac];
endmodule
| 7.755309 |
module adder_4in (
A,
B,
C,
out
);
parameter DWIDTH = 32;
parameter frac = 24;
input signed [DWIDTH-1:0] A, B, C;
output signed [DWIDTH-1:0] out;
assign out = A + B + C;
endmodule
| 9.091391 |
module dsp_signed_mac_18_13_23_32 (
input clk,
input reset,
input ena,
input i_valid,
input [17:0] ax,
input [12:0] ay,
input [22:0] az,
output o_valid,
output [31:0] resulta
);
reg [17:0] reg_ax;
reg [12:0] reg_ay;
reg [22:0] reg_az;
reg [31:0] reg_res;
always @(posedge c... | 7.738783 |
module shift_register_unit_1_3 (
input clk,
input reset,
input enable,
input [0:0] in,
output [0:0] out
);
reg [0:0] shift_registers_0;
reg [0:0] shift_registers_1;
reg [0:0] shift_registers_2;
always @(posedge clk) begin
if (reset) begin
shift_registers_0 <= 1'd0;
shift_reg... | 6.854847 |
module sigmoid_seq #(
parameter DATA_WIDTH = 16, // indicate the length of input data, in 2's complement
parameter DECIMAL_POINT = 5 // indicate the location of decimal point, starting at 0 (LSB)
) (
// timeing signals
clk,
rst_n,
// data signals
i_valid, // valid input data signal
... | 7.671713 |
module sigm_coef (
i_sel,
o_coef0,
o_coef1,
o_coef2
);
// parameters
parameter WIDTH = 32;
// parameter c0_01 = 32'b0000_0000_1000_0000_0000_0000_0000_0000 ;
parameter c0_01 = 32'b0000_0000_1001_1111_0011_1011_0110_0100;
parameter c0_12 = 32'b0000_0000_1101_0001_0100_0000_0000_0000;
param... | 7.676238 |
module sign_extend (
input [15:0] instr,
output [31:0] extend_instr
);
assign extend_instr[15:0] = instr[15:0];
assign extend_instr[31:16] = {16{instr[15]}};
endmodule
| 7.581479 |
module sign_extend (
input [25:0] in,
output [31:0] out
);
assign out = {{6{in[25]}}, in};
endmodule
| 7.581479 |
module
module signExtend
(
input SignExt,
input [5:0] data,
output [15:0] out
);
assign out = (SignExt) ? {{10{data[5]}}, data[5:0]} : {{10{1'b0}}, data[5:0]};
endmodule
| 6.645743 |
module SignAddSub #(
parameter INPUT_BIT_WIDTH = 8
) (
input Clk,
input [INPUT_BIT_WIDTH-1:0] InputA,
input [INPUT_BIT_WIDTH-1:0] InputB,
input wire AddSubMode,
output reg [INPUT_BIT_WIDTH-1:0] Result,
output reg [INPUT_BIT_WIDTH-1:0] ResultB
);
always @(posedge Clk) begin
if (AddSubM... | 6.763947 |
module signalch (
input clk,
input rst_n,
input [15:0] din,
output [3:0] we_rd,
output en_rd,
output reg fs_enb,
output reg [10:0] addr_rd,
output reg [15:0] ram_rd_out
//output reg [11:0] addr_o
);
reg [9:0] counter;
assign we_rd = 4'b0;
assign en_rd = 1'b1;
//clock perio... | 6.851099 |
module SignalChangeTimeOut (
clk,
SignalIn,
TimeOut
);
input clk, SignalIn;
output reg TimeOut;
parameter [7:0] clkFreqIn_MHz = 40;
parameter [11:0] TimeOutIn_ms = 1;
localparam [31:0] PR = clkFreqIn_MHz * (1000 * TimeOutIn_ms);
reg [31:0] Cnt = 32'h00000000;
reg pre_strb_0 = 1'b0;
alw... | 8.530325 |
module signalclkctrl (
rst_n,
clk_sys,
load,
acqnum,
stripnum,
periodnum,
entop,
//enadd,
//enclk,
clk_add,
clk_acq,
clkin
//clkin1,
//clkin2
);
input rst_n;
input clk_sys;
input load;
input [15:0] acqnum;
input [11:0] stripnum;
input [3:0] periodnum;... | 6.559224 |
module signalDeal (
input [6:0] upButton,
input [7:1] downButton,
input [7:0] stairChooser,
input rst_n,
output reg [7:0] signal
);
// 综合各个输入信号
always @(*) begin
if (rst_n) begin
signal <= 8'b00000001;
end else begin
signal <= ({1'b0, upButton} | stairChooser) | {downButton,... | 7.980499 |
module SignalExt_32 (
input S,
output [31:0] So
);
assign So = {32{S}}; //1 bit to 32 bits
endmodule
| 8.953122 |
module SignalGenerator (
input Clock, // 50 MHz
input Reset_n,
output [13:0] SignalOut // 25 MHz square wave
);
// 2 time steps
parameter VPP = 15'hFFF;
reg [14:0] Signal_q, Signal_d;
(* syn_encoding = "user, safe" *) reg [1:0] State_q, State_d;
parameter RISING_STATE = 3'b... | 7.43334 |
module that generates the signal to be measured
module signalInput(sysclk,resetb,testmode,sigIn);
input sysclk; //50MHz system clock
input resetb; //asynchronous reset signal
input [1:0] testmode; //use SW1~SW0 to control
output sigIn; ... | 6.649759 |
module signalInput_tb;
reg sysclk, resetb;
reg [1:0] testmode;
initial begin
sysclk <= 0;
resetb <= 0;
testmode <= 2'b11;
#1 resetb <= 1;
#9000 resetb <= 0;
end
initial begin
repeat (10000) #1 sysclk <= ~sysclk;
end
signalInput si (
.sysclk(sysclk),
.resetb(rese... | 7.04976 |
module SignalPipeLineDelay #(
parameter SIG_DLY = 3
) (
input clk,
input signal_in,
output signal_out
);
reg [SIG_DLY:0] signal_delay;
assign signal_out = signal_delay[SIG_DLY];
// setting clk delays between audio_en and X_pcm_d_en
always @(posedge clk) begin
signal_delay[0] <= signal_i... | 6.760383 |
module PCIe #(
parameter MAXPIPEWIDTH = 32,
parameter DEVICETYPE = 0, //0 for downstream 1 for upstream
parameter LANESNUMBER = 16,
parameter GEN1_PIPEWIDTH = 8,
parameter GEN2_PIPEWIDTH = 8,
parameter GEN3_PIPEWIDTH = 8,
parameter GEN4_PIPEWIDTH = 8,
parameter GEN5_PIPEWIDTH =... | 8.391032 |
module SignalSelect (
input wire clk,
input wire [bitwidth*channels-1:0] signal_in,
input wire [channels-1:0] available_in,
input wire [7:0] channel_select,
output reg [bitwidth-1:0] signal_out,
output reg available_out
);
parameter bitwidth = 16;
parameter channels = 8;
always @(posedge ... | 7.81086 |
module SignalsMuxModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire [1:0] Addr,
input wire [7:0] Sig0,
input wire [7:0] Sig1,
input wire [7:0] Sig2,
input wire [7:0] Sig3,
output wire [7:0] Value
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam... | 6.930777 |
module signalSync (
input clock,
input asynchronous_signal,
output rising_edge,
output falling_edge
);
reg [1:3] resync;
reg fall, rise;
initial begin
fall <= 0;
rise <= 0;
resync <= 0;
end
//sampling frequency must be double
//two clock cycles from signal to get a logic... | 7.0263 |
module signals_counter (
input clock,
reset,
input REF,
MES,
output [31:0] DIFF,
output sign
);
reg r_d, r_d_1, m_d, m_d_1;
reg state, state1;
reg REF_posedge, MES_posedge;
reg [31:0] counter_RtoM, counter_MtoR;
reg [31:0] DIFF_RtoM, DIFF_MtoR;
assign DIFF = (DIFF_RtoM > DIFF_MtoR)... | 6.93084 |
module signals_tb;
reg RESET;
reg CLOCK;
reg ENABLE;
wire [15:0] OUT_SIGNALS;
signals STEPS (
RESET,
CLOCK,
ENABLE,
OUT_SIGNALS
);
initial begin
CLOCK = 0;
RESET = 1;
ENABLE = 1;
#20 RESET = 0;
ENABLE = 1;
end
always begin
#10 CLOCK = !CLOCK;
... | 6.840931 |
module
module signalTapTest0 (SW, CLOCK_50, LEDR);
input [9:0] SW;
input CLOCK_50;
output [9:0] LEDR;
wire [31:0] dclock;
// Clock divider added to allow us to physically observe the behaviors of the counter.
clock_divider cdiv (.clock(CLOCK_50), .divided_clocks(dclock));
// su_counter counter (.out(LEDR[3... | 7.166586 |
module that generates 1Hz signal
module signal_1Hz(sysclk,sig1Hz);
input sysclk; //system clock of 50M Hz
output reg sig1Hz; //output signal of 1 Hz
reg [25:0] count;
initial
begin
count<=26'd0;
sig1Hz<=0;
end
always @(posedge sysclk)
begin
if(count==26'd50000000)
count<=26... | 6.649759 |
module that test the module signal_1Hz
module signal_1Hz_tb;
reg sysclk;
wire sig1Hz;
initial //simulate the system clock
begin
sysclk<=0;
repeat(200000000)
#2 sysclk<=~sysclk;
end
signal_1Hz s1Hz(.sysclk(sysclk),.sig1Hz(sig1Hz));
endmodule
| 7.095159 |
module signal_analyser_tb ();
`SETUP_TEST
reg clk;
reg rst;
reg [7:0] d;
wire [31:0] t;
wire [7:0] dOut;
wire newData;
reg data_sent;
initial begin
$dumpfile(`VCD_OUTPUT);
$dumpvars(0, signal_analyser_tb);
clk = 0;
d = 0;
data_sent = 0;
forever begin
#1 clk = ~clk;
... | 8.044799 |
module signal_check #(
parameter U_DLY = 1
)(
input clk,
input rst_n,
input si,
input [1:0] type,
input ms_pulse,
input [7:0] ... | 6.847663 |
module Signal_comb (
input iclk,
input irst_n,
input [9:0] iRed_1,
input [9:0] iGreen_1,
input [9:0] iBlue_1,
input [9:0] iRed_2,
input [9:0] iGreen_2,
input [9:0] iBlue_2,
input [2:0] iTrans,
input slt,
output [9:0] now_x,
output [9:0] now_y,
output [9:0] oRed,
o... | 7.688122 |
module and its ports. This is
// using Verilog-2001 syntax.
module signal_counter(
input wire pclk,
input wire rst,
input wire signal,
output reg [3:0] signal_counter
);
localparam IDLE = 2'b00;
localparam INCREMENT = 2'b01;
localparam SIGNAL_ON = 2'b10;
reg [3:0] signal_counter_nxt;
reg [1:0] state, next_s... | 6.630177 |
module Signal_CrossDomain (
input clkA,
input SignalIn_clkA,
input clkB,
output SignalOut_clkB
);
// We use a two-stages shift-register to synchronize SignalIn_clkA to the clkB clock domain
reg [1:0] SyncA_clkB;
always @(posedge clkB) SyncA_clkB[0] <= SignalIn_clkA; // notice that we use clkB... | 7.487392 |
module Signal_CrossDomain_As_Flag (
clkA,
SignalIn,
clkB,
SignalOut
);
// clkA domain signals
input clkA;
input SignalIn;
// clkB domain signals
input clkB;
output SignalOut;
/*
/// This code is from fpga4fun.com and doesn't "quite" work right...
// Now let's transfer SignalIn into the... | 7.487392 |
module signal_cross_domain (
input clkA, // we actually don't need clkA in that example, but it is here for completeness as we'll need it in further examples
input SignalIn_clkA,
input clkB,
output SignalOut_clkB
);
// We use a two-stages shift-register to synchronize SignalIn_clkA to the clkB cloc... | 7.456695 |
module signal_detector (
input clk_50mhz_in,
input hsync_in,
output signal_present_out
);
reg [31:0] keepalive = 0;
reg signal_present = 1'b0;
reg last_hsync_in = 1'b1;
assign signal_present_out = signal_present;
parameter signal_present_threshold = 15000000;
always @(posedge clk_50mhz_in... | 6.88188 |
module that interfaces with and ADC
* and outputs the result on 7 inline LEDs like a VU
* meter.
*/
module signal_display (
input adc_sdat, // \
output adc_saddr, // | - ADC interface
output adc_sclk, // |
output adc_cs_n, ///
input rst_n,
input clk, // ... | 7.728819 |
module signal_edge (
input clk,
input button,
output button_edge
);
reg button_r1, button_r2;
always @(posedge clk) begin
button_r1 <= button;
end
always @(posedge clk) begin
button_r2 <= button_r1;
end
assign button_edge = button_r1 & ~button_r2;
endmodule
| 6.590149 |
module signal_extend #(
parameter OUT_DATA_WIDTH = 32,
parameter IN_DATA_WIDTH = 16
) (
input [ IN_DATA_WIDTH-1:0] signal_in,
output [OUT_DATA_WIDTH-1:0] signal_out
);
// Verificar se vai extender o sinal apenas de uma forma
assign signal_out = {{(OUT_DATA_WIDTH - IN_DATA_WIDTH) {signal_in[IN_DAT... | 8.699792 |
module signal_extensor (
clock,
operation,
reg_a,
reg_b,
immediate,
ex_op,
ex_a,
ex_b,
ex_im
);
input clock;
input [2:0] operation;
input [2:0] reg_a;
input [1:0] reg_b;
input [7:0] immediate;
output reg [2:0] ex_op;
output reg [2:0] ex_a;
output reg [2:0] ex_b;
o... | 6.973518 |
module signal_generation_unit (
input wire [ `STATE_COUNT-1:0] state,
input wire cycle_count,
input wire [`OPCODE_COUNT-1:0] opcode_type,
input wire [ `GROUP_COUNT-1:0] opcode_group,
output wire [`SIGNAL_COUNT-1:0] signals
);
/* Control signals */
/* Register interface ... | 7.665978 |
module SIGNAL_GENERATOR (
output [13:0] signal_dc,
input SW,
input i_Clk
);
parameter WAIT = 1'b0, OUT = 1'b1;
reg siggen_state;
reg [13:0] signal_dc_0;
assign signal_dc = signal_dc_0;
reg [23:0] counter;
reg [ 3:0] signal_state;
always @(posedge i_Clk) begin
case (siggen_state)
WA... | 7.196948 |
module signal_generator_testbackplane (
error_led,
enable,
reset,
delay_select,
half_period,
noise_1,
noise_2,
noise_3,
noise_4,
noise_5,
noise_6,
hex0,
hex1,
hex2,
hex3,
data_pattern_tx,
data_pattern_rx,
data_pattern_rx_oszi,
data_pattern_tx_o... | 7.665978 |
module signal_generator_testbackplane_toplevel (
ledr,
ledg,
hex0,
hex1,
hex2,
hex3,
key,
sw,
gpio1,
gpio0,
clk_50
);
inout [35:0] gpio1;
output [35:0] gpio0;
input wire [3:0] key;
input wire [9:0] sw;
input clk_50; // 50MHz CLK offered by quarz
output wire ... | 7.665978 |
module sync(
//input signal
input sys_clk,
input sys_rst,
input data_in,
//output signal
output data_out
);
//parameter define
//reg define
reg data_out_reg;
reg data_tem;
//wire define
//*****************************************************************... | 6.552618 |
module sync (
//clock signal and reset signal
input sys_clk,
input sys_rst,
//data input from different fir filters
input fir1,
input fir2,
input fir3,
input fir4,
//select signal
input [2:0] select,
//data output
output select_output
);
//reg define
reg select_output_reg;
//*********... | 7.636153 |
module signal_gen_testbench ();
/* Parameters */
parameter NUM_WIDTH = 3;
parameter NUM_VALUE = 7;
/* Variables */
reg [NUM_WIDTH - 1 : 0] num = 0;
reg clk = 0;
wire signal;
/* Behavioral */
// Signal Generator Instance
signal_gen #(
.NUM_WIDTH(NUM_WIDTH),
.NUM_VALUE(NUM_VALUE)
... | 7.556425 |
module to record signals
//
// It samples a signal on the rising edge of every clock
// cycle and records any changes to its value.
//
// Utility variables
// events - The number of events that have occured
// cycle - the number of clock cycles which have occurred
//
// Utility functions/tasks
// get_value(index) - Get... | 6.60204 |
module signal_hold #(
parameter HOLD_CLOCKS = 2,
parameter DATA_WIDTH = 1
) (
input clk,
input aresetn,
input [DATA_WIDTH-1:0] data_in,
output wire [DATA_WIDTH-1:0] data_out
);
localparam HOLD_COUNT = (HOLD_CLOCKS > 1) ? (HOLD_CLOCKS - 1) : ... | 8.280243 |
module signal_holder #(
parameter DELAY_COUNT = 1000,
parameter COUNTER_WIDTH = log2(DELAY_COUNT)
) (
input reset_in,
input clk,
output reg reset_out
);
`LOG2
reg [COUNTER_WIDTH-1 : 0] counter;
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
reset_out <= 1'b1... | 6.5636 |
module signal_invert (
input sig_in,
output sig_out
);
assign sig_out = ~sig_in;
endmodule
| 6.656259 |
module Signal_in_div_module (
input signal_in,
input rst,
output signal_in1
);
reg [31:0] cnt;
reg signal_in1_reg;
assign signal_in1 = signal_in1_reg;
always @(posedge signal_in or negedge rst) begin
if (!rst) begin
cnt <= 0;
signal_in1_reg <= 0;
end else begin
cnt <= ... | 7.512472 |
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