code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module simple_if ();
reg latch;
wire enable, din;
always @(enable or din)
if (enable) begin
latch <= din;
end
endmodule
| 6.709566 |
module simple_imem #(
parameter loadfile = "build/jupiter_asm.hex"
) (
input clock_i,
input re_i,
input ssr_i,
input [09:0] address_i,
output reg [63:0] data_o = 0
);
reg [7:0] instmemory[0:1023];
wire [9:0] address0, address1, address2, address3;
wire [9:0] address... | 6.685139 |
module simple_imgcontroller (
input [10:0] h_cnt,
input [9:0] v_cnt,
input rgbvalid,
output rgb
);
endmodule
| 6.50423 |
module simple_keyboard (
PS2_DATA,
PS2_CLK,
clk,
rst,
dec,
ssd_ctrl
);
input clk, rst;
inout PS2_DATA, PS2_CLK;
output [7:0] dec;
output [3:0] ssd_ctrl;
wire [8:0] last_change;
wire key_valid;
wire [511:0] key_down;
reg [3:0] ssd_ctrl;
always @* begin
if (last_change == 9... | 6.962619 |
module simple_memory #(
parameter [31:0] pWords = 32'd128
) (
input wire iwClk,
input wire iwnRst,
input wire [31:0] iwReadAddr,
input wire [31:0] iwWriteAddr,
input wire [31:0] iwWriteData,
input wire [ 3:0] iwWstrb,
output reg [31:0] orReadData
);
reg [7:0] rMemory[0:pWords * 4 - 1... | 6.595109 |
module simple_memory_tb ();
logic clk;
logic read;
logic write;
logic [31:0] addr;
logic [3:0] byteenable;
logic [31:0] writedata;
logic [31:0] readdata;
logic waitrequest;
//Ram emulation setup
parameter SIZE = 1024;
parameter RAM_FILE = "ram.txt";
logic [31:0] mem[SIZE-1:0];
int j;
initia... | 6.595109 |
module clau
// (
// input wire [3:0]p ,
// input wire [3:0]g ,
// input wire cin ,
// output wire [3:0]cout ,
// output wire pp ,
// output wire gg
// );
// assign gg=g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0]);
// as... | 7.613021 |
module simple_move (
input clk,
input pwm_clk,
input en_PWM,
input rx,
output tx,
output rx_flag_out,
output [7:0] rx_reg_out,
output [3:0] sig_to_mot,
dirp,
dirn
);
parameter FOR = "f";
parameter BCK = "b";
parameter RHT = "r";
parameter LFT = "l";
parameter UPW = "u"... | 6.895578 |
module simple_mult #(
parameter widtha = 1,
parameter widthb = 1,
parameter widthp = 2
) (
input clk,
input signed [widtha-1:0] a,
input signed [widthb-1:0] b,
output [widthp-1:0] out
);
//----------------------------------------------------------------------... | 7.455839 |
module simple_multiplier (
ce,
rst,
clk,
a,
b,
p
);
localparam ASIZE = 16; //@IPC int 2,72
localparam BSIZE = 16; //@IPC int 2,72
localparam A_SIGNED = 0; //@IPC enum 0,1
localparam B_SIGNED = 0; //@IPC enum 0,1
localparam ASYNC_RST = 0; //@IPC enum 0,1
localparam OPTIMA... | 6.987822 |
module simple_multiplier_tb ();
localparam T_CLK_PERIOD = 10; //clock a half perid
localparam T_RST_TIME = 200; //reset time
localparam T_SIM_TIME = 100000; //simulation time
localparam ASIZE = 16; //@IPC int 2,72
localparam BSIZE = 16; //@IPC int 2,72
localparam A_SIGNED = 0; //@IPC enum 0,1
... | 6.987822 |
module simple_mux (
data,
sel,
out
);
`include "log2.inc"
parameter WIDTH = 64;
parameter LOG_WIDTH = log2(WIDTH - 1);
input [WIDTH-1:0] data;
input [LOG_WIDTH-1:0] sel;
output out;
assign out = data[sel];
endmodule
| 8.118637 |
module tuner (
input [15:0] num,
output [16:0] tuned_num
);
localparam [16:0] piece = 17'd65536 / 17'd9;
assign tuned_num = (num >= 17'd65529) ? 17'd8 : num / piece;
endmodule
| 6.979321 |
module simple_piano (
input clk,
input keyC4,
keyC4h,
keyD4,
keyD4h,
keyE4,
keyF4,
keyF4h,
keyG4,
keyG4h,
keyA4,
keyA4h,
keyB4,
keyC5,
output reg [9:0] simpletone
);
wire [9:0] toneC4;
sin_anyfreq #(93664) C4 (
clk,
toneC4
);
wire [9:0] to... | 8.610757 |
modules: lookup_tables, SINE_LUT
*- Description: Generate arbitrary frequency 10-bit sin wave
*-
*- Example of Usage:
Refer to the STEPFPGA tutorial book Chapter 5 for more details
f_out = M * f_clk/(2^N), since f_clk = 12MHz, N = 32 bit, so we have:
M = f_out * 358
To obtain any desired frequency of the sin... | 6.976376 |
module simple_piano_top (
input clk,
input keyC4,
keyC4h,
keyD4,
keyD4h,
keyE4,
keyF4,
keyF4h,
keyG4,
keyG4h,
keyA4,
keyA4h,
keyB4,
keyC5,
output reg [9:0] simpletone
);
wire [9:0] toneC4;
sin_anyfreq #(93664) C4 (
clk,
toneC4
);
wire [9:0... | 8.197605 |
module simple_pic (
clk_i,
rst_i,
cyc_i,
stb_i,
adr_i,
we_i,
dat_i,
dat_o,
ack_o,
int_o,
irq
);
parameter is = 8; // Number of interrupt sources
parameter dwidth = 32;
//
// Inputs & outputs
//
// 8bit WISHBONE bus slave interface
input clk_i; // clock
inpu... | 7.271373 |
module simple_pipeline_behavioral (
input clk, // Clock
input [7:0] a,
b,
c,
d, // Data
output reg [7:0] f
); // Output Data
reg [7:0] y1, y2, y3, d1, d2;
// STAGE 1
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(posedge clk) begin
y1 ... | 7.408918 |
module SIMPLE_PIPELINE_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg [7:0] A, B, C, D;
reg CLK;
wire [7:0] F;
// FOR TESTING
reg [31:0] VECTORCOUNT, ERRORS;
reg [7:0] FEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
simple_pipeline_behavio... | 7.112782 |
module simple_ram #(
parameter width = 1,
parameter widthad = 1
) (
input clk,
input [widthad-1:0] wraddress,
input wren,
input [ width-1:0] data,
input [widthad-1:0] rdaddress,
output [ width-1:0] q
);
reg [width-1:0] mem[(2**widthad)-1:0];
reg [widthad-1:0] rd... | 8.038499 |
module is a simple single port RAM. This RAM is implemented in such a
way that Xilinx's tools will recognize it as a RAM and implement large
instances in block RAM instead of flip-flops.
The parameter SIZE is used to specify the word size. That is the size of
each entry in the RAM.
The parameter... | 9.737646 |
module simple_ram_dual_clock #(
parameter DATA_WIDTH = 64, //width of data bus
parameter ADDR_WIDTH = 20
//width of addresses buses
) (
input [DATA_WIDTH-1:0] data, //data to be written
input [ADDR_WIDTH-1:0] read_addr, //address for read operation
input [ADDR_WIDTH-1:0... | 7.653584 |
module simple_register #(
parameter SIZE = 8
) (
input wire clk,
input wire reset,
input wire [SIZE-1:0] idata,
input wire wen,
output reg [SIZE-1:0] odata
);
always @(posedge clk) begin
if (reset) odata <= 0;
else if (wen) odata = idata;
end
endmodule
| 7.087079 |
module simple_register_load #(
parameter N = 4
) (
input clk,
input load,
input [N - 1:0] I,
output [N - 1:0] Q
);
reg [N - 1:0] Q_reg, Q_next;
always @(posedge clk) begin
Q_reg <= Q_next;
end
// Next State logic
always @(load, I, Q_reg) begin
if (load) Q_next = I;
else Q_ne... | 7.087079 |
module Simple_Reg_w_Reset #(
parameter W = 4
) (
clk,
reset,
load,
out
);
//inputs
input [W-1:0] load;
input clk, reset;
//output
output reg [W-1:0] out;
initial begin
out <= 0;
end
always @(posedge clk) begin
//check reset
if (reset == 1) begin
out <= 0;
en... | 7.398106 |
module simple_rom (
clk,
addr,
rdata
);
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 24;
parameter ROM_DATA_FILE = "numbers.mem";
input clk;
input [ADDR_WIDTH-1:0] addr;
output reg [DATA_WIDTH-1:0] rdata;
reg [DATA_WIDTH-1:0] MY_ROM[0:2**ADDR_WIDTH-1];
initial $readmemh(ROM_DATA_FILE, M... | 8.078646 |
module Simple_Single_CPU (
clk_i,
rst_i
);
//I/O port
input clk_i;
input rst_i;
//Internal Signles
wire [31:0] alu_result, instr_o, writeData, ReadData1, ReadData2, pc_in_i, pc_out_o, signed_addr, after_extended, ALUin,
adder_out1, adder_out2, mux_jump_out, mux_jumpReg_out, MemRead_data;
wire... | 7.128434 |
module Simple_Single_CPU (
clk_i,
rst_i
);
//I/O port
input clk_i;
input rst_i;
//Internal Signles
wire [31:0] pc;
wire [31:0] pc_next;
wire [31:0] pc_back;
wire [31:0] pc_back_pre;
wire [31:0] instr_w;
wire [31:0] RSdata;
wire [31:0] RTdata;
wire [31:0] imm;
wire [31:0] Mux_ALUSrc_w... | 7.128434 |
module simple_single_rom (
input clk,
input [widthad-1:0] addr,
output [ width-1:0] q
);
parameter width = 1;
parameter widthad = 1;
parameter datafile = "none";
reg [width-1:0] mem[(2**widthad)-1:0];
reg [widthad-1:0] rdaddr;
initial begin
$readmemb(datafile, mem);
end
always @(... | 7.28811 |
module simple_spi_master_wb #(
parameter BASE_ADR = 32'h2100_0000,
parameter CONFIG = 8'h00,
parameter DATA = 8'h04
) (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
outpu... | 8.719715 |
module generic_sram_byte_en #(
parameter DATA_WIDTH = 32,
parameter ADDRESS_WIDTH = 4
) (
input i_clk,
input [ DATA_WIDTH-1:0] i_write_data,
input i_write_enable,
input [ADDRESS_WIDTH-1:0] i_address,
input [ DATA_WIDTH/8-1... | 7.001881 |
module simple_state_machine (
input clk,
input rstn,
input a,
output reg out
);
localparam S0 = 2'b00;
localparam S1 = 2'b01;
reg [1:0] state;
reg [1:0] next_state;
always @(negedge rstn or posedge clk) begin
if (!rstn) begin
state <= S0;
end else begin
state <= next_sta... | 6.817329 |
module Simple_Subt #(
parameter W = 8,
N = 3
) /*#(W=11)*/ //tam�o del exponente en 32 y 64 bits respectivamente
(
input wire [W-1:0] A,
input wire [N-1:0] B,
output wire [W-1:0] Y
);
assign Y = A - B;
endmodule
| 8.146224 |
module simple_sync_sig #(
parameter RST_VAL = 1'b0,
parameter WIDTH = 1
) (
input wire dst_clk,
input wire dst_rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
(* KEEP = "TRUE" *)reg [WIDTH-1:0] sync_reg_1;
(* KEEP = "TRUE" *)reg [WIDTH-1:0] sync_reg_2;
always @(posedge d... | 7.529254 |
module example (
a,
b,
c,
d
);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
input a;
input b;
input c;
output d;
NOT _13_ (
.A(_05_),
.Y(_08_)
);
NOT _14_... | 6.978445 |
module simple_timer #(
parameter BASE = 0
) (
input clk,
input reset,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
output reg onetime_int,
output reg periodic_int
);
reg [31:0] onetime_ctr;
always @(posedge clk)
if (reset) begin
onetime_int <= 0;
oneti... | 7.288999 |
modules: divider_integer
*- Description: Using a state machine to control two RGB LEDs to simulate a traffic light
*- Example of Usage:
- You may assign the output directly to the 2 RGB LEDs on the STEPFPGA board
* - Read more details in Chapter 5 (simple traffic light) of the tutorial book.
*- Cop... | 7.015432 |
module divider_integer #(
parameter WIDTH = 24,
parameter N = 12000000
) (
input clk,
output reg clkout
);
reg [WIDTH-1:0] cnt;
always @(posedge clk) begin
if (cnt >= (N - 1)) cnt <= 1'b0;
else cnt <= cnt + 1'b1;
clkout <= (cnt < N / 2) ? 1'b1 : 1'b0;
end
endmodule
| 6.687714 |
module simple_uart #(
parameter TXDEPTH = 1,
parameter RXDEPTH = 1,
parameter CLKDIV_DEFAULT = 16'd0
) (
input clk_i,
input rst_i,
input we_i,
input stb_i,
input cyc_i,
output reg ack_o,
input [2:0] adr_i,
input [31:0] dat_i,
output reg [31:0] dat_o,
output rx_int_o,
... | 8.007311 |
module simple_uart_receiver (
i_clk,
i_rst_n,
i_rx,
o_dat,
o_dat_vld
);
input i_clk;
input i_rst_n;
input i_rx;
output reg o_dat_vld;
output [7:0] o_dat;
parameter RCONST = 1085; //230400bps for 250MHz i_clk
reg [10:0] baud_rate_cnt;
reg [ 3:0] bit_cnt;
reg [ 7:0] shift_reg;
... | 6.61118 |
module simple_uart_rx #(
parameter DEPTH = 0
) (
input clk,
input rst,
output [7:0] fifo_out,
input fifo_read,
output [7:0] fifo_level,
output fifo_empty,
input [15:0] clkdiv,
input rx
);
reg rx_d1, rx_d2;
always @(posedge clk)
if (rst) {rx_d2, rx_d1} <= 0;
else {rx_d2, ... | 6.61118 |
module simple_weird2 (
input a
, input b
, output [1:0] z
);
assign z[0] = a | b;
assign z[1] = a & b;
endmodule
| 6.766052 |
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305 |
module simplified_snn #(
parameter DW = 16,
INPUTNUM = 8,
EXCNUM = 2,
INT_DW = 8
) (
// Clock, reset and enable
input wire clk,
input wire rst,
input wire en
);
wire signed [DW + INT_DW - 1 : 0] synapses_results[INPUTNUM - 1 : 0][EXCNUM - 1 : 0];
wire signed [DW + INT_DW - 1 : 0] af... | 6.768951 |
module X_AND16 (
O,
I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7,
I8,
I9,
I10,
I11,
I12,
I13,
I14,
I15
);
parameter LOC = "UNPLACED";
output O;
input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
and (O, I0, I1, I2, I3, I4, I5, I6, ... | 6.651338 |
module X_BSCAN_SPARTAN2 (
DRCK1,
DRCK2,
RESET,
SEL1,
SEL2,
SHIFT,
TDI,
UPDATE,
TDO1,
TDO2
);
input TDO1, TDO2;
output DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE;
parameter LOC = "UNPLACED";
pulldown (TDI);
pulldown (RESET);
pulldown (SHIFT);
pulldown (U... | 6.811719 |
module X_BSCAN_SPARTAN3 (
CAPTURE,
DRCK1,
DRCK2,
RESET,
SEL1,
SEL2,
SHIFT,
TDI,
UPDATE,
TDO1,
TDO2
);
input TDO1, TDO2;
output CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE;
parameter LOC = "UNPLACED";
pulldown (DRCK1);
pulldown (DRCK2);
pulldow... | 6.811719 |
module X_BSCAN_VIRTEX (
DRCK1,
DRCK2,
RESET,
SEL1,
SEL2,
SHIFT,
TDI,
UPDATE,
TDO1,
TDO2
);
input TDO1, TDO2;
output DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE;
parameter LOC = "UNPLACED";
pulldown (TDI);
pulldown (RESET);
pulldown (SHIFT);
pulldown (UPD... | 6.666319 |
module X_BSCAN_VIRTEX2 (
CAPTURE,
DRCK1,
DRCK2,
RESET,
SEL1,
SEL2,
SHIFT,
TDI,
UPDATE,
TDO1,
TDO2
);
input TDO1, TDO2;
output CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE;
parameter LOC = "UNPLACED";
pulldown (DRCK1);
pulldown (DRCK2);
pulldown... | 6.666319 |
module X_BSCAN_VIRTEX4 (
CAPTURE,
DRCK,
RESET,
SEL,
SHIFT,
TDI,
UPDATE,
TDO
);
output CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE;
input TDO;
reg SEL_zd;
parameter integer JTAG_CHAIN = 1;
parameter LOC = "UNPLACED";
pulldown (DRCK);
pulldown (RESET);
pulldown (SEL)... | 6.666319 |
module X_BSCAN_VIRTEX5 (
CAPTURE,
DRCK,
RESET,
SEL,
SHIFT,
TDI,
UPDATE,
TDO
);
output CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE;
input TDO;
reg SEL_zd;
parameter integer JTAG_CHAIN = 1;
parameter LOC = "UNPLACED";
pulldown (DRCK);
pulldown (RESET);
pulldown (SEL)... | 6.666319 |
module x_clkdll_maximum_period_check (
clock,
rst
);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;
time clock_edge;
time clock_period;
initial begin
clock_edge = 0;
clock_period = 0;
end
always @(posedge clock) begin
clock_edge <= $time;
... | 6.843597 |
module x_clkdlle_maximum_period_check (
clock,
rst
);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;
time clock_edge;
time clock_period;
initial begin
clock_edge <= 0;
clock_period <= 0;
end
always @(posedge clock) begin
clock_edge <= $time;... | 7.085301 |
module X_CLK_DIV (
CLKDV,
CDRST,
CLKIN
);
parameter DIVIDE_BY = 2;
parameter DIVIDER_DELAY = 0;
input CDRST, CLKIN;
parameter LOC = "UNPLACED";
output CLKDV;
integer CLOCK_DIVIDER;
integer RESET_WAIT_COUNT;
integer START_WAIT_COUNT;
integer DELAY_RESET;
integer DELAY_START;
integer S... | 6.81624 |
module x_dcm_clock_divide_by_2 (
clock,
clock_type,
clock_out,
rst
);
input clock;
input clock_type;
input rst;
output clock_out;
reg clock_out;
reg clock_div2;
reg [2:0] rst_reg;
initial begin
clock_out = 1'b0;
clock_div2 = 1'b0;
end
always @(posedge clock) clock_div2 <=... | 6.910797 |
module x_dcm_maximum_period_check (
clock
);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
time clock_edge;
time clock_period;
initial begin
clock_edge = 0;
clock_period = 0;
end
always @(posedge clock) begin
clock_edge <= $time;
clock_period <= $time -... | 7.071183 |
module x_dcm_adv_clock_divide_by_2 (
clock,
clock_type,
clock_out,
rst
);
input clock;
input clock_type;
input rst;
output clock_out;
reg clock_out;
reg clock_div2;
reg [2:0] rst_reg;
initial begin
clock_out = 1'b0;
clock_div2 = 1'b0;
end
always @(posedge clock) clock_div... | 6.620628 |
module x_dcm_adv_maximum_period_check (
clock,
rst
);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;
time clock_edge;
time clock_period;
initial begin
clock_edge = 0;
clock_period = 0;
end
always @(posedge clock) begin
clock_edge <= $time;
... | 7.709591 |
module x_dcm_adv_clock_lost (
clock,
enable,
lost,
rst
);
input clock;
input enable;
input rst;
output lost;
reg lost_r, lost_f, lost;
time clock_edge;
reg [63:0] period;
reg clock_low, clock_high;
reg clock_posedge, clock_negedge;
reg clock_second_pos, clock_second_neg;
initial... | 6.620628 |
module x_dcm_sp_maximum_period_check (
clock,
rst
);
parameter clock_name = "";
parameter maximum_period = 0;
input clock;
input rst;
time clock_edge;
time clock_period;
initial begin
clock_edge = 0;
clock_period = 0;
end
always @(posedge clock) begin
clock_edge <= $time;
... | 7.301584 |
module X_KEEPER (
O
);
inout O;
parameter LOC = "UNPLACED";
wire O_int;
reg I;
always @(O_int)
if (O_int) I <= 1;
else I <= 0;
buf (pull1, pull0) (O, I);
buf (O_int, O);
specify
(O => O) = (0: 0: 0, 0: 0: 0);
endspecify
endmodule
| 6.911627 |
module X_LATCH (
O,
CLK,
I,
RST,
SET
);
parameter INIT = 1'b0;
parameter LOC = "UNPLACED";
output O;
input CLK, I, RST, SET;
wire nrst, nset, in_clk_enable;
reg notifier;
wire o_out;
reg rst_int, set_int;
reg o_reg = INIT;
tri0 GSR = glbl.GSR;
buf O1 (O, o_reg);
alway... | 6.572167 |
module X_LATCHE (
O,
CLK,
GE,
I,
RST,
SET
);
parameter INIT = 1'b0;
parameter LOC = "UNPLACED";
output O;
input CLK, GE, I, RST, SET;
wire nrst, nset, in_out;
wire in_clk_enable, ge_clk_enable, set_clk_enable;
wire o_out;
reg o_reg = INIT;
reg rst_int, set_int;
reg notif... | 6.594904 |
module X_MUX2 (
O,
IA,
IB,
SEL
);
output O;
input IA, IB, SEL;
parameter LOC = "UNPLACED";
mux(
O, IA, IB, SEL
); specify
(IA => O) = (0: 0: 0, 0: 0: 0);
(IB => O) = (0: 0: 0, 0: 0: 0);
(SEL => O) = (0: 0: 0, 0: 0: 0);
specparam PATHPULSE$ = 0;
endspecify
endmodul... | 6.528689 |
module X_OR16 (
O,
I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7,
I8,
I9,
I10,
I11,
I12,
I13,
I14,
I15
);
parameter LOC = "UNPLACED";
output O;
input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
or (O, I0, I1, I2, I3, I4, I5, I6, I7... | 6.699554 |
module X_SRLC16E (
Q,
Q15,
A0,
A1,
A2,
A3,
CE,
CLK,
D
);
parameter INIT = 16'h0000;
parameter LOC = "UNPLACED";
output Q, Q15;
input A0, A1, A2, A3, CE, CLK, D;
reg [15:0] data;
wire [ 3:0] addr;
wire d_in, ce_in, clk_in;
reg q_out, q15_out;
reg notifier;
buf... | 6.533195 |
module X_SRLC32E (
Q,
Q31,
A,
CE,
CLK,
D
);
parameter INIT = 32'h00000000;
parameter LOC = "UNPLACED";
output Q;
output Q31;
input [4:0] A;
input CE, CLK, D;
reg [31:0] data;
wire [ 4:0] addr;
wire d_in, ce_in, clk_in;
reg q_out;
reg notifier;
buf b_d (d_in, D);
... | 7.13322 |
module X_XOR16 (
O,
I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7,
I8,
I9,
I10,
I11,
I12,
I13,
I14,
I15
);
parameter LOC = "UNPLACED";
output O;
input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15;
xor (O, I0, I1, I2, I3, I4, I5, I6, ... | 6.708118 |
module simram (
clock,
reset,
addr_i,
clk_en_i,
clk_i,
rst_i,
wr_data_i,
wr_en_i,
rd_data_o
);
input [7:0] addr_i;
input clk_en_i;
input clk_i;
input rst_i;
input [15:0] wr_data_i;
input wr_en_i;
output [15:0] rd_data_o;
// ------------------------------
// ... | 7.851599 |
module simsd (
input wire clk,
input wire cs,
input wire [31:0] bus_addr,
input wire [31:0] bus_wr_val,
input wire [3:0] bus_bytesel,
output reg bus_ack,
output reg [31:0] bus_data
);
reg [31:0] readval;
initial begin
bus_ack = 1'b0;
bus_data = 32'b0;
initspi();
end
... | 6.712465 |
module simu04 ();
reg clk = 1;
always #1 clk <= !clk;
reg reset = 0;
reg enable = 1;
wire [15:0] dIn;
wire [15:0] dOut;
wire [15:0] addr;
wire write_en;
wire quit;
wire debug;
wire content_ok;
reflet_cpu #(
.wordsize(16)
) cpu (
.clk(clk),
.reset(reset),
.enable(enab... | 6.627228 |
module simu05_tb;
reg clk = 0;
always #1 clk = !clk;
reg reset = 1;
wire [6:0] segments;
wire [3:0] seg_select;
wire seg_colon;
wire seg_dot;
clock_cpu cpu (
.clk(clk),
.reset_in(reset),
.debug(),
.quit(),
.gpi(16'h0),
.gpo(),
.tx(),
.rx(1'b1),
.p... | 6.701743 |
module simu7_mcu #(
parameter clk_freq = 1000000
) (
input clk,
input reset_in,
input rx,
output tx
);
//reset control
wire reset, blink;
reflet_blink reset_bootstrap (
.clk(clk),
.out(blink)
);
assign reset = reset_in & !blink;
//system bus and interrupt request
wire ... | 7.307663 |
module simu08_tb ();
reg clk = 0;
always #1 clk <= !clk;
reg reset_cpu = 0;
reg reset_uart = 0;
wire rx, tx, synth_out;
simu8_mcu #(
.clk_freq(2_000_000)
) mcu (
.clk(clk),
.reset_in(reset_cpu),
.synth_out(synth_out),
.rx(rx),
.tx(tx)
);
uart_sending #(
.cl... | 6.955926 |
module simu8_mcu #(
parameter clk_freq = 1000000
) (
input clk,
input reset_in,
output synth_out,
input rx,
output tx
);
//reset control
wire reset, blink;
reflet_blink reset_bootstrap (
.clk(clk),
.out(blink)
);
assign reset = reset_in & !blink;
//system bus and int... | 7.220712 |
module simu09_tb ();
reg clk = 0;
always #1 clk <= !clk;
reg reset_uart = 0;
wire rx, quit, debug, debug_tx;
reflet_16bit_controller #(
.clk_freq(1000000),
.debug_output(1),
.data_size('h2000),
.inst_size(8192),
.enable_interrupt_mux(1),
.enable_gpio(0),
.enable_ti... | 6.757917 |
module simu10_tb ();
reg clk = 0;
always #1 clk <= !clk;
reg reset_cpu = 0;
wire h_sync;
wire v_sync;
wire [1:0] R_out;
wire [1:0] G_out;
wire [1:0] B_out;
simu10_mcu #(
.clk_freq(20_000_000)
) mcu (
.clk(clk),
.reset_in(reset_cpu),
.h_sync(h_sync),
.v_sync(v_sync),... | 7.220492 |
module simu10_mcu #(
parameter clk_freq = 1000000
) (
input clk,
input reset_in,
output h_sync,
output v_sync,
output [1:0] R_out,
output [1:0] G_out,
output [1:0] B_out
);
//reset control
wire reset, blink;
reflet_blink reset_bootstrap (
.clk(clk),
.out(blink)
);
... | 6.931624 |
module timer1 (
clk,
rst,
start_timer1,
time_up1
);
input clk, rst;
input start_timer1;
output reg time_up1;
reg [31:0] counter;
always @(posedge clk or posedge rst) begin
if (rst) begin
counter <= 0;
time_up1 <= 0;
end else begin
if (start_timer1) begin
i... | 6.616152 |
module simula;
reg CLK;
wire [7:0] saida_pc;
wire [7:0] saida_instrucao;
wire [7:0] valorlido;
wire [7:0] valorescrito;
wire [7:0] endereco;
wire EscreveMemoria;
wire LeMemoria;
/* Declaracao do contador de estagios */
reg [15:0] counter;
integer i;
BancoInstrucao instrucao (
CLK,
... | 7.046162 |
module simulacao ();
reg clock = 0;
always #1 clock = !clock;
/*pc*/
wire [31:0] readAddress;
pc pc (
clock,
novoPC,
readAddress
);
/*instruction memory*/
wire [31:0] Instruction;
instructionmemory instructionmemory (
readAddress,
Instruction
);
/*mux1*/
wire ... | 7.066937 |
module simulare ();
reg b1, b5, b10;
reg clk, reset;
wire cola;
wire r1, r2;
automat a (
b1,
b5,
b10,
clk,
reset,
cola,
r1,
r2
);
always #20 clk = ~clk;
initial begin
b1 = 0;
b5 = 0;
b10 = 0;
clk = 0;
reset = 1;
#50 b1 = 0;
b5 ... | 6.575123 |
module simulate0 (
// Inputs
CLKA,
// Outputs
data
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input CLKA;
//--------------------------------------------------------------------
// ... | 6.684029 |
module simulated_io (
input clock,
input reset,
input io_read,
input io_write,
output ioack,
output [15:0] data_in,
input [15:0] data_out
);
reg [15:0] inputs [65535:0];
reg [15:0] outputs[65535:0];
reg [15:0] inaddr, outaddr;
reg prev_io_read, prev_io_write;
assign data_in = (... | 7.003473 |
module simulated_mem (
input clk,
input [31:0] addr,
input [3:0] mask,
input enable,
input cmd,
input [31:0] write_data,
output reg [31:0] load_data,
output reg valid
);
localparam MEMORY_SIZE = (1 << 14);
reg [31:0] memory[MEMORY_SIZE - 1:0];
wire [29:0] word_addr = addr[31:2];
... | 6.782645 |
module simulated_memory #(
parameter memdata = "test2.txt"
) (
input read,
input write,
input [15:0] addr,
input [15:0] data_out,
output [15:0] data_in,
output ack
);
reg [15:0] contents[65535:0];
wire dread;
assign data_in = dread ? contents[addr] : 16'bX;
assign #5 dread = read;... | 6.782645 |
module Fir;
reg clk, reset_n;
reg [15:0] x_in;
reg [15:0] data_mem[0:15];
integer i;
wire [23:0] y_out;
always #`clock clk = ~clk;
initial begin
clk = 0;
reset_n = 1;
#20 reset_n = 0;
#10 reset_n = 1;
end
initial begin
$readmemh("tir.txt", data_mem);
end
always @(posedge cl... | 6.50049 |
module Project1Test ();
//Input Registers of ALUSystem
reg [1:0] RF_OutASel;
reg [1:0] RF_OutBSel;
reg [1:0] RF_FunSel;
reg [3:0] RF_RegSel;
reg [3:0] ALU_FunSel;
reg [1:0] ARF_OutCSel;
reg [1:0] ARF_OutDSel;
reg [1:0] ARF_FunSel;
reg [2:0] ARF_RegSel;
reg IR_LH;
reg IR_Enable;
reg... | 7.239416 |
module SequenceCounterTest ();
reg CLK;
reg Reset;
wire [3:0] T;
SequenceCounter uut (
CLK,
Reset,
T
);
initial begin
CLK = 0;
forever #20 CLK = ~CLK;
end
initial begin
Reset = 0;
#235 Reset = 1;
#2 Reset = 0;
end
endmodule
| 7.141471 |
module HardwiredControlUnitTest ();
reg CLK;
wire Reset;
wire [2:0] T;
wire [7:0] R1;
wire [7:0] R2;
wire [7:0] R3;
wire [7:0] R4;
wire [7:0] PC;
wire [7:0] AR;
wire [7:0] SP;
HardwiredControlUnit uut (
.CLK(CLK),
.Reset_out(Reset),
.T_out(T),
.R1_out(R1),
.R2_out(R... | 7.607372 |
module to limit the time the simulation runs. Otherwise,
a bug in the simulation might let it freeze or run forever,
which is always undesirable, specially during a daily build.
The simulation timeout is based on the simulated clock ticks,
and not real (wall clock) time, in order to be independent from
... | 7.521663 |
module simulation_top_tb ();
localparam CLK_PERIOD = 20;
reg clk;
initial begin
clk <= 0;
forever begin
#(CLK_PERIOD / 2);
clk <= ~clk;
end
end
localparam CORE_COUNT = 8;
reg rstN, startN;
wire processor_ready, processDone;
simulation_top #(
.CORE_COUNT(CORE_COUNT)
)... | 7.339034 |
module simulator ();
reg sys_rst_n;
reg sys_clk;
initial begin
sys_rst_n = 1;
sys_clk = 0;
#40 sys_rst_n = 1'b0;
end
always #20 sys_clk <= ~sys_clk;
openmips_min_sopc openmips_min_sopc0 (
sys_clk,
sys_rst_n
);
endmodule
| 6.818339 |
module start wrting on terminal when the buffer becomes full or wait counter reach its limit.
* The buffer perevents the conflict between multiple simulation UART messages
* Wait counter reset by each individual write on buffer
***************************************/
// synthesis translate... | 8.150401 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
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