code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module mux_2x1_5 (
ip0,
ip1,
sel,
out
);
input sel;
input [4:0] ip1;
input [4:0] ip0;
output reg [4:0] out;
always @(*) begin
if (sel == 1'b1) begin
out = ip1;
end else begin
out = ip0;
end
end
endmodule
| 6.663991 |
module mux_2x1_32 (
ip0,
ip1,
sel,
out
);
input sel;
input [31:0] ip1;
input [31:0] ip0;
output reg [31:0] out;
always @(*) begin
if (sel == 1'b1) begin
out = ip1;
end else begin
out = ip0;
end
end
endmodule
| 7.462987 |
module signext (
ip,
op
);
input [15:0] ip;
output [31:0] op;
reg [31:0] ext;
always @(*) begin
ext[15:0] = ip;
ext[31:16] = {16{ip[15]}};
end
assign op = ext;
endmodule
| 7.970829 |
module SingleCycleProc (
CLK,
Reset_L,
startPC,
currentPC,
dMemOut
);
input CLK;
input Reset_L;
input [63:0] startPC;
output [63:0] currentPC;
output [63:0] dMemOut;
//PC Logic
wire [63:0] nextPC;
reg [63:0] currentPC;
//Instruction Decode
wire [31:0] currentInstruction;
wir... | 7.687219 |
module SingleCycleProcessor (
CLK,
RegSrc,
RegWrite,
ALUSrc,
PCSrc,
MemWrite,
MemtoReg,
ImmSrc
);
input wire CLK;
output wire RegSrc;
output wire RegWrite;
output wire ALUSrc;
output wire PCSrc;
output wire MemWrite;
output wire MemtoReg;
output wire ImmSrc;
wire [3:... | 7.687219 |
module SingleCycleProcessor_tb ();
reg CLK;
reg [31:0] testvector[0:15];
integer number;
SingleCycleProcessor Single_Cycle_Processor (
.CLK(CLK),
.MemtoReg(MemtoReg),
.MemWrite(MemWrite),
.ImmSrc(ImmSrc),
.PCSrc(PCSrc),
.ALUSrc(ALUSrc),
.RegWrite(RegWrite),
.RegSr... | 7.687219 |
module: SingleCycleProc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
////////////////////////////////////////////////////////////////////////////////
`define STRLEN 32
`define HalfClockPeriod 60
`define ClockPeriod `HalfClockPeriod * 2
module SingleCycleProcTest_v;
/... | 6.596 |
module SingleCycle_MIPS (
clk,
rst_n,
IR_addr,
IR,
RF_writedata,
ReadDataMem,
CEN,
WEN,
A,
ReadData2,
OEN
);
//==== in/out declaration =================================
//-------- processor ----------------------------------
input clk, rst_n;
input [31:0] IR;
outpu... | 7.100802 |
module SingleCycle_tb ();
reg reset, clock;
// Change the TopLevel module's name to yours
SingleCycle singlecycle (
.reset(reset),
.clock(clock)
);
integer k;
initial begin
// posedge clock
// Hold reset for one cycle
reset = 1;
clock = 0;
#1;
clock = 1;
#1;
cl... | 7.04878 |
module SingleDisplay7 (
iData,
iSel,
ena,
oData,
oSel
);
input [3:0] iData;
input [2:0] iSel;
input ena;
output [6:0] oData;
output [7:0] oSel;
//ѡλ
assign oSel[7] = ~(ena & iSel[2] & iSel[1] & iSel[0]);
assign oSel[6] = ~(ena & iSel[2] & iSel[1] & (~iSel[0]));
assign oSel[5] = ~(... | 7.366028 |
module SingleInstruction (
input clk,
input wire [31:0] instruction,
input wire [31:0] pcNext,
output wire [31:0] aluResult,
output wire [31:0] bus_address,
output wire [31:0] bus_wr_data,
input wire [31:0] bus_read_data,
output wire [ 2:0] bus_write_length,
output wi... | 8.440709 |
module MuxRegisterWriteDataSource (
input [ 1:0] sourceSelection,
input [31:0] aluResult,
input [31:0] upperImmediateSignExtended,
input [31:0] pcNext,
input [31:0] mainMemory,
output [31:0] resultValue
);
reg [31:0] internal;
always @(*) begin
case (sourceSelection)
REG_SRC... | 7.398617 |
module ALURightInputSource (
input wire sourceSelection,
input wire [31:0] immediateSource,
input wire [31:0] registerSource,
output wire [31:0] resultValue
);
reg [31:0] internal_result;
// Selects source to feed ALU right input
always @(*) begin
case (sourceSelection)
ALU_SRC_IMMEDIA... | 7.221403 |
module ImmediateExtractor (
input [31:0] instruction,
output wire [31:0] result
);
wire [ 6:0] opcode = instruction[6:0];
wire [ 4:0] shamt = instruction[24:20];
wire [ 6:0] funct7 = instruction[31:25];
reg [31:0] result_internal;
always @(*) begin
casez ({
funct7, opcode
})
14... | 7.640358 |
module prevents multiple keys from being pressed at the same time
* by only accepting a single keypress from KEY[3-0]. If multiple keys are
* pressed, the output is zero.
*
*/
// Declare input and output ports.
module SingleKeypressFilter (input [3:0] key,
output reg [3:0] filtered... | 7.83378 |
module singleLED (
input [4:0] data,
output reg [7:0] LEDout
);
always @(data) begin
case (data)
5'b00000: LEDout = 8'b11111100;
5'b00001: LEDout = 8'b01100000;
5'b00010: LEDout = 8'b11011010;
5'b00011: LEDout = 8'b11110010;
5'b00100: LEDout = 8'b01100110;
5'b00101: LED... | 6.858774 |
module SingleMemory (
input clk,
input rst,
input [11:0] addr,
input [31:0] data_in,
//data mem
input mem_read,
input mem_write,
input [2:0] F3,
//output
output reg [31:0] data_out
);
parameter mem_size = 4096;
parameter offset = 2048;
reg [8:0] mem[0:(mem_size-1)];
... | 8.112228 |
module singleNeuron #(
parameter N = 10,
parameter DW = 8,
parameter DW_VEC = N * DW
) (
input wire clk,
input wire rst,
input wire start,
input wire shiftEn,
input wire [DW_VEC-1:0] in_vec,
input wire [DW_VEC-1:0] w_vec,
output wire [7:0] out,
output wire ready
);
functio... | 7.453483 |
module SinglePortDRAM #(
parameter DATA = 32,
parameter ADDR = 32,
parameter MEM_SIZE = 10
) (
// Port
input wire clk,
input wire wr,
input wire [ADDR - 1:0] addr,
input wire [DATA - 1:0] din,
output reg [DATA - 1:0] dout
);
//memory
reg [31 : 0] m... | 7.704526 |
module SinglePortNeuronRAM #(
parameter INTEGER_WIDTH = 16,
parameter DATA_WIDTH_FRAC = 32,
parameter DATA_WIDTH = INTEGER_WIDTH + DATA_WIDTH_FRAC,
parameter TREF_WIDTH = 5,
parameter NEURON_WIDTH_LOGICAL = 11,
parameter WORD_WIDTH = (DATA_WIDTH*6)+(TREF_WIDTH+3)+(NEURON_WIDTH_LOGICAL)+2, //F... | 7.345718 |
module SinglePortOffChipRAM #(
parameter WORD_WIDTH = 32 + 32,
parameter ADDR_WIDTH = 25,
parameter NUM_ROWS = 0,
parameter NUM_COLS = 0,
parameter FILENAME = "weights_bin.mem"
) (
input Clock,
input Reset,
input ChipEnable,
input WriteEnable,
input [(WORD_WIDTH-1):0] Inpu... | 7.075945 |
module Single_Port_RAM (
clk,
rst,
Wr_Rd,
valid,
ADDR,
WDATA,
RDATA,
ready
);
parameter N = 4; //No. of Address Lines
parameter D = 16; //Depth of Memory
parameter W = 8; //Width of Memory
input clk, rst, Wr_Rd, valid;
input [N-1:0] ADDR;
input [W-1:0] WDATA;
output [W... | 8.183175 |
module singlePulseDebounce (
input i_clk,
input i_button,
output reg o_press
);
integer counter = 0;
parameter clockCount = 1000000;
always @(posedge i_clk) begin
if ((counter < clockCount) & i_button) counter <= counter + 1;
else if (!i_button) counter <= 0;
end
always @(pose... | 6.581667 |
module SinglePulseGene (
clk,
rst_n,
pulse1start,
pulse1end,
startclock,
gpio
);
input clk;
input rst_n;
input [31:0] pulse1start;
input [31:0] pulse1end;
input startclock;
output reg [5:0] gpio;
reg startint1 = 0;
reg startint2 = 0;
reg [40:0] counter; //32 位记... | 7.734424 |
module singlereg (
clk,
rst,
wr,
rd,
we
);
parameter WIDTH = 8;
input clk;
input rst;
input [WIDTH-1:0] wr;
output [WIDTH-1:0] rd;
input we;
reg [WIDTH-1:0] data;
assign rd = data;
always @(posedge clk) begin
if (rst) data <= 0;
else if (we) data <= wr;
end
endmodule... | 9.189022 |
module SingleSM (
input wire CLK,
input wire RST,
input wire start_i,
output reg idle_o,
input wire idle_i,
output reg start_o,
input wire pb_rdy_i,
output reg pb_start_o,
output wire [1:0] fsm_o
);
// from/to SM(m)
// from... | 7.903308 |
module SingleStage (
input a,
input b,
input cin,
output cout,
output s
);
assign s = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 7.54112 |
module single_7seg (
input wire [3:0] numDigit,
input digitEnable,
output reg [6:0] digitDrive
);
always @(digitEnable or numDigit) begin
if (digitEnable) begin
case (numDigit)
4'h0: digitDrive[6:0] <= 7'h01;
4'h1: digitDrive[6:0] <= 7'h4F;
4'h2: digitDrive[6:0] <= 7'h12;... | 6.783583 |
module single_7seg_test (
input clk,
output reg [7:0] se7enDriver
);
reg [24:0] clockCounter;
reg [ 3:0] numberCounter;
wire [ 3:0] numberVal;
single_7seg mySegger (
.numDigit(numberVal),
.digitEnable(1)
);
assign numberVal = numberCounter;
always @(posedge clk) begin
if (clockCo... | 6.969677 |
module single_add (
op1,
op2,
out
);
input [31:0] op1;
input [31:0] op2;
output [31:0] out;
assign out = op1 + op2;
endmodule
| 7.3839 |
module adderTB ();
reg clk = 0, rst = 1;
reg [31:0] a, b;
wire [31:0] z;
reg a_stb, b_stb, z_ack;
wire a_ack, b_ack, z_stb;
always #10 clk = ~clk; // 25MHz
adder adder_39759952 (
.clk(clk),
.rst(rst),
.input_a(a),
.input_a_stb(a_stb),
.input_a_ack(a_ack),
.input_b(b)... | 6.822313 |
module single_alu (
i_r,
i_s,
i_aluc,
o_zf,
o_alu
);
input [31:0] i_r; //r input
input [31:0] i_s; //s input
input [2:0] i_aluc; //i_aluc: ctrl input
output o_zf; //o_zf: zero flag output
output [31:0] o_alu; //o_alu: alu result output
reg o_zf;
reg [31:0] o_alu;
//ALU CONTR... | 6.840397 |
module: single_alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module single_alu_test;
// Inputs
reg [31:0] i_r;
reg [31:0] i_s;
reg [2:0] i_aluc;
// Outputs
wire o_zf;
wire [3... | 6.603759 |
module single_async_distributed_ram #(
parameter RAM_WIDTH = 512, // Element bits.
parameter RAM_ADDR_BITS = 8
) // Address of array.
(
input clk,
input [RAM_ADDR_BITS-1:0] address,
input [ RAM_WIDTH-1:0] input_data,
input wr_enb,
output [ ... | 8.818595 |
module box (
(* invertible_pin="INV_A" *)
input wire A,
input wire B, (* invertible_pin="INV_C" *)
input wire C,
input wire D,
output wire Y
);
parameter [0:0] INV_A = 1'b0;
parameter [0:0] INV_C = 1'b0;
endmodule
| 7.681437 |
module top(
input wire [3:0] di,
output wire do
);
wire [3:0] d;
\$_NOT_ n0 (.A(di[0]), .Y(d[0]));
\$_NOT_ n1 (.A(di[1]), .Y(d[1]));
\$_NOT_ n2 (.A(di[2]), .Y(d[2]));
\$_NOT_ n3 (.A(di[3]), .Y(d[3]));
box #(.INV_A(1'b1)) the_box (
.A (d[0]),
.B (d[1]),
.... | 6.776298 |
module single_bit_b_pe (
input wire b,
input wire [`DATA_WIDTH - 1 : 0] a,
input wire [`DATA_WIDTH - 1 : 0] g,
input wire t_i1_m1,
input wire [`DATA_WIDTH - 1 : 0] t_i1_j1,
output wire [`DATA_WIDTH - 1 : 0] t_i_j
);
generate
genvar j;
for (j = `DATA_WIDTH - 1; j >= 0; j = j - 1) beg... | 7.299457 |
module FIFO (
clk,
reset,
data_in,
put,
get,
data_out,
fillcount,
empty,
full
);
//----------parameters--------------
parameter ADDR_WIDTH = 4;
parameter DEPTH_P2 = 1 << ADDR_WIDTH;
parameter WIDTH = 8;
//-----------------------------------
input [WIDTH-1:0] data_in;
... | 6.626407 |
module FIFO (
clk,
reset,
data_in,
put,
get,
data_out,
fillcount,
empty,
full
);
//----------parameters--------------
parameter ADDR_WIDTH = 3;
parameter DEPTH_P2 = 1 << ADDR_WIDTH;
parameter WIDTH = 8;
//-----------------------------------
input [WIDTH-1:0] data_in;
... | 6.626407 |
module FIFO (
clk,
reset,
data_in,
put,
get,
data_out,
fillcount,
empty,
full
);
//----------parameters--------------
parameter ADDR_WIDTH = 3;
parameter DEPTH_P2 = 1 << ADDR_WIDTH;
parameter WIDTH = 16;
//-----------------------------------
input [WIDTH-1:0] data_in;... | 6.626407 |
module FIFO_expwidth (
clk,
reset,
data_in,
put,
get,
data_out,
fillcount,
empty,
full
);
input [31:0] data_in;
output [31:0] data_out;
output [3:0] fillcount;
input clk, reset, put, get;
output empty, full;
wire empty_a, full_a, empty_b, full_b;
FIFO F1 (
.p1(cl... | 6.697298 |
module FIFO_expwidth (
clk,
reset,
data_in,
put,
get,
data_out,
fillcount,
empty,
full
);
parameter ADDR_WIDTH = 3;
parameter DEPTH_P2 = 1 << ADDR_WIDTH;
parameter WIDTH = 32;
input [WIDTH-1 : 0] data_in;
input put, get, reset, clk;
output [WIDTH-1 : 0] data_out;
outp... | 6.697298 |
module : single_cycle_memory_subsystem
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to d... | 7.603959 |
module control (
opcode,
func,
zf,
sel_dest,
sel_data,
sel_pc,
sel_opA,
sel_opB,
wr_en,
data_wr,
alu_op
);
input [5:0] opcode;
input [5:0] func;
output [1:0] sel_dest;
output [1:0] sel_data;
output [1:0] sel_pc;
output [5:0] alu_op;
input zf;
output sel_opA, s... | 7.715617 |
module slowmem16 (rdy, rdata, addr, wdata, wtoo, strobe, clk);
output reg rdy = 0;
output reg `LINE rdata;
input `LINEADDR addr;
input `LINE wdata;
input wtoo, strobe, clk;
reg [7:0] busy = 0;
reg `LINEADDR maddr;
reg mwtoo;
reg `LINE mwdata;
reg `LINE m `LINES;
initial begin
// put your memory initialization code h... | 6.718967 |
module SingleCycleProc (
CLK,
Reset_L,
startPC,
dMemOut
);
input CLK, Reset_L;
input [31:0] startPC;
output [31:0] dMemOut;
wire [31:0] Data;
wire [31:0] Address;
wire [31:0] updated_PC_Address;
//SCC1 wires
wire RegDst;
wire ALUSrc;
wire MemToReg;
wire RegWrite;
wire MemRead... | 7.687219 |
module Program_Counter (
clk,
reset,
PC_in,
PC_out
);
input clk, reset;
input [6:0] PC_in;
output [6:0] PC_out;
reg [6:0] PC_out;
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) PC_out <= 0;
else PC_out <= PC_in;
end
endmodule
| 6.785422 |
module Register_File (
read_addr_1,
read_addr_2,
write_addr,
read_data_1,
read_data_2,
write_data,
RegWrite,
clk,
reset
);
input [4:0] read_addr_1, read_addr_2, write_addr;
input [31:0] write_data;
input clk, reset, RegWrite;
output [31:0] read_data_1, read_data_2;
reg [31... | 6.725474 |
module Data_Memory (
addr,
write_data,
read_data,
clk,
reset,
MemRead,
MemWrite
);
input [7:0] addr;
input [31:0] write_data;
output [31:0] read_data;
input clk, reset, MemRead, MemWrite;
reg [31:0] DMemory[63:0];
integer k;
wire [5:0] shifted_addr;
assign shifted_addr = addr... | 7.239913 |
module ALUControl (
ALUOp,
funct,
out_to_ALU
);
input [1:0] ALUOp;
input [5:0] funct;
output [3:0] out_to_ALU;
assign out_to_ALU[3] = 0;
assign out_to_ALU[2]=((~ALUOp[1])&(ALUOp[0])) | ((ALUOp[1])&(~ALUOp[0])&(~funct[3])&(~funct[2])&(funct[1])&(~funct[0])) | ((ALUOp[1])&(~ALUOp[0])&(funct[3])&(~f... | 8.639118 |
module Sign_Extension (
sign_in,
sign_out
);
input [15:0] sign_in;
output [31:0] sign_out;
assign sign_out[15:0] = sign_in[15:0];
assign sign_out[31:16] = sign_in[15] ? 16'b1111_1111_1111_1111 : 16'b0;
endmodule
| 6.651391 |
module Shift_Left_2_Branch (
shift_in,
shift_out
);
input [31:0] shift_in;
output [31:0] shift_out;
assign shift_out[31:0] = {shift_in[29:0], 2'b00};
endmodule
| 7.469131 |
module Shift_Left_2_Jump (
shift_in,
shift_out
);
input [25:0] shift_in;
output [27:0] shift_out;
assign shift_out[27:0] = {shift_in[25:0], 2'b00};
endmodule
| 7.469131 |
module Mux_N_bit (
in0,
in1,
mux_out,
control
);
parameter N = 32;
input [N-1:0] in0, in1;
output [N-1:0] mux_out;
input control;
assign mux_out = control ? in1 : in0;
endmodule
| 7.338689 |
module ALU (
inA,
inB,
alu_out,
zero,
control
);
input [31:0] inA, inB;
output [31:0] alu_out;
output zero;
reg zero;
reg [31:0] alu_out;
input [3:0] control;
always @(control or inA or inB) begin
case (control)
4'b0000: begin
zero <= 0;
alu_out <= inA & inB;
... | 7.331505 |
module ALU_add_only (
inA,
inB,
add_out
);
input [31:0] inA, inB;
output [31:0] add_out;
assign add_out = inA + inB;
endmodule
| 8.730539 |
module Dff_asy (
q,
d,
clk,
rst
);
input d, clk, rst;
output reg q;
always @(posedge clk or posedge rst)
if (rst == 1) q <= 0;
else q <= d;
endmodule
| 6.505392 |
module ssd_driver (
in_BCD,
out_SSD
);
input [3:0] in_BCD; // input in Binary-Coded Decimal
output [6:0] out_SSD; // output to Seven-Segment Display
reg [6:0] out_SSD;
always @(in_BCD) begin
case (in_BCD)
0: out_SSD = 7'b0000001;
1: out_SSD = 7'b1001111;
2: out_SSD = 7'b0010010;
... | 7.53888 |
module Program_Counter (
clk,
reset,
PC_in,
PC_out
);
input clk, reset;
input [7:0] PC_in;
output [7:0] PC_out;
reg [7:0] PC_out;
always @(posedge clk or posedge reset) begin
if (reset == 1'b1) PC_out <= 0;
else PC_out <= PC_in;
end
endmodule
| 6.785422 |
module Register_File (
read_addr_1,
read_addr_2,
write_addr,
read_data_1,
read_data_2,
write_data,
RegWrite,
clk,
reset
);
input [4:0] read_addr_1, read_addr_2, write_addr;
input [31:0] write_data;
input clk, reset, RegWrite;
output [31:0] read_data_1, read_data_2;
reg [31... | 6.725474 |
module Data_Memory (
addr,
write_data,
read_data,
clk,
reset,
MemRead,
MemWrite
);
input [7:0] addr;
input [31:0] write_data;
output [31:0] read_data;
input clk, reset, MemRead, MemWrite;
reg [31:0] DMemory[63:0];
integer k;
wire [5:0] shifted_addr;
assign shifted_addr = addr... | 7.239913 |
module ALUControl (
ALUOp,
funct,
out_to_ALU
);
input [1:0] ALUOp;
input [5:0] funct;
output [3:0] out_to_ALU;
assign out_to_ALU[3] = 0;
assign out_to_ALU[2]=((~ALUOp[1])&(ALUOp[0])) | ((ALUOp[1])&(~ALUOp[0])&(~funct[3])&(~funct[2])&(funct[1])&(~funct[0])) | ((ALUOp[1])&(~ALUOp[0])&(funct[3])&(~f... | 8.639118 |
module Sign_Extension (
sign_in,
sign_out
);
input [15:0] sign_in;
output [31:0] sign_out;
assign sign_out[15:0] = sign_in[15:0];
assign sign_out[31:16] = sign_in[15] ? 16'b1111_1111_1111_1111 : 16'b0;
endmodule
| 6.651391 |
module Shift_Left_2_Branch (
shift_in,
shift_out
);
input [31:0] shift_in;
output [31:0] shift_out;
assign shift_out[31:0] = {shift_in[29:0], 2'b00};
endmodule
| 7.469131 |
module Shift_Left_2_Jump (
shift_in,
shift_out
);
input [25:0] shift_in;
output [27:0] shift_out;
assign shift_out[27:0] = {shift_in[25:0], 2'b00};
endmodule
| 7.469131 |
module Mux_N_bit (
in0,
in1,
mux_out,
control
);
parameter N = 32;
input [N-1:0] in0, in1;
output [N-1:0] mux_out;
input control;
assign mux_out = control ? in1 : in0;
endmodule
| 7.338689 |
module ALU (
inA,
inB,
alu_out,
zero,
control
);
input [31:0] inA, inB;
output [31:0] alu_out;
output zero;
reg zero;
reg [31:0] alu_out;
input [3:0] control;
always @(control or inA or inB) begin
case (control)
4'b0000: begin
zero <= 0;
alu_out <= inA & inB;
... | 7.331505 |
module ALU_add_only (
inA,
inB,
add_out
);
input [31:0] inA, inB;
output [31:0] add_out;
assign add_out = inA + inB;
endmodule
| 8.730539 |
module Dff_asy (
q,
d,
clk,
rst
);
input d, clk, rst;
output reg q;
always @(posedge clk or posedge rst)
if (rst == 1) q <= 0;
else q <= d;
endmodule
| 6.505392 |
module ssd_driver (
in_BCD,
out_SSD
);
input [3:0] in_BCD; // input in Binary-Coded Decimal
output [6:0] out_SSD; // output to Seven-Segment Display
reg [6:0] out_SSD;
always @(in_BCD) begin
case (in_BCD)
0: out_SSD = 7'b0000001;
1: out_SSD = 7'b1001111;
2: out_SSD = 7'b0010010;
... | 7.53888 |
module single_dff (
input dff_clock,
input d,
output reg q
);
always @(posedge dff_clock) begin
q <= d;
end
endmodule
| 6.706786 |
module single_digit_decimal_adder (
PS2_DATA,
PS2_CLK,
clk,
rst,
ssd_ctrl,
show,
test,
test2
);
inout PS2_DATA, PS2_CLK;
input clk, rst;
output [3:0] ssd_ctrl;
output [7:0] show;
output [1:0] test;
reg [1:0] test;
always @* begin
test = sel;
end
output [5:0] test2;... | 7.277665 |
module single_digit_display (
input [3:0] digit,
output reg [6:0] seven_segments
);
always @*
case (digit)
'h0: seven_segments = 'b1000000; // a b c d e f g
'h1: seven_segments = 'b1111001;
'h2: seven_segments = 'b0100100; // --a--
'h3: seven_segments = 'b0110000; // | ... | 7.277665 |
module for a simple divider
// Written by Gandhi Puvvada Date: 7/17/98, 2/15/2008, 10/13/08
// rob tag is added for OoE divider Date:10/01/2014
// revised on 03/15/2015: "state" signal as output
// File name: Single_div.v
module single_divider (Xin, Yin, Start, Ack, Clk, Reset,
Quotient, Remainder, ta... | 9.18418 |
module single_divider_TB ();
reg clk = 0, rst = 1;
reg [31:0] a, b;
wire [31:0] z;
reg a_stb, b_stb, z_ack;
wire a_ack, b_ack, z_stb;
integer fd;
always #10 clk = ~clk; // 25MHz
divider_newton divider_0 (
.clk(clk),
.rst(rst),
.input_a(a),
.input_a_stb(a_stb),
.input_a_a... | 6.697348 |
module top (
input clock,
in,
output reg out
);
always @(posedge clock) out <= in;
endmodule
| 7.233807 |
module single_gpr (
rst, //reset
clk, //clock
i_adr1, //register index 1
i_adr2, //register index 2
i_adr3, //register index 3
i_wreg, //register to write
i_wdata, //data to write
i_wen, //write enable
o_op1, //read data1, out
o_op2, //read data2, out
o_op3 //read ... | 6.96446 |
module RAM_1port (
input clk,
input rst,
input enb,
input [6:0] addr,
input [3:0] w_data,
output wire [3:0] r_data
);
//parameter N = 7; //2^N
//*************code***********//
reg [3:0] mem[127:0];
always @(posedge clk or negedge rst) begin
if (!rst) begin
mem[addr] <= 'b0;
... | 7.715376 |
module single_instruction_tb ();
reg clk;
reg [31:0] instruction;
SingleInstruction mut (
.clk(clk),
.instruction(instruction)
);
initial begin
clk = 0;
end
always begin
#5;
clk = ~clk;
end
initial begin
$dumpfile("single_instruction_out.vcd");
$dumpvars(0, mut);
... | 7.926673 |
module single_inv (
d_in,
d_out,
clock,
rst
);
input clock;
input rst;
input d_in;
output d_out;
assign d_out = ~d_in;
endmodule
| 6.548701 |
module single_inv_tb ();
reg clock, rst;
reg d_in;
wire d_out;
wire rdy;
initial begin
$display($time, " << Starting the Simulation >>");
d_in = 1'b0;
wait (rdy == 1'b1) begin
d_in = 1'b0;
end
#20 d_in = 1'b1;
#20 d_in = 1'b0;
#20 $display($time, " << Simulation Compl... | 6.694854 |
module single_inv_reg (
d_in,
d_out,
clock,
rst
);
input clock;
input rst;
input d_in;
reg d_d;
output d_out;
always @(posedge clock)
if (rst) d_d <= 1'b0;
else d_d <= ~d_in;
assign d_out = d_d;
endmodule
| 6.896215 |
module single_inv_reg_tb ();
reg clock, rst;
reg d_in;
wire d_out;
wire rdy;
initial begin
$display($time, " << Starting the Simulation >>");
d_in = 1'b0;
wait (rdy == 1'b1) begin
d_in = 1'b0;
end
#30 d_in = 1'b1;
#20 d_in = 1'b0;
#40 $display($time, " << Simulation C... | 6.896215 |
module single_inv_reg_tb ();
reg clock, rst;
reg d_in;
wire d_out;
initial begin
$display($time, " << Starting the Simulation >>");
d_in = 1'b0;
#30 d_in = 1'b0;
#20 d_in = 1'b1;
#20 d_in = 1'b0;
#40 $display($time, " << Simulation Complete >>");
end
initial begin
$monit... | 6.896215 |
module single_inv_tb ();
reg clock, rst;
reg d_in;
wire d_out;
initial begin
$display($time, " << Starting the Simulation >>");
d_in = 1'b0;
#30 d_in = 1'b0;
#20 d_in = 1'b1;
#20 d_in = 1'b0;
#20 $display($time, " << Simulation Complete >>");
end
initial begin
$monitor($... | 6.694854 |
module single_leg_switch (
CLK,
Sin,
Q1,
Q2
);
input CLK; //50 MHz clock
//input RST; //reset signal
input Sin; //1 if leg output should be high, 0 if leg output should be low
output reg Q1; //1 if top switch should be on, 0 if top switch should be off
output reg Q2; //1 if bot switch sho... | 6.754226 |
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module single_max_tb;
reg clk;
reg [31:0] single_max_a;
reg [31:0] single_max_b;
wire [31:0] single_max_z;
integer single_max_a_file;
integer single_max_b_file;
integer single_max_z_file;
integer single_max_a_count;
integer single_max_b_count;
integer single_max_z_count;
single_max single_max1 (
... | 7.212858 |
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module single_min_tb;
reg clk;
reg [31:0] single_min_a;
reg [31:0] single_min_b;
wire [31:0] single_min_z;
integer single_min_a_file;
integer single_min_b_file;
integer single_min_z_file;
integer single_min_a_count;
integer single_min_b_count;
integer single_min_z_count;
single_min single_min1 (
... | 7.307471 |
module single_multiplexer #(
parameter NUM_PES = 16,
DATA_TYPE = 8,
NUM_SEL = $clog2(NUM_PES)
) (
input clk,
input [ NUM_SEL-1:0] sel_in,
input [NUM_PES*DATA_TYPE-1:0] data_in,
output [ DATA_TYPE-1:0] data_out
);
reg [DATA_TYPE-1:0] data_out_reg;
... | 7.340148 |
module multiplier_TB ();
reg clk = 0, rst = 1;
reg [31:0] a, b;
wire [31:0] z;
reg a_stb, b_stb, z_ack;
wire a_ack, b_ack, z_stb;
always #10 clk = ~clk; // 25MHz
multiplier multiplier_39759952 (
.clk(clk),
.rst(rst),
.input_a(a),
.input_a_stb(a_stb),
.input_a_ack(a_ack),
... | 6.822233 |
module single_mux (
input sig1,
input sig2,
input select,
output reg mux_output
);
always @(*) begin
if (select) mux_output = sig1;
else mux_output = sig2;
end
endmodule
| 7.045386 |
module single_mux32 (
Ai,
Bi,
sel,
out
);
input [31:0] Ai;
input [31:0] Bi;
input sel;
output [31:0] out;
assign out[31:0] = (sel == 1) ? (Bi[31:0]) : (Ai[31:0]);
endmodule
| 8.089521 |
module single_mux5 (
Ai,
Bi,
sel,
out
);
input [4:0] Ai;
input [4:0] Bi;
input sel;
output [4:0] out;
assign out[4:0] = (sel == 1) ? (Bi[4:0]) : (Ai[4:0]);
endmodule
| 7.193599 |
module single_packer (
z_s,
z_m,
z_e,
z
);
output reg [31:0] z;
input [23:0] z_m;
input [9:0] z_e;
input z_s;
always @(*) begin
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] = 0;
z[30 : 23] = 255;
z[31] = z_s;
end else if ($signed(z_e) ... | 7.294823 |
module single_pitch_oscillator #(
parameter PITCH = 30578
) (
input clk,
output out
);
reg [23:0] counter; // 24-bit counter
reg counterout = 0;
always @(posedge clk) begin
if (counter < PITCH) begin
counter <= counter + 1;
end else begin
counter <= 0;
counterout <= ~coun... | 6.932456 |
module single_port_blockram #(
parameter SINGLE_ENTRY_SIZE_IN_BITS = 64,
parameter NUM_SET = 64,
parameter SET_PTR_WIDTH_IN_BITS = $clog2(NUM_SET),
parameter WRITE_MASK_LEN = SINGLE_ENTRY_SIZE_IN_BITS / `BYTE_LEN_IN_BITS
) (
input clk_in,
input ... | 7.829748 |
module single_port_lutram #(
parameter SINGLE_ENTRY_SIZE_IN_BITS = 64,
parameter NUM_SET = 64,
parameter SET_PTR_WIDTH_IN_BITS = $clog2(NUM_SET),
parameter WRITE_MASK_LEN = SINGLE_ENTRY_SIZE_IN_BITS / `BYTE_LEN_IN_BITS
) (
input clk_in,
input reset_in,
input... | 7.253224 |
module
single_port_memory #(parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
MEM_SIZE = 512
)(
input clk,
input Enable_Write,
input Enable_Read,
input [$clog2(MEM_SIZE)-1:0] Address,
input [DATA_WIDTH-1:0] Data_Input,
output reg [DATA_WIDTH-1:0] Data_Output
);
reg [DATA_W... | 7.715227 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.