code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sky130_fd_sc_hdll__clkinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinvlp (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endm... | 7.212805 |
module sky130_fd_sc_hdll__clkinvlp (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinvlp (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinvlp (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinvlp (
//# {{data|Data Signals}}
input A,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinvlp (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinvlp_2 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule... | 7.212805 |
module sky130_fd_sc_hdll__clkinvlp_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinvlp_4 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule... | 7.212805 |
module sky130_fd_sc_hdll__clkinvlp_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_1 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_12 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_12 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_16 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_2 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_4 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_8 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkmux2 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire mux_2to10_out_X;
wire pwrgood_pp0_out_X;
// ... | 7.212805 |
module sky130_fd_sc_hdll__clkmux2 (
X,
A0,
A1,
S
);
// Module ports
output X;
input A0;
input A1;
input S;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire mux_2to10_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__clkmux2 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkmux2 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire mux_2to10_out_X;
wire pwrgood_pp0_out_X;
// ... | 7.212805 |
module sky130_fd_sc_hdll__clkmux2 (
X,
A0,
A1,
S
);
// Module ports
output X;
input A0;
input A1;
input S;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (
mux_2to10_o... | 7.212805 |
module sky130_fd_sc_hdll__clkmux2 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkmux2 (
//# {{data|Data Signals}}
input A0,
input A1,
output X,
//# {{control|Control Signals}}
input S,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkmux2 (
//# {{data|Data Signals}}
input A0,
input A1,
output X,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkmux2_1 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkmux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),... | 7.212805 |
module sky130_fd_sc_hdll__clkmux2_1 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkmux2 base (
.X (X),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkmux2_2 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkmux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),... | 7.212805 |
module sky130_fd_sc_hdll__clkmux2_2 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkmux2 base (
.X (X),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__clkmux2_4 (
X,
A0,
A1,
S,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A0;
input A1;
input S;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__clkmux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),... | 7.212805 |
module sky130_fd_sc_hdll__clkmux2_4 (
X,
A0,
A1,
S
);
output X;
input A0;
input A1;
input S;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__clkmux2 base (
.X (X),
.A0(A0),
.A1(A1),
.S (S)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__conb (
HI,
LO,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output HI;
output LO;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pullup0_out_HI;
wire pulldown0_out_LO;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output
pullup pullup0 (HI);
pulldown pulldown0 (LO);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__conb (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__conb (
HI,
LO,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output HI;
output LO;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pullup0_out_HI;
wire pulldown0_out_LO;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Name Output
pullup pullup0 (HI);
pulldown pulldown0 (LO);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__conb (
HI,
LO,
VPWR,
VGND,
VPB,
VNB
);
output HI;
output LO;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__conb (
//# {{data|Data Signals}}
output HI,
output LO,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__conb (
//# {{data|Data Signals}}
output HI,
output LO
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__conb_1 (
HI,
LO,
VPWR,
VGND,
VPB,
VNB
);
output HI;
output LO;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__conb base (
.HI (HI),
.LO (LO),
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
en... | 7.212805 |
module sky130_fd_sc_hdll__conb_1 (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__conb base (
.HI(HI),
.LO(LO)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap ();
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap (
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap_12 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap_12 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap_3 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap_3 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap_4 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap_6 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap_6 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap_8 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__decap_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__decap base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dfrtp (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire D_delayed;
... | 7.212805 |
module sky130_fd_sc_hdll__dfrtp (
Q,
CLK,
D,
RESET_B
);
// Module ports
output Q;
input CLK;
input D;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire RESET;
reg notifier;
wire D_delaye... | 7.212805 |
module sky130_fd_sc_hdll__dfrtp (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
... | 7.212805 |
module sky130_fd_sc_hdll__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
... | 7.212805 |
module sky130_fd_sc_hdll__dfrtp (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dfrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dfrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dfrtp_1 (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)... | 7.212805 |
module sky130_fd_sc_hdll__dfrtp_1 (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)... | 7.212805 |
module sky130_fd_sc_hdll__dfrtp_2 (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)... | 7.212805 |
module sky130_fd_sc_hdll__dfrtp_2 (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)... | 7.212805 |
module sky130_fd_sc_hdll__dfrtp_4 (
Q,
CLK,
D,
RESET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input RESET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)... | 7.212805 |
module sky130_fd_sc_hdll__dfrtp_4 (
Q,
CLK,
D,
RESET_B
);
output Q;
input CLK;
input D;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)... | 7.212805 |
module sky130_fd_sc_hdll__dfstp (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire D_delayed;
wire ... | 7.212805 |
module sky130_fd_sc_hdll__dfstp (
Q,
CLK,
D,
SET_B
);
// Module ports
output Q;
input CLK;
input D;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf_Q;
wire SET;
reg notifier;
wire D_delayed;
w... | 7.212805 |
module sky130_fd_sc_hdll__dfstp (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire bu... | 7.212805 |
module sky130_fd_sc_hdll__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not ... | 7.212805 |
module sky130_fd_sc_hdll__dfstp (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dfstp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dfstp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dfstp_1 (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
... | 7.212805 |
module sky130_fd_sc_hdll__dfstp_1 (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
e... | 7.212805 |
module sky130_fd_sc_hdll__dfstp_2 (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
... | 7.212805 |
module sky130_fd_sc_hdll__dfstp_2 (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
e... | 7.212805 |
module sky130_fd_sc_hdll__dfstp_4 (
Q,
CLK,
D,
SET_B,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input CLK;
input D;
input SET_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
... | 7.212805 |
module sky130_fd_sc_hdll__dfstp_4 (
Q,
CLK,
D,
SET_B
);
output Q;
input CLK;
input D;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
e... | 7.212805 |
module sky130_fd_sc_hdll__diode (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode (
DIODE
);
// Module ports
input DIODE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
| 7.212805 |
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