code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hdll__diode (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode (
//# {{power|Power}}
input DIODE,
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode (
//# {{power|Power}}
input DIODE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode_2 (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE),
.VPWR (VPWR),
.VGND (VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode_2 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__diode base (.DIODE(DIODE));
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode_4 (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE),
.VPWR (VPWR),
.VGND (VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode_4 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__diode base (.DIODE(DIODE));
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode_6 (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE),
.VPWR (VPWR),
.VGND (VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode_6 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__diode base (.DIODE(DIODE));
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode_8 (
DIODE,
VPWR,
VGND,
VPB,
VNB
);
input DIODE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE),
.VPWR (VPWR),
.VGND (VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__diode_8 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__diode base (.DIODE(DIODE));
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlrtn (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
wire GATE;
reg notifier;
wire D_delay... | 7.212805 |
module sky130_fd_sc_hdll__dlrtn (
Q,
RESET_B,
D,
GATE_N
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
wire GATE;
reg notifier;
wire D_d... | 7.212805 |
module sky130_fd_sc_hdll__dlrtn (
Q,
RESET_B,
D,
GATE_N
);
output Q;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
... | 7.212805 |
module sky130_fd_sc_hdll__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET;
wire GATE ;
wire buf_Q;
// Delay Name Out... | 7.212805 |
module sky130_fd_sc_hdll__dlrtn (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlrtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlrtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlrtn_1 (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GA... | 7.212805 |
module sky130_fd_sc_hdll__dlrtn_1 (
Q,
RESET_B,
D,
GATE_N
);
output Q;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GA... | 7.212805 |
module sky130_fd_sc_hdll__dlrtn_2 (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GA... | 7.212805 |
module sky130_fd_sc_hdll__dlrtn_2 (
Q,
RESET_B,
D,
GATE_N
);
output Q;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GA... | 7.212805 |
module sky130_fd_sc_hdll__dlrtn_4 (
Q,
RESET_B,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GA... | 7.212805 |
module sky130_fd_sc_hdll__dlrtn_4 (
Q,
RESET_B,
D,
GATE_N
);
output Q;
input RESET_B;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GA... | 7.212805 |
module sky130_fd_sc_hdll__dlrtp (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire RESET;
reg notifier;
wire D_delayed;
wire GATE_d... | 7.212805 |
module sky130_fd_sc_hdll__dlrtp (
Q,
RESET_B,
D,
GATE
);
// Module ports
output Q;
input RESET_B;
input D;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire RESET;
reg notifier;
wire D_delayed;
wire GA... | 7.212805 |
module sky130_fd_sc_hdll__dlrtp (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
... | 7.212805 |
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other argumen... | 7.212805 |
module sky130_fd_sc_hdll__dlrtp (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlrtp (
//# {{data|Data Signals}}
input D,
output Q,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlrtp_1 (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(G... | 7.212805 |
module sky130_fd_sc_hdll__dlrtp_1 (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(G... | 7.212805 |
module sky130_fd_sc_hdll__dlrtp_2 (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(G... | 7.212805 |
module sky130_fd_sc_hdll__dlrtp_2 (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(G... | 7.212805 |
module sky130_fd_sc_hdll__dlrtp_4 (
Q,
RESET_B,
D,
GATE,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input RESET_B;
input D;
input GATE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(G... | 7.212805 |
module sky130_fd_sc_hdll__dlrtp_4 (
Q,
RESET_B,
D,
GATE
);
output Q;
input RESET_B;
input D;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(G... | 7.212805 |
module sky130_fd_sc_hdll__dlxtn (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire GATE;
wire buf_Q;
wire GATE_N_delayed;
wire D_delayed;
reg notifier;
w... | 7.212805 |
module sky130_fd_sc_hdll__dlxtn (
Q,
D,
GATE_N
);
// Module ports
output Q;
input D;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire GATE;
wire buf_Q;
wire GATE_N_delayed;
wire D_delayed;
reg notifi... | 7.212805 |
module sky130_fd_sc_hdll__dlxtn (
Q,
D,
GATE_N
);
output Q;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlxtn (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire GATE;
wire buf_Q;
// Name Output O... | 7.212805 |
module sky130_fd_sc_hdll__dlxtn (
Q,
D,
GATE_N
);
// Module ports
output Q;
input D;
input GATE_N;
// Local signals
wire GATE;
wire buf_Q;
// Name Output Other arguments
not not0 (GATE, GATE_N);
sky130_fd_sc_hdll__udp_dlatch$P dlatch0 (
buf_Q,
... | 7.212805 |
module sky130_fd_sc_hdll__dlxtn (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlxtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlxtn (
//# {{data|Data Signals}}
input D,
output Q,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlxtn_1 (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
... | 7.212805 |
module sky130_fd_sc_hdll__dlxtn_1 (
Q,
D,
GATE_N
);
output Q;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlxtn_2 (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
... | 7.212805 |
module sky130_fd_sc_hdll__dlxtn_2 (
Q,
D,
GATE_N
);
output Q;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlxtn_4 (
Q,
D,
GATE_N,
VPWR,
VGND,
VPB,
VNB
);
output Q;
input D;
input GATE_N;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
... | 7.212805 |
module sky130_fd_sc_hdll__dlxtn_4 (
Q,
D,
GATE_N
);
output Q;
input D;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
e... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd1 (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd1 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd1_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
end... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd1_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd2 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
e... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd2 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd2 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd2 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd2_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlygate4sd2 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
end... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd2_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlygate4sd2 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd3 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
e... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd3 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd3 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire buf0_out_X;
wire pwrgood_pp0_out_X;
// Name Output ... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A);
buf buf1 (X, buf0_out_X);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd3 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd3 (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd3 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd3_1 (
X,
A,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__dlygate4sd3 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
end... | 7.212805 |
module sky130_fd_sc_hdll__dlygate4sd3_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__dlygate4sd3 base (
.X(X),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__ebufn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_teb;
// ... | 7.212805 |
module sky130_fd_sc_hdll__ebufn (
Z,
A,
TE_B
);
// Module ports
output Z;
input A;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
bufif0 bufif00 (Z, A, TE_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__ebufn (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__ebufn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_teb;
// ... | 7.212805 |
module sky130_fd_sc_hdll__ebufn (
Z,
A,
TE_B
);
// Module ports
output Z;
input A;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z, A, TE_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__ebufn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__ebufn (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__ebufn (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__ebufn_1 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(... | 7.212805 |
module sky130_fd_sc_hdll__ebufn_1 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__ebufn_2 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(... | 7.212805 |
module sky130_fd_sc_hdll__ebufn_2 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__ebufn_4 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(... | 7.212805 |
module sky130_fd_sc_hdll__ebufn_4 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__ebufn_8 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(... | 7.212805 |
module sky130_fd_sc_hdll__ebufn_8 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_teb;
// ... | 7.212805 |
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