code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module sky130_fd_sc_hdll__einvn (
Z,
A,
TE_B
);
// Module ports
output Z;
input A;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
notif0 notif00 (Z, A, TE_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_teb,
TE_B,
VPWR,
VGND
);
notif0 notif00 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn (
Z,
A,
TE_B
);
// Module ports
output Z;
input A;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z, A, TE_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn_1 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn_1 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn_2 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn_2 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn_4 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn_4 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn_8 (
Z,
A,
TE_B,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvn_8 (
Z,
A,
TE_B
);
output Z;
input A;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_TE,
TE,
VPWR,
VGND
);
notif1 notif10 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp (
Z,
A,
TE
);
// Module ports
output Z;
input A;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
notif1 notif10 (Z, A, TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire pwrgood_pp0_out_A;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_A,
A,
VPWR,
VGND
);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (
pwrgood_pp1_out_TE,
TE,
VPWR,
VGND
);
notif1 notif10 (Z, pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp (
Z,
A,
TE
);
// Module ports
output Z;
input A;
input TE;
// Name Output Other arguments
notif1 notif10 (Z, A, TE);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp (
//# {{data|Data Signals}}
input A,
output Z,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp_1 (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp_1 (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__einvp base (
.Z (Z),
.A (A),
.TE(TE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp_2 (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp_2 (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__einvp base (
.Z (Z),
.A (A),
.TE(TE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp_4 (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp_4 (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__einvp base (
.Z (Z),
.A (A),
.TE(TE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp_8 (
Z,
A,
TE,
VPWR,
VGND,
VPB,
VNB
);
output Z;
input A;
input TE;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__einvp_8 (
Z,
A,
TE
);
output Z;
input A;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__einvp base (
.Z (Z),
.A (A),
.TE(TE)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill (
VPWR,
VGND,
VPB,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB;
input VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// No contents.
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill (
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill_1 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__fill base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill_2 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__fill base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill_4 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__fill base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill_8 (
VPWR,
VGND,
VPB,
VNB
);
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB (VPB),
.VNB (VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__fill_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__fill base ();
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0n (
X,
A,
SLEEP_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input SLEEP_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, SLEEP_B);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
X,
and0_out_X,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0n (
X,
A,
SLEEP_B
);
// Module ports
output X;
input A;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
and and0 (X, A, SLEEP_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0n (
X,
A,
SLEEP_B
);
output X;
input A;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0n (
X,
A,
SLEEP_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input SLEEP_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, SLEEP_B);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
X,
and0_out_X,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0n (
X,
A,
SLEEP_B
);
// Module ports
output X;
input A;
input SLEEP_B;
// Name Output Other arguments
and and0 (X, A, SLEEP_B);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0n (
X,
A,
SLEEP_B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input SLEEP_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0n (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input SLEEP_B,
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0n (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0n_1 (
X,
A,
SLEEP_B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input SLEEP_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__inputiso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0n_1 (
X,
A,
SLEEP_B
);
output X;
input A;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__inputiso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0p (
X,
A,
SLEEP,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input SLEEP;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire sleepn;
wire and0_out_X;
// Name Output Other arguments
not not0 (sleepn, SLEEP);
and and0 (and0_out_X, A, sleepn);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
X,
and0_out_X,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0p (
X,
A,
SLEEP
);
// Module ports
output X;
input A;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP);
and and0 (X, A, sleepn);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0p (
X,
A,
SLEEP
);
output X;
input A;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0p (
X,
A,
SLEEP,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input SLEEP;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire sleepn;
wire and0_out_X;
// Name Output Other arguments
not not0 (sleepn, SLEEP);
and and0 (and0_out_X, A, sleepn);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
X,
and0_out_X,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0p (
X,
A,
SLEEP
);
// Module ports
output X;
input A;
input SLEEP;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP);
and and0 (X, A, sleepn);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0p (
X,
A,
SLEEP,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input SLEEP;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0p (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input SLEEP,
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0p (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0p_1 (
X,
A,
SLEEP,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input SLEEP;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__inputiso0p base (
.X(X),
.A(A),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso0p_1 (
X,
A,
SLEEP
);
output X;
input A;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__inputiso0p base (
.X(X),
.A(A),
.SLEEP(SLEEP)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1n (
X,
A,
SLEEP_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input SLEEP_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire SLEEP;
wire or0_out_X;
// Name Output Other arguments
not not0 (SLEEP, SLEEP_B);
or or0 (or0_out_X, A, SLEEP);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
X,
or0_out_X,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1n (
X,
A,
SLEEP_B
);
// Module ports
output X;
input A;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP, SLEEP_B);
or or0 (X, A, SLEEP);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1n (
X,
A,
SLEEP_B
);
output X;
input A;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1n (
X,
A,
SLEEP_B,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input SLEEP_B;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire SLEEP;
wire or0_out_X;
// Name Output Other arguments
not not0 (SLEEP, SLEEP_B);
or or0 (or0_out_X, A, SLEEP);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
X,
or0_out_X,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1n (
X,
A,
SLEEP_B
);
// Module ports
output X;
input A;
input SLEEP_B;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP, SLEEP_B);
or or0 (X, A, SLEEP);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1n (
X,
A,
SLEEP_B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input SLEEP_B;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1n (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input SLEEP_B,
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1n (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1n_1 (
X,
A,
SLEEP_B,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input SLEEP_B;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__inputiso1n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1n_1 (
X,
A,
SLEEP_B
);
output X;
input A;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__inputiso1n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1p (
X,
A,
SLEEP,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input SLEEP;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
X,
or0_out_X,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1p (
X,
A,
SLEEP
);
// Module ports
output X;
input A;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Name Output Other arguments
or or0 (X, A, SLEEP);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1p (
X,
A,
SLEEP
);
output X;
input A;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1p (
X,
A,
SLEEP,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output X;
input A;
input SLEEP;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
X,
or0_out_X,
VPWR,
VGND
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1p (
X,
A,
SLEEP
);
// Module ports
output X;
input A;
input SLEEP;
// Name Output Other arguments
or or0 (X, A, SLEEP);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1p (
X,
A,
SLEEP,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input SLEEP;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1p (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input SLEEP,
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1p (
//# {{data|Data Signals}}
input A,
output X,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1p_1 (
X,
A,
SLEEP,
VPWR,
VGND,
VPB,
VNB
);
output X;
input A;
input SLEEP;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__inputiso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inputiso1p_1 (
X,
A,
SLEEP
);
output X;
input A;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__inputiso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
not0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
// Module ports
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
// Local signals
wire not0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (
pwrgood_pp0_out_Y,
not0_out_Y,
VPWR,
VGND
);
buf buf0 (Y, pwrgood_pp0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A);
buf buf0 (Y, not0_out_Y);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv (
//# {{data|Data Signals}}
input A,
output Y,
//# {{power|Power}}
input VPB,
input VPWR,
input VGND,
input VNB
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_1 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_12 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_12 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB;
supply0 VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
| 7.212805 |
module sky130_fd_sc_hdll__inv_16 (
Y,
A,
VPWR,
VGND,
VPB,
VNB
);
output Y;
input A;
input VPWR;
input VGND;
input VPB;
input VNB;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
| 7.212805 |
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