code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module slink_dp_ram #(
parameter DWIDTH = 32, // Data width
parameter SIZE = 256, // RAM size in DWIDTHs
parameter AWIDTH = $clog2(SIZE) // Address width
) (
input wire clk_0,
input wire [AWIDTH-1:0] addr_0,
input wire en_0,
input wire ... | 7.099784 |
module slip_rx (
/* clock input, reset input */
input wire clk,
rst,
/* frame signal - set to '1' when in the middle of
* frame processing */
output reg frame,
/* slip encoded input data */
input wire [7:0] din,
/* input data ready signal */
input wire din_rdy,
/* decoded d... | 8.05036 |
module sll2_32 (
in,
out
);
input signed [31:0] in;
output signed [31:0] out;
assign out = in <<< 1;
endmodule
| 7.420334 |
module sll32 (
input [31:0] A,
input [31:0] B,
output [31:0] res
);
assign res = A << B[10:6];
endmodule
| 6.513823 |
module shifts the input by 2 digits to the left.
module sll4(input [25:0]in,
output [25:0] out
);
assign out = in << 2;
endmodule
| 6.615679 |
module SLL_mux (
X,
S,
Z
);
//parameter definitions
parameter BUSSIZE = 1; //define size of input or output buses
parameter n = 32; // number of muxes total
parameter i = 2; // number mux being created, corresponding to index of output
//port definitions - customize for different bit widths
... | 8.060865 |
module sloader (
input wire clk,
input wire [7:0] rx_byte,
input wire rbyte_ready,
input wire vsync,
input wire key0,
input wire key1,
input wire torus_last,
output reg seed,
output reg seed_ena,
output wire life_step,
output wire [15:0] wdata,
output wire [12:0] waddr,
... | 6.926828 |
module slope9 #(
parameter R = 15
) (
// data
input clk, // clock
input rst, // reset - active low
input read_en, // read enable
input signed [R-1:0] dat_i, // input data
output reg signed [R-1:0] dat_o // out... | 7.612788 |
module slotExp (
input RSTb,
input ADFFFF,
input SLTSL,
input WRb,
input [7:0] DIN,
input [1:0] PAGE,
output [7:0] DOUT,
output reg [3:0] subSLT,
output outSSREG
);
reg [7:0] regSS;
reg [1:0] BSEL;
always @(negedge WRb or negedge RSTb)
if (~RSTb) regSS <= 8'h00;
els... | 6.971912 |
module SlotTop(/*reset*/, mainClock, switch, extsegsel, extled, led, seg, segsel);
//input reset; // Zbg
input mainClock; // 6MHz̃CNbN
input [2:0] switch; // 3XCb`
//output clock1KHz; // _Ci~bN_pNbN
//output clock10Hz; // XbgpNbN
output [15:0] extled;
o... | 7.052818 |
module slot_keeper #(
parameter SLOT_COUNT = 8,
parameter SLOT_WIDTH = $clog2(SLOT_COUNT + 1)
) (
input wire clk,
input wire rst,
input wire [SLOT_WIDTH-1:0] init_slots,
input wire init_valid,
input wire [SLOT_WIDTH-1:0] slot_in,
input wire slot_in_val... | 6.558911 |
module slot_machine (
input clk,
input mode,
input spin,
input up,
input down,
input reset,
output [7:0] led,
output [3:0] an,
output [7:0] seven_segment_out,
output [7:0] sound,
output speaker
);
wire mode_db;
wire spin_db;
wire up_db;
wire down_db;
wire reset_db;... | 6.861122 |
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (reset) begin
q <= 0;
end else begin
if (slowena) begin
if (q == 4'd9) begin
q <= 0;
end else begin
q <= q + 1;
end
end
... | 7.203305 |
module AND2X1 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.586662 |
module AND2X2 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.581256 |
module BUFX16 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.017424 |
module BUFX1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.745651 |
module BUFX20 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.887067 |
module BUFX2 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.749484 |
module BUFX8 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.734604 |
module BUFXL (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.751245 |
module DLY1X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.803121 |
module DLY2X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.888716 |
module DLY4X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.836106 |
module INVX12 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.954558 |
module INVX16 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.76246 |
module INVX1 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.147471 |
module INVX20 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.664121 |
module INVX2 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.594979 |
module INVX3 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.820921 |
module INVX4 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.745486 |
module INVX8 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.420124 |
module INVXL (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.7964 |
module MXI2X1 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
... | 6.596441 |
module MXI2X2 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
... | 6.513 |
module NAND2X1 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.753512 |
module NAND2X2 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.714648 |
module NOR2X1 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.900171 |
module NOR2X2 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.834679 |
module OR2X1 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.671603 |
module OR2X2 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.718483 |
module TBUFX12 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 6.509442 |
module TBUFX16 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 6.879027 |
module TBUFX1 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 7.023106 |
module TBUFX20 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 7.162916 |
module TBUFX2 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.905349 |
module TBUFX8 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.928405 |
module TBUFXL (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.635503 |
module TBUFIXL (
Y,
A,
OE
);
output Y;
input A, OE;
notif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 6.787417 |
module slow2fast (
output o_sgl, //output to fast clk region
input i_sgl, //input from slow clk region
input f_clk,
input frst_n
);
reg sgl_reg1;
reg sgl_reg2;
reg sgl_reg3;
assign o_sgl = sgl_reg2 & (~sgl_reg3);
always @(posedge f_clk, negedge frst_n) begin
if (~frst_n) begin
... | 7.122618 |
module SlowArea_1 (
output reg io_c0,
output reg io_c1,
input clk,
input reset
);
reg [1:0] _zz_when_ClockDomain_l369;
wire when_ClockDomain_l369;
reg when_ClockDomain_l369_regNext;
reg slow_tmp;
assign when_ClockDomain_l369 = (_zz_when_ClockDomain_l369 == 2'b1... | 8.238921 |
module slowclk (
input clk,
output reg hclk
);
always @(posedge clk) hclk = ~hclk;
endmodule
| 7.153401 |
module slowclock_5 (
output reg clk_slow,
input clk,
rst
);
reg [2:0] counter;
initial clk_slow <= 0;
always @(posedge clk, negedge rst) begin
if (!rst) begin
clk_slow <= 0;
counter <= 1;
end else begin
counter <= counter + 1'b1;
if (counter == 5) begin
coun... | 6.660956 |
module slowfil_fixedtaps (
i_clk,
i_reset,
i_tap_wr,
i_tap,
i_ce,
i_sample,
o_ce,
o_result
);
`ifdef FORMAL
parameter NTAPS = 16, IW = 9, TW = IW, OW = 2 * IW + 5;
`else
parameter NTAPS = 128, IW = 12, TW = IW, OW = 2 * IW + 7;
`endif
parameter [0:0] FIXED_TAPS = 0;
input wire i_... | 8.350244 |
module slowfil_srl_fixedtaps (
i_clk,
i_reset,
i_tap_wr,
i_tap,
i_ce,
i_sample,
o_ce,
o_result
);
`ifdef FORMAL
parameter NTAPS = 16, IW = 9, TW = IW, OW = 2 * IW + 5;
`else
parameter NTAPS = 128, IW = 12, TW = IW, OW = 2 * IW + 7;
`endif
parameter [0:0] FIXED_TAPS = 0;
input wir... | 8.291486 |
module slowsampleclk (
input clock,
input reset,
output reg new_clock
);
reg [21:0] clock_counter = 0;
always @(posedge clock) begin
if (reset) begin
clock_counter <= 0;
new_clock <= 0;
end else if (clock_counter == 6) begin // sample slow clock //675000
new_clock <= ~new_c... | 6.707127 |
module slow_addr (
a,
b,
out,
carry
);
parameter WIDTH = 64;
input [WIDTH-1:0] a, b;
output [WIDTH-1:0] out;
output carry;
wire [WIDTH-1:0] carry_vec;
genvar i;
generate
if (WIDTH == 1) begin
full_addr fa (
a,
b,
out,
1'b0,
ca... | 8.354973 |
module half_addr (
a,
b,
out,
carry
);
input a, b;
output out, carry;
xor2$ add_x (
out,
a,
b
);
and2$ carry_a (
carry,
a,
b
);
endmodule
| 7.083188 |
module full_addr (
a,
b,
out,
cin,
cout
);
input a, b, cin;
output out, cout;
wire overflow, overflow2, out_m;
half_addr ha0 (
a,
b,
out_m,
overflow
);
half_addr ha1 (
out_m,
cin,
out,
overflow2
);
or2$ carry_o (
cout,
ov... | 7.496224 |
module slow_bridge (
// 32-bit local bus (slave)
input lb_clk,
input [14:0] lb_addr,
input lb_read,
output [7:0] lb_out,
// Output status bit, valid in slow_clk domain
output invalid, // indicates internal data transfer in progress
// 8-bit shift-register port (master)
input slow_cl... | 7.247183 |
module slow_clk_20kHz (
input CLOCK,
output CLK_20kHz
);
reg [12:0] COUNTER = 12'b0;
reg slow_clock = 0;
always @(posedge CLOCK) begin
if (COUNTER == 12'b100111000011) begin
COUNTER <= 0;
slow_clock <= ~slow_clock;
end else COUNTER <= COUNTER + 1;
end
assign CLK_20kHz = slow_cl... | 7.061422 |
module top_module (
input clk,
input slowena,
input reset,
output reg [3:0] q
);
always @(posedge clk) begin
if (reset || q == 9 && slowena) q <= 0;
else begin
if (!slowena) q <= q;
else q <= q + 1;
end
end
endmodule
| 7.203305 |
module slow_memory (
clk,
mem_read,
mem_write,
mem_addr,
mem_wdata,
mem_rdata,
mem_ready
);
parameter MEM_NUM = 256;
parameter MEM_WIDTH = 128;
parameter LATENCY = 15; // negedge clock after [Unconditional carry(15ns/CYCLE)+1] cycle
parameter IDLE = 2'd0;
parameter WAIT = 2'd1;
... | 7.713766 |
module AND2X1 (
Y,
A,
B
);
output Y;
input A, B;
// Function
and (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.586662 |
module AND2X2 (
Y,
A,
B
);
output Y;
input A, B;
// Function
and (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.581256 |
module BUFX16 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.017424 |
module BUFX2 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.749484 |
module BUFX20 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.887067 |
module BUFX8 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.734604 |
module DLY1X1 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.803121 |
module DLY1X4 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.769339 |
module DLY2X1 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.888716 |
module DLY2X4 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.784512 |
module DLY4X1 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.836106 |
module DLY4X4 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.727196 |
module INVX1 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.147471 |
module INVX12 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.954558 |
module INVX16 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.76246 |
module INVX2 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.594979 |
module INVX20 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.664121 |
module INVX3 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.820921 |
module INVX4 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.745486 |
module INVX6 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.139895 |
module INVX8 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.420124 |
module INVXL (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.7964 |
module MX2X8 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
// Function
wire int_fwire_0, int_fwire_1, S0__bar;
not (S0__bar, S0);
and (int_fwire_0, S0__bar, A);
and (int_fwire_1, S0, B);
or (Y, int_fwire_1, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(pose... | 6.679592 |
module MXI2X1 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire S0__bar;
not (S0__bar, S0);
and (int_fwire_0, S0__bar, A);
and (int_fwire_1, S0, B);
or (int_fwire_2, int_fwire_1, int_fwire_0);
not (Y, int_fwire_2);
// Timing
... | 6.596441 |
module MXI2X2 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire S0__bar;
not (S0__bar, S0);
and (int_fwire_0, S0__bar, A);
and (int_fwire_1, S0, B);
or (int_fwire_2, int_fwire_1, int_fwire_0);
not (Y, int_fwire_2);
// Timing
... | 6.513 |
module MXI2X8 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire S0__bar;
not (S0__bar, S0);
and (int_fwire_0, S0__bar, A);
and (int_fwire_1, S0, B);
or (int_fwire_2, int_fwire_1, int_fwire_0);
not (Y, int_fwire_2);
// Timing
... | 6.589143 |
module MXI3X4 (
Y,
A,
B,
C,
S0,
S1
);
output Y;
input A, B, C, S0, S1;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire int_fwire_3, int_fwire_4, int_fwire_5;
wire S0__bar, S1__bar;
not (S0__bar, S0);
and (int_fwire_0, S0__bar, A);
and (int_fwire_1, S0, B);
or (... | 6.578424 |
module NAND2X1 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
and (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.753512 |
module NAND2X2 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
and (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.714648 |
module NOR2X1 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
or (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.900171 |
module NOR2X2 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
or (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.834679 |
module NOR2X6 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
or (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.536029 |
module NOR2X8 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
or (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.745176 |
module OR2X1 (
Y,
A,
B
);
output Y;
input A, B;
// Function
or (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.671603 |
module OR2X2 (
Y,
A,
B
);
output Y;
input A, B;
// Function
or (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.718483 |
module TBUFX1 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 7.023106 |
module TBUFX12 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.509442 |
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