code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module slink_dp_ram #(
parameter DWIDTH = 32, // Data width
parameter SIZE = 256, // RAM size in DWIDTHs
parameter AWIDTH = $clog2(SIZE) // Address width
) (
input wire clk_0,
input wire [AWIDTH-1:0] addr_0,
input wire en_0,
input wire we_0,
input wire [DWIDTH-1:0] wdata_0,
output wire [DWIDTH-1:0] rdata_0,
input wire clk_1,
input wire [AWIDTH-1:0] addr_1,
input wire en_1,
input wire we_1,
input wire [DWIDTH-1:0] wdata_1,
output wire [DWIDTH-1:0] rdata_1
);
reg [DWIDTH-1:0] mem[SIZE-1:0];
wire write_0, read_0;
wire write_1, read_1;
reg [AWIDTH-1:0] addr_0_reg, addr_1_reg;
assign write_0 = en_0 & we_0;
assign read_0 = en_0 & ~we_0;
integer i;
always @(posedge clk_0) begin
if (write_0) begin
mem[addr_0] <= wdata_0;
end
end
always @(posedge clk_0) begin
if (read_0) begin
addr_0_reg <= addr_0;
end
end
assign rdata_0 = read_0 ? mem[addr_0] : mem[addr_0_reg];
assign write_1 = en_1 & we_1;
assign read_1 = en_1 & ~we_1;
integer j;
// always @(posedge clk_1) begin
// if (write_1) begin
// mem[addr_1] <= wdata_1;
// end
// end
always @(posedge clk_1) begin
if (read_1) begin
addr_1_reg <= addr_1;
end
end
assign rdata_1 = read_1 ? mem[addr_1] : mem[addr_1_reg];
endmodule
| 7.099784 |
module slip_rx (
/* clock input, reset input */
input wire clk,
rst,
/* frame signal - set to '1' when in the middle of
* frame processing */
output reg frame,
/* slip encoded input data */
input wire [7:0] din,
/* input data ready signal */
input wire din_rdy,
/* decoded data output */
output reg [7:0] dout,
/* decoded data ready */
output reg dout_rdy,
/* decoded data ack */
input wire dout_ack
);
/* state machine states */
localparam SOF = 0;
localparam READ = 1;
localparam ESC = 2;
/* special characters */
localparam CHAR_END = 8'hC0;
localparam CHAR_ESC = 8'hDB;
localparam CHAR_ESC_END = 8'hDC;
localparam CHAR_ESC_ESC = 8'hDD;
/* current state */
reg [1:0] state;
/* buffered version of data */
reg [7:0] din_buf;
/* synchronous logic */
always @(posedge clk or posedge rst) begin
/* reset logic */
if (rst) begin
state <= SOF;
frame <= 1'b0;
dout_rdy <= 0;
dout <= 0;
/* normal operation */
end else begin
/* clear flag */
if (dout_ack) dout_rdy <= 1'b0;
/* time to process data? */
if (din_rdy) begin
/* slip state machine */
case (state)
/* wait for sof */
SOF: begin
dout <= din;
/* start of frame received */
if (din == CHAR_END) state <= READ;
end
/* normal operation */
READ: begin
dout <= din;
/* got ending character? */
if (din == CHAR_END) begin
/* prevent multiple consecutive 0xc0 */
if (frame) begin
frame <= 1'b0;
state <= SOF;
end
/* normal decoding */
end else begin
/* we are now in the middle of the frame */
frame <= 1'b1;
/* got an escape character? */
if (din == CHAR_ESC) begin
state <= ESC;
/* normal character */
end else begin
dout_rdy <= 1'b1;
end
end
end
/* escape */
ESC: begin
/* store decoded character */
dout <= din == CHAR_ESC_END ? CHAR_END : CHAR_ESC;
/* go back to 'normal' data reading */
state <= READ;
dout_rdy <= 1'b1;
end
endcase
end
end
end
endmodule
| 8.05036 |
module sll2_32 (
in,
out
);
input signed [31:0] in;
output signed [31:0] out;
assign out = in <<< 1;
endmodule
| 7.420334 |
module sll32 (
input [31:0] A,
input [31:0] B,
output [31:0] res
);
assign res = A << B[10:6];
endmodule
| 6.513823 |
module shifts the input by 2 digits to the left.
module sll4(input [25:0]in,
output [25:0] out
);
assign out = in << 2;
endmodule
| 6.615679 |
module SLL_mux (
X,
S,
Z
);
//parameter definitions
parameter BUSSIZE = 1; //define size of input or output buses
parameter n = 32; // number of muxes total
parameter i = 2; // number mux being created, corresponding to index of output
//port definitions - customize for different bit widths
input wire [31:0] X;
input wire [31:0] S;
output wire Z;
wire [31:0] MuxIn; // wires that actually get hooked up to the mux.
wire W0, W1, W2;
// Assigns the right value to each mux input.
genvar j;
// wires input wires to mux.
for (j = 0; j < i + 1; j = j + 1) begin : assign_muxIns_values
assign MuxIn[j] = X[i-j];
end
// grounds remaining connections to mux.
for (j = i + 1; j < n; j = j + 1) begin : assign_muxIns_ground
assign MuxIn[j] = 0;
end
mux_16to1 #(
.BUSSIZE(BUSSIZE)
) MUX_012_0 (
.A(MuxIn[0]),
.B(MuxIn[1]),
.C(MuxIn[2]),
.D(MuxIn[3]),
.E(MuxIn[4]),
.F(MuxIn[5]),
.G(MuxIn[6]),
.H(MuxIn[7]),
.I(MuxIn[8]),
.J(MuxIn[9]),
.K(MuxIn[10]),
.L(MuxIn[11]),
.M(MuxIn[12]),
.N(MuxIn[13]),
.O(MuxIn[14]),
.P(MuxIn[15]),
.S(S[3:0]),
.Z(W0)
);
mux_16to1 #(
.BUSSIZE(BUSSIZE)
) MUX_012_1 (
.A(MuxIn[16]),
.B(MuxIn[17]),
.C(MuxIn[18]),
.D(MuxIn[19]),
.E(MuxIn[20]),
.F(MuxIn[21]),
.G(MuxIn[22]),
.H(MuxIn[23]),
.I(MuxIn[24]),
.J(MuxIn[25]),
.K(MuxIn[26]),
.L(MuxIn[27]),
.M(MuxIn[28]),
.N(MuxIn[29]),
.O(MuxIn[30]),
.P(MuxIn[31]),
.S(S[3:0]),
.Z(W1)
);
mux_2to1 #(
.BUSSIZE(BUSSIZE)
) MUX_3_0 (
.X(W0),
.Y(W1),
.S(S[4]),
.Z(W2)
);
// checks if shift is greater than 2^5. If so, 0, else W2.
assign Z = |S[31:5] ? 0 : W2;
endmodule
| 8.060865 |
module sloader (
input wire clk,
input wire [7:0] rx_byte,
input wire rbyte_ready,
input wire vsync,
input wire key0,
input wire key1,
input wire torus_last,
output reg seed,
output reg seed_ena,
output wire life_step,
output wire [15:0] wdata,
output wire [12:0] waddr,
output wire wr,
output wire [7:0] debug
);
parameter TORUS_WIDTH = 32;
parameter TORUS_HEIGHT = 16;
//find edge of hsync impulse
reg [2:0] vsyncf;
wire vsynce;
assign vsynce = (vsyncf[2:1] == 2'b01);
always @(posedge clk) vsyncf <= {vsyncf[1:0], vsync};
//process board button, against metastability and jitter
reg [2:0] key0f_;
wire key0f;
assign key0f = key0f_[2];
reg [2:0] key1f_;
wire key1f;
assign key1f = key1f_[2];
always @(posedge clk)
if (vsynce) begin
key0f_ <= {key0f_[1:0], key0};
key1f_ <= {key1f_[1:0], key1};
end
reg [3:0] rbyte_readyf_;
wire rbyte_readyf;
assign rbyte_readyf = (rbyte_readyf_[1:0] == 2'b01);
always @(posedge clk) rbyte_readyf_ <= {rbyte_readyf_[2:0], rbyte_ready};
//find 1 second impulse
reg [7:0] vsync_cnt;
wire second_imp;
assign second_imp = (vsync_cnt == 20);
always @(posedge clk)
if (vsynce) begin
if (second_imp) vsync_cnt <= 0;
else vsync_cnt <= vsync_cnt + 1'b1;
end
reg life_step_;
always @(posedge clk) life_step_ <= key0f & vsynce & second_imp;
assign life_step = life_step_ & key1f;
reg [7:0] rx_bytef;
always @(posedge clk) begin
if (rbyte_readyf) rx_bytef <= rx_byte;
end
reg [15:0] cell_counter;
reg [ 1:0] state;
always @(posedge clk) begin
if (~key0f) begin
seed <= (rx_bytef == 8'h2A);
seed_ena <= (rbyte_readyf_[3:2] == 2'b01) & (rx_bytef == 8'h2A || rx_bytef == 8'h2D);
cell_counter <= 0;
state <= 0;
end else begin
seed <= torus_last;
case (state)
0: begin
cell_counter <= 0;
seed_ena <= life_step_;
state <= life_step_;
end
1: begin
seed_ena <= 1;
state <= 2;
cell_counter <= 0;
end
2: begin
if (cell_counter == TORUS_WIDTH * TORUS_HEIGHT - 1) begin
seed_ena <= 0;
cell_counter <= 0;
state <= 0;
end else begin
seed_ena <= 1;
state <= 2;
cell_counter <= cell_counter + 1'b1;
end
end
endcase
end
end
assign wr = (state == 2);
assign wdata = torus_last ? 16'h4f2a : 16'h1f30;
parameter WBITS = $clog2(TORUS_WIDTH);
parameter HBITS = $clog2(TORUS_HEIGHT);
wire [3:0] wb;
assign wb = WBITS;
wire [3:0] hb;
assign hb = HBITS;
assign debug = {hb, wb};
//assign waddr = {2'b00,cell_counter[8:5],2'b00,cell_counter[4:0]};
wire [6:0] addr_l;
assign addr_l = cell_counter[WBITS-1:0] + 4;
wire [5:0] addr_h;
assign addr_h = cell_counter[HBITS-1+WBITS:WBITS];
assign waddr = {addr_h, addr_l};
//assign waddr = {2'b00,cell_counter[8:5],2'b00,cell_counter[4:0]};
//assign waddr = {1'b0,cell_counter[10:6],1'b01,cell_counter[5:0]};
endmodule
| 6.926828 |
module slope9 #(
parameter R = 15
) (
// data
input clk, // clock
input rst, // reset - active low
input read_en, // read enable
input signed [R-1:0] dat_i, // input data
output reg signed [R-1:0] dat_o // output data
);
wire signed [R+5-1:0] sum;
wire signed [ R-1:0] sum_div;
reg signed [R-1:0] mem0, mem1, mem2, mem3, mem4, mem5, mem6, mem7, mem8;
wire signed [ R-1: 0] mem_next0,mem_next1,mem_next2,mem_next3,mem_next4,mem_next5,mem_next6,mem_next7,mem_next8;
always @(posedge clk) begin
if (rst) begin
mem0 <= {R{1'b0}};
mem1 <= {R{1'b0}};
mem2 <= {R{1'b0}};
mem3 <= {R{1'b0}};
mem4 <= {R{1'b0}};
mem5 <= {R{1'b0}};
mem6 <= {R{1'b0}};
mem7 <= {R{1'b0}};
mem8 <= {R{1'b0}};
dat_o <= {R{1'b0}};
end else begin
mem0 <= mem_next0;
mem1 <= mem_next1;
mem2 <= mem_next2;
mem3 <= mem_next3;
mem4 <= mem_next4;
mem5 <= mem_next5;
mem6 <= mem_next6;
mem7 <= mem_next7;
mem8 <= mem_next8;
dat_o <= sum_div;
end
end
// Next-state logic
assign mem_next0 = read_en ? $signed(dat_i) : mem0;
assign mem_next1 = read_en ? mem0 : mem1;
assign mem_next2 = read_en ? mem1 : mem2;
assign mem_next3 = read_en ? mem2 : mem3;
assign mem_next4 = read_en ? mem3 : mem4;
assign mem_next5 = read_en ? -mem4 : mem5;
assign mem_next6 = read_en ? mem5 : mem6;
assign mem_next7 = read_en ? mem6 : mem7;
assign mem_next8 = read_en ? mem7 : mem8;
// Output
assign sum = $signed(
{mem0, 2'b0}
) + // error[ 0] * 4
$signed(
{mem1, 1'b0}
) + $signed(
mem1
) + // error[-1] * 3
$signed(
{mem2, 1'b0}
) + // error[-2] * 2
$signed(
mem3
) + // error[-3] * 1
// error[-4] * 0
$signed(
mem5
) + // error[-5] * -1
$signed(
{mem6, 1'b0}
) + // error[-6] * -2
$signed(
{mem7, 1'b0}
) + $signed(
mem7
) + // error[-7] * -3
$signed(
{mem8, 2'b0}
); // error[-8] * -4
assign sum_div = $signed(sum[R-1:0]);
endmodule
| 7.612788 |
module slotExp (
input RSTb,
input ADFFFF,
input SLTSL,
input WRb,
input [7:0] DIN,
input [1:0] PAGE,
output [7:0] DOUT,
output reg [3:0] subSLT,
output outSSREG
);
reg [7:0] regSS;
reg [1:0] BSEL;
always @(negedge WRb or negedge RSTb)
if (~RSTb) regSS <= 8'h00;
else if (ADFFFF & SLTSL) regSS <= DIN;
assign DOUT = ~regSS;
assign outSSREG = SLTSL & ADFFFF;
always @(*) begin
case (PAGE)
2'b00: BSEL = regSS[1:0];
2'b01: BSEL = regSS[3:2];
2'b10: BSEL = regSS[5:4];
2'b11: BSEL = regSS[7:6];
endcase
end
always @(*) begin
if (SLTSL)
case (BSEL)
2'b00: subSLT = 4'b0001;
2'b01: subSLT = 4'b0010;
2'b10: subSLT = 4'b0100;
2'b11: subSLT = 4'b1000;
endcase
else subSLT = 4'b0000;
end
endmodule
| 6.971912 |
module SlotTop(/*reset*/, mainClock, switch, extsegsel, extled, led, seg, segsel);
//input reset; // Zbg
input mainClock; // 6MHz̃CNbN
input [2:0] switch; // 3XCb`
//output clock1KHz; // _Ci~bN_pNbN
//output clock10Hz; // XbgpNbN
output [15:0] extled;
output [7:0] led;
output [7:0] seg;
output [1:0] segsel;
output [3:0] extsegsel;
// M
wire clk1KHz, clk10Hz;
wire [3:0] extsegsel;
wire [15:0] extled;
wire [7:0] led;
wire [7:0] seg;
wire [1:0] segsel;
wire [7:0] extseg;
// NEbÑCX^X
DividingClock S0(mainClock, // 6MHźEECNEbN
clk1KHz, // 7ZOLED̃_Ci~bN_pNbN
clk10Hz); // Xbgp̃NbN
// XbgVXẽCX^X
SlotSystem S1(clk10Hz, // Xbgp
clk1KHz, // _Ci~bN_pNbN
//reset, // Zbg
~switch[2], // Xbg̃X^[gXCb`
~switch[2:0], // ~߂XCb`
extsegsel, //
extseg,
extled[7:0]); // feverLed
endmodule
| 7.052818 |
module slot_keeper #(
parameter SLOT_COUNT = 8,
parameter SLOT_WIDTH = $clog2(SLOT_COUNT + 1)
) (
input wire clk,
input wire rst,
input wire [SLOT_WIDTH-1:0] init_slots,
input wire init_valid,
input wire [SLOT_WIDTH-1:0] slot_in,
input wire slot_in_valid,
output wire [SLOT_WIDTH-1:0] slot_out,
output wire slot_out_valid,
input wire slot_out_pop,
output wire [SLOT_WIDTH-1:0] slot_count,
// enq_err is asserted 2 cycles later after the wrong slot enq
output wire enq_err
);
wire enque = slot_in_valid && (slot_in != 0);
wire deque = slot_out_valid && slot_out_pop;
reg [SLOT_COUNT:1] occupied;
reg [SLOT_WIDTH-1:0] selected_slot;
integer i;
always @(*) begin
selected_slot = {{(SLOT_WIDTH - 1) {1'b0}}, 1'b1};
for (i = SLOT_COUNT; i >= 1; i = i - 1) if (occupied[i]) selected_slot = i;
end
reg [SLOT_COUNT:1] slot_err;
//counts enq error to know when output is not valid
reg [SLOT_WIDTH:0] last_valid_count;
always @(posedge clk) begin
if (enque) begin
if (occupied[slot_in]) begin
slot_err[slot_in] <= 1'b1;
last_valid_count <= last_valid_count + {{(SLOT_WIDTH - 1) {1'b0}}, 1'b1};
end
occupied[slot_in] <= 1'b1;
end
if (deque) occupied[selected_slot] <= 1'b0;
if (init_valid) begin
occupied <= ({SLOT_COUNT{1'b1}} >> (SLOT_COUNT - init_slots));
slot_err <= {SLOT_COUNT{1'b0}};
last_valid_count <= {{(SLOT_WIDTH - 1) {1'b0}}, 1'b1};
end
if (rst) begin
occupied <= {SLOT_COUNT{1'b0}};
slot_err <= {SLOT_COUNT{1'b0}};
last_valid_count <= {{(SLOT_WIDTH - 1) {1'b0}}, 1'b1};
end
end
reg [SLOT_WIDTH:0] slot_count_r;
reg valid_r;
always @(posedge clk)
if (rst) begin
slot_count_r <= {SLOT_WIDTH{1'b0}};
valid_r <= 1'b0;
end else begin
if (init_valid) begin
slot_count_r <= init_slots;
valid_r <= (init_slots != 0);
end
if (enque && !deque) begin
slot_count_r <= slot_count_r + {{(SLOT_WIDTH - 1) {1'b0}}, 1'b1};
valid_r <= 1'b1;
end else if (!enque && deque) begin
slot_count_r <= slot_count_r - {{(SLOT_WIDTH - 1) {1'b0}}, 1'b1};
if (slot_count_r == last_valid_count) valid_r <= 1'b0;
end
end
reg enq_err_r;
always @(posedge clk)
if (rst) enq_err_r <= 1'b0;
else enq_err_r <= |slot_err;
assign slot_out_valid = valid_r;
assign slot_out = selected_slot;
assign enq_err = enq_err_r;
assign slot_count = slot_count_r;
endmodule
| 6.558911 |
module slot_machine (
input clk,
input mode,
input spin,
input up,
input down,
input reset,
output [7:0] led,
output [3:0] an,
output [7:0] seven_segment_out,
output [7:0] sound,
output speaker
);
wire mode_db;
wire spin_db;
wire up_db;
wire down_db;
wire reset_db;
wire clk_spin;
wire clk_fast;
wire clk_increment;
wire clk_sound;
wire clk_led;
db_mode db_mode_ (
.clk(clk),
.raw_input(mode),
.db(mode_db)
);
db_spin db_spin_ (
.clk(clk),
.raw_input(spin),
.db(spin_db)
);
db_up db_up_ (
.clk(clk),
.raw_input(up),
.db(up_db)
);
db_down db_down_ (
.clk(clk),
.raw_input(down),
.db(down_db)
);
db_reset db_reset_ (
.clk(clk),
.raw_input(reset),
.db(reset_db)
);
master_clock clock_ (
.clk(clk),
.clk_spin(clk_spin),
.clk_fast(clk_fast),
.clk_increment(clk_increment),
.clk_sound(clk_sound),
.clk_led(clk_led)
);
display display_ (
.mode(mode_db),
.spin(spin_db),
.up(up_db),
.down(down_db),
.reset(reset_db),
.clk(clk),
.clk_spin(clk_spin),
.clk_fast(clk_fast),
.clk_increment(clk_increment),
.clk_led(clk_led),
.clk_sound(clk_sound),
.led(led),
.an(an),
.seven_segment_out(seven_segment_out),
.sound(sound),
.speaker(speaker)
);
endmodule
| 6.861122 |
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (reset) begin
q <= 0;
end else begin
if (slowena) begin
if (q == 4'd9) begin
q <= 0;
end else begin
q <= q + 1;
end
end
end
end
endmodule
| 7.203305 |
module AND2X1 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.586662 |
module AND2X2 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.581256 |
module BUFX16 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.017424 |
module BUFX1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.745651 |
module BUFX20 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.887067 |
module BUFX2 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.749484 |
module BUFX8 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.734604 |
module BUFXL (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.751245 |
module DLY1X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.803121 |
module DLY2X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.888716 |
module DLY4X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.836106 |
module INVX12 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.954558 |
module INVX16 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.76246 |
module INVX1 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.147471 |
module INVX20 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.664121 |
module INVX2 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.594979 |
module INVX3 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.820921 |
module INVX4 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.745486 |
module INVX8 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.420124 |
module INVXL (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.7964 |
module MXI2X1 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
// path delays
if ((A == 1'b1) && (B == 1'b0)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
if ((A == 1'b0) && (B == 1'b1)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.596441 |
module MXI2X2 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
// path delays
if ((A == 1'b1) && (B == 1'b0)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
if ((A == 1'b0) && (B == 1'b1)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.513 |
module NAND2X1 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.753512 |
module NAND2X2 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.714648 |
module NOR2X1 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.900171 |
module NOR2X2 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.834679 |
module OR2X1 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.671603 |
module OR2X2 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.718483 |
module TBUFX12 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 6.509442 |
module TBUFX16 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 6.879027 |
module TBUFX1 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 7.023106 |
module TBUFX20 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 7.162916 |
module TBUFX2 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 6.905349 |
module TBUFX8 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 6.928405 |
module TBUFXL (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 6.635503 |
module TBUFIXL (
Y,
A,
OE
);
output Y;
input A, OE;
notif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 6.787417 |
module slow2fast (
output o_sgl, //output to fast clk region
input i_sgl, //input from slow clk region
input f_clk,
input frst_n
);
reg sgl_reg1;
reg sgl_reg2;
reg sgl_reg3;
assign o_sgl = sgl_reg2 & (~sgl_reg3);
always @(posedge f_clk, negedge frst_n) begin
if (~frst_n) begin
sgl_reg1 <= 0;
sgl_reg2 <= 0;
sgl_reg3 <= 0;
end else begin
sgl_reg1 <= i_sgl;
sgl_reg2 <= sgl_reg1;
sgl_reg3 <= sgl_reg2;
end
end
endmodule
| 7.122618 |
module SlowArea_1 (
output reg io_c0,
output reg io_c1,
input clk,
input reset
);
reg [1:0] _zz_when_ClockDomain_l369;
wire when_ClockDomain_l369;
reg when_ClockDomain_l369_regNext;
reg slow_tmp;
assign when_ClockDomain_l369 = (_zz_when_ClockDomain_l369 == 2'b11);
always @(posedge clk or posedge reset) begin
if (reset) begin
io_c0 <= 1'b0;
io_c1 <= 1'b0;
_zz_when_ClockDomain_l369 <= 2'b00;
when_ClockDomain_l369_regNext <= 1'b0;
end else begin
io_c0 <= (!io_c0);
_zz_when_ClockDomain_l369 <= (_zz_when_ClockDomain_l369 + 2'b01);
if (when_ClockDomain_l369) begin
_zz_when_ClockDomain_l369 <= 2'b00;
end
when_ClockDomain_l369_regNext <= when_ClockDomain_l369;
io_c1 <= slow_tmp;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
slow_tmp <= 1'b0;
end else begin
if (when_ClockDomain_l369_regNext) begin
slow_tmp <= (!slow_tmp);
end
end
end
endmodule
| 8.238921 |
module slowclk (
input clk,
output reg hclk
);
always @(posedge clk) hclk = ~hclk;
endmodule
| 7.153401 |
module slowclock_5 (
output reg clk_slow,
input clk,
rst
);
reg [2:0] counter;
initial clk_slow <= 0;
always @(posedge clk, negedge rst) begin
if (!rst) begin
clk_slow <= 0;
counter <= 1;
end else begin
counter <= counter + 1'b1;
if (counter == 5) begin
counter <= 1;
clk_slow <= ~clk_slow;
end
end
end
endmodule
| 6.660956 |
module slowfil_fixedtaps (
i_clk,
i_reset,
i_tap_wr,
i_tap,
i_ce,
i_sample,
o_ce,
o_result
);
`ifdef FORMAL
parameter NTAPS = 16, IW = 9, TW = IW, OW = 2 * IW + 5;
`else
parameter NTAPS = 128, IW = 12, TW = IW, OW = 2 * IW + 7;
`endif
parameter [0:0] FIXED_TAPS = 0;
input wire i_clk, i_reset;
//
input wire i_tap_wr; // Ignored if FIXED_TAPS
input wire [(TW-1):0] i_tap; // Ignored if FIXED_TAPS
//
input wire i_ce;
input wire [(IW-1):0] i_sample;
output wire o_ce;
output wire [(OW-1):0] o_result;
slowfil #(
.FIXED_TAPS(1),
.NTAPS(NTAPS),
.IW(IW),
.TW(TW),
.INITIAL_COEFFS("taps.hex")
) fir (
.i_clk(i_clk),
.i_reset(i_reset),
.i_tap_wr(i_tap_wr),
.i_tap(i_tap),
.i_ce(i_ce),
.i_sample(i_sample),
.o_ce(o_ce),
.o_result(o_result)
);
endmodule
| 8.350244 |
module slowfil_srl_fixedtaps (
i_clk,
i_reset,
i_tap_wr,
i_tap,
i_ce,
i_sample,
o_ce,
o_result
);
`ifdef FORMAL
parameter NTAPS = 16, IW = 9, TW = IW, OW = 2 * IW + 5;
`else
parameter NTAPS = 128, IW = 12, TW = IW, OW = 2 * IW + 7;
`endif
parameter [0:0] FIXED_TAPS = 0;
input wire i_clk, i_reset;
//
input wire i_tap_wr; // Ignored if FIXED_TAPS
input wire [(TW-1):0] i_tap; // Ignored if FIXED_TAPS
//
input wire i_ce;
input wire [(IW-1):0] i_sample;
output wire o_ce;
output wire [(OW-1):0] o_result;
// This is a modified variant of the original slowfil that uses a
// shift-register approach to store all input samples
slowfil_srl #(
.FIXED_TAPS(1),
.NTAPS(NTAPS),
.IW(IW),
.TW(TW),
.INITIAL_COEFFS("taps.hex")
) fir (
.i_clk(i_clk),
.i_reset(i_reset),
.i_tap_wr(i_tap_wr),
.i_tap(i_tap),
.i_ce(i_ce),
.i_sample(i_sample),
.o_ce(o_ce),
.o_result(o_result)
);
endmodule
| 8.291486 |
module slowsampleclk (
input clock,
input reset,
output reg new_clock
);
reg [21:0] clock_counter = 0;
always @(posedge clock) begin
if (reset) begin
clock_counter <= 0;
new_clock <= 0;
end else if (clock_counter == 6) begin // sample slow clock //675000
new_clock <= ~new_clock;
clock_counter <= 0;
end else clock_counter <= clock_counter + 1;
end
endmodule
| 6.707127 |
module slow_addr (
a,
b,
out,
carry
);
parameter WIDTH = 64;
input [WIDTH-1:0] a, b;
output [WIDTH-1:0] out;
output carry;
wire [WIDTH-1:0] carry_vec;
genvar i;
generate
if (WIDTH == 1) begin
full_addr fa (
a,
b,
out,
1'b0,
carry
);
end else begin
for (i = 0; i < WIDTH; i = i + 1) begin
if (i == 0) begin
full_addr fa (
a[i],
b[i],
out[i],
1'b0,
carry_vec[i]
);
end else begin
full_addr fa (
a[i],
b[i],
out[i],
carry_vec[i-1],
carry_vec[i]
);
end
end
end
endgenerate
assign carry = carry_vec[WIDTH-1];
endmodule
| 8.354973 |
module half_addr (
a,
b,
out,
carry
);
input a, b;
output out, carry;
xor2$ add_x (
out,
a,
b
);
and2$ carry_a (
carry,
a,
b
);
endmodule
| 7.083188 |
module full_addr (
a,
b,
out,
cin,
cout
);
input a, b, cin;
output out, cout;
wire overflow, overflow2, out_m;
half_addr ha0 (
a,
b,
out_m,
overflow
);
half_addr ha1 (
out_m,
cin,
out,
overflow2
);
or2$ carry_o (
cout,
overflow,
overflow2
);
endmodule
| 7.496224 |
module slow_bridge (
// 32-bit local bus (slave)
input lb_clk,
input [14:0] lb_addr,
input lb_read,
output [7:0] lb_out,
// Output status bit, valid in slow_clk domain
output invalid, // indicates internal data transfer in progress
// 8-bit shift-register port (master)
input slow_clk,
output slow_op,
input slow_snap,
input [7:0] slow_out
);
reg running = 0, shifting = 0;
reg [8:0] write_addr = 0;
always @(posedge slow_clk) begin
if (slow_snap | &write_addr) running <= slow_snap;
if (running) write_addr <= write_addr + 1;
shifting <= running & |write_addr[8:4];
end
wire [7:0] ram_out;
dpram #(
.aw(9),
.dw(8)
) ram (
.clka (slow_clk),
.clkb (lb_clk),
.addra(write_addr),
.dina (slow_out),
.wena (running),
.addrb(lb_addr[8:0]),
.doutb(ram_out)
);
assign lb_out = ram_out; // pad from 8 to 32 bits?
assign slow_op = slow_snap | shifting;
assign invalid = running;
endmodule
| 7.247183 |
module slow_clk_20kHz (
input CLOCK,
output CLK_20kHz
);
reg [12:0] COUNTER = 12'b0;
reg slow_clock = 0;
always @(posedge CLOCK) begin
if (COUNTER == 12'b100111000011) begin
COUNTER <= 0;
slow_clock <= ~slow_clock;
end else COUNTER <= COUNTER + 1;
end
assign CLK_20kHz = slow_clock;
endmodule
| 7.061422 |
module top_module (
input clk,
input slowena,
input reset,
output reg [3:0] q
);
always @(posedge clk) begin
if (reset || q == 9 && slowena) q <= 0;
else begin
if (!slowena) q <= q;
else q <= q + 1;
end
end
endmodule
| 7.203305 |
module slow_memory (
clk,
mem_read,
mem_write,
mem_addr,
mem_wdata,
mem_rdata,
mem_ready
);
parameter MEM_NUM = 256;
parameter MEM_WIDTH = 128;
parameter LATENCY = 15; // negedge clock after [Unconditional carry(15ns/CYCLE)+1] cycle
parameter IDLE = 2'd0;
parameter WAIT = 2'd1;
parameter BUBBLE = 2'd2;
parameter READY = 2'd3;
input clk;
input mem_read, mem_write;
input [27:0] mem_addr;
input [MEM_WIDTH-1:0] mem_wdata;
output [MEM_WIDTH-1:0] mem_rdata;
output mem_ready;
// internal FF
reg [31:0] mem [MEM_NUM*4-1:0];
reg [31:0] mem_next[MEM_NUM*4-1:0];
reg [1:0] state, state_next;
// input FF
reg mem_read_r, mem_write_r;
reg [ 27:0] mem_addr_r;
reg [MEM_WIDTH-1:0] mem_wdata_r;
// output FF
reg mem_ready, mem_ready_next;
reg [MEM_WIDTH-1:0] mem_rdata, mem_rdata_next;
integer i;
always @(*) begin // FSM & control sig
case (state)
IDLE: begin
if (mem_read_r || mem_write_r) begin
state_next = WAIT;
end else begin
state_next = IDLE;
end
mem_ready_next = 1'b0;
end
WAIT: begin
#(LATENCY);
state_next = BUBBLE;
mem_ready_next = 1'b0;
end
BUBBLE: begin
// mem_ready PULL UP just 1 cycle
state_next = READY;
mem_ready_next = 1'b1;
end
READY: begin
state_next = IDLE;
mem_ready_next = 1'b0;
end
default: begin
state_next = IDLE;
mem_ready_next = 1'b0;
end
endcase
end
always @(*) begin // Mem array
for (i = 0; i < MEM_NUM * 4; i = i + 1) mem_next[i] = mem[i];
if (state == BUBBLE) begin
if (~mem_read_r && mem_write_r) begin
mem_next[mem_addr_r*4] = mem_wdata_r[31:0];
mem_next[mem_addr_r*4+1] = mem_wdata_r[63:32];
mem_next[mem_addr_r*4+2] = mem_wdata_r[95:64];
mem_next[mem_addr_r*4+3] = mem_wdata_r[127:96];
end
if (mem_read_r && ~mem_write_r) begin
mem_rdata_next = {
mem[mem_addr_r*4+3], mem[mem_addr_r*4+2], mem[mem_addr_r*4+1], mem[mem_addr_r*4]
};
end
end
end
always @(negedge clk) begin
state <= state_next;
mem_ready <= mem_ready_next;
mem_rdata <= mem_rdata_next;
for (i = 0; i < MEM_NUM * 4; i = i + 1) mem[i] <= mem_next[i];
end
always @(negedge clk) begin
mem_read_r <= mem_read;
mem_write_r <= mem_write;
mem_addr_r <= mem_addr;
mem_wdata_r <= mem_wdata;
end
endmodule
| 7.713766 |
module AND2X1 (
Y,
A,
B
);
output Y;
input A, B;
// Function
and (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.586662 |
module AND2X2 (
Y,
A,
B
);
output Y;
input A, B;
// Function
and (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.581256 |
module BUFX16 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.017424 |
module BUFX2 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.749484 |
module BUFX20 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.887067 |
module BUFX8 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.734604 |
module DLY1X1 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.803121 |
module DLY1X4 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.769339 |
module DLY2X1 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.888716 |
module DLY2X4 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.784512 |
module DLY4X1 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.836106 |
module DLY4X4 (
Y,
A
);
output Y;
input A;
// Function
buf (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.727196 |
module INVX1 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.147471 |
module INVX12 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.954558 |
module INVX16 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.76246 |
module INVX2 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.594979 |
module INVX20 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.664121 |
module INVX3 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.820921 |
module INVX4 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.745486 |
module INVX6 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.139895 |
module INVX8 (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 7.420124 |
module INVXL (
Y,
A
);
output Y;
input A;
// Function
not (Y, A);
// Timing
specify
(A => Y) = 0;
endspecify
endmodule
| 6.7964 |
module MX2X8 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
// Function
wire int_fwire_0, int_fwire_1, S0__bar;
not (S0__bar, S0);
and (int_fwire_0, S0__bar, A);
and (int_fwire_1, S0, B);
or (Y, int_fwire_1, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(posedge S0 => (Y: S0)) = 0;
(negedge S0 => (Y: S0)) = 0;
endspecify
endmodule
| 6.679592 |
module MXI2X1 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire S0__bar;
not (S0__bar, S0);
and (int_fwire_0, S0__bar, A);
and (int_fwire_1, S0, B);
or (int_fwire_2, int_fwire_1, int_fwire_0);
not (Y, int_fwire_2);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(posedge S0 => (Y: S0)) = 0;
(negedge S0 => (Y: S0)) = 0;
endspecify
endmodule
| 6.596441 |
module MXI2X2 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire S0__bar;
not (S0__bar, S0);
and (int_fwire_0, S0__bar, A);
and (int_fwire_1, S0, B);
or (int_fwire_2, int_fwire_1, int_fwire_0);
not (Y, int_fwire_2);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(posedge S0 => (Y: S0)) = 0;
(negedge S0 => (Y: S0)) = 0;
endspecify
endmodule
| 6.513 |
module MXI2X8 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire S0__bar;
not (S0__bar, S0);
and (int_fwire_0, S0__bar, A);
and (int_fwire_1, S0, B);
or (int_fwire_2, int_fwire_1, int_fwire_0);
not (Y, int_fwire_2);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(posedge S0 => (Y: S0)) = 0;
(negedge S0 => (Y: S0)) = 0;
endspecify
endmodule
| 6.589143 |
module MXI3X4 (
Y,
A,
B,
C,
S0,
S1
);
output Y;
input A, B, C, S0, S1;
// Function
wire int_fwire_0, int_fwire_1, int_fwire_2;
wire int_fwire_3, int_fwire_4, int_fwire_5;
wire S0__bar, S1__bar;
not (S0__bar, S0);
and (int_fwire_0, S0__bar, A);
and (int_fwire_1, S0, B);
or (int_fwire_2, int_fwire_1, int_fwire_0);
not (S1__bar, S1);
and (int_fwire_3, S1__bar, int_fwire_2);
and (int_fwire_4, S1, C);
or (int_fwire_5, int_fwire_4, int_fwire_3);
not (Y, int_fwire_5);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
(C => Y) = 0;
(posedge S0 => (Y: S0)) = 0;
(negedge S0 => (Y: S0)) = 0;
(posedge S1 => (Y: S1)) = 0;
(negedge S1 => (Y: S1)) = 0;
endspecify
endmodule
| 6.578424 |
module NAND2X1 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
and (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.753512 |
module NAND2X2 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
and (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.714648 |
module NOR2X1 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
or (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.900171 |
module NOR2X2 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
or (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.834679 |
module NOR2X6 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
or (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.536029 |
module NOR2X8 (
Y,
A,
B
);
output Y;
input A, B;
// Function
wire int_fwire_0;
or (int_fwire_0, A, B);
not (Y, int_fwire_0);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.745176 |
module OR2X1 (
Y,
A,
B
);
output Y;
input A, B;
// Function
or (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.671603 |
module OR2X2 (
Y,
A,
B
);
output Y;
input A, B;
// Function
or (Y, A, B);
// Timing
specify
(A => Y) = 0;
(B => Y) = 0;
endspecify
endmodule
| 6.718483 |
module TBUFX1 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 7.023106 |
module TBUFX12 (
Y,
A,
OE
);
output Y;
input A, OE;
// Function
bufif1 (Y, A, OE);
// Timing
specify
(A => Y) = 0;
(OE => Y) = 0;
endspecify
endmodule
| 6.509442 |
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