code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module Name: ssDisplayer
//////////////////////////////////////////////////////////////////////////////////
module ssDisplayer(
//====================================================
//======= Input ======
//====================================================
input ... | 7.117325 |
module: ssDecoder
//////////////////////////////////////////////////////////////////////////////////
module ssDecoder(
//====================================================
//======= Input ======
//====================================================
input [2:0] ... | 6.986735 |
module SSDTranslation
/*** IN/OUT ***/
(
// IN
input [7 : 0] Value,
// OUT
output [6 : 0] Result
);
reg [6 : 0] SegValue;
always @(Value) begin
case (Value)
0: SegValue <= 7'b1000000;
1: SegValue <= 7'b1111001;
2: ... | 8.128128 |
module ssd_dis (
input CLK,
input RST,
input [9:0] DIN,
output reg [3:0] sel,
output reg [6:0] segs
);
//generate 2kHZ scanning clock
parameter cnt_max = 49999;
reg [15:0] cnt;
reg clk_scan;
always @(posedge CLK) begin
if (cnt == cnt_max) cnt <= 16'b0;
else cnt <= cnt + 1'b1;
en... | 7.030548 |
module ssd_driver (
in_bcd,
out_ssd
);
input [3:0] in_bcd; // input in BCD
output [6:0] out_ssd; // output to Seven-Segment Display
reg [6:0] out_ssd;
always @(in_bcd) begin
case (in_bcd)
0: out_ssd = 7'b0000001;
1: ... | 7.53888 |
module ssd_freq_div (
input clock_in,
output reg clock_out
);
parameter width = 32;
reg [width-1:0] count;
initial begin
count = 0;
clock_out = 0;
end
always @(posedge clock_in) begin
if (count == 50000000) begin
count <= 0;
clock_out = ~clock_out;
end else count <= count +... | 6.592768 |
module ssd_gen (
input [31:0] SW,
input clk,
input rst,
output reg [6:0] a_to_g,
output reg [7:0] an,
output wire dp
);
assign dp = `dp_off;
wire [ 2:0] s;
wire [ 7:0] aen;
reg [19:0] clkdiv;
reg [ 3:0] digit;
assign s = clkdiv[19:17];
assign aen = `initial_digit;
// clo... | 7.699001 |
module ssd_letters (
input wire clk,
//input wire player_place, and player fire
input wire p1fire,
input wire p2fire,
input wire p1place,
input wire p2place,
output wire [7:0] cathode,
output wire [7:0] anode
);
wire [2:0] refreshcounter;
wire refreshclock;
clk_div #(49999) refr... | 7.349804 |
module SSD_0 (
in,
out
);
input [3:0] in;
output [6:0] out;
reg [6:0] out;
always @(in) begin
case (in)
4'b0000: out <= 7'b0000001;
4'b0001: out <= 7'b1001111;
4'b0010: out <= 7'b0010010;
4'b0011: out <= 7'b0000110;
4'b0100: out <= 7'b1001100;
4'b0101: out <= 7'b0... | 6.689118 |
module Segments_tb ();
reg [3:0] BCD;
wire [6:0] SEG;
//BCD = 0;
BCD7Segments SEG1 (
BCD,
SEG
);
initial begin
$display("BCD\tSEG");
$monitor("%b %b", BCD, SEG);
BCD = 0;
#10 BCD = 1;
#10 BCD = 2;
#10 BCD = 3;
#10 BCD = 4;
#10 BCD = 5;
#10 BCD = 6;
#10 BC... | 6.607117 |
module SSD_Top (
input [3:0] switch,
output [6:0] led,
output [7:0] anode, //which ssd out of 8 will be used
output dp
);
assign anode = 8'b11111110; //only first ssd will be enable
assign dp = 1;
ssd D1 (
.x(switch),
.a_to_g(led)
);
endmodule
| 6.608239 |
module ssdController4 #(
parameter CLOCK_PERIOD = 10
) (
clk,
rst,
mode,
digit3,
digit2,
digit1,
digit0,
seg,
an
);
localparam TARGET_PERIOD = 655360; //655.36µs or ~1.526 kHz
localparam DIVISION_COUNT = $clog2(TARGET_PERIOD / CLOCK_PERIOD) - 1;
input clk, rst;
input [3:... | 7.160001 |
module ssdController2 #(
parameter CLOCK_PERIOD = 10
) (
clk,
rst,
mode,
digit1,
digit0,
seg,
an
);
localparam TARGET_PERIOD = 655360; //655.36µs or ~1.526 kHz
localparam DIVISION_COUNT = $clog2(TARGET_PERIOD / CLOCK_PERIOD) - 1;
input clk, rst;
input [1:0] mode; //each bit rep... | 7.160001 |
module ssd_encode (
in,
abcdefg
);
parameter zero = 7'b0000001, one = 7'b1001111, two = 7'b0010010;
parameter thr = 7'b0000110, four = 7'b1001100, five = 7'b0100100;
parameter six = 7'b0100000, svn = 7'b0001111, eght = 7'b0000000;
parameter nine = 7'b0000100, A = 7'b0001000, B = 7'b1100000;
parameter ... | 6.711742 |
module sseg #(
parameter X = 0,
parameter Y = 0,
parameter W = 100,
parameter H = 200
) (
input wire [7:0] bcd,
input wire [9:0] x,
input wire [9:0] y,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b
);
parameter VLD = (W / 4); //vertical line depth |
pa... | 6.650912 |
module ssegment (
input clk,
rst,
input [3:0] hited,
input [3:0] hit,
output reg [7:0] SSEG_AN,
SSEG_CA
);
parameter FIRST = 8'b1111_1110, THIRD = 8'b1111_1011;
parameter LIFE = 4'd3;
reg [31:0] count2;
reg a;
reg [3:0] score, life;
wire [7:0] w1, w3;
initial begin
score = 4... | 7.056711 |
module sseg_decode #(
parameter REG = 0, // register outputs
parameter INV = 1 // invert outputs
) (
input wire clk,
input wire rst,
input wire [4-1:0] num, // input
output wire [7-1:0] sseg // output
);
reg [7-1:0] sseg_decode;
always @(*) begin
case (num)
... | 6.855334 |
module SSEG_Display (
clk_50M,
reset,
sseg_a_to_dp,
sseg_an,
data
);
input wire clk_50M; // 50MHz clock input
input wire reset; // 8-bit DIP switch
output wire [7:0] sseg_a_to_dp; // cathode of seven segment display( a,b,c,d,e,f,g,dp )
output wire [3:0] sseg_an; // anaode of seven segme... | 7.886854 |
module: sseg_display
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sseg_display_tb;
// Inputs
reg clk;
reg reset;
reg [3:0] hexa3;
reg [3:0] hexa2;
reg [3:0] hexa1;
reg [3:... | 6.912911 |
module: sseg_display
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sseg_display_test;
// Inputs
reg rst;
reg clk;
reg [7:0] value;
// Outputs
wire [3:0] sseg_an;
wire [7:0... | 6.912911 |
module sseg_driver (
input wire [3 : 0] digit, /* digit to show */
input wire [1 : 0] sel, /* place to show */
output reg [3 : 0] anode, /* common anode enable */
output reg [6 : 0] cathode /* cathode enable */
);
/* decode anode enable signal */
always @(sel) begin
case (sel)
2'b00: ... | 7.535657 |
module sseg_sweeper (
input wire CLOCK_SWEEP,
input wire [19:0] GPIO_IN,
output reg [5:0] SEL,
output wire [6:0] HEX
);
integer CASE;
reg [3:0] BIN;
wire [7:0] PARA;
always @(posedge CLOCK_SWEEP) begin
case (CASE)
0: begin
SEL <= 6'b111110;
BIN[3:0] <= GPIO_IN[3:0];
... | 6.772916 |
module sseg_x4_top (
input [15:0] sw,
input clk,
input rst,
output [0:6] seg,
output [3:0] an,
output dp
);
wire [3:0] not_used; // Place holder individual anodes which are handled by digit_selector
wire clkd; // 200 Hz Clock
wire [0:3] hex_num; // Can't be called sw any more so I'll c... | 7.829466 |
module ssg_emb_dc_ballast_dec128 (
input clk, // ADC clock
input reset_n, // syetm reset
input cnr128, // Decimator pulse
input dec_rate, // Decimation rate control register bit 1: M=64, 0: M=128
input [15:0] offset, // zero offset register
input [21:0]... | 6.798838 |
module ssg_emb_dc_ballast_diff (
input clk_adc, // ADC clock
input reset_n, // System reset
input data, // ADC data in clk_adc domain
input dec_rate, // Decimation rate control register bit in clk_adc domain 1: M=64 or 8, 0: M=128 or 16
// All outputs in clk_adc domain
output... | 6.798838 |
module ssg_emb_sd_adc_dec128 (
input clk, // ADC clock
input reset_n, // syetm reset
input cnr128, // Decimator pulse
input dec_rate, // Decimation rate control register bit 1: M=64, 0: M=128
input [15:0] offset, // zero offset register
input [21:0] cn_... | 6.950756 |
module ssg_emb_sd_adc_dec16 (
input clk, // ADC clock
input reset_n, // syetm reset
input cnr16, // Decimator pulse
input dec_rate, // Decimation rate control register bit 1: M=8, 0: M=16
input [21:0] cn_in, // Input from integrator
output reg [9:0] ... | 6.950756 |
module ssg_emb_sd_adc_diff (
input clk, // System clock
input clk_adc, // ADC clock
input reset_n, // System reset
input data, // ADC data in clk_adc domain
input start, // Start conversion pulse in system clk domain
input dec_rate, // Decimation rate control register bit in... | 6.950756 |
module bit_clock_synchronizer (
rst,
clk,
serial_clock_in,
bit_clock
);
(* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:60" *)
output bit_clock;
wire bit_clock;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
input clk;
wire clk;
(* ... | 7.69458 |
module frame_clock_synchronizer (
rst,
clk,
frame_start_in,
frame_clock
);
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
input clk;
wire clk;
(* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:61" *)
output frame_clock;
wire frame_clock... | 6.816093 |
module ssio_ddr_out #(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Use 90 degree clock fo... | 6.621865 |
module ssio_ddr_out_diff #(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Use 90 degree clo... | 6.75509 |
module ssio_sdr_out #(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register in b... | 7.092957 |
module ssio_sdr_out_diff #(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register... | 7.06669 |
module OR (
output O,
input I1,
input I2
);
assign O = I1 | I2;
endmodule
| 7.937706 |
module NOT (
output O,
input I
);
assign O = ~I;
endmodule
| 7.920372 |
module NAND (
output reg O,
input I1,
input I2
);
always @(*) begin
O = ~(I1 & I2);
end
endmodule
| 7.659562 |
module NOR (
output reg O,
input I1,
input I2
);
always @(*) begin
O = ~(I1 | I2);
end
endmodule
| 7.918619 |
module EXOR (
output O,
input I1,
input I2
);
LUT2 #(
.INIT(4'b0110)
) lut (
.O (O),
.I1(I1),
.I0(I2)
);
endmodule
| 7.264641 |
module EXNOR (
output O,
input I1,
input I2
);
LUT2 #(
.INIT(4'b1001)
) lut (
.O (O),
.I1(I1),
.I0(I2)
);
endmodule
| 7.07346 |
module TRI (
output O,
input I,
input E
);
assign O = E ? I : 1'bz;
endmodule
| 7.03312 |
module TOP (
output O_or,
output O_not,
output O_nand,
output O_nor,
output O_exor,
output O_exnor,
output O_tri,
input I1,
input I2
);
OR or_gate (
O_or,
I1,
I2
);
NOT not_gate (
O_not,
I1
);
NAND nand_gate (
O_nand,
I1,
I... | 8.04928 |
module contains the top level design that will be implemented
* the FPGA board.
*/
`timescale 1ns/100ps
module ssl(eclk, erst, din, dIdA, dIdB, dIdC, dSsA);//, dSsB, dSsC);
/* Parameter declaration */
parameter RSTSIZE = 4;
parameter ENASIZE = 2;
parameter DIV = 50;
parameter NDATA = 12... | 7.358377 |
module ssled (
input [15:0] in_score,
input clk_disp,
output [6:0] seg,
output [3:0] an
);
// AN3 - AN0
// CA - CG
reg [3:0] unary;
reg [1:0] binary;
wire [3:0] d;
initial begin
unary = 4'b1110;
binary = 2'b0;
end
wire [15:0] n;
assign n = in_score;
assign d = n[(4*binar... | 6.660095 |
module ssled_disp (
input [3:0] digit,
input [3:0] ssled_sel,
output [6:0] seg,
output [3:0] an
);
reg [6:0] seg_reg;
reg [3:0] an_reg;
reg [6:0] map[0:9];
assign seg[6:0] = seg_reg[6:0];
assign an[3:0] = an_reg[3:0];
initial begin
seg_reg[6:0] = 7'b0;
an_reg[3:0] = 4'b0;
ma... | 6.743125 |
module sspi (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
input i_clk,
input i_rst,
input spi_clk,
input spi_mosi,
output reg spi_miso,
output reg wb_cyc,
output reg wb_stb,
output reg [23:0] wb_adr,
input [15:0] wb_i_dat,
output reg [15:0] wb_o_dat,
out... | 8.472542 |
module SspRevAnd (
// Inputs
TieOff1,
TieOff2,
// Outputs
Revision
);
// Inputs
input TieOff1; // AND gate input 1
input TieOff2; // AND gate input 2
// Outputs
output Revision; // AND gate output
// ---------------------------------------------------------------------
//
// ... | 6.880756 |
modules for operating the ssp implementation
// Improved from original file as required/desired
`timescale 1 ns / 10 ps
module ssp_test1;
reg clock, clear_b, pwrite, psel, sspclkin, sspfssin, ssprxd;
reg [ 7: 0 ] data_in;
wire sspoe_b, ssptxd, sspfssout, sspclkout, ssptxintr, ssprxintr;
wire [ 7: 0 ] data_out;
ini... | 7.655239 |
module ssp_test2;
reg clock, clear_b, pwrite, psel;
reg [7:0] data_in;
wire [7:0] data_out;
wire sspoe_b, tx_to_rx, clk_wire, fss_wire, ssptxintr, ssprxintr;
initial begin
clock = 1'b0;
clear_b = 1'b0;
psel = 1'b1;
@(posedge clock);
#1;
@(posedge clock);
data_in = 8'b11111111; ... | 7.127636 |
module implements a parameterized version of a distributed
// RAM synchronous FIFO. The address width, FIFO width and depth
// are all specified by parameters. Default parameters settings
// describe a 16x16 FIFO with Full (FF), Empty (EF), and Half
// Full (HF) fla... | 6.904081 |
module implements the Baud Rate Generator for the SSP
// UART described for the 1700-0403 MicroBridge Option Card.
//
// The Baud Rate Generator implements the 16 baud rates defined
// in Table 3 of the SSP UART Specification.
//
// Dependencies:
//
// Revision History:
//
// 0.... | 7.842559 |
module ssr (
input [4:1] j,
input p,
i,
y,
input [3:0] senha_sistema,
senha_usuario,
input gerador_frequencia,
output alarme
);
wire habilitador;
wire [5:0] fio;
wire and1, or1;
// instanciacao do modulo de entrada de senha
entrada_senha es_ssr (
senha_usuario,
s... | 8.314705 |
module ssram(clock,addr,data,wen,ce);
parameter addrbits = 19;
parameter depth = 524288;
input clock;
input [addrbits-1:0] addr;
inout [35:0] data;
input wen;
input ce;
reg [35:0] ram [0:depth-1];
reg read_d1,read_d2;
reg write_d1,write_d2;
reg [addrbits-1:0] addr_d1,addr_d2;
... | 7.670943 |
module ssram_test (
input clk,
input reset_n,
// ssram
output reg [18:0] ssram_address,
output reg ssram_oe_n,
output reg ssram_writeen_n,
output reg [3:0] ssram_byteen_n,
output ssram_adsp_n,
output ssram_clk,
output ssram_globalw_n,
output ssram_advance_n,
output ssram... | 7.729181 |
module ssrv_memory
(
input clk,
input rst,
input imem_req,
input `N(`XLEN) imem_addr,
output imem_resp,
output `N(`XLEN) ... | 6.58188 |
module sssp_pipeline (
clk,
rst,
last_input_in,
word_in,
word_in_valid,
control,
current_level,
control_out,
last_input_out,
word_out,
valid_out,
word_in_valid_out
);
parameter ADDR_W = 2;
parameter pipeline_id = 0;
parameter DATA_W = 32;
input clk, rst;
input... | 6.685683 |
module sss_fallthrough_small_fifo #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout... | 8.243607 |
module sss_small_fifo #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, //... | 8.374224 |
module sstv_pixel (
input reset,
input [11:0] freq,
output reg [1:0] color
);
localparam PIXEL_BLACK = 2'b00;
localparam PIXEL_DARKGRAY = 2'b01;
localparam PIXEL_LIGHTGRAY = 2'b10;
localparam PIXEL_WHITE = 2'b11;
localparam FREQ_BLACK_LOWER = 12'd1500;
localparam FREQ_BLACK_UPPER = 12'd1700;
... | 7.10573 |
module sstv_pixel_tb;
reg clk;
reg reset;
reg [11:0] freq;
wire [1:0] color;
reg [1:0] color_check;
reg test_fail;
wire [6:0] vis_code;
wire valid;
localparam CLK_TICKS_30MS = 32'd3_000;
sstv_pixel SSTV_PIXEL (
.reset(reset),
.freq(freq),
.color(color)... | 7.50039 |
module sstv_tb;
reg clk;
reg reset;
reg [11:0] freq;
reg test_fail;
wire [14:0] vid_addr;
wire [1:0] vid_pixel;
wire [6:0] vis_code;
wire vis_valid;
localparam CLK_TICKS_10MS = 32'd1_000;
localparam CLK_TICKS_30MS = 32'd3_000;
localparam CLK_TICKS_300MS = 32'd30_000... | 6.973788 |
module vga (
input clk,
input reset,
input [1:0] alt_color,
input video_on,
input [9:0] pixel_row,
input [9:0] pixel_col,
// Input from bitmap ROM
output [14:0] bitmap_rom_addr,
input bitmap_rom_data,
// Input from SSTV RAM
output [14:0] sstv_ram_addr,
in... | 6.790484 |
module ssvga_wbs_if (
// Clock and reset
wb_clk_i,
wb_rst_i,
// WISHBONE Slave I/F
wbs_cyc_i,
wbs_stb_i,
wbs_sel_i,
wbs_we_i,
wbs_adr_i,
wbs_dat_i,
wbs_cab_i,
wbs_dat_o,
wbs_ack_o,
wbs_err_o,
wbs_rty_o,
// Other signals
ssvga_en,
pal_wr_en,
p... | 6.575547 |
module ss_A2D (
clk,
rst_n,
strt_cnv,
result,
cnv_cmplt
);
input clk, rst_n; // clock and active low reset
input strt_cnv; // start conversion
output [9:0] result; // result of average of 8-samples
output cnv_cmplt; // asserted for 1 clock when conversion completes
wire [9:0] result... | 6.864672 |
module SS_ADDSUB (
CLK,
INIT,
IN,
SIGN,
R_condition,
OUT,
SIGN_out
);
parameter N = 6;
//parameter DIFFCOUNTER_SIZE = 5;
//parameter DIFFCOUNT_LOWERLIM = 4;
parameter DIFFCOUNTER_SIZE = 1;
parameter DIFFCOUNT_LOWERLIM = 0;
input CLK, INIT;
input [N-1:0] IN, SIGN;
input R_co... | 7.109077 |
module SS_ADDSUB2 (
CLK,
INIT,
IN,
SIGN,
R_condition,
OUT,
SIGN_out
);
parameter N = 2;
parameter DIFFCOUNTER_SIZE = 2;
parameter DIFFCOUNT_MIN = 1;
input CLK, INIT;
input [N-1:0] IN, SIGN;
input R_condition;
output OUT, SIGN_out;
wire INPUT_SUM_pos, INPUT_SUM_neg;
wire... | 6.832631 |
module Mux_PC (
input [63:0] PC_in,
input [63:0] Shift_in,
input Jump_control,
output reg [63:0] PC_out
);
always @(PC_in, Shift_in, Jump_control, PC_out) begin
if (Jump_control == 0) begin
PC_out = PC_in;
end else begin
PC_out = Shift_in;
end
end
endmodule
| 8.32273 |
module Mux_REG (
input [4:0] in_1,
input [4:0] in_2,
input Reg2Loc_control,
output reg [4:0] Mux_out
);
always @(in_1, in_2, Reg2Loc_control) begin
if (Reg2Loc_control == 0) begin
Mux_out = in_1;
end else begin
Mux_out = in_2;
end
end
endmodule
| 6.735029 |
module Mux_ALU (
input [63:0] in_1,
input [63:0] in_2,
input ALUSrc_control,
output reg [63:0] Mux_out
);
always @(in_1, in_2, ALUSrc_control, Mux_out) begin
if (ALUSrc_control == 0) begin
Mux_out = in_1;
end else begin
Mux_out = in_2;
end
end
endmodule
| 7.307889 |
module Mux_Data_Memory (
input [63:0] Data_read,
input [63:0] ALU_out,
input Mem2Reg_control,
output reg [63:0] Mux_out
);
always @(Data_read, ALU_out, Mem2Reg_control, Mux_out) begin
if (Mem2Reg_control == 0) begin
Mux_out = ALU_out;
end else begin
Mux_out = Data_read;
end
... | 8.61217 |
module Sign_Extend (
input [31:0] instruction_in,
output reg [63:0] immediate_out
);
always @(instruction_in) begin
if (instruction_in[31:26] == 6'b000101) begin // B
immediate_out[25:0] = instruction_in[25:0];
immediate_out[63:26] = {64{immediate_out[25]}};
end else if (instruction_... | 7.338842 |
module Shift_LEFT2 (
input [63:0] Data_in,
output reg [63:0] Data_out
);
always @(Data_in) begin
Data_out = Data_in << 2;
end
endmodule
| 7.060616 |
module ALU (
input [63:0] A,
B,
input [3:0] SELECT,
output reg [63:0] OUT,
output reg ZEROFLAG
);
always @(A or B or SELECT) begin
case (SELECT)
4'b0000: OUT = A & B;
4'b0001: OUT = A | B;
4'b0010: OUT = A + B;
4'b0110: OUT = A - B;
4'b0111: OUT = B;
4'b110... | 7.960621 |
module Registers (
input [4:0] read_1,
input [4:0] read_2,
input [4:0] Reg_write,
input [63:0] Data_write,
input RegWrite_control,
output reg [63:0] data_1,
output reg [63:0] data_2
);
reg [63:0] Data[31:0];
integer initCount;
initial begin
for (initCount = 0; initCount < 31; ... | 7.405039 |
module Data_Memory (
input [63:0] address_in,
input [63:0] data_in,
input MemRead_control,
input MemWrite_control,
output reg [63:0] Data_out
);
reg [63:0] Data[31:0];
integer initCount;
initial begin
for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
Data[initCo... | 7.239913 |
module SS_ARM_tb;
/* Clock Signal */
reg CLK;
/* Wires to connect instruction memory to CPU */
wire [63:0] PC_instruction;
wire [31:0] Out_instruction;
/* Wires to connect registers to CPU */
wire [4:0] Read_register_1;
wire [4:0] Read_register_2;
wire [4:0] Write_register;
wire [63:0] Write_data;... | 9.328874 |
module SS_Control #(
N = 4
) (
input clk, // clock freq of about 750 Hz
input rst,
input [N*4-1:0] numbers, // list of 4 bit numbers to display
output [ N-1:0] displays, // the displays (active low)
output [ 6:0] segments // abcdefg segments (active low)
);
... | 7.206497 |
module ss_dataforward (
input [4:0] Rd1e1,
Rd2e1,
Rd1e2,
Rd2e2,
input RegWriteE1,
RegWriteM1,
RegWriteW1,
RegWriteE2,
RegWriteM2,
RegWriteW2,
input [4:0] WriteRegE1,
WriteRegM1,
WriteRegW1,
WriteRegE2,
WriteRegM2,
WriteRegW2,
input [31:0] AluOutE1,
... | 8.116127 |
module data_forward_b (
input [4:0] WriteRegE,
RsD,
RtD,
input RegWriteE,
BranchD,
BranchNot,
output reg ForwardAD,
ForwardBD
);
always @(*) begin
//default case: direct values in muxes
ForwardAD <= 0;
ForwardBD <= 0;
//IF RSD AND RTD ARE EQUAL TO WRITEREGE AND BRANCH... | 8.771124 |
module ss_decode (
input clk,
input [3:0] BCD,
output [7:0] sseg_o
);
reg [7:0] sseg = 8'b11111111;
always @(posedge clk) begin
case (BCD)
4'b0000: sseg <= 8'b11000000; //00000011;
4'b0001: sseg <= 8'b11111001; //10011111;
4'b0010: sseg <= 8'b10100100; //00100101;
4'b... | 6.916481 |
module ss_disp (
bcd,
seg
);
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
always @(bcd) begin
case (bcd)
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg = 7'b1001100;
5: seg = 7'b0100100;
6: seg = 7'b0100000;
... | 7.335569 |
module ss_drive (
input clk,
rst,
input [3:0] data7,
data6,
data5,
data4,
input [3:0] data3,
data2,
data1,
data0,
input [7:0] mask,
output ssA,
ssB,
ssC,
ssD,
output ssE,
ssF,
ssG,
ssDP,
output reg AN7,
AN6,
AN5,
AN4,
output... | 7.226071 |
module SS_Driver (
input Clk,
Reset,
input [3:0] BCD3,
BCD2,
BCD1,
BCD0, // Binary-coded decimal input 1
input [3:0] BCD7,
BCD6,
BCD5,
BCD4, // Binary-coded decimal input 2
output reg [7:0] SegmentDrivers, // Digit drivers (active low)
output reg [7:0] SevenSegment //... | 6.888374 |
module SS_MOVAVG (
IN,
AVG,
CLK,
INIT
);
parameter W = 1000;
parameter N = 16;
parameter F_sampling = 5;
input IN;
input CLK, INIT;
output [N-1:0] AVG;
reg [W-1:0] BUFFER = 1'b0 - 1'b1;
reg [ 7:0] sampleCOUNTER = 8'd0;
always @(posedge CLK) begin
if (sampleCOUNTER < F_sampli... | 6.81602 |
module ss_mux (
input clk,
input [31:0] bcd,
input [7:0] dots,
output [7:0] ss_value,
output [7:0] ss_select
);
/*
* Los siguientes parámetros locales representan el "estado" de nuestro módulo,
* en el cual cada uno de ellos está asociado a la activación de un solo dígito
* del display. Nóte... | 7.543549 |
module SS_OCT_SOPC_reset_clk_50_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRE... | 6.920192 |
module sgdma_tx_out_arbitrator (
// inputs:
clk,
reset_n,
sgdma_tx_out_data,
sgdma_tx_out_empty,
sgdma_tx_out_endofpacket,
sgdma_tx_out_error,
sgdma_tx_out_startofpacket,
sgdma_tx_out_valid,
tse_mac_transmit_ready_from_sa,
// outputs:
sgdma_tx_out_ready
);
output sgdm... | 7.131253 |
module tse_mac_transmit_arbitrator (
// inputs:
clk,
reset_n,
sgdma_tx_out_data,
sgdma_tx_out_empty,
sgdma_tx_out_endofpacket,
sgdma_tx_out_error,
sgdma_tx_out_startofpacket,
sgdma_tx_out_valid,
tse_mac_transmit_ready,
// outputs:
tse_mac_transmit_data,
tse_mac_trans... | 6.631183 |
module tse_mac_receive_arbitrator (
// inputs:
clk,
reset_n,
sgdma_rx_in_ready_from_sa,
tse_mac_receive_data,
tse_mac_receive_empty,
tse_mac_receive_endofpacket,
tse_mac_receive_error,
tse_mac_receive_startofpacket,
tse_mac_receive_valid,
// outputs:
tse_mac_receive_read... | 7.122298 |
module SS_OCT_SOPC_reset_ddr2_phy_clk_out_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=O... | 6.920192 |
module SS_OCT_SOPC_reset_pll_sys_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; S... | 6.920192 |
module ext_flash_lane0_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [24:0] rdaddress;
input rdclken;
input [24:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [335... | 6.952907 |
module ext_flash_lane1_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [24:0] rdaddress;
input rdclken;
input [24:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [335... | 6.952907 |
module ext_flash (
// inputs:
address,
read_n,
select_n,
write_n,
// outputs:
data
);
inout [15:0] data;
input [24:0] address;
input read_n;
input select_n;
input write_n;
wire [15:0] data;
wire [ 7:0] data_0;
wire [ 7:0] data_1;
wire [15:0] logic_vector_gasket;
wire [... | 6.719908 |
module SS_OCT_SOPC_clock_0_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <=... | 7.008946 |
module SS_OCT_SOPC_clock_0_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to... | 7.008946 |
module SS_OCT_SOPC_clock_1_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <=... | 7.008946 |
module SS_OCT_SOPC_clock_1_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to... | 7.008946 |
module SS_OCT_SOPC_clock_2_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <=... | 7.008946 |
module SS_OCT_SOPC_clock_2_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to... | 7.008946 |
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