code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Name: ssDisplayer
//////////////////////////////////////////////////////////////////////////////////
module ssDisplayer(
//====================================================
//======= Input ======
//====================================================
input clk, // 25 MHz clock
input rst, // Asynchronus reset
input [3:0] mask, // 1-bit encode, position of displayed num e.g. 1000:rightest display
input [6:0] seg3,
input [6:0] seg2,
input [6:0] seg1,
input [6:0] seg0,
//====================================================
//======= Output ======
//====================================================
output reg [6:0] seg, // Number
output dp_on, // Dot point
output reg [3:0] an // Mux for 4 number
);
assign dp_on = 1'b1;
reg [16:0] cnt_time, next_cnt_time;
reg [6:0] next_seg;
reg [3:0] next_an;
always@(*) begin
next_cnt_time = cnt_time+1;
case(cnt_time[16:15])
2'b00: begin
next_seg = (~mask[3])?seg3:7'b1111111;
next_an = 4'b0111;
end
2'b01: begin
next_seg = (~mask[2])?seg2:7'b1111111;
next_an = 4'b1011;
end
2'b10: begin
next_seg = (~mask[1])?seg1:7'b1111111;
next_an = 4'b1101;
end
2'b11: begin
next_seg = (~mask[0])?seg0:7'b1111111;
next_an = 4'b1110;
end
endcase
end
always@(posedge clk or posedge rst) begin
if(rst) begin
cnt_time <= 17'd0;
seg <= 7'b1111111;
an <= 4'b1111;
end
else begin
cnt_time <= next_cnt_time;
seg <= next_seg;
an <= next_an;
end
end
endmodule
| 7.117325 |
module: ssDecoder
//////////////////////////////////////////////////////////////////////////////////
module ssDecoder(
//====================================================
//======= Input ======
//====================================================
input [2:0] num3, // decimal number on leftmost 7-segment (0-7)
input [2:0] num2, // decimal number on 7-segment (0-7)
input [2:0] num1, // decimal number on 7-segment (0-7)
input [2:0] num0, // decimal number on rightmost 7-segment (0-7)
//====================================================
//======= Output ======
//====================================================
//-----------to ssDisplayer-----
output [6:0] seg3, // The seven segment representation for num3
output [6:0] seg2, // The seven segment representation for num2
output [6:0] seg1, // The seven segment representation for num1
output [6:0] seg0 // The seven segment representation for num0
);
//=======================================
//======= TODO ======
wire A0,B0,C0,A1,B1,C1,A2,B2,C2,A3,B3,C3;
assign C0=num0[0];
assign B0=num0[1];
assign A0=num0[2];
assign C1=num1[0];
assign B1=num1[1];
assign A1=num1[2];
assign C2=num2[0];
assign B2=num2[1];
assign A2=num2[2];
assign C3=num3[0];
assign B3=num3[1];
assign A3=num3[2];
assign seg0[0]=(A0&~B0&~C0)|(~A0&~B0&C0);
assign seg0[1]=(A0&~B0&C0)|(A0&B0&~C0);
assign seg0[2]=(~A0&B0&~C0);
assign seg0[3]=(A0&~B0&~C0)|(~A0&~B0&C0)|(A0&B0&C0);
assign seg0[4]=(C0)|(A0&~B0);
assign seg0[5]=(~A0&B0)|(~A0&C0)|(B0&C0);
assign seg0[6]=(~A0&~B0)|(A0&B0&C0);
assign seg1[0]=(A1&~B1&~C1)|(~A1&~B1&C1);
assign seg1[1]=(A1&~B1&C1)|(A1&B1&~C1);
assign seg1[2]=(~A1&B1&~C1);
assign seg1[3]=(A1&~B1&~C1)|(~A1&~B1&C1)|(A1&B1&C1);
assign seg1[4]=(C1)|(A1&~B1);
assign seg1[5]=(~A1&B1)|(~A1&C1)|(B1&C1);
assign seg1[6]=(~A1&~B1)|(A1&B1&C1);
assign seg2[0]=(A2&~B2&~C2)|(~A2&~B2&C2);
assign seg2[1]=(A2&~B2&C2)|(A2&B2&~C2);
assign seg2[2]=(~A2&B2&~C2);
assign seg2[3]=(A2&~B2&~C2)|(~A2&~B2&C2)|(A2&B2&C2);
assign seg2[4]=(C2)|(A2&~B2);
assign seg2[5]=(~A2&B2)|(~A2&C2)|(B2&C2);
assign seg2[6]=(~A2&~B2)|(A2&B2&C2);
assign seg3[0]=(A3&~B3&~C3)|(~A3&~B3&C3);
assign seg3[1]=(A3&~B3&C3)|(A3&B3&~C3);
assign seg3[2]=(~A3&B3&~C3);
assign seg3[3]=(A3&~B3&~C3)|(~A3&~B3&C3)|(A3&B3&C3);
assign seg3[4]=(C3)|(A3&~B3);
assign seg3[5]=(~A3&B3)|(~A3&C3)|(B3&C3);
assign seg3[6]=(~A3&~B3)|(A3&B3&C3);
//=======================================
endmodule
| 6.986735 |
module SSDTranslation
/*** IN/OUT ***/
(
// IN
input [7 : 0] Value,
// OUT
output [6 : 0] Result
);
reg [6 : 0] SegValue;
always @(Value) begin
case (Value)
0: SegValue <= 7'b1000000;
1: SegValue <= 7'b1111001;
2: SegValue <= 7'b0100100;
3: SegValue <= 7'b0110000;
4: SegValue <= 7'b0011001;
5: SegValue <= 7'b0010010;
6: SegValue <= 7'b0000010;
7: SegValue <= 7'b1111000;
8: SegValue <= 7'b0000000;
9: SegValue <= 7'b0011000;
default SegValue <= 7'b1000000;
endcase
end
assign Result = SegValue;
endmodule
| 8.128128 |
module ssd_dis (
input CLK,
input RST,
input [9:0] DIN,
output reg [3:0] sel,
output reg [6:0] segs
);
//generate 2kHZ scanning clock
parameter cnt_max = 49999;
reg [15:0] cnt;
reg clk_scan;
always @(posedge CLK) begin
if (cnt == cnt_max) cnt <= 16'b0;
else cnt <= cnt + 1'b1;
end
always @(posedge CLK) begin
if (cnt == cnt_max) clk_scan <= 1'b1;
else clk_scan <= 1'b0;
end
//convert binary to bcd
wire [15:0] BCDdata;
Binary_to_BCD BtoBCD (
.CLK(CLK),
.RST(RST),
.START(clk_scan),
.BIN(DIN),
.BCDOUT(BCDdata)
);
//display
reg [3:0] dis_data;
reg [1:0] dis_sel;
always @(posedge clk_scan) begin
if (RST) dis_sel <= 0;
else if (dis_sel == 2'b11) dis_sel <= 2'b0;
else dis_sel <= dis_sel + 1'b1;
end
always @(posedge clk_scan) begin
if (RST) sel <= 4'b0000;
else begin
case (dis_sel)
2'b00: sel <= 4'b1110;
2'b01: sel <= 4'b1101;
2'b10: sel <= 4'b1011;
2'b11: sel <= 4'b0111;
default: sel <= 4'b1111;
endcase
end
end
always @(posedge clk_scan) begin
if (RST) dis_data <= 4'b0;
else begin
case (dis_sel)
2'b00: dis_data <= BCDdata[3:0];
2'b01: dis_data <= BCDdata[7:4];
2'b10: dis_data <= BCDdata[11:8];
2'b11: dis_data <= BCDdata[15:12];
default: dis_data <= 4'b0;
endcase
end
end
always @(*) begin
case (dis_data)
4'h0: segs <= 7'b1000000; // 0
4'h1: segs <= 7'b1111001; // 1
4'h2: segs <= 7'b0100100; // 2
4'h3: segs <= 7'b0110000; // 3
4'h4: segs <= 7'b0011001; // 4
4'h5: segs <= 7'b0010010; // 5
4'h6: segs <= 7'b0000010; // 6
4'h7: segs <= 7'b1111000; // 7
4'h8: segs <= 7'b0000000; // 8
4'h9: segs <= 7'b0010000; // 9
default: segs <= 7'b1000000;
endcase
end
endmodule
| 7.030548 |
module ssd_driver (
in_bcd,
out_ssd
);
input [3:0] in_bcd; // input in BCD
output [6:0] out_ssd; // output to Seven-Segment Display
reg [6:0] out_ssd;
always @(in_bcd) begin
case (in_bcd)
0: out_ssd = 7'b0000001;
1: out_ssd = 7'b1001111;
2: out_ssd = 7'b0010010;
3: out_ssd = 7'b0000110;
4: out_ssd = 7'b1001100;
5: out_ssd = 7'b0100100;
6: out_ssd = 7'b0100000;
7: out_ssd = 7'b0001111;
8: out_ssd = 7'b0000000;
9: out_ssd = 7'b0000100;
10: out_ssd = 7'b0001000;
11: out_ssd = 7'b1100000;
12: out_ssd = 7'b0110001;
13: out_ssd = 7'b1000010;
14: out_ssd = 7'b0110000;
15: out_ssd = 7'b0111000;
default out_ssd = 7'b1111111; // no ssd
endcase
end
endmodule
| 7.53888 |
module ssd_freq_div (
input clock_in,
output reg clock_out
);
parameter width = 32;
reg [width-1:0] count;
initial begin
count = 0;
clock_out = 0;
end
always @(posedge clock_in) begin
if (count == 50000000) begin
count <= 0;
clock_out = ~clock_out;
end else count <= count + 1;
end
endmodule
| 6.592768 |
module ssd_gen (
input [31:0] SW,
input clk,
input rst,
output reg [6:0] a_to_g,
output reg [7:0] an,
output wire dp
);
assign dp = `dp_off;
wire [ 2:0] s;
wire [ 7:0] aen;
reg [19:0] clkdiv;
reg [ 3:0] digit;
assign s = clkdiv[19:17];
assign aen = `initial_digit;
// clock divider
always @(posedge clk or posedge rst) begin
if (rst) clkdiv <= 0;
else clkdiv <= clkdiv + 1;
end
// digit select :ancode
always @(aen, s) begin
an = 8'b11111111;
if (aen[s] == 1) an[s] = 0;
end
// 4-to-1 Mux: mux4x1
always @(s, SW) begin
case (s)
0: digit = SW[3 : 0];
1: digit = SW[7 : 4];
2: digit = SW[11:8];
3: digit = SW[15:12];
4: digit = SW[19:16];
5: digit = SW[23:20];
6: digit = SW[27:24];
7: digit = SW[31:28];
default: digit = 4'bZZZZ;
endcase
end
// 7-segement decoder : hex7seg
always @(digit) begin
case (digit)
0: a_to_g = 7'b0000001;
1: a_to_g = 7'b1001111;
2: a_to_g = 7'b0010010;
3: a_to_g = 7'b0000110;
4: a_to_g = 7'b1001100;
5: a_to_g = 7'b0100100;
6: a_to_g = 7'b0100000;
7: a_to_g = 7'b0001111;
8: a_to_g = 7'b0000000;
9: a_to_g = 7'b0000100;
'hA: a_to_g = 7'b0001000;
'hB: a_to_g = 7'b1100000;
'hC: a_to_g = 7'b0110001;
'hD: a_to_g = 7'b1000010;
'hE: a_to_g = 7'b0110000;
'hF: a_to_g = 7'b0111000;
default: a_to_g = 7'bZZZZZZZ;
endcase
end
endmodule
| 7.699001 |
module ssd_letters (
input wire clk,
//input wire player_place, and player fire
input wire p1fire,
input wire p2fire,
input wire p1place,
input wire p2place,
output wire [7:0] cathode,
output wire [7:0] anode
);
wire [2:0] refreshcounter;
wire refreshclock;
clk_div #(49999) refreshclock_generator (
.clk(clk),
.slow_clk(refreshclock)
);
refreshcounter ref_cou (
.refresh_clock (refreshclock),
.refreshcounter(refreshcounter)
);
anode_control ano (
.refreshcounter(refreshcounter),
.anode(anode)
);
cathode_turn cat (
.refreshcounter(refreshcounter),
.p1fire(p1fire),
.p2fire(p2fire),
.p1place(p1place),
.p2place(p2place),
.cathode(cathode)
);
endmodule
| 7.349804 |
module SSD_0 (
in,
out
);
input [3:0] in;
output [6:0] out;
reg [6:0] out;
always @(in) begin
case (in)
4'b0000: out <= 7'b0000001;
4'b0001: out <= 7'b1001111;
4'b0010: out <= 7'b0010010;
4'b0011: out <= 7'b0000110;
4'b0100: out <= 7'b1001100;
4'b0101: out <= 7'b0100100;
4'b0110: out <= 7'b0100000;
4'b0111: out <= 7'b0001111;
4'b1000: out <= 7'b0000000;
4'b1001: out <= 7'b0000100;
4'b1111: out <= 7'b1111111;
4'b1110: out <= 7'b1111110;
endcase
end
endmodule
| 6.689118 |
module Segments_tb ();
reg [3:0] BCD;
wire [6:0] SEG;
//BCD = 0;
BCD7Segments SEG1 (
BCD,
SEG
);
initial begin
$display("BCD\tSEG");
$monitor("%b %b", BCD, SEG);
BCD = 0;
#10 BCD = 1;
#10 BCD = 2;
#10 BCD = 3;
#10 BCD = 4;
#10 BCD = 5;
#10 BCD = 6;
#10 BCD = 7;
#10 BCD = 8;
#10 BCD = 9;
#10 BCD = 10;
#10 BCD = 11;
#10 BCD = 12;
#10 BCD = 13;
#10 BCD = 14;
#10 BCD = 15;
#20 $finish;
end
endmodule
| 6.607117 |
module SSD_Top (
input [3:0] switch,
output [6:0] led,
output [7:0] anode, //which ssd out of 8 will be used
output dp
);
assign anode = 8'b11111110; //only first ssd will be enable
assign dp = 1;
ssd D1 (
.x(switch),
.a_to_g(led)
);
endmodule
| 6.608239 |
module ssdController4 #(
parameter CLOCK_PERIOD = 10
) (
clk,
rst,
mode,
digit3,
digit2,
digit1,
digit0,
seg,
an
);
localparam TARGET_PERIOD = 655360; //655.36µs or ~1.526 kHz
localparam DIVISION_COUNT = $clog2(TARGET_PERIOD / CLOCK_PERIOD) - 1;
input clk, rst;
input [3:0] mode; //each bit represents enableing correspond ssd
//e.g. mode=0001 means only least significant digit (rightmost, digit0) is going to be enabled
input [3:0] digit0, digit1, digit2, digit3;
output [6:0] seg;
wire a, b, c, d, e, f, g;
output reg [3:0] an;
reg [1:0] state; //shows a diffrent digit every state
wire stateClk; //state changes every edge of stateClk
reg [DIVISION_COUNT:0] counter; //655.36µs or ~1.526 kHz
//Some signals for better readability
wire [3:0] encode_in;
wire [6:0] abcdefg;
reg [3:0] digit[3:0];
assign seg = {g, f, e, d, c, b, a};
assign stateClk = counter[DIVISION_COUNT]; //state clock determined by MSB of counter
//both state and counter will warp 11.. to 00.. at max
always@(posedge stateClk or posedge rst) //state transactions
begin
if (rst) state <= 2'b0;
else state <= state + 2'b1;
end
always@(posedge clk or posedge rst) //counter
begin
if (rst) counter <= {(DIVISION_COUNT + 1) {1'b0}};
else counter <= counter + {{DIVISION_COUNT{1'b0}}, 1'b1};
end
always@* //anode control
begin
case (state)
2'd0: an = 4'b1110;
2'd1: an = 4'b1101;
2'd2: an = 4'b1011;
2'd3: an = 4'b0111;
endcase
end
always@* //collect digits in one block
begin
digit[0] = digit0;
digit[1] = digit1;
digit[2] = digit2;
digit[3] = digit3;
end
assign {a, b, c, d, e, f, g} = (mode[state]) ? abcdefg : 7'b1111111;
assign encode_in = digit[state];
ssd_encode encoder (
encode_in,
abcdefg
);
endmodule
| 7.160001 |
module ssdController2 #(
parameter CLOCK_PERIOD = 10
) (
clk,
rst,
mode,
digit1,
digit0,
seg,
an
);
localparam TARGET_PERIOD = 655360; //655.36µs or ~1.526 kHz
localparam DIVISION_COUNT = $clog2(TARGET_PERIOD / CLOCK_PERIOD) - 1;
input clk, rst;
input [1:0] mode; //each bit represents enableing correspond ssd
//e.g. mode=01 means only least significant digit (rightmost, digit0) is going to be enabled
input [3:0] digit0, digit1;
wire a, b, c, d, e, f, g;
output reg [1:0] an;
output [6:0] seg;
reg state; //shows a diffrent digit every state
wire stateClk; //state changes every edge of stateClk
reg [15:0] counter; //655.36µs or ~1.526 kHz
//Some signals for better readability
wire [3:0] encode_in;
wire [6:0] abcdefg;
reg [3:0] digit[1:0];
assign seg = {g, f, e, d, c, b, a};
assign stateClk = counter[DIVISION_COUNT]; //state clock determined by MSB of counter
always@(posedge stateClk or posedge rst) //state transactions
begin
if (rst) state <= 1'b0;
else state <= ~state;
end
always@(posedge clk or posedge rst) //counter
begin
if (rst) counter <= {(DIVISION_COUNT + 1) {1'b0}};
else counter <= counter + {{DIVISION_COUNT{1'b0}}, 1'b1};
end
always@* //anode control
begin
case (state)
1'b0: an = 4'b10;
1'b1: an = 2'b01;
endcase
end
always@* //collect digits in one block
begin
digit[0] = digit0;
digit[1] = digit1;
end
assign {a, b, c, d, e, f, g} = (mode[state]) ? abcdefg : 7'b1111111;
assign encode_in = digit[state];
ssd_encode encoder (
encode_in,
abcdefg
);
endmodule
| 7.160001 |
module ssd_encode (
in,
abcdefg
);
parameter zero = 7'b0000001, one = 7'b1001111, two = 7'b0010010;
parameter thr = 7'b0000110, four = 7'b1001100, five = 7'b0100100;
parameter six = 7'b0100000, svn = 7'b0001111, eght = 7'b0000000;
parameter nine = 7'b0000100, A = 7'b0001000, B = 7'b1100000;
parameter C = 7'b0110001, D = 7'b1000010, E = 7'b0110000, F = 7'b0111000;
input [3:0] in;
output reg [6:0] abcdefg;
always @* begin
case (in)
4'b0: abcdefg = zero;
4'b1: abcdefg = one;
4'b10: abcdefg = two;
4'b11: abcdefg = thr;
4'b100: abcdefg = four;
4'b101: abcdefg = five;
4'b110: abcdefg = six;
4'b111: abcdefg = svn;
4'b1000: abcdefg = eght;
4'b1001: abcdefg = nine;
4'b1010: abcdefg = A;
4'b1011: abcdefg = B;
4'b1100: abcdefg = C;
4'b1101: abcdefg = D;
4'b1110: abcdefg = E;
4'b1111: abcdefg = F;
endcase
end
endmodule
| 6.711742 |
module sseg #(
parameter X = 0,
parameter Y = 0,
parameter W = 100,
parameter H = 200
) (
input wire [7:0] bcd,
input wire [9:0] x,
input wire [9:0] y,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b
);
parameter VLD = (W / 4); //vertical line depth |
parameter HLD = (H / 7); //horisontal line depth --
parameter MID = (H / 2); //MID line
parameter hVLD = (VLD / 2); //vertical line depth /2
parameter hHLD = (HLD / 2); //horisontal line depth /2
wire A, B, C, D, E, F, G, DP;
assign {DP, G, F, E, D, C, B, A} = bcd;
wor [2:0] line;
assign r = 3'b000;
assign g = line;
assign b = 3'b000;
wire [2:0] line_A = ( ( x >= ( X )) &&
( x <= ( X + W ) )&&
( y >= ( Y ) ) &&
( y <= ( Y + HLD ) ) &&
( A ) ) ? 3'b111: 3'b000;
wire [2:0] line_D = ( ( x >= ( X )) &&
( x <= ( X + W ) )&&
( y >= ( Y + H - HLD) ) &&
( y <= ( Y + H ) ) &&
( D ) ) ? 3'b111: 3'b000;
wire [2:0] line_G = ( ( x >= ( X ) ) &&
( x <= ( X + W ) )&&
( y >= ( Y + MID - hVLD ) ) &&
( y <= ( Y + MID + hVLD ) ) &&
( G ) ) ? 3'b111: 3'b000;
wire [2:0] line_F = ( ( x >= ( X ) ) &&
( x <= ( X + VLD ) )&&
( y >= ( Y ) ) &&
( y <= ( Y + MID + hVLD ) ) &&
( F ) ) ? 3'b111: 3'b000;
wire [2:0] line_E = ( ( x >= ( X ) ) &&
( x <= ( X + VLD ) )&&
( y >= ( Y + MID - hVLD ) ) &&
( y <= ( Y + H ) ) &&
( E ) ) ? 3'b111: 3'b000;
wire [2:0] line_B = ( ( x >= ( X + W - VLD ) ) &&
( x <= ( X + W ) )&&
( y >= ( Y ) ) &&
( y <= ( Y + MID + hVLD ) ) &&
( B ) ) ? 3'b111: 3'b000;
wire [2:0] line_C = ( ( x >= ( X + W - VLD ) ) &&
( x <= ( X + W ) )&&
( y >= ( Y + MID - hVLD ) ) &&
( y <= ( Y + H ) ) &&
( C ) ) ? 3'b111: 3'b000;
wire [2:0] line_DP = ( ( x >= ( X + W + hHLD ) ) &&
( x <= ( X + W + hHLD + HLD ) )&&
( y >= ( Y + H - VLD ) ) &&
( y <= ( Y + H ) ) &&
( DP ) ) ? 3'b111: 3'b000;
assign line = line_A;
assign line = line_D;
assign line = line_G;
assign line = line_F;
assign line = line_E;
assign line = line_B;
assign line = line_C;
assign line = line_DP;
assign line = 3'b000;
endmodule
| 6.650912 |
module ssegment (
input clk,
rst,
input [3:0] hited,
input [3:0] hit,
output reg [7:0] SSEG_AN,
SSEG_CA
);
parameter FIRST = 8'b1111_1110, THIRD = 8'b1111_1011;
parameter LIFE = 4'd3;
reg [31:0] count2;
reg a;
reg [3:0] score, life;
wire [7:0] w1, w3;
initial begin
score = 4'b0;
life = LIFE;
count2 = 4'b0;
a = 1'b0;
end
always @(posedge clk)//Ƶ
begin
count2 = count2 + 1;
if (count2 == 1) a = ~a;
else if (count2 == 32'h0001ffff) count2 = 0;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
score <= 4'b0;
life <= LIFE;
end else begin
score <= hit;
life <= LIFE - hited;
end
end
always @(posedge clk) begin
if (a) begin
SSEG_AN <= FIRST;
SSEG_CA <= w1;
end else begin
SSEG_AN <= THIRD;
SSEG_CA <= w3;
end
end
ROM_ssegment R0 (
score,
w1
);
ROM_ssegment R1 (
life,
w3
);
endmodule
| 7.056711 |
module sseg_decode #(
parameter REG = 0, // register outputs
parameter INV = 1 // invert outputs
) (
input wire clk,
input wire rst,
input wire [4-1:0] num, // input
output wire [7-1:0] sseg // output
);
reg [7-1:0] sseg_decode;
always @(*) begin
case (num)
4'h0: sseg_decode = 7'b0111111;
4'h1: sseg_decode = 7'b0000110;
4'h2: sseg_decode = 7'b1011011;
4'h3: sseg_decode = 7'b1001111;
4'h4: sseg_decode = 7'b1100110;
4'h5: sseg_decode = 7'b1101101;
4'h6: sseg_decode = 7'b1111101;
4'h7: sseg_decode = 7'b0000111;
4'h8: sseg_decode = 7'b1111111;
4'h9: sseg_decode = 7'b1101111;
4'ha: sseg_decode = 7'b1110111;
4'hb: sseg_decode = 7'b1111100;
4'hc: sseg_decode = 7'b0111001;
4'hd: sseg_decode = 7'b1011110;
4'he: sseg_decode = 7'b1111001;
4'hf: sseg_decode = 7'b1110001;
default: sseg_decode = 7'b0000000;
endcase
end
generate
if (REG == 1) begin
reg [7-1:0] sseg_reg;
always @(posedge clk, posedge rst) begin
if (rst) sseg_reg <= #1 7'h0;
else sseg_reg <= #1 INV ? ~sseg_decode : sseg_decode;
end
assign sseg = sseg_reg;
end else begin
assign sseg = INV ? ~sseg_decode : sseg_decode;
end
endgenerate
endmodule
| 6.855334 |
module SSEG_Display (
clk_50M,
reset,
sseg_a_to_dp,
sseg_an,
data
);
input wire clk_50M; // 50MHz clock input
input wire reset; // 8-bit DIP switch
output wire [7:0] sseg_a_to_dp; // cathode of seven segment display( a,b,c,d,e,f,g,dp )
output wire [3:0] sseg_an; // anaode of seven segment display( AN3,AN2,AN1,AN0 )
input wire [15:0] data; // display "1234" on sseg led
SSEG_Driver U1 (
.clk_50M(clk_50M),
.reset(reset),
.data(data),
.sseg(sseg_a_to_dp),
.an(sseg_an),
.dp_in(4'b1111), // turn off all decimal points
);
endmodule
| 7.886854 |
module: sseg_display
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sseg_display_tb;
// Inputs
reg clk;
reg reset;
reg [3:0] hexa3;
reg [3:0] hexa2;
reg [3:0] hexa1;
reg [3:0] hexa0;
reg [3:0] dps;
// Outputs
wire [3:0] selec_disp;
wire [7:0] sseg;
// Instantiate the Unit Under Test (UUT)
sseg_display uut (
.clk(clk),
.reset(reset),
.hexa3(hexa3),
.hexa2(hexa2),
.hexa1(hexa1),
.hexa0(hexa0),
.dps(dps),
.selec_disp(selec_disp),
.sseg(sseg)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
hexa3 = 4'h0;
hexa2 = 4'h0;
hexa1 = 4'h0;
hexa0 = 4'h0;
dps = 4'h0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever #50 clk=~clk;
end
initial begin
#100
reset = 0;
hexa3 = 4'h1;
hexa2 = 4'h2;
hexa1 = 4'h3;
hexa0 = 4'h4;
dps = 4'hf;
#300
$stop;
end
endmodule
| 6.912911 |
module: sseg_display
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sseg_display_test;
// Inputs
reg rst;
reg clk;
reg [7:0] value;
// Outputs
wire [3:0] sseg_an;
wire [7:0] sseg_sig;
// Instantiate the Unit Under Test (UUT)
sseg_display uut (
.rst(rst),
.clk(clk),
.value(value),
.sseg_an(sseg_an),
.sseg_sig(sseg_sig)
);
initial begin
// Initialize Inputs
rst = 1;
clk = 0;
value = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
forever
begin
clk = !clk;
#10;
end
end
always begin
#100;
value = value + 1;
end
endmodule
| 6.912911 |
module sseg_driver (
input wire [3 : 0] digit, /* digit to show */
input wire [1 : 0] sel, /* place to show */
output reg [3 : 0] anode, /* common anode enable */
output reg [6 : 0] cathode /* cathode enable */
);
/* decode anode enable signal */
always @(sel) begin
case (sel)
2'b00: anode = 4'b1110;
2'b01: anode = 4'b1101;
2'b10: anode = 4'b1011;
2'b11: anode = 4'b0111;
endcase
end
/* decode digit into 7-segment driver output */
always @(digit) begin
case (digit) /* ABCDEFG */
4'h0: cathode = 7'b0000001;
4'h1: cathode = 7'b1001111;
4'h2: cathode = 7'b0010010;
4'h3: cathode = 7'b0000110;
4'h4: cathode = 7'b1001100;
4'h5: cathode = 7'b0100100;
4'h6: cathode = 7'b0100000;
4'h7: cathode = 7'b0001111;
4'h8: cathode = 7'b0000000;
4'h9: cathode = 7'b0000100;
4'ha: cathode = 7'b0001000;
4'hb: cathode = 7'b1100000;
4'hc: cathode = 7'b0110001;
4'hd: cathode = 7'b1000010;
4'he: cathode = 7'b0110000;
4'hf: cathode = 7'b0111000;
endcase
end
endmodule
| 7.535657 |
module sseg_sweeper (
input wire CLOCK_SWEEP,
input wire [19:0] GPIO_IN,
output reg [5:0] SEL,
output wire [6:0] HEX
);
integer CASE;
reg [3:0] BIN;
wire [7:0] PARA;
always @(posedge CLOCK_SWEEP) begin
case (CASE)
0: begin
SEL <= 6'b111110;
BIN[3:0] <= GPIO_IN[3:0];
CASE <= CASE + 1;
end
1: begin
SEL <= 6'b111101;
BIN[3:0] <= GPIO_IN[7:4];
CASE <= CASE + 1;
end
2: begin
SEL <= 6'b111011;
BIN[3:0] <= GPIO_IN[11:8];
CASE <= CASE + 1;
end
3: begin
SEL <= 6'b110111;
BIN[3:0] <= GPIO_IN[15:12];
CASE <= CASE + 1;
end
4: begin
SEL <= 6'b101111;
BIN[3:0] <= PARA[3:0];
CASE <= CASE + 1;
end
5: begin
SEL <= 6'b011111;
BIN[3:0] <= PARA[7:4];
CASE <= 0;
end
endcase
end
bin_to_sseg(
.BIN(BIN), .HEX(HEX)
); para_decoder(
.PARA_IN(GPIO_IN[19:16]), .PARA_OUT(PARA)
);
// para_to_sseg (
endmodule
| 6.772916 |
module sseg_x4_top (
input [15:0] sw,
input clk,
input rst,
output [0:6] seg,
output [3:0] an,
output dp
);
wire [3:0] not_used; // Place holder individual anodes which are handled by digit_selector
wire clkd; // 200 Hz Clock
wire [0:3] hex_num; // Can't be called sw any more so I'll call it
// Get the clock frequency divided down by the clock generator (200Hz)
clk_gen U1 (
.clk(clk),
.rst(rst),
.clk_div(clkd)
);
// Display one character at a time
digit_selector U2 (
.clk(clkd),
.rst(rst),
.digit_sel(an)
);
// Assign the correct hexadecimal number to the correct digit
hex_num_gen U3 (
.digit_sel(an),
.sw(sw),
.hex_num(hex_num)
);
// Handle hardware for display
sseg U4 (
.seg(seg),
.an (not_used),
.dp (dp),
.sw (hex_num)
);
endmodule
| 7.829466 |
module ssg_emb_dc_ballast_dec128 (
input clk, // ADC clock
input reset_n, // syetm reset
input cnr128, // Decimator pulse
input dec_rate, // Decimation rate control register bit 1: M=64, 0: M=128
input [15:0] offset, // zero offset register
input [21:0] cn_in, // Input from integrator
output reg [15:0] sample // Output sample
);
reg [18:0] dn0, dn1, dn3, dn5;
reg [19:0] sample_x;
wire [18:0] cn3, cn4, cn5;
always @(posedge clk or negedge reset_n)
if (~reset_n) begin
dn0 <= 19'b0;
dn1 <= 19'b0;
dn3 <= 19'b0;
dn5 <= 19'b0;
sample_x <= 20'b0;
end else if (cnr128) begin
dn0 <= dec_rate ? cn_in[18:0] : cn_in[21:3];
dn1 <= dn0;
dn3 <= cn3;
dn5 <= cn4;
end else sample_x <= {cn5[18], cn5} - {offset[15], offset, 3'b000};
assign cn3 = dn0 - dn1;
assign cn4 = cn3 - dn3;
assign cn5 = cn4 - dn5;
always @(posedge clk or negedge reset_n)
if (~reset_n) sample <= 16'b0;
else if (sample_x[19:18] == 2'b00) sample <= sample_x[18:3];
else if (sample_x[18] == 1'b0) // Limit to +ve full scale
sample <= 16'h7FFF;
else if (sample_x[18] == 1'b1) // Limit to 0
sample <= 16'h0000;
endmodule
| 6.798838 |
module ssg_emb_dc_ballast_diff (
input clk_adc, // ADC clock
input reset_n, // System reset
input data, // ADC data in clk_adc domain
input dec_rate, // Decimation rate control register bit in clk_adc domain 1: M=64 or 8, 0: M=128 or 16
// All outputs in clk_adc domain
output reg [21:0] cn_out, // Third stage integrator output
output reg cnr128 // Decimator pulse for highres conversion
);
reg [21:0] delta1, cn1, cn2;
always @(posedge clk_adc or negedge reset_n)
if (~reset_n) delta1 <= 22'b0;
else if (data) delta1 <= delta1 + 22'b1;
always @(posedge clk_adc or negedge reset_n)
if (~reset_n) begin
cn1 <= 22'b0;
cn2 <= 22'b0;
cn_out <= 22'b0;
end else begin
cn1 <= cn1 + delta1;
cn2 <= cn2 + cn1;
cn_out <= cn2;
end
// Generate sample strobes for high resolution decimator and output result latch
reg [8:0] counter;
always @(posedge clk_adc or negedge reset_n)
if (~reset_n) counter <= 9'b0;
else counter <= counter + 9'b1;
// Generate pulses to tell high resolution decimator when to take a sample
// Use start_adc to force first result to be used
always @(posedge clk_adc or negedge reset_n)
if (~reset_n) cnr128 <= 1'b0;
else begin
if (dec_rate)
// for high res converter M = 64
cnr128 <= (counter[5:0] == 6'b111111);
else
// for high res converter M = 128
cnr128 <= (counter[6:0] == 7'b1111111);
end
endmodule
| 6.798838 |
module ssg_emb_sd_adc_dec128 (
input clk, // ADC clock
input reset_n, // syetm reset
input cnr128, // Decimator pulse
input dec_rate, // Decimation rate control register bit 1: M=64, 0: M=128
input [15:0] offset, // zero offset register
input [21:0] cn_in, // Input from integrator
output reg [15:0] sample // Output sample
);
reg [18:0] dn0, dn1, dn3, dn5, sample_x;
wire [18:0] cn3, cn4, cn5;
always @(posedge clk or negedge reset_n)
if (~reset_n) begin
dn0 <= 19'b0;
dn1 <= 19'b0;
dn3 <= 19'b0;
dn5 <= 19'b0;
sample_x <= 19'b0;
end else if (cnr128) begin
dn0 <= dec_rate ? cn_in[18:0] : cn_in[21:3];
dn1 <= dn0;
dn3 <= cn3;
dn5 <= cn4;
end else sample_x <= cn5 - {1'b0, offset, 2'b11};
assign cn3 = dn0 - dn1;
assign cn4 = cn3 - dn3;
assign cn5 = cn4 - dn5;
always @(posedge clk or negedge reset_n)
if (~reset_n) sample <= 16'b0;
else if ((sample_x[18:17] == 2'b00) || (sample_x[18:17] == 2'b11)) sample <= sample_x[17:2];
else if (sample_x[18] == 1'b0) // Limit to +ve full scale
sample <= 16'h7FFF;
else if (sample_x[18] == 1'b1) // Limit to -ve full scale
sample <= 16'h8001;
endmodule
| 6.950756 |
module ssg_emb_sd_adc_dec16 (
input clk, // ADC clock
input reset_n, // syetm reset
input cnr16, // Decimator pulse
input dec_rate, // Decimation rate control register bit 1: M=8, 0: M=16
input [21:0] cn_in, // Input from integrator
output reg [9:0] sample // Output sample
);
reg [9:0] dn0, dn1, dn3, dn5, sample_x;
wire [9:0] cn3, cn4, cn5;
always @(posedge clk or negedge reset_n)
if (~reset_n) begin
dn0 <= 10'b0;
dn1 <= 10'b0;
dn3 <= 10'b0;
dn5 <= 10'b0;
sample_x <= 10'b0;
end else if (cnr16) begin
dn0 <= dec_rate ? cn_in[9:0] : cn_in[12:3];
dn1 <= dn0;
dn3 <= cn3;
dn5 <= cn4;
end else sample_x <= cn5 - 10'b0011111111;
assign cn3 = dn0 - dn1;
assign cn4 = cn3 - dn3;
assign cn5 = cn4 - dn5;
always @(posedge clk or negedge reset_n)
if (~reset_n) sample <= 10'b0;
else sample <= sample_x;
endmodule
| 6.950756 |
module ssg_emb_sd_adc_diff (
input clk, // System clock
input clk_adc, // ADC clock
input reset_n, // System reset
input data, // ADC data in clk_adc domain
input start, // Start conversion pulse in system clk domain
input dec_rate, // Decimation rate control register bit in clk_adc domain 1: M=64 or 8, 0: M=128 or 16
// All outputs in clk_adc domain
output wire [21:0] cn_out, // Third stage integrator output
output reg cnr16, // Decimator pulse for low res conversion
output reg cnr128, // Decimator pulse for highres conversion
output wire latch_en // Output sample latch enable
);
reg [21:0] delta1, cn1, cn2;
always @(posedge clk_adc or negedge reset_n)
if (~reset_n) delta1 <= 22'b0;
else if (data) delta1 <= delta1 + 22'b1;
always @(posedge clk_adc or negedge reset_n)
if (~reset_n) begin
cn1 <= 22'b0;
cn2 <= 22'b0;
end else begin
cn1 <= cn1 + delta1;
cn2 <= cn2 + cn1;
end
assign cn_out = cn2;
// Synchronise start pulse to clk_adc by strecthing it and handshaking between
// the clock domains
reg start_r;
reg start_adc_sync;
reg start_adc_sync2;
reg start_sync_adc;
reg start_sync2_adc;
wire start_adc;
always @(posedge clk or negedge reset_n)
if (~reset_n) begin
start_r <= 1'b0;
start_adc_sync <= 1'b0;
start_adc_sync2 <= 1'b0;
end else begin
if (start) start_r <= 1'b1;
else if (start_adc_sync2) start_r <= 1'b0;
start_adc_sync <= start_sync2_adc;
start_adc_sync2 <= start_adc_sync;
end
always @(posedge clk_adc or negedge reset_n)
if (~reset_n) begin
start_sync_adc <= 1'b0;
start_sync2_adc <= 1'b0;
end else begin
start_sync_adc <= start_r;
start_sync2_adc <= start_sync_adc;
end
assign start_adc = ~start_sync2_adc & start_sync_adc;
// Generate sample strobes for high resolution decimator and output result latch
reg [8:0] counter;
reg run;
always @(posedge clk_adc or negedge reset_n)
if (~reset_n) begin
counter <= 9'b0;
run <= 1'b0;
end else begin
if (start_adc) run <= 1'b1;
else if (counter == 9'd399) begin
run <= 1'b0;
counter <= 9'b0;
end else if (run) counter <= counter + 9'b1;
end
assign latch_en = run & (counter == 9'd399);
// Generate pulses to tell high resolution decimator when to take a sample
// Use start_adc to force first result to be used
always @(posedge clk_adc or negedge reset_n)
if (~reset_n) cnr128 <= 1'b0;
else begin
if (dec_rate)
// for high res converter M = 64
cnr128 <= run & (counter[5:0] == 6'b111111) | start_adc;
else
// for high res converter M = 128
cnr128 <= run & (counter[6:0] == 7'b1111111) | start_adc;
end
// For low resolution decimator use a free running counter
reg [3:0] counter16;
always @(posedge clk_adc or negedge reset_n)
if (~reset_n) counter16 <= 4'b0;
else counter16 <= counter16 + 4'b1;
always @(posedge clk_adc or negedge reset_n)
if (~reset_n) cnr16 <= 1'b0;
else begin
if (dec_rate)
// for low res converter M = 8
cnr16 <= (counter16[2:0] == 3'b111);
else
// for low res converter M = 16
cnr16 <= (counter16[3:0] == 4'b1111);
end
endmodule
| 6.950756 |
module bit_clock_synchronizer (
rst,
clk,
serial_clock_in,
bit_clock
);
(* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:60" *)
output bit_clock;
wire bit_clock;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
input clk;
wire clk;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
input rst;
wire rst;
(* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:48" *)
input serial_clock_in;
wire serial_clock_in;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
reg stage0 = 1'h0;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
wire \stage0$next ;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
reg stage1 = 1'h0;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
wire \stage1$next ;
always @(posedge clk) stage0 <= \stage0$next ;
always @(posedge clk) stage1 <= \stage1$next ;
assign bit_clock = stage1;
assign \stage1$next = stage0;
assign \stage0$next = serial_clock_in;
endmodule
| 7.69458 |
module frame_clock_synchronizer (
rst,
clk,
frame_start_in,
frame_clock
);
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
input clk;
wire clk;
(* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:61" *)
output frame_clock;
wire frame_clock;
(* src = "/home/kkojima/ad9874iq/ad9874iq/verilog/../ad9874ssi.py:50" *)
input frame_start_in;
wire frame_start_in;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/hdl/ir.py:527" *)
input rst;
wire rst;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
reg stage0 = 1'h0;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
wire \stage0$next ;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
reg stage1 = 1'h0;
(* src = "/home/kkojima/.local/lib/python3.10/site-packages/amaranth/lib/cdc.py:89" *)
wire \stage1$next ;
always @(posedge clk) stage0 <= \stage0$next ;
always @(posedge clk) stage1 <= \stage1$next ;
assign frame_clock = stage1;
assign \stage1$next = stage0;
assign \stage0$next = frame_start_in;
endmodule
| 6.816093 |
module ssio_ddr_out #(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Use 90 degree clock for transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
// Width of register in bits
parameter WIDTH = 1
) (
input wire clk,
input wire clk90,
input wire [WIDTH-1:0] input_d1,
input wire [WIDTH-1:0] input_d2,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
wire ref_clk = USE_CLK90 == "TRUE" ? clk90 : clk;
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(1)
) clk_oddr_inst (
.clk(ref_clk),
.d1 (1'b1),
.d2 (1'b0),
.q (output_clk)
);
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(WIDTH)
) data_oddr_inst (
.clk(clk),
.d1 (input_d1),
.d2 (input_d2),
.q (output_q)
);
endmodule
| 6.621865 |
module ssio_ddr_out_diff #(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Use 90 degree clock for transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE",
// Width of register in bits
parameter WIDTH = 1
) (
input wire clk,
input wire clk90,
input wire [WIDTH-1:0] input_d1,
input wire [WIDTH-1:0] input_d2,
output wire output_clk_p,
output wire output_clk_n,
output wire [WIDTH-1:0] output_q_p,
output wire [WIDTH-1:0] output_q_n
);
wire output_clk;
wire [WIDTH-1:0] output_q;
ssio_ddr_out #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.USE_CLK90(USE_CLK90),
.WIDTH(WIDTH)
) ssio_ddr_out_inst (
.clk(clk),
.clk90(clk90),
.input_d1(input_d1),
.input_d2(input_d2),
.output_clk(output_clk),
.output_q(output_q)
);
genvar n;
generate
if (TARGET == "XILINX") begin
OBUFDS clk_obufds_inst (
.I (output_clk),
.O (output_clk_p),
.OB(output_clk_n)
);
for (n = 0; n < WIDTH; n = n + 1) begin
OBUFDS data_obufds_inst (
.I (output_q[n]),
.O (output_q_p[n]),
.OB(output_q_n[n])
);
end
end else if (TARGET == "ALTERA") begin
ALT_OUTBUF_DIFF clk_outbuf_diff_inst (
.i(output_clk),
.o(output_clk_p),
.obar(output_clk_n)
);
for (n = 0; n < WIDTH; n = n + 1) begin
ALT_OUTBUF_DIFF data_outbuf_diff_inst (
.i(output_q[n]),
.o(output_q_p[n]),
.obar(output_q_n[n])
);
end
end else begin
assign output_clk_p = output_clk;
assign output_clk_n = ~output_clk;
assign output_q_p = output_q;
assign output_q_n = ~output_q;
end
endgenerate
endmodule
| 6.75509 |
module ssio_sdr_out #(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register in bits
parameter WIDTH = 1
) (
input wire clk,
input wire [WIDTH-1:0] input_d,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(1)
) clk_oddr_inst (
.clk(clk),
.d1 (1'b0),
.d2 (1'b1),
.q (output_clk)
);
(* IOB = "TRUE" *)
reg [WIDTH-1:0] output_q_reg = {WIDTH{1'b0}};
assign output_q = output_q_reg;
always @(posedge clk) begin
output_q_reg <= input_d;
end
endmodule
| 7.092957 |
module ssio_sdr_out_diff #(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register in bits
parameter WIDTH = 1
) (
input wire clk,
input wire [WIDTH-1:0] input_d,
output wire output_clk_p,
output wire output_clk_n,
output wire [WIDTH-1:0] output_q_p,
output wire [WIDTH-1:0] output_q_n
);
wire output_clk;
wire [WIDTH-1:0] output_q;
ssio_sdr_out #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(WIDTH)
) ssio_ddr_out_inst (
.clk(clk),
.input_d(input_d),
.output_clk(output_clk),
.output_q(output_q)
);
genvar n;
generate
if (TARGET == "XILINX") begin
OBUFDS clk_obufds_inst (
.I (output_clk),
.O (output_clk_p),
.OB(output_clk_n)
);
for (n = 0; n < WIDTH; n = n + 1) begin
OBUFDS data_obufds_inst (
.I (output_q[n]),
.O (output_q_p[n]),
.OB(output_q_n[n])
);
end
end else if (TARGET == "ALTERA") begin
ALT_OUTBUF_DIFF clk_outbuf_diff_inst (
.i(output_clk),
.o(output_clk_p),
.obar(output_clk_n)
);
for (n = 0; n < WIDTH; n = n + 1) begin
ALT_OUTBUF_DIFF data_outbuf_diff_inst (
.i(output_q[n]),
.o(output_q_p[n]),
.obar(output_q_n[n])
);
end
end else begin
assign output_clk_p = output_clk;
assign output_clk_n = ~output_clk;
assign output_q_p = output_q;
assign output_q_n = ~output_q;
end
endgenerate
endmodule
| 7.06669 |
module OR (
output O,
input I1,
input I2
);
assign O = I1 | I2;
endmodule
| 7.937706 |
module NOT (
output O,
input I
);
assign O = ~I;
endmodule
| 7.920372 |
module NAND (
output reg O,
input I1,
input I2
);
always @(*) begin
O = ~(I1 & I2);
end
endmodule
| 7.659562 |
module NOR (
output reg O,
input I1,
input I2
);
always @(*) begin
O = ~(I1 | I2);
end
endmodule
| 7.918619 |
module EXOR (
output O,
input I1,
input I2
);
LUT2 #(
.INIT(4'b0110)
) lut (
.O (O),
.I1(I1),
.I0(I2)
);
endmodule
| 7.264641 |
module EXNOR (
output O,
input I1,
input I2
);
LUT2 #(
.INIT(4'b1001)
) lut (
.O (O),
.I1(I1),
.I0(I2)
);
endmodule
| 7.07346 |
module TRI (
output O,
input I,
input E
);
assign O = E ? I : 1'bz;
endmodule
| 7.03312 |
module TOP (
output O_or,
output O_not,
output O_nand,
output O_nor,
output O_exor,
output O_exnor,
output O_tri,
input I1,
input I2
);
OR or_gate (
O_or,
I1,
I2
);
NOT not_gate (
O_not,
I1
);
NAND nand_gate (
O_nand,
I1,
I2
);
NOR nor_gate (
O_nor,
I1,
I2
);
EXOR exor_gate (
O_exor,
I1,
I2
);
EXNOR exnor_gate (
O_exnor,
I1,
I2
);
TRI tri_gate (
O_tri,
I1,
I2
);
endmodule
| 8.04928 |
module contains the top level design that will be implemented
* the FPGA board.
*/
`timescale 1ns/100ps
module ssl(eclk, erst, din, dIdA, dIdB, dIdC, dSsA);//, dSsB, dSsC);
/* Parameter declaration */
parameter RSTSIZE = 4;
parameter ENASIZE = 2;
parameter DIV = 50;
parameter NDATA = 128;
parameter NDATA_LOG = $clog2(NDATA);
/* Input/output declaration */
input eclk;
input erst;
input [3:0] din;
output [NDATA_LOG-1:0] dIdA;
output [NDATA_LOG-1:0] dIdB;
output [NDATA_LOG-1:0] dIdC;
output [20:0] dSsA;
//output [20:0] dSsB;
//output [20:0] dSsC;
/* Global control wire declaration */
wire frst;
wire fena;
wire clk;
wire rst;
wire ena;
wire [NDATA_LOG-1:0] cntin;
wire [NDATA-1:0] dinRef;
wire [NDATA-1:0] dinSigA;
wire [NDATA-1:0] dinSigB;
wire [NDATA-1:0] dinSigC;
/* Module declaration */
// Master reset synchronizer module
rst_synch #(RSTSIZE, ENASIZE) rstSynchInstA (
.clk (eclk),
.erst (erst),
.rst (frst),
.ena (fena)
);
// Clock division module
clkdiv #(DIV) clkdivInst (
.clk (eclk),
.rst(frst),
.ena(fena),
.clkout (clk)
);
// Slow clock synchronizer module
rst_synch #(RSTSIZE, ENASIZE) rstSynchInstB (
.clk (clk),
.erst (frst),
.rst (rst),
.ena (ena)
);
// Master counter module
counter #(NDATA) counterInst (
.clk (clk),
.rst (rst),
.ena (ena),
.dout (cntin)
);
// Input buffer module
input_buff #(NDATA) inputBuffInst (
.din (din),
.cntin (cntin),
.clk (clk),
.rst (rst),
.ena (ena),
.doutRef (dinRef),
.doutSigA (dinSigA),
.doutSigB (dinSigB),
.doutSigC (dinSigC)
);
// Processor array module
proc_array #(NDATA) procArrayA (
.dinRef (dinRef),
.dinSig (dinSigA),
.clk (clk),
.rst (rst),
.ena (ena),
.cntin (cntin),
.dout (dIdA)
);
proc_array #(NDATA) procArrayB (
.dinRef (dinRef),
.dinSig (dinSigB),
.clk (clk),
.rst (rst),
.ena (ena),
.cntin (cntin),
.dout (dIdB)
);
proc_array #(NDATA) procArrayC (
.dinRef (dinRef),
.dinSig (dinSigC),
.clk (clk),
.rst (rst),
.ena (ena),
.cntin (cntin),
.dout (dIdC)
);
output_proc #(NDATA) outputProcA (
.din (dIdA),
.clk (clk),
.rst (rst),
.ena (ena),
.cntin (cntin),
.dout (dSsA)
);
endmodule
| 7.358377 |
module ssled (
input [15:0] in_score,
input clk_disp,
output [6:0] seg,
output [3:0] an
);
// AN3 - AN0
// CA - CG
reg [3:0] unary;
reg [1:0] binary;
wire [3:0] d;
initial begin
unary = 4'b1110;
binary = 2'b0;
end
wire [15:0] n;
assign n = in_score;
assign d = n[(4*binary+3)-:4];
ssled_disp _disp (
.digit(d),
.ssled_sel(unary),
.seg(seg),
.an(an)
);
function [3:0] binary_to_unary;
input [1:0] bin;
begin
case (bin[1:0])
2'b00: binary_to_unary = 4'b1110;
2'b01: binary_to_unary = 4'b1101;
2'b10: binary_to_unary = 4'b1011;
2'b11: binary_to_unary = 4'b0111;
endcase
end
endfunction
function [15:0] bcd(input [15:0] bin);
reg [7:0] i;
begin
bcd = 0;
for (
i = 0; i < 16; i = i + 1
) //run for 8 iterations
begin
bcd = {bcd[14:0], bin[15-i]}; //concatenation
//if a hex digit of 'bcd' is more than 4, add 3 to it.
if (i < 15 && bcd[3:0] > 4) bcd[3:0] = bcd[3:0] + 3;
if (i < 15 && bcd[7:4] > 4) bcd[7:4] = bcd[7:4] + 3;
if (i < 15 && bcd[11:8] > 4) bcd[11:8] = bcd[11:8] + 3;
if (i < 15 && bcd[15:12] > 4) bcd[15:12] = bcd[15:12] + 3;
end
end
endfunction
integer f;
initial begin
//f = $fopen("ssled.txt", "w");
end
always @(posedge clk_disp) begin
//$display("ssled: from ssled_disp: %d %d : %d %d", n[15:12], n[11:8], n[7:4], n[3:0]);
//$display("ssled: binary = %d, digit = %d", binary, d);
//$fwrite(f, "%b,%b\n", seg, an);
binary <= binary + 1'b1;
if (unary == 4'b0111) begin
unary <= 4'b1110;
end else if (unary == 4'b1111) begin
unary <= binary_to_unary(binary + 1'b1);
end else begin
unary <= {unary[2:0], 1'b1};
end
//$display("displaying unary %b, binary %d", unary, binary);
end
endmodule
| 6.660095 |
module ssled_disp (
input [3:0] digit,
input [3:0] ssled_sel,
output [6:0] seg,
output [3:0] an
);
reg [6:0] seg_reg;
reg [3:0] an_reg;
reg [6:0] map[0:9];
assign seg[6:0] = seg_reg[6:0];
assign an[3:0] = an_reg[3:0];
initial begin
seg_reg[6:0] = 7'b0;
an_reg[3:0] = 4'b0;
map[0] = 7'b1000000;
map[1] = 7'b1111001;
map[2] = 7'b0100100;
map[3] = 7'b0110000;
map[4] = 7'b0011001;
map[5] = 7'b0010010;
map[6] = 7'b0000010;
map[7] = 7'b1111000;
map[8] = 7'b0000000;
map[9] = 7'b0010000;
end
function [6:0] ssled_map(input [3:0] digit_);
begin
if (digit_ < 4'b1010) ssled_map = map[digit_];
else ssled_map = 7'b0;
end
endfunction
always @* begin
seg_reg[6:0] = ssled_map(digit);
an_reg[3:0] = ssled_sel[3:0];
end
endmodule
| 6.743125 |
module sspi (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
input i_clk,
input i_rst,
input spi_clk,
input spi_mosi,
output reg spi_miso,
output reg wb_cyc,
output reg wb_stb,
output reg [23:0] wb_adr,
input [15:0] wb_i_dat,
output reg [15:0] wb_o_dat,
output reg wb_we,
output [1:0] wb_sel,
input wb_ack,
input wb_err
);
reg [2:0] sy_clk;
wire sclk_edge = (sy_clk[2] ^ sy_clk[1]) & ~sy_clk[2];
always @(posedge i_clk) begin
if (i_rst) sy_clk <= 3'b0;
else sy_clk <= {sy_clk[1], sy_clk[0], spi_clk};
end
reg [23:0] req_addr;
reg [15:0] req_data;
reg [15:0] res_data;
reg resp_err;
reg [4:0] bit_cnt;
reg [3:0] state;
localparam STATE_IDLE = 4'b0;
localparam STATE_ADDR = 4'b1;
localparam STATE_RW = 4'b10;
localparam STATE_WRITE_DAT = 4'b11;
localparam STATE_WRITE_WB = 4'b100;
localparam STATE_WB_RESP = 4'b101;
localparam STATE_READ_WB = 4'b110;
localparam STATE_READ_DAT = 4'b111;
always @(posedge i_clk) begin
if (i_rst) begin
state <= STATE_IDLE;
bit_cnt <= 'b0;
spi_miso <= 1'b1;
end else if (sclk_edge) begin
if (state == STATE_IDLE) begin
spi_miso <= 1'b1;
if (~spi_mosi) state <= STATE_ADDR;
end else if (state == STATE_ADDR) begin
req_addr[bit_cnt] <= spi_mosi;
bit_cnt <= bit_cnt + 5'b1;
if (bit_cnt == 5'd23) begin
state <= STATE_RW;
bit_cnt <= 5'b0;
end
end else if (state == STATE_RW) begin
state <= (spi_mosi ? STATE_WRITE_DAT : STATE_READ_WB);
end else if (state == STATE_WRITE_DAT) begin
req_data[bit_cnt[3:0]] <= spi_mosi;
bit_cnt <= bit_cnt + 5'b1;
if (bit_cnt == 5'd15) begin
state <= STATE_WRITE_WB;
bit_cnt <= 5'b0;
end
end else if (state == STATE_WRITE_WB) begin
wb_cyc <= 1'b1;
wb_stb <= 1'b1;
wb_we <= 1'b1;
wb_adr <= req_addr;
wb_o_dat <= req_data;
if ((wb_ack | wb_err) & wb_cyc) begin
state <= STATE_WB_RESP;
bit_cnt <= 5'b0;
resp_err <= wb_err;
wb_cyc <= 1'b0;
wb_stb <= 1'b0;
spi_miso <= 1'b0; // end of wait
end
end else if (state == STATE_WB_RESP) begin
spi_miso <= resp_err;
state <= STATE_IDLE;
end else if (state == STATE_READ_WB) begin
wb_cyc <= 1'b1;
wb_stb <= 1'b1;
wb_we <= 1'b0;
wb_adr <= req_addr;
if ((wb_ack | wb_err) & wb_cyc) begin
state <= STATE_READ_DAT;
bit_cnt <= 5'b0;
res_data <= wb_i_dat;
resp_err <= wb_err;
wb_cyc <= 1'b0;
wb_stb <= 1'b0;
spi_miso <= 1'b0; // end of wait
end
end else if (state == STATE_READ_DAT) begin
spi_miso <= res_data[bit_cnt[3:0]];
bit_cnt <= bit_cnt + 5'b1;
if (bit_cnt == 5'd15) begin
state <= STATE_WB_RESP;
bit_cnt <= 5'b0;
end
end
end
end
assign wb_sel = 2'b11;
endmodule
| 8.472542 |
module SspRevAnd (
// Inputs
TieOff1,
TieOff2,
// Outputs
Revision
);
// Inputs
input TieOff1; // AND gate input 1
input TieOff2; // AND gate input 2
// Outputs
output Revision; // AND gate output
// ---------------------------------------------------------------------
//
// SspRevAnd
// =========
//
// ---------------------------------------------------------------------
//
// Overview
// ========
// This module contains a single AND gate to be used as a
// place-holder cell to mark the Revision of the Ssp.
// The 2 input pins will be tied-off at the top level of the
// hierarchy. These "TieOffs" can be identified during layout
// and re-wired to "VDD" or "VSS" if needed.
//
// ---------------------------------------------------------------------
// ---------------------------------------------------------------------
// Register declarations
// ---------------------------------------------------------------------
// ---------------------------------------------------------------------
//
// Main body of code
// =================
//
// ---------------------------------------------------------------------
assign Revision = TieOff1 & TieOff2;
endmodule
| 6.880756 |
modules for operating the ssp implementation
// Improved from original file as required/desired
`timescale 1 ns / 10 ps
module ssp_test1;
reg clock, clear_b, pwrite, psel, sspclkin, sspfssin, ssprxd;
reg [ 7: 0 ] data_in;
wire sspoe_b, ssptxd, sspfssout, sspclkout, ssptxintr, ssprxintr;
wire [ 7: 0 ] data_out;
initial
begin
clock = 1'b0;
clear_b = 1'b0;
psel = 1'b0;
sspclkin = 1'b0;
sspfssin = 1'b0;
ssprxd = 1'b0;
@( posedge clock );
#1;
@( posedge clock );
data_in = 8'b11111111; // 8'hFF, dummy data. should not enter into SSP.
#1;
clear_b = 1'b1;
#50 psel = 1'b1;
pwrite = 1'b1;
data_in = 8'b00110101; // 8'h35
#40 data_in = 8'b10101110; // 8'hAE
#30 psel = 1'b0;
#200 data_in = 8'b00100110; // 8'h26
#10 psel = 1'b1;
#40 data_in = 8'b00111001; // 8'h39
#40 data_in = 8'b10011101; // 8'h9D
#40 data_in = 8'b01110100; // 8'h74
#40 data_in = 8'b10001111; // 8'h8F
#40 data_in = 8'b10110001; // 8'bB1
#40 data_in = 8'b01010101; // 8'b55
#4000;
$stop;
end
always
#20 clock = ~clock;
// serial output from SSP is looped back to the serial input.
ssp ssp1 (
.PCLK( clock ),
.CLEAR_B( clear_b ),
.PSEL( psel ),
.PWRITE( pwrite ),
.SSPCLKIN( sspclkin ),
.SSPFSSIN( sspfssin ),
.SSPRXD( ssprxd ),
.PWDATA( data_in ),
.PRDATA( data_out ),
.SSPCLKOUT( sspclkout ),
.SSPFSSOUT( sspfssout ),
.SSPTXD( ssptxd ),
.SSPOE_B( sspoe_b ),
.SSPTXINTR( ssptxintr ),
.SSPRXINTR( ssprxintr )
);
endmodule
| 7.655239 |
module ssp_test2;
reg clock, clear_b, pwrite, psel;
reg [7:0] data_in;
wire [7:0] data_out;
wire sspoe_b, tx_to_rx, clk_wire, fss_wire, ssptxintr, ssprxintr;
initial begin
clock = 1'b0;
clear_b = 1'b0;
psel = 1'b1;
@(posedge clock);
#1;
@(posedge clock);
data_in = 8'b11111111; // 8'hFF, dummy data. should not enter into SSP.
#1;
clear_b = 1'b1;
#15 pwrite = 1'b1;
data_in = 8'b10010100; // 8'h94
#40 data_in = 8'b00001111; // 8'h0F
#40 data_in = 8'b01010001; // 8'h51
#40 data_in = 8'b00100100; // 8'h24
#40 data_in = 8'b01100111; // 8'h67
#40 data_in = 8'b11110011; // 8'hF3
#40 data_in = 8'b10110110; // 8'hB6
#40 data_in = 8'b10000100; // 8'b84
#30 psel = 1'b0;
#870 psel = 1'b1;
pwrite = 1'b0;
#80 pwrite = 1'b1;
#40 psel = 1'b0;
#3600 pwrite = 1'b0;
psel = 1'b1;
#40;
$stop;
end
always #20 clock = ~clock;
// serial output from SSP is looped back to the serial input.
ssp ssp2 (
.PCLK(clock),
.CLEAR_B(clear_b),
.PSEL(psel),
.PWRITE(pwrite),
.SSPCLKIN(clk_wire),
.SSPFSSIN(fss_wire),
.SSPRXD(tx_to_rx),
.PWDATA(data_in),
.PRDATA(data_out),
.SSPCLKOUT(clk_wire),
.SSPFSSOUT(fss_wire),
.SSPTXD(tx_to_rx),
.SSPOE_B(sspoe_b),
.SSPTXINTR(ssptxintr),
.SSPRXINTR(ssprxintr)
);
endmodule
| 7.127636 |
module implements a parameterized version of a distributed
// RAM synchronous FIFO. The address width, FIFO width and depth
// are all specified by parameters. Default parameters settings
// describe a 16x16 FIFO with Full (FF), Empty (EF), and Half
// Full (HF) flags. The module also outputs the count words in the
// FIFO.
//
// Dependencies: None
//
// Revision History:
//
// 0.01 07L22 MAM File Created
//
// 0.10 08K05 MAM Changed depth to a localparam based on addr
//
// 1.00 13G14 MAM Converted to Verilog 2001 standard
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DPSFnmCE #(
parameter addr = 4, // Sets depth of the FIFO: 2**addr
parameter width = 16, // Sets width of the FIFO
parameter init = "DPSFnmRAM.coe" // Initializes FIFO memory
)(
input Rst,
input Clk,
input WE,
input RE,
input [(width - 1):0] DI,
output [(width - 1):0] DO,
output FF,
output EF,
output HF,
output [addr:0] Cnt
);
////////////////////////////////////////////////////////////////////////////////
//
// Module Parameter List
//
localparam depth = (2**addr);
////////////////////////////////////////////////////////////////////////////////
//
// Module Level Declarations
//
reg [(width - 1):0] RAM [(depth - 1):0];
reg [ (addr - 1):0] A, DPRA;
reg [ (addr - 1):0] WCnt;
reg nEF, rFF;
wire Wr, Rd, CE;
////////////////////////////////////////////////////////////////////////////////
//
// Implementation
//
//
// Combinatorial Control Signals
//
assign Wr = WE & ~FF;
assign Rd = RE & ~EF;
assign CE = Wr ^ Rd;
//
// Write Address Counter
//
always @(posedge Clk)
begin
if(Rst)
A <= #1 0;
else if(Wr)
A <= #1 A + 1;
end
//
// Read Address Counter
//
always @(posedge Clk)
begin
if(Rst)
DPRA <= #1 0;
else if(Rd)
DPRA <= #1 DPRA + 1;
end
//
// Word Counter
//
always @(posedge Clk)
begin
if(Rst)
WCnt <= #1 0;
else if(Wr & ~Rd)
WCnt <= #1 WCnt + 1;
else if(Rd & ~Wr)
WCnt <= #1 WCnt - 1;
end
//
// External Word Count
//
assign Cnt = {FF, WCnt};
//
// Empty Flag Register (Active Low)
//
always @(posedge Clk)
begin
if(Rst)
nEF <= #1 0;
else if(CE)
nEF <= #1 ~(RE & (Cnt == 1));
end
assign EF = ~nEF;
//
// Full Flag Register
//
always @(posedge Clk)
begin
if(Rst)
rFF <= #1 0;
else if(CE)
rFF <= #1 (WE & (&WCnt));
end
assign FF = rFF;
//
// Half-Full Flag
//
assign HF = Cnt[addr] | Cnt[(addr - 1)];
//
// Dual-Port Synchronous RAM
//
initial
$readmemh(init, RAM, 0, (depth - 1));
always @(posedge Clk)
begin
if(Wr)
RAM[A] <= #1 DI; // Synchronous Write
end
assign DO = RAM[DPRA]; // Asynchronous Read
endmodule
| 6.904081 |
module implements the Baud Rate Generator for the SSP
// UART described for the 1700-0403 MicroBridge Option Card.
//
// The Baud Rate Generator implements the 16 baud rates defined
// in Table 3 of the SSP UART Specification.
//
// Dependencies:
//
// Revision History:
//
// 0.01 08E10 MAM File Created
//
// 1.00 08E10 MAM Initial Release
//
// 1.10 08E13 MAM Changed interface so Prescaler and Divider values
// passed directly in by removing Baud Rate ROM.
//
// 1.11 08E14 MAM Reduced width of divider from 10 to 8 bits.
//
// 1.20 08E15 MAM Changed the structure of the PSCntr and Divider
// to use a multiplxer on the input to load or count
// which results in a more efficient implementation.
// Added a registered TC on the PSCntr which functions
// to break the combinatorial logic chains and speed
// counter implementations.
//
// 1.30 08G26 MAM Corrected initial condition of the PSCntr, which
// caused the prescaler to always divide by two.
// Removed FF in PSCntr TC path to remove the divide
// by two issue. CE_16x output remains as registered.
//
// 2.00 11B06 MAM Converted to Verilog 2001.
//
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////////
module UART_BRG(
input Rst,
input Clk,
input [3:0] PS, // Baud Rate Generator Prescaler Load Value
input [7:0] Div, // Baud Rate Generator Divider Load Value
output reg CE_16x // Clock Enable Output - 16x Baud Rate Output
);
///////////////////////////////////////////////////////////////////////////////
//
// Local Signal Declarations
//
reg [ 3:0] PSCntr; // BRG Prescaler
reg [ 7:0] Divider; // BRG Divider
wire TC_PSCntr; // BRG Prescaler TC/Divider CE
wire TC_Divider; // BRG Divider TC
///////////////////////////////////////////////////////////////////////////////
//
// Implementation
//
// BRG Prescaler Counter
always @(posedge Clk)
begin
if(Rst)
PSCntr <= #1 0;
else if(TC_PSCntr)
PSCntr <= #1 PS;
else
PSCntr <= #1 PSCntr - 1;
end
assign TC_PSCntr = (PSCntr == 0);
// BRG Divider
always @(posedge Clk)
begin
if(Rst)
Divider <= #1 0;
else if(TC_Divider)
Divider <= #1 Div;
else if(TC_PSCntr)
Divider <= #1 Divider - 1;
end
assign TC_Divider = TC_PSCntr & (Divider == 0);
// Output 16x Bit Clock/CE
always @(posedge Clk)
begin
if(Rst)
CE_16x <= #1 1'b0;
else
CE_16x <= #1 TC_Divider;
end
endmodule
| 7.842559 |
module ssr (
input [4:1] j,
input p,
i,
y,
input [3:0] senha_sistema,
senha_usuario,
input gerador_frequencia,
output alarme
);
wire habilitador;
wire [5:0] fio;
wire and1, or1;
// instanciacao do modulo de entrada de senha
entrada_senha es_ssr (
senha_usuario,
senha_sistema,
gerador_frequencia,
habilitador
);
// verifica as possibilidades de violacao da residencial
and_3entradas Z1 (
i,
~y,
habilitador,
fio[0]
);
and_3entradas Z2 (
p,
y,
habilitador,
fio[1]
);
and_3entradas Z3 (
j[1],
y,
habilitador,
fio[2]
);
and_3entradas Z4 (
j[2],
y,
habilitador,
fio[3]
);
and_3entradas Z5 (
j[3],
y,
habilitador,
fio[4]
);
and_3entradas Z6 (
j[4],
y,
habilitador,
fio[5]
);
// verifica se pelo menos uma das entradas da casa foi violada
or_6entradas K (
fio[0],
fio[1],
fio[2],
fio[3],
fio[4],
fio[5],
alarme
);
endmodule
| 8.314705 |
module ssram(clock,addr,data,wen,ce);
parameter addrbits = 19;
parameter depth = 524288;
input clock;
input [addrbits-1:0] addr;
inout [35:0] data;
input wen;
input ce;
reg [35:0] ram [0:depth-1];
reg read_d1,read_d2;
reg write_d1,write_d2;
reg [addrbits-1:0] addr_d1,addr_d2;
always @(posedge clock)
begin
read_d1 <= #1 ce & ~wen;
write_d1 <= #1 ce & wen;
addr_d1 <= #1 addr;
read_d2 <= #1 read_d1;
write_d2 <= #1 write_d1;
addr_d2 <= #1 addr_d1;
if(write_d2)
ram[addr_d2] = data;
end // always @ (posedge clock)
data = (ce & read_d2) ? ram[addr_d2] : 36'bz;
always @(posedge clock)
if(~ce & (write_d2 | write_d1 | wen))
$display("$time ERROR: RAM CE not asserted during write cycle");
endmodule
| 7.670943 |
module ssram_test (
input clk,
input reset_n,
// ssram
output reg [18:0] ssram_address,
output reg ssram_oe_n,
output reg ssram_writeen_n,
output reg [3:0] ssram_byteen_n,
output ssram_adsp_n,
output ssram_clk,
output ssram_globalw_n,
output ssram_advance_n,
output ssram_adsc_n,
output ssram_ce1_n,
output ssram_ce2,
output ssram_ce3_n,
inout [35:0] ssram_data,
output [7:0] debug
);
assign debug = DAT_I[31:24];
assign ssram_clk = clk;
assign ssram_globalw_n = 1'b1;
assign ssram_adsp_n = 1'b1;
assign ssram_ce1_n = 1'b0;
assign ssram_ce2 = 1'b1;
assign ssram_ce3_n = 1'b0;
assign ssram_advance_n = 1'b1;
assign ssram_adsc_n = 1'b1;
reg ssram_data_oe;
reg [35:0] ssram_data_reg;
assign ssram_data = (ssram_data_oe == 1'b1) ? ssram_data_reg : 36'bZ;
reg [31:0] DAT_I;
reg [ 3:0] state;
parameter [3:0]
S_IDLE = 4'd0,
S_W1 = 4'd1,
S_W2 = 4'd2,
S_W3 = 4'd3,
S_W4 = 4'd4,
S_W5 = 4'd5,
S_IDLE2 = 4'd6,
S_R1 = 4'd7,
S_R2 = 4'd8,
S_R3 = 4'd9,
S_R4 = 4'd10,
S_IDLE3 = 4'd11;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) begin
ssram_address <= 19'd0;
ssram_data_reg <= 36'd0;
ssram_data_oe <= 1'b0;
ssram_oe_n <= 1'b1;
ssram_writeen_n <= 1'b1;
ssram_byteen_n <= 4'b1111;
DAT_I <= 32'd0;
state <= S_IDLE;
end else begin
case (state)
S_IDLE: begin
ssram_address <= 19'd0;
ssram_data_reg <= 36'd0;
ssram_data_oe <= 1'b0;
ssram_oe_n <= 1'b1;
ssram_writeen_n <= 1'b1;
ssram_byteen_n <= 4'b1111;
state <= S_W1;
end
S_W1: begin
// address, byte enables and write enables output
ssram_address <= 19'd0;
ssram_data_reg <= 36'd0;
ssram_data_oe <= 1'b0;
ssram_oe_n <= 1'b1;
ssram_writeen_n <= 1'b0;
ssram_byteen_n <= 4'b0000;
state <= S_W2;
end
S_W2: begin
// address, byte enables and write enables latched
ssram_data_reg <= {4'b0, 32'h71000000};
ssram_data_oe <= 1'b1;
ssram_address <= 19'd1;
state <= S_W3;
end
S_W3: begin
state <= S_W4;
end
S_W4: begin
ssram_data_reg <= {4'b0, 32'h72000000};
state <= S_IDLE2;
end
S_IDLE2: begin
ssram_address <= 19'd0;
ssram_data_reg <= 32'd0;
ssram_data_oe <= 1'b0;
ssram_oe_n <= 1'b1;
ssram_writeen_n <= 1'b1;
ssram_byteen_n <= 4'b1111;
state <= S_R1;
end
S_R1: begin
// address and byte enables output
ssram_address <= 19'd0;
ssram_data_reg <= 32'd0;
ssram_data_oe <= 1'b0;
ssram_oe_n <= 1'b1;
ssram_writeen_n <= 1'b1;
ssram_byteen_n <= 4'b0000;
state <= S_R2;
end
S_R2: begin
// address and byte enables latched
state <= S_R3;
end
S_R3: begin
// output enable output
ssram_oe_n <= 1'b0;
state <= S_R4;
end
S_R4: begin
// save data output
DAT_I <= ssram_data[31:0];
state <= S_IDLE3;
end
S_IDLE3: begin
ssram_address <= 19'd0;
ssram_data_reg <= 32'd0;
ssram_data_oe <= 1'b0;
ssram_oe_n <= 1'b1;
ssram_writeen_n <= 1'b1;
ssram_byteen_n <= 4'b1111;
end
endcase
end
end
endmodule
| 7.729181 |
module ssrv_memory
(
input clk,
input rst,
input imem_req,
input `N(`XLEN) imem_addr,
output imem_resp,
output `N(`XLEN) imem_rdata,
output imem_err,
input dmem_req,
input dmem_cmd,
input `N(2) dmem_width,
input `N(`XLEN) dmem_addr,
input `N(`XLEN) dmem_wdata,
output `N(`XLEN) dmem_rdata,
output dmem_resp,
output dmem_err
);
wire rden_a = imem_req & ( imem_addr[31:16]==0 );
wire `N(14) addr_a = imem_addr[15:0]>>2;
reg delay_rden_a;
`FFx(delay_rden_a,0)
delay_rden_a <= rden_a;
assign imem_resp = delay_rden_a;
assign imem_err = 1'b0;
wire rden_b = dmem_req & ( dmem_addr[31:16]==0 ) & ~dmem_cmd;
wire wren_b = dmem_req & ( dmem_addr[31:16]==0 ) & dmem_cmd;
wire `N(14) addr_b = dmem_addr[15:0]>>2;
wire `N(4) byteena_b = (dmem_width==2) ? 4'b1111 : ( (dmem_width==1) ? ( 2'b11<<{dmem_addr[1],1'b0} ) : (1'b1<<dmem_addr[1:0]) );
wire `N(`XLEN) data_b = (dmem_width==2) ? dmem_wdata : ( (dmem_width==1) ? {2{dmem_wdata[15:0]}} : {4{dmem_wdata[7:0]}} );
wire `N(`XLEN) q_b;
reg `N(4) dmem_para;
`FFx(dmem_para,0)
dmem_para <= { dmem_width,dmem_addr[1:0] };
assign dmem_rdata = (dmem_para[3:2]==2) ? q_b : ( (dmem_para[3:2]==1) ? ( q_b>>(`HLEN*dmem_para[1]) ) : ( q_b>>(8*dmem_para[1:0]) ) );
reg dmem_ack;
`FFx(dmem_ack,0)
dmem_ack <= rden_b|wren_b;
assign dmem_resp = dmem_ack;
assign dmem_err = 1'b0;
dualram i_dram (
.address_a ( addr_a ),
.address_b ( addr_b ),
.byteena_b ( byteena_b ),
.clock ( clk ),
.data_a ( 32'h0 ),
.data_b ( data_b ),
.rden_a ( rden_a ),
.rden_b ( rden_b ),
.wren_a ( 1'b0 ),
.wren_b ( wren_b ),
.q_a ( imem_rdata ),
.q_b ( q_b )
);
endmodule
| 6.58188 |
module sssp_pipeline (
clk,
rst,
last_input_in,
word_in,
word_in_valid,
control,
current_level,
control_out,
last_input_out,
word_out,
valid_out,
word_in_valid_out
);
parameter ADDR_W = 2;
parameter pipeline_id = 0;
parameter DATA_W = 32;
input clk, rst;
input [511:0] word_in;
input [0:0] word_in_valid;
input [1:0] control;
input [7:0] current_level;
input [0:0] last_input_in;
output reg [0:0] last_input_out;
reg [0:0] last_input_buff;
reg [0:0] last_input_buff_2;
output reg [63:0] word_out;
output reg valid_out;
output reg [1:0] control_out;
output reg [0:0] word_in_valid_out; // from afu-io
wire [ 31:0] bram_out;
reg [ 1:0] control_out_buff;
reg [ 1:0] control_out_buff_2;
reg [ 0:0] word_in_valid_buff;
reg [ 0:0] word_in_valid_buff_2;
reg [511:0] word_in_out_buff;
reg [511:0] word_in_out_buff_2;
multi_bank_bram #(
.DATA_W(DATA_W),
.ADDR_W(ADDR_W)
) bram0 (
.data_in(word_in),
//.r_addr(word_in[63:32]),
.r_addr(word_in[ADDR_W+3+40+pipeline_id*64:40+pipeline_id*64]),
.we_in((control == 1) & (word_in_valid)),
//.we_in(control),
.clk(clk),
//.rst(rst),
.data_out(bram_out)
);
always @(posedge clk) begin
if (rst) begin
word_out <= 0;
valid_out <= 1'b0;
control_out <= 0;
control_out_buff <= 0;
control_out_buff_2 <= 0;
last_input_buff <= 0;
last_input_buff_2 <= 0;
word_in_valid_buff <= 0;
word_in_valid_buff_2 <= 0;
word_in_valid_out <= 0;
word_in_out_buff <= 0;
word_in_out_buff_2 <= 0;
end else begin
control_out <= control_out_buff_2;
control_out_buff_2 <= control_out_buff;
control_out_buff <= control;
last_input_buff <= last_input_in;
last_input_buff_2 <= last_input_buff;
last_input_out <= last_input_buff_2;
word_in_valid_out <= word_in_valid_buff_2;
word_in_valid_buff_2 <= word_in_valid_buff;
word_in_valid_buff <= word_in_valid;
word_in_out_buff_2 <= word_in_out_buff;
word_in_out_buff <= word_in;
word_out <= 0;
valid_out <= 1'b0;
if ((word_in_valid_buff_2) & (control == 2)) begin
if (bram_out[7:0] == current_level) begin
word_out <= {
8'h00,
word_in_out_buff_2[39+pipeline_id*64:16+pipeline_id*64],
8'h00,
(word_in_out_buff_2[15+pipeline_id*64:0+pipeline_id*64] + bram_out[31:8])
};
valid_out <= 1'b1;
end
end
end
end
endmodule
| 6.685683 |
module sss_fallthrough_small_fifo #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
// SI: queue_depth
output reg [MAX_DEPTH_BITS:0] depth,
input reset,
input clk
);
reg fifo_valid, middle_valid, dout_valid;
reg [(WIDTH-1):0] middle_dout;
wire [(WIDTH-1):0] fifo_dout;
wire fifo_empty, fifo_rd_en;
wire will_update_middle, will_update_dout;
// gather fifo_depth info
wire [MAX_DEPTH_BITS:0] fifo_depth;
// orig_fifo is just a normal (non-FWFT) synchronous or asynchronous FIFO
sss_small_fifo #(
.WIDTH(WIDTH),
.MAX_DEPTH_BITS(MAX_DEPTH_BITS),
.PROG_FULL_THRESHOLD(PROG_FULL_THRESHOLD)
) fifo (
.din (din),
.wr_en (wr_en),
.rd_en (fifo_rd_en),
.dout (fifo_dout),
.full (full),
.nearly_full(nearly_full),
.prog_full (prog_full),
.empty (fifo_empty),
.depth (fifo_depth),
.reset (reset),
.clk (clk)
);
assign will_update_middle = fifo_valid && (middle_valid == will_update_dout);
assign will_update_dout = (middle_valid || fifo_valid) && (rd_en || !dout_valid);
assign fifo_rd_en = (!fifo_empty) && !(middle_valid && dout_valid && fifo_valid);
assign empty = !dout_valid;
always @(posedge clk) begin
if (reset) begin
fifo_valid <= 0;
middle_valid <= 0;
dout_valid <= 0;
dout <= 0;
middle_dout <= 0;
// SI
depth <= 0;
end else begin
if (will_update_middle) middle_dout <= fifo_dout;
if (will_update_dout) dout <= middle_valid ? middle_dout : fifo_dout;
if (fifo_rd_en) fifo_valid <= 1;
else if (will_update_middle || will_update_dout) fifo_valid <= 0;
if (will_update_middle) middle_valid <= 1;
else if (will_update_dout) middle_valid <= 0;
if (will_update_dout) dout_valid <= 1;
else if (rd_en) dout_valid <= 0;
// SI
depth <= fifo_depth;
end
end
endmodule
| 8.243607 |
module sss_small_fifo #(
parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2 ** MAX_DEPTH_BITS - 1
) (
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
output reg [MAX_DEPTH_BITS : 0] depth,
input reset,
input clk
);
parameter MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [WIDTH-1:0] queue[MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
//reg [MAX_DEPTH_BITS : 0] depth;
(* mark_debug = "true" *) wire [MAX_DEPTH_BITS : 0] queue_depth_debug = depth;
(* mark_debug = "true" *) wire wr_en_debug = wr_en;
(* mark_debug = "true" *) wire rd_en_debug = rd_en;
// Sample the data
always @(posedge clk) begin
if (wr_en) queue[wr_ptr] <= din;
if (rd_en)
dout <=
// synthesis translate_off
#1
// synthesis translate_on
queue[rd_ptr];
end
always @(posedge clk) begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en)
depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth + 'h1;
else if (~wr_en & rd_en)
depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth - 'h1;
end
end
assign full = depth == MAX_DEPTH;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= MAX_DEPTH - 1;
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk) begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0) $display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule
| 8.374224 |
module sstv_pixel (
input reset,
input [11:0] freq,
output reg [1:0] color
);
localparam PIXEL_BLACK = 2'b00;
localparam PIXEL_DARKGRAY = 2'b01;
localparam PIXEL_LIGHTGRAY = 2'b10;
localparam PIXEL_WHITE = 2'b11;
localparam FREQ_BLACK_LOWER = 12'd1500;
localparam FREQ_BLACK_UPPER = 12'd1700;
localparam FREQ_GRAY_MIDDLE = 12'd1900;
localparam FREQ_WHITE_LOWER = 12'd2100;
localparam FREQ_WHITE_UPPER = 12'd2300;
// Simple combinatorial logic to map the
// received frequencies into one of four
// "color bins."
always @(*)
if (reset) color = 0;
else begin
// White
if ((freq > FREQ_WHITE_LOWER) && (freq <= FREQ_WHITE_UPPER)) color = PIXEL_WHITE;
else
// Light Gray
if ((freq > FREQ_GRAY_MIDDLE) && (freq <= FREQ_WHITE_LOWER))
color = PIXEL_LIGHTGRAY;
else
// Dark Gray
if ((freq > FREQ_BLACK_UPPER) && (freq <= FREQ_GRAY_MIDDLE))
color = PIXEL_DARKGRAY;
else
// Black
color = PIXEL_BLACK;
end
endmodule
| 7.10573 |
module sstv_pixel_tb;
reg clk;
reg reset;
reg [11:0] freq;
wire [1:0] color;
reg [1:0] color_check;
reg test_fail;
wire [6:0] vis_code;
wire valid;
localparam CLK_TICKS_30MS = 32'd3_000;
sstv_pixel SSTV_PIXEL (
.reset(reset),
.freq(freq),
.color(color)
);
localparam PIXEL_BLACK = 2'b00;
localparam PIXEL_DARKGRAY = 2'b01;
localparam PIXEL_LIGHTGRAY = 2'b10;
localparam PIXEL_WHITE = 2'b11;
localparam FREQ_BLACK_LOWER = 12'd1500;
localparam FREQ_BLACK_UPPER = 12'd1700;
localparam FREQ_GRAY_MIDDLE = 12'd1900;
localparam FREQ_WHITE_LOWER = 12'd2100;
localparam FREQ_WHITE_UPPER = 12'd2300;
localparam FREQ_MAX = 12'hfff;
localparam FREQ_MIN = 12'h000;
localparam FREQ_1900HZ = 12'd1900;
localparam FREQ_1300HZ = 12'd1300;
localparam FREQ_1200HZ = 12'd1200;
localparam FREQ_1100HZ = 12'd1100;
// Run the clock
always #100 clk = ~clk;
initial begin
// Drive all of our inputs to known states
clk = 0;
reset = 1;
freq = 0;
test_fail = 0;
$dumpfile("sstv_pixel.vcd");
$dumpvars(0);
@(posedge clk);
sstv_pixel_decode();
$dumpflush;
#100 $finish;
end
task sstv_pixel_reset;
integer ticks;
begin
ticks = 0;
$display("Starting RESET");
while (ticks < 10) begin
@(posedge clk);
reset = 1'b1;
ticks = ticks + 1;
end
$display("Ending RESET");
@(posedge clk);
reset = 1'b0;
end
endtask
function [1:0] sstv_pixel_colormap;
input [11:0] freq;
begin
// White
if ((freq > FREQ_WHITE_LOWER) &&
(freq <= FREQ_WHITE_UPPER))
sstv_pixel_colormap = PIXEL_WHITE;
else
// Light Gray
if ((freq > FREQ_GRAY_MIDDLE) &&
(freq <= FREQ_WHITE_LOWER))
sstv_pixel_colormap = PIXEL_LIGHTGRAY;
else
// Dark Gray
if ((freq > FREQ_BLACK_UPPER) &&
(freq <= FREQ_GRAY_MIDDLE))
sstv_pixel_colormap = PIXEL_DARKGRAY;
else
// Black
sstv_pixel_colormap = PIXEL_BLACK;
end
endfunction
task sstv_pixel_decode;
integer driven_freq;
localparam TESTNAME = "sstv_pixel_decode";
begin
// Reset block
sstv_pixel_reset();
$display ("[%s] Starting test @ %g", TESTNAME, $time);
// Spin through the possible frequencies and verify that the output
// color is correct.
for (driven_freq = FREQ_MIN; driven_freq <= FREQ_MAX; driven_freq = driven_freq + 1) begin
$display ("[%s] Checking color decode for freq = %04d Hz", TESTNAME, driven_freq);
freq = driven_freq;
@(posedge clk);
assign color_check = sstv_pixel_colormap(freq);
if (color != color_check) begin
$display("freq: %d Color: %d should be: %d", freq, color, color_check);
test_fail = 1'b1;
end
end
end
endtask
assert_never #(
`OVL_ERROR,
`OVL_ASSERT,
"TEST FAIL!",
) sstv_pixel_tb_test_fail (
.clk(clk),
.reset_n(~reset),
.test_expr(test_fail)
);
endmodule
| 7.50039 |
module sstv_tb;
reg clk;
reg reset;
reg [11:0] freq;
reg test_fail;
wire [14:0] vid_addr;
wire [1:0] vid_pixel;
wire [6:0] vis_code;
wire vis_valid;
localparam CLK_TICKS_10MS = 32'd1_000;
localparam CLK_TICKS_30MS = 32'd3_000;
localparam CLK_TICKS_300MS = 32'd30_000;
localparam CLK_TICKS_350US = 32'd35;
sstv #(
.simulate(1)
) SSTV (
.clk(clk),
.reset(reset),
.freq(freq),
.vid_addr(vid_addr),
.vid_pixel(vid_pixel),
.vis_code(vis_code),
.vis_valid(vis_valid)
);
localparam FREQ_MAX = 12'hfff;
localparam FREQ_MIN = 12'h000;
localparam FREQ_1900HZ = 12'd1900;
localparam FREQ_1300HZ = 12'd1300;
localparam FREQ_1200HZ = 12'd1200;
localparam FREQ_1100HZ = 12'd1100;
localparam FREQ_BLACK = 12'd1500;
localparam FREQ_WHITE = 12'd2300;
// Run the clock
always #100 clk = ~clk;
task sstv_reset;
integer ticks;
begin
ticks = 0;
while (ticks < 10) begin
@(posedge clk);
reset = 1'b1;
ticks = ticks + 1;
end
@(posedge clk);
reset = 1'b0;
end
endtask
task sstv_delay;
integer ticks;
begin
ticks = 0;
while (ticks < CLK_TICKS_30MS) begin
@(posedge clk);
ticks = ticks + 1;
end
@(posedge clk);
end
endtask
task sstv_udelay;
integer ticks;
begin
ticks = 0;
while (ticks < CLK_TICKS_350US) begin
@(posedge clk);
ticks = ticks + 1;
end
@(posedge clk);
end
endtask
task sstv_vis_sendbit;
input bit;
begin
if (bit)
freq = FREQ_1100HZ;
else
freq = FREQ_1300HZ;
sstv_delay();
end
endtask
task sstv_frame;
integer freq_val;
integer ticks;
integer i;
reg [7:0] vis_code;
localparam TESTNAME = "sstv_frame";
begin
$display ("[%s] Starting test @ %g", TESTNAME, $time);
// Reset block
sstv_reset();
// Sending header
$display ("[%s] Sending header tone", TESTNAME);
freq = FREQ_1900HZ;
ticks = 0;
while (ticks < CLK_TICKS_300MS) begin
@(posedge clk);
ticks = ticks + 1;
end
@(posedge clk);
@(posedge clk);
freq = FREQ_1200HZ;
ticks = 0;
while (ticks < CLK_TICKS_10MS) begin
@(posedge clk);
ticks = ticks + 1;
end
@(posedge clk);
@(posedge clk);
freq = FREQ_1900HZ;
ticks = 0;
while (ticks < CLK_TICKS_300MS) begin
@(posedge clk);
ticks = ticks + 1;
end
@(posedge clk);
freq = FREQ_1200HZ;
sstv_delay();
vis_code = 8'h88;
for (i = 0; i < 8; i = i + 1) begin
sstv_vis_sendbit(vis_code[i]);
end
freq = FREQ_1200HZ;
sstv_delay();
// Sending VIS
for (i = 0; i < (160 * 120); i = i + 1) begin
freq = $random % (FREQ_WHITE - FREQ_BLACK + 1) + FREQ_BLACK;
sstv_udelay();
end
end
endtask
initial begin
// Drive all of our inputs to known states
clk = 0;
reset = 1;
freq = 0;
test_fail = 0;
$dumpfile("sstv.vcd");
$dumpvars(0);
@(posedge clk);
sstv_frame();
$dumpflush;
#100 $finish;
end
assert_never #(
`OVL_ERROR,
`OVL_ASSERT,
"TEST FAIL!",
) sstv_vis_tb_test_fail (
.clk(clk),
.reset_n(~reset),
.test_expr(test_fail)
);
endmodule
| 6.973788 |
module vga (
input clk,
input reset,
input [1:0] alt_color,
input video_on,
input [9:0] pixel_row,
input [9:0] pixel_col,
// Input from bitmap ROM
output [14:0] bitmap_rom_addr,
input bitmap_rom_data,
// Input from SSTV RAM
output [14:0] sstv_ram_addr,
input [ 1:0] sstv_ram_data,
// Colors
output reg [2:0] red,
output reg [2:0] green,
output reg [1:0] blue
);
reg [7:0] bitmap_col;
reg [6:0] bitmap_row;
reg [7:0] sstv_col;
reg [6:0] sstv_row;
reg [7:0] color;
reg [7:0] on_color;
// Convert the row/col into a sensible address.
assign bitmap_rom_addr = (bitmap_row * 160) + bitmap_col;
assign sstv_ram_addr = (sstv_row * 160) + sstv_col;
// Update the color registers on a clock edge.
always @(posedge clk) begin
if (video_on) begin
red <= color[2:0];
green <= color[5:3];
blue <= color[7:6];
end else begin
// All colors to black during the blanking interval.
red <= 3'b000;
green <= 3'b000;
blue <= 2'b00;
end
end
// Constants for the few supported colors
localparam COLOR_BLACK = 8'b00_000_000;
localparam COLOR_WHITE = 8'b11_111_111;
localparam COLOR_GREEN = 8'b00_111_000;
localparam COLOR_RED = 8'b00_000_111;
localparam COLOR_BLUE = 8'b11_000_000;
localparam COLOR_DARKGRAY = 8'b01_010_010;
localparam COLOR_LIGHTGRAY = 8'b10_100_100;
// Combo logic for mapping our "on" color.
always @(*)
if (reset) on_color = COLOR_WHITE;
else
case (alt_color)
2'b00: on_color = COLOR_WHITE;
2'b01: on_color = COLOR_GREEN;
2'b10: on_color = COLOR_RED;
2'b11: on_color = COLOR_BLUE;
endcase
// More combo logic for mapping ROM/RAM pixels
// into VGA space. Deeper logic than I'd like,
// but it works and I'm tired.
always @(*)
if (reset) color = COLOR_BLACK;
else begin
color = COLOR_BLACK;
// Bitmap ROM data
if ((pixel_col >= 10'd0) && (pixel_col < 10'd320)) begin
if (pixel_row < 10'd240) begin
bitmap_col = pixel_col >> 1;
bitmap_row = pixel_row >> 1;
if (bitmap_rom_data) color = on_color;
else color = COLOR_BLACK;
end
end // RAM (SSTV output) data
else if ((pixel_col >= 10'd320) && (pixel_col < 10'd640)) begin
if (pixel_row < 10'd240) begin
sstv_col = (pixel_col - 10'd320) >> 1;
sstv_row = pixel_row >> 1;
if (sstv_ram_data) color = on_color;
else color = COLOR_BLACK;
end
end
end
endmodule
| 6.790484 |
module ssvga_wbs_if (
// Clock and reset
wb_clk_i,
wb_rst_i,
// WISHBONE Slave I/F
wbs_cyc_i,
wbs_stb_i,
wbs_sel_i,
wbs_we_i,
wbs_adr_i,
wbs_dat_i,
wbs_cab_i,
wbs_dat_o,
wbs_ack_o,
wbs_err_o,
wbs_rty_o,
// Other signals
ssvga_en,
pal_wr_en,
pal_rd_en,
pal_dat,
pix_start_addr
);
//
// I/O ports
//
//
// Clock and reset
//
input wb_clk_i; // Pixel Clock
input wb_rst_i; // Reset
//
// WISHBONE Slave I/F
//
input wbs_cyc_i;
input wbs_stb_i;
input [3:0] wbs_sel_i;
input wbs_we_i;
input [31:0] wbs_adr_i;
input [31:0] wbs_dat_i;
input wbs_cab_i;
output [31:0] wbs_dat_o;
output wbs_ack_o;
output wbs_err_o;
output wbs_rty_o;
//
// Other signals
//
output ssvga_en; // Global enable
output pal_wr_en; // Palette write enable
output pal_rd_en; // Palette read enable
input [15:0] pal_dat; // Palette data
output [31:2] pix_start_addr;
//
// Internal regs and wires
//
reg wbs_ack_o; // WISHBONE ack
reg wbs_err_o; // WISHBONE err
reg [0:0] ctrl_r; // Control register
wire valid_access; // Access to SSVGA
//
// Control register
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) ctrl_r <= #1 1'b0;
else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & !wbs_adr_i[`SEL_ADDRESS])
ctrl_r <= #1 wbs_dat_i[0];
reg [31:2] pix_start_addr;
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) pix_start_addr <= #1 30'h0000_0000;
else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & wbs_adr_i[`SEL_ADDRESS])
pix_start_addr <= #1 wbs_dat_i[31:2];
//
// Generate delayed WISHBONE ack/err
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
wbs_ack_o <= #1 1'b0;
wbs_err_o <= #1 1'b0;
end else if (valid_access) begin
wbs_ack_o <= #1 1'b1;
wbs_err_o <= #1 1'b0;
end else if (wbs_cyc_i & wbs_stb_i) begin
wbs_ack_o <= #1 1'b0;
wbs_err_o <= #1 1'b1;
end else begin
wbs_ack_o <= #1 1'b0;
wbs_err_o <= #1 1'b0;
end
//
// Generate WISHBONE output signals
//
reg [31:0] wbs_dat_o;
always @(wbs_adr_i or pal_dat or ctrl_r or pix_start_addr) begin
if (wbs_adr_i[`SEL_PAL]) wbs_dat_o = {16'h0000, pal_dat};
else if (wbs_adr_i[`SEL_ADDRESS]) wbs_dat_o = {pix_start_addr, 2'b00};
else wbs_dat_o = {{31{1'b0}}, ctrl_r};
end
assign wbs_rty_o = 1'b0;
//
// Generate other signals
//
assign valid_access = wbs_cyc_i & wbs_stb_i & (wbs_sel_i == 4'b1111);
assign ssvga_en = ctrl_r[0];
assign pal_wr_en = valid_access & wbs_we_i & wbs_adr_i[`SEL_PAL];
assign pal_rd_en = valid_access & ~wbs_we_i & wbs_adr_i[`SEL_PAL];
endmodule
| 6.575547 |
module ss_A2D (
clk,
rst_n,
strt_cnv,
result,
cnv_cmplt
);
input clk, rst_n; // clock and active low reset
input strt_cnv; // start conversion
output [9:0] result; // result of average of 8-samples
output cnv_cmplt; // asserted for 1 clock when conversion completes
wire [9:0] result;
/////////////////////////////////////
// Instantiate datapath of ss_A2D //
///////////////////////////////////
ss_A2D_datapath iDP (
.clk(clk),
.clr_dac(clr_dac),
.inc_dac(inc_dac),
.clr_smp(clr_smp),
.inc_smp(inc_smp),
.accum(accum),
.gt(gt),
.result(result),
.smp_eq_8(smp_eq_8)
);
//////////////////////////////////////////
// Instantiate state machine of ss_A2D //
////////////////////////////////////////
ss_A2D_SM iSM (
.clk(clk),
.rst_n(rst_n),
.strt_cnv(strt_cnv),
.smp_eq_8(smp_eq_8),
.gt(gt),
.clr_dac(clr_dac),
.inc_dac(inc_dac),
.clr_smp(clr_smp),
.inc_smp(inc_smp),
.accum(accum),
.cnv_cmplt(cnv_cmplt)
);
endmodule
| 6.864672 |
module SS_ADDSUB (
CLK,
INIT,
IN,
SIGN,
R_condition,
OUT,
SIGN_out
);
parameter N = 6;
//parameter DIFFCOUNTER_SIZE = 5;
//parameter DIFFCOUNT_LOWERLIM = 4;
parameter DIFFCOUNTER_SIZE = 1;
parameter DIFFCOUNT_LOWERLIM = 0;
input CLK, INIT;
input [N-1:0] IN, SIGN;
input R_condition;
output OUT, SIGN_out;
wire INPUT_SUM_pos, INPUT_SUM_neg;
wire OUTPUT_pos, OUTPUT_neg, OUT;
//wire COUNT_ACTIVE;
reg [DIFFCOUNTER_SIZE-1:0] DIFFCOUNT = 1'd0;
reg DIFFCOUNT_SIGN = 1'd0;
reg [DIFFCOUNTER_SIZE-1:0] DIFFCOUNT_LIMIT = 1'd0 - 1'd1;
wire [N-1:0] N_INPUTS_pos;
wire [N-1:0] N_INPUTS_neg;
M_SIDEADD #(
.N_inputs(N),
.NB_out (N)
) SIDEADDpos (
.EN (1'b1),
.IN (IN & (~SIGN)),
.OUT(N_INPUTS_pos)
);
M_SIDEADD #(
.N_inputs(N),
.NB_out (N)
) SIDEADDneg (
.EN (1'b1),
.IN (IN & (SIGN)),
.OUT(N_INPUTS_neg)
);
//defparam SIDEADDpos.N_inputs = N;
//defparam SIDEADDpos.NB_out = N;
//defparam SIDEADDneg.N_inputs = N;
//defparam SIDEADDneg.NB_out = N;
wire EQUAL, INPUT_SIGN;
assign EQUAL = (N_INPUTS_pos == N_INPUTS_neg);
assign INPUT_SIGN = (R_condition) ? (N_INPUTS_neg>=N_INPUTS_pos) : (N_INPUTS_neg>N_INPUTS_pos);
always @(posedge CLK or posedge INIT) begin
if (INIT) begin
DIFFCOUNT_SIGN = 1'b0;
//DIFFCOUNT_SIGN = DIFFCOUNT_SIGN;
DIFFCOUNT <= 1'b0;
end else if (EQUAL) DIFFCOUNT <= DIFFCOUNT;
else if ((!INPUT_SIGN)&(DIFFCOUNT_SIGN)&(DIFFCOUNT<N_INPUTS_pos)) begin // +ve input, currently -ve, cross: -ve -> +ve
DIFFCOUNT_SIGN = 1'b0;
DIFFCOUNT <= N_INPUTS_pos;
// NOTE: If DIFFCOUNT = 1, (DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_pos) will never be satisfied when only a single input is 1.
end else if ((!INPUT_SIGN)&(DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_pos))&(!DIFFCOUNT_SIGN)) begin // +ve input, currently +ve, stay as positive and increment
DIFFCOUNT <= DIFFCOUNT + N_INPUTS_pos;
end else if ((!INPUT_SIGN)&(DIFFCOUNT_SIGN)) begin // +ve input, currently -ve, stay -ve and decrement
DIFFCOUNT <= DIFFCOUNT - N_INPUTS_pos;
end else if ((INPUT_SIGN)&(!DIFFCOUNT_SIGN)&(DIFFCOUNT<N_INPUTS_neg)) begin // -ve input, currently +ve, cross: +ve -> -ve
DIFFCOUNT_SIGN = 1'b1;
DIFFCOUNT <= N_INPUTS_neg;
end else if ((INPUT_SIGN)&(DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_neg))&(DIFFCOUNT_SIGN)) begin // -ve input, currently +ve, cross: +ve -> -ve
DIFFCOUNT <= DIFFCOUNT + N_INPUTS_neg;
end else if ((INPUT_SIGN)&(!DIFFCOUNT_SIGN)) begin // -ve input, currently +ve, stay +ve and decrement
DIFFCOUNT <= DIFFCOUNT - N_INPUTS_neg;
end else DIFFCOUNT <= DIFFCOUNT;
end
assign SIGN_out = DIFFCOUNT_SIGN;
M_OR OR_pos (
1'b1,
IN & (~SIGN),
INPUT_SUM_pos
);
defparam OR_pos.N = N;
M_OR OR_neg (
1'b1,
IN & (SIGN),
INPUT_SUM_neg
);
defparam OR_neg.N = N;
assign OUTPUT_pos = INPUT_SUM_pos & (~INPUT_SUM_neg);
assign OUTPUT_neg = INPUT_SUM_neg & (~INPUT_SUM_pos);
assign OUT_temp = (SIGN_out) ? (OUTPUT_neg) : (OUTPUT_pos);
//assign OUT = (DIFFCOUNT > (DIFFCOUNT_LIMIT-2'd2)) ? OUT_temp : 1'b0;
assign OUT = (DIFFCOUNT > (DIFFCOUNT_LOWERLIM)) ? OUT_temp : 1'b0;
endmodule
| 7.109077 |
module SS_ADDSUB2 (
CLK,
INIT,
IN,
SIGN,
R_condition,
OUT,
SIGN_out
);
parameter N = 2;
parameter DIFFCOUNTER_SIZE = 2;
parameter DIFFCOUNT_MIN = 1;
input CLK, INIT;
input [N-1:0] IN, SIGN;
input R_condition;
output OUT, SIGN_out;
wire INPUT_SUM_pos, INPUT_SUM_neg;
wire OUTPUT_pos, OUTPUT_neg, OUT;
wire COUNT_ACTIVE;
reg [DIFFCOUNTER_SIZE-1:0] DIFFCOUNT = 1'd0;
reg DIFFCOUNT_SIGN = 1'd0;
reg [DIFFCOUNTER_SIZE-1:0] DIFFCOUNT_LIMIT = 1'd0 - 1'd1;
wire [N-1:0] N_INPUTS_pos;
wire [N-1:0] N_INPUTS_neg;
assign N_INPUTS_pos = {1'b0, IN[0] & (~SIGN[0])} + {1'b0, IN[1] & (~SIGN[1])};
assign N_INPUTS_neg = {1'b0, IN[0] & (SIGN[0])} + {1'b0, IN[1] & (SIGN[1])};
wire EQUAL, INPUT_SIGN;
assign EQUAL = (N_INPUTS_pos == N_INPUTS_neg);
assign INPUT_SIGN = (R_condition) ? (N_INPUTS_neg>=N_INPUTS_pos) : (N_INPUTS_neg>N_INPUTS_pos);
always @(posedge CLK) begin
if (INIT) begin
DIFFCOUNT_SIGN = DIFFCOUNT_SIGN;
DIFFCOUNT <= 1'b0;
end else if (EQUAL) DIFFCOUNT <= DIFFCOUNT;
else if ((!INPUT_SIGN)&(DIFFCOUNT_SIGN)&(DIFFCOUNT<N_INPUTS_pos)) begin // +ve input, currently -ve, cross: -ve -> +ve
DIFFCOUNT_SIGN = 1'b0;
DIFFCOUNT <= N_INPUTS_pos;
end else if ((!INPUT_SIGN)&(DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_pos))&(!DIFFCOUNT_SIGN)) begin // +ve input, currently +ve, stay as positive and increment
DIFFCOUNT <= DIFFCOUNT + N_INPUTS_pos;
end else if ((!INPUT_SIGN)&(DIFFCOUNT_SIGN)) begin // +ve input, currently -ve, stay -ve and decrement
DIFFCOUNT <= DIFFCOUNT - N_INPUTS_pos;
end else if ((INPUT_SIGN)&(!DIFFCOUNT_SIGN)&(DIFFCOUNT<N_INPUTS_neg)) begin // -ve input, currently +ve, cross: +ve -> -ve
DIFFCOUNT_SIGN = 1'b1;
DIFFCOUNT <= N_INPUTS_neg;
end else if ((INPUT_SIGN)&(DIFFCOUNT<(DIFFCOUNT_LIMIT-N_INPUTS_neg))&(DIFFCOUNT_SIGN)) begin // -ve input, currently -ve, stay as negative and increment
DIFFCOUNT <= DIFFCOUNT + N_INPUTS_neg;
end else if ((INPUT_SIGN)&(!DIFFCOUNT_SIGN)) begin // -ve input, currently +ve, stay +ve and decrement
DIFFCOUNT <= DIFFCOUNT - N_INPUTS_neg;
end else DIFFCOUNT <= DIFFCOUNT;
end
assign SIGN_out = DIFFCOUNT_SIGN;
assign INPUT_SUM_pos = (IN[0] & (~SIGN[0])) | (IN[1] & (~SIGN[1]));
assign INPUT_SUM_neg = (IN[0] & (SIGN[0])) | (IN[1] & (SIGN[1]));
assign OUTPUT_pos = INPUT_SUM_pos & (~INPUT_SUM_neg);
assign OUTPUT_neg = INPUT_SUM_neg & (~INPUT_SUM_pos);
//assign OUTPUT_pos = INPUT_SUM_pos&(~INPUT_SUM_neg)&(DIFFCOUNT>DIFFCOUNT_MIN);
//assign OUTPUT_neg = INPUT_SUM_neg&(~INPUT_SUM_pos)&(DIFFCOUNT>DIFFCOUNT_MIN);
assign OUT_temp = (SIGN_out) ? (OUTPUT_neg) : (OUTPUT_pos);
assign OUT = (DIFFCOUNT > (DIFFCOUNT_MIN)) ? OUT_temp : 1'b0;
endmodule
| 6.832631 |
module Mux_PC (
input [63:0] PC_in,
input [63:0] Shift_in,
input Jump_control,
output reg [63:0] PC_out
);
always @(PC_in, Shift_in, Jump_control, PC_out) begin
if (Jump_control == 0) begin
PC_out = PC_in;
end else begin
PC_out = Shift_in;
end
end
endmodule
| 8.32273 |
module Mux_REG (
input [4:0] in_1,
input [4:0] in_2,
input Reg2Loc_control,
output reg [4:0] Mux_out
);
always @(in_1, in_2, Reg2Loc_control) begin
if (Reg2Loc_control == 0) begin
Mux_out = in_1;
end else begin
Mux_out = in_2;
end
end
endmodule
| 6.735029 |
module Mux_ALU (
input [63:0] in_1,
input [63:0] in_2,
input ALUSrc_control,
output reg [63:0] Mux_out
);
always @(in_1, in_2, ALUSrc_control, Mux_out) begin
if (ALUSrc_control == 0) begin
Mux_out = in_1;
end else begin
Mux_out = in_2;
end
end
endmodule
| 7.307889 |
module Mux_Data_Memory (
input [63:0] Data_read,
input [63:0] ALU_out,
input Mem2Reg_control,
output reg [63:0] Mux_out
);
always @(Data_read, ALU_out, Mem2Reg_control, Mux_out) begin
if (Mem2Reg_control == 0) begin
Mux_out = ALU_out;
end else begin
Mux_out = Data_read;
end
end
endmodule
| 8.61217 |
module Sign_Extend (
input [31:0] instruction_in,
output reg [63:0] immediate_out
);
always @(instruction_in) begin
if (instruction_in[31:26] == 6'b000101) begin // B
immediate_out[25:0] = instruction_in[25:0];
immediate_out[63:26] = {64{immediate_out[25]}};
end else if (instruction_in[31:24] == 8'b10110100) begin // CBZ
immediate_out[19:0] = instruction_in[23:5];
immediate_out[63:20] = {64{immediate_out[19]}};
end else begin // D Type
immediate_out[9:0] = instruction_in[20:12];
immediate_out[63:10] = {64{immediate_out[9]}};
end
end
endmodule
| 7.338842 |
module Shift_LEFT2 (
input [63:0] Data_in,
output reg [63:0] Data_out
);
always @(Data_in) begin
Data_out = Data_in << 2;
end
endmodule
| 7.060616 |
module ALU (
input [63:0] A,
B,
input [3:0] SELECT,
output reg [63:0] OUT,
output reg ZEROFLAG
);
always @(A or B or SELECT) begin
case (SELECT)
4'b0000: OUT = A & B;
4'b0001: OUT = A | B;
4'b0010: OUT = A + B;
4'b0110: OUT = A - B;
4'b0111: OUT = B;
4'b1100: OUT = ~(A | B);
endcase
if (OUT == 0) begin
ZEROFLAG = 1'b1;
end else begin
ZEROFLAG = 1'b0;
end
end
endmodule
| 7.960621 |
module Registers (
input [4:0] read_1,
input [4:0] read_2,
input [4:0] Reg_write,
input [63:0] Data_write,
input RegWrite_control,
output reg [63:0] data_1,
output reg [63:0] data_2
);
reg [63:0] Data[31:0];
integer initCount;
initial begin
for (initCount = 0; initCount < 31; initCount = initCount + 1) begin
Data[initCount] = initCount;
end
Data[31] = 64'h00000000;
end
always @(read_1, read_2, Reg_write, Data_write, RegWrite_control) begin
data_1 = Data[read_1];
data_2 = Data[read_2];
if (RegWrite_control == 1) begin
Data[Reg_write] = Data_write;
end
end
endmodule
| 7.405039 |
module Data_Memory (
input [63:0] address_in,
input [63:0] data_in,
input MemRead_control,
input MemWrite_control,
output reg [63:0] Data_out
);
reg [63:0] Data[31:0];
integer initCount;
initial begin
for (initCount = 0; initCount < 32; initCount = initCount + 1) begin
Data[initCount] = initCount * 100;
end
Data[10] = 1540;
Data[11] = 2117;
end
always @(address_in, data_in, MemRead_control, MemWrite_control) begin
if (MemWrite_control == 1) begin
Data[address_in] = data_in;
end
if (MemRead_control == 1) begin
Data_out = Data[address_in];
end
end
endmodule
| 7.239913 |
module SS_ARM_tb;
/* Clock Signal */
reg CLK;
/* Wires to connect instruction memory to CPU */
wire [63:0] PC_instruction;
wire [31:0] Out_instruction;
/* Wires to connect registers to CPU */
wire [4:0] Read_register_1;
wire [4:0] Read_register_2;
wire [4:0] Write_register;
wire [63:0] Write_data;
wire [63:0] Data_out_1;
wire [63:0] Data_out_2;
/* Wires to connect Data Memory to CPU */
wire [63:0] memory_data;
wire [63:0] ALU_result;
/* Wires to connect CPU Control Lines to Memories */
wire Reg2Loc_control;
wire RegWrite_control;
wire MemRead_control;
wire MemWrite_control;
wire Branch_control;
/* Instruction Memory Module */
Instruction_Memory mem1 (
PC_instruction,
Out_instruction
);
/* Registers Module */
Registers mem2 (
Read_register_1,
Read_register_2,
Write_register,
Write_data,
RegWrite_control,
Data_out_1,
Data_out_2
);
/* Data Memory Module */
Data_Memory mem3 (
ALU_result,
Data_out_2,
MemRead_control,
MemWrite_control,
memory_data
);
/* CPU Module */
SS_ARM core (
.CLK(CLK),
.instruction_word(Out_instruction),
.PC(PC_instruction),
.Reg2Loc_control(Reg2Loc_control),
.RegWrite_control(RegWrite_control),
.MemRead_control(MemRead_control),
.MemWrite_control(MemWrite_control),
.Branch_control(Branch_control),
.Read_register_1(Read_register_1),
.Read_register_2(Read_register_2),
.Write_register(Write_register),
.register_data_1(Data_out_1),
.register_data_2(Data_out_2),
.ALU_result(ALU_result),
.memory_data(memory_data),
.Write_register_data(Write_data)
);
/* Setup the clock */
initial begin
CLK = 1'b0;
#30 $finish;
end
/* Toggle the clock */
always begin
#1 CLK = ~CLK;
end
endmodule
| 9.328874 |
module SS_Control #(
N = 4
) (
input clk, // clock freq of about 750 Hz
input rst,
input [N*4-1:0] numbers, // list of 4 bit numbers to display
output [ N-1:0] displays, // the displays (active low)
output [ 6:0] segments // abcdefg segments (active low)
);
reg [6:0] abcdefg[N-1:0];
reg [$clog2(N)+1:0] count;
assign displays = ~reset ? ~(1'b1 << count) : ~1'b0;
assign segments = abcdefg[count];
always @(posedge clk) count <= (count == N - 1) ? 1'b0 : count + 1'b1;
generate
for (genvar i = 0; i < N; i = i + 1) begin : decoder
always @(*) begin
case (numbers[i*4+3:i*4])
4'h0: abcdefg[i] <= 7'h01;
4'h1: abcdefg[i] <= 7'h4F;
4'h2: abcdefg[i] <= 7'h12;
4'h3: abcdefg[i] <= 7'h06;
4'h4: abcdefg[i] <= 7'h4C;
4'h5: abcdefg[i] <= 7'h24;
4'h6: abcdefg[i] <= 7'h20;
4'h7: abcdefg[i] <= 7'h0F;
4'h8: abcdefg[i] <= 7'h00;
4'h9: abcdefg[i] <= 7'h04;
4'hA: abcdefg[i] <= 7'h08;
4'hB: abcdefg[i] <= 7'h60;
4'hC: abcdefg[i] <= 7'h31;
4'hD: abcdefg[i] <= 7'h42;
4'hE: abcdefg[i] <= 7'h30;
4'hF: abcdefg[i] <= 7'h38;
endcase
end
end
endgenerate
endmodule
| 7.206497 |
module ss_dataforward (
input [4:0] Rd1e1,
Rd2e1,
Rd1e2,
Rd2e2,
input RegWriteE1,
RegWriteM1,
RegWriteW1,
RegWriteE2,
RegWriteM2,
RegWriteW2,
input [4:0] WriteRegE1,
WriteRegM1,
WriteRegW1,
WriteRegE2,
WriteRegM2,
WriteRegW2,
input [31:0] AluOutE1,
AluOutM1,
WriteData3_1,
AluOutE2,
AluOutM2,
WriteData3_2,
output reg SSForwardAE1,
SSForwardBE1,
SSForwardAE2,
SSForwardBE2,
output reg [31:0] SSAluInA1,
SSAluInB1,
SSAluInA2,
SSAluInB2
);
/* DATA FORWARDING FOR FORWARDING HAZARDS
FORWARD ON THE FOLLOWING CASES:
-REGS OF NEXT EXEC INSTR USES ANY REGS IN MEM STAGE
-REGS OF NEXT EXEC NSTR USES ANY REGS IN WB STAGE */
always @(*) begin
//default case: direct values in muxes
SSForwardAE1 <= 0;
SSForwardBE1 <= 0;
SSForwardAE2 <= 0;
SSForwardBE2 <= 0;
//GET REG VALUES FROM D1EX IF THEY ARE NEEDED IN D2EX
if ((RegWriteE1) && (WriteRegE1 != 0) && (WriteRegE1 == Rd1e2)) begin
SSForwardAE2 <= 1;
SSAluInA2 <= AluOutE1;
end
if ((RegWriteE1) && (WriteRegE1 != 0) && (WriteRegE1 == Rd2e2)) begin
SSForwardBE2 <= 1;
SSAluInB2 <= AluOutE1;
end
//GET REG VALUES FROM D1MEM IF THEY ARE NEEDED IN D2EX
if( (RegWriteM1) &&
(WriteRegM1 != 0) &&
(WriteRegM1 != WriteRegE1) &&
(WriteRegM1 == Rd1e2)) begin
SSForwardAE2 <= 1;
SSAluInA2 <= AluOutM1;
end
if( (RegWriteM1) &&
(WriteRegM1 != 0) &&
(WriteRegM1 != WriteRegE1) &&
(WriteRegM1 == Rd2e2)) begin
SSForwardBE2 <= 1;
SSAluInB2 <= AluOutM1;
end
//GET REG VALUES FROM D1WB IF THEY ARE NEEDED IN D2EX
if( (RegWriteW1) &&
(WriteRegW1 != 0) &&
(WriteRegW1 != WriteRegM1) &&
(WriteRegW1 != WriteRegE1) &&
(WriteRegW1 == Rd1e2)) begin
SSForwardAE2 <= 1;
SSAluInA2 <= WriteData3_1;
end
if( (RegWriteW1) &&
(WriteRegW1 != 0) &&
(WriteRegW1 != WriteRegM1) &&
(WriteRegW1 != WriteRegE1) &&
(WriteRegW1 == Rd2e2)) begin
SSForwardBE2 <= 1;
SSAluInB2 <= WriteData3_1;
end
if ((RegWriteE1) && (WriteRegE1 != 0) && (WriteRegE1 == Rd1e2)) begin
SSForwardAE2 <= 1;
SSAluInA2 <= AluOutE1;
end
if ((RegWriteE1) && (WriteRegE1 != 0) && (WriteRegE1 == Rd2e2)) begin
SSForwardBE2 <= 1;
SSAluInB2 <= AluOutE1;
end
//THIS IS FOR VICE VERSA DATA FORWARD FROM DP2 TO DP1
//GET REG VALUES FROM D1MEM IF THEY ARE NEEDED IN D2EX
if ((RegWriteM2) && (WriteRegM2 != 0) && (WriteRegM2 == Rd1e1)) begin
SSForwardAE1 <= 1;
SSAluInA1 <= AluOutM2;
end
if ((RegWriteM2) && (WriteRegM2 != 0) && (WriteRegM2 == Rd2e1)) begin
SSForwardBE1 <= 1;
SSAluInB1 <= AluOutM2;
end
//GET REG VALUES FROM D1WB IF THEY ARE NEEDED IN D2EX
if( (RegWriteW2) &&
(WriteRegW2 != 0) &&
(WriteRegW2 != WriteRegM2) &&
(WriteRegW2 == Rd1e1)) begin
SSForwardAE1 <= 1;
SSAluInA1 <= WriteData3_2;
end
if( (RegWriteW2) &&
(WriteRegW2 != 0) &&
(WriteRegW2 != WriteRegM2) &&
(WriteRegW2 == Rd2e1)) begin
SSForwardBE1 <= 1;
SSAluInB1 <= WriteData3_2;
end
end
endmodule
| 8.116127 |
module data_forward_b (
input [4:0] WriteRegE,
RsD,
RtD,
input RegWriteE,
BranchD,
BranchNot,
output reg ForwardAD,
ForwardBD
);
always @(*) begin
//default case: direct values in muxes
ForwardAD <= 0;
ForwardBD <= 0;
//IF RSD AND RTD ARE EQUAL TO WRITEREGE AND BRANCHD, ENABLE FORWARDS
if ((RegWriteE) && (BranchD || BranchNot) && (WriteRegE != 0) && (WriteRegE == RsD))
ForwardAD <= 1;
if ((RegWriteE) && (BranchD || BranchNot) && (WriteRegE != 0) && (WriteRegE == RtD))
ForwardBD <= 1;
end
endmodule
| 8.771124 |
module ss_decode (
input clk,
input [3:0] BCD,
output [7:0] sseg_o
);
reg [7:0] sseg = 8'b11111111;
always @(posedge clk) begin
case (BCD)
4'b0000: sseg <= 8'b11000000; //00000011;
4'b0001: sseg <= 8'b11111001; //10011111;
4'b0010: sseg <= 8'b10100100; //00100101;
4'b0011: sseg <= 8'b10110000; //00001101;
4'b0100: sseg <= 8'b10011001; //10011001;
4'b0101: sseg <= 8'b10010010; //01001001;
4'b0110: sseg <= 8'b10000010; //01000001;
4'b0111: sseg <= 8'b11111000; //00011111;
4'b1000: sseg <= 8'b10000000; //00000001;
4'b1001: sseg <= 8'b10010000; //00001001;
default sseg <= 8'b11111111;
endcase
end
assign sseg_o = sseg;
endmodule
| 6.916481 |
module ss_disp (
bcd,
seg
);
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
always @(bcd) begin
case (bcd)
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg = 7'b1001100;
5: seg = 7'b0100100;
6: seg = 7'b0100000;
7: seg = 7'b0001111;
8: seg = 7'b0000000;
9: seg = 7'b0000100;
default: seg = 7'b1111111;
endcase
end
endmodule
| 7.335569 |
module ss_drive (
input clk,
rst,
input [3:0] data7,
data6,
data5,
data4,
input [3:0] data3,
data2,
data1,
data0,
input [7:0] mask,
output ssA,
ssB,
ssC,
ssD,
output ssE,
ssF,
ssG,
ssDP,
output reg AN7,
AN6,
AN5,
AN4,
output reg AN3,
AN2,
AN1,
AN0
);
reg [2:0] sel;
reg [3:0] data;
integer cnt;
always @(posedge clk or posedge rst)
if (rst) begin
cnt <= 0;
sel <= 3'b000;
end else if (cnt < 20000) begin
cnt <= cnt + 1;
sel <= sel;
end else begin
cnt <= 0;
sel <= sel + 1;
end
always @(data7, data6, data5, data4, data3, data2, data1, data0, sel, mask) begin
{AN7, AN6, AN5, AN4, AN3, AN2, AN1, AN0} = 8'b1111_1111;
case (sel)
3'b000: begin
data = data0;
AN0 = 0 | (~mask[0]);
end
3'b001: begin
data = data1;
AN1 = 0 | (~mask[1]);
end
3'b010: begin
data = data2;
AN2 = 0 | (~mask[2]);
end
3'b011: begin
data = data3;
AN3 = 0 | (~mask[3]);
end
3'b100: begin
data = data4;
AN4 = 0 | (~mask[4]);
end
3'b101: begin
data = data5;
AN5 = 0 | (~mask[5]);
end
3'b110: begin
data = data6;
AN6 = 0 | (~mask[6]);
end
default: begin
data = data7;
AN7 = 0 | (~mask[7]);
end
endcase
end
ss_decoder data_decode (
.Din(data),
.a (ssA),
.b (ssB),
.c (ssC),
.d (ssD),
.e (ssE),
.f (ssF),
.g (ssG),
.dp (ssDP)
);
endmodule
| 7.226071 |
module SS_Driver (
input Clk,
Reset,
input [3:0] BCD3,
BCD2,
BCD1,
BCD0, // Binary-coded decimal input 1
input [3:0] BCD7,
BCD6,
BCD5,
BCD4, // Binary-coded decimal input 2
output reg [7:0] SegmentDrivers, // Digit drivers (active low)
output reg [7:0] SevenSegment // Segments (active low)
);
// Make use of a subcircuit to decode the BCD to seven-segment (SS)
wire [6:0] SS[7:0];
BCD_Decoder BCD_Decoder0 (
BCD0,
SS[0]
);
BCD_Decoder BCD_Decoder1 (
BCD1,
SS[1]
);
BCD_Decoder BCD_Decoder2 (
BCD2,
SS[2]
);
BCD_Decoder BCD_Decoder3 (
BCD3,
SS[3]
);
BCD_Decoder BCD_Decoder4 (
BCD4,
SS[4]
);
BCD_Decoder BCD_Decoder5 (
BCD5,
SS[5]
);
BCD_Decoder BCD_Decoder6 (
BCD6,
SS[6]
);
BCD_Decoder BCD_Decoder7 (
BCD7,
SS[7]
);
// Counter to reduce the 100 MHz clock to 762.939 Hz (100 MHz / 2^17)
reg [16:0] Count; //16
// Scroll through the digits, switching one on at a time
always @(posedge Clk) begin
Count <= Count + 1'b1;
if (Reset) SegmentDrivers <= 8'hFE;
else if (&Count) SegmentDrivers <= {SegmentDrivers[6:0], SegmentDrivers[7]};
end
//------------------------------------------------------------------------------
always @(*) begin // This describes a purely combinational circuit
SevenSegment[7] <= 1'b1; // Decimal point always off
if (Reset) begin
SevenSegment[6:0] <= 7'hE; // All off during Reset
end else begin
case (~SegmentDrivers) // Connect the correct signals,
8'h1: SevenSegment[6:0] <= ~SS[0]; // depending on which digit is on at
8'h2: SevenSegment[6:0] <= ~SS[1]; // this point
8'h4: SevenSegment[6:0] <= ~SS[2];
8'h8: SevenSegment[6:0] <= ~SS[3];
8'h10: SevenSegment[6:0] <= ~SS[4];
8'h20: SevenSegment[6:0] <= ~SS[5];
8'h40: SevenSegment[6:0] <= ~SS[6];
8'h80: SevenSegment[6:0] <= ~SS[7];
default: SevenSegment[6:0] <= 7'h7F; //change back after test: 7'h7F;
endcase
end
end
endmodule
| 6.888374 |
module SS_MOVAVG (
IN,
AVG,
CLK,
INIT
);
parameter W = 1000;
parameter N = 16;
parameter F_sampling = 5;
input IN;
input CLK, INIT;
output [N-1:0] AVG;
reg [W-1:0] BUFFER = 1'b0 - 1'b1;
reg [ 7:0] sampleCOUNTER = 8'd0;
always @(posedge CLK) begin
if (sampleCOUNTER < F_sampling) begin
sampleCOUNTER <= sampleCOUNTER + 1'b1;
BUFFER <= BUFFER;
end else begin
sampleCOUNTER <= 1'b0;
BUFFER <= {IN, BUFFER[W-1:1]};
end
end
M_SIDEADD SIDEADD0 (
.EN (1'b1),
.IN (BUFFER),
.OUT(AVG)
);
defparam SIDEADD0.N_inputs = W; defparam SIDEADD0.NB_out = N;
endmodule
| 6.81602 |
module ss_mux (
input clk,
input [31:0] bcd,
input [7:0] dots,
output [7:0] ss_value,
output [7:0] ss_select
);
/*
* Los siguientes parámetros locales representan el "estado" de nuestro módulo,
* en el cual cada uno de ellos está asociado a la activación de un solo dígito
* del display. Nótese que convenientemente están representados con una codificación
* "one-hot", pues se usarán como salida en la señal ss_select.
*/
localparam DIG_0 = 8'b00000001;
localparam DIG_1 = 8'b00000010;
localparam DIG_2 = 8'b00000100;
localparam DIG_3 = 8'b00001000;
localparam DIG_4 = 8'b00010000;
localparam DIG_5 = 8'b00100000;
localparam DIG_6 = 8'b01000000;
localparam DIG_7 = 8'b10000000;
reg [7:0] ss_select_q; // Contiene el estado actual
reg [7:0] ss_select_d; // Contiene el estado siguiente
/* dot_enable nos indica si hay que encender el LED del punto (DP) según el estado actual */
wire dot_enable;
assign dot_enable = |(ss_select_q & dots);
/*
* Instanciamos el conversor de BCD a 7 segmentos
*/
reg [3:0] bcd_nibble;
wire [6:0] ss_digits;
bcd_to_ss to_ss (
.bcd_in(bcd_nibble),
.out(ss_digits)
);
/* Salidas del módulo, en lógica inversa (active LOW) */
assign ss_value = {~dot_enable, ss_digits};
assign ss_select = ~ss_select_q;
/*
* En el siguiente bloque combinacional, asignamos el estado siguiente (ss_select_d)
* y el valor a mostrar, según el estado actual (ss_select_q)
*/
always @(*) begin
case (ss_select_q)
DIG_0: begin
// En este caso (DIG_0) haremos que el conversor a 7 segmentos tome y
// muestre el primer dígito (bcd[3:0]) en el display, y luego defina el
// estado siguiente (DIG_1)
bcd_nibble = bcd[3:0];
ss_select_d = DIG_1;
end
DIG_1: begin
bcd_nibble = bcd[7:4];
ss_select_d = DIG_2;
end
DIG_2: begin
bcd_nibble = bcd[11:8];
ss_select_d = DIG_3;
end
DIG_3: begin
bcd_nibble = bcd[15:12];
ss_select_d = DIG_4;
end
DIG_4: begin
bcd_nibble = bcd[19:16];
ss_select_d = DIG_5;
end
DIG_5: begin
bcd_nibble = bcd[23:20];
ss_select_d = DIG_6;
end
DIG_6: begin
bcd_nibble = bcd[27:24];
ss_select_d = DIG_7;
end
DIG_7: begin
// En este caso (DIG_7), se muestra el último dígito (de más a la izquierda) y
// para el estado siguiente comience nuevamente a mostrar primer dígito (DIG_0)
bcd_nibble = bcd[31:28];
ss_select_d = DIG_0;
end
default: begin
// Por razones de buenas prácticas se tiene un estado por defecto, pese a que
// aparentemente "no debería" ocurrir en este diseño :)
bcd_nibble = bcd[31:28];
ss_select_d = DIG_0;
end
endcase
end
/* Actualizamos al estado siguiente si la señal clk_enable está en alto */
always @(posedge clk) ss_select_q <= ss_select_d;
endmodule
| 7.543549 |
module SS_OCT_SOPC_reset_clk_50_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 6.920192 |
module sgdma_tx_out_arbitrator (
// inputs:
clk,
reset_n,
sgdma_tx_out_data,
sgdma_tx_out_empty,
sgdma_tx_out_endofpacket,
sgdma_tx_out_error,
sgdma_tx_out_startofpacket,
sgdma_tx_out_valid,
tse_mac_transmit_ready_from_sa,
// outputs:
sgdma_tx_out_ready
);
output sgdma_tx_out_ready;
input clk;
input reset_n;
input [31:0] sgdma_tx_out_data;
input [1:0] sgdma_tx_out_empty;
input sgdma_tx_out_endofpacket;
input sgdma_tx_out_error;
input sgdma_tx_out_startofpacket;
input sgdma_tx_out_valid;
input tse_mac_transmit_ready_from_sa;
wire sgdma_tx_out_ready;
//mux sgdma_tx_out_ready, which is an e_mux
assign sgdma_tx_out_ready = tse_mac_transmit_ready_from_sa;
endmodule
| 7.131253 |
module tse_mac_transmit_arbitrator (
// inputs:
clk,
reset_n,
sgdma_tx_out_data,
sgdma_tx_out_empty,
sgdma_tx_out_endofpacket,
sgdma_tx_out_error,
sgdma_tx_out_startofpacket,
sgdma_tx_out_valid,
tse_mac_transmit_ready,
// outputs:
tse_mac_transmit_data,
tse_mac_transmit_empty,
tse_mac_transmit_endofpacket,
tse_mac_transmit_error,
tse_mac_transmit_ready_from_sa,
tse_mac_transmit_startofpacket,
tse_mac_transmit_valid
);
output [31:0] tse_mac_transmit_data;
output [1:0] tse_mac_transmit_empty;
output tse_mac_transmit_endofpacket;
output tse_mac_transmit_error;
output tse_mac_transmit_ready_from_sa;
output tse_mac_transmit_startofpacket;
output tse_mac_transmit_valid;
input clk;
input reset_n;
input [31:0] sgdma_tx_out_data;
input [1:0] sgdma_tx_out_empty;
input sgdma_tx_out_endofpacket;
input sgdma_tx_out_error;
input sgdma_tx_out_startofpacket;
input sgdma_tx_out_valid;
input tse_mac_transmit_ready;
wire [31:0] tse_mac_transmit_data;
wire [ 1:0] tse_mac_transmit_empty;
wire tse_mac_transmit_endofpacket;
wire tse_mac_transmit_error;
wire tse_mac_transmit_ready_from_sa;
wire tse_mac_transmit_startofpacket;
wire tse_mac_transmit_valid;
//mux tse_mac_transmit_data, which is an e_mux
assign tse_mac_transmit_data = sgdma_tx_out_data;
//mux tse_mac_transmit_endofpacket, which is an e_mux
assign tse_mac_transmit_endofpacket = sgdma_tx_out_endofpacket;
//mux tse_mac_transmit_error, which is an e_mux
assign tse_mac_transmit_error = sgdma_tx_out_error;
//mux tse_mac_transmit_empty, which is an e_mux
assign tse_mac_transmit_empty = sgdma_tx_out_empty;
//assign tse_mac_transmit_ready_from_sa = tse_mac_transmit_ready so that symbol knows where to group signals which may go to master only, which is an e_assign
assign tse_mac_transmit_ready_from_sa = tse_mac_transmit_ready;
//mux tse_mac_transmit_startofpacket, which is an e_mux
assign tse_mac_transmit_startofpacket = sgdma_tx_out_startofpacket;
//mux tse_mac_transmit_valid, which is an e_mux
assign tse_mac_transmit_valid = sgdma_tx_out_valid;
endmodule
| 6.631183 |
module tse_mac_receive_arbitrator (
// inputs:
clk,
reset_n,
sgdma_rx_in_ready_from_sa,
tse_mac_receive_data,
tse_mac_receive_empty,
tse_mac_receive_endofpacket,
tse_mac_receive_error,
tse_mac_receive_startofpacket,
tse_mac_receive_valid,
// outputs:
tse_mac_receive_ready
);
output tse_mac_receive_ready;
input clk;
input reset_n;
input sgdma_rx_in_ready_from_sa;
input [31:0] tse_mac_receive_data;
input [1:0] tse_mac_receive_empty;
input tse_mac_receive_endofpacket;
input [5:0] tse_mac_receive_error;
input tse_mac_receive_startofpacket;
input tse_mac_receive_valid;
wire tse_mac_receive_ready;
//mux tse_mac_receive_ready, which is an e_mux
assign tse_mac_receive_ready = sgdma_rx_in_ready_from_sa;
endmodule
| 7.122298 |
module SS_OCT_SOPC_reset_ddr2_phy_clk_out_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 6.920192 |
module SS_OCT_SOPC_reset_pll_sys_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 6.920192 |
module ext_flash_lane0_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [24:0] rdaddress;
input rdclken;
input [24:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [33554431:0];
wire [ 7:0] q;
reg [24:0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress) begin
read_address = rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial $readmemh("ext_flash_lane0.dat", mem_array);
always @(posedge wrclock) begin
// Write data
if (wren) mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "ext_flash_lane0.mif",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 8,
// lpm_ram_dp_component.lpm_widthad = 25,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.952907 |
module ext_flash_lane1_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [7:0] q;
input [7:0] data;
input [24:0] rdaddress;
input rdclken;
input [24:0] wraddress;
input wrclock;
input wren;
reg [ 7:0] mem_array [33554431:0];
wire [ 7:0] q;
reg [24:0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress) begin
read_address = rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial $readmemh("ext_flash_lane1.dat", mem_array);
always @(posedge wrclock) begin
// Write data
if (wren) mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "ext_flash_lane1.mif",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 8,
// lpm_ram_dp_component.lpm_widthad = 25,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.952907 |
module ext_flash (
// inputs:
address,
read_n,
select_n,
write_n,
// outputs:
data
);
inout [15:0] data;
input [24:0] address;
input read_n;
input select_n;
input write_n;
wire [15:0] data;
wire [ 7:0] data_0;
wire [ 7:0] data_1;
wire [15:0] logic_vector_gasket;
wire [ 7:0] q_0;
wire [ 7:0] q_1;
//s1, which is an e_ptf_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign logic_vector_gasket = data;
assign data_0 = logic_vector_gasket[7 : 0];
//ext_flash_lane0, which is an e_ram
ext_flash_lane0_module ext_flash_lane0 (
.data (data_0),
.q (q_0),
.rdaddress(address),
.rdclken (1'b1),
.wraddress(address),
.wrclock (write_n),
.wren (~select_n)
);
assign data_1 = logic_vector_gasket[15 : 8];
//ext_flash_lane1, which is an e_ram
ext_flash_lane1_module ext_flash_lane1 (
.data (data_1),
.q (q_1),
.rdaddress(address),
.rdclken (1'b1),
.wraddress(address),
.wrclock (write_n),
.wren (~select_n)
);
assign data = (~select_n & ~read_n) ? {q_1, q_0} : {16{1'bz}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.719908 |
module SS_OCT_SOPC_clock_0_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_0_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n) begin
if (reset_clk1_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n) begin
if (reset_clk2_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_1_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_1_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n) begin
if (reset_clk1_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n) begin
if (reset_clk2_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_2_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
| 7.008946 |
module SS_OCT_SOPC_clock_2_bit_pipe (
// inputs:
clk1,
clk2,
data_in,
reset_clk1_n,
reset_clk2_n,
// outputs:
data_out
);
output data_out;
input clk1;
input clk2;
input data_in;
input reset_clk1_n;
input reset_clk2_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-to \"*\"} CUT=ON ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk1 or negedge reset_clk1_n) begin
if (reset_clk1_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk2 or negedge reset_clk2_n) begin
if (reset_clk2_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.008946 |
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