code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module OAI22B2LEHMX2 (
O,
A1,
A2,
B1B,
B2B
);
output O;
input A1, A2, B1B, B2B;
wire o2;
wire o1;
or g1 (o1, A1, A2);
nand g2 (o2, B1B, B2B);
nand g3 (O, o1, o2);
endmodule
| 7.003483 |
module OAI22B2LEHMX3 (
O,
A1,
A2,
B1B,
B2B
);
output O;
input A1, A2, B1B, B2B;
wire o2;
wire o1;
or g1 (o1, A1, A2);
nand g2 (o2, B1B, B2B);
nand g3 (O, o1, o2);
endmodule
| 7.100676 |
module OAI22LEHMX1 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
or g1 (o1, B1, B2);
or g2 (o2, A1, A2);
nand g3 (O, o1, o2);
endmodule
| 7.247224 |
module OAI22LEHMX2 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
or g1 (o1, B1, B2);
or g2 (o2, A1, A2);
nand g3 (O, o1, o2);
endmodule
| 7.345724 |
module OAI22LEHMX3 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
or g1 (o1, B1, B2);
or g2 (o2, A1, A2);
nand g3 (O, o1, o2);
endmodule
| 7.443579 |
module OAI22LEHMX4 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
or g1 (o1, B1, B2);
or g2 (o2, A1, A2);
nand g3 (O, o1, o2);
endmodule
| 7.173528 |
module OAI22LEHMX6 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
or g1 (o1, B1, B2);
or g2 (o2, A1, A2);
nand g3 (O, o1, o2);
endmodule
| 7.28557 |
module OAI22M2HLEHMX4 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
or g1 (o1, B1, B2);
or g2 (o2, A1, A2);
nand g3 (O, o1, o2);
endmodule
| 7.15427 |
module OAI22M2HLEHMX6 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
or g1 (o1, B1, B2);
or g2 (o2, A1, A2);
nand g3 (O, o1, o2);
endmodule
| 7.15427 |
module OAI22M2HLEHMX8 (
O,
A1,
A2,
B1,
B2
);
output O;
input A1, A2, B1, B2;
wire o2;
wire o1;
or g1 (o1, B1, B2);
or g2 (o2, A1, A2);
nand g3 (O, o1, o2);
endmodule
| 7.15427 |
module OR2B1LEHMX1 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
or g1 (O, I1, i2);
not g2 (i2, B1);
endmodule
| 8.030419 |
module OR2B1LEHMX2 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
or g1 (O, I1, i2);
not g2 (i2, B1);
endmodule
| 8.005804 |
module OR2B1LEHMX3 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
or g1 (O, I1, i2);
not g2 (i2, B1);
endmodule
| 8.141863 |
module OR2B1LEHMX4 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
or g1 (O, I1, i2);
not g2 (i2, B1);
endmodule
| 8.023997 |
module OR2B1LEHMX6 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
or g1 (O, I1, i2);
not g2 (i2, B1);
endmodule
| 8.026357 |
module OR2B1LEHMX8 (
O,
I1,
B1
);
output O;
input I1, B1;
wire i2;
or g1 (O, I1, i2);
not g2 (i2, B1);
endmodule
| 8.077847 |
module OR2CKLEHMX1 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 7.224268 |
module OR2CKLEHMX2 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 7.140968 |
module OR2CKLEHMX3 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 7.159892 |
module OR2CKLEHMX4 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 6.94115 |
module OR2CKLEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 7.224779 |
module OR2CKLEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 7.109488 |
module OR2LEHMX1 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 7.521104 |
module OR2LEHMX2 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 7.418378 |
module OR2LEHMX3 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 7.49442 |
module OR2LEHMX4 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 7.150072 |
module OR2LEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 7.395071 |
module OR2LEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
or g1 (O, I1, I2);
endmodule
| 7.436099 |
module OR3B1LEHMX1 (
O,
I1,
I2,
B1
);
output O;
input I1, I2, B1;
wire i3;
or3 g1 (
O,
I1,
I2,
i3
);
not g2 (i3, B1);
endmodule
| 7.966789 |
module OR3B1LEHMX2 (
O,
I1,
I2,
B1
);
output O;
input I1, I2, B1;
wire i3;
or3 g1 (
O,
I1,
I2,
i3
);
not g2 (i3, B1);
endmodule
| 8.023574 |
module OR3B1LEHMX3 (
O,
I1,
I2,
B1
);
output O;
input I1, I2, B1;
wire i3;
or3 g1 (
O,
I1,
I2,
i3
);
not g2 (i3, B1);
endmodule
| 7.993119 |
module OR3LEHMX1 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
or3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 7.28661 |
module OR3LEHMX2 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
or3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 7.439577 |
module OR3LEHMX3 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
or3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 7.198689 |
module OR3LEHMX4 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
or3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 7.404109 |
module OR3LEHMX6 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
or3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 7.135068 |
module OR3LEHMX8 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
or3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 7.04643 |
module OR4LEHMX1 (
O,
I1,
I2,
I3,
I4
);
output O;
input I1, I2, I3, I4;
or4 g1 (
O,
I1,
I2,
I3,
I4
);
endmodule
| 7.317507 |
module OR4LEHMX2 (
O,
I1,
I2,
I3,
I4
);
output O;
input I1, I2, I3, I4;
or4 g1 (
O,
I1,
I2,
I3,
I4
);
endmodule
| 7.458896 |
module OR4LEHMX3 (
O,
I1,
I2,
I3,
I4
);
output O;
input I1, I2, I3, I4;
or4 g1 (
O,
I1,
I2,
I3,
I4
);
endmodule
| 7.487126 |
module QBDFCRBNLEHMX1 (
QB,
D,
CK,
RB
);
wire flag;
assign flag = 0; // Notifier flag
output QB;
input D, CK, RB;
wire vcc;
assign vcc = 1;
wire d_CK, d_D, d_RB;
//Function Block
wire Q;
wire qt;
wire d1;
buf g3 (Q, qt);
not g1 (QB, qt);
dffrsb_udp5 g2 (
qt,
d... | 6.536336 |
module QBDFCRBNLEHMX2 (
QB,
D,
CK,
RB
);
wire flag;
assign flag = 0;
output QB;
input D, CK, RB;
wire vcc;
assign vcc = 1;
wire d_CK, d_D, d_RB;
wire qt;
wire d1;
not g1 (QB, qt);
dffrsb_udp5 g2 (
qt,
d1,
d_CK,
vcc,
vcc,
flag
);
and g4 (d... | 6.536336 |
module QBDFCRBNLEHMX3 (
QB,
D,
CK,
RB
);
wire flag;
assign flag = 0; // Notifier flag
output QB;
input D, CK, RB;
wire vcc;
assign vcc = 1;
wire d_CK, d_D, d_RB;
//Function Block
wire Q;
wire qt;
wire d1;
buf g3 (Q, qt);
not g1 (QB, qt);
dffrsb_udp5 g2 (
qt,
d... | 6.536336 |
module QBDFFRBNLEHMX1 (
QB,
D,
CK,
RB
);
wire flag;
assign flag = 0; // Notifier flag
output QB;
input D, CK, RB;
wire vcc;
assign vcc = 1;
// wire D_flag;
// wire D_flag1;
wire d_CK, d_D;
//Function Block
wire qt;
not g3 (QB, qt);
dffrsb_udp5 g2 (
qt,
d_D,... | 7.036597 |
module QBDFFRBNLEHMX2 (
QB,
D,
CK,
RB
);
wire flag;
assign flag = 0; // Notifier flag
output QB;
input D, CK, RB;
wire vcc;
assign vcc = 1;
// wire D_flag;
// wire D_flag1;
wire d_CK, d_D;
//Function Block
wire qt;
not g3 (QB, qt);
dffrsb_udp5 g2 (
qt,
d_D,... | 7.036597 |
module QBDFFRBNLEHMX3 (
QB,
D,
CK,
RB
);
wire flag;
assign flag = 0; // Notifier flag
output QB;
input D, CK, RB;
wire vcc;
assign vcc = 1;
// wire D_flag;
// wire D_flag1;
wire d_CK, d_D;
//Function Block
wire qt;
not g3 (QB, qt);
dffrsb_udp5 g2 (
qt,
d_D,... | 7.036597 |
module QBDFZNLEHMX1 (
QB,
D,
TD,
CK,
SEL
);
wire flag;
assign flag = 0; // Notifier flag
output QB;
input D, CK, TD, SEL;
wire vcc;
assign vcc = 1;
wire d_CK, d_D, d_TD, d_SEL;
//Function Block
wire qt;
wire d1;
not g3 (QB, qt);
dffrsb_udp5 g2 (
qt,
d1,
... | 6.608845 |
module QBDFZNLEHMX3 (
QB,
D,
TD,
CK,
SEL
);
wire flag;
assign flag = 0; // Notifier flag
output QB;
input D, CK, TD, SEL;
wire vcc;
assign vcc = 1;
wire d_CK, d_D, d_TD, d_SEL;
//Function Block
wire qt;
wire d1;
not g3 (QB, qt);
dffrsb_udp5 g2 (
qt,
d1,
... | 6.624525 |
module QDFCRBNLEHMX3 (
Q,
D,
CK,
RB
);
wire flag;
assign flag = 0; // Notifier flag
output Q;
input D, CK, RB;
wire vcc;
assign vcc = 1;
wire d_CK, d_D, d_RB;
//Function Block
wire qt;
wire d1;
buf b1 (Q, qt);
dffrsb_udp5 g1 (
qt,
d1,
d_CK,
vcc,
... | 6.59974 |
module XNR2CKLEHMX1 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.0583 |
module XNR2CKLEHMX2 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.025043 |
module XNR2CKLEHMX3 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.029214 |
module XNR2CKLEHMX4 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 6.671191 |
module XNR2CKLEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.027207 |
module XNR2CKLEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 6.917226 |
module XNR2LEHMX1 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.49296 |
module XNR2LEHMX2 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.544412 |
module XNR2LEHMX3 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.307924 |
module XNR2LEHMX4 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.078412 |
module XNR2LEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.332055 |
module XNR2LEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.512817 |
module XNR2M2HLEHMX10 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.352132 |
module XNR2M2HLEHMX12 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.352132 |
module XNR2M2HLEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.336696 |
module XNR2M2HLEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
xnor g1 (O, I1, I2);
endmodule
| 7.336765 |
module XNR3LEHMX1 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
xnor3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 6.881636 |
module XNR3LEHMX2 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
xnor3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 7.079761 |
module XNR3LEHMX3 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
xnor3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 6.893378 |
module XOR2CKLEHMX1 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.45463 |
module XOR2CKLEHMX2 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.302111 |
module XOR2CKLEHMX3 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.394683 |
module XOR2CKLEHMX4 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.014755 |
module XOR2CKLEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.219759 |
module XOR2CKLEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.078365 |
module XOR2LEHMX1 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.63686 |
module XOR2LEHMX2 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.444102 |
module XOR2LEHMX3 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.667779 |
module XOR2LEHMX4 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.233359 |
module XOR2LEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.40121 |
module XOR2LEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.415751 |
module XOR2M2HLEHMX10 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.665774 |
module XOR2M2HLEHMX12 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.665774 |
module XOR2M2HLEHMX6 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.626159 |
module XOR2M2HLEHMX8 (
O,
I1,
I2
);
output O;
input I1, I2;
xor g1 (O, I1, I2);
endmodule
| 7.401953 |
module XOR3LEHMX1 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
xor3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 7.756708 |
module XOR3LEHMX2 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
xor3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 7.711819 |
module XOR3LEHMX3 (
O,
I1,
I2,
I3
);
output O;
input I1, I2, I3;
xor3 g1 (
O,
I1,
I2,
I3
);
endmodule
| 7.57561 |
module GTECH_AND2 (
A,
B,
Z
);
output Z;
input A, B;
and g1 (Z, A, B);
endmodule
| 6.80074 |
module GTECH_AND3 (
A,
B,
C,
Z
);
output Z;
input A, B, C;
and3 g1 (
Z,
A,
B,
C
);
endmodule
| 6.751779 |
module GTECH_AND4 (
A,
B,
C,
D,
Z
);
output Z;
input A, B, C, D;
and4 g1 (
Z,
A,
B,
C,
D
);
endmodule
| 6.848117 |
module GTECH_OR2 (
A,
B,
Z
);
output Z;
input A, B;
or g1 (Z, A, B);
endmodule
| 7.221424 |
module GTECH_XOR2 (
A,
B,
Z
);
output Z;
input A, B;
xor g1 (Z, A, B);
endmodule
| 7.157738 |
module GTECH_BUF (
A,
Z
);
output Z;
input A;
assign Z = A;
endmodule
| 7.604895 |
module steck (
input wire clk,
input wire [3:0] wea,
input wire [31:0] dina,
input wire ena,
output reg [31:0] douta,
input wire [31:0] addra,
output reg [31:0] doutb,
input wire enb,
input wire [31:0] addrb
);
//simle write first dual port ram
parameter data_mem_size_in_bits ... | 7.848697 |
module steerA (
output [1:0] Ss,
input SCOMP,
output [1:0] Ts,
input TCOMP,
output [1:0] Us,
input UCOMP,
output [1:0] Vs,
input VCOMP,
input [1:0] A,
output ACOMP,
input [3:0] steerin,
output steerinCOMP,
output [3:0] steerout,
input steeroutCOMP,
input init
... | 7.95506 |
module steerC (
output [1:0] Ss,
input SCOMP,
output [1:0] Ts,
input TCOMP,
output [1:0] Us,
input UCOMP,
output [1:0] Vs,
input VCOMP,
input [1:0] A,
output ACOMP,
input [3:0] steerin,
output steerinCOMP,
output [3:0] steerout,
input steeroutCOMP,
input init
... | 6.954747 |
module steerF (
output [1:0] Ss,
output [1:0] Ts,
output [1:0] Us,
output [1:0] Vs,
input [1:0] A,
input [3:0] steerin,
output [3:0] steerout
);
// 4 way steer component
TH22 stu14 (
Ss[0],
A[0],
steerin[0]
);
TH22 stu24 (
Ss[1],
A[1],
steerin[... | 6.658082 |
module step1_sr (
input S,
R,
output Q,
Q_n
);
assign Q = ~(R | Q_n);
assign Q_n = ~(S | Q);
endmodule
| 6.502857 |
module step2_dff (
input clk,
rst,
input [3:0] din,
output reg [3:0] dout
);
always @(posedge clk or posedge rst) begin
if (rst) dout <= 4'b0;
else dout <= din;
end
endmodule
| 7.061126 |
module top (
input [7:0] sw,
output [7:0] led
);
assign led = sw;
endmodule
| 7.233807 |
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