code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_4 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_5 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_6 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_7 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_8 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_9 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u1u1u1_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input in3, in2, in1;
output [1:0] out1;
wire [1:0] asc001;
wire [1:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u1u1u1_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input in3, in2, in1;
output [1:0] out1;
wire [1:0] asc001;
wire [1:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u1u1u1_4_0 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input in3, in2, in1;
output [1:0] out1;
wire [1:0] asc001;
wire [1:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u1u1u1_4_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input in3, in2, in1;
output [1:0] out1;
wire [1:0] asc001;
wire [1:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u32u32u32_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_0 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_1 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_1_0 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
wire [15:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_0 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_1 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_10 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_11 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_12 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
wire [15:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_13 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
wire [15:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_14 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
wire [15:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_15 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
wire [15:0] asc001_tmp_0;
wire [15:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_2 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_3 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_4 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_5 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_6 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_7 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_8 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3u8u8Subu16u16_4_9 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2, in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
wire [17:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) - (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_1 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_0 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_1 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_10 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_2 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_3 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_4 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_5 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_6 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_7 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_8 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_9 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in9, in8, in7, in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in5 * in6);
assign asc003 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
assign asc001_tmp_2 = +(in9);
assign asc001_tmp_1 = asc001_tmp_2 + (in7 * in8);
assign asc001_tmp_0 = asc001_tmp_1 + (asc002 * in4);
assign asc001 = asc001_tmp_0 + (asc003 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4u1u1u1u1_1 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input in4, in3, in2, in1;
output [2:0] out1;
wire [2:0] asc001;
wire [2:0] asc001_tmp_0;
wire [2:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) + (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4u1u1u1u1_4 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input in4, in3, in2, in1;
output [2:0] out1;
wire [2:0] asc001;
wire [2:0] asc001_tmp_0;
wire [2:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) + (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4u1u1u1u1_4_0 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input in4, in3, in2, in1;
output [2:0] out1;
wire [2:0] asc001;
wire [2:0] asc001_tmp_0;
wire [2:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) + (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4u1u1u1u1_4_1 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input in4, in3, in2, in1;
output [2:0] out1;
wire [2:0] asc001;
wire [2:0] asc001_tmp_0;
wire [2:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) + (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add4u32u32u32u32_4 (
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in4) + (in3);
assign asc001_tmp_0 = asc001_tmp_1 + (in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_1 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_0 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_1 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_10 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_2 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_3 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_4 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_5 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_6 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_7 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_8 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add5u32Mul3u16u16u16Mul3u16u16u16Mul2u16u16u16_4_9 (
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in10, in9, in8, in7, in6, in5, in4, in3, in2;
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001, asc002, asc003;
assign asc002 = +(in6 * in7);
assign asc003 = +(in3 * in4);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
wire [31:0] asc001_tmp_2;
wire [31:0] asc001_tmp_3;
assign asc001_tmp_3 = +(in10);
assign asc001_tmp_2 = asc001_tmp_3 + (in8 * in9);
assign asc001_tmp_1 = asc001_tmp_2 + (asc002 * in5);
assign asc001_tmp_0 = asc001_tmp_1 + (asc003 * in2);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Sx9U_16S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Sx9U_16S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Sx9U_16S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Sx9U_16S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Sx9U_16S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux1U_16U_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_10 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_11 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_12 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_13 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_14 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_5 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_6 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_7 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_8 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux6U_16U_4_9 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [5:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add_16Ux8U_16U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.57659 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.