code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module st_feature_addr_gen_GtSubi1Add2u8u16u16_4_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input [7:0] in1;
output out1;
wire asc001;
wire [18:0] asc002;
wire [17:0] asc003;
wire [17:0] asc003_tmp_0;
assign asc003_tmp_0 = +(in2) + (in1);
assign asc003 = asc003_tmp_0 - (18'B000000000000000001);
assign asc002 = {asc003[17], asc003};
assign asc001 = (in3 > asc002);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_GtSubi1Add2u8u16u16_4_2 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input [7:0] in1;
output out1;
wire asc001;
wire [18:0] asc002;
wire [17:0] asc003;
wire [17:0] asc003_tmp_0;
assign asc003_tmp_0 = +(in2) + (in1);
assign asc003 = asc003_tmp_0 - (18'B000000000000000001);
assign asc002 = {asc003[17], asc003};
assign asc001 = (in3 > asc002);
assign out1 = asc001;
endmodule
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module st_feature_addr_gen_GtSubi1Add2u8u16u16_4_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input [7:0] in1;
output out1;
wire asc001;
wire [18:0] asc002;
wire [17:0] asc003;
wire [17:0] asc003_tmp_0;
assign asc003_tmp_0 = +(in2) + (in1);
assign asc003 = asc003_tmp_0 - (18'B000000000000000001);
assign asc002 = {asc003[17], asc003};
assign asc001 = (in3 > asc002);
assign out1 = asc001;
endmodule
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module st_feature_addr_gen_LessThan_16Ux8U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 > in2);
assign out1 = asc001;
endmodule
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module st_feature_addr_gen_LessThan_16Ux8U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 > in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_LessThan_16Ux8U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 > in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_LessThan_16Ux8U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 > in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_LessThan_16Ux8U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 > in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_LessThan_16Ux8U_1U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 > in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_LessThan_16Ux8U_1U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 > in2);
assign out1 = asc001;
endmodule
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module st_feature_addr_gen_Mul2Add2i1u8u16_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [ 8:0] asc002;
assign asc002 = +(in1) + (9'B000000001);
assign asc001 = +(in2 * asc002);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul2Add2i1u8u16_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [ 8:0] asc002;
assign asc002 = +(in1) + (9'B000000001);
assign asc001 = +(in2 * asc002);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul2Add2i1u8u16_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [ 8:0] asc002;
assign asc002 = +(in1) + (9'B000000001);
assign asc001 = +(in2 * asc002);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul2Add2i1u8u16_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [ 8:0] asc002;
assign asc002 = +(in1) + (9'B000000001);
assign asc001 = +(in2 * asc002);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul2Add2i1u8u16_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [ 8:0] asc002;
assign asc002 = +(in1) + (9'B000000001);
assign asc001 = +(in2 * asc002);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul2Add2i1u8u16_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
wire [ 8:0] asc002;
assign asc002 = +(in1) + (9'B000000001);
assign asc001 = +(in2 * asc002);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul3u16u16u16_4_0 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
assign asc001 = +(asc002 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux16U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux16U_16U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux16U_32U_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux16U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux16U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux16U_32U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux16U_32U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux8U_16U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux8U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux8U_16U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux8U_16U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux8U_16U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux8U_16U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux8U_16U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux9U_16U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux9U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux9U_16U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux9U_16U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux9U_16U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux9U_16U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16Ux9U_16U_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [8:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16U_19_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16U_19_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_16U_19_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1 * in2);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_32Ux16U_32U_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_32Ux16U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Mul_32Ux16U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2 * in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_MuxAdd2i1u16u16u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_MuxAdd2i1u16u16u1_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_MuxAdd2i1u16u16u1_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_MuxAdd2i1u16u16u1_4_2 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_MuxAdd3i1u8u16u16u1_1 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [15:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in3) + (in2);
assign asc002 = asc002_tmp_0 + (16'B0000000000000001);
reg [15:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002 or in4) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = in4;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_MuxAdd3i1u8u16u16u1_4 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [15:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in3) + (in2);
assign asc002 = asc002_tmp_0 + (16'B0000000000000001);
reg [15:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002 or in4) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = in4;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_MuxAdd3i1u8u16u16u1_4_0 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [15:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in3) + (in2);
assign asc002 = asc002_tmp_0 + (16'B0000000000000001);
reg [15:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002 or in4) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = in4;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_MuxAdd3i1u8u16u16u1_4_1 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [15:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in3) + (in2);
assign asc002 = asc002_tmp_0 + (16'B0000000000000001);
reg [15:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002 or in4) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = in4;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_MuxAdd3i1u8u16u16u1_4_2 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [15:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in3) + (in2);
assign asc002 = asc002_tmp_0 + (16'B0000000000000001);
reg [15:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002 or in4) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = in4;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_MuxAdd3i1u8u16u16u1_4_3 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [15:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in3) + (in2);
assign asc002 = asc002_tmp_0 + (16'B0000000000000001);
reg [15:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002 or in4) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = in4;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_MuxAdd3i1u8u16u16u1_4_4 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
wire [15:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in3) + (in2);
assign asc002 = asc002_tmp_0 + (16'B0000000000000001);
reg [15:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002 or in4) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = in4;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Muxi0Subu8u16u1_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc003;
assign asc003 = +(in3) - (in2);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc003;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Muxi0Subu8u16u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc003;
assign asc003 = +(in3) - (in2);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc003;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Muxi0Subu8u16u1_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc003;
assign asc003 = +(in3) - (in2);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc003;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Muxi0Subu8u16u1_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc003;
assign asc003 = +(in3) - (in2);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc003;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Muxi0Subu8u16u1_4_2 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc003;
assign asc003 = +(in3) - (in2);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc003;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Muxi0Subu8u16u1_4_3 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc003;
assign asc003 = +(in3) - (in2);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc003;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Muxi0Subu8u16u1_4_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3;
input [7:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc003;
assign asc003 = +(in3) - (in2);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc003) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = asc003;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Nei1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Nei1u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Nei1u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Nei1u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (21'B000000000000000000001 == in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_NotEQ_16Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_NotEQ_16Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_NotEQ_16Ux1U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_NotEQ_16Ux1U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Not_1U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Not_1U_1U_4_0 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Not_1U_1U_4_1 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_N_Mux_16_2_24_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_N_Mux_16_2_24_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_N_Mux_16_2_24_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_N_Mux_16_2_24_4_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_N_Mux_16_2_24_4_2 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_N_Mux_16_2_25_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_N_Mux_16_2_25_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_N_Mux_16_2_27_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_N_Mux_16_2_28_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_N_Mux_16_2_28_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_N_Mux_16_2_28_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_OrReduction_4U_1U_1 (
in1,
out1
); /* architecture "behavioural" */
input [3:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_OrReduction_4U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input [3:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_OrReduction_4U_1U_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [3:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_OrReduction_4U_1U_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [3:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_OrReduction_4U_1U_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [3:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_OrReduction_4U_1U_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [3:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_OrReduction_4U_1U_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [3:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Or_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Or_1Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Or_1Ux1U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1Add2u8u16_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1Add2u8u16_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1Add2u8u16_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1Add2u8u16_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1Add2u8u16_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1Add2u8u16_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
wire [17:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in2) + (in1);
assign asc001 = asc001_tmp_0 - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
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