code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module st_feature_addr_gen_Subi1u11_1 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16S_26_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16S_26_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux1U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux1U_17S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux1U_17S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux1U_17S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_22_1 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_22_4 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_22_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_22_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_22_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_23_4 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_23_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
module st_mux_2_to_1 (... | 7.702374 |
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0;... | 8.472603 |
module st_weight_addr_gen_Add2i1u16_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_10 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_11 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_5 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_6 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_7 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_8 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_9 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i32u16_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i32u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i32u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i32u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i32u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = a... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = a... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_0 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 =... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 =... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_10 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 ... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_2 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 =... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_3 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 =... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 =... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_5 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 =... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_6 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 =... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_7 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 =... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_8 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 =... | 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_9 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 =... | 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_1 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
... | 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_0 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0... | 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_1 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0... | 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_10 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_... | 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_2 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0... | 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_3 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0... | 6.57659 |
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