code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module st_feature_addr_gen_Subi1u11_1 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u11_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [10:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in1) - (12'B000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Subi1u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_11Ux1U_12S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [10:0] in2;
input in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16S_26_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16S_26_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux1U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux1U_17S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux1U_17S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux1U_17S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_16S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_16Ux8U_17S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [7:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux1U_18S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_17Ux8U_18S_4_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [7:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_22_1 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_22_4 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_22_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_22_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_22_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_23_4 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module st_feature_addr_gen_Sub_18S_23_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [16:0] in1;
output [17:0] out1;
wire [17:0] asc001;
assign asc001 = +(in1) - (18'B000000000000000001);
assign out1 = asc001;
endmodule
| 6.663606 |
module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
module st_mux_2_to_1 (
input wire clk, // clock.clk
input wire reset, // .reset
input wire [7:0] avs_control_port_address, // control_port.address
input wire avs_control_port_read, // .read
output reg [31:0] avs_control_port_readdata, // .readdata
input wire avs_control_port_write, // .write
input wire [31:0] avs_control_port_writedata, // .writedata
output wire avs_control_port_waitrequest, // .waitrequest
input wire [31:0] asi_sink0_data, // sink0.data
output wire asi_sink0_ready, // .ready
input wire asi_sink0_valid, // .valid
input wire asi_sink0_error, // .error
input wire asi_sink0_startofpacket, // .startofpacket
input wire asi_sink0_endofpacket, // .endofpacket
input wire [1:0] asi_sink0_empty, // .empty
input wire [31:0] asi_sink1_data, // sink1.data
output wire asi_sink1_ready, // .ready
input wire asi_sink1_valid, // .valid
input wire asi_sink1_error, // .error
input wire asi_sink1_startofpacket, // .startofpacket
input wire asi_sink1_endofpacket, // .endofpacket
input wire [1:0] asi_sink1_empty, // .empty
output wire [31:0] aso_source_data, // source.data
input wire aso_source_ready, // .ready
output wire aso_source_valid, // .valid
output wire aso_source_error, // .error
output wire aso_source_startofpacket, // .startofpacket
output wire aso_source_endofpacket, // .endofpacket
output wire [1:0] aso_source_empty // .empty
);
reg sel;
always @ (posedge clk or posedge reset)
begin
if (reset)
sel <= 1'b0;
else if (avs_control_port_write & avs_control_port_address == 32'h0)
sel <= avs_control_port_writedata[0];
end
always @ *
begin
if (avs_control_port_read)
begin
case (avs_control_port_address)
32'h0: avs_control_port_readdata = sel;
default: avs_control_port_readdata = 32'h0;
endcase
end
end
st_mux st_mux_0 (
.data0x ({asi_sink0_data, asi_sink0_valid, asi_sink0_error, asi_sink0_startofpacket, asi_sink0_endofpacket, asi_sink0_empty}),
.data1x ({asi_sink1_data, asi_sink1_valid, asi_sink1_error, asi_sink1_startofpacket, asi_sink1_endofpacket, asi_sink1_empty}),
.sel (sel),
.result ({aso_source_data, aso_source_valid, aso_source_error, aso_source_startofpacket, aso_source_endofpacket, aso_source_empty})
);
assign asi_sink0_ready = aso_source_ready;
assign asi_sink1_ready = aso_source_ready;
endmodule
| 7.702374 |
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @(posedge clk or posedge reset) begin
if (reset) begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end else if (start) begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
barrelshifter_B_d1 <= 0;
end else begin
if (start == 1) begin
barrelshifter_B_d1 <= 0;
end else if (fifo_readack == 1) begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for (
input_offset = 0; input_offset < (DATA_WIDTH / 8); input_offset = input_offset + 1
) begin : barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1) begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end else begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
| 8.472603 |
module st_weight_addr_gen_Add2i1u16_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_10 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_11 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_5 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_6 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_7 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_8 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i1u16_4_9 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i32u16_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i32u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i32u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i32u16_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2i32u16_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000100000);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_0 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_10 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_2 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_3 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_5 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_6 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_7 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_8 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add2Mul2u16u16u16_4_9 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3);
assign asc001 = asc001_tmp_0 + (in1 * in2);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_1 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_0 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_1 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_10 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_2 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
module st_weight_addr_gen_Add3Mul3u16u16u16Mul2u16u16u16_4_3 (
in6,
in5,
in4,
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in6, in5, in4, in3, in2, in1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2 * in3);
wire [31:0] asc001_tmp_0;
wire [31:0] asc001_tmp_1;
assign asc001_tmp_1 = +(in6);
assign asc001_tmp_0 = asc001_tmp_1 + (in4 * in5);
assign asc001 = asc001_tmp_0 + (asc002 * in1);
assign out1 = asc001;
endmodule
| 6.57659 |
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