code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sub_ksa_16b (
A16,
B16,
R16,
COUT_16
);
input [15:0] A16;
input [15:0] B16;
output COUT_16;
output [15:0] R16;
wire [15:0] A16;
wire [15:0] B16;
wire COUT_16;
wire [15:0] R16;
wire [15:0] B16neg;
notgate #(
.DATA_WIDTH(16)
) notgate_inst0 (
.A(B16),
... | 7.004282 |
module sub_mod (
input wire clk,
input wire [23:0] a,
input wire [23:0] b,
output wire [23:0] out
);
reg [24:0] a_sub_b;
always @(posedge clk) a_sub_b <= a - b;
assign out = a_sub_b[23:0] + (a_sub_b[24] ? 24'd12587009 : 23'd0);
endmodule
| 7.09534 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//1-bit full adder
module fa (input wire i0, i1, cin, out... | 7.088073 |
module Adder (
a,
b,
sum
);
input [31:0] a, b;
output [31:0] sum;
wire cout;
wire [31:0] q;
fa fa1 (
a[0],
b[0],
1'b0,
sum[0],
q[0]
);
fa fa2 (
a[1],
b[1],
q[0],
sum[1],
q[1]
);
fa fa3 (
a[2],
b[2],
q[1],
s... | 6.808429 |
module sub_mon #(
parameter WIDTH = 32
) (
input clk,
input reset,
input [WIDTH-1:0] i_a,
input [WIDTH-1:0] i_b,
input [WIDTH-1:0] i_dut_o,
output reg [WIDTH-1:0] o_mon_o,
output reg [WIDTH-1:0] o_dtm_o
);
// adder logic
always @(posedge clk)
// introduce 25% err... | 6.945325 |
module SUB_n_bit (
c_out,
SUB_out,
R2,
R3
);
parameter word_size = 32; // the default size of this n bit subtractor
input [word_size-1:0] R2, R3;
output [word_size-1:0] SUB_out;
output c_out;
wire [word_size-1:0] c_inner, not_R3;
NOT_n_bit #(word_size) NOTN (
not_R3,
R3
)... | 7.334721 |
module SUB_RAMZ #(
parameter RAMADDR_W = 6,
parameter RAMDATA_W = 12
) (
input wire [RAMDATA_W - 1:0] d,
input wire [RAMADDR_W - 1:0] waddr,
input wire [RAMADDR_W - 1:0] raddr,
input wire we,
input wire clk,
output wire [RAMDATA_W - 1:0] q
);
/... | 6.553331 |
module sub_rom (
input [4:0] addr,
input [3:0] imm4,
output reg [7:0] label
);
always @(*)
case (addr)
0: label = "S";
1: label = "U";
2: label = "B";
4: label = imm4[3];
5: label = imm4[2];
6: label = imm4[1];
7: label = imm4[0];
default: label = " ";
... | 6.706154 |
module pool_add2 (
input clock,
input reset,
input [`POOL_OUT_BITWIDTH:0] operand_a,
input [`POOL_OUT_BITWIDTH:0] operand_b,
output reg [`POOL_OUT_BITWIDTH:0] sum
);
`ifdef POOL_RESET
always @(posedge clock or negedge reset) begin
if (reset == 1'b0) sum <= `POOL_OUT_BITWIDTH'd0;
else sum... | 6.890651 |
module sub_t (
input [5:0] a_e,
output [5:0] sub_a_e
);
assign sub_a_e = 15 - a_e;
endmodule
| 7.30096 |
module sub_UserTimeScaleBox (
MASTER_CLK,
MASTER_RST,
VALUE_OUT,
BUTTON_RISE,
BUTTON_FALL,
XCOORD,
YCOORD
);
//==================================================================//
// DEFINITIONS //
//================================... | 7.987097 |
module sub_UserTriggerStyleBox (
MASTER_CLK,
MASTER_RST,
VALUE_OUT,
BUTTON_RISE,
BUTTON_FALL,
XCOORD,
YCOORD
);
//==================================================================//
// DEFINITIONS //
//=============================... | 7.632384 |
module sub_UserLines (
MASTER_CLK,
MASTER_RST,
LINE_VALUE_OUT,
BUTTON_RISE,
BUTTON_FALL,
XCOORD,
YCOORD,
RESET_VALUE,
LEFT,
RGHT,
BOT,
TOP,
SETXnY
);
//==================================================================//
// DEFINITIONS ... | 7.060856 |
module sequential_unsigned_comparator (
input a,
input b,
input rst,
input clk,
input op,
output reg L,
output reg E,
output reg G
);
reg [1:0] present_state, next_state;
localparam s0 = 2'b00; // equal state
localparam s1 = 2'b01; // greater than state
localparam s2 = 2'b10; ... | 7.35408 |
module AND (
a,
b,
y
);
input a, b;
output y;
assign y = a & b;
endmodule
| 7.053445 |
module OR (
a,
b,
y
);
input a, b;
output y;
assign y = a | b;
endmodule
| 7.086775 |
module NOR (
a,
b,
y
);
input a, b;
output y;
assign y = ~(a | b);
endmodule
| 7.611112 |
module XOR (
a,
b,
y
);
input a, b;
output y;
assign y = (a ^ b);
endmodule
| 7.915029 |
module NOT (
a,
b
);
output b;
input a;
assign b = !a;
endmodule
| 7.483426 |
module comp (
input [6:0] A,
input [6:0] B,
output reg Q
);
wire [6:0] temp1;
wire [6:0] temp2;
//XOR x1(.A(A[7]),.B(B[7]),.Q(temp));
assign temp1[0] = A[0];
assign temp1[1] = A[1];
assign temp1[2] = A[2];
assign temp1[3] = A[3];
assign temp1[4] = A[4];
assign temp1[5] = A[5];
assign te... | 6.601597 |
module mux21 (
a,
b,
s,
o
);
input a;
input b;
input s;
output o;
wire not_sel;
wire temp1, temp2;
wire Data_out_temp;
not n1 (not_sel, s);
and and_1 (temp1, a, not_sel);
and and_2 (temp2, b, s);
or or_1 (Data_out_temp, temp1, temp2);
assign o = Data_out_temp;
endmodule
| 7.579812 |
module Pnode (
input sign_LLR_C,
input sign_LLR_D,
input comp1,
input frozen1,
input frozen2,
output u2i_1,
output u2i
);
wire h, i, j, k, l, m, n, comp, o, p, q, r, s, t, u;
XOR X1 (
.a(sign_LLR_C),
.b(sign_LLR_D),
.y(j)
);
NOT N1 (
.a(frozen1),
... | 7.741602 |
module SUCORE (
input [31:0] instr,
output [4:0] A1,
output reg [2:0] rsTuse,
output [4:0] A2,
output reg [2:0] rtTuse,
output [4:0] A3,
output reg [2:0] E_Tnew,
output reg [2:0] M_Tnew
);
wire [6:0] order;
BasicCORE basiccore (
.instr(instr),
.order(order),
.A1(A... | 7.213999 |
module sudoku (
clk,
rst,
puzzle_io,
puzzle_oe,
next_puzzle,
solution,
give_up,
extra_out
);
input clk, rst;
inout [9*9*4-1:0] puzzle_io;
tri [9*9*4-1:0] puzzle_io;
output puzzle_oe;
output next_puzzle;
output solution, give_up;
output [9*9*4-1:0] extra_out;
// PLL sign... | 7.075497 |
module sudoku_accelerator (
input wire wb_clk_i,
input wire wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [ 3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output wb_ack_o,
output [31:0] wb_dat_o,
output uart_enable... | 6.637512 |
module sudoku_accelerator_wrapper (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input wire wb_clk_i,
input wire wb_rst_i,
input wire la_rst,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [ 3:0] wb_sel_i,
in... | 6.637512 |
module sudoku_ans (
puzzle_mask_bin,
puzzle_ans_bin
);
input [9*9*9-1:0] puzzle_mask_bin;
output [9*9*9-1:0] puzzle_ans_bin;
wire [9*9*9*9-1:0] partial_x;
wire [9*9*9*9-1:0] partial_y;
wire [9*9*9*9-1:0] partial_z;
wire [9*9*9*9-1:0] partial_sq;
sudoku_partials sp (
.in(puzzle_mask_bin),
... | 7.336424 |
module bin2hex (
input [9-1:0] bin,
output [ 3:0] out
);
integer hex;
always @(bin) begin
case (bin)
9'b000000001: hex = 4'h1;
9'b000000010: hex = 4'h2;
9'b000000100: hex = 4'h3;
9'b000001000: hex = 4'h4;
9'b000010000: hex = 4'h5;
9'b000100000: hex = 4'h6;
9... | 7.54151 |
module sudoku_hex2bin (
hex,
bin
);
input [9*9*4-1:0] hex;
output [9*9*9-1:0] bin;
generate
genvar i;
for (i = 0; i < 9 * 9; i = i + 1) begin : HEX2BIN
hex2bin h2b (
.hex(hex[i*4+4-1:i*4]),
.out(bin[i*9+9-1:i*9])
);
end
endgenerate
endmodule
| 6.603685 |
module hex2bin (
input [ 3:0] hex,
output [9-1:0] out
);
integer bin;
always @(hex) begin
case (hex)
4'h 1 : bin = 9'b 000000001;
4'h 2 : bin = 9'b 000000010;
4'h 3 : bin = 9'b 000000100;
4'h 4 : bin = 9'b 000001000;
4'h 5 : bin = 9'b 000010000;
4'h 6 ... | 7.029544 |
module sudoku_mask (
puzzle_reg_bin,
puzzle_mask_bin
);
input [9*9*9-1:0] puzzle_reg_bin;
output [9*9*9-1:0] puzzle_mask_bin;
wire [9*9*9*9-1:0] partial_x;
wire [9*9*9*9-1:0] partial_y;
wire [9*9*9*9-1:0] partial_z;
wire [9*9*9*9-1:0] partial_sq;
sudoku_partials sp (
.in(puzzle_reg_bin),
... | 7.070515 |
module spw_to_one_hot (
input [3:0] value,
output [8:0] result,
input invert
);
assign result = invert ? ~tmp : tmp;
reg [8:0] tmp;
always @(value) begin
case (value)
1: tmp = 9'b000000001;
2: tmp = 9'b000000010;
3: tmp = 9'b000000100;
4: tmp = 9'b000001000;
5: tmp... | 6.506008 |
module sudoku_solution (
puzzle_ans,
solution
);
parameter WIDTH = 4; //default to puzzle_ans_hex width of 4
//width of 9 for puzzle_ans_bin.
input [9*9*WIDTH-1:0] puzzle_ans;
output solution;
wire [9*9-1:0] non_zero;
assign solution = &non_zero;
genvar i;
generate
... | 7.46617 |
module suhddpsram1024x16_rq (
input wire [15:0] data_a, // ram_input.datain_a
input wire [15:0] data_b, // .datain_b
input wire [ 9:0] address_a, // .address_a
input wire [ 9:0] address_b, // .address_b
input wire wren_a, // .wren_a
... | 6.853809 |
module suhddpsram1024x16_rq_ram_2port_191_tdpa2va (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [9:0] address_a;
input [9:0] address_b;
input clock;
input [15:0] data_a;
input [15:0] data_b;... | 6.853809 |
module suhddpsram1024x8_rq (
input wire [7:0] data_a, // ram_input.datain_a
input wire [7:0] data_b, // .datain_b
input wire [9:0] address_a, // .address_a
input wire [9:0] address_b, // .address_b
input wire wren_a, // .wren_a
in... | 6.853809 |
module suhddpsram1024x8_rq_ram_2port_191_go2l72y (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [9:0] address_a;
input [9:0] address_b;
input clock;
input [7:0] data_a;
input [7:0] data_b;
... | 6.853809 |
module suhddpsram16384x9_s (
input wire [ 8:0] data_a, // ram_input.datain_a
input wire [ 8:0] data_b, // .datain_b
input wire [13:0] address_a, // .address_a
input wire [13:0] address_b, // .address_b
input wire wren_a, // .wren_a
... | 7.411889 |
module suhddpsram16384x9_s_ram_2port_191_emqbfsi (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [13:0] address_a;
input [13:0] address_b;
input clock;
input [8:0] data_a;
input [8:0] data_b;
... | 7.411889 |
module suhddpsram32x57 (
input wire [56:0] data_a, // ram_input.datain_a
input wire [56:0] data_b, // .datain_b
input wire [ 4:0] address_a, // .address_a
input wire [ 4:0] address_b, // .address_b
input wire wren_a, // .wren_a
i... | 7.080523 |
module suhddpsram32x57_ram_2port_191_5cp27sq (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [4:0] address_a;
input [4:0] address_b;
input clock;
input [56:0] data_a;
input [56:0] data_b;
in... | 7.080523 |
module suhddpsram512x4_rq (
input wire [3:0] data_a, // ram_input.datain_a
input wire [3:0] data_b, // .datain_b
input wire [8:0] address_a, // .address_a
input wire [8:0] address_b, // .address_b
input wire wren_a, // .wren_a
inp... | 6.75558 |
module suhddpsram512x4_rq_ram_2port_191_gytxvfq (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [8:0] address_a;
input [8:0] address_b;
input clock;
input [3:0] data_a;
input [3:0] data_b;
i... | 6.75558 |
module suhddpsram65536x134_s (
input wire [133:0] data_a, // ram_input.datain_a
input wire [133:0] data_b, // .datain_b
input wire [ 15:0] address_a, // .address_a
input wire [ 15:0] address_b, // .address_b
input wire wren_a, // .w... | 7.116652 |
module suhddpsram65536x134_s_ram_2port_191_pu2i72y (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [15:0] address_a;
input [15:0] address_b;
input clock;
input [133:0] data_a;
input [133:0] da... | 7.116652 |
module testsum (
output f,
input a,
b,
c
);
// sum S1(f, a, b, c); //this is known as structural modeling
assign f = (a & b & c); //known as behavioral modeling.
endmodule
| 7.006159 |
module sum512 (
input [512-1:0] in,
output [9:0] out
);
wire [8:0] outr, outl;
sum256 l (
in[512-1:256],
outl
);
sum256 r (
in[256-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.8124 |
module sum256 (
input [256-1:0] in,
output [8:0] out
);
wire [7:0] outr, outl;
sum128 l (
in[256-1:128],
outl
);
sum128 r (
in[128-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.811341 |
module sum128 (
input [128-1:0] in,
output [7:0] out
);
wire [6:0] outr, outl;
sum64 l (
in[128-1:64],
outl
);
sum64 r (
in[64-1:0],
outr
);
assign out = outr + outl;
endmodule
| 7.151327 |
module sum64 (
input [64-1:0] in,
output [6:0] out
);
wire [5:0] outr, outl;
sum32 l (
in[64-1:32],
outl
);
sum32 r (
in[32-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.986065 |
module sum32 (
input [32-1:0] in,
output [5:0] out
);
wire [4:0] outr, outl;
sum16 l (
in[32-1:16],
outl
);
sum16 r (
in[16-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.761252 |
module sum8 (
input [8-1:0] in,
output [ 3:0] out
);
wire [2:0] outr, outl;
sum4 l (
in[8-1:4],
outl
);
sum4 r (
in[4-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.64273 |
module sum4 (
input [4-1:0] in,
output [ 2:0] out
);
wire [1:0] outr, outl;
sum2 l (
in[4-1:2],
outl
);
sum2 r (
in[2-1:0],
outr
);
assign out = outr + outl;
endmodule
| 6.907832 |
module sum2 (
input [2-1:0] in,
output [ 1:0] out
);
assign out = in[1] + in[0];
endmodule
| 7.219206 |
module sum4 (
output wire [3:0] S,
output wire c_out,
input wire [3:0] A,
input wire [3:0] B,
input wire c_in
);
wire C1, C2, C3;
fa full_adder0 (
S[0],
C1,
A[0],
B[0],
c_in
);
fa full_adder1 (
S[1],
C2,
A[1],
B[1],
C1
);
fa f... | 7.206358 |
module sum4b (
init,
xi,
yi,
co,
sal
);
input init;
input [3 : 0] xi;
input [3 : 0] yi;
output co;
output [3 : 0] sal;
wire [4:0] st;
assign sal = st[3:0];
assign Cout = st[4];
assign st = xi + yi;
endmodule
| 7.504786 |
module sum4b_TB;
// Inputs
reg [3:0] xi;
reg [3:0] yi;
// Outputs
wire co;
wire [3:0] zi;
// Instantiate the Unit Under Test (UUT)
sum4b uut (
.xi(xi),
.yi(yi),
.co(co),
.zi(zi)
);
initial begin
// Initialize Inputs
xi = 0;
for (yi = 0; yi < 16; yi = yi + 1) b... | 7.47404 |
module sum4 (
output wire [3:0] S,
output wire c_out,
input wire [3:0] A,
input wire [3:0] B,
input wire c_in
);
assign {c_out, S} = A + B + c_in;
endmodule
| 7.206358 |
module sum4_sin_fa (
output wire [3:0] S,
output wire c_out,
input wire [3:0] A,
input wire [3:0] B,
input wire c_in
); // Se hace uso del operador de concatenación:
assign {c_out, S} = a + b + c_in; // El c_out y el S deben ir en ese orden ya que es el bit más significativo de la operación
endmo... | 6.538546 |
module sum4_tb;
//declaracion de se�ales
reg [3:0] test_A, test_B;
reg test_c_in;
wire [3:0] test_S;
wire test_c_out;
//instancia del modulo a testear
sum4 sum (
test_S,
test_c_out,
test_A,
test_B,
test_c_in
);
initial begin
$monitor("tiempo=%0d A=%b B=%b cin=%b S=... | 7.744039 |
module Suma #(
parameter N = 25
) //Se parametriza para hacer flexible el cambio de ancho de palabra
//Declaracion de senales de entrada y salida
(
input wire signed [N-1:0] A,
B,
output reg signed [N-1:0] SUMA
);
//Declaracion de senales utilizadas dentro del modulo
reg signed [N-1:0] SUMAAux;
... | 7.636157 |
module Sumador1bit (
input a,
b,
c_in,
output sum,
c_out
);
wire s1, s2, c1;
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (s2, s1, c_in);
xor (c_out, s2, c1);
endmodule
| 6.871432 |
module sumador3bits(
input [0:2] in,
output reg [0:1] out,
);
always @(in)
begin
case(in)
3'b000: out = 2'b00;
3'b001: out = 2'b01;
3'b010: out = 2'b01;
3'b011: out = 2'b10;
3'b100: out = 2'b01;
3'b101: out = 2'b10;
3'b110: out = 2'b10;
3'b111: out = 2'b11;
default: out = 2'b00;
endcase
end
endmodule... | 7.566174 |
module Sum4bit (
output wire [3:0] S,
output wire Co,
input wire [3:0] e1,
input wire [3:0] e2,
input wire Ci
);
wire fa0c, fa1c, fa2c;
FA fa0 (
S[0],
fa0c,
e1[0],
e2[0],
Ci
);
FA fa1 (
S[1],
fa1c,
e1[1],
e2[1],
fa0c
);
FA fa2... | 7.43216 |
module SumadorBranch (
input [63:0] inputPC,
input [63:0] inputSEU,
output [63:0] Nextinst
);
assign Nextinst = inputPC + inputSEU;
endmodule
| 6.523469 |
module sumadorCarryLook_4bits (
input [3:0] A,
input [3:0] B,
input Ci,
output [3:0] S,
output Co
);
wire [3:0] P, G;
wire [4:1] C;
wire temp;
medio_sumador ms0 (
A[0],
B[0],
P[0],
G[0]
);
medio_sumador ms1 (
A[1],
B[1],
P[1],
G[1]
);
m... | 6.778141 |
module FA (
output wire S,
output wire Co,
input wire e1,
input wire e2,
input wire ci
);
wire HA1S, HA1C, HA2C;
HA ha1 (
HA1S,
HA1C,
e1,
e2
);
HA ha2 (
S,
HA2C,
ci,
HA1S
);
or (Co, HA1C, HA2C);
endmodule
| 7.885402 |
module SumadorNbits #(
parameter N = 8
) (
input [N-1:0] a,
input [N-1:0] b,
input c_in,
output [N-1:0] sum,
output c_out
);
wire [0:N-1] carry;
genvar i;
Sumador1bit sumador0 (
.a(a[0]),
.b(b[0]),
.c_in(1'b0),
.sum(sum[0]),
.c_out(carry[0])
);
generate... | 6.915605 |
module Sumador_12b (
input [11:0] A,
B, // Operandos
output [11:0] SUM // Suma
);
assign SUM = A + B;
endmodule
| 6.768738 |
module sumador_4bits (
input [3:0] A,
input [3:0] B,
input Ci,
output [3:0] S,
output Co
);
wire C1, C2, C3;
sumador_completo sc0 (
A[0],
B[0],
Ci,
S[0],
C1
);
sumador_completo sc1 (
A[1],
B[1],
Ci,
S[1],
C2
);
sumador_completo ... | 6.746912 |
module Sumador_8b (
input [7:0] A,
B, // Operandos
output [7:0] SUM // Suma
);
assign SUM = A + B;
endmodule
| 6.769222 |
module sumador_completo (
input A,
input B,
input Cin,
output S,
output Cout
);
wire P, G, H;
medio_sumador ms1 (
A,
B,
P,
G
);
medio_sumador ms2 (
P,
Cin,
S,
H
);
or (Cout, G, H);
endmodule
| 7.210508 |
module SUM8_LOGICO (
a,
b,
ci,
s,
co
);
parameter PwrC = 0;
input [7:0] a, b;
input ci;
output [7:0] s;
output co;
wire [7:0] a, b, s;
wire [3:0] a_L, a_H, b_L, b_H, s_L, s_H;
wire ci, co;
SUM4_logico #(PwrC) sum4_L (
a_L,
b_L,
ci,
s_L,
co_L
);
... | 6.549223 |
module SUM8_LOOKAHEAD (
a,
b,
ci,
s,
co
);
parameter PwrC = 0;
input [7:0] a, b;
input ci;
output [7:0] s;
output co;
wire [7:0] a, b, s;
wire [3:0] a_L, a_H, b_L, b_H, s_L, s_H;
wire ci, co;
SUM4_lookahead #(PwrC) sum4look_L (
a_L,
b_L,
ci,
s_L,
co... | 7.193794 |
module Sumador_pipe (
input clk,
input reset,
input [3:0] idx,
input [3:0] dataA,
input [3:0] dataB,
output reg [3:0] idx_dd,
output [3:0] sum30_dd
);
reg [3:0] idx_d;
always @(posedge clk) begin
if (!reset) begin
idx_d <= 0;
id... | 6.586775 |
module sumador_completo ( // all 1 bit
// input wire a,
// input wire b,
// input wire ci,
// output reg s,
// output reg co
// );
// parameter
// PwrC = 0;
// // For outputs connections
// wire w0,w1,w2,w3,w4,w5;
// /////////
// /// w0
// ////////
// xor2_p xorw0(
// // Outp... | 7.210508 |
module sumador_completo ( // all 1 bit
input wire a,
input wire b,
input wire ci,
output reg s,
output reg co
);
parameter PwrC = 0;
// For outputs connections
wire w1, w2, w3, w4, w5;
/////////
/// w4
////////
xor3_p xorw4 (
// Outputs
.a(w4),
//Inputs
... | 7.210508 |
module SUM_RIZADO (
input wire [7:0] a, // 8 bits
input wire [7:0] b, // 8 bits
input wire ci,
output reg [7:0] s, // 8 bits
output reg co
);
parameter PwrC = 0;
// for 8 bits
wire [7:0] ws_8bit;
wire [7:0] carry_8bit;
sumador_completo sumador_completo0 (
//outputs
.s (ws... | 7.198251 |
module top (
input wire FPGA_SYSCLK_P,
input wire FPGA_SYSCLK_N,
inout wire I2C_FPGA_SCL,
inout wire I2C_FPGA_SDA,
output wire [7:0] LED,
// Ethernet
input wire SFP_CLK_P,
input wire SFP_CLK_N,
output wire SFP_REC_CLK_P,
output wire SFP_REC_CLK_N,
input wire SFP_CLK_ALARM... | 7.233807 |
module sume_to_sdnet (
// clk/rst input
input axi_clk,
input axi_resetn,
// input SUME axi signals
input SUME_axi_tvalid,
input SUME_axi_tlast,
input SUME_axi_tready,
// output SDNet signals
output SDNet_tuple_VALID,
output SDNet_axi_TLAST
);
// registers to hold the valu... | 7.079365 |
module Summation_Logic #(
parameter DATA_WIDTH = 32,
parameter TOTAL_PARTICLE_NUM = 20000,
parameter PARTICLE_GLOBAL_ID_WIDTH = 15, // log(TOTAL_PARTICLE_NUM)/log(2)
parameter NUM_CELL_X = 5,
parameter NUM_CELL_Y = 5,
parameter NUM_CELL_Z = 5,
parameter NUM_TOTAL_CELL = NUM_CELL_X * NUM_CEL... | 7.086003 |
module code_ram #(
parameter integer ADDR_SIZE = 18,
parameter integer WORD_SIZE = 18,
parameter integer MEM_SIZE = 1024
) (
input wire [(ADDR_SIZE-1):0] addr,
output wire [(WORD_SIZE-1):0] dout
);
reg [(WORD_SIZE-1):0] mem[(MEM_SIZE-1):0];
initial $readmemh("vmem.txt", mem);
assign dout ... | 7.26833 |
module processor_tb;
parameter MEM_SIZE = 64;
parameter WORD_SIZE = 18;
reg clock;
logic [(WORD_SIZE-1):0] program_memory_addr;
wire [(WORD_SIZE-1):0] program_memory_out_data;
logic processor_reset;
logic wait_continue_execution;
logic wait_for_continue;
integer i;
wire data_we;
wire [(WORD_S... | 6.711119 |
module mullxx_tb;
parameter WORD_SIZE = 18;
logic [WORD_SIZE-1:0] r0;
logic [WORD_SIZE-1:0] r1;
logic [WORD_SIZE-1:0] res;
logic [4:0] shift;
logic signx;
logic signy;
logic signed [WORD_SIZE-1:0] r0s;
logic signed [WORD_SIZE-1:0] r1s;
logic signed [WORD_SIZE-1:0] ress;
assign r0s = $signed(r0)... | 6.838219 |
module takes in an array of numbers and sums them. guaranteed ceil(log2(BLOCKLENGTH)) registers.
Executes the sum with recursive calls.
PipelineSummer is a wrapper of Summer with ready and valid logic.
*/
`include "2dArrayMacros.v"
`include "PipelineTrain.v"
/* recursive sum tree with pipeline logic*/
module Pipelin... | 6.546226 |
module SummerRec #(
parameter BLOCKLENGTH = 2,
parameter DATA_WIDTH = 8
) (
input clk,
input reset,
input enable,
input [DATA_WIDTH*BLOCKLENGTH-1:0] data_in,
output signed [DATA_WIDTH-1:0] sum
);
wire signed [DATA_WIDTH-1:0] in[0:BLOCKLENGTH-1];
`UNPACK_ARRAY(DATA_WIDTH, BLOCKLENGTH, ... | 6.815015 |
module sumofN(CLK,
RST_N,
in_put,
EN_in_put,
RDY_in_put,
EN_out_get,
out_get,
RDY_out_get,
configure_address,
configure_data,
EN_configure,
RDY_configure,
interrupt,
RDY_interrupt);
input CLK;
input RST_N;
// action ... | 6.541892 |
module sumsub1 #(
parameter WIDTH = 8
) (
input wire signed [WIDTH-1:0] a, // primer operando
input wire signed [WIDTH-1:0] b, // segundo operando
input wire op, // operación (0-suma, 1-resta)
output reg signed [WIDTH-1:0] f, // salida
output reg ... | 7.422484 |
module sumsub2 #(
parameter WIDTH = 8
) (
input wire [WIDTH-1:0] a, // primer operando
input wire [WIDTH-1:0] b, // segundo operando
input wire op, // operación (0-suma, 1-resta)
output reg [WIDTH-1:0] f, // salida
output reg ov // desbordamiento
);
alway... | 7.070679 |
module SumUnit (
input G,
input P,
input Pi,
input Cin,
output Cout,
output Sum
);
assign Cout = G | (P & Cin);
assign Sum = Pi ^ Cin;
endmodule
| 6.81255 |
module Sum_28 (
A,
B,
sum
);
input [27:0] A, B;
output [27:0] sum;
assign sum = A + B;
endmodule
| 7.150979 |
module sum_2N #(
parameter R = 8,
N = 3
) (
input clk,
rst,
input wire signed [R-1 : 0] in, // input vl
output reg signed [R+N-1:0] out, // sum val
output reg signed [R-1 : 0] mean, // mean val
output wire tick // output tick
);
//si... | 6.85532 |
module sum_2N2 #(
parameter R1 = 8,
R2 = 8,
N = 3
) (
input clk,
rst,
input wire signed [R1-1 : 0] in1, // input vl
output reg signed [R1+N-1:0] out1, // sum val
output reg signed [R1-1 : 0] mean1, // mean val
input wire signed [R2-1 : 0] in2, //... | 7.259604 |
module Sum_51 (
A,
B,
sum
);
input [50:0] A, B;
output [50:0] sum;
assign sum = A + B;
endmodule
| 6.73343 |
module sum_and_max #(
parameter DATA_WIDTH = 8,
parameter LENGTH = 10
)
//note: this module is not fully parametrized and must be rewritten for different LENGTH
(
input clk,
input reset_n,
input ready,
input [2*DATA_WIDTH*LENGTH-1:0] input_data,
input [DATA_WIDTH*LENGTH-1:0] biases,
outp... | 7.447021 |
module sum_async_mem #(
parameter AWIDTH = 10,
parameter DWIDTH = 32,
parameter DEPTH = 1024,
parameter MEM_INIT_HEX_FILE = ""
) (
input clk,
input reset,
output done,
input [31:0] size,
output [31:0] sum
);
// TODO: Fill in the remaining logic to compute the sum of memory data fr... | 7.664892 |
module sum_async_mem_tb ();
localparam AWIDTH = 10;
localparam DWIDTH = 32;
localparam DEPTH = 1024;
reg clk;
initial clk = 0;
always #(4) clk <= ~clk;
reg reset;
reg [31:0] size;
wire [DWIDTH-1:0] sum;
wire done;
sum_async_mem #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH),
.DEPTH(DEPTH... | 7.664892 |
module counter input
CLR: module counter input
out_num: output port for the counter module, 8 bits
------------------------------------------------------
History:
01-13-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignmen... | 7.206611 |
module counter input
CLR: module counter input
out_num: output port for the counter module, 8 bits
------------------------------------------------------
History:
01-13-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignmen... | 7.206611 |
module Sum_35 (
A,
B,
sum
);
input [34:0] A, B;
output [34:0] sum;
assign sum = A + B;
endmodule
| 7.472767 |
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