code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module subr (
input a,
input b,
input c,
output diff,
output borr
);
wire anot;
assign anot = (~a);
assign diff = (a ^ b ^ c);
assign borr = (anot & b) | (b & c) | (c & anot);
endmodule
| 8.270388 |
module subractor #(
parameter dataIN_width = 4
) (
input [dataIN_width - 1 : 0] A,
B,
output reg [ dataIN_width -1 : 0] C
);
always @(A, B) C <= A - B;
endmodule
| 6.544854 |
module TB_SUBREG_TIM_DIV #(
parameter C_C = 10.0
) ();
reg CK;
initial begin
CK <= 1'b1;
forever begin
#(C_C / 2);
CK <= ~CK;
end
end
reg XARST;
initial begin
XARST <= 1'b1;
#(0.1 * C_C);
XARST <= 1'b0;
#(2.1 * C_C);
XARST <= 1'b1;
end
assign ENCBIN_XDIRECT... | 6.817315 |
module subsampling #(
parameter XI_SUBSAMPLE = 1,
parameter YI_SUBSAMPLE = 1,
parameter XO_SUBSAMPLE = 2,
parameter YO_SUBSAMPLE = 2,
parameter MCU_WIDTH = 8,
parameter MCU_HEIGHT = 8,
parameter COLOR_PRECISION = 8,
parameter REGISTER = "YES"
) (
input i_arst,
input i_sysclk,
... | 6.78233 |
module subservient #( //Memory parameters
parameter memsize = 512,
parameter aw = $clog2(memsize),
//Enable CSR + interrupts
parameter WITH_CSR = 0
) (
input wire i_clk,
input wire i_rst,
//SRAM interface
output wire [aw-1:0] o_sram_waddr,
output wire [7:0] o_sram_wdata,
... | 8.153472 |
module subservient_debug_switch ( //Debug selector
input wire i_debug_mode,
//Debug interface
input wire [31:0] i_wb_dbg_adr,
input wire [31:0] i_wb_dbg_dat,
input wire [ 3:0] i_wb_dbg_sel,
input wire i_wb_dbg_we,
input wire i_wb_dbg_stb,
output wire [31:0] o_wb_dbg_... | 8.522888 |
module subservient_fpga (
input wire i_clk,
input wire i_rst,
output wire q
);
parameter memfile = "hello.hex";
parameter memsize = 1024;
localparam aw = $clog2(memsize);
wire clk;
wire rst;
wire [aw-1:0] sram_waddr;
wire [ 7:0] sram_wdata;
wire sram_wen;
... | 7.119097 |
module subservient_fpga_clock_gen (
input wire i_clk,
input wire i_rst,
output wire o_clk,
output reg o_rst
);
assign o_clk = i_clk;
always @(posedge i_clk) o_rst <= i_rst;
endmodule
| 7.119097 |
module subservient_generic_ram #(
parameter depth = 0,
parameter aw = $clog2(depth),
parameter memfile = ""
) (
input wire i_clk,
input wire i_rst,
//SRAM interface
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output re... | 8.499675 |
module subservient_gpio (
input wire i_wb_clk,
input wire i_wb_rst,
input wire i_wb_dat,
input wire i_wb_we,
input wire i_wb_stb,
output reg o_wb_rdt,
output reg o_wb_ack,
output reg o_gpio
);
always @(posedge i_wb_clk) begin
o_wb_rdt <= o_gpio;
if (i_wb_stb & i_wb_we)... | 8.499675 |
module subservient_fpga_clock_gen (
input wire i_clk,
input wire i_rst,
output wire o_clk,
output reg o_rst
);
wire clkfb;
wire locked;
reg locked_r;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKIN1_PERIOD(10.0), //100MHz
.CLKFBOUT_MULT(16),
.CLKOUT0_DIVIDE(50),
... | 7.119097 |
module subservient_openram_if (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
outpu... | 9.413267 |
module subservient_ram #( //Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth)
) (
input wire i_clk,
input wire i_rst,
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output wire [7:0] o_rdata... | 7.296578 |
module subservient_rf_ram_if #(
parameter width = 8,
parameter reset_strategy = "MINI",
parameter csr_regs = 4,
parameter depth = 32 * (32 + csr_regs) / width,
parameter l2w = $clog2(width)
) (
//SERV side
input wire i_clk,
input wire ... | 7.296578 |
module subservient_tb;
parameter memfile = "";
parameter memsize = 8192;
parameter with_csr = 0;
parameter aw = $clog2(memsize);
reg clk = 1'b0;
reg rst = 1'b1;
wire [aw-1:0] sram_waddr;
wire [7:0] sram_wdata;
wire sram_wen;
wire [aw-1:0] sram_raddr;
wire [7:0] sram_rdata;
wire sram_r... | 7.118656 |
module subservient_wrapped (
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [... | 6.642427 |
module subservient_wrapper_tb;
parameter memfile = "";
parameter memsize = 512;
parameter with_csr = 0;
parameter aw = $clog2(memsize);
reg clk = 1'b0;
reg rst = 1'b1;
wire PWR = 1'b1;
wire GND = 1'b0;
//Debug interface
reg la_data_in;
reg [31:0] wbs_adr_i... | 6.642427 |
module dec8 (
input wire en, // habilitación (enable) activo en bajo
input wire [2:0] i, // entradas
output reg [7:0] o // salidas
/* Recuerda: para cada puerto de entrada o salida, el compilador define
* una señal tipo 'wire' del mismo nombre. El tipo de señal puede
* cambiarse d... | 6.847764 |
module mux8_1 (
input wire [2:0] sel, // entradas de selección
input wire [7:0] in, // entradas de datos
output reg out // salida
);
always @(sel, in)
/* La forma más directa de describir un multiplexor es mediante
* un bloque 'case'. */
case (sel)
3'h0: out = in[0... | 7.497332 |
module cod8 (
input wire [7:0] in, // entradas
output reg [2:0] out, // salida condificada
output reg e // salida de error (1-ninguna entrada activa)
);
always @(in) begin
/* 'e' valdrá cero salvo que alguna condición posterior
* cambie su valor */
e = 0;
/* 'case' ta... | 8.604602 |
module comp4 (
input wire [3:0] a, // número a
input wire [3:0] b, // número b
input wire g0, // entradas para conexión en cascada
input wire e0, // y salidas de la comparación
input wire l0, // si a > b => (g,e,l) = (1,0,0)
output reg g, // si a < b =>... | 7.171488 |
module info ();
initial begin
$display("Seleccione un banco de pruebas definiendo una ", "de las siguientes macros:");
$display(" TEST_DEC: decodificador");
$display(" TEST_MUX: multiplexor");
$display(" TEST_COD: codificador de prioridad");
$display(" TEST_COMP: comparador de magnitudes");
... | 7.219665 |
module: subErrCtrlSplitter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module subSplitter_tb;
// Inputs
reg [0:0] err_ctrl;
// Outputs
wire [0:0] sub_err_ctrl;
// Instantiate th... | 7.391929 |
module switching_latch (
input clk, // the system clock
input int_clk, // the interupt clock domain
input reset_n,
input trigger,
input ack,
output reg out
);
reg ack_clk_1; // Doing a 3 stage sync between the clock domains - Fuck I hate these.......
// But t... | 8.237858 |
module clock_reg_latch #(
parameter data_size = 32
) (
input write_clk, // the APF clock
input read_clk, // the system clock
input reset_n,
input write_trigger,
input [data_size-1:0] write_data_in... | 7.962295 |
module timer_core (
input clk_sys,
input millisecond_counter_reset,
output reg [31:0] millisecond_counter,
output reg [31:0] millisecond_tick,
output reg [31:0] millisecond_real,
input [31:0] sysclk_frequency,
input [31:0] interupt_counter,
output reg ... | 6.564985 |
module sub_byte (
in_key,
out_key
);
input [0:127] in_key;
output [0:127] out_key;
sbox sb1 (
in_key[0:3],
in_key[4:7],
out_key[0:7]
);
sbox sb2 (
in_key[8:11],
in_key[12:15],
out_key[8:15]
);
sbox sb3 (
in_key[16:19],
in_key[20:23],
out_key[16... | 7.059994 |
module seq_detector (
//Control signals
input clk, //Positive edge triggered.
input areset, //Reset all in 1
//Data signals
input seq,
output detected
);
//Declare your variables here.
/*parameter[1:0] S0 = 2'b00,
S1 = 2'b01,
S2 = 2'b10;
*/
reg [1:0] state = 2'b00... | 7.041455 |
module substract (
a,
b,
c
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
parameter IWIDTH = 64;
parameter HiddenNeuron = 16;
parameter x = 4;
parameter Layer = 3;
input signed [DWIDTH-1:0] a;
input signed [DWIDTH-1:0] b;
output signed [DWIDTH-1:0] c;
assign c = a - b;
endmodule
| 6.706886 |
module Substraction (
flag_ex,
ans_tmp,
A,
B
);
input [7:0] A, B;
output wire [3:0] flag_ex;
output wire [7:0] ans_tmp;
add_sub_8bit Add (
flag_ex[2],
ans_tmp,
flag_ex[0],
A,
B,
1'b1
);
assign flag_ex[1] = ~(|ans_tmp);
assign flag_ex[3] = ^(ans_tmp);
... | 7.172059 |
module Substractor_1Bit (
//define inputs
input _subInA,
_subInB,
_subBin,
//define ouputs
output _differenceOut,
_borrowOut
);
reg _diffReg, _borrowReg;
assign _differenceOut = ({_subInA,_subInB} == 2'b00) ? _subBin:
({_subInA,_subInB} == 2'b01) ? (~_subBin):... | 6.786421 |
module Substractor_4bit (
//define inputs
input [7:0] _subInA,
_subInB,
input _subBin,
//define outputs
output [7:0] _differenceOut,
output _borrowOut
);
wire [7:0] _bOut;
Substractor_1Bit M0 (
_subInA[0],
_subInB[0],
_subBin,
_differenceOut[0],
_bOut[0]
... | 7.138275 |
module subsystem_v1_0 #(
// Users to add parameters here
parameter integer SIZE = 4,
parameter integer MAX_WORD_LENGTH = 32,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32... | 6.503653 |
module subtract (
a,
b,
result
);
parameter WIDTH = 8;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
output [WIDTH-1:0] result;
wire [WIDTH-1:0] inv_b;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
inv1$(
inv_b[i], b[i]
);
end
endgenerate
slow_ad... | 7.409159 |
module slow_addr_cin (
a,
b,
out,
carry,
cin
);
parameter WIDTH = 64;
input cin;
input [WIDTH-1:0] a, b;
output [WIDTH-1:0] out;
output carry;
wire [WIDTH-1:0] carry_vec;
genvar i;
generate
if (WIDTH == 1) begin
full_addr fa (
a,
b,
out,
... | 7.756084 |
module subtracter (
S,
A,
B,
CarryIn
);
input [31:0] A, B;
input CarryIn;
output [31:0] S;
wire [31:0] noted;
noter N (
noted,
B
);
adder ADD (
S,
A,
noted,
CarryIn
);
endmodule
| 6.924494 |
module subtracter_32 (
out,
in1,
in2
);
input [31:0] in1, in2;
output [31:0] out;
wire [31:0] a;
wire carry;
not_32 NOT (
a,
in2
);
full_adder_32 FA (
out,
carry,
in1,
a,
1'b1
);
endmodule
| 7.076294 |
module subtraction (
a,
b,
c
);
// bit depth
localparam BIT_DEPTH = 14;
input wire [BIT_DEPTH-1:0] a, b;
output wire [BIT_DEPTH:0] c;
pos_sub #(BIT_DEPTH, BIT_DEPTH) SUB (
a,
b,
c
);
endmodule
| 8.183545 |
module subtra (
a,
b,
cin,
o,
signbit
);
input [255:0] a, b;
input cin;
output [255:0] o;
output signbit;
wire [255:0] r, f, i;
wire carryout;
twoscomplement w (
b,
r
);
fullmodu q (
a,
r,
1'b0,
f,
carryout
);
twoscomplement e (
f... | 6.662515 |
module twoscomplement (
f,
i
);
input [255:0] f;
output [255:0] i;
assign i = (~f) + 1'b1;
endmodule
| 7.994634 |
module fulladder (
X,
Y,
Ci,
S,
Co
);
input X, Y, Ci;
output S, Co;
wire w1, w2, w3;
//Structural code for one bit full adder
xor G1 (w1, X, Y);
xor G2 (S, w1, Ci);
and G3 (w2, w1, Ci);
and G4 (w3, X, Y);
or G5 (Co, w2, w3);
endmodule
| 7.454465 |
module rippe_adder (
X,
Y,
Cin,
S,
co
);
input [7:0] X, Y;
output [7:0] S;
output co;
input Cin;
wire w1, w2, w3, w4, w5, w6, w7;
//instantiating 4 1-bit full adders in Verilog
fulladder u1 (
X[0],
Y[0],
Cin,
S[0],
w1
);
fulladder u2 (
X[1],
... | 7.974568 |
module SubtractOperation (
input [11:0] lhs,
input [11:0] rhs,
output [11:0] result,
output overflow
);
assign overflow = lhs < rhs;
assign result = lhs - rhs;
endmodule
| 7.126781 |
module subtractor_nb (
A,
B,
SUB,
sign_flag,
Co
);
parameter n = 32;
input signed [n-1:0] A, B;
output signed [n-1:0] SUB;
output sign_flag;
output Co;
rca_nb subtr (
.a (A),
.b (~B),
.cin(32'b0000000000000000_0000000000000001),
.sum(SUB),
.co (Co)
);... | 7.15584 |
module Subtractor_8Bit (
input [7:0] A,
input [7:0] B,
output [7:0] D,
output Bout
);
wire [7:0] w;
HalfSubtractor H1 (
A[0],
B[0],
D[0],
w[0]
);
FullSubtractor F1 (
A[1],
B[1],
w[0],
D[1],
w[1]
);
FullSubtractor F2 (
A[2],
... | 6.897715 |
module sub_16_bit (
input1,
input2,
answer
);
parameter N = 16;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire M;
wire [N-1:0] temp;
wire [N-1:0] carry;
assign M = 1;
genvar i;
for (i = 0; i < N; i = i + 1) begin
assign temp[i] = input2[i] ^ M;
end
gene... | 6.856011 |
module Subtractor_2_input (
p_sub,
q_sub,
p,
q
);
parameter size = 4;
output [(size-1):0] p_sub;
output [(size-1):0] q_sub;
input [(size-1):0] p;
input [(size-1):0] q;
assign p_sub = p - 1;
assign q_sub = q - 1;
endmodule
| 6.954463 |
module subtractor_4bit (
a,
b,
diff,
sgn
);
input [3:0] a, b; //a is the minuend, b is the subtrahend
output [3:0] diff;
output sgn; //sign of result, 1 for '+'ve no. and 0 for '-'ve no.
wire boutin; //generated borrow, which is to be ignored /***********/
wire [3:0] b_bar; //comp... | 7.028549 |
module regN (
reset,
CLK,
D,
Q
);
input reset;
input CLK;
parameter N = 8;
input [N-1:0] D;
output [N-1:0] Q;
reg [N-1:0] Q;
always @(posedge CLK or posedge reset)
if (reset) Q = 0;
else Q = D;
endmodule
| 7.765402 |
module subtractor_full (
minuend,
subtrahend,
inborrow,
diff,
outborrow
);
input minuend, subtrahend, inborrow;
/*
`inborrow` is the bit that tells us whether the previous operation required a BORROW or not. This information is impactful for the outputs of the current operation.
inborro... | 7.458539 |
module testbenchforhalfsubtractor;
reg minuend, subtrahend;
wire diff, outborrow;
subtractor_half wire_driver (
minuend,
subtrahend,
diff,
outborrow
);
// We name the instance of the module as `wire_driver` since it is DRIVING the values of the wires `diff` and `outborrow`.
//* Beh... | 7.057029 |
module subtract_10_5_bits (
input [4:0] x,
output [3:0] A
);
assign A = x - 10;
endmodule
| 7.42961 |
module subtract_512 (
in_1,
in_2,
out
);
input [40:0] in_1;
input [40:0] in_2;
output [40:0] out;
assign out[40:0] = in_1[40:0] - in_2[40:0];
endmodule
| 7.267621 |
module add_8bit (
a,
b,
c_in,
s,
c_out
);
input [7:0] a;
input [7:0] b;
input c_in;
output [7:0] s;
output c_out;
wire [6:0] c;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.c_in(c_in),
.s(s[0]),
.c_out(c[0])
);
full_adder fa1 (
.a(a[1]),
.b(b[1... | 6.573601 |
module subtract_8bit (
a,
b,
b_in,
d,
b_out
);
input [7:0] a;
input [7:0] b;
input b_in;
output [7:0] d;
output b_out;
wire [7:0] twos_comp;
wire c_out;
add_8bit rca0 (
.a(~b),
.b(8'b00000001),
.c_in(1'b0),
.s(twos_comp),
.c_out(c_out)
);
add_8bit r... | 6.606639 |
module subtract_8bit_tb;
reg [7:0] a;
reg [7:0] b;
reg b_in;
wire [7:0] d;
wire b_out;
subtract_8bit uut (
.a(a),
.b(b),
.b_in(b_in),
.d(d),
.b_out(b_out)
);
initial begin
$dumpfile("subtract_8bit_tb.vcd");
$dumpvars(0, subtract_8bit_tb);
a = 8'b00000001;
... | 6.606639 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module subtract_module(Clk, data_in, reset, enable, textO... | 7.088073 |
module notGate (
s,
x
);
output s;
input x;
nand NAND1 (s, x, x);
endmodule
| 8.310861 |
module andGate (
s,
x,
y
);
output s0, s;
input x, y;
wire s, s0;
nand NAND1 (s, x, y);
notGate NOT1_NAND1 (
s0,
s
);
endmodule
| 9.12182 |
module orGate (
s0,
x,
y
);
output s0, sX, sY;
input x, y;
wire s0, sX, sY;
notGate NOT1 (
sX,
x
);
notGate NOT2 (
sY,
y
);
nand NAND1 (s0, sX, sY);
endmodule
| 7.703609 |
module saida1 (
s,
x,
y
);
output s1, s2, s;
input x, y;
wire s;
notGate NOT1 (
s1,
x
);
nand NAND1 (s2, s1, y);
notGate NOT2 (
s,
s2
);
endmodule
| 6.784364 |
module meiaDiferenca1 (
s0,
s1,
x,
y
);
input x, y;
output s0, s1;
wire s0, s1;
saida0 S0 (
s0,
x,
y
);
saida1 S1 (
s1,
x,
y
);
endmodule
| 8.132121 |
module diferenca_2bits (
s0,
s1,
s2,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s0, s1, s2, saida0, saida1;
wire saida0, saida1;
diferencaCompleta DIFERENCACOMPLETA1 (
s0,
saida0,
a0,
b0,
0
);
diferencaCompleta DIFERENCACOMPLETA2 (
s1,
... | 7.053639 |
module notGate (
s,
a
);
output s;
input a;
nand NAND1 (s, a, a);
endmodule
| 8.310861 |
module andGate (
s,
a,
b
);
output s0, s;
input a, b;
wire s, s0;
nand NAND1 (s, a, b);
notGate NOT1_NAND1 (
s0,
s
);
endmodule
| 9.12182 |
module orGate (
s0,
a,
b
);
output s0, sA, sB;
input a, b;
wire s0, sA, sB;
notGate NOT1 (
sA,
a
);
notGate NOT2 (
sB,
b
);
nand NAND1 (s0, sA, sB);
endmodule
| 7.703609 |
module saida1 (
s,
a,
b
);
output s1, s2, s;
input a, b;
wire s;
notGate NOT1 (
s1,
a
);
nand NAND1 (s2, s1, b);
notGate NOT2 (
s,
s2
);
endmodule
| 6.784364 |
module meiaDiferenca1 (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
wire s0, s1;
saida0 S0 (
s0,
a,
b
);
saida1 S1 (
s1,
a,
b
);
endmodule
| 8.132121 |
module subtree_212_wrapper #(
parameter num_leaves = 32,
parameter payload_sz = 43,
parameter p_sz = 49,
parameter addr = 2'b00,
parameter level = 2
) (
input [p_sz-1:0] leaf_0_in,
input [p_sz-1:0] leaf_1_in,
input [p_sz-1:0] leaf_2_in,
input [p_sz-1:0] leaf_3_in,
input [p_... | 7.441331 |
module SUBT_32Bits (
input wire [31:0] A, //ENTRADA A
input wire [31:0] B, //ENTRADA B
output wire [31:0] Y //SALIDA Y
);
assign Y = A - B; //RESTA DE ENTRADAS
endmodule
| 8.641194 |
module SUBU (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output reg carry
);
always @(*) begin
if (a < b) carry = 1;
else carry = 0;
end
assign r = a - b;
endmodule
| 6.97686 |
module reg32 (
input [31:0] in,
clk,
rst,
output reg [31:0] out
);
reg [31:0] mem;
always @(posedge clk) // trigger on rising clk
begin
if (rst) mem = 32'd0;
else mem = in;
out = mem;
end
endmodule
| 7.501717 |
module twomux32 (input [31:0]a, [31:0]b, sel, output reg [31:0]out);
always @(*)
begin
case(sel)
1'd0: out = a;
1'd1: out = b;
default: out = 32'bx;
endcase
end
endmodule
| 7.441983 |
module twomux16 (input [15:0]a, [15:0]b, sel, clk, output reg [15:0]out);
always @(*)
begin
case (sel)
1'd0: out = a;
1'd1: out = b;
default: out = 16'bx;
endcase
end
endmodule
| 7.137584 |
module SUB_ #(
parameter N = 8,
M = N
) ( // N >= M
input [N-1:0] A,
input [M-1:0] B,
output [ N:0] O
);
assign {CO, S} = A - B;
endmodule
| 6.980838 |
module sub_254 (
input wire clk,
input wire rst,
input wire [253 : 0] sub_in0,
input wire [253 : 0] sub_in1,
output reg [253 : 0] sub_out
);
always @(posedge clk)
if (rst) begin
sub_out <= 254'b0;
end else begin
sub_out <= sub_in0 - sub_in1;
end
endmodule
| 7.768499 |
module sub_32b (
dataa,
datab,
overflow,
result
);
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
wire [32:0] computation; //one extra bit to account for overflow
assign computation = dataa - datab;
assign overflow = computation[32];
assign result = co... | 7.033184 |
module sub_32b_testbench ();
reg [31:0] A;
reg [31:0] B;
reg C_in;
wire [31:0] O;
wire C_out;
wire V;
sub_32b sub32tb (
O,
V,
C_out,
A,
B,
C_in
);
initial begin
C_in = 1'b0;
A = 32'b00000000000000000000000000000010;
B = 32'b000000000000000000000000... | 6.636855 |
module sub_32_bit (
input wire [31:0] Ra,
input wire [31:0] Rb,
input wire cin,
output wire [31:0] sum,
output wire cout
);
wire [31:0] tempValue;
negate_32_bit negate (
.Ra(Rb),
.Rz(tempValue)
);
add_32_bit add (
.Ra (Ra),
.Rb (tempValue),
.cin (cin),
.... | 7.502319 |
module SUB_64 (
diff,
a,
b
);
parameter n = 64;
input signed [n-1:0] a, b;
output signed [n-1:0] diff;
wire signed [n-1:0] b1; // 1s completement of b
wire signed [n-1:0] b2; // 2s comp of b
wire signed [n-1:0] dummy; // random dummy variables
wire signed [n-1:0] dummy2;
NOT_64 g1 (
... | 6.881718 |
module sub_8bit (
a,
b,
result_sub1
); // test bench
// signals used in test bench (the interconnections)
input [7:0] a; // so bi tru
input [7:0] b; // so tru
output [8:0] result_sub1;
wire [8:0] cout;
// tang 1: khoi tru
//
// a,b,t,c_in,r,q
cas_1bit bit03 (
a[0],
... | 7.534545 |
module SUB_AB #(
parameter WIDTH3 = 8
) (
A,
B,
OUT
);
input [WIDTH3-1:0] A, B;
output [WIDTH3-1:0] OUT;
assign OUT = A - B;
endmodule
| 7.30172 |
module sub_ALU (
a,
b,
c_in,
diff,
c_out
);
input a, b;
input c_in;
output diff;
output c_out;
wire b_not;
not_ALU notb (
.in (b),
.out(b_not)
);
FA_str subt (
c_out,
diff,
a,
b_not,
c_in
);
endmodule
| 8.011854 |
module Sub_BIST (
rst,
clk,
wrt_addrs,
rd_addrs,
wrt_dat,
wrt_en,
button,
rd_data,
led_out
);
input rst;
input clk;
input [9:0] wrt_addrs;
input [9:0] rd_addrs;
input [7:0] wrt_dat;
input wrt_en;
input button;
output wire [7:0] rd_data;
output reg [7:0] led_out;
... | 6.747637 |
module sub_byte (
input [127:0] subByteInput,
input startTransition,
input clock,
output [127:0] subByteOutput
);
genvar twoBytes;
generate
for (twoBytes = 0; twoBytes < 128; twoBytes = twoBytes + 8) begin : subByte
s_box subValue (
.inputValue(subByteInput[twoBytes+:8]),
... | 7.059994 |
module sub_bytes (
in,
out
);
input [16*8-1 : 0] in;
output [16*8-1 : 0] out;
wire [16*8-1 : 0] out;
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : sb
sbox s (
.in (in[8*i+7:8*i]),
.out(out[8*i+7:8*i])
);
end
endgenerate
endmodule
| 6.930515 |
module inv_sub_bytes (
in,
out
);
input [16*8-1 : 0] in;
output [16*8-1 : 0] out;
wire [16*8-1 : 0] out;
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : sb
inv_sbox s (
.in (in[8*i+7:8*i]),
.out(out[8*i+7:8*i])
);
end
endgenerate
endmodule
| 6.81424 |
module is a test bench for the sub_byte. The output of test bench is
// a pass or fail results passed on the obtained values.
`timescale 1ns / 100ps
module sub_byte_tb;
reg startTransition;
reg clock50MHz;
reg [127:0] inputValue;
reg [127:0] expectedValue;
wire [127:0] outputValue;
sub_byte dut(
.subByteInput (i... | 6.595812 |
module SUB_CLA_2 (
iG,
iP,
iC,
oG,
oP,
oC
);
input [1:0] iG, iP;
input iC;
output oG, oP;
output [2:0] oC;
assign oC[0] = iC;
assign oC[1] = iG[0] | (iP[0] & oC[0]);
assign oG = iG[1] | (iP[1] & iG[0]);
assign oP = iP[1] & iP[0];
assign oC[2] = oG | (oP & oC[0]);
endmodul... | 7.185222 |
module SUB_CLA_24 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [23:0] iA, iB;
input iC;
output [23:0] oS;
output oG, oP, oC;
wire [2:0] G, P, C;
SUB_CLA_8 sub0 (
.iA(iA[7:0]),
.iB(iB[7:0]),
.iC(C[0]),
.oS(oS[7:0]),
.oG(G[0]),
.oP(P[0]),
.oC(... | 7.790524 |
module SUB_CLA_4 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [3:0] iA, iB;
input iC;
output [3:0] oS;
output oG, oP, oC;
wire [3:0] G, P, C;
assign G = (~iA) & iB;
assign P = iA ^~ iB;
CLA_4 ADD_CLA_4_ (
.iG(G),
.iP(P),
.iC(iC),
.oG(oG),
.oP(oP),
... | 7.222282 |
module SUB_CLA_8 (
iA,
iB,
iC,
oS,
oG,
oP,
oC
);
input [7:0] iA, iB;
input iC;
output [7:0] oS;
output oG, oP, oC;
wire [1:0] G, P, C;
SUB_CLA_4 sub0 (
.iA(iA[3:0]),
.iB(iB[3:0]),
.iC(C[0]),
.oS(oS[3:0]),
.oG(G[0]),
.oP(P[0]),
.oC()
... | 8.464706 |
module SUB_CLA_8_tb ();
reg [7:0] iA, iB;
reg iC;
wire [7:0] oS;
wire oG, oP, oC;
SUB_CLA_8 SUB_CLA_8_ (
.iA(iA),
.iB(iB),
.iC(iC),
.oS(oS),
.oG(oG),
.oP(oP),
.oC(oC)
);
initial begin
#0;
iA = 8'd125;
iB = 8'd11;
iC = 1'b0;
#10;
... | 6.723066 |
module sub_control_ID_EX_stage (
input signal_sub,
input clock,
output reg out_sub_control_reg
);
always @(posedge clock) out_sub_control_reg = signal_sub;
endmodule
| 6.703082 |
module sub_deparser #(
parameter C_PKT_VEC_WIDTH = (6 + 4 + 2) * 8 * 8 + 20 * 5 + 256,
parameter C_PARSE_ACT_LEN = 6 // only 6 bits are used here
) (
input clk,
input aresetn,
input parse_act_valid,
input [C_PARSE_ACT_LEN-1:0] parse_act,
... | 6.769988 |
module sub_edge_sum (
input clk,
input rst,
input [5:0] din,
output reg [4:0] sum_position_tmp,
output reg [2:0] num_edge_tmp
);
always @(posedge clk or posedge rst) begin
if (rst) begin
sum_position_tmp <= 0;
num_edge_tmp <= 0;
end else begin
sum_position_tmp = din[0]*... | 6.587314 |
module sub_fast (
input clk,
input [31:0] a,
input [31:0] b,
output [31:0] res
);
floating_point_5 sub_core (
.aclk (clk), // input wire aclk
.s_axis_a_tvalid ('b1), // input wire s_axis_a_tvalid
.s_axis_a_tready (s_axis_a_t... | 6.640754 |
module sub_full (
S,
C_out,
A,
B,
C_in
);
input A, B, C_in;
output S, C_out;
wire temp_S, first_C_out, second_C_out;
sub_half first_S (
temp_S,
first_C_out,
A,
B
);
sub_half second_S (
S,
second_C_out,
temp_S,
C_in
);
or final_C_out (... | 6.80851 |
module sub_func (
X,
Y,
diff,
overflow
);
//parameter definitions
//port definitions - customize for different bit widths
input wire [31:0] X;
input wire [31:0] Y;
output wire [31:0] dif;
output wire overflow;
wire if_do = 0; //this here means we will invert, because this follows op_cod... | 7.213675 |
module sub_half (
S,
C,
A,
B
);
input A, B;
output S, C;
wire Anot;
xor (S, A, B);
not (Anot, A);
and (C, Anot, B);
endmodule
| 7.152518 |
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