code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sum_rest_disp_p1 (
input [3:0] a,
input [3:0] b,
input sum_rest,
input clk,
output [6:0] disp,
output [3:0] transistor
);
wire [6:0] count;
wire [3:0] out;
wire [3:0] co;
wire mux_disp;
adder_subs i_adder_subs (
.a (a),
.b (b),
.sel(sum_rest),
.s (out... | 7.106596 |
module sum_sync_mem #(
parameter AWIDTH = 10,
parameter DWIDTH = 32,
parameter DEPTH = 1024,
parameter MEM_INIT_HEX_FILE = ""
) (
input clk,
input reset,
output done,
input [31:0] size,
output [31:0] sum
);
// TODO: Fill in the remaining logic to compute the sum of memory data fro... | 8.4127 |
module sum_sync_mem_tb ();
localparam AWIDTH = 10;
localparam DWIDTH = 32;
localparam DEPTH = 1024;
reg clk;
initial clk = 0;
always #(4) clk <= ~clk;
reg reset;
reg [31:0] size;
wire [DWIDTH-1:0] sum;
wire done;
sum_sync_mem #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH),
.DEPTH(DEPTH),... | 7.602181 |
module counter input
CLR: module counter input
out_num: output port for the counter module, 8 bits
sel: for selection, 2 bits
OV: overflow flag
------------------------------------------------------
History:
12-11-2015: First Version by Garfield
*******************************************... | 7.206611 |
module P_to_BCD_8bit (
input [7:0] P,
output reg [3:0] BCD0,
BCD1,
BCD2
);
reg [7:0] PVar;
reg [3:0] B0, B1, B2;
always @(P) begin
PVar = P;
B0 = PVar % 8'b0000_1010;
PVar = PVar / 8'b0000_1010;
B1 = PVar % 8'b0000_1010;
PVar = PVar / 8'b0000_1010;
B2 = PVar;
BCD... | 7.301694 |
module moduleName (
input clk,
input rst_n,
input vld,
input [15:0] data_in,
output reg [23:0] sum,
output reg done,
);
reg [23:0] sum_all;
reg vld_d1;
wire fallen_vld;
reg fallen_vld_d1;
reg [15:0] max;
reg [15:0] min;
always @(posedge clk or negedge rst_n) begin... | 8.443212 |
module inv (
input A,
output Y
);
assign Y = ~A;
endmodule
| 7.812163 |
module tri_inv (
input A,
input S,
output reg Y
);
always @(*) begin
if (S == 1'b0) begin
Y <= 1'bz;
end else begin
Y <= ~A;
end
end
endmodule
| 7.509959 |
module buffer (
input A,
output Y
);
assign Y = A;
endmodule
| 6.861394 |
module nand2 (
input A,
input B,
output Y
);
assign Y = ~(A & B);
endmodule
| 7.360689 |
module nor2 (
input A,
input B,
output Y
);
assign Y = ~(A | B);
endmodule
| 7.781479 |
module xor2 (
input A,
input B,
output Y
);
assign Y = A ^ B;
endmodule
| 8.782532 |
module imux2 (
input A,
input B,
input S,
output Y
);
assign Y = ~(S ? A : B);
endmodule
| 9.412521 |
module dff (
input CLK,
input D,
input RESET,
input PRESET,
output reg Q,
output reg QN
);
always @(CLK or RESET or PRESET) begin
if (RESET) begin
Q <= 1'b0;
QN <= 1'b1;
end else if (PRESET) begin
Q <= 1'b1;
QN <= 1'b0;
end else if (CLK) begin
Q <= ... | 7.174483 |
module aoi211 (
input A,
input B,
input C,
output Y
);
assign Y = ~((A & B) | C);
endmodule
| 8.072296 |
module oai211 (
input A,
input B,
input C,
output Y
);
assign Y = ~((A | B) & C);
endmodule
| 8.027893 |
module fulladder (
input A,
input B,
input CI,
output CO,
output Y
);
assign Y = (A ^ B) ^ CI;
assign CO = ((A & B) | (B & CI)) | (CI & A);
endmodule
| 7.454465 |
module superOS (
clk_clk,
led_export,
reset_reset_n
);
input clk_clk;
output [7:0] led_export;
input reset_reset_n;
endmodule
| 6.727399 |
module superOS_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
w... | 7.202128 |
module superOS_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
... | 7.202128 |
module superOS_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:... | 7.202128 |
module superOS_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input ... | 7.202128 |
module superOS_memory (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "superOS_memory.hex";
output [31:0] readdata;
input [12:0] address;
input [3:0] byteen... | 6.982809 |
module arithmetic_logic_unit (
op,
alu1,
alu2,
bus
);
input [2:0] op;
input [15:0] alu1;
input [15:0] alu2;
output [15:0] bus;
assign bus = (op == `ADD) ? alu1 + alu2 : (op == `NAND) ? ~(alu1 & alu2) : alu2;
endmodule
| 6.612484 |
module IFID (
clk,
reset,
IFID_we,
IFID_instr__in,
IFID_pc__in,
IFID_instr__out,
IFID_pc__out
);
input clk, reset, IFID_we;
input [15:0] IFID_instr__in, IFID_pc__in;
output [15:0] IFID_instr__out, IFID_pc__out;
wire clk_A, clk_B, clk_C, clk_D, clk_E, clk_F, clk_G, clk_H,
res_A, r... | 8.278578 |
module IDEX (
clk,
reset,
IDEX_op0__in,
IDEX_op1__in,
IDEX_op2__in,
IDEX_op__in,
IDEX_rT__in,
IDEX_x__in,
IDEX_pc__in,
IDEX_op0__out,
IDEX_op1__out,
IDEX_op2__out,
IDEX_op__out,
IDEX_rT__out,
IDEX_x__out,
IDEX_pc__out
);
input clk, reset;
input [15:0]... | 6.523922 |
module EXMEM (
clk,
reset,
EXMEM_stdata__in,
EXMEM_ALUout__in,
EXMEM_op__in,
EXMEM_rT__in,
EXMEM_x__in,
EXMEM_pc__in,
EXMEM_stdata__out,
EXMEM_ALUout__out,
EXMEM_op__out,
EXMEM_rT__out,
EXMEM_x__out,
EXMEM_pc__out
);
input clk, reset;
input [15:0] EXMEM_stdat... | 6.790538 |
module SuperTopEntity ( // Inputs
input CLOCK // clock
, input RESET // asynchronous reset: active high
, input RX
, input SDO
, input BUTRST
// Output
, output wire MANRST
, output wire TX
, output wire [6:0] LED
, output wire CLK_OUT
, output wire [2:0] C1
, ou... | 7.49293 |
module super_display (
input clk,
input rst,
input [3:0] sel_in,
input [15:0] dat,
output [3:0] sel,
output [7:0] c
);
//reg [15:0] data;
integer counter;
reg [3:0] temp_data;
reg [3:0] temp_sel;
reg [1:0] state;
parameter freq = 10000000;
localparam bond = freq / 1000;
always @(... | 8.32471 |
module display_HEX (
input [3:0] S,
output [6:0] H
);
assign H[0] = ~S[3]&~S[2]&~S[1]&S[0] | ~S[3]&S[2]&~S[1]&~S[0] | S[3]&~S[2]&S[1]&S[0] | S[3]&S[2]&~S[1]&S[0];
assign H[1] = ~S[3]&S[2]&~S[1]&S[0] | ~S[3]&S[2]&S[1]&~S[0] | S[3]&~S[2]&S[1]&S[0] | S[3]&S[2]&~S[1]&~S[0] | S[3]&S[2]&S[1];
assign H[2] = ~S... | 6.533988 |
module super_stop_watch_test (
output [3:0] en0,
en1,
output [7:0] sseg0,
sseg1,
input [31:0] show_data,
input clk
);
scan_hex_led_disp scan_hex_led_disp_unit0 (
.clk(clk),
.reset(1'b0),
.hex3(show_data[15:12]),
.hex2(show_data[11:8]),
.hex1(show_data[7:4]),
... | 6.815538 |
module super_top_level (
input clk,
input btns,
input btnu,
input btnl,
input btnd,
input btnr,
input rst,
input [3:0] sw,
input SDI,
output [7:0] Led,
output [2:0] vgaRed,
output [2:0] vgaGreen,
output [2:1] vgaBlue,
output Hsync,
output Vsync,
output SDO... | 7.502277 |
module test;
supply0 gnd;
supply1 vdd;
initial begin
#1;
if (gnd !== 0) begin
$display("FAILED -- gnd == %b", gnd);
$finish;
end
if (vdd !== 1) begin
$display("FAILED -- vdd == %b", vdd);
$finish;
end
$display("PASSED");
end
endmodule
| 6.553995 |
module test;
supply0 gnd;
supply1 vdd;
// These should drop away as meaningless.
assign gnd = 1;
assign vdd = 0;
initial begin
#1
if (gnd !== 0) begin
$display("FAILED -- gnd == %b", gnd);
$finish;
end
if (vdd !== 1) begin
$display("FAILED -- vdd == %b", vdd);
$fi... | 6.553995 |
module rom2764 #(
parameter INIT_FILE = "rom.txt"
) (
input clk,
input [12:0] addr,
output reg [7:0] data
);
reg [7:0] mem[0:8191];
always @(posedge clk) data <= mem[addr];
initial begin
$readmemh(INIT_FILE, mem);
end
endmodule
| 7.756638 |
module dprom2764 (
input a_clk,
input [12:0] a_addr,
output reg [7:0] a_data,
input b_clk,
b_we,
input [12:0] b_addr,
input [7:0] b_data
);
reg [7:0] mem[0:8191];
always @(posedge a_clk) a_data <= mem[a_addr];
always @(posedge b_clk) if (b_we) mem[b_addr] <= b_data;
endmodule
| 7.213826 |
module sram (
input clk,
input we,
input [10:0] addr,
input [7:0] din,
output reg [7:0] dout
);
reg [7:0] mem[0:2047];
always @(posedge clk) begin
if (we) mem[addr] <= din;
else dout <= mem[addr];
end
endmodule
| 7.547687 |
module moram (
input clk,
input we,
cs,
input [7:0] addr,
input [3:0] din,
output reg [3:0] dout
);
reg [3:0] mem[0:255];
always @(posedge clk) begin
if (we & cs) mem[addr] <= din;
else dout <= mem[addr];
end
endmodule
| 7.193837 |
module cram82S09 (
input clk,
input we,
input [4:0] addr,
input [8:0] din,
output reg [8:0] dout
);
reg [8:0] mem[0:31];
always @(posedge clk) begin
if (we) mem[addr] <= din;
else dout <= mem[addr];
end
initial begin
$readmemh("cram.rom", mem); // initial colors at boot
end... | 7.026823 |
module PokeyW (
input clk,
input ce,
input rst_n,
input [3:0] ad,
input cs,
input we,
input [7:0] data_to_pokey,
output [7:0] data_from_pokey,
output [5:0] snd,
input [7:0] p
);
wire [3:0] ch0, ch1, ch2, ch3;
pokey core (
.reset_n(rst_n),
.clk(clk),
.ce(ce)... | 7.366478 |
module LETA (
input clk,
reset_n,
input X1,
Y1,
X2,
Y2,
X3,
Y3,
X4,
Y4,
input [1:0] addr,
output reg [7:0] data
);
wire [7:0] data1, data2, data3, data4;
quad_decoder qd1 (
.clk(clk),
.reset_n(reset_n),
.A(X1),
.B(Y1),
.count(data1)
);... | 6.640609 |
module surf4_debug(
input wbc_clk_i,
input clk0_i,
input clk1_i,
`WBM_NAMED_PORT(wbvio, 32, 20, 4),
input [70:0] wbc_debug_i,
input [70:0] ice_debug_i,
input [70:0] lab4_i2c_debug_i,
input [23:0] i2c_debug_i,
input [70:0] rfp_debug_i,
output [7:0] global_debug_o
);
reg [70:0] ila0_debug = {71{... | 7.414675 |
module surf4_hk_collector(
input clk_i,
input rst_i,
`WBS_NAMED_PORT(wbsc, 32, 16, 4),
`WBM_NAMED_PORT(wbmc, 32, 20, 4),
input pps_i,
// external ports (MGT_1V/MGT_VTT)
input MGT1V_P,
input MGT1V_N,
input MGT1P2_P,
input MGT1P2_N
);
// The HK collector handles housekeeping stuff. It's called a... | 9.000491 |
module: surf4_id_ctrl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`include "wishbone.vh"
module surf4_id_ctrl_tb;
// Inputs
reg clk_i;
reg rst_i;
`WB_DEFINE(wb, 32, 16, 4);
wire... | 7.482888 |
module surf5_debug(
input wbc_clk_i,
input clk0_i,
input clk1_i,
input clk_big_i,
`WBM_NAMED_PORT(wbvio, 32, 20, 4),
input [70:0] clk0_debug0_i,
input [70:0] clk0_debug1_i,
input [70:0] clk0_debug2_i,
input [70:0] clk0_debug3_i,
input [70:0] clk1_debug_i,
input [14:0] clk_big_debug_i,
output [7:... | 7.59826 |
module surf5_phase_scanner(
input clk_i,
input rst_i,
`WBS_NAMED_PORT(wb, 32, 1, 4),
output ps_en_o,
output ps_incdec_o,
input ps_done_i,
input sync_i,
input clk_ps_i,
inout sync_mon_io,
input [11:0] MONTIMING_B,
output [11:0] montiming_q_o,
output sync_q_o,
output scan_valid_o,
output... | 7.585902 |
module suspicious_object_detector (
input clk,
input resetn,
input i2c_config_done,
input capture_pixel,
input [16:0] capture_addr,
input capture_wren,
input [15:0] detection_thres,
input [15:0] static_thres,
input [15:0] suspicion_thres,
... | 7.107474 |
module testbench;
reg clk_sys;
reg rst_n;
reg state_start;
reg [3:0] dump_sustain_data;
reg clk_10k;
initial begin
rst_n = 1'b0;
state_start = 1'b0;
dump_sustain_data = 4'd0;
clk_sys = 1'b0;
clk_10k = 1'b0;
end
initial begin
#500000 rst_n = 1'b1;
state_start = 1'b1;
du... | 7.015571 |
module suTwosComp #(
parameter DATA_WIDTH = 8
) (
X_parallel,
enable,
reset,
Clk,
X_pos
);
input [DATA_WIDTH-1:0] X_parallel;
input enable, reset, Clk;
output [DATA_WIDTH-1:0] X_pos;
reg [DATA_WIDTH-1:0] X_pos;
always @(posedge Clk or posedge reset)
if (reset) begin //non-blockin... | 6.798455 |
module check_par (
clk,
parity,
data
);
input clk, parity;
input [31:0] data;
property p_check_par;
@(posedge clk) (^(data ^ parity)) == 1'b0;
endproperty
a_check_par :
assert property (p_check_par);
endmodule
| 7.129536 |
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b, signal;
default clocking @(posedge clk);
endclocking
initial forever #10 clk = !clk;
realtime duration = 45.0ns;
property glitch_p;
realtime first_change;
// realtime duration = 10;
@(signal) // pos and neg edge
// detecting ... | 7.408481 |
module svca (
in,
cv,
signal_out
); //
parameter WIDTH = 8; //
input wire [(WIDTH-1):0] in, cv;
output wire [(WIDTH-1):0] signal_out;
wire signed [(WIDTH):0] s_in = in - 8'd128; // 0..255 -> signed -128..127
wire signed [(WIDTH):0] s_cv = cv;
wire signed [(WIDTH*2):0] result_s = s_in * s_... | 7.466967 |
module SVC_Vote_mux_104_bkb #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
... | 7.186634 |
module SVD_interface_tb ();
reg clk;
reg rst;
reg we;
reg oe;
reg [4:0] data_i;
reg [1:0] element_sel;
wire ready;
wire [7:0] data_o_UV;
wire [6:0] data_o_S;
SVD_interface svd (
.clk(clk),
.rst(rst),
.we(we),
.oe(oe),
.data_i(data_... | 7.25109 |
module SVD_tb ();
reg clk;
reg rst;
reg we;
reg oe;
reg [4:0] data_i;
reg [1:0] element_sel;
wire ready;
wire [7:0] data_o_UV;
wire [6:0] data_o_S;
SVD svd (
.clk(clk),
.rst(rst),
.we(we),
.oe(oe),
.data_i(data_i),
.element_s... | 7.039789 |
module video (
output [15:0] RGB,
output reg HSync = 1,
output reg VSync = 1,
output [13:0] PIXADDR,
input [7:0] PIXDATA,
input PixClock
);
//reg [15:0]COLOR;
reg [7:0] SHIFT;
assign RGB = {
wCOLOR[15:11], // RED:5
wCOLOR[10:5], // GREEN:6
wCOLOR[4:0] // BLUE:5
... | 6.925225 |
module video (
output [8:0] RGB,
output reg HSync = 1,
output reg VSync = 1,
output [13:0] PIXADDR,
input [7:0] PIXDATA,
input PixClock
);
//reg [15:0]COLOR;
reg [7:0] SHIFT;
assign RGB = {
wCOLOR[8:6], // RED:5
wCOLOR[5:3], // GREEN:6
wCOLOR[2:0] // BLUE:5
};
... | 6.925225 |
module TopModule (
input logic clk,
input logic rst,
input logic [1:0] sig,
input logic flip,
output logic [15:0] passThrough,
output logic [21:0] outOther,
output logic [1:0] sig_out
);
logic MyInterfaceInstance_setting;
logic [3:0] MyInterfaceInstance_other_setting;
logic [1:0] MyI... | 6.503818 |
module SubModule1 (
input logic clk,
input logic rst,
input logic u_MyInterface_setting,
output logic [3:0] u_MyInterface_other_setting,
output logic [1:0] u_MyInterface_mysig_out,
output logic [21:0] outOther,
input logic [1:0] sig,
output logic [15:0] passThrough
);
always @(posedge... | 6.770638 |
module TopModule (
input logic clk,
input logic rst,
input logic [1:0] sig,
input logic flip,
output logic [15:0] passThrough,
output logic [21:0] outOther,
input logic interfaceInstanceAtTop_setting,
output logic [2:0] interfaceInstanceAtTop_other_setting,
output logic [1:0] interfa... | 6.503818 |
module SubModule1 (
input logic clk,
input logic rst,
input logic u_MyInterface_setting,
output logic [3:0] u_MyInterface_other_setting,
output logic [1:0] u_MyInterface_mysig_out,
output logic [21:0] outOther,
input logic [1:0] sig,
input logic u_MyInterfaceFromTop_setting,
output l... | 6.770638 |
module svm_detection_test_v;
// Inputs
reg [`SVM_PARAM_WIDTH * `SVM_PARAM_COUNT - 1:0] x;
reg data_valid;
reg clk;
reg reset;
// Outputs
wire [`SVM_CLASS_WIDTH - 1:0] class;
wire ready;
wire new_result;
reg error;
// Instantiate the Unit Under Test (UUT)
svm_detection uut (
.x(x),
.data_valid(dat... | 6.971674 |
module
`timescale 1ns / 1ps
`include "../config/svm_parameters.v"
module svm_kernel_test;
// Inputs
reg [`SVM_PARAM_WIDTH * `SVM_PARAM_COUNT - 1:0] x;
reg [`SVM_PARAM_WIDTH * `SVM_PARAM_COUNT - 1:0] sv;
reg [`SVM_CLASS_WIDTH - 1:0] sv_class;
reg [(`SVM_COEF_WIDTH_INT + `SVM_COEF_WIDTH_FRAC) * (`SVM_CLASS_COUNT... | 6.608387 |
module svo_pong
//
// a clone of the Atari 1972 game PONG. this is implemented as a video
// filter with enable input. when enabled it will overlay the game on the
// video stream. connect .auto_btn with .btn to let the game play against
// itself.
// --------------------------------------------------------------------... | 7.003866 |
module svo_axis_pipe
//
// this core is a simple helper for creating video pipeline cores with
// an axi stream interface.
// ----------------------------------------------------------------------
module svo_axis_pipe #(
parameter TDATA_WIDTH = 8,
parameter TUSER_WIDTH = 1
) (
input clk, resetn,
// axis input str... | 7.843568 |
module svo_buf
//
// just a buffer that adds an other ff layer to the stream.
// ----------------------------------------------------------------------
module svo_buf #(
parameter TUSER_WIDTH = 1,
`SVO_DEFAULT_PARAMS
) (
input clk, resetn,
// input stream
// tuser[0] ... start of frame
input in_axis_tvalid,
... | 7.290203 |
module svo_dim
//
// this core dims the video data (half each r/g/b sample value) when
// the enable input is high. it is also a nice demo of how to create
// simple pipelines that integrate with axi4 streams.
// ----------------------------------------------------------------------
module svo_dim #( `SVO_DEFAULT_PARA... | 6.968906 |
module svo_overlay
//
// overlay one video stream ontop of another one
// ----------------------------------------------------------------------
module svo_overlay #( `SVO_DEFAULT_PARAMS ) (
input clk, resetn, enable,
// input stream
// tuser[0] ... start of frame
input in_axis_tvalid,
output in_axis_tready,
... | 6.882282 |
module SVPWM (
iClk,
iRst_n,
iModulate_en,
iValpha,
iVbeta,
oPWM_u,
oPWM_v,
oPWM_w,
oModulate_done
);
input wire iClk;
input wire iRst_n;
input wire iModulate_en;
input wire [15:0] iValpha, iVbeta;
output wire oPWM_u, oPWM_v, oPWM_w;
output wire oModulate_done;
wire [2... | 6.694093 |
module SVPWM_Analyse_Sector (
iClk,
iRst_n,
iAS_en,
iA,
iB,
iC,
oSector,
oAS_done
);
input wire iClk;
input wire iRst_n;
input wire iAS_en;
input wire iA, iB, iC;
output reg [2:0] oSector;
output reg oAS_done;
localparam Sector_1 = 3'd1;
localparam Sector_2 = 3'd2;
loc... | 7.994209 |
module wrapper_norm_corr_20 (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5,
corr_out_6,
corr_out_7,
corr_out_8,
corr_out_9,
corr_out_10,
corr_out_11,
corr_out_12,
corr_out_13,
... | 6.699338 |
module wrapper_norm_corr_10 (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5,
corr_out_6,
corr_out_7,
corr_out_8,
corr_out_9,
corr_out_10
);
parameter sh_reg_w = 4'b1000;
input clk;
i... | 6.699338 |
module wrapper_norm_corr_5_seq (
clk,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5
);
parameter sh_reg_w = 4'b1000;
input clk;
input wen;
input [15:0] d_l_1;
input [15:0] d_l_2;
input [15:0] d_r_1;
... | 6.699338 |
module wrapper_corr_5_seq (
tm3_clk_v0,
wen,
d_l_1,
d_l_2,
d_r_1,
d_r_2,
corr_out_0,
corr_out_1,
corr_out_2,
corr_out_3,
corr_out_4,
corr_out_5
);
parameter sh_reg_w = 4'b1000;
input tm3_clk_v0;
input wen;
input [7:0] d_l_1;
input [7:0] d_l_2;
input [7:0] d_... | 6.720326 |
module wrapper_norm_seq (
clk,
nd,
din_1,
din_2,
dout_1,
dout_2
);
parameter sh_reg_w = 4'b1000;
input clk;
input nd;
input [15:0] din_1;
input [15:0] din_2;
output [sh_reg_w - 1:0] dout_1;
wire [sh_reg_w - 1:0] dout_1;
output [sh_reg_w - 1:0] dout_2;
wire [sh_reg_w - 1:0] dou... | 6.699338 |
module my_wrapper_divider (
rst,
clk,
data_in_a,
data_in_b,
data_out
);
parameter INPUT_WIDTH_A = 5'b10000;
parameter INPUT_WIDTH_B = 5'b10001;
parameter OUTPUT_WIDTH = 4'b1000;
parameter S1 = 2'b00;
parameter S2 = 2'b01;
parameter S3 = 2'b10;
parameter S4 = 2'b11;
input rst;
inp... | 7.258611 |
module my_divider (
clk,
rst,
start,
LA,
EB,
data_in_a,
data_in_b,
Remainder,
data_out,
Done
);
parameter INPUT_WIDTH_A = 5'b10000;
parameter INPUT_WIDTH_B = 5'b10001;
parameter OUTPUT_WIDTH = 4'b1000;
parameter LOGN = 3'b100;
parameter S1 = 2'b00;
parameter S2 = 2'... | 7.482014 |
module my_fir_f1 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=29,101,-15,-235,-15,101,29;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data... | 7.162286 |
module my_fir_f2 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=4,42,163,255,163,42,4;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_rea... | 7.093413 |
module my_fir_f3 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-12,-77,-148,0,148,77,12;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_r... | 7.589128 |
module my_fir_h1 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-15,25,193,0,-193,-25,15;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_... | 7.258261 |
module my_fir_h2 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=4,42,163,255,163,42,4;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_read... | 7.118788 |
module my_fir_h3 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-9,-56,-109,0,109,56,9;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_read... | 7.61466 |
module my_fir_h4 (
clk,
new_data_rdy,
output_data_ready,
din,
dout
);
//coefdata=-9,-56,-109,0,109,56,9;
parameter WIDTH = 5'b10000;
input clk;
input [WIDTH - 1:0] din;
output [28 - 1:0] dout;
reg [28 - 1:0] dout;
input new_data_rdy;
output output_data_ready;
reg output_data_read... | 7.756091 |
module dff1 (
output bit_t q,
input bit_t,
d,
clk,
resetb
);
always_ff @(posedge clk, negedge resetb) begin
if (!resetb) q <= 0;
else q <= d;
end
endmodule
| 6.627306 |
module mux3c (
output reg y,
input [1:0] sel,
input a,
b,
c
);
always @*
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
default: y = 1'bx;
endcase
endmodule
| 7.807275 |
module wb_env_top_mod ();
logic clk;
logic rst;
// Clock Generation
parameter sim_cycle = 10;
// Reset Delay Parameter
parameter rst_delay = 10;
initial begin
clk = 0;
#10;
forever clk = #(sim_cycle / 2) ~clk;
#10000 $finish;
end
wb_master_if mast_if (
clk,
rst
);
w... | 7.074495 |
module sw6 (
input [7:0] a,
output reg [2:0] y
);
// With 1 volt/step, step size is approximately 51/volt.
// Thresholds pick the midpoints between voltage ranges.
localparam THRESHOLD_0_1 = 26; // 0-1 volts
localparam THRESHOLD_1_2 = 76; // 1-2 volts
localparam THRESHOLD_2_3 = 127; // 2-3 volts
... | 6.65049 |
module SW7seg (
SW,
HEX0
);
input [3:0] SW;
output [6:0] HEX0;
// Your code for Phase 2 goes here. Be sure to check the Slide Set 2 notes,
// since one of the slides almost gives away the answer here. I wrote this as
// a single combinational always block containing a single case statement, but
... | 8.016256 |
module SwAlloc2x1 (
input wire clk,
input wire rstn,
input wire ValidA_i,
input wire [31:0] DataA_i,
output wire ReadyA_o,
input wire ValidB_i,
input wire [31:0] DataB_i,
output wire ReadyB_o,
input wire FifoFull_i,
output wire [31:0] Fi... | 7.324019 |
module SwAlloc3x1 (
input wire clk,
input wire rstn,
input wire ValidA_i,
input wire [31:0] DataA_i,
output wire ReadyA_o,
input wire ValidB_i,
input wire [31:0] DataB_i,
output wire ReadyB_o,
input wire ValidC_i,
input wire [31:0] Data... | 7.455022 |
module swap (
input a,
b,
output x,
y
);
assign x = a ^ (a ^ b);
assign y = b ^ (a ^ b);
endmodule
| 8.099526 |
modules.
//
// Params: None
//------------------------------------------------------------------------------
module SwapController(
input clock,
input reset,
output reg swap,
input swap_ack,
output reg bg_start,
input bg_start_ack,
input bg_done,
output reg bg_done_ack);
reg bg_done_ack_r;
wire b... | 6.877912 |
module performs the swap logic in each round.
module Swapper(
input [31:0] i_LPT,
input [31:0] i_RPT,
output [31:0] o_LPT,
output [31:0] o_RPT
);
assign o_LPT = i_RPT;
assign o_RPT = i_LPT;
endmodule
| 7.634754 |
module swap_data (
a_input,
b_input,
out_sel,
swap_en,
data_out
);
/**
* SWAP DATA REGISTER FILE - swap_data.v
*Inputs:
* -a_input (32bits): Data to be swapped from RS
* -b_input (32bits): Data to be swapped from RT
* -out_sel 1 bit: choose which register to output to multiplexer. multiplexer i... | 8.022415 |
module swap_endian #(
parameter UNIT_WIDTH = 8,
parameter UNIT_COUNT = 4
) (
input wire [(UNIT_WIDTH*UNIT_COUNT)-1:0] src,
output reg [(UNIT_WIDTH*UNIT_COUNT)-1:0] dst
);
integer i;
always @* begin
for (i = 0; i < UNIT_COUNT; i = i + 1) begin
dst[(i*UNIT_WIDTH)+:UNIT_WIDTH] = src[((UNIT... | 6.594776 |
module swap_endianness #(
parameter WIDTH = 32
) (
input wire [WIDTH-1 : 0] in_vect,
output wire [WIDTH-1 : 0] out_vect
);
localparam WIDTH_BYTES = WIDTH / 8;
generate
genvar i;
for (i = 0; i < WIDTH_BYTES; i = i + 1) begin
assign out_vect[i*8+:8] = in_vect[(WIDTH-1)-(i*8)-:8];
end
... | 6.877557 |
module swap_fsm (
input clk,
reset_n,
input swap,
output w,
output [1:0] sel
);
reg [1:0] state_reg, state_next;
parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3;
// Sequential state register
always @(posedge clk, negedge reset_n) begin
if (~reset_n) state_reg <= s0;
else state_reg <= stat... | 7.249526 |
module swap_reg (
a_input,
b_input,
out_sel,
data_out
);
/**
* SWAP REG REGISTER FILE - swap_reg.v
*Inputs:
* -a_input (4bits): Address of RS
* -b_input (4bits): Address of RT
* -out_sel 1 bit: choose which register to output to multiplexer. multiplexer inputs into rf
* 0 -> swap rs; 1-> swap rt
*... | 7.24337 |
module swap_reg_file #(
parameter ADDR_WIDTH = 7,
DATA_WIDTH = 8
) (
input clk,
reset_n,
input we,
input [ADDR_WIDTH - 1:0] address_w,
address_r,
input [DATA_WIDTH - 1:0] data_w,
output [DATA_WIDTH - 1:0] data_r,
// inputs for swap functionality
input [ADDR_WIDTH - 1:0] addr... | 7.494731 |
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