code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module swap_reg_file_tb ();
localparam ADDR_WIDTH = 7;
localparam DATA_WIDTH = 8;
reg clk, reset_n;
reg we;
reg [ADDR_WIDTH - 1:0] address_w, address_r;
reg [DATA_WIDTH - 1:0] data_w;
wire [DATA_WIDTH - 1:0] data_r;
reg [ADDR_WIDTH - 1:0] address_A, address_B;
reg swap;
integer i;
// Instantiat... | 7.494731 |
module swap_tb ();
reg clk, rst, load;
reg [3:0] data_in0, data_in1, data_in2, data_in3, data_in4, data_in5, data_in6, data_in7;
wire [3:0] data_out0, data_out1, data_out2, data_out3, data_out4, data_out5, data_out6, data_out7;
initial begin
#0 rst = 0;
#0 clk = 0;
#0 load = 0;
#5 data_in0 = 8;... | 7.589824 |
module swBUF (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q
);
input clock;
input [31:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [31:0] q;
wire sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2;
wire empty = sub_wire0;
w... | 7.116942 |
module swBUF (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q
);
input clock;
input [31:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [31:0] q;
endmodule
| 7.116942 |
module swDac #(
parameter width = 4,
sample_time = 128 /*Default 32768 Hz*/
) (
input clk,
input [width-1:0] left,
input [width-1:0] right
);
fixedTimer #(sample_time) timer (
clk,
sampleClk
);
initial $display("%d %d", width, sample_time); // begin with params so we can interp... | 6.674944 |
module Swept (
input i_clk,
output reg [3:0] o_Row
);
reg [1:0] r_count = 0;
always @(posedge i_clk) begin
case (r_count)
2'b00: o_Row <= 4'b1000;
2'b01: o_Row <= 4'b0100;
2'b10: o_Row <= 4'b0010;
2'b11: o_Row <= 4'b0001;
endcase
r_count <= r_count + 1;
end
endmodule... | 6.620203 |
module SevSegDisplays_Controller (
input wire clk,
input wire rst_n,
input wire [ 7:0] Enables_Reg,
input wire [31:0] Digits_Reg,
output wire [ 7:0] AN,
output wire [ 6:0] Digits_Bits
);
wire [(COUNT_MAX-1):0] countSelection;
wire [3:0] DecNumber;
wire overflow_o_count;
... | 6.733215 |
module SevenSegDecoder (
input wire [3:0] data,
output reg [6:0] seg
);
always @(*)
case (data)
// abc_defg
4'h0: seg = 7'b000_0001;
4'h1: seg = 7'b100_1111;
4'h2: seg = 7'b001_0010;
4'h3: seg = 7'b000_0110;
4'h4: seg = 7'b100_1100;
4'h5: seg = 7'b010_0100;
... | 7.177629 |
module SevSegMux #(
parameter DATA_WIDTH = 64,
parameter N_IN = 16,
parameter SEL_WIDTH = $clog2(N_IN)
) (
input wire [ N_IN-1:0][DATA_WIDTH-1:0] IN_DATA,
output wire [DATA_WIDTH-1:0] OUT_DATA,
input wire [ SEL_WIDTH-1:0] SEL
);
assign OUT_DATA =... | 9.048564 |
module rvclkhdr (
en,
clk,
scan_mode,
l1clk
);
input en;
input clk;
input scan_mode;
output l1clk;
wire l1clk;
clockhdr rvclkhdr (
.TE(scan_mode),
.E (en),
.CP(clk),
.Q (l1clk)
);
endmodule
| 6.611808 |
module rvdff_WIDTH1 (
din,
clk,
rst_l,
dout
);
input [0:0] din;
output [0:0] dout;
input clk;
input rst_l;
wire N0;
reg [0:0] dout;
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[0] <= 1'b0;
end else if (1'b1) begin
dout[0] <= din[0];
end
end
as... | 6.586933 |
module rvdffsc_WIDTH1 (
din,
en,
clear,
clk,
rst_l,
dout
);
input [0:0] din;
output [0:0] dout;
input en;
input clear;
input clk;
input rst_l;
wire [0:0] dout, din_new;
wire N0, N1, N2, N3, N4;
rvdff_WIDTH1 dffsc (
.din (din_new[0]),
.clk (clk),
.rst_l(rst... | 6.581838 |
module rvdffs_WIDTH4 (
din,
en,
clk,
rst_l,
dout
);
input [3:0] din;
output [3:0] dout;
input en;
input clk;
input rst_l;
wire [3:0] dout;
wire N0, N1, n_0_net__3_, n_0_net__2_, n_0_net__1_, n_0_net__0_, N2;
rvdff_WIDTH4 dffs (
.din ({n_0_net__3_, n_0_net__2_, n_0_net__1_, n... | 6.583077 |
module rvbtb_addr_hash (
pc,
hash
);
input [31:1] pc;
output [5:4] hash;
wire [5:4] hash;
wire N0, N1;
assign hash[5] = N0 ^ pc[9];
assign N0 = pc[5] ^ pc[7];
assign hash[4] = N1 ^ pc[8];
assign N1 = pc[4] ^ pc[6];
endmodule
| 7.670784 |
module rvbtb_tag_hash (
pc,
hash
);
input [31:1] pc;
output [8:0] hash;
wire [8:0] hash;
assign hash[8] = pc[23] ^ pc[14];
assign hash[7] = pc[22] ^ pc[13];
assign hash[6] = pc[21] ^ pc[12];
assign hash[5] = pc[20] ^ pc[11];
assign hash[4] = pc[19] ^ pc[10];
assign hash[3] = pc[18] ^ pc[9];
... | 6.629617 |
module rvdffe_WIDTH48 (
din,
en,
clk,
rst_l,
scan_mode,
dout
);
input [47:0] din;
output [47:0] dout;
input en;
input clk;
input rst_l;
input scan_mode;
wire [47:0] dout;
wire l1clk;
rvclkhdr genblock_clkhdr (
.en(en),
.clk(clk),
.scan_mode(scan_mode),
... | 6.571079 |
module rvdff_WIDTH8 (
din,
clk,
rst_l,
dout
);
input [7:0] din;
output [7:0] dout;
input clk;
input rst_l;
wire N0;
reg [7:0] dout;
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[7] <= 1'b0;
end else if (1'b1) begin
dout[7] <= din[7];
end
end
a... | 6.58784 |
module rvdffe_WIDTH8 (
din,
en,
clk,
rst_l,
scan_mode,
dout
);
input [7:0] din;
output [7:0] dout;
input en;
input clk;
input rst_l;
input scan_mode;
wire [7:0] dout;
wire l1clk;
rvclkhdr genblock_clkhdr (
.en(en),
.clk(clk),
.scan_mode(scan_mode),
.l1... | 6.62585 |
module rveven_paritycheck (
data_in,
parity_in,
parity_err
);
input [15:0] data_in;
input parity_in;
output parity_err;
wire parity_err, N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14;
assign parity_err = N14 ^ parity_in;
assign N14 = N13 ^ data_in[0];
assign N13 = N12 ^ data... | 7.582388 |
module rveven_paritygen_WIDTH16 (
data_in,
parity_out
);
input [15:0] data_in;
output parity_out;
wire parity_out, N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13;
assign parity_out = N13 ^ data_in[0];
assign N13 = N12 ^ data_in[1];
assign N12 = N11 ^ data_in[2];
assign N11 = N10 ^ dat... | 7.582388 |
module rvdff_WIDTH18 (
din,
clk,
rst_l,
dout
);
input [17:0] din;
output [17:0] dout;
input clk;
input rst_l;
wire N0;
reg [17:0] dout;
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[17] <= 1'b0;
end else if (1'b1) begin
dout[17] <= din[17];
end
en... | 6.563022 |
module rvdff_WIDTH20 (
din,
clk,
rst_l,
dout
);
input [19:0] din;
output [19:0] dout;
input clk;
input rst_l;
wire N0;
reg [19:0] dout;
always @(posedge clk or posedge N0) begin
if (N0) begin
dout[19] <= 1'b0;
end else if (1'b1) begin
dout[19] <= din[19];
end
en... | 6.72609 |
module rvdffs_WIDTH8 (
din,
en,
clk,
rst_l,
dout
);
input [7:0] din;
output [7:0] dout;
input en;
input clk;
input rst_l;
wire [7:0] dout;
wire N0,N1,n_0_net__7_,n_0_net__6_,n_0_net__5_,n_0_net__4_,n_0_net__3_,n_0_net__2_,
n_0_net__1_,n_0_net__0_,N2;
rvdff_WIDTH8 dffs (
.di... | 6.635246 |
module cmp_and_mux_ID_BITS8_INTPRIORITY_BITS4 (
a_id,
a_priority,
b_id,
b_priority,
out_id,
out_priority
);
input [7:0] a_id;
input [3:0] a_priority;
input [7:0] b_id;
input [3:0] b_priority;
output [7:0] out_id;
output [3:0] out_priority;
wire [7:0] out_id;
wire [3:0] out_prior... | 7.470804 |
module rvdffsc_WIDTH2 (
din,
en,
clear,
clk,
rst_l,
dout
);
input [1:0] din;
output [1:0] dout;
input en;
input clear;
input clk;
input rst_l;
wire [1:0] dout, din_new;
wire N0, N1, N2, N3, N4, N5;
rvdff_WIDTH2 dffsc (
.din (din_new),
.clk (clk),
.rst_l(rs... | 6.581838 |
module rveven_paritygen_WIDTH20 (
data_in,
parity_out
);
input [19:0] data_in;
output parity_out;
wire parity_out, N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17;
assign parity_out = N17 ^ data_in[0];
assign N17 = N16 ^ data_in[1];
assign N16 = N15 ^ data_in[2];
as... | 7.582388 |
module rveven_paritycheck_WIDTH20 (
data_in,
parity_in,
parity_err
);
input [19:0] data_in;
input parity_in;
output parity_err;
wire parity_err,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18;
assign parity_err = N18 ^ parity_in;
assign N18 = N17 ^ data_in[0];
assign N17 = N... | 7.582388 |
module switch_register (
input qclk, // 20MHz
// the bus
input [12:0] RAL, // latched address
input RBS7,
input [15:0] RDL, // data lines
output [15:0] TDL,
// control lines
input [17:0] addr, // default should be 777570
output addr_match,
input assert_vector,
input write... | 7.57998 |
module Switch ( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [1:0] io_i0, // @[:@6.4]
input io_i1, // @[:@6.4]
output io_out // @[:@6.4]
);
assign io_out = io_i1; // @[Switch.scala 30:10:@40.4]
endmodule
| 6.71488 |
module switch (
input [63:0] p0,
input [63:0] p1,
input [63:0] p2,
input [63:0] p3,
input [63:0] p4,
input [63:0] p5,
input [63:0] p6,
input [63:0] p7,
input [63:0] p8,
input [63:0] p9,
input [63:0] p10,
input [63:0] p11,
input [63:0] p12,
input [63:0] p13,
in... | 6.864438 |
module SwitchAsyncFIFO (
inReset,
iWClk,
iWEn,
ivDataIn,
qWFull,
qvWCount,
iRClk,
iREn,
ovDataOut,
qREmpty,
qvRNumberLeft
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
input inReset;
input iWClk;
input iWEn;
input [... | 8.02377 |
module DualPortRAM_ASYN (
// Generic synchronous two-port RAM interface
WriteClock,
MemWEn,
MemWAddr,
MemDataIn,
ReadClock,
MemRAddr,
MemDataOut
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
// Generic synchronous two-port RAM interf... | 8.984598 |
module or connected to the CODEC Core to
// form a complete SpaceWire Routing Switch (Router).
//Origin: SpaceWire Std - Draft-1(Clause 9/10) of ECSS(European Cooperation for Space Standardization),ESTEC,ESA.
// SpaceWire Router Requirements Specification Issue 1 Rev 5. Astrium & Uni... | 8.201424 |
module SwitchData (
datainm,
datainf,
dataout,
clk,
rst_n,
over,
overout
);
input clk, rst_n, over;
input [31:0] datainm, datainf;
output overout;
output [31:0] dataout;
reg [31:0] dataout;
reg overout;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
d... | 8.580228 |
module SwitchDB (
CLK,
SW,
ACLR_L,
SWDB
);
input CLK, SW, ACLR_L;
output reg SWDB;
wire aclr_i;
reg [1:0] Q_CURR;
parameter [1:0] SW_OFF = 2'b00; //Symbolic state definitions; Simple binary counting order
parameter [1:0] SW_EDGE = 2'b01;
parameter [1:0] SW_VERF = 2'b10;
parameter [1:0... | 8.192784 |
module switchDebouncer #(
parameter integer N = 16
) (
output reg switchOut,
input switchIn,
input clk
);
wire rst, add;
reg dFF1, dFF2;
reg [N-1:0] timeReg, nextReg;
assign rst = dFF1 ^ dFF2;
assign add = ~timeReg[N-1];
always @(rst, add, timeReg) begin
case ({
rst, add
})
... | 6.935528 |
module SwitchDriver (
switclk,
switchrst,
switchread,
switchctl,
switchaddr,
switchrdata,
switch_input
);
input switclk; // ʱź
input switchrst; // λź
input switchctl; // memorioswitchƬ !!!!!!!!!!
input [1:0] switchaddr; // switchģĵ??Ͷ !!!!!!!!!!!!!!!
input switchread; //... | 7.534764 |
module SwitchEmu (
input clk,
input pulse_in,
output pulse_out
);
reg pulse_out_i = 1'b0;
reg [23:0] cnt_i = 24'h0;
assign pulse_out = pulse_out_i;
parameter Idle_st = 3'b001;
parameter Start_st = 3'b010;
parameter SwitchOn_st = 3'b100;
reg [2:0] st = Idle_st;
always @(posedge clk)
c... | 7.227526 |
module SwitchEncoder (
input [4:0] sw,
output reg [6:0] seg7
);
always @(sw)
if (sw == 5'b00001) seg7 = 7'h40;
else if (sw == 5'b00001) seg7 = 7'h79;
else if (sw == 5'b00100) seg7 = 7'h24;
else if (sw == 5'b01000) seg7 = 7'h30;
else if (sw == 5'b10000) seg7 = 7'h19;
else seg7 = 7'h7E;
... | 6.676161 |
module SwitchesToLEDs (
input i_Switch_1,
input i_Switch_2,
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4
);
assign o_LED_1 = i_Switch_1 & i_Switch_2; // AND gate
assign o_LED_2 = i_Switch_1 | i_Switch_2; // OR gate
assign o_LED_3 = ~(i_Switch_1 & i_Switch_2); // ... | 7.42013 |
module SwitchesToLEDs_tb;
reg i_Switch_1;
reg i_Switch_2;
wire o_LED_1;
wire o_LED_2;
wire o_LED_3;
wire o_LED_4;
// Instantiating module to test
SwitchesToLEDs uut (
.i_Switch_1(i_Switch_1),
.i_Switch_2(i_Switch_2),
.o_LED_1(o_LED_1),
.o_LED_2(o_LED_2),
.o_LED_3(o_LED_3... | 7.42013 |
module switches_bus (
input sw0,
input sw1,
input sw2,
input sw3,
input sw4,
input sw5,
input sw6,
input sw7,
output [7:0] bus
);
assign bus[0] = sw0;
assign bus[1] = sw1;
assign bus[2] = sw2;
assign bus[3] = sw3;
assign bus[4] = sw4;
assign bus[5] = sw5;
assign bus[6... | 6.842316 |
module SwitchFreq (
select,
CLK,
clk
);
input select;
input CLK;
output reg clk;
wire clk1, clk2;
//assign clk = CLK;
divider_ #(2) divider1 (
.clk(CLK),
.parameterN(1),
.clk_N(clk1)
);
divider_ #(1000000) divider2 (
.clk(CLK),
.parameterN(1),
.clk_N(clk2... | 7.314714 |
module divider_ #(
parameter N = 100_000
) (
clk,
parameterN,
clk_N
);
input clk; // ϵͳʱ
input [3:0] parameterN; //Ƶ
output reg clk_N; // Ƶʱ
reg [31:0] counter; /* ͨʵַƵ
0(N/2-1)ʱ
ʱӷת */
initial begin
counter = 0;
... | 7.117642 |
module M_Median_Filter (
Clk,
Rst,
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
New_X0_P,
New_X1_P,
New_X2_P,
New_X3_P,
New_X4_P,
New_X5_P,
New_X6_P,
New_X7_P,
New_X8_P,
New_X0_S,
New_X1_S,
New_X2_S,
New_X3_S,
New_X4_S,
New_X... | 6.835633 |
module M_Switching_Stage (
Clk,
Reset,
CV,
MV,
XX
);
input Clk, Reset;
input [7:0] CV, MV;
output [7:0] XX;
wire [7:0] AD;
wire F;
M_Thershold_Value SD0 (
Clk,
Reset,
CV,
MV,
AD
);
M_Thershold_Detector SD1 (
Clk,
AD,
F
);
Mux_2X... | 7.081628 |
module switching_generator //the switching generator
#(
parameter N,
M
) (
clk,
seed,
set,
out
);
input clk;
input set;
input [0:N + 3 * M - 1] seed;
output out;
reg [0:M * M - 1] M1;
reg [0:M * M - 1] M2;
wire [0:M * M - 1] data_trans_seed1;
wire [0:M * M - 1] data_trans_se... | 7.403493 |
module switching_latch (
input clk, // the system clock
input int_clk, // the interupt clock domain
input reset_n,
input trigger,
input ack,
output reg out
);
reg ack_clk_1; // Doing a 3 stage sync between the clock domains - Fuck I hate these.......
// But t... | 8.237858 |
module SwitchInterface (
clk,
reset,
FirstScreen,
GameScreen,
Player1Wins,
Player2Wins,
sw,
color,
port_id,
write_strobe,
out_port,
in_port,
interrupt,
interrupt_ack,
player_screen,
led,
reset_plyrScrn,
mode
);
//inputs
input clk, reset;
i... | 7.571517 |
module SwitchPeripheral (
input CLK,
input RESET,
inout [7:0] BUS_DATA,
input [7:0] BUS_ADDR,
input BUS_WE,
input SWITCH_IN
);
parameter [7:0] SwitchBaseAddress = 8'hA8;
//Tristate
reg [7:0] Out;
reg SwitchBusWE;
//Only place data on the bus if the processor is NOT writing, and it i... | 8.73452 |
module SwitchReverseSignal (
SwiReverse,
KeySwi,
clk,
EditMode,
reset
);
output reg SwiReverse;
input KeySwi, clk, EditMode, reset;
reg [31:0] count;
reg [ 2:0] count2;
always @(posedge clk, negedge KeySwi, negedge reset) begin
if (~reset) begin
count <= 0;
count2 <= 0;
... | 6.989813 |
module SwitchSyncFIFO (
nReset,
iClk,
iWEn,
ivDataIn,
iREn,
ovDataOut,
qEmpty,
qFull,
qvCount
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
input nReset;
input iClk;
input iWEn;
input [pWordWidth-1:0] ivDataIn;
input iREn... | 8.40197 |
module DualPortRAM (
clock,
MemWEn,
qvWAddr,
vDataIn,
qvRAddr,
vDataOut
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
// Generic synchronous two-port RAM interface
input clock; // clock
input MemWEn; // write enable input
input [pDep... | 8.237962 |
module switch_2_tb();
localparam period = 2;
localparam max_test = 2000;
integer test_idx;
reg clk_r;
reg rst_r;
wire
fabric #(
.DATA_SIZE(4),
.ADDR_SIZE(1),
.ADDR(0),
.NODES_NUM(2),
.PACKS_TO_GEN(10),
.MAX_PACK_LEN(10)
) IP0 (
.clk (clk_r),
.a_rst (rst_r),
... | 6.820912 |
module switch_4x4_tb ();
reg clk, rst;
always #25 clk = ~clk;
reg [31:0] input_word_1, input_word_2, input_word_3, input_word_4;
// wire [32:0] to_output_buf_1, to_output_buf_2, to_output_buf_3, to_output_buf_4;
switch_4x4 switch_4x4_instance (
.clk(clk),
.rst(rst),
.input_1(input_word_1)... | 6.74646 |
module SWITCH_BCD (
CLK,
RESET,
DIP,
SEGMENT,
ENABLE
);
input CLK;
input RESET;
input [7:0] DIP;
output [7:0] SEGMENT;
output [5:0] ENABLE;
reg [23:0] DIVID;
reg [ 7:0] BCD;
reg [ 5:0] ENABLE;
reg [ 7:0] SEGMENT;
reg [ 3:0] DECODE;
wire [ 7:0] DIP1;
always @(posedge C... | 7.05735 |
module Switch_Board (
input i_Clk,
input i_Switch_1,
input i_Switch_2,
input i_Switch_3,
input i_Switch_4,
output [3:0] o_Buttons
);
reg [3:0] r_Buttons = 4'b0000;
reg r_Any_Switch = 1'b0;
wire w_Any_Switch;
wire w_Any_Switch_Filtered;
r_Any_Switch = i_Switch_1 || i_Switch_2 || i_Switch_3 || ... | 7.345207 |
module switch_box_connector #(
parameter W0 = 5,
parameter W1 = 7
) (
input [W0-1:0] data0_in,
output [W0-1:0] data0_out,
input [W1-1:0] data1_in,
output [W1-1:0] data1_out
);
genvar i, j;
generate
for (i = 0; i < W0; i = i + 1) begin
assign data0_out[i] = data1_in[i%W1];
en... | 6.803101 |
module switch_box_connector_tb;
localparam W0 = 3;
localparam W1 = 10;
reg clk = 0;
always #10 clk = ~clk;
reg [W0-1:0] d0_in;
wire [W0-1:0] d0_out;
reg [W1-1:0] d1_in;
wire [W1-1:0] d1_out;
switch_box_connector #(
.W0(W0),
.W1(W1)
) dut (
.data0_in (d0_in),
.data1_in (d... | 6.803101 |
module Switch_Counter (
input i_Clk,
input i_Reset,
input i_Switch,
output [3:0] o_Nibble
);
reg r_Switch = 1'b0;
reg [3:0] r_Nibble = 4'h0;
always @(posedge i_Clk) begin
r_Switch <= i_Switch;
if (i_Reset) begin
r_Nibble <= 0;
end else if ((i_Switch == 1'b1) && (r_Switch == 1'b... | 6.569469 |
module SWITCH_DEBOUNCER #(
parameter BITS_NUM = 4,
parameter REPEAT_PRESC_CNT_MODULO = 100,
parameter REPEAT_START_DELAY = REPEAT_PRESC_CNT_MODULO - 1
) (
input CLK,
input CLR,
input CE,
input REP_CE,
input S_IN,
output KEY_EN,
output KEY_UP
);
reg [BITS_NUM-1:0] P_OUT;
... | 7.65145 |
module switch_decoder (
input [1:0] in,
output reg [3:0] out
);
always @* begin
case (in)
0: out = 4'b0001;
1: out = 4'b0010;
2: out = 4'b0100;
3: out = 4'b1000;
endcase
end
endmodule
| 7.014339 |
module switch_detect (
input CLK,
input RST,
input switch_in,
output detected
);
//Definition for Variables in the module
wire timer_on;
wire timer_start;
//Load other module(s)
edge_detect E1 (
.CLK(CLK),
.RST(RST),
.input_signal(switch_in),
.enable(~timer_on),
... | 7.889888 |
module, 2 ns period
switch_on: swith pushed on
------------------------------------------------------
History:
01-21-2016: First Version by Garfield
***********************************************/
`timescale 1 ns/100 ps
//Simulation time assignment
//Insert the modules
module switch_detect_press_t... | 6.753859 |
module, 2 ns period
switch_on: swith pushed on
------------------------------------------------------
History:
01-21-2016: First Version by Garfield
***********************************************/
`timescale 1 ns/100 ps
//Simulation time assignment
//Insert the modules
module switch_detect_test;
/... | 6.753859 |
module switch_display (
input wire [3:0] KEY,
output wire [3:0] DIG,
output [7:0] SEG
);
// Atribuicao para os digitos do display de 7 segmentos
assign DIG = 4'b1110;
// Variavel com os dados a serem inseridos no display de 7 segmentos
reg [7:0] data_r;
always @(KEY) begin
case (KEY)
4... | 9.366303 |
module switch_driver (
input wire clk,
input wire [23:0] switch,
output reg [31:0] switch_data
);
always @(posedge clk) begin
switch_data <= switch;
end
endmodule
| 7.702861 |
module SWITCH_INPUT (
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire [1:0] HTRANS,
input wire HREADY,
input wire HSEL,
output wire HREADYOUT,
output reg [31:0] HRDATA,
output wire SWITCH_IRQ,
input w... | 6.710742 |
module switch_key_ctrl (
input clk,
input reset,
input [3:0] keys,
input [3:0] switches,
output flipped,
output [7:0] readdata
);
wire [7:0] switch_key = {switches, keys};
reg [7:0] switch_key_reg;
reg [7:0] switch_key_flipped;
assign readdata = switch_key_reg;
assign flipped =... | 7.625779 |
module switch_map (
output [31:0] data,
input [31:0] addr,
input [11:0] sw
);
assign en = addr[31:4] == 28'h0000ffe;
assign data = (en) ? {28'b0, data_out} : 32'bz;
reg [3:0] data_out;
always @(addr) begin
case (addr[3:0])
4'h0: data_out = sw[3:0];
4'h4: data_out = sw[7:4];
... | 7.504168 |
module Switch_Matrix (
in,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7
, sel8,
sel9,
sel10,
sel11,
sel12,
sel13,
sel14,
sel15,
out
);
input [15:0] in;
input [3:0] sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7;
input [3:0] sel8, sel9, sel... | 6.632007 |
module switch_mode (
input wire clk,
input wire clkps2,
input wire dataps2,
output reg mode,
output reg vga,
output reg sdtest,
output reg flashtest,
output reg memtestf,
output reg memtests,
output reg mousetest,
output reg sdramtest,
output reg serialtest,
... | 7.025622 |
module switch_mux (
input in0,
input in1,
input in2,
input in3,
input [1:0] sel,
output reg out
);
always @(in0 or in1 or in2 or in3 or sel)
case (sel)
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
2'b11: out = in3;
default: out = 2'b00;
e... | 8.756739 |
module c_gate_0_0 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_0 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
... | 7.08672 |
module latch_controller_1_0 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n1;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_0 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 ... | 7.224712 |
module c_gate_0_5 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_5 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI21X3 U3 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U4 (
.A(preset),
.Z(n1)
... | 7.033274 |
module latch_controller_1_5 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_5 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 ... | 7.224712 |
module c_gate_0_4 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_4 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)... | 7.046409 |
module latch_controller_1_4 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_4 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 ... | 7.224712 |
module c_gate_0_3 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_3 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)... | 7.34217 |
module latch_controller_1_3 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_3 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 ... | 7.224712 |
module sr_latch_0_2 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
... | 6.553251 |
module c_gate_0_2 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_2 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)... | 7.222928 |
module latch_controller_1_2 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_2 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 ... | 7.224712 |
module c_gate_0_1 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_1 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_OAI12X18 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)... | 6.95665 |
module latch_controller_1_1 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, N0, n2;
assign Rout = Aout;
assign lt_en = N0;
c_gate_0_1 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 ... | 7.224712 |
module c_gate_1_0 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_0 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
... | 7.390817 |
module latch_controller_0_0 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n2;
assign Rout = Aout;
c_gate_1_0 gate (
.preset(preset),
.a(n2),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
... | 7.224712 |
module c_gate_1_1 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_1 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
... | 7.498178 |
module latch_controller_0_1 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_1 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
... | 7.224712 |
module sr_latch_1_2 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
... | 6.665385 |
module c_gate_1_2 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_2 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
... | 7.741961 |
module latch_controller_0_2 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_2 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
... | 7.224712 |
module sr_latch_1_3 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
... | 6.608477 |
module c_gate_1_3 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_3 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
... | 7.685153 |
module latch_controller_0_3 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_3 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
... | 7.224712 |
module sr_latch_1_4 (
s,
r,
q,
qn
);
input s, r;
output q, qn;
wire N1, n1;
HS65_LS_AND2X27 C8 (
.A(n1),
.B(N1),
.Z(q)
);
HS65_LS_IVX9 U1 (
.A(r),
.Z(n1)
);
HS65_LS_IVX9 U2 (
.A(qn),
.Z(N1)
);
HS65_LS_NOR2X6 U3 (
.A(s),
.B(q),
... | 6.598887 |
module c_gate_1_4 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset;
sr_latch_1_4 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_NOR3X4 U3 (
.A(a),
.B(preset),
.C(b),
.Z(reset)
);
HS65_LS_AO12X9 U4 (
.A(a),
.B(b),
... | 7.541928 |
module latch_controller_0_4 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset, Rin, Ain;
output Aout, Rout, lt_en;
wire Aout, n1;
assign Rout = Aout;
c_gate_1_4 gate (
.preset(preset),
.a(n1),
.b(Rin),
.c(Aout)
);
HS65_LS_IVX9 U1 (
.A(Aout),
... | 7.224712 |
module c_gate_0_6 (
preset,
a,
b,
c
);
input preset, a, b;
output c;
wire set, reset, n1;
sr_latch_0_8 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.A(preset),
.Z(n1)
);
HS65_LS_OAI21X3 U4 (
.A(b),
.B(a),
.C(n1),
.Z(reset)
... | 7.291887 |
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