code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module c_gate_0_8 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_8 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
... | 6.999778 |
module latch_controller_1_8 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_8 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
... | 7.224712 |
module select_element_4 (
preset,
\input ,
true,
false,
sel
);
input preset;
input \input ;
output true;
output false;
input sel;
// Internal wires
wire n1;
wire n2;
wire n3;
HS65_LS_LDHRQX9 true_latch_out_reg (
.RN(n3),
.Q (true),
.G (sel),
.D (n1)
);... | 6.561954 |
module c_gate_0_14 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_18 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
... | 7.06524 |
module c_gate_0_9 (
preset,
a,
b,
c
);
input preset;
input a;
input b;
output c;
// Internal wires
wire set;
wire reset;
wire n1;
sr_latch_0_9 latch (
.s(set),
.r(reset),
.q(c)
);
HS65_LS_IVX9 U3 (
.Z(n1),
.A(preset)
);
HS65_LS_OAI21X3 U4 (
... | 7.105424 |
module latch_controller_1_9 (
preset,
Rin,
Aout,
Rout,
Ain,
lt_en
);
input preset;
input Rin;
output Aout;
output Rout;
input Ain;
output lt_en;
// Internal wires
wire not_Ain;
assign Rout = Aout;
c_gate_0_9 gate (
.preset(preset),
.a(not_Ain),
.b(Rin),
... | 7.224712 |
module switch_output (
/* inputs */
d_in_NW,
d_in_N,
d_in_E,
d_in_W,
d_in_S,
conf,
/* outputs */
d_out,
select_NW, // Is NW input data being used?
select_N,
select_E,
select_W,
select_S
);
input [`PATH_WIDTH:0] d_in_NW;
input [`PATH_WIDTH:0] d_in_N;
input... | 9.107562 |
module switch_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [17:0] readdata;
input [1:0] address;
input clk;
input [17:0] in_port;
input reset_n;
wire clk_en;
wire [17:0] data_in;
wire [17:0] read_mux_out;
reg [17:0] readdata;
... | 6.552887 |
module switch_post_top (
input clk,
input rstn,
input o_cell_fifo_wr,
input [ 3:0] o_cell_fifo_sel,
input [127:0] o_cell_fifo_din,
input o_cell_first,
input o_cell_last,
output [ 3:0] o_cell_bp,
input data_fifo_rd0,
output [ 7:0] data_fifo... | 6.77809 |
module switch_pre (
input clk,
input rstn,
input sof,
input dv,
input [ 7:0] din,
output reg [127:0] i_cell_data_fifo_dout,
output reg i_cell_data_fifo_wr,
output reg [ 15:0] i_cell_ptr_fifo_dout,
output reg i_... | 7.423376 |
module: switch_pre
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module switch_pre_tb;
// Inputs
reg clk;
reg rstn;
reg data_sof;
reg data_dv;
reg [7:0] data_in;
reg i_cell_ack;
... | 6.857429 |
module switch_qc (
input clk,
input rstn,
input [15:0] q_din,
input q_wr,
output q_full,
output ptr_rdy,
input ptr_ack,
output [15:0] ptr_dout
);
reg [15:0] ptr_din;
reg ptr_wr;
reg q_rd;
wire [15:0] q_dout;
wire q_empty;
sfifo_w1... | 6.933098 |
module switch_seg (
input switch0,
input switch1,
input switch2,
input switch3,
output [6:0] seg,
output [3:0] an
);
reg [6:0] seg_temp;
reg an_temp = 4'b1110;
always @(*) begin
if (switch0 == 1) seg_temp = 7'b1000000;
//0
else if (switch1 == 1) seg_temp = 7'b1111001;
//1... | 7.298789 |
module switch_sync (
output reg out,
input clk,
input data
);
always @(posedge clk) begin
out <= data;
end
endmodule
| 6.981364 |
module switch_synchronizers (
input wire i_clk,
input wire [3:0] i_switches,
output wire [3:0] o_switches
);
wire w_switch_1;
synchronizer switch_1_sync (
.i_clk(i_clk),
.i_input(i_switches[0]),
.o_input_sync(w_switch_1)
);
wire w_switch_2;
synchronizer switch_2_sync (
... | 7.393011 |
module: SWITCH
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module SWITCH_tb;
// Inputs
reg x1;
reg x2;
reg x3;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
SWI... | 6.512897 |
module switch_testBench ();
reg clock;
reg [3:0] SW;
wire [3:0] switchesUp;
wire PWM_pulse;
switch UUT (
.clock(clock),
.SW(SW),
.switchesUp(switchesUp)
);
PWM pwmInst (
.clock(clock),
.enable(1),
.speed(SW),
.PWM_pulse(PWM_pulse)
);
initial begin
cloc... | 6.813116 |
module switch_top (
input clk,
input rstn,
input sof,
input dv,
input [7:0] din,
input ptr_fifo_rd0,
input ptr_fifo_rd1,
input ptr_fifo_rd2,
input ptr_fifo_rd3,
input data_fifo_rd0,
input data_fifo_rd1,
input ... | 6.654788 |
module assumes
that the lowest note is the LSB.
----------------------------------------------------------------------------- */
module switch_to_note(
input clk,
input reset,
input scale_button,
input [5:0] root,
input [7:0] switches,
output reg [47:0] notes
);
wire [1:0] scale_counter;
dffre #(.WIDTH(2)... | 7.427124 |
module switch_to_note_tb ();
reg [ 5:0] root = 6'b0;
reg [ 7:0] switches = 8'b00000000;
wire [47:0] notes;
switch_to_note SWITCH_TO_NOTE (
.root(root),
.switches(switches),
.notes(notes)
);
//TODO: Just print parsed versions of the notes output to make the tests more legible.
initial... | 7.436012 |
module swo (
clk,
out1,
out2
);
input clk;
output out1;
output out2;
reg [31:0] counter;
reg status;
initial begin
counter <= 32'b0;
status <= 1'b0;
end
always @(posedge clk) begin
counter <= counter + 1'b1;
if (counter > 300000) begin
status <= !status;
cou... | 6.501376 |
module SWOCapture #(
parameter DONE_CHAR = 8'h04, // Simulation termination character
parameter BUF_SIZE = 80
) (
input wire CLK,
input wire RESETn,
input wire SWO
);
localparam CHAR_CR = 8'h0D;
localparam CHAR_LF = 8'h0A;
//
// Internal Signals
//
wire [ 7:0] w_rx_char;
reg ... | 6.607799 |
module dff_s (
din,
clk,
q,
se,
si,
so
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enable
input [SIZE-1:0] si; // scan-input
output [SIZE-1:0] so; // scan-out... | 7.138281 |
module dff_ns (
din,
clk,
q
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk
output [SIZE-1:0] q; // output
reg [SIZE-1:0] q;
always @(posedge clk) q[SIZE-1:0] <= din[SIZE-1:0];
endmodule
| 6.540346 |
module dffe_s (
din,
en,
clk,
q,
se,
si,
so
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enable
input [SIZE-1:0] si; // scan... | 6.980273 |
module dffre_s (
din,
rst,
en,
clk,
q,
se,
si,
so
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input rst; // reset
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enabl... | 7.001438 |
module dffrle_s (
din,
rst_l,
en,
clk,
q,
se,
si,
so
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input rst_l; // reset
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-... | 6.660956 |
module mux3ds (dout, in0, in1, in2, sel0, sel1, sel2) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input sel0;
input sel1;
input sel2;
// reg declaration does not imply state being maintained
// across cycles. Used to con... | 6.938207 |
module sink (
in
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] in;
// Alexey
// `ifdef PITON_PROTO
// As of version 8.2 XST does not remove this module without the
// following additional dead code
wire a;
assign a = |in;
// `endif
endmodule
| 6.752622 |
module dffsl_async_ns (
din,
clk,
set_l,
q
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk or scan clk
input set_l; // set
output [SIZE-1:0] q; // output
reg [SIZE-1:0] q;
// synopsys async_set_reset "set_l"
always @(posedge clk or... | 6.557894 |
module dff_s (
din,
clk,
q,
se,
si,
so,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-enable
input [SIZE-1:0] si; // scan-input
... | 7.138281 |
module dff_ns (
din,
clk,
q,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk
output [SIZE-1:0] q; // output
input err_en; // error enable
reg [SIZE-1:0] q;
always @(posedge clk)
if (NO_ERR) begin... | 6.540346 |
module dffe_s (
din,
en,
clk,
q,
se,
si,
so,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input clk; // clk or scan clk
output [SIZE-1:0] q; // output
input se; // scan-en... | 6.980273 |
module dffre_s (
din,
rst,
en,
clk,
q,
se,
si,
so,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input rst; // reset
input clk; // clk or scan clk
output [SIZE-1:0] q; /... | 7.001438 |
module dffrle_s (
din,
rst_l,
en,
clk,
q,
se,
si,
so,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input rst_l; // reset
input clk; // clk or scan clk
output [SIZE-1:0] ... | 6.660956 |
module mux3ds (dout, in0, in1, in2, sel0, sel1, sel2) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input sel0;
input sel1;
input sel2;
// reg declaration does not imply state being maintained
// across cycles. Used to con... | 6.938207 |
module sink (
in
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] in;
`ifdef FPGA_SYN
// As of version 8.2 XST does not remove this module without the
// following additional dead code
wire a;
assign a = |in;
`endif
endmodule
| 6.752622 |
module dffsl_async_ns (
din,
clk,
set_l,
q,
err_en
);
// synopsys template
parameter NO_ERR = 1;
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input clk; // clk or scan clk
input set_l; // set
output [SIZE-1:0] q; // output
input err_en; // error enable
reg [SIZE-1... | 6.557894 |
module dp_mux5ds (dout, in0, in1, in2, in3, in4,
sel0_l, sel1_l, sel2_l, sel3_l, sel4_l) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input [SIZE-1:0] in4;
input sel0_l;
input sel1_l;
input se... | 6.521486 |
module dp_mux8ds (dout, in0, in1, in2, in3,
in4, in5, in6, in7,
sel0_l, sel1_l, sel2_l, sel3_l,
sel4_l, sel5_l, sel6_l, sel7_l) ;
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input [SIZE-1:0... | 6.611255 |
module dp_mux3ds (dout, in0, in1, in2,
sel0_l, sel1_l, sel2_l);
// synopsys template
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input sel0_l;
input sel1_l;
input sel2_l;
// reg declaration does not imply state being maintained
// acro... | 6.6565 |
module swselect (
input wire adesE, //ѾijM
input [31:0] addressE,
input [7:0] alucontrolE,
input [3:0] memwriteE,
output reg [3:0] memwrite2E
);
always @(*) begin
if (adesE) memwrite2E <= 4'b0000;
else begin
case (alucontrolE)
`EXE_SB_OP: begin
case (addressE[1:0])... | 6.810139 |
module SW_Set (
CLK,
PREV,
NEXT,
SW
);
input CLK;
input [2:0] PREV;
input [2:0] NEXT;
output reg [2:0] SW = 0;
integer sw_delay = 0;
always @(negedge CLK) begin
if (sw_delay == 0) begin
if (PREV) begin
sw_delay <= 500000;
SW <= SW - PREV;
end else if (NEXT) b... | 6.674243 |
module SW_23bit (
in_0,
in_1,
se,
out
);
parameter DATA_WIDTH = 23;
input [DATA_WIDTH - 1:0] in_0;
input [DATA_WIDTH - 1:0] in_1;
input se;
output [DATA_WIDTH - 1:0] out;
wire [DATA_WIDTH - 1:0] in_0;
wire [DATA_WIDTH - 1:0] in_1;
wire se;
reg [DATA_WIDTH - 1:0] out;
initial begi... | 6.625967 |
module SW_24 (
in_0,
in_1,
sel,
out
);
parameter DATA_WIDTH = 24;
input [DATA_WIDTH - 1:0] in_0;
input [DATA_WIDTH - 1:0] in_1;
input sel;
output [DATA_WIDTH - 1:0] out;
wire [DATA_WIDTH - 1:0] in_0;
wire [DATA_WIDTH - 1:0] in_1;
reg [DATA_WIDTH - 1:0] out;
always @*
case (se... | 7.830606 |
module SW_8bit (
in_0,
in_1,
se,
out
);
parameter DATA_WIDTH = 8;
input [DATA_WIDTH - 1:0] in_0;
input [DATA_WIDTH - 1:0] in_1;
input se;
output [DATA_WIDTH - 1:0] out;
wire [DATA_WIDTH - 1:0] in_0;
wire [DATA_WIDTH - 1:0] in_1;
wire se;
reg [DATA_WIDTH - 1:0] out;
initial begin
... | 6.801097 |
module sw_alloc_first_arbiter #(
parameter VC_NUM_PER_PORT = 4,
parameter PORT_NUM = 5,
parameter PORT_SEL_WIDTH = PORT_NUM - 1, //assumed that no port request for itself!
parameter PORT_SEL_BCD_WIDTH = log2(PORT_SEL_WIDTH),
parameter TOTAL_VC_NUM = VC_NUM_PER_PORT * PORT_NUM,
parameter PORT_SE... | 8.693202 |
module sw_alloc_second_arbiter #(
parameter VC_NUM_PER_PORT = 4,
parameter PORT_NUM = 5,
parameter ARBITER_WIDTH = PORT_NUM - 1, //assumed that no port request for itself!
parameter PORT_REQ_WIDTH = PORT_NUM * ARBITER_WIDTH
) (
input [PORT_REQ_WIDTH-1 : 0] port_requests,
... | 7.437006 |
module SW_Clk_Divide (
clk,
clk_div
);
input clk;
output reg clk_div;
integer count = 0;
always @(posedge clk) begin
if (count == 499999) //to generate 100Hz Signal ie T = 0.01s
count <= 1'b0;
else count <= count + 1'b1;
end
always @(posedge clk) begin
if (count == 499999) clk_d... | 6.920851 |
module sw_debounce (
clk,
rst_n,
sw1_n,
sw2_n,
sw3_n,
led_d1,
led_d2,
led_d3
);
input clk; //ʱźţ50MHz
input rst_n; //λźţЧ
input sw1_n, sw2_n, sw3_n; //ͱʾ
output led_d1, led_d2, led_d3; //ܣֱɰ
//---------------------------------------------------------------------------
r... | 6.798414 |
module sw_gen_affine (
clk,
rst,
i_query_length,
i_local,
query,
i_vld,
i_data,
o_vld,
m_result
);
localparam SCORE_WIDTH = 11, N_A = 2'b00, //nucleotide "A"
N_G = 2'b01, //nucleotide "G"
N_T = 2'b10, //nucleotide "T"
N_C = 2'b11, //nucleotide "C"
INS = 1, //insertion... | 7.000366 |
module sw_gen_min (
input wire clk_min,
input wire reset,
output reg [3:0] min_low,
min_high
);
initial begin
min_low = 0;
min_high = 0;
end
always @(posedge clk_min or posedge reset) begin
if (reset) begin
min_low = 0;
min_high = 0;
end else if (min_low == 9) begin... | 7.000059 |
module sw_gen_psec (
input wire clk_psec,
input wire reset,
output reg clk_sec,
output reg [3:0] psec_low,
psec_high
);
initial begin
psec_low = 0;
psec_high = 0;
end
always @(posedge clk_psec or posedge reset) begin
if (reset) begin
psec_low = 0;
psec_high = 0;
... | 7.01611 |
module sw_gen_sec (
input wire clk_sec,
input wire reset,
output reg clk_min,
output reg [3:0] sec_low,
sec_high
);
initial begin
sec_low = 0;
sec_high = 0;
end
always @(posedge clk_sec or posedge reset) begin
if (reset) begin
sec_low = 0;
sec_high = 0;
end else... | 7.502251 |
module sw_iterB_i (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:... | 6.824429 |
module to deal with LEDs and switches
* Copyright (C) 2010 Zeus Gomez Marmolejo <zeus@aluzina.org>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* F... | 8.872476 |
module sw_maxscore_readRefPacked_0_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 5;
parameter MEM_SIZE = 24;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input ... | 6.721326 |
module sw_maxscore_readRefPacked_0 (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd24;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
... | 6.721326 |
module sw_mem_sel (
input [31:0] switch_cs,
input [15:0] sw,
input [31:0] data,
output [31:0] data_sel
);
assign data_sel = (switch_cs) ? {16'b0, sw[15:0]} : data;
endmodule
| 7.04254 |
module sw_mux (
adress,
in,
out0,
out1,
out2,
out3,
out4
);
input [3:0] adress;
input [3:0] in;
output [3:0] out0, out1, out2, out3, out4;
wire [3:0] in;
reg [3:0] out0, out1, out2, out3, out4;
always @(adress or in) begin
case (adress)
4'b0001: out1 <= in;
4'... | 8.001779 |
module.
Info: monemi@fkegraduate.utm.my
************************************************************************/
module sw_out#(
parameter VC_NUM_PER_PORT = 4,
parameter PORT_NUM = 5,
parameter PYLD_WIDTH = 32,
parameter FLIT_TYPE_WIDTH = 2,
parameter SW_OUTPUT_REGISTERED = 0, // 1: registered , 0... | 8.401637 |
module sw_p (
input clk,
input rst,
input [3:0] addra,
output reg [31:0] douta,
input [7:0] sw
);
reg [31:0] sw_p_r[0:15];
always @(posedge clk) begin
douta <= sw_p_r[addra];
if (rst) begin
sw_p_r[0] <= 0;
sw_p_r[1] <= 0;
sw_p_r[2] <= 0;
sw_p_r[3] <= 0;
... | 7.152432 |
module sw_pe_array_proc_element_query_mem_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd4;
parameter AddressRange = 32'd2048;
parameter AddressWidth = 32'd11;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input... | 7.184438 |
module sw_pe_array_receive_match_matchBuf (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd5;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [Dat... | 6.692945 |
module SW_PE_clk (
input clk,
input reset,
input [2:0] seq1,
input [2:0] seq2,
input [31:0] diag_score,
input [31:0] left_score,
input [31:0] top_score,
output reg [31:0] score
);
parameter match_score = 2;
parameter mismatch_score = 1;
parameter gap_penalty = 1;
wire [31:0] sc... | 7.174761 |
module sw_pulse (
clk,
rst_n,
sw_en,
sw_out
);
input clk;
input rst_n;
input sw_en;
output sw_out;
reg sw_signal;
reg [19:0] count;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
count <= 20'b0;
sw_signal <= 1'b1;
end else if (!sw_en) begin
coun... | 6.959327 |
module SW_Refresh_Clk (
input Clk,
output reg Clk_Div
);
integer count = 0;
always @(posedge Clk) begin
if (count == 4999) //to generate 10KHz for refresh counter
count <= 1'b0;
else count <= count + 1'b1;
end
always @(posedge Clk) begin
if (count == 4999) Clk_Div <= ~Clk_Div;
e... | 6.76437 |
modules //
// //
//============================================================================//
// _________ //
// ... | 8.225128 |
module, and provides and interface //
// to test the module from Python (MyHDL) //
// Date: Dec 2011 //
// Developer: Wesley New //
// Licence: GNU General Public ... | 9.300519 |
module, and provides and interface //
// to test the module from Python (MyHDL) //
// Date: Dec 2011 //
// Developer: Wesley New //
// Licence: GNU General Public ... | 9.300519 |
module sw_reset #(
parameter WIDTH = 32,
parameter LOG2_RESET_CYCLES = 8
) (
input clk,
input resetn,
// Slave port
input slave_address, // Word address
input [WIDTH-1:0] slave_writedata,
input slave_read,
input slave_write,
input [WIDTH/8-1:0] slave_byteenable,
output slav... | 8.079645 |
module sw_sep_alloc #(
parameter VC_NUM_PER_PORT = 4,
parameter PORT_NUM = 5,
parameter PORT_SEL_WIDTH = PORT_NUM - 1, //assumed that no port request for itself!
parameter PORT_SEL_BCD_WIDTH = log2(PORT_SEL_WIDTH),
parameter TOTAL_VC_NUM = VC_NUM_PER_PORT * PORT_NUM,
parameter PORT_SEL_ARRAY_WI... | 7.357073 |
module sw_top_tb;
parameter PERIOD = 10;
parameter CTSW_DWIDTH = 24;
wire clk_100m;
wire clk_25m;
wire locked;
clk_gen #(
.PERIOD (PERIOD),
.REST_VALUE(1'b0)
) clk_gen_100m (
.clk (clk_100m),
.rstn(locked)
);
reg [CTSW_DWIDTH-1:0] timer_data_l_i;
reg [CTSW_DWIDTH-1:0] t... | 6.894027 |
module SW_to_LEDR (
input [9:0] SW,
output [9:0] LEDR
);
assign LEDR = SW;
endmodule
| 6.830166 |
module sw_wrbck #(
parameter BARHIT = 2,
parameter BARMP = 6'bxxxxxx
) (
input clk,
input rst,
// TRN rx
input [63:0] trn_rd,
input [ 7:0] trn_rrem_n,
input trn_rsof_n,
input trn_reof_n,
input trn_rsrc_rdy_n,
input [ 6:0] trn_rbar_hit_n,
output re... | 8.216159 |
module sxrRISC621_addsub (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [13:0] dataa;
input [13:0] datab;
output cout;
output overflow;
output [13:0] result;
wire sub_wire0;
wire sub_wire1;
wire [13:0] sub_wire2;
wire cout = sub_wire0;
wire overfl... | 7.169797 |
module sxrRISC621_addsub (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [13:0] dataa;
input [13:0] datab;
output cout;
output overflow;
output [13:0] result;
endmodule
| 7.169797 |
module sxrRISC621_cache (
address,
clock,
data,
wren,
q);
input [7:0] address;
input clock;
input [13:0] data;
input wren;
output [13:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [13:0] sub_wire0;
... | 8.187166 |
module sxrRISC621_cache (
address,
clock,
data,
wren,
q
);
input [7:0] address;
input clock;
input [13:0] data;
input wren;
output [13:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodul... | 8.187166 |
module sxrRISC621_cam (
we_n,
rd_n,
din,
argin,
addrs,
dout,
mbits
);
//----------------------------------------------------------------------------
//-- Declare input and output port types
//----------------------------------------------------------------------------
input we_n, r... | 8.187166 |
module sxrRISC621_div (
denom,
numer,
quotient,
remain
);
input [13:0] denom;
input [13:0] numer;
output [13:0] quotient;
output [13:0] remain;
wire [13:0] sub_wire0;
wire [13:0] sub_wire1;
wire [13:0] quotient = sub_wire0[13:0];
wire [13:0] remain = sub_wire1[13:0];
lpm_divide LPM_... | 6.784939 |
module sxrRISC621_div (
denom,
numer,
quotient,
remain
);
input [13:0] denom;
input [13:0] numer;
output [13:0] quotient;
output [13:0] remain;
endmodule
| 6.784939 |
module sxrRISC621_vaddsub (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [6:0] dataa;
input [6:0] datab;
output cout;
output overflow;
output [6:0] result;
wire sub_wire0;
wire sub_wire1;
wire [6:0] sub_wire2;
wire cout = sub_wire0;
wire overflow ... | 7.25902 |
module sxrRISC621_vaddsub (
add_sub,
dataa,
datab,
cout,
overflow,
result
);
input add_sub;
input [6:0] dataa;
input [6:0] datab;
output cout;
output overflow;
output [6:0] result;
endmodule
| 7.25902 |
module SyncFIFO #(
parameter DataWidth = 64,
parameter Deepth = 16
) (
input Clk,
input Rst,
input [DataWidth - 1 : 0] WData,
input WInc,
output WFull,
output reg [DataWidth - 1 : 0] RData,
input RInc,
output REmpty
);
localparam DeepthBit = $clog2(Deepth);
reg [DeepthBit :... | 9.340894 |
module TOP (
in,
out
);
input [7:0] in;
output [5:0] out;
COUNT_BITS8 count_bits (
.IN(in),
.C (out)
);
endmodule
| 7.097448 |
module Symbol_Lookup (
input wire [2:0] in,
output reg [2:0] out
);
always @* begin
case (in)
3'd0: out <= 3'b000;
3'd1: out <= 3'b100;
3'd2: out <= 3'b010;
3'd3: out <= 3'b001;
3'd4: out <= 3'b110;
3'd5: out <= 3'b011;
3'd6: out <= 3'b111;
3'd7: out <= 3'... | 7.846087 |
module Index_Lookup (
input wire [2:0] in,
output reg [2:0] out
);
always @* begin
case (in)
3'b000: out <= 3'd0;
3'b100: out <= 3'd1;
3'b010: out <= 3'd2;
3'b001: out <= 3'd3;
3'b110: out <= 3'd4;
3'b011: out <= 3'd5;
3'b111: out <= 3'd6;
3'b101: ... | 8.600708 |
module symbolSync #(
parameter SYM_WIDTH = 1, //符号位位宽
parameter INT_WIDTH = 1, //整数部分位宽
parameter DEC_WIDTH = 14 //小数部分位宽
) (
input wire clk,
input wire rstn,
input wire signed [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] InputDataQ,
input wire signed [SYM_WIDTH+INT_WIDTH+DEC_WIDTH-1 : 0] InputD... | 7.961162 |
module symbol_game(answer, submit, clock, counter, difficulty, reset,
out_LEDG, out_LEDR, out_HEX1, out_HEX2, out_HEX3, out_HEX4,
win, lose);
input [17:0] answer;
input submit;
input clock;
input [27:0] counter;
input [1:0] difficulty;
input reset;
out... | 7.125038 |
module symbol_game_symbol_maker (
in,
out
);
input [2:0] in;
output reg [6:0] out;
always @(*) begin
case (in[2:0])
3'b000: out = 7'b1101000;
3'b001: out = 7'b1100010;
3'b010: out = 7'b1010011;
3'b011: out = 7'b1000001;
3'b100: out = 7'b1110100;
3'b101: out = 7'b01... | 7.223403 |
module symbol_game_combination_maker (
in,
out
);
input [2:0] in;
output reg [17:0] out;
always @(*) begin
case (in[2:0])
3'b000: out = 18'b10_0100_0110_1111_0000;
3'b001: out = 18'b01_0110_0001_0100_1101;
3'b010: out = 18'b00_1100_0111_1010_1010;
3'b011: out = 18'b11_0110_010... | 6.842603 |
module ratedivider (
clock,
reset,
divide,
cout
);
input clock;
input reset;
input [27:0] divide;
output reg cout;
reg [27:0] count; //counts upto divide
initial count = 0;
// new clock based on divide where output flips at divide
always @(posedge clock) begin
if (!reset) begin
... | 8.084012 |
module symbol_top2 (
CLOCK_50,
KEY,
VGA_HS,
VGA_VS,
column,
row,
VGA_B,
VGA_G,
VGA_R,
VGA_CLK,
LEDR
);
input wire CLOCK_50;
input wire [3:0] KEY;
output wire VGA_HS;
output wire VGA_VS;
output wire [9:0] column;
output wire [8:0] row;
output wire [7:0] VGA_B;
... | 7.665902 |
module symbol_top_inst (
// wr_en,
CLOCK_50,
// data_in,
KEY,
VGA_HS,
VGA_VS,
column,
// freeslots,
row,
VGA_B,
VGA_G,
VGA_R,
VGA_SYNC_N,
VGA_BLANK_N,
VGA_CLK,
LEDR
);
//input wire wr_en;
input wire CLOCK_50;
//input wire [31:0] data_in;
input wir... | 7.137362 |
module symmetric_mem_core #(
parameter RAM_WIDTH = 16,
parameter RAM_ADDR_BITS = 5
)(
input wire clockA,
input wire clockB,
input wire write_enableA,
input wire write_enableB,
input wire [RAM_ADDR_BITS-1:0] addressA,
input wire [RAM_ADDR_BITS-1:0] addressB,
input w... | 8.125302 |
module SYMM_MUL4 (
input clk_mul4,
input en_mul4,
input signed [25:0] i11,
i12,
i13,
i14,
input signed [25:0] i21,
i22,
i23,
i24,
input signed [25:0] i31,
i32,
i33,
i34,
input signed [25:0] i41,
i42,
i43,
i44,
output reg signed [25:0] o11,
... | 6.644102 |
module SYMM_SELECT (
input clk_sel,
input en_sel,
input select,
input signed [25:0] i11,
i12,
i13,
i14,
input signed [25:0] i21,
i22,
i23,
i24,
input signed [25:0] i31,
i32,
i33,
i34,
input signed [25:0] i41,
i42,
i43,
i44,
input signed ... | 6.698418 |
module SYMM_SUB (
input clk_sub,
input en_sub,
input signed [25:0] i1_11,
i1_12,
i1_13,
i1_14,
input signed [25:0] i1_21,
i1_22,
i1_23,
i1_24,
input signed [25:0] i1_31,
i1_32,
i1_33,
i1_34,
input signed [25:0] i1_41,
i1_42,
i1_43,
i1_44,
inp... | 6.5141 |
module SYMM_TEST (
input clk_test,
input en_test,
input signed [25:0] i11,
i12,
i13,
i14,
input signed [25:0] i21,
i22,
i23,
i24,
input signed [25:0] i31,
i32,
i33,
i34,
input signed [25:0] i41,
i42,
i43,
i44,
input signed [25:0] i11_2,
i... | 6.830955 |
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