code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module
module syncreg (
CLKA,
CLKB,
RST,
DATA_IN,
DATA_OUT
);
input CLKA;
input CLKB;
input RST;
input [3:0] DATA_IN;
output [3:0] DATA_OUT;
reg [3:0] regA;
reg [3:0] regB;
reg strobe_toggle;
reg ack_toggle;
... | 7.4465 |
module across clock domains.
// Uses a Handshake Pulse protocol to trigger the load on
// destination side registers
// Transfer takes 3 dCLK for destination side to see data,
// sRDY recovers takes 3 dCLK + 3 sCLK
module SyncRegister(
sCLK,
sRST,
dCLK,
... | 6.595237 |
module testSyncRegister() ;
parameter dsize = 8;
wire sCLK, sRST, dCLK ;
wire sEN ;
wire sRDY ;
reg [dsize -1:0] sCNT ;
wire [dsize -1:0] sDIN, dDOUT ;
ClockGen#(20,9,10) sc( sCLK );
ClockGen#(11,12,26) dc( dCLK );
initial
begin
sCNT = 0;
$dumpfile(... | 7.222289 |
module syncRegisterFile #(
parameter LOG = 0,
PulseWidth = 100
) (
input clk,
input _wr_en,
input [1:0] wr_addr,
input [7:0] wr_data,
input _rdL_en,
input [1:0] rdL_addr,
output [7:0] rdL_data,
input _rdR_en,
input [1:0] rdR_addr,
output [7:0] rdR_data
);
logic [31:0... | 7.223018 |
module for resets. Output resets are held for
// RSTDELAY+1 cycles, RSTDELAY >= 0. Both assertion and deassertions is
// synchronized to the clock.
module SyncReset (
IN_RST,
CLK,
OUT_RST
);
parameter RSTDELAY = 1 ; // Width of re... | 7.035349 |
module for resets. Output resets are held for
// RSTDELAY+1 cycles, RSTDELAY >= 0. Reset assertion is asynchronous,
// while deassertion is synchronized to the clock.
module SyncResetA (
IN_RST,
CLK,
OUT_RST
);
parameter RSTDELA... | 7.035349 |
module syncreset_enable_divider (
clk,
ce,
syncreset,
reset_n,
enable_in,
enable_out
);
parameter count = 1;
parameter resetcount = 0;
input clk;
input ce;
input syncreset;
input reset_n;
input enable_in;
output enable_out;
parameter width = $clog2(count);
reg [width-1:0] c... | 7.174894 |
module Syncro (
input PixClk,
output reg HSync,
output reg VSync,
output reg Video
);
// -----------------------------------
// 640x360@60Hz -- PixClk = 25.200MHz
// -----------------------------------
parameter integer H_sync_start = 656;
parameter integer H_sync_stop = 751;
parameter int... | 7.711369 |
module sync #(
parameter WIDTH = 1
) (
input clk,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
reg [WIDTH-1:0] buffer;
always @(posedge clk) begin
buffer <= d;
q <= buffer;
end
endmodule
| 7.012515 |
module d_flip_flop #(
parameter WIDTH = 1
) (
input clk,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk) q <= d;
endmodule
| 8.794161 |
module syncSRAM #(
parameter DW = 256,
AW = 8
) (
input clk,
input we,
input [AW-1:0] wa,
input [DW-1:0] wd,
input re,
input [AW-1:0] ra,
output [DW-1:0] rd
);
parameter DP = 1 << AW; // depth
reg [DW-1:0] mem[0:DP-1];
reg [DW-1:0] reg_rd;
assign rd = reg_rd;
always @(p... | 8.304167 |
module is the dataflow level model of the counter.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
module syncUp(q, clk, rst);
output [3:0] q;
input clk, rst;
wire [3:0] d, qb;
// Connecting DFFs to form a 4 bit counter
assign d[3] = (qb[0] & q[3]) | (qb[1] & q[... | 8.908359 |
module DFlipFlop (
q,
qBar,
D,
clk,
rst
);
input D, clk, rst;
output q, qBar;
reg q;
not n1 (qBar, q);
always @(negedge rst or posedge clk) begin
if (!rst) q = 0;
else q = D;
end
endmodule
| 7.170064 |
module is intended for use with GTKwave on the PC.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
`include "syncUp.v"
module syncUpGTK;
// connect the two modules
wire [3:0] qBench;
wire clkBench, rstBench;
// declare an instance of the syncUp module
syncUp my... | 9.106975 |
module is intended for use with the DE1_SoC and Spinal Tap.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
module syncUpTop (LEDR, CLOCK_50, SW);
output [3:0] LEDR; // present state output
input CLOCK_50;
input [9:0] SW;
wire [31:0] clk; // choosing from 32 d... | 9.106975 |
module clock_divider (
clock,
divided_clocks
);
input clock;
output [31:0] divided_clocks;
reg [31:0] divided_clocks;
initial divided_clocks = 0;
always @(posedge clock) divided_clocks = divided_clocks + 1;
endmodule
| 6.818038 |
module syncUp_DE1 (
LEDR,
SW,
CLOCK_50
);
//Declaration of clocks, switches, and LEDs for usage
output [9:0] LEDR;
input [9:0] SW;
input CLOCK_50;
wire [31:0] clk;
//A 50 MHz clock is used for the DE1_SoC and Signal Tap
parameter clkBit = 0;
//Set unused LED's to low
assign LEDR[9:4] = ... | 7.044091 |
module that acts as our testbench. Required for iVerilog analysis
module Tester (clkTest, rstTest, qTest);
//Input and output decleration to connect to DUT
output reg rstTest, clkTest;
input [3:0] qTest;
parameter stimDelay = 20;
initial // Stimulus
begin
//Manually changing clock and applying reset
clkT... | 7.301252 |
module syncVGAGen (
input wire px_clk, // Pixel clock.
output wire [9:0] x_px, // X position for actual pixel.
output wire [9:0] y_px, // Y position for actual pixel.
output wire hsync, // Horizontal sync out.
output wire vsync, // Vertical sync out.... | 7.856028 |
module SyncWire (
DIN,
DOUT
);
parameter width = 1;
input [width - 1 : 0] DIN;
output [width - 1 : 0] DOUT;
assign DOUT = DIN;
endmodule
| 7.635778 |
module sync_1bit #(
parameter N_STAGES = 2 // Should be >=2
) (
input wire clk,
input wire rst_n,
input wire i,
output wire o
);
(* keep = 1'b1 *) reg [N_STAGES-1:0] sync_flops;
always @(posedge clk or negedge rst_n)
if (!rst_n) sync_flops <= {N_STAGES{1'b0}};
else sync_flops <= {s... | 8.65853 |
module clk_wiz_0 (
clk_out1,
clk_out2,
reset,
locked,
clk_in1
);
output clk_out1;
output clk_out2;
input reset;
output locked;
input clk_in1;
wire clk_in1;
wire clk_out1;
wire clk_out2;
wire locked;
wire reset;
clk_wiz_0_clk_wiz inst (
.clk_in1(clk_in1),
.clk_out1... | 6.750754 |
module clk_wiz_0_clk_wiz (
clk_out1,
clk_out2,
reset,
locked,
clk_in1
);
output clk_out1;
output clk_out2;
input reset;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clk_out2;
wire clk_out2_clk_wiz_0;
wire cl... | 7.432971 |
module sync_2ff (
clk,
din,
dout
);
input wire clk;
input wire din;
output wire dout;
reg temp1;
reg temp2;
assign dout = temp2;
always @(posedge clk) begin
temp1 <= din;
temp2 <= temp1;
end
endmodule
| 6.684057 |
module sync_2_fifo (
input clk,
input rst,
output [ 1:0] afull_out,
input [ 1:0] write_en_in,
input [63:0] data_1_in,
input [63:0] data_0_in,
output empty_out,
input read_en_in,
output [63:0] data_1_out,
output [63:0] data_0_out
);
wire [1:0] fifo_empty_s;
... | 7.617307 |
module sync_3_fifo (
input clk,
input rst,
output [ 2:0] afull_out,
input [ 2:0] write_en_in,
input [63:0] data_2_in,
input [63:0] data_1_in,
input [63:0] data_0_in,
output empty_out,
input read_en_in,
output [63:0] data_2_out,
output [63:0] data_1_out,
... | 8.519773 |
module sync_addr_gray #(
parameter FIFO_DEPTH_BIT = 10'd4
) (
input w_clk,
r_clk,
input w_rst,
r_rst,
input [FIFO_DEPTH_BIT:0] write_addr_gray,
input [FIFO_DEPTH_BIT:0] read_addr_gray,
output reg [FIFO_DEPTH_BIT:0] write_addr_gray_sync,
output r... | 6.693009 |
module sync_adpll
(
refclk,
reset,
sync_stream,
out_bclk
);
parameter ACCUM_SIZE = 24;
parameter CLK_OVERSAMPLE_LOG2 = 4; // Clock oversample = 16
input refclk, reset, sync_stream;
output out_bclk;
// IO regs
reg out_bclk;
// Internal regs
reg [ACCUM_SIZE-1:0] accum;
reg [ACCUM_SIZE-1:0] ... | 7.403748 |
module sync_and_debounce_one #(
parameter depth = 8
) (
input clk,
input sw_in,
output reg sw_out
);
reg [depth - 1:0] cnt;
reg [ 2:0] sync;
wire sw_in_s;
assign sw_in_s = sync[2];
always @(posedge clk) sync <= {sync[1:0], sw_in};
always @(posedge clk)
... | 7.085396 |
module sync_and_debounce #(
parameter w = 1,
depth = 8
) (
input clk,
input [w - 1:0] sw_in,
output [w - 1:0] sw_out
);
genvar sw_cnt;
generate
for (sw_cnt = 0; sw_cnt < w; sw_cnt = sw_cnt + 1) begin : gen_sync_and_debounce
sync_and_debounce_one #(
.depth(depth... | 7.085396 |
module sync_and_debounce_one #(
parameter depth = 8
) (
input clk,
input reset,
input sw_in,
output reg sw_out
);
reg [depth - 1:0] cnt;
reg [ 2:0] sync;
wire sw_in_s;
assign sw_in_s = sync[2];
always @(posedge clk or posedge reset)
if (reset) s... | 7.085396 |
module sync_async_reset (
input clock,
input reset_n,
input data_a,
input data_b,
output out_a,
output out_b
);
reg reg1, reg2;
reg reg3, reg4;
assign out_a = reg1;
assign out_b = reg2;
assign rst_n = reg4;
always @(posedge clock, negedge reset_n) begin
if (!reset_n) begin
... | 6.677077 |
modules for Autonomous wrapper use
// Description : Clock crossing support for Autonomous
// This contains support for cross-clock-domain (CDC) synchronization
// as needed specifically for autonomous regs. This is basically
// only 4-phase handshakes
//
// -----------------------------------------------... | 8.776205 |
module SYNC_AClr_C2S (
input CLK, // system domain
input RSTn,
input local_set,
input async_clear,
output o_value
);
reg value; // CLK domain
always @(posedge CLK or negedge RSTn)
if (!RSTn) value <= 1'b0;
else if (local_set) value <= 1'b1;
else if (async_clear) // CDC
valu... | 6.822945 |
module SYNC_S2B #(
parameter WIDTH = 1
) (
input rst_n,
input clk,
input [WIDTH-1:0] scl_data,
output [WIDTH-1:0] out_clk // output copy in CLK domain
);
reg [WIDTH-1:0] clk_copy;
assign out_clk = clk_copy;
// note: could use clk_copy^scl_data as test to allow ... | 7.850005 |
module sync_axi2ddr_1bit (
input wire rst,
input wire axi_clk,
input wire ddr_clk,
input wire [0:0] axi_data,
output wire [0:0] ddr_data
);
wire [0:0] ddr_stage1;
wire [0:0] ddr_stage2;
// axi data
(* DONT_TOUCH="yes" *)
FDCE #(
.INIT(1'b0)
) axidata_0 (
... | 8.11951 |
module sync_axi2ddr_nbit #(
parameter WIDTH = 32
) (
input wire rst,
input wire axi_clk,
input wire ddr_clk,
input wire [WIDTH-1:0] axi_data,
output wire [WIDTH-1:0] ddr_data
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
syn... | 8.11951 |
module txtest (
input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
input wire load, //-- Señal de cargar / desplazamiento
output reg tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
//-- Pruebas del caso peor: a 300 baudios
parameter BAUD = 400... | 7.489425 |
module sync_bench;
parameter width = 16;
reg a_clk, a_reset;
reg b_clk, b_reset;
wire [width-1:0] a_data;
wire a_srdy, a_drdy;
wire b_srdy, b_drdy;
initial begin
`ifdef VCS
$vcdpluson;
`else
$dumpfile("sync.vcd");
$dumpvars;
`endif
a_clk = 0;
b_clk = 0;
a_reset = 1;
b... | 6.86177 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module sync_cdc_bit #(
parameter integer C_SYNC_STAGES = 3
) (
input wire clk,
input wire d,
output wire q
);
xpm_cdc_single #(
.DEST_SYNC_FF(C_SYNC_STAGES), // DECIMAL; range: 2-10
.INIT_SYNC_FF ( 0 ), // DECIMAL; 0 = disable simulation init values, 1=enable simulation ... | 7.959215 |
module sync_cdc_bus #(
parameter integer C_SYNC_STAGES = 3,
parameter integer C_SYNC_WIDTH = 8
) (
input wire src_clk,
input wire [C_SYNC_WIDTH - 1 : 0] src_in,
input wire src_req,
output wire src_ack,
input wire ... | 8.114374 |
module sync_cell (
input wire clk,
input wire rst_n,
input wire in,
output wire out
);
reg in_d1;
reg in_d2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
in_d1 <= 1'b0;
in_d2 <= 1'b0;
end else begin
in_d1 <= in;
in_d2 <= in_d1;
end
end
... | 6.838352 |
module sync_check (
pclk,
rst,
enable,
hsync,
vsync,
csync,
blanc,
hpol,
vpol,
cpol,
bpol,
thsync,
thgdel,
thgate,
thlen,
tvsync,
tvgdel,
tvgate,
tvlen
);
input pclk, rst, enable, hsync, vsync, csync, blanc;
input hpol, vpol, cpol, bpol;
... | 7.543711 |
module sync_clk_core ( /*AUTOARG*/
// Inputs
clk_xgmii_tx,
reset_xgmii_tx_n
);
input clk_xgmii_tx;
input reset_xgmii_tx_n;
//input ctrl_tx_disable_padding;
//output ctrl_tx_disable_padding_ccr;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)... | 6.713529 |
module sync_clk_wb ( /*AUTOARG*/
// Outputs
status_crc_error,
status_fragment_error,
status_txdfifo_ovflow,
status_txdfifo_udflow,
status_rxdfifo_ovflow,
status_rxdfifo_udflow,
status_pause_frame_rx,
status_local_fault,
status_remote_fault,
// Inputs
wb_clk_i,
wb_rst... | 6.854147 |
module sync_clk_xgmii_tx ( /*AUTOARG*/
// Outputs
ctrl_tx_enable_ctx,
status_local_fault_ctx,
status_remote_fault_ctx,
// Inputs
clk_xgmii_tx,
reset_xgmii_tx_n,
ctrl_tx_enable,
status_local_fault_crx,
status_remote_fault_crx
);
input clk_xgmii_tx;
input reset_xgmii_tx_n;
... | 7.832497 |
module name - clock_output_control
// Version: COC_V1.0.0_20211202
// Created:
// by - fenglin
// at - 12.2021
////////////////////////////////////////////////////////////////////////////
// Description:
// clock_output_control
///////////////////////////////////////////////////////////////////... | 8.290552 |
module syn_control (
input clk_50m,
input cfg_rst,
input lose,
input corase_syn_en,
input fine_syn_en,
input slot_interrupt,
input [31:0] corase_syn_pos,
input [31:0] fine_syn_pos,
output [31:0] corase_pos,
output [31:0] fine_pos,
ou... | 6.86222 |
module sync_control_dual #(
parameter DATA_WIDTH = 32,
max_steps = 7
) (
input clk,
input finished1,
input finished2,
input rst, // a reset flag that reset all operations; after lap > max_steps, rst needs to be set high by PS to reset everything
output rdy1,
output rdy2, //
output ... | 8.153933 |
module sync_control_dual_tb #(
parameter period = 10,
DATA_WIDTH = 32,
max_steps = 7
) ();
integer i, j;
reg clk, finished1, finished2, rst;
wire [DATA_WIDTH-1:0] l_step;
sync_control_dual #(
.DATA_WIDTH(DATA_WIDTH),
.max_steps (max_steps)
) lap_control (
.clk(clk),
.fini... | 8.153933 |
module that needs to keep track of which Row/Col
// position we are on in the middile of frame
////////////////////////////////////////////////////////////////////////////////
module sync_count
(
input i_clk,
input i_hsync,
input i_vsync,
output reg o_hsync,
output reg o_vsync... | 7.477982 |
module Sync_counter_32bit (
out,
clock,
clear_bar,
count_en
);
output [31:0] out;
input clock, count_en, clear_bar;
Sync_counter_4bit C0 (
.out(out[3:0]),
.and_out(aout0),
.clock(clock),
.clear_bar(clear_bar),
.count_en(count_en)
);
and_2_GT6100 C0A (
ce1... | 6.642277 |
module Sync_counter_4bit (
out,
and_out,
clock,
clear_bar,
count_en
);
output [3:0] out;
output and_out;
input clock, count_en, clear_bar;
Toggle_FF_GT6100 T0 (
.out(out[0]),
.en(count_en),
.clear_bar(clear_bar),
.clock(clock)
);
Toggle_FF_GT6100 T1 (
.out... | 6.642277 |
module testbench;
parameter PERIOD = 20;
reg i_clk, i_rst_n;
wire [9:0] o_cnt_dat;
sync_counter cnt_inst (
.CLOCK_50(i_clk),
.KEY({i_rst_n, 1'b0}),
.LEDR(o_cnt_dat)
);
initial begin
i_clk = 0;
forever #(PERIOD / 2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
... | 7.015571 |
module sync_cs_dev (
clk,
addr,
dq,
cs_,
we_,
oe_,
ack_
);
input clk;
input [15:0] addr;
inout [31:0] dq;
input cs_, we_, oe_;
output ack_;
reg [31:0] data_o;
reg [31:0] mem[0:1024];
wire rd, wr;
integer rd_del;
reg [31:0] rd_r;
wire rd_d;
integer wr_del;
reg [31... | 6.681558 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module sync_ddr2axi_1bit (
input wire rst,
input wire axi_clk,
input wire ddr_clk,
input wire [0:0] ddr_data,
output wire [0:0] axi_data
);
wire [0:0] axi_stage1;
wire [0:0] axi_stage2;
// ddr data
(* DONT_TOUCH="yes" *)
FDCE #(
.INIT(1'b0)
) ddrdata_0 (
... | 8.149816 |
module sync_ddr2axi_nbit #(
parameter WIDTH = 4
) (
input wire rst,
input wire axi_clk,
input wire ddr_clk,
input wire [WIDTH-1:0] ddr_data,
output wire [WIDTH-1:0] axi_data
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
sync... | 8.149816 |
module sync_dd_c (
input wire clk,
input wire reset_,
input wire sync_in,
output wire sync_out
);
reg sync_in_p1;
reg sync_in_p2;
always @(posedge clk) begin
if (!reset_) begin
sync_in_p1 <= 1'b0;
sync_in_p2 <= 1'b0;
end else begin
sync_in_p1 <= sync_in;
sync_i... | 7.332177 |
module sync_debouncer_10ms (
// OUTPUTs
signal_debounced, // Synchronized and 10ms debounced signal
// INPUTs
clk_50mhz, // 50MHz clock
rst, // reset
signal_async // Asynchonous signal
);
// OUTPUTs
//=========
output signal_debounced; // Synchronized and 10ms debounced signal
/... | 6.58024 |
module sync_delay #(
//=============
// parameters
//=============
parameter DATA_WIDTH = 32,
parameter DELAY_CYCLES = 1
) (
//=====================
// input/output ports
//=====================
input clk,
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:... | 6.888122 |
module sync_dp_ram #(
parameter ADDR_WIDTH = 8, // address's width
parameter DATA_WIDTH = 8 // data's width
) (
input clk, // systems's clock
input cen_0, // chip select, port 0, low active
input wen_0, // write enable, port 0, low active
input ... | 8.376729 |
module
KEYWORDS: dual clock, sync
MODIFICATION HISTORY:
$Log$
Xudong 18/6/20 original version
\*-------------------------------------------------------------------------*/
module sync_dual_clock
#(
parameter WIDTH = 6, // 带同步的数据宽度
parameter SYNC_STAGE = 2 // 同步的级数（级数越多，竞争冒险越少）
)
(
input wire clock_dst... | 7.592673 |
module sync_dual_port_ram #(
parameter ADDRESS_WIDTH = 4, // number of words in ram
DATA_WIDTH = 4 // number of bits in word
)
// IO ports
(
input wire clk, // clk for synchronous read/write
input wire write_en, // signal to enable synchr... | 9.050225 |
module sync_edge (
input clk,
rst_n,
sig,
output rise_edge,
fall_edge,
sig_edge
);
reg sig_r;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) sig_r <= 0;
else sig_r <= sig;
end
assign rise_edge = sig & !sig_r;
assign fall_edge = !sig & sig_r;
assign sig_edge = si... | 6.90187 |
module sync_edge_detect (
input async_sig,
output sync_out,
input clk,
output reg rise,
output reg fall
);
reg [1:3] resync;
always @(posedge clk) begin
// detect rising and falling edges.
rise <= ~resync[3] & resync[2];
fall <= ~resync[2] & resync[3];
// update history ... | 6.898603 |
module sync_edge_detect_tb ();
reg t_clk;
reg t_rst_n;
reg t_d;
wire t_flag;
sync_edge_detect dut (
.clock(t_clk),
.rst_n(t_rst_n),
.din (t_d),
.flag (t_flag)
);
//Produce the clock
initial begin
t_clk = 0;
end
always #10 t_clk = ~t_clk;
//Generates a reset sign... | 6.898603 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module sync_fifo_32 (
clk,
rst,
read_req,
write_data,
write_enable,
read_data,
fifo_empty,
rdata_valid
);
input clk;
input rst;
input read_req;
input [31:0] write_data;
input write_enable;
output [31:0] read_data;
output fifo_empty;
output rdata_valid;
reg [4:0] read_p... | 7.237888 |
module. */
`timescale 1ns / 100ps
module sync_fifo_ff (clk, rst, read_req, write_data, write_enable, rollover_write,
read_data, fifo_empty, rdata_valid);
input clk;
input rst;
input read_req;
input [90:0] write_data;
input write_enable;
input rollover_write;
output [90:0] read_data;
output fifo_empty;
output r... | 6.895322 |
module sync_fifo_in #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 4
) (
input wire clk_i,
input wire resetn_i,
input wire fifo_write_en_h_i,
input wire [DATA_WIDTH-1:0] fifo_write_data_i,
output reg fifo_full_h_o,
input wire [ ADDR_WIDTH:0]... | 8.009897 |
module sync_fifo_out #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 4
) (
input wire clk_i,
input wire resetn_i,
input wire [ ADDR_WIDTH:0] write_addr_i,
output wire [ ADDR_WIDTH:0] read_addr_o,
input wire [DATA_WIDTH-1:0] read_data_i,
input wire fifo_read_e... | 8.730267 |
module sync_fifo_sim ();
reg clk;
reg rst_n;
reg [31:0] counter_w;
wire [31:0] rdata;
reg [31:0] counter_r;
reg w_req;
reg r_req;
wire full;
wire empty;
initial begin
clk <= 0;
rst_n <= 0;
w_req <= 0;
r_req <= 0;
counter_w <= 0;
counter_r <= 0;
#100 rst_n <= 1;
#200 ... | 7.300378 |
module sync_fifo_tb;
localparam FIFO_WIDTH = 32;
localparam FIFO_DEPTH = 8;
localparam ADDR_WIDTH = 3;
reg clk;
reg rst_n;
reg wr_en;
reg [FIFO_WIDTH-1:0] wr_data;
reg rd_en;
wire full;
wire... | 6.967938 |
module Sync_gen (
input clk,
output vga_h_sync,
output vga_v_sync,
output reg InDisplayArea,
output reg [9:0] CounterX,
output reg [9:0] CounterY
);
//=======================================//
// Clock Divider //
//================================... | 8.172637 |
module sync_generate #(
parameter cw = 10,
parameter minc = 128
) (
input clk,
input [cw-1:0] cset,
output sync
);
reg [cw-1:0] count = 0;
reg ctl_bit = 0, invalid = 0;
wire rollover = count == 1;
always @(posedge clk) begin
count <= rollover ? cset : (count - 1);
invalid <= cse... | 6.900043 |
module sync_generator (
input wire vga_clk,
input wire reset,
output reg disp_en,
output reg hsync,
output reg vsync,
output reg [31:0] column,
output reg [31:0] row
);
localparam h_total = 800; //total number of pixels
localparam h_disp = 640; //displayed interval
localparam h_pw =... | 6.935912 |
module sync_generators (
input clk,
input reset,
input enable,
output wire hsync,
output wire vsync,
output wire valid_data,
output reg [`log2NUM_COLS-1:0] x,
output reg [`log2NUM_ROWS-1:0] y
);
/* Regs and Wires */
reg [`log2NUM_XCLKS_IN_ROW-1 : 0] pixel_counter;
reg [`log2NUM_L... | 6.935912 |
module sync_generator_pal_ntsc (
input wire clk, // 7 MHz
input wire in_mode, // 0: PAL, 1: NTSC
output reg csync_n,
output reg hsync_n,
output reg vsync_n,
output wire [8:0] hc,
output wire [8:0] vc,
output reg vblank,
output reg hblank,
output reg blank
);
parameter PAL = ... | 6.935912 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module sync_header_align #(
) (
input clk,
input reset,
input [65:0] i_data,
output i_slip,
input i_slip_done,
output [63:0] o_data,
output [1:0] o_header,
output o_block_sync
);
assign {o_header, o_data} = i_data;
// TODO : Add alignment FSM
localparam STATE_SH_HUNT = 3'b001;
... | 7.188995 |
module sync_level2level (
clk,
rst_b,
sync_in,
sync_out
);
parameter SIGNAL_WIDTH = 1;
parameter FLOP_NUM = 3;
input clk;
input rst_b;
input [SIGNAL_WIDTH-1:0] sync_in;
output [SIGNAL_WIDTH-1:0] sync_out;
reg [SIGNAL_WIDTH-1:0] sync_ff [FLOP_NUM-1:0];
wire clk;
... | 8.759645 |
module sync_level2pulse (
clk,
rst_b,
sync_in,
sync_out,
sync_ack
);
input clk;
input rst_b;
input sync_in;
output sync_out;
output sync_ack;
reg sync_ff;
wire clk;
wire rst_b;
wire sync_in;
wire sync_out;
wire sync_ack;
wire sync_out_level;
sync_level2level x_sync_l... | 7.54875 |
module sync_logic #(
parameter c_DATA_WIDTH = 10
) (
rstn,
wr_clk,
wr_data,
rd_clk,
rd_data
);
input rstn;
input wr_clk;
input [c_DATA_WIDTH-1:0] wr_data;
input rd_clk;
output [c_DATA_WIDTH-1:0] rd_data;
//registers driven by wr_clk
reg [1:0] update_ack_dly;
reg u... | 7.839665 |
module sync_low (
clk,
n_rst,
async_in,
sync_out
);
input clk, n_rst, async_in;
output sync_out;
wire values;
DFFSR values_reg (
.D (async_in),
.CLK(clk),
.R (n_rst),
.S (1'b1),
.Q (values)
);
DFFSR sync_out_reg (
.D (values),
.CLK(clk),
... | 6.522048 |
module sync_module (
input CLK_40M,
input RSTn,
output reg end_sig,
output reg start
);
reg [31:0] Count;
parameter T1s = 32'd25_000_000;
always @(posedge CLK_40M or negedge RSTn)
if (!RSTn) begin
end_sig <= 1'b0;
start <= 1'b1;
end else if (Count == T1s) begin
st... | 6.618592 |
module sync_pre_process (
input clk,
input reset_n,
input ext_hsync_i,
input ext_vsync_i,
output hsync_redge_o,
output vsync_redge_o,
output hsync_fedge_o,
output vsync_fedge_o
);
parameter DLY_WIDTH = 12;
reg hsync_temp;
reg vsync_temp;
reg [... | 9.524769 |
module sync_ptr #(
parameter ASIZE = 4
) (
input wire dest_clk,
input wire dest_rst_n,
input wire [ASIZE:0] src_ptr,
output reg [ASIZE:0] dest_ptr
);
reg [ASIZE:0] ptr_x;
always @(posedge dest_clk or negedge dest_rst_n) begin
if (!dest_rst_n) {dest_ptr, ptr_x} <= 0... | 7.489374 |
module sync_pulse_synchronizer ( /*AUTOARG*/
// Outputs
sync_out,
so,
// Inputs
async_in,
gclk,
rclk,
si,
se
);
output sync_out;
output so;
input async_in;
input gclk;
input rclk;
input si;
input se;
wire pre_sync_out;
wire so_rptr;
wire so_lockup;
// Flop ... | 6.944583 |
module sync_ram (
aclr,
data,
rdclk,
wrclk,
q
);
parameter data_bits = 32;
input aclr;
input [data_bits-1:0] data;
input rdclk;
input wrclk;
output [data_bits-1:0] q;
wire [2:0] wraddress;
wire [2:0] rdaddress;
assign wraddress = 0;
assign rdaddress = 0;
dp_ram #(
.DAT... | 6.884981 |
module sync_ram_data (
input clk,
input en, //access enable, HIGH valid
input [ 3:0] wen, //write enable by byte, HIGH valid
input [ 9:0] addr,
input [31:0] wdata,
output [31:0] rdata
);
reg [31:0] bit_array[10:0];
reg en_r;
reg [ 3:0] wen_r;
reg [ ... | 6.88962 |
module sync_ram_display (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdusedw,
wrusedw
);
parameter data_bits = 41;
parameter addr_bits = 4;
input aclr;
input [data_bits-1:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [data_bits-1:0] q;
output... | 6.967505 |
module sync_ram_emul (
input clk,
input en, //access enable, HIGH valid
input [ 3:0] wen, //write enable by byte, HIGH valid
input [ 9:0] addr,
input [31:0] wdata,
output [31:0] rdata
);
reg [31:0] bit_array[100:0];
reg en_r;
reg [ 3:0] wen_r;
reg [... | 6.861571 |
module sync_ram_wf_x32 ( /*AUTOARG*/
// Outputs
dout,
// Inputs
clk,
web,
enb,
addr,
din
);
parameter ADDR_WIDTH = 10;
input clk;
input [3:0] web;
input [3:0] enb;
input [9:0] addr;
input [31:0] din;
output [31:0] dout;
reg [31:0] RAM [(2<<ADDR_WIDTH)-1:0];
reg [31:0... | 6.793915 |
module sync_rebuiltSignal (
input clock,
input [3:0] sensors,
output [3:0] rebuiltSignal
);
reg [3:0] rebuiltSignal_reg;
wire [3:0] rising_edge_wire;
wire [3:0] falling_edge_wire;
//syncing sensors /////////////
signalSync sync_reb0 (
.clock(clock),
.asynchronous_signal(sensors[0]),... | 7.126084 |
module sync_reg #(
parameter INIT = 0,
parameter ASYNC_RESET = 0
) (
input clk,
input rst,
input in,
output out
);
(* ASYNC_REG = "TRUE" *)reg sync1;
(* ASYNC_REG = "TRUE" *)reg sync2;
assign out = sync2;
generate
if (ASYNC_RESET) begin
always @(posedge clk or pos... | 6.715762 |
module sync_regf (
clk, // system clock
reset_b, // power on reset
halt, // system wide halt
addra, // Port A read address
a_en, // Port A read enable
addrb, // Port B read address
b_en, // Port B read enable
addrc, // Port C write address
dc, // Port C write data
w... | 7.134558 |
module sync_regs #(
parameter WIDTH = 32,
parameter DEPTH = 2 // minimum of 2
) (
input clk,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [WIDTH-1:0]
din_meta = 0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -to [... | 7.401305 |
module sync_regs_aclr_m2 #(
parameter WIDTH = 32,
parameter DEPTH = 2 // minimum of 2
) (
input clk,
input aclr,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [WIDTH-1:0]
din_meta = 0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMEN... | 6.640836 |
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