code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SYM_Mod (
input CLK_I,
RST_I,
input [5:0] DAT_I,
input CYC_I,
WE_I,
STB_I,
output ACK_O,
output reg [31:0] DAT_O,
output reg CYC_O,
STB_O,
output WE_O,
input ACK_I,
input [1:0] STD,
input [1:0] MOD
);
... | 6.895176 |
module MYMUL (
A,
B,
Y
);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output [WIDTH-1:0] Y;
assign Y = A * B;
endmodule
| 8.265005 |
module \$mul (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
MYMUL #(... | 7.524175 |
module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn);
input clk;
input [30:0] opa, opb;
output inf, ind, qnan, snan, opa_nan, opb_nan;
output opa_00, opb_00;
output opa_inf, opb_inf;
output opa_dn;
output opb_dn;
///////////////////////////////... | 6.521738 |
module mul_r2 (
clk,
opa,
opb,
prod
);
input clk;
input [23:0] opa, opb;
output [47:0] prod;
reg [47:0] prod1, prod;
always @(posedge clk) prod1 <= #1 opa * opb;
always @(posedge clk) prod <= #1 prod1;
endmodule
| 6.757243 |
module add_sub27 (
add,
opa,
opb,
sum,
co
);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb});
endmodule
| 6.628721 |
module is designed for asynchronous clocks and transfers a one clock
// period long pulse from one clock domain to another. The maximum delay is
// one clock domain A period plus two clock domain B periods.
//
module syn2clk(
input a, // input
input aclk, // input clock
input arst, // reset input
output b, //... | 7.589677 |
module is designed for asynchronous clocks and transfers a one clock
// period long pulse from one clock domain to another. The maximum delay is
// one clock domain A period plus two clock domain B periods. This version
// has an enable for the output clock.
//
module syn2clkoe(
input a, // input
input aclk, // in... | 7.589677 |
module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn);
input clk;
input [30:0] opa, opb;
output inf, ind, qnan, snan, opa_nan, opb_nan;
output opa_00, opb_00;
output opa_inf, opb_inf;
output opa_dn;
output opb_dn;
///////////////////////////////... | 6.521738 |
module mul_r2 (
clk,
opa,
opb,
prod
);
input clk;
input [23:0] opa, opb;
output [47:0] prod;
reg [47:0] prod1, prod;
always @(posedge clk) prod1 <= #1 opa * opb;
always @(posedge clk) prod <= #1 prod1;
endmodule
| 6.757243 |
module add_sub27 (
add,
opa,
opb,
sum,
co
);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb});
endmodule
| 6.628721 |
module SynAddCounter (
clk,
reset,
dout
);
input clk, reset;
wire [3:0] Q;
output [6:0] dout;
wire T2, T3;
and T_2 (T2, Q[0], Q[1]);
and T_3 (T3, T2, Q[2]);
Tflip_flop Q_0 (
.T(1'b1),
.clk(clk),
.reset(reset),
.Q(Q[0])
);
Tflip_flop Q_1 (
.T(Q[0]),
.c... | 7.005917 |
module SynAddCounter_tb;
reg clk, reset;
wire [6:0] dout;
initial begin
clk <= 0;
repeat (40) #55 clk <= ~clk;
end
initial begin
reset <= 0;
#10 reset <= ~reset;
#2000 reset <= ~reset;
#50 reset <= ~reset;
end
SynAddCounter synaddcounter (
.clk (clk),
.reset(reset)... | 7.005917 |
module synapse #(
parameter p_width = 9,
parameter p_weight_width = 9
) (
input i_clk,
input i_rst_n,
input i_event,
input [ p_weight_width-1:0] i_weight,
output [ p_width -1:0] o_t... | 7.703646 |
module synaps_weight #(
parameter p_input_width = 9,
parameter p_weight_width = 9
) (
input [ p_input_width -1:0] i_synaps,
input [ p_weight_width -1:0] i_weight,
output [p_weight_width + p_input_width -1 : 0] o_cell_out
);
assign o_cell_out = i_synaps * i_we... | 7.23079 |
module SynapticIntegrationUnit #(
parameter INTEGER_WIDTH = 16,
parameter DATA_WIDTH_FRAC = 32,
parameter DATA_WIDTH = INTEGER_WIDTH + DATA_WIDTH_FRAC
) (
input wire signed [(DATA_WIDTH-1):0] gex,
input wire signed [(DATA_WIDTH-1):0] gin,
input wire signed [(DATA_WIDTH-1):0] ExWeightSum,
... | 8.293417 |
module
//
// Project: ODIN - An online-learning digital spiking neuromorphic processor
//
// Author: C. Frenkel, Université catholique de Louvain (UCLouvain), 04/2017
//
// Cite/paper: C. Frenkel, M. Lefebvre, J.-D. Legat and D. Bol, "A 0.086-mm² 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning
// Digit... | 7.855863 |
module SRAM_8192x32_wrapper (
// Global inputs
input RSTN, // Reset
input CK, // Clock (synchronous read/write)
// Control and data inputs
input CS, // Chip select (active low) (init low)
input WE, // Write enable (active low)
input [12:0] A, // Address bus
input... | 7.469494 |
module sync (
////////// inputs //////////
input clk, // clock
input rst_n, // active low reset
input a, // input to be synchronized
////////// outputs //////////
output y
);
parameter P_DEFVAL = 1'b0;
parameter P_NFF = 2;
localparam NFF = (P_NFF > 1) ? P_NFF : 2;
// TBA Fri ... | 8.281552 |
module sync1(
input clk,rst_n,
input din,
output reg dout
);
reg din_r;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
dout<=0;
din_r<=0;
else begin
din_r<=din;
dout<=din_r;
end
end
endmodule
| 6.712543 |
module sync1s (
f_clk,
s_clk,
rst_n,
in_fclk,
out_sclk
);
parameter WIDTH = 1;
input f_clk; // Fast clock.
input s_clk; // Slow clock.
input rst_n; // reset signal.
input [WIDTH-1:0] in_fclk; // Input pulse in fast clock domain.
output [WIDTH-1:0] out_sclk; // Output pulse in slo... | 6.646049 |
module sync2bcs (
input clk,
input rst, // !SPI_running
input [31:0] frame_No, // FIFO_TIME_TO_XIKE
output [11:0] sec,
output sync_pulse
);
parameter fs = 25000;
parameter pulse_width = 100; //100ms
//parameter [7:0] INTERVAL [7:0] = {1, 3, 14, 15, 92, 65, 3... | 7.14964 |
module sync2ff (
input wire dst_clk,
input wire din,
output wire dout
);
reg [1:0] d = 2'b00;
assign dout = d[1];
always @(posedge dst_clk) d[0] <= din;
always @(posedge dst_clk) d[1] <= d[0];
endmodule
| 6.84922 |
module sync2s (
rst,
clk,
i,
o
);
input rst;
input clk;
input i;
output o;
reg [1:0] s;
always @(posedge clk)
if (rst) s <= 0;
else s <= {s[0], i};
assign o = s[1];
endmodule
| 7.424263 |
module sync2_toggle_to_pulse (
input clk,
input rst,
input toggle,
output pulse,
output reg out_toggle
);
wire s_toggle;
sync2 i_sync2 (
clk,
rst,
toggle,
s_toggle
);
always @(posedge clk or posedge rst)
if (rst) out_toggle <= 0;
else out... | 6.659074 |
module, where data is synchronized
// by passing through 2 registers of the destination clock
module SyncBit (
sCLK,
sRST,
dCLK,
sEN,
sD_IN,
dD_OUT
);
parameter init = 1'b0; // initial value for all ... | 7.352735 |
module, where data is synchronized
// by passing through ONLY ONE register of the destination clock, and
// that clocked on the negedge.
module SyncBit05 (
sCLK,
sRST,
dCLK,
sEN,
sD_IN,
dD_OUT
)... | 7.352735 |
module, where data is synchronized
// by passing through ONLY ONE register of the destination clock.
module SyncBit1 (
sCLK,
sRST,
dCLK,
sEN,
sD_IN,
dD_OUT
);
parameter init = 1'b0; // initial value... | 7.352735 |
module, where data is synchronized
// by passing through 2 registers of the destination clock where the first
// register is triggered on the negative edge
module SyncBit15 (
sCLK,
sRST,
dCLK,
sEN,
sD_IN,
dD_OUT
... | 7.352735 |
module syncbram_fifo (
clk,
rst,
buf_in,
buf_out,
wr_en,
rd_en,
buf_empty,
buf_full
);
// system clock, reset
input clk;
input rst;
// write enable, read enable
input wr_en;
input rd_en;
// buffer data in
input [7 : 0] buf_in;
// buffer data out
output [7 : 0] buf_ou... | 7.246447 |
module master (
input clock,
w,
output [15:0] address,
inout [15:0] data
);
reg [15:0] ar, dr;
assign address = ar;
assign data = (w) ? dr : 16'hzzzz;
always @(*) begin
if (!w) dr = #1 data;
end
endmodule
| 7.034859 |
module syncCorrector (
input wire pxlClk,
input wire rst,
input wire vsync,
input wire hsync,
input wire de,
output wire vsync_o,
output wire hsync_o,
output wire de_o
);
wire normalVsync, normalHsync;
syncPolDecter hdect (
.pxlClk(pxlClk),
.rst(rst),
.sync(hsy... | 7.346458 |
module SyncCounter (
CountEn,
clock,
Q
);
input CountEn, clock;
output [3:0] Q;
wire w0, w1, w2;
JK_Flip_Flop jk1 (
CountEn,
CountEn,
clock,
Q[0]
);
and gate1 (w0, CountEn, Q[0]);
JK_Flip_Flop jk2 (
w0,
w0,
clock,
Q[1]
);
and gate2 (w1, w0, Q... | 6.712306 |
module syncdivider (
input CLK,
input sync_in, // Input sync signal, should stay up exactly one cycle.
output sync_out, // Divided output sync signal, will stay up exactly one cycle.
input pb_divby, // Preferably debounced, staying up exactly one FPGA-cycle.
input pb_offset, // As well.
outp... | 7.672204 |
module will simulate the operation of a 4 bit synchronous down counter.
module syncDownCounter(clk, rst, out);
input clk;
input rst;
output [3:0] out;
wire [3:0] d;
// assign each bit of wire to logical operations with outputs.
assign d[0] = ~out[0];
assign d[1] = out[1] ~^ out[0];
assign d[2] = out[2] ~^ (out... | 7.492578 |
module syncDownCounter_gl (
clk,
rst,
out
);
input clk, rst;
wire [3:0] d;
output [3:0] out;
wire orOut1, orOut2;
not firstBit (d[0], out[0]);
xnor secondBit (d[1], out[1], out[0]);
or orOne (orOut1, out[1], out[0]);
xnor thirdBit (d[2], out[2], orOut1);
or orTwo (orOut2, out[2], out[1], ... | 6.929131 |
module syncDownCounter_gl_tb ();
wire clk, rst;
wire [3:0] out;
syncDownCounter_gl syncDownCounter_gl (
.clk,
.rst,
.out
);
syncDownCounter_gl_tester tester (
.out,
.clk,
.rst
);
initial begin
$dumpfile("syncDownCounter_gl_tb.vcd");
$dumpvars;
end
endmodule... | 6.929131 |
module syncDownCounter_gl_tester (
out,
clk,
rst
);
input [3:0] out;
output clk, rst;
reg clk, rst;
parameter CLOCK_PERIOD = 2;
initial begin
clk = 1;
forever #(CLOCK_PERIOD / 2) clk = ~clk;
end
initial begin
$display("\t\t rst \t clk \t bit");
$monitor("\t\t %b \t %b \t %b %... | 6.929131 |
module syncDownCounter_tb ();
wire clk, rst;
wire [3:0] out;
syncDownCounter sd_counter (
.clk,
.rst,
.out
);
sd_counter_tester tester (
.out,
.clk,
.rst
);
initial begin
$dumpfile("syncDownCounter_tb.vcd");
$dumpvars;
end
endmodule
| 6.929131 |
module sd_counter_tester (
rst,
clk,
out
);
output reg rst, clk;
input [3:0] out;
parameter CLOCK_PERIOD = 2; //gtkwave simulates in seconds
initial begin
clk = 0;
forever #(CLOCK_PERIOD / 2) clk = ~clk;
end
initial begin
$display("\t\t rst \t clk \t out");
$monitor("\t\t %b \t... | 7.194704 |
module SYNCEDGE (
I,
O,
CLK,
PIPE
);
//% Number of clock edges required before output is true when condition met.
parameter LATENCY = 1;
//% Edge detector type - "RISING" or "FALLING".
parameter EDGE = "RISING";
//% Output signal "true" polarity - "POSITIVE" or "NEGATIVE"
parameter POLARITY ... | 7.812723 |
module based on SYNCEDGE. Rising edge detector.
//% @gensymbol
//% MODULE SYNCEDGE_R
//% LPORT I input
//% LPORT CLK input
//% RPORT O output
//% @endgensymbol
module SYNCEDGE_R(
I,
O,
CLK
);
input I;
output O;
input CLK;
SYNCEDGE #(.EDGE("RISING"),.POLARITY("POSITIVE"),.LATENCY(1),.CLKED... | 6.941394 |
module SyncEventCounterV1 (
input clk,
input event_trigger,
input reset,
output reg [31:0] events_counted,
// Note this next parameter is new and is not in the original implementation
// from the earlier Chapter 5 project.
output reg data_ready = 0
);
// ----- Begin copy of Language Templ... | 7.219404 |
module syncff (
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff syncFF (
.CLK(CLK),
.D (IN_ASYNC),
.Q (wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D (wSyncFFQ),
.Q (OUT_SYNC)
);
endmodule
| 7.613166 |
module testSyncFIFO() ;
parameter dsize = 8;
parameter fifodepth = 32;
parameter fifoidx = 5;
wire sCLK, dCLK, dRST ;
wire sENQ, dDEQ;
wire sFULL_N, dEMPTY_N ;
wire [dsize -1:0] sDIN, dDOUT ;
reg [dsize -1:0] sCNT, dCNT ;
reg sRST, sCLR ;
ClockGen#(15,14,10) sc( sCLK )... | 7.223533 |
module testSyncFIFO0() ;
parameter fifodepth = 32;
parameter fifoidx = 5;
wire sCLK, dCLK, dRST ;
wire sENQ, dDEQ;
wire sFULL_N, dEMPTY_N ;
reg sRST, sCLR ;
ClockGen#(15,14,10) sc( sCLK );
ClockGen#(11,12,2600) dc( dCLK );
initial
begin
sCLR = 1'b0 ;
... | 6.561957 |
module SyncFIFO1(
sCLK,
sRST,
dCLK,
sENQ,
sD_IN,
sFULL_N,
dDEQ,
dD_OUT,
dEMPTY_N
) ;
parameter dataWidth = 1 ;
// input clock ... | 6.548293 |
module testSyncFIFOLevel() ;
parameter dsize = 8;
parameter fifodepth = 32;
parameter fifoidx = 5;
wire sCLK, dCLK, dRST ;
wire sENQ, dDEQ;
wire sFULL_N, dEMPTY_N ;
wire [dsize -1:0] sDIN, dDOUT ;
reg [dsize -1:0] sCNT, dCNT ;
reg sRST ;
wire [fifoidx:0] dItemCnt, sItem... | 7.415524 |
module testSyncFIFOLevel ();
parameter dsize = 8;
parameter fifodepth = 32;
parameter fifoidx = 5;
wire sCLK, dCLK, dRST;
wire sENQ, dDEQ;
wire sFULL_N, dEMPTY_N;
reg sRST;
wire [fifoidx:0] dItemCnt, sItemCnt;
wire sCLR_RDY;
wire dCLR_RDY;
wire sCLR;
wire dCLR;
r... | 7.415524 |
module syncfifo_512x32 (
clk,
din,
rd_en,
srst,
wr_en,
dout,
empty,
full
);
input clk;
input [31 : 0] din;
input rd_en;
input srst;
input wr_en;
output [31 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOC... | 6.970954 |
module syncfifo_512x32 (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q
);
input clock;
input [31:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [31:0] q;
endmodule
| 6.970954 |
module syncfifo_512x36 (
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full
);
input clk;
input [35 : 0] din;
input rd_en;
input rst;
input wr_en;
output [35 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(... | 6.970954 |
module syncfifo_512x36_fallthrough (
clk,
din,
rd_en,
rst,
wr_en,
almost_full,
dout,
empty,
full
);
input clk;
input [35 : 0] din;
input rd_en;
input rst;
input wr_en;
output almost_full;
output [35 : 0] dout;
output empty;
output full;
// synthesis translate_o... | 6.970954 |
module syncfifo_512x72 (
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full
);
input clk;
input [71 : 0] din;
input rd_en;
input rst;
input wr_en;
output [71 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_2 #(
.C_COMMON_CLOCK(... | 6.970954 |
module SyncFIFO_RTL #(
parameter width = 32,
parameter depth = 16,
parameter depth_LOG = 4,
parameter FWFT = 1 //1:First Word Fall Through,0:Standard
) (
input wire clk_i,
input wire rst_i,
input wire read_i,
input wire write_i,
output reg full_o,
output reg ... | 8.203937 |
module syncfifo_showahead_aclr_w35d4 (
input wire [34:0] data, // fifo_input.datain
input wire wrreq, // .wrreq
input wire rdreq, // .rdreq
input wire clock, // .clk
input wire aclr, // .aclr
output wire [34:0] ... | 6.738914 |
module syncfifo_showahead_aclr_w35d4_fifo_191_vo6tksa (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [34:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [34:0] q;
output [1:0] usedw;
wire sub_wire0... | 6.738914 |
module syncfifo_showahead_aclr_w64d256 (
input wire [63:0] data, // fifo_input.datain
input wire wrreq, // .wrreq
input wire rdreq, // .rdreq
input wire clock, // .clk
input wire aclr, // .aclr
output wire [63:0... | 6.738914 |
module syncfifo_showahead_aclr_w64d256_fifo_191_uadsfsq (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [63:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [63:0] q;
output [7:0] usedw;
wire sub_wir... | 6.738914 |
module syncfifo_showahead_aclr_w71d32 (
input wire [70:0] data, // fifo_input.datain
input wire wrreq, // .wrreq
input wire rdreq, // .rdreq
input wire clock, // .clk
input wire aclr, // .aclr
output wire [70:0]... | 6.738914 |
module syncfifo_showahead_aclr_w71d32_fifo_191_wojwlyy (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [70:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [70:0] q;
output [4:0] usedw;
wire sub_wire... | 6.738914 |
module syncfifo_showahead_aclr_w9d256 (
input wire [8:0] data, // fifo_input.datain
input wire wrreq, // .wrreq
input wire rdreq, // .rdreq
input wire clock, // .clk
input wire aclr, // .aclr
output wire [8:0] q, ... | 6.738914 |
module syncfifo_showahead_aclr_w9d256_fifo_191_53aeptq (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [8:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [8:0] q;
output [7:0] usedw;
wire sub_wire0;... | 6.738914 |
module SyncFIFO_tb;
// Parameters
localparam Depth = 8;
localparam WordWidth = 32;
// Ports
reg push_i = 0;
reg [WordWidth-1:0] push_payload_i;
reg pop_i = 0;
wire [WordWidth-1:0] pop_payload_o;
wire full_o;
wire empty_o;
reg flush_i = 0;
reg clk = 0;
reg rstn = 0;
bit [WordWidth-1:0] gol... | 6.503114 |
module syncfifo_w9d128_aclr_showahead (
input wire [8:0] data, // fifo_input.datain
input wire wrreq, // .wrreq
input wire rdreq, // .rdreq
input wire clock, // .clk
input wire aclr, // .aclr
output wire [8:0] q, ... | 6.585977 |
module syncfifo_w9d128_aclr_showahead_fifo_191_sqyurki (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input aclr;
input clock;
input [8:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [8:0] q;
output [6:0] usedw;
wire sub_wire0;... | 6.585977 |
module SyncGen ( /*AUTOARG*/
// Outputs
vs,
hs,
x,
y,
border,
// Inputs
fbclk,
rst_b
);
input fbclk;
input rst_b;
output reg vs, hs;
output reg [11:0] x, y;
output reg border;
parameter XRES = 640;
parameter XFPORCH = 24;
parameter XSYNC = 40;
parameter XBPORCH =... | 7.245209 |
module syncGen_time_to_sync_rom (
addr0,
ce0,
q0,
clk
);
parameter DWIDTH = 11;
parameter AWIDTH = 6;
parameter MEM_SIZE = 42;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial beg... | 7.084799 |
module syncGen_time_to_sync (
reset,
clk,
address0,
ce0,
q0
);
parameter DataWidth = 32'd11;
parameter AddressRange = 32'd42;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
syncGen_time_to_syn... | 7.084799 |
module SyncHandshake(
sCLK,
sRST,
dCLK,
sEN,
sRDY,
dPulse
);
parameter init = 1'b0;
// Source clock port signal
input sCLK ;
input sRST ;
input s... | 7.226902 |
module synchroniser #(
parameter width = 1,
parameter depth = 2,
parameter init_high = 0
) (
input clk,
input [width-1:0] signal,
output [width-1:0] sync_signal
);
reg [width-1:0] sync[depth-1:0];
assign sync_signal = sync[depth-1];
integer i;
initial begin
for (i = 0; i < depth; ... | 7.631043 |
module for ADC and LA sourses
******************************************************************************
**/
/* Internal includes */
`include "ADC_TRIG.v"
`include "LA_TRIG.v"
module Synchronization
(
input [7:0] SYNC_DATA_IN,
input [7:0] Delay,
input [7:0] Trg_Lv_UP,
input [7:0] Trg_Lv_DOWN,
input [7:0]... | 6.64064 |
module is for synchronization of signals between 200M( System workspace)clk domain and
// 83M(flash controller moduler) clk domain.
// Method: Adding two FFs betwwn the two specified clk domains to mitigate the damage cased by metastability.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File C... | 7.12845 |
module synchronizer (
input wire clk,
input wire [10:0] cnt_h,
input wire [ 9:0] cnt_v,
output reg sync_h,
output reg sync_v,
output reg disp_en
);
reg h_disp_band;
reg v_disp_band;
reg h_sync_band;
reg v_sync_band;
always @(posedge clk) begin
ca... | 6.883367 |
module SynchronizerShiftReg_w1_d3 ( // @[:freechips.rocketchip.system.TinyConfig.fir@115270.2]
input clock, // @[:freechips.rocketchip.system.TinyConfig.fir@115271.4]
input io_d, // @[:freechips.rocketchip.system.TinyConfig.fir@115273.4]
output io_q // @[:freechips.rocketchip.system.TinyConfig.fir@... | 6.820992 |
module SynchronizerShiftReg_w2_d3 (
input clock,
input [1:0] io_d,
output [1:0] io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
wire output_chain_1_clock; // @[ShiftReg.scala... | 6.820992 |
module synchronizer (
input clk, // Clock
input async_in, // input signal
output reg Q // output after synchronization
);
reg connect = 1'b0; //to implement double flip flop
always @(posedge clk) begin
connect <= async_in;
Q <= connect;
end
endmodule
| 6.883367 |
module changes signals from one domain to another, when the signals
// have no relation to each other. For signals that are vectors, use the
// synchronizer_vector module instead.
//
// This module has variable width to synchronize several signals using
// one instantiation of the module. Uses a simple double regist... | 7.072679 |
module Synchronizer_tb #(
parameter NUM_STAGES = 2,
BUS_WIDTH = 1
) ();
reg [BUS_WIDTH-1:0] ASYNC_tb;
reg CLK_tb;
reg RST_tb;
wire [BUS_WIDTH-1:0] SYNC_tb;
parameter Clock_Period = 10;
integer i;
always #(Clock_Period / 2) CLK_tb = ~CLK_tb;
initial begin
$dumpfile("Synchronizer.vcd");
... | 6.568034 |
module asynchronus_ram #(
parameter ADDR_WDITH = 8,
DATA_WDITH = 1
) (
clk,
we,
addr,
din,
dout
);
input wire clk, we;
input wire [ADDR_WDITH-1:0] addr;
input wire [DATA_WDITH-1:0] din;
output wire [DATA_WDITH-1:0] dout;
reg [DATA_WDITH-1:0] ram[2*ADDR_WDITH-1:0];
reg [ADDR_WDI... | 7.327964 |
module SynchronousROMModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire Clock,
input wire Reset,
input wire [7:0] Addr1,
input wire [7:0] Addr2,
input wire [7:0] REAddr,
input wire RE,
output wire [7:0] Data1,
output wire [7:0] Data2,
output wire [7:0] RE... | 7.353306 |
module Synchronous_FIFO #(
parameter A_WIDTH = 8,
parameter D_WIDTH = 48
) (
input i_clk, // single clock domain
input i_rst_n, // active low reset
input i_wr_en, // write enable signal
input i_rd_en, // read enable signal
input [D_WIDTH-1:0] i_data, // data input //
out... | 8.091587 |
module synchronous_two_input_multiplexer #(
parameter WIDTH = 16
) (
input clk,
input select,
input [WIDTH-1:0] in0,
input [WIDTH-1:0] in1,
output reg [WIDTH-1:0] out
);
always @(posedge clk)
case (select)
1'b0: out = in0;
1'b1: out ... | 7.068496 |
module synchro_ram (
clk,
datain,
addr,
read,
write,
dataout
);
input clk;
input [3:0] addr;
input read;
input write;
input [3:0] datain;
output [3:0] dataout;
//While asynchronous read,please comment it.
reg [3:0] dataout;
//Memory 4 bits,16 words.
reg [3:0] memory [0:15]... | 7.148942 |
module rw_seperate_ram_tb ();
reg [3:0] t_datain;
reg [3:0] t_addr;
reg t_read;
reg t_write;
wire [3:0] t_dataout;
rw_seperate_ram dut (
.datain (t_datain),
.addr (t_addr),
.read (t_read),
.write (t_write),
.dataout(t_dataout)
);
//Generates the read... | 6.780476 |
module SYNCH_FIFO #(
parameter data_width = 25,
parameter addr_width = 8,
parameter depth = 61
) (
/// Control signal
input clk,
input rd_en,
input wr_en,
input rst_n,
/// status signal
output empty,
output full,
/// data signal
output reg [data_width-1:0] data_o... | 8.231823 |
module Synch_out (
input clk,
rst,
input [31:0] dat_in,
input cyc_i,
input stb_i,
output ack_o,
output reg time_syn_run,
input time_syn_done,
output reg [31:0] dat_out,
output reg cyc_o,
stb_o,
... | 6.593513 |
module synch_ram #(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire write_en,
input wire [ADDR_WIDTH-1:0] addr,
input wire [DATA_WIDTH-1:0] data_in,
output wire [DATA_WIDTH-1:0] data_out
);
reg [DATA_WIDTH-1:0] ram[2*... | 8.110761 |
module synch_reg #(
parameter wbits = 128
) (
input clock,
input resetn,
input wen,
input ren,
input [wbits-1:0] wdata,
output [wbits-1:0] rdata,
output reg full,
output empty
);
reg [wbits-1:0] mem;
always @(posedge clock) begin
if (!resetn) begin
full <= 1'b0;
... | 7.918275 |
module syncInput (
input clk,
input btn,
output reg syncBtn = 0
);
reg b1;
reg b2;
always @(posedge clk) begin
b1 <= btn;
b2 <= b1;
if (b1 && !b2) begin
syncBtn <= 1;
end
if (!b1 && b2) begin
syncBtn <= 0;
end
end
endmodule
| 6.850704 |
module is the behavioral level model of the counter.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
module syncJohn(out, clk, rst);
output reg [3:0] out; // present state output
input clk, rst;
// DFF
always @(posedge clk)
if (!rst)
out <= 4'b0000;
else b... | 7.595207 |
module is intended for use with GTKwave on the PC.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
`include "syncJohn.v"
module syncJohnGTK;
// connect the two modules
wire [3:0] outBench;
wire clkBench, rstBench;
// declare an instance of the syncJohn module
s... | 9.106975 |
module is intended for use with the DE1_SoC and Spinal Tap.
// Written by Jack Gentsch, Jacky Wang, and Chinh Bui
// 4/3/2016 instructed by Professor Peckol
module syncJohnTop (LEDR, CLOCK_50, SW);
output [3:0] LEDR;
input CLOCK_50;
input [9:0] SW;
wire [31:0] clk; // choosing from 32 different clock speeds
... | 9.106975 |
module clock_divider (
clock,
divided_clocks
);
input clock;
output [31:0] divided_clocks;
reg [31:0] divided_clocks;
initial divided_clocks = 0;
always @(posedge clock) divided_clocks = divided_clocks + 1;
endmodule
| 6.818038 |
module synCordicAtan (clk, rst, en, x, y, atanOut); // {
22 //省略了非关键性代码，完整内容请参考电子附件
23 assign negzo = -zo;
24 assign tmpx = -x;
25 assign tmpy = -y;//调用Cordic流水实现，由多个旋转模块串接组合而成
28 CordicSeq cs (.clk(clk),.rst(rst), .en(en), .xi(xi), .yi(yi), .zi(zi), .xo(xo),.yo(yo),.zo(zo));
39 always @( posedge clk)
40 be... | 6.664238 |
module synCordicSinCos (clk, rst, en, inp, sinout, cosout); // {
18 parameter signed [29:0] xif=128'b0010_0110_1101_1101_0011_1011_0110_10;
23 parameter signed [bitWidth-1:0] xi = xif[29:30-bitWidth];//正弦比例k值
24 parameter signed [bitWidth-1:0] yi = 0;
25 wire signed [angBitWidth-2:0] zo;
27
28 assign argi = in... | 7.518259 |
module syncout (
rst,
clk32,
clk_i,
clk_d2,
datain,
Bit_Sync,
dataout
);
input rst; //复位信号，高电平有效
input clk32; //FPGA系统时钟:32MHz
input clk_d2;
input clk_i;
input [5:0] datain;
output Bit_Sync;
output [5:0] dataout;
//检测分频器输出的同相支路信号，上升沿产生位同步脉冲
reg clki, sync;
always @(... | 6.982085 |
module SyncPulse(
sCLK,
sRST,
dCLK,
sEN,
dPulse
);
// source clock ports
input sCLK ;
input sRST ;
input sEN ;
// destination clock ports
input dCLK ;
output dPulse ;
... | 6.967198 |
module syncPulses (
clk9MHz,
hSync,
vSync,
hData,
vData,
clk3Hz,
disp,
vgaCount,
lineCount,
start
);
input clk9MHz;
integer vcount, hzcount;
output reg [9:0] vgaCount;
output reg [8:0] lineCount;
reg hData, vData; // horizontal data enable, vertical data enable
int... | 7.057983 |
module syncRAM (
clk,
resetn,
dataIn,
Addr,
CS,
RD,
dataOut
);
// parameters for the width
parameter ADDR = 8;
parameter DATA = 8;
parameter DEPTH = 8;
//ports
input clk;
input resetn;
input [ADDR-1:0] Addr;
input [DATA-1:0] dataIn;
input CS, RD;
output reg [DAT... | 8.718308 |
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