code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module sync_regs_m2 #(
parameter WIDTH = 32,
parameter DEPTH = 2 // minimum of 2
) (
input clk,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [WIDTH-1:0]
din_meta = 0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_multicycle_pa... | 6.766461 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module sync_reset_stretch #(
parameter CYCLES = 2 // clock cycles by which pulse needs to be streched
) (
input clk_i,
input rst_n_i,
input data_i,
output reg data_o
);
//--------------------------------------------------------------------------------
// Pulse stretching logic
... | 7.925087 |
module sync_reset_tb ();
reg rst_n_i;
reg clk_i;
reg data_i;
wire data_o;
sync_reset dut (
.clk_i (clk_i),
.rst_n_i(rst_n_i),
.data_i (data_i),
.data_o (data_o)
);
initial begin
clk_i = 1'b0;
forever #5 clk_i = ~clk_i;
end
initial begin
rst_n_i = 1'b0;
d... | 7.351688 |
module sync_sig (
input clk,
input rst_n,
input in_sig,
output reg out_sig
);
parameter SHIFT_WIDTH = 2;
reg [SHIFT_WIDTH-1:0] sig_dly;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
sig_dly <= {SHIFT_WIDTH{1'b0}};
end else begin //Sync signal
sig_dly[0] <= i... | 7.187767 |
module sync_signal #(
parameter WIDTH = 1, // width of the input and output signals
parameter N = 2 // depth of synchronizer
) (
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in th... | 8.633074 |
module sync_sp_ram #(
// Parameters
parameter ADDR_WIDTH = 8, // address's width
parameter DATA_WIDTH = 8 // data's width
) (
input clk, // system clock
input cen, // chip select, low active
input wen, // write enable, low active
input [ADDR_WIDTH-1:0] a, // address
input ... | 7.34309 |
modules for general use
// Description : Clock crossing support for Slave
// This contains support for cross-clock-domain (CDC) synchronization
// of type 2-phase and other, covering pulses and levels. Used for
// SCL to (system) CLK and CLK to SCL. Used for single nets, handshakes,
// FIFOs, etc.
//... | 9.122374 |
module SYNC_2PH_LVL_S2C_STATE (
input rst_n,
input scl,
input clk,
input trig_scl, // trigger level from SCL domain
output out_clk, // output state in CLK domain
input clear_clk // input clear from CLK domain
);
reg clk_state;
reg clk_ack;
// see SYNC_2PH_S2C_STATE for details. ... | 7.703339 |
module SYNC_Pulse_S2C (
input SCL,
input CLK,
input RSTn,
input local_set,
output o_pulse
);
// 4 phase handshake, but pulse out
reg svalue, cvalue, cpulse;
always @(posedge SCL or negedge RSTn)
if (!RSTn) svalue <= 1'b0;
else if (local_set) svalue <= 1'b1;
else if (cvalue) /... | 6.541296 |
module SYNC_ASet_Seq2 (
input CLK,
input RSTn,
input async_set,
input local_clear,
output o_pulse
);
reg value, seq;
always @(posedge CLK or negedge RSTn)
if (!RSTn) value <= 1'b0;
else if (async_set) // CDC
value <= 1'b1;
else if (local_clear) value <= 1'b0;
always @(p... | 6.607617 |
module SYNC_AClr_Seq2 (
input CLK,
input RSTn,
input local_set,
input async_clear,
output o_pulse
);
reg value, seq;
always @(posedge CLK or negedge RSTn)
if (!RSTn) value <= 1'b0;
else if (local_set) value <= 1'b1;
else if (async_clear) // CDC
value <= 1'b0;
always @(p... | 6.659348 |
module SYNC_S2C #(
parameter WIDTH = 1
) (
input rst_n,
input clk,
input [WIDTH-1:0] scl_data,
output [WIDTH-1:0] out_clk // output copy in CLK domain
);
reg [WIDTH-1:0] clk_copy;
assign out_clk = clk_copy;
// note: could use clk_copy^scl_data as test to allow ... | 8.207379 |
module SYNC_C2S #(
parameter WIDTH = 1
) (
input rst_n,
input scl, // could be SCL_n as well
input [WIDTH-1:0] clk_data,
output [WIDTH-1:0] out_scl // output copy in CLK domain
);
reg [WIDTH-1:0] scl_copy;
assign out_scl = scl_copy;
// note: could use clk... | 8.248687 |
module SYNC_AClr_C2S (
input CLK, // system domain
input RSTn,
input local_set,
input async_clear,
output o_value
);
reg value; // CLK domain
always @(posedge CLK or negedge RSTn)
if (!RSTn) value <= 1'b0;
else if (local_set) value <= 1'b1;
else if (async_clear) // CDC
valu... | 6.822945 |
module tb_dff ();
reg D, clk, reset;
wire Q;
integer i;
dff dut (
D,
clk,
reset,
Q
);
initial
//begin
clk = 0;
always #100 clk = ~clk;
//end
initial begin
$dumpfile("sync_DFF.vcd");
$dumpvars;
$monitor("Clock=%d, D=%d, Q=%d", clk, D, Q);
D <= ... | 6.88469 |
module will take incoming horizontal and veritcal sync pulses and
// create Row and Column counters based on these syncs.
// It will align the Row/Col counters to the output Sync pulses.
// Useful for any module that needs to keep track of which Row/Col position we
// are on in the middle of a frame
module Sync_To_Coun... | 7.054311 |
module sync_up_counter (
input clk_i, // Clock
input rst_i, // Reset
output [3:0] count_o // Count Value
);
wire [3:0] d;
wire [3:0] q;
wire [3:0] q_n;
assign d[0] = q_n[0];
assign d[1] = (q_n[1] & q[0]) | (q[1] & q_n[0]);
assign d[2] = (q[2] & q_n[1]) | (q[2] & q_n[0]) | (q... | 6.737946 |
module dff (
input clk_i,
input rst_i,
input d_i,
output reg q_o,
output q_n_o
);
assign q_n_o = ~q_o;
always @(posedge clk_i) begin
if (rst_i) begin
q_o <= 1'b0;
end else begin
q_o <= d_i;
end
end
endmodule
| 7.174483 |
module sync_vg # (
parameter X_BITS=12,
parameter Y_BITS=12,
//MODE_720p
parameter V_TOTAL = 12'd750,
parameter V_FP = 12'd5,
parameter V_BP = 12'd20,
parameter V_SYNC = 12'd5,
parameter V_ACT = 12'd720,
parameter H_TOTAL = 12'd1650,
parameter H_FP = ... | 8.440742 |
module sync_vg
#(
parameter X_BITS=12,
parameter Y_BITS=12
)
(
input wire clk,
input wire reset,
input wire interlaced,
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wire [Y_BITS-1:0]
input wi... | 7.274187 |
module cde_sync_with_reset #(
parameter DEPTH = 2,
RST_VAL = 1'b0,
WIDTH = 1
) (
input wire clk,
input wire reset_n,
input wire [WIDTH-1 : 0] data_in,
output wire [WIDTH-1 : 0] data_out
);
reg [WIDTH - 1:0] sync_data[DEPTH:0];
always @(*) begin
sync_dat... | 7.756212 |
modules provides an an interface to
// instantiate the synchronizer block in VHDL.
//
`default_nettype none
module sync_wrapper #(
parameter WIDTH = 1,
parameter STAGES = 2,
parameter INITIAL_VAL = 0,
parameter FALSE_PATH_TO_IN = 1
)(
input wire clk,
input w... | 8.032052 |
module synDff (
D,
clr_n,
clk,
Q
);
input D;
input clr_n;
input clk;
output reg Q;
always @(posedge clk) begin
if (!clr_n) begin
Q <= 0;
end else Q <= D;
end
endmodule
| 6.572321 |
module SynFIFO (
clk,
rst_n,
rdata,
wfull,
rempty,
wdata,
winc,
rinc
);
parameter DSIZE = 32;
parameter ASIZE = 9;
parameter MEMDEPTH = 1 << ASIZE;
parameter RAM_TYPE = "block"; // Type of RAM: string; "auto", "block", or "distributed";
output reg [DSIZE-1:0] rdata;
output... | 7.205019 |
module fulladdersync (
a,
b,
phi,
y,
c_out
);
input a, b, phi;
output c_out, y;
wire cin1;
dynamicFF m1 (
c_out,
phi,
cin1
);
fulladder1 m2 (
a,
b,
cin1,
y,
c_out
);
endmodule
| 6.930859 |
module SYNinterrupt (
input clk,
input rst,
input INT,
output SYN_INT
);
reg SYNINT;
always @(posedge clk or posedge rst or posedge INT) begin
if (rst) SYNINT <= 1'b0;
else begin
if (INT) SYNINT <= 1'b1;
else SYNINT <= INT;
end
end
assign SYN_INT = SYNINT;
endmodule
| 7.077049 |
module synAddSub (
in1,
in2,
outp
);
parameter inp1_width = 16;
parameter inp2_width = 16;
parameter out_width = 16;
parameter opr = "add";
parameter dataType = "signed"; // for unsigned, use datatype = ""
input [inp1_width-1:0] in1;
input [inp2_width-1:0] in2;
output [out_width-1:0] outp;
... | 6.919617 |
module synMult (
in1,
in2,
outp
);
parameter inp1_width = 16;
parameter inp2_width = 16;
parameter out_width = 32;
parameter dataType = "signed";
input [inp1_width-1:0] in1;
input [inp2_width-1:0] in2;
output [out_width-1:0] outp;
wire signed [inp1_width-1:0] in1S;
wire signed [inp2_width... | 6.86167 |
module synBusAdapter (
inp,
outp
);
parameter inp_width = 16;
parameter out_width = 16;
parameter datatype = "signed";
parameter preshift = 0; // negative values denote left shift
// Arguments to sat logic
parameter infrac = 0;
parameter outfrac = 0;
parameter round = 0;
parameter sat = 0;
... | 7.549782 |
module synBusAdapter_sat (
inp,
outp,
outsp
);
parameter inp_width = 16;
parameter out_width = 16;
parameter datatype = "signed";
parameter preshift = 0; // negative values denote left shift
// Arguments to sat logic
parameter infrac = 0;
parameter outfrac = 0;
parameter round = 0;
parame... | 7.549782 |
module synGain (
inp,
outp
);
parameter inp_width = 16;
parameter out_width = 16;
parameter coef_width = 2;
parameter coefVal = 128'b1;
parameter dataType = "signed";
input [inp_width-1:0] inp;
output [out_width-1:0] outp;
wire signed [ inp_width-1:0] inpS;
wire signed [ co... | 7.616726 |
module singleDelayWithEnableGeneric (
clk,
grst,
rst,
en,
inp,
outp
);
parameter bitwidth = 16;
input clk, grst, rst, en;
input [bitwidth-1:0] inp;
output [bitwidth-1:0] outp;
reg [bitwidth-1:0] outreg;
always @(`proclineg) begin
if (grst == `activehigh) outreg <= {bitwidth{1'b0... | 6.583835 |
module synDelayWithEnable (
clk,
grst,
rst,
en,
inp,
outp
);
parameter preferRAMImpl = 1;
parameter bitwidth = 16;
parameter delaylength = 100;
input clk, grst, rst, en;
input [bitwidth-1:0] inp;
output [bitwidth-1:0] outp;
generate
begin : GenBlock
if (delaylength == ... | 6.727391 |
module synMux (
sel,
inp,
outp
);
parameter inp_width = 2;
parameter inp_size = 3;
parameter sel_bits = 2;
input [sel_bits-1:0] sel;
input [inp_width*inp_size-1:0] inp;
reg [inp_width-1:0] inpBuf[0:inp_size-1];
reg [inp_width-1:0] tmp;
output reg [inp_width-1:0] outp;
integer i, j;
alw... | 6.920522 |
module synCounter (
clk,
en,
grst,
rst,
up,
ld,
din,
cnt,
rdy
);
parameter en_exists = 1;
parameter rst_exists = 1;
parameter ld_exists = 0;
parameter rdy_exists = 0;
parameter ctype = 2;
parameter ival = 0;
parameter signed ivalS = ival;
parameter ivalU = ival;
par... | 7.088457 |
module synCounterSync (
clk,
en,
grst,
rdy
);
parameter tval = 127;
parameter bitwidth = 16;
parameter sample_offset = 0;
localparam resetVal = sample_offset != 0 ? 1'b0 : 1'b1;
input clk, en, grst;
output rdy;
reg [bitwidth-1:0] cntU;
reg rdyR;
generate
begin : C... | 6.739524 |
module synCounterFR (
clk,
en,
grst,
rst,
up,
ld,
din,
cnt
);
parameter en_exists = 1;
parameter rst_exists = 1;
parameter ld_exists = 0;
parameter ctype = 2;
parameter ival = 0;
parameter signed ivalS = ival;
parameter ivalU = ival; //$unsigned(ival);
parameter tval = 1... | 7.100612 |
module synRegister (
clk,
D,
en,
rst,
outp
);
parameter bitwidth = 16;
input clk;
input [bitwidth-1:0] D;
input en;
input rst;
output [bitwidth-1:0] outp;
// NOTE: VHDL initializes this to zero.
reg [bitwidth-1:0] outp;
//regproc: process(clk)
always @(`procline) begin
if (r... | 7.000795 |
module synStepFunction (
clk,
en,
grst,
rst,
outp
);
parameter bitwidth = 16;
parameter delaylength = 32;
parameter stepvalue = 1;
parameter cntWidth = `log_floor(delaylength);
parameter resetType = `grsttype;
input clk, en, grst, rst;
output [bitwidth-1:0] outp;
reg [cntWidth-1:0... | 7.331865 |
module synAbs (
inp,
outp
);
parameter bitwidth = 16;
input [bitwidth-1:0] inp;
output reg [bitwidth-1:0] outp;
always @(inp) begin
if ($signed(inp) < 0) outp <= -$signed(inp);
else outp <= inp;
end
endmodule
| 7.552306 |
module synBinLogic (
inpA,
inpB,
outp
);
parameter bitwidth = 16;
parameter opr = "ANDD";
input [bitwidth-1:0] inpA;
input [bitwidth-1:0] inpB;
output [bitwidth-1:0] outp;
reg [bitwidth-1:0] outp;
always @(*)
case (opr)
"ANDD": outp = inpA & inpB;
"ORRR": outp = inpA | inpB;
... | 7.51569 |
module synComparator (
inpA,
inpB,
outp
);
parameter bitwidth = 16;
parameter datatype = "signed";
parameter opr = "equ";
input [bitwidth-1:0] inpA;
input [bitwidth-1:0] inpB;
output outp;
reg outp;
wire signed [bitwidth-1:0] AS;
wire signed [bitwidth-1:0] BS;
wire... | 7.482897 |
module synInverter (
inp,
outp
);
parameter bitwidth = 16;
input [bitwidth-1:0] inp;
output [bitwidth-1:0] outp;
assign outp = ~inp;
endmodule
| 7.159415 |
module synNegate (
inp,
outp
);
parameter bitwidth = 16;
input [bitwidth-1:0] inp;
output [bitwidth-1:0] outp;
assign outp = $signed(-(inp));
endmodule
| 6.820187 |
module synFIFO (
clk,
din,
en,
we,
re,
grst,
rst,
dout,
full,
empty,
itemcnt
);
parameter bitwidth = 16;
parameter depth = 16;
parameter cntwidth = 5;
parameter adrWidth = 4;
parameter isFwftMode = 0;
input clk;
input [bitwidth-1:0] din;
input en;
input we;... | 6.555056 |
module synFIFO_MC (
clk,
st,
din,
we,
re,
grst,
rst,
dout,
full,
empty,
itemcnt
);
parameter ch_no = 2;
parameter st_width = 1;
parameter bitwidth = 16;
parameter depth = 16;
parameter cntwidth = 5;
parameter adrWidth = 4;
parameter isFwftMode = 0;
input clk,... | 6.772367 |
module synDownsampleSimple (
clk,
en,
grst,
inp,
outp
);
parameter bitwidth = 16;
input clk, grst, en;
input [bitwidth-1:0] inp;
output [bitwidth-1:0] outp;
reg [bitwidth-1:0] outreg;
wire [bitwidth-1:0] inp_ds;
reg [bitwidth-1:0] outp_ds /* synthesis syn_allow_retiming = 0 */;
a... | 7.63334 |
module SynPC (
input clk,
input rst_n,
input en,
input load_use,
//input halt,
input jp_success,
input [31:0] pc_new,
output [31:0] pc,
pc_4
);
reg [9:0] pc_simp;
wire [9:0] pc_4_simp = pc_simp + 1;
assign pc = {{20{1'b0}}, pc_simp, {2{1'b0}}};
assign pc_4 = {{20{1'b0}},... | 7.278982 |
module SynPiplIntf (
clk,
rst_n,
en,
nop,
data_i,
data_o
);
parameter NBit = 32;
input clk, rst_n, en, nop;
input [NBit - 1:0] data_i;
output reg [NBit - 1:0] data_o;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) data_o <= {NBit{1'b0}};
else if (en) begin
data_o... | 7.587627 |
module SynPS2 (
input clk,
input rst_n,
input en,
input clear,
input [4:0] rd_in,
input regfile_w_en_in,
input r_datamem_in,
input [1:0] bht_state_in,
input is_branch_in,
output reg [4:0] rd,
output reg regfile_w_en,
output reg r_datamem,
output reg [1:0] bht_state,
... | 7.33424 |
module SynPS4 (
input clk,
input rst_n,
input en,
input clear,
input data_in,
input regfile_w_en_in,
input [4:0] regfile_req_w_in,
input r_datamem_in,
output reg data,
output reg regfile_w_en,
output reg [4:0] regfile_req_w,
output reg r_datamem
);
always @(posedge clk,... | 7.150542 |
module synqrst (
input wire clk,
input wire asynq_rst_n,
output wire synq_rst_n
);
reg [2:0] synq = 3'b000;
always @(posedge clk) begin
synq[2] <= synq[1];
synq[1] <= synq[0];
synq[0] <= asynq_rst_n;
end
assign synq_rst_n = synq[2];
endmodule
| 7.446645 |
module synrecounter10 (
input clk,
input reset, //synchronous active-high reset
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'b0000;
else if (q == 4'b1001) q <= 4'b0000;
else q <= q + 1;
end
endmodule
| 7.096496 |
module synrecounter10_tb;
`define synrecounter10_TEST(ID, CLK, RESET, Q)\
clk=CLK;\
reset=RESET;\
if(q==Q)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
wire [3:0] q;
synrecoun... | 7.096496 |
module synrecounter15 (
input wire clk,
input wire reset, //synchronous active-high reset
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'b0000;
else q <= q + 1;
end
endmodule
| 7.096496 |
module synrecounter15_tb;
`define synrecounter15_TEST(ID, CLK, RESET, Q)\
clk=CLK;\
reset=RESET;\
if(q==Q)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
wire [3:0] q;
... | 7.096496 |
module synrefsm1 (
input wire clk,
input wire reset, //synchronous active-high reset
input wire in,
output reg out
);
reg state;
parameter A = 1'b0, B = 1'b1;
always @(posedge clk)
if (reset) begin
state <= B;
out <= 1'b1;
end else if (state == A) begin
if (in == ... | 7.067922 |
module synrefsm1_tb;
`define synrefsm1_TEST(ID, CLK, RESET, IN, OUT)\
clk=CLK;\
reset=RESET;\
in=IN;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg reset;
reg i... | 7.227527 |
module synrefsm2 (
input wire clk,
input wire reset, //synchronous active-high reset
input wire j,
input wire k,
output reg out
);
reg state;
parameter ON = 1'b1, OFF = 1'b0;
always @(posedge clk)
if (reset) begin
state <= OFF;
out <= 1'b0;
end else if (state == OF... | 7.485647 |
module synrefsm2_tb;
`define synrefsm2_TEST(ID, CLK, RESET, J, K, OUT)\
clk=CLK;\
reset=RESET;\
j=J;\
k=K;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg res... | 7.015763 |
module SynRegFile (
clk,
rst_n,
en,
w_en,
req_dbg,
req_w,
req_a,
req_b,
data_w,
data_dbg,
data_a,
data_b
);
input clk;
input rst_n;
input en;
input w_en;
input [4:0] req_dbg;
input [4:0] req_w;
input [4:0] req_a;
input [4:0] req_b;
input [31:0] data_w;
... | 7.308638 |
module synrevem (
input wire clk,
input wire rst, //synchronous active-high reset
input wire [1:0]in,
output reg [1:0]out
);
reg [2:0] cur_state, next_state;
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100;
always @(posedge clk)
if (rst) begin
cur_state <= s... | 8.320534 |
module synrevem_tb;
`define synrevem_TEST(ID, CLK, RST, IN, OUT)\
clk=CLK;\
rst=RST;\
in=IN;\
if(out==OUT)\
$display("Case %d passed!", ID); \
else begin\
$display("Case %d failed!", ID); \
$finish;\
end\
reg clk;
reg rst;
reg [1:0] in;
wi... | 7.009266 |
module SynSyscall (
clk,
rst_n,
en,
syscall_en,
data_v0,
data_a0,
display,
halt
);
input clk;
input rst_n;
input en;
input syscall_en;
input [31:0] data_v0;
input [31:0] data_a0;
output reg [31:0] display;
output halt;
wire enabled = en && syscall_en;
assign halt = (... | 6.629811 |
module SynTestbed (
A,
B,
control,
Out,
flagout,
clk,
reset
);
input [`WIDTH-1:0] A, B;
input [`WCONTROL-1:0] control;
input clk;
input reset;
output [`WIDTH-1:0] Out;
output [`WFLAG-1:0] flagout;
wire [`WFLAG-1:0] flags;
reg [`WFLAG-1:0] flags2;
reg [`WCONTROL-1:0] contr... | 6.553513 |
module flop (
clk,
reset,
d,
q
);
input clk;
input reset;
input [31:0] d;
output [31:0] q;
reg [31:0] state;
always @(posedge clk or posedge reset) begin
if (reset) state <= #1 0;
else state <= #1 d;
end
assign #1 q = state;
endmodule
| 6.813917 |
module.
*HDL depends on other modules.
*It is
* spi_rx.v
* synth_arb.v
* operator.v
* -sine.v
* -diff_rom.v
* -sin_rom.v
* pwm_out.v
* fifo_tx.v(Altera QuartusII Megafunction IP dcfifo)
* pll.v(Altera QuartusII Megafunction IP altpll)
*
*External MicroController can controll module by 3wire-Seri... | 7.207867 |
module synth1_test();
`timescale 1ps / 1ps
reg clk, reset_n, ss_n, sck_r;
wire sdi, sck;
reg [15:0] shift_reg, add_reg;
assign sdi = shift_reg[15];
initial
begin
clk <= 0;
reset_n <= 0;
ss_n <= 0;
sck_r <= 1;
add_reg <= 16'h01AB;
shift_reg <= 1... | 6.946935 |
module adder_N #(
parameter N = 8
) (
input [N-1:0] ina,
inb,
input cin,
output [N-1:0] sum,
output cout
);
assign {cout, sum} = ina + inb + cin;
endmodule
| 7.024611 |
module compare_N #(
parameter N = 8
) (
input [N-1:0] a,
b, // Ƚ
output equal // ȽϽ
);
assign equal = (a == b) ? 1 : 0; //ȽϽ
endmodule
| 7.961439 |
module decoder3_8 (
input [2:0] in,
output [7:0] out
);
assign out = 1'b1 << in; //ݴinֵ,λ1ƶӦλ
endmodule
| 7.729152 |
module mux_N #(
parameter N = 8
) (
input [N-1:0] a,
b,
input sel,
output [N-1:0] out
);
//ʹassignselѡa,b
assign out = sel ? a : b; //selΪ1ʱoutΪaΪb
endmodule
| 6.786136 |
module mux_N2 #(
parameter N = 6
) (
input [N-1:0] a,
b,
input sel,
output reg [N-1:0] out
);
always @(*)
case (sel) //ʹif_elseźselֵ
1'b0: out = a;
1'b0: out = b;
default: out = a;
endcase
endmodule
| 6.757377 |
module tri_Gate #(
parameter N = 6
) (
input [N-1:0] in,
input enable,
output [N-1:0] out
); //ʹassign״̬
assign out = enable ? in : 'bz;
endmodule
| 8.76848 |
module tri_Gate1 #(
parameter N = 6
) (
input [N-1:0] in,
input enable,
output [N-1:0] out
); //bufif1һVerilogżԭ
generate
genvar i;
for (i = 0; i < N; i = i + 1) begin : buf_test
bufif1 mybuf1 (out[i], in[i], enable);
end
endgenerate
endmodule
| 7.045924 |
module bidir #(
parameter N = 6
) (
input [N-1:0] in,
input enable,
inout [N-1:0] tri_inout,
output [N-1:0] out
);
assign tri_inout = enable ? in : 'bz; //̬ŵΪin
assign out = tri_inout; //̬ŵ
endmodule
| 6.687599 |
module DFF_N #(
parameter N = 6
) (
input CLK,
input RESET_N,
input [N-1:0] D,
output reg [N-1:0] Q
);
always @(posedge CLK or negedge RESET_N)
if (!RESET_N) Q <= 'h0;
else Q <= D;
endmodule
| 8.05977 |
module shiftReg_N #(
parameter N = 8
) (
input CLK,
RESET_N,
input din,
output reg [N-1:0] dout
);
always @(posedge CLK)
if (!RESET_N) //
dout <= 'b0;
else begin
dout[N-1:1] <= dout[N-2:0]; //һλ
dout[0] <= din; //źŷĴλ
end
endmodule
| 7.990468 |
module counter_N #(
parameter N = 16
) (
input clk,
input load,
input [N-1:0] data,
output reg [N-1:0] cnt,
output cout // ־
);
always @(posedge clk)
if (load) //źż
cnt <= data;
else cnt <= cnt + 1;
assign cout = &cnt;
endmodule
| 7.94355 |
module counter_N2 #(
parameter N = 16
) (
input clk,
input load,
input [N-1:0] data,
output reg [N-1:0] cnt,
output reg cout // ־
);
reg [N-1:0] preout; // FSMһ״̬ʱΪ
always @(posedge clk) cnt <= preout;
always @(*) begin
{cout, preout} = cnt + 1... | 7.390396 |
module latch_N #(
parameter N = 16
) (
input clk,
input [N-1:0] d,
output [N-1:0] q
);
assign q = clk ? d : q; //ͨassign䣬ʵֵһ
endmodule
| 7.259438 |
module latch_N1 #(
parameter N = 16
) (
input clk,
input [N-1:0] d,
output reg [N-1:0] q
);
always @(*)
if (clk) //clkΪߵƽʱqdֵ
q = d;
endmodule
| 7.449385 |
module adderN #(
parameter N = 8
) (
input clk,
cin,
input [N-1:0] ina,
inb,
output reg [N-1:0] sum,
output reg cout
);
reg [7:0] tempa, tempb;
reg tempc;
always @(posedge clk) begin
tempa = ina;
tempb = inb;
tempc = cin; //
end
always @(posed... | 7.016561 |
module pipeline_adderN #(
parameter N = 8
) (
input clk,
cin,
input [N-1:0] ina,
inb,
output reg [N-1:0] sum,
output reg cout
);
reg [7:0] tempa, tempb;
reg tempci, firstco, secondco, thirdco;
reg [1:0] firsts, thirda, thirdb;
reg [3:0] seconda, secondb, sec... | 6.839437 |
module add_ahead #(
parameter N = 8
) (
input cin,
input [N-1:0] a,
b,
output [N-1:0] sum,
output cout
);
wire [N-1:0] G, P, C;
assign C[0] = cin;
assign cout = C[N-1];
generate
genvar i;
for (i = 0; i < N; i = i + 1) begin : adder_ahead
assign G[i] = a[... | 7.708081 |
module FSM (
input clk,
rst_n,
start,
step2,
step3,
output reg [2:0] out
);
reg [1:0] state, next_state;
localparam state0 = 2'b00, state1 = 2'b01, state2 = 2'b11, state3 = 2'b10;
always @(posedge clk or negedge rst_n) //FSM״̬
if (!rst_n) state <= state0;
else state <= next_state;... | 8.007563 |
module trigger #(
parameter wait_time = 12,
N = 5
) (
input clk,
input trig_in,
output trig_flag
);
reg [N-1:0] cnt;
reg state = 0; //
assign trig_flag = (cnt == 'b0) ? 1'b1 : 1'b0;
always @(posedge clk)
if (state == 0) cnt <= wait_time;
else if (state) cnt <= cnt - 1;
always @(... | 6.963093 |
module edge_detect (
input clk,
input rst_n,
input trig_in,
output pos_edge,
output neg_edge
); //
//
reg trig_in_r0, trig_in_r1, trig_in_r2;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
trig_in_r0 <= 1'b0;
trig_in_r1 <= 1'b0;
trig_in_r2 <= 1'b0;
end ... | 7.114144 |
module input16_mux (
A_0,
B_1,
Select,
Out
);
input [31:0] A_0, B_1;
input Select;
output [15:0] Out;
wire [31:0] A_0, B_1;
wire Select;
wire [15:0] Out;
wire n_0, n_3, n_4, n_5, n_17;
NAND2_X2 g184 (
.A1(n_5),
.A2(n_17),
.ZN(Out[1])
);
MUX2_X2 g194 (
.A(B_1[3... | 7.268914 |
module input5_mux (
A_0,
B_1,
Select,
Out
);
input [4:0] A_0, B_1;
input Select;
output [4:0] Out;
wire [4:0] A_0, B_1;
wire Select;
wire [4:0] Out;
MUX2_X2 g58 (
.A(A_0[4]),
.B(B_1[4]),
.S(Select),
.Z(Out[4])
);
MUX2_X2 g62 (
.A(A_0[2]),
.B(B_1[2]),... | 7.793605 |
module input16_mux (
A_0,
B_1,
Select,
Out
);
input [31:0] A_0;
input [31:0] B_1;
input Select;
output [15:0] Out;
// Internal wires
wire n_0;
wire n_3;
wire n_4;
wire n_5;
wire n_17;
NAND2_X2 g184 (
.A1(n_5),
.A2(n_17),
.ZN(Out[1])
);
MUX2_X2 g194 (
.... | 7.268914 |
module input5_mux (
A_0,
B_1,
Select,
Out
);
input [4:0] A_0;
input [4:0] B_1;
input Select;
output [4:0] Out;
MUX2_X2 g58 (
.A(A_0[4]),
.B(B_1[4]),
.S(Select),
.Z(Out[4])
);
MUX2_X2 g62 (
.A(A_0[2]),
.B(B_1[2]),
.S(Select),
.Z(Out[2])
);
... | 7.793605 |
module synthesizer (
CLOCK_50,
CLOCK2_50,
KEY,
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
AUD_XCK,
AUD_DACLRCK,
AUD_ADCLRCK,
AUD_BCLK,
AUD_ADCDAT,
AUD_DACDAT,
PS2_DAT,
PS2_CLK,
SW,
LEDR
);
input CLOCK_50, CLOCK2_50;
input [3:0] KEY;
input [9:0] SW;
// I2C Audio/V... | 7.72962 |
module control (
// ~KEY[1]
input load,
// ~KEY[3]
input keyboard_pushed,
input write_ready,
input enable,
input release_done,
input clock,
input resetn,
output reg load_a,
load_d,
load_s,
load_r,
load_p,
load_amp,
output reg reset_p,
output reg cou... | 7.715617 |
module datapath (
input clk,
input counter_clock,
input resetn,
input [3:0] offset,
input [3:0] adsr_data_in,
input [1:0] wave_select,
input keyboard_pushed,
input load_a,
load_d,
load_s,
load_r,
load_p,
load_amp,
input reset_p,
input reset_attack,
input p... | 6.91752 |
module demux (
in0,
in1,
in2,
in3,
d0,
d1,
out
);
input in0, in1, in2, in3, d0, d1;
output out;
wire n1, n2;
MUX2X1 U26 (
.B(n1),
.A(n2),
.S(d1),
.Y(out)
);
MUX2X1 U27 (
.B(in2),
.A(in3),
.S(d0),
.Y(n2)
);
MUX2X1 U28 (
.B... | 7.081334 |
module synthfilt (
input wire clk,
input wire rst,
input wire v,
input wire signed [15:0] x,
input wire signed [15:0] A0,
input wire signed [15:0] A1,
input wire signed [15:0] A2,
input wire signed [15:0] A3,
input wire signed [15:0]... | 6.683529 |
module synthfilt_tb;
reg clk, rst, v;
reg signed [15:0] A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10;
wire signed [15:0] x, x1, y;
wire vout;
synthfilt synthfilt (
.clk(clk),
.rst(rst),
.v(v),
.x(x),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.A5(A... | 6.535263 |
module adder2bit (
a_in,
b_in,
o_sum
);
(* src = "adder2bit.v:4" *)
input [1:0] a_in;
(* src = "adder2bit.v:5" *)
input [1:0] b_in;
(* src = "adder2bit.v:6" *)
output [2:0] o_sum;
(* src = "adder2bit.v:9" *)
wire r_c0;
(* src = "adder2bit.v:10" *)
wire r_s1;
assign o_sum[0] = a_in[0] ^... | 7.19208 |
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