code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb_rca_clk;
reg clock; //input clock
reg [31:0] tb_a, tb_b; //32bits 2 input
reg tb_ci; //carry in
wire [31:0] tb_s_rca; //32bits sum(output)
wire tb_co_rca; //carry out
parameter STEP = 10; //define STEP=10ns
rca_clk U0_rca_clk (
.clock(clock),
.a(tb_a),
.b(tb_b),
... | 6.819511 |
module tb_rca_net;
// TB_SIGNALS
reg clk, reset;
reg [7:0] num1;
reg [7:0] num2;
wire [8:0] sum_out;
// Instantiate the Unit Under Test (UUT)
rca uut (
.num1(num1),
.num2(num2),
.sum (sum_out)
);
initial begin
$dumpfile("tb_rca_net.vcd");
$dumpvars(0, tb_rca_net);
// I... | 7.21298 |
module tb_rd_control ();
reg clk;
reg reset;
reg active;
wire [3:0] rd_en;
wire [31:0] rd_addr;
always begin
#5;
clk = ~clk;
end
initial begin
clk = 1'b0;
reset = 1'b1;
active = 1'b0;
#10;
reset = 1'b0;
#10;
#10;
active = 1'b1;
#10;
$stop;
#10;
... | 6.552346 |
module tb;
`define NULL 0
`define CYCLE 20
integer fp; // file handler
integer handle;
reg clk;
reg nrst;
//reg [8*1-1:0] strings;
reg [8*32-1:0] strings;
reg [8*5-1:0] cmd, op1, op2;
//reg [0:8*32-1] strings;
reg [255:0] str;
in... | 7.134967 |
module testbench;
reg clk_tb, reset_tb;
reg [31:0] data_tb; // synchronous
reg [31:0] s_data_fill; // asynchronous
parameter halfperiod = 5;
parameter reset_delay = 100;
wire [31:0] data; // synchronous
wire valid, ready; // valid synchronous, ready asynchronous
wire valid_var;
master m0 (
... | 7.015571 |
module tb_receiver (
input clk,
input rst,
input en,
input [3:0] data,
output reg [3:0] expected,
output reg failure
);
always @(posedge clk or posedge rst)
if (rst) begin
expected <= 1;
failure <= 0;
end else if (en) begin
... | 7.305894 |
module TestBench ();
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, i... | 7.747207 |
module tb_record_play;
reg clk_i;
reg button_a;
reg button_b;
wire [4:0] leds_o;
initial begin
$from_myhdl(clk_i, button_a, button_b);
$to_myhdl(leds_o);
end
record_play dut (
clk_i,
button_a,
button_b,
leds_o
);
endmodule
| 6.534233 |
module tb_reg32bit ();
wire [31:0] q;
reg [31:0] d;
reg clk, reset;
reg_32bit register (
q,
d,
clk,
reset
);
always @(clk) #5 clk <= ~clk;
initial
$monitor("clk: ", clk, " Reset = ", reset, " D = %b ", d, "Q = %b ", q, " time = ", $time);
initial begin
clk = 1'b1;
... | 7.279752 |
module : tb_regFile
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Soft... | 8.600464 |
module tb_regFile_hier ( /*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] read1Data; // From top of rf_hier.v
wire [15:0] read2Data; // From top of rf_hier.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inpu... | 7.156617 |
module tb_register ();
reg rst;
reg clk;
reg en;
reg [7:0] din;
wire [6:0] qout;
register regi (
rst,
clk,
en,
din,
qout
);
initial begin
clk = 1'b0;
repeat (30) #10 clk = ~clk;
end
initial begin
rst <= 1'b0;
#40;
rst <= 1'b1;
din <= 4'b010011... | 6.508049 |
module tb_register12bit_cgrundey ();
reg [11:0] reg_in;
reg enable;
wire [11:0] reg_out;
clk M1 (
enable,
clk_out
);
register12bit_cgrundey M2 (
clk_out,
reg_in,
reg_out
);
initial begin
enable = 1'b1;
reg_in = 12'd160;
#200 reg_in = 12'd250;
#200 reg_in =... | 7.137969 |
module: registerFile
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_RegisterFile;
// Inputs
reg [4:0] Rn;
reg [4:0] Rm;
reg RegWr;
reg [4:0] Rd;
reg [63:0] data;
reg clk;... | 7.614083 |
module RegistersBankTestbench;
reg clock;
reg [1:0] readReg1;
reg [1:0] readReg2;
reg [1:0] readReg3;
reg [1:0] writeReg;
reg [7:0] writeData;
reg [7:0] memWrite;
wire [7:0] data1;
wire [7:0] data2;
wire [7:0] data3;
wire [7:0] memRead;
wire [7:0] raRead;
// sinais de controle
reg RegWrite... | 6.816238 |
module tb_register_controller ();
reg clock;
reg [7:0] rx_in;
wire [7:0] tx_out;
wire [3:0] Byte_0;
wire [3:0] Byte_1;
wire [3:0] Byte_2;
wire [3:0] Byte_3;
wire [3:0] Byte_4;
wire [3:0] Byte_5;
always #1 clock = ~clock;
register_controller tb_register_Controller_DUT (
//INPUTS
.c... | 7.141602 |
module tb_register_file;
reg clk, reset;
reg WrEn; // write enable
reg [0:2] sel; // ppp value
reg [0:`DATA_WIDTH - 1] wr_data;
reg [0:`ADDR_WIDTH - 1] rd_addr_0, rd_addr_1, wr_addr;
wire [0:`DATA_WIDTH - 1] rd_data_0, rd_data_1;
always #(0.5 * `CLK_CYCLE) clk = ~clk;
// Instantiation of DUT
reg... | 6.997046 |
module tb_register_file_syn;
reg clk, reset;
reg WrEn; // write enable
reg [0:2] sel; // ppp value
reg [0:`DATA_WIDTH - 1] wr_data;
reg [0:`ADDR_WIDTH - 1] rd_addr_0, rd_addr_1, wr_addr;
wire [0:`DATA_WIDTH - 1] rd_data_0, rd_data_1;
always #(0.5 * `CLK_CYCLE) clk = ~clk;
// Instantiation of DUT
... | 6.997046 |
module Tb_Registros;
reg [7:0] Mux_a_Reg;
reg [2:0] Sel_RX;
reg [2:0] Sel_RY;
reg [7:0] R0;
reg Load_Store;
reg i_Clk;
reg i_Reset;
wire [7:0] RX;
wire [7:0] RY;
Registros uut (
.Mux_a_Reg(Mux_a_Reg),
.Sel_RX(Sel_RX),
.Sel_RY(Sel_RY),
.R0(R0),
.Load_Store(Load_Store),
... | 6.830561 |
module TB_regis_nao_bloq;
reg TB_clear, TB_clock, TB_in;
wire TB_Q3, TB_Q2, TB_Q1, TB_Q0;
// parameter stop_time = 1000;
// initial # stop_time ;
registrador_nao_bloqueante dut (
TB_in,
TB_clear,
TB_clock,
TB_Q0,
TB_Q1,
TB_Q2,
TB_Q3
);
initial begin
TB_cl... | 6.812593 |
module tb_REG_SHIFT_PLOAD;
reg [31:0] Din;
reg p_load;
reg start_tx;
reg reset;
reg clk;
reg clk_tx;
wire tx_done;
wire tx_busy;
wire Dout;
REG_SHIFT_PLOAD DUT (
Din,
p_load,
start_tx,
reset,
clk,
clk_tx,
tx_done,
tx_busy,
Dout
);
initial ... | 6.922928 |
module tb_relu_seq ();
localparam DATA_WIDTH = 8;
localparam NUM_INPUT_DATA = 1;
localparam WIDTH_INPUT_DATA = NUM_INPUT_DATA * DATA_WIDTH;
localparam NUM_OUTPUT_DATA = 1;
localparam WIDTH_OUTPUT_DATA = WIDTH_INPUT_DATA;
localparam signed [DATA_WIDTH-1:0] ZERO_POINT = {DATA_WIDTH{1'b0}};
localparam NUM ... | 6.930274 |
module tb_reset #(
parameter ASSERT_TIME = 32
) (
output rst_out
);
reg tb_rst;
initial tb_rst <= 1'b1;
task assert_reset;
begin
tb_rst = 1'b1;
#ASSERT_TIME;
tb_rst = 1'b0;
$display("-#- %15.t | %m: tb_rst asserted!", $time);
end
endtask
assign rst_out = tb_rst;
... | 7.710531 |
module. It should be instantiated
// and connected to both the DUT
//
//
// Parameters:
// None
//
// Notes :
//
// Multicycle and False Paths
// None - this is a testbench file only, and is not intended for synthesis
//
`timescale 1ns/1ps
module tb_resetgen (
input clk,
output reg reset
)... | 7.134595 |
module TB_reset_block();
wire reset_o;
reg reset_i;
reg areset;
reg clk;
reg state;
reg [31:0] counter;
reset_block #(
.DELAY(`SIM_RESET_DELAY),
.WIDTH(`SIM_RESET_WIDTH)
) reset_block (
.clk(clk), .async_reset_i(areset), .reset_i(reset_i), .reset_o(reset_o)
);
initial begin
... | 7.040415 |
module checks the data received from the DUT against
// the data stored in a FIFO
//
// Parameters:
//
// Tasks:
// start_chk : Enables the checker
//
// Functions:
//
// Internal variables:
// reg enabled;
//
//
// Notes :
//
//
// Multicycle and False Paths
// None - this i... | 6.949591 |
module: retnuoCl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_retnuoCl;
// Inputs
reg [15:0] lfsr;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
... | 7.20633 |
module tb_RE_Control;
parameter s_IDLE = 2'b00; //States for the main FSM
parameter s_EXPOSURE = 2'b01;
parameter s_READOUT = 2'b10;
parameter s_INIT = 3'b000; //States for the sub-FSM
parameter s_NRE_1 = 3'b001;
parameter s_ADC_1 = 3'b010;
parameter s_NOTHING = 3'b011;
parameter s_NRE_2 = 3'b100;
... | 6.673291 |
module tb_rf_modulator;
reg clk;
reg rst_n;
wire [5:0] video;
wire [6:0] rf;
//Accumulate 3 signals
// Color
// VSYNC
// HSYNC
reg [31:0] color_acc;
reg [31:0] vsync_acc;
reg [31:0] hsync_acc;
//Make dummy signal
always @(posedge clk) begin
if (!rst_n) begin
color_acc <= 0;
... | 6.576049 |
module TB_rgb2gray;
`timescale 10ns/10ns
reg clk;
reg [11:0] rgb_in;
wire [11:0] gray_out;
grayScale UUT(clk, rgb_in, gray_out);
initial begin
#20;
rgb_in = 12'b1111_1111_1111;
#20;
rgb_in = 12'b1010_1010_1010;
$stop;
end
always @(posedge clk) begin
clk =#10 ~ clk;
end
endmodule
| 6.527697 |
module TB_Ring ();
reg en;
wire clk_out;
Ring #(3, 17) UUT (
en,
clk_out
);
initial begin
#200 en = 1'b0;
#200 en = 1'b0;
#200 en = 1'b1;
#100000 $stop;
end
endmodule
| 6.827656 |
module tb_ripple_carry ();
reg [3:0] A, B; // Declaration of two four-bit inputs
reg cin; // and the one-bit input carry
wire [3:0] s; // Declaration of the five-bit outputs
wire cout; // internal carry wires
ripple_carry DUT (
s,
cout,
cin,
A,
B
);
initial begin
#10... | 7.753905 |
module ripple_test_bench ();
reg [3:0] A, B;
reg Cin;
wire [3:0] Sout;
wire Cout;
ripple_carry_adder F6 (
Sout,
Cout,
A,
B,
Cin
);
initial begin
A = 4'd0;
B = 4'd0;
Cin = 1'b0;
#5 A = 4'd3;
B = 4'd4;
#5 A = 4'd2;
B = 4'd5;
#5 A = 4'd10;
... | 6.602528 |
module tb_ripple_counter;
// Inputs
reg clk, reset;
// Output
wire [1:0] q;
// Instantiate the Unit Under Test (UUT)
ripple_counter uut (
.clk(clk),
.reset(reset),
.q(q)
);
initial begin
$dumpfile("tb_ripple_counter.vcd");
$dumpvars(0, tb_ripple_counter);
// Initialize In... | 7.002753 |
module : RISC_V_Core
* @author : Adaptive & Secure Computing Systems (ASCS) Laboratory
* Copyright (c) 2018 BRISC-V (ASCS/ECE/BU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software w... | 8.748131 |
module tb_riscv ();
reg clk;
reg rst_n;
wire [31:0] x1 = tb_riscv.m_riscv_soc.top.m_regs.regs[1];
wire [31:0] x2 = tb_riscv.m_riscv_soc.top.m_regs.regs[2];
wire [31:0] x3 = tb_riscv.m_riscv_soc.top.m_regs.regs[3];
wire [31:0] x26 = tb_riscv.m_riscv_soc.top.m_regs.regs[26];
wire [31:0] x27 = tb_riscv.m_ris... | 7.067704 |
module tb_RISCV_CPU ();
parameter nb = 32;
parameter INSTR_WIDTH = 32;
parameter MEM_ADDR_SIZE = 12;
wire CLK_i;
wire RST_n_i;
wire [nb-1:0] PC_i;
wire [INSTR_WIDTH-1:0] INSTR_i;
wire MEM_READ_i;
wire MEM_WRITE_i;
wire DUMP_i;
wire [nb-1:0] ADDR_MEM_i;
wire [nb-1:0] WR_DATA_i;
wire [nb-1:0] R... | 7.079136 |
module tb_RISCV_CPU_abs ();
parameter nb = 32;
parameter INSTR_WIDTH = 32;
parameter MEM_ADDR_SIZE = 12;
wire CLK_i;
wire RST_n_i;
wire [nb-1:0] PC_i;
wire [INSTR_WIDTH-1:0] INSTR_i;
wire MEM_READ_i;
wire MEM_WRITE_i;
wire DUMP_i;
wire [nb-1:0] ADDR_MEM_i;
wire [nb-1:0] WR_DATA_i;
wire [nb-1:... | 7.30689 |
module tb_RISC_16bit #(
parameter W = 16
) ();
reg clk;
reg reset;
wire [W-9:0] PC_addr;
wire [W-1:0] alu_out;
wire [2:0] alu_s;
wire [2:0] state;
wire [2:0] nstate;
RISC_16bit UUT (
.clk (clk),
.reset (reset),
.PC_addr(PC_addr),
.alu_out(alu_out),
.alu_s (alu_s... | 6.736813 |
module tb_RISC_16bit_ControlUnit #(
parameter W = 16
) ();
reg clk;
reg reset;
reg RF_Rp_zero;
wire [W-9:0] PC_addr;
wire PC_clr; //
wire D_addr_sel;
wire [W-9:0] D_addr;
wire D_rd;
wire D_wr;
wire [W-9:0] RF_W_data;
wire RF... | 6.736813 |
module tb_RISC_16bit_Datapath #(
parameter W = 16
) ();
reg clk;
reg [W-1:0] R_data;
reg [W-9:0] RF_W_data; // A, B input;
reg RF_s1;
reg RF_s0;
reg [ 3:0] RF_W_addr;
reg W_wr;
reg [ 3:0] RF_Rp_addr;
reg Rp_rd;
reg [ 3:0] RF_Rq_addr;
reg ... | 6.736813 |
module tb_RISC_16bit_test #(
parameter W = 16
) ();
reg clk;
reg reset;
wire [W-9:0] PC_addr;
wire [W-1:0] alu_out;
wire [2:0] alu_s;
wire [2:0] state;
wire [2:0] nstate;
RISC_16bit_test UUT (
.clk (clk),
.reset (reset),
.PC_addr(PC_addr),
.alu_out(alu_out),
.alu... | 6.736813 |
module : tb_RISC_V_Core
* @author : Adaptive & Secure Computing Systems (ASCS) Laboratory
* Copyright (c) 2018 BRISC-V (ASCS/ECE/BU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Softwar... | 8.302029 |
module : tb_double_tx
* @author : Adaptive & Secure Computing Systems (ASCS) Laboratory
* Copyright (c) 2018 BRISC-V (ASCS/ECE/BU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software w... | 8.202371 |
module tb_ri_limit_checker (
// Inputs - System.
aclk_i,
aresetn_i,
// Inputs
valid_i,
ready_i,
last_i,
id_i
);
//----------------------------------------------------------------------
// MODULE PARAMETERS.
//----------------------------------------------------------------------... | 7.283601 |
module tb_rmii_loopback ();
reg arst_n;
reg PHY0_REF_CLK;
reg PHY1_REF_CLK;
initial begin
$dumpfile("./vcd/tb_rmii_repeater.vcd");
$dumpvars(0, rmii_repeater);
PHY0_REF_CLK <= 1'b0;
PHY1_REF_CLK <= 1'b0;
arst_n <= 1;
#100 arst_n <= 0;
#100 arst_n <= 1;
#200000 $finish;
end
... | 6.998667 |
module: RO
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_RO;
// Inputs
reg RESET;
// Outputs
wire CLK_O;
// Instantiate the Unit Under Test (UUT)
RO uut (
.RESET(RESE... | 6.909776 |
module tb_rom_ctrl ();
//input
reg sys_clk;
reg sys_rst_n;
reg key1;
reg key2;
//output
wire [7:0] addr;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
key1 <= 1'b0;
key2 <= 1'b0;
#30 sys_rst_n <= 1'b1;
#700_000
//key1
key1 <= 1'b1;
#2... | 7.341808 |
module tb_rotate_led ();
reg clk, reset, pause, fast, rt;
wire [4:0] dout;
rotate_led UUT (
.clk(clk),
.reset(reset),
.pause(pause),
.fast(fast),
.rt(rt),
.dout(dout)
);
//Period of the Base Clock
parameter T = 20;
initial begin
clk = 0;
forever #(T / 2) clk... | 6.806908 |
module tb_rs232 ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire tx;
//reg define
reg sys_clk;
reg sys_r... | 7.523568 |
module tb_rst_ctrl;
// rst_ctrl Parameters
parameter real PERIOD_SRC = 5;
parameter real PERIOD_SYS = 4;
// rst_ctrl Inputs
reg src_clk = 0;
reg sys_clk = 0;
reg arstn = 1;
reg pll_locked = 0;
// rst_ctrl Outputs
wire rstn_pll;
wire rstn_sys;
wire rstn_mac;
initial begin
forever ... | 7.347006 |
module tb_RS_Decoder ();
reg [0:59] msg_in;
wire [0:43] msg_out;
wire valid;
RS_Decoder decode (
msg_in,
msg_out,
valid
);
initial begin
msg_in = 60'h123456789AB33cc;
#50 $display("TC01: No errors");
if (msg_out != 44'h123456789AB) $display("Result is wrong");
msg_in = 6... | 6.635579 |
module tb_rtc ();
reg clk;
reg rst_n;
wire interrupt;
reg io_address = 1'b0;
reg io_read = 1'b0;
wire [ 7:0] io_readdata;
reg io_write = 1'b0;
reg [ 7:0] io_writedata = 8'd0;
reg [ 7:0] mgmt_address = 8'd0;
reg mgmt_write = 1'b0;
reg [3... | 7.447439 |
module tb_RTL_SYNC_FIFO ();
reg [7:0] din;
reg clk;
reg we;
reg EOD_in;
reg re;
reg rst;
integer i;
initial begin
$dumpfile("./vcd/tb_rtl_sync_fifo.vcd");
$dumpvars(0, rtl_sync_fifo);
rst <= 1'b1;
clk <= 1'b0;
din <= 8'b0;
we <= 1'b0;
re <= 1'b0;
#1000 rst <= 1'b0;
... | 7.06836 |
module tb_rx_byte_aligner;
reg clk;
reg reset;
reg [7:0]byte_i;
wire [7:0]byte_o;
wire synced;
wire reset_g;
GSR
GSR_INST (
.GSR_N(1'b1),
.CLK(1'b0)
);
mipi_rx_byte_aligner inst1( .clk_i(clk),
.reset_i(reset),
.byte_i(byte_i),
.byte_o(byte_o),
.byte_valid_o(synced));
task sen... | 6.839329 |
module tb_rx_fsm ();
reg clk_wr;
reg clk_rd;
reg rst_n;
initial begin
rst_n = 1'b0;
#25 rst_n = 1'b1;
end
// 50 MHz clk_wr:
initial begin
clk_wr = 1'b1;
forever begin
#10 clk_wr = ~clk_wr;
end
end
// 100 MHz clk_rd:
initial begin
clk_rd = 1'b1;
#2
forever be... | 6.827902 |
module tb_s2mm ();
reg clk = 0;
always @(*) clk <= #1 ~clk;
reg [15:0] resetn_reg = 0;
wire resetn;
wire send_data;
always @(posedge clk) resetn_reg <= {resetn_reg[14:0], 1'b1};
assign resetn = resetn_reg[12];
assign send_data = resetn_reg[15];
initial begin
wait (send_data == 1);
@... | 7.620385 |
module tb_S2P;
// Inputs
reg clk;
reg rst;
reg start;
// Outputs
wire [3:0] parallel_data;
wire serial_in;
wire data_flag;
// DUT
data_generator dat_gen (
.clk(clk),
.rst(rst),
.enable(start),
.serial_in(serial_in),
.data_flag(data_fl... | 6.699513 |
module tb_sale_machine ();
parameter CHARGE_WIDTH = 2;
reg clk_inst;
reg rst_n_inst;
reg ten_inst;
reg twenty_inst;
reg fifty_inst;
wire out_inst;
wire [CHARGE_WIDTH-1:0] charge_inst;
sale_machine #(
.CHARGE_WIDTH(CHARGE_WIDTH)
) sale_machine_inst (
.clk(clk_inst),
.rst_n(rst_n_... | 6.545279 |
module tb_salidas;
reg Rst;
reg Clk;
reg [7:0] Rx;
reg [7:0] Ry;
reg [7:0] num;
reg [1:0] outbus;
wire [7:0] DataOut_Bus;
wire [7:0] Addres_Data_Bus;
wire LE;
salidas uut (
.Rst(Rst),
.Clk(Clk),
.Rx(Rx),
.Ry(Ry),
.num(num),
.outbus(outbus),
.DataOut_Bus(Da... | 6.586853 |
module: samcoupe
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_samcoupe;
// Inputs
reg clk24;
reg clk12;
reg clk6;
reg ear;
reg clkps2;
reg dataps2;
reg rst_n;
// ... | 6.699229 |
module is to test the sample rate controller
*/
module tb_sample_rate_controller();
reg clk;
reg reset_n;
reg en;
wire [15:0] sample_rate;
wire go;
assign sample_rate = 16'd100;
parameter CLK_HALF_PERIOD = 20; // 25Mhz
parame... | 7.58345 |
module tb_SA_Data_mover;
parameter FIFO_DATA_WIDTH = 8;
parameter FIFO_DEPTH = 14;
parameter PE_SIZE = 14;
parameter integer MEM0_DEPTH = 896;
parameter integer MEM1_DEPTH = 896;
parameter integer MEM0_ADDR_WIDTH = 10;
parameter integer MEM1_ADDR_WIDTH = 10;
parameter integer MEM0_DATA_WIDTH = 112;
pa... | 6.590882 |
module t_Sequential_Binary_Multiplier;
parameter dp_width = 5; // Set to width of datapath
wire [2*dp_width -1:0] Product; // Output from multiplier
wire Ready;
reg [dp_width -1:0] Multiplicand, Multiplier; // Inputs to multiplier
reg Start, clock, reset_b;
// Instantiate multiplier
Sequential_Binary_M... | 7.172672 |
module*/
`timescale 1 ns / 1 ps
module tb_sbox();
wire [7:0] data_out;
reg [7:0] counter = 0;
reg [7:0] insert;
reg [7:0] result = 0;
integer test_vector;
initial
test_vector = $fopen("sbox_testVector.txt","r");
always
#10 counter = counter + 1;
always
#10
if (! $feof(test_vector))
begin
$fscanf(test... | 6.729021 |
module tb_sc ();
reg clk, rst;
main A (
rst,
clk
);
always #5 clk = ~clk;
initial begin
$monitor($time, " r0=%d, r1=%d, r3=%d r4=%d mem16=%d", A.regs.reg_num[0], A.regs.reg_num[1],
A.regs.reg_num[3], A.regs.reg_num[4], A.D_mem.d_mem[16]);
rst = 1'b1;
clk = 1'b0;
#1 ... | 6.555518 |
module tb_scaler_5 ();
reg [1:0] d;
wire [3:0] q;
scaler_5 scaler0 (
.d(d),
.q(q)
);
initial begin
d <= 0;
#10 d <= 2'b01;
#10 d <= 2'b10;
#10 d <= 2'b11;
#10 $finish;
end
endmodule
| 6.988045 |
module: asic
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_scandoubler;
// Inputs
reg clk12;
reg clk24;
// Outputs
wire [18:0] vramaddr;
wire [18:0] cpuramaddr;
wire hs... | 6.618777 |
module dummy_proc #(
parameter DATA_WIDTH = 16
) (
input wire reset,
input wire clk,
input wire [DATA_WIDTH-1:0] s_data,
input wire s_valid,
output wire s_ready,
output wire [DATA_WIDTH-1:0] m_data,
output wire m_valid,
input wi... | 7.363305 |
module TB_scheduler_partial #(
parameter W = 59
);
// Inputs
reg clk;
reg rst;
reg wr;
reg [W-2:0] task_in;
reg [8*W-1:0] running_tasks_in;
reg action, subtract_en;
// Outputs
wire [8*W-1:0] running_tasks;
wire v_exch, busy_ready, v_active;
wire [W-2:0] task_exch;
// Instantiate the Unit ... | 7.041905 |
module tb_scoreboard (
///////////////////////////////////////////
input wire C_syn_rco, // from synthesizable counter A, B, C
input wire C_syn_load,
input wire [3:0] C_syn_Q,
///////////////////////////////////////////
output reg clk,
output reg reset,
output reg [1:0] tb_mode, // choose from 00, 01, ... | 7.549901 |
module tb_sdckgen;
// Local declarations
// {{{
reg clk, reset;
reg cfg_clk90, cfg_shutdown;
reg [7:0] cfg_ckspd;
wire w_ckstb, w_halfck;
wire [7:0] w_ckwide;
// }}}
////////////////////////////////////////////////////////////////////////
//
// Clock and reset generation
// {{{
initial begin
... | 7.075031 |
module tb_sdio;
// Local declarations
// {{{
parameter [1:0] OPT_SERDES = 1'b1;
parameter [1:0] OPT_DDR = 1'b1;
parameter [0:0] OPT_VCD = 1'b0;
localparam AW = 3, DW = 32;
localparam VCD_FILE = "trace.vcd";
reg [2:0] ckcounter;
wire clk, hsclk;
reg reset;
wire bfm_cyc, bfm_stb, bfm_we, bfm_stall... | 7.380832 |
module tb_sdp_ram ();
parameter MEM_ADDR_WIDTH = 9;
parameter MEM_WORD_WIDTH = 64;
parameter MEM_WR_MASK_WIDTH = MEM_WORD_WIDTH / 8;
// Parameters for Simulation
parameter clk_period = 10; // ns, 100MHz
parameter start_delay = 100; // clk cycle
parameter rst_delay = 20;
parameter rst_period = 5;
... | 7.383146 |
module tb_sdp_ram_rdonly ();
parameter MEM_ADDR_WIDTH = 9;
parameter MEM_WORD_WIDTH = 64;
parameter MEM_WR_MASK_WIDTH = MEM_WORD_WIDTH / 8;
// Parameters for Simulation
parameter clk_period = 10; // ns, 100MHz
parameter start_delay = 100; // clk cycle
parameter rst_delay = 20;
parameter rst_period =... | 7.464556 |
module tb_sdram_ctrl ();
reg clk_100m;
reg clk_100m_shift;
reg rst_n;
initial begin
rst_n = 1'b0;
#25 rst_n = 1'b1;
end
// 100 MHz clk and clk_shift:
initial begin
clk_100m = 1'b1;
forever begin
#5 clk_100m = ~clk_100m;
end
end
initial begin
clk_100m_shift = 1'b0;
... | 6.548358 |
module tb_sdram_init ();
//********************************************************************//
//****************** Internal Signal and Defparam ********************//
//********************************************************************//
//wire define
//clk_gen
wire clk_50m; //PLL输出50M时钟
w... | 7.021773 |
module tb_sdrd_SPIctrl;
/*----------------------------------*/
/* parameters */
/*----------------------------------*/
parameter P_CYCLE_CLK = 10;
parameter STB = 1;
parameter outfile = "output.txt";
/*----------------------------------*/
/* regsters */
/*----------------------------------*/
/*---... | 7.058725 |
module: sdtest
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_sdtest;
// Inputs
reg clk;
reg rst;
reg spi_do;
// Outputs
wire spi_clk;
wire spi_di;
wire spi_cs;
wire t... | 6.772562 |
module tb_sd_send;
reg ex_clk, sd_clk, reset, send_en;
reg [37:0] cmd_content;
reg [47:0] correct_send;
wire sd_cmd, sending;
wire [3:0] sd_dat;
integer index;
sd_send uut (
ex_clk,
sd_clk,
reset,
send_en,
cmd_content,
sending,
sd_cmd,
sd_dat
);
task ... | 7.103496 |
module tb_segment7;
reg [3:0] bcd;
wire [6:0] seg;
integer i;
// Instantiate the Unit Under Test (UUT)
lab3ex uut (
.bcd(bcd),
.seg(seg)
);
//Apply inputs
initial begin
for (
i = 0; i < 30; i = i + 1
) //run loop for 0 to 15.
begin
bcd = i;
#10; //wai... | 6.669573 |
module tb_seg_595_static ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire stcp; //输出数据存储寄时钟
wire shcp; //移位寄存器的... | 8.260895 |
module tb_seg_dynamic ();
//input
reg sys_clk;
reg sys_rst_n;
reg [19:0] data;
reg [ 5:0] point;
reg sign;
reg seg_en;
//output
wire [ 5:0] sel;
wire [ 7:0] seg;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
data <= 20'd0;
point <= 6'b0;
... | 7.091586 |
module tb_seg_static ();
// seg_static Inputs
reg sys_clk ;
reg sys_rst_n ;
// seg_static Outputs
wire [5:0] sel;
wire [7:0] seg;
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#20 sys_rst_n <= 1'b1;
end
always #10 sys_clk = ~sys_clk;
seg_static #(
.CNT_MAX(25'd24... | 7.338977 |
module tb_selector ();
reg [2:0] c_sel;
reg [7:0] Result;
reg [7:0] Datain_Bus;
reg [7:0] num;
reg [7:0] Adress_Instruction_Bus;
reg [7:0] Ry;
wire [7:0] selector;
selector uut (
.c_sel(c_sel),
.Result(Result),
.Datain_Bus(Datain_Bus),
.num(num),
.Ry(Ry),
.Adre... | 7.063898 |
module tb_sender (
input clk,
input rst,
output reg [3:0] data,
output reg en,
input ack,
input [7:0] gap_from,
input [7:0] gap_to
);
reg can_send;
always @(posedge clk or posedge rst)
if (rst) can_send <= 1;
else if (ack) can_send <= 1;
... | 7.501668 |
module tb_send_control;
reg clk, busy, rst;
wire [15:0] segment_num;
wire [7:0] txid, txid_inter, aux;
wire start_sending;
reg start_frame, oneframe_done;
send_control uut (
.clk125MHz(clk),
.RST(rst),
// .switches(8'b01010000),
// .switches(8'b01011111),
.switches(8'b0101000... | 6.786488 |
module tb ();
reg D_IN;
reg RST;
reg CLK;
wire MATCH;
integer fd_in;
integer fd_out;
integer test;
integer fp;
parameter DUTY = 1;
always #DUTY CLK = ~CLK;
initial begin
fd_out = $fopen("./seq.out", "w");
fd_in = $fopen("./pattern.in", "r");
$fmonitor(fd_out, "At time %t ns, CLK=%d... | 7.002324 |
module tb_seq_detect ();
wire p_flag;
reg p_din, p_clk, p_rst_n;
reg [35:0] data = 36'b0000_1100_0010_0110_1001_1011_0010_0001_1101;
seq_detect dec (
.flag (p_flag),
.clk (p_clk),
.din (p_din),
.rst_n(p_rst_n)
);
initial begin
p_clk = 1'b1;
forever #5 p_clk = ~p_clk;
e... | 7.61768 |
module tb_serialAdder4bit();
wire [3:0] Acc;
wire SI2;
reg SI;
reg clr, clk, ShftCtrl;
integer i;
serialAdder_4bit sa( Acc,SI2, SI, ShftCtrl, clr, clk );
always @(posedge clk) begin
$display("ShftCtrl = %b ", ShftCtrl, " SI = %b ", SI," SI2:= ",SI2 ," Acc = %b ", Acc, "Clk:... | 6.578503 |
module tb_SerialAdd;
reg clk, reset, a, b;
wire c_out;
wire [3:0] s_out;
SerialAdd SA (
a,
b,
clk,
reset,
c_out,
s_out
);
initial begin
clk = 1;
forever #5 clk = ~clk;
end
initial begin
reset = 0;
a = 0;
b = 0;
reset = 1;
//a=1111,b=1010,s... | 6.937421 |
module: serializer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_serializer;
wire [7:0] data;
wire clk;
wire send;
wire txd;
seri... | 7.107914 |
module name: tb_Serial_Adder
Created By: Ard Aunario
Date Created: 9/13/19
Description: Testbench for Serial_Adder
Revised:
********************************************************
*******************************************************/
`timescale 1 ns / 1 ps
`define CLK_PER 10
module tb_Serial_Adder();
parameter... | 7.372984 |
module tb_serial_crc_ccitt;
reg clk;
reg reset;
reg enable;
reg init;
reg data_in;
wire [15:0] crc_out;
serial_crc_ccitt dut (
clk,
reset,
enable,
init,
data_in,
crc_out
);
initial begin
clk = 0;
data_in = 0;
ini... | 7.130267 |
module tb_serial_transmit;
localparam LEN_CODED_BLOCK = 66;
reg [9:0] counter;
reg clock;
reg reset;
reg block_clock;
reg tx_clock;
reg [LEN_CODED_BLOCK-1 : 0] data;
wire tx_bit;
initial begin
clock = 0;
reset = 1;
counter = 0;
data = {LEN_CODED_BLOCK{1'b0}};
#6 reset = 0;
#4... | 6.66482 |
module TB_serial_uart();
wire serial_in;
wire serial_out;
wire [7:0] data_out;
wire busy;
wire gotdata;
reg ostrb;
reg clk;
reg [7:0] testval;
reg reset;
assign serial_in=serial_out;
serial_uart #(
) uart(.serial_in(serial_in), .serial_out(serial_out), .clk(clk), .reset(reset),
.as_data_i(testval), .as_d... | 6.604073 |
module tb_sete_segmentos;
//Input
reg [3:0] Num_Binario;
//Outputs
wire Segmento_A, Segmento_B, Segmento_C, Segmento_D, Segmento_E, Segmento_F, Segmento_G;
integer i;
//Instancia a unidade a ser testada
sete_segmentos uut (
.Num_Binario(Num_Binario),
.Segmento_A (Segmento_A),
.Segmen... | 6.529645 |
module tb_set_alarm;
// set_alarm Parameters
parameter PERIOD = 10;
// set_alarm Inputs
reg signal = 0;
reg load = 0;
reg moveRightBtn = 0;
reg moveLeftBtn = 0;
reg incrementBtn = 0;
reg decrementBtn = 0;
// set_alarm Outputs
wire [3:0] load_seconds;
... | 7.849587 |
module: SignExtensionUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_SEU;
// Inputs
reg [25:0] instruction;
reg [1:0] seuSignal;
// Outputs
wire [63:0] seuOutput;
//... | 7.426185 |
module
`timescale 1ns/1ns
module tb_Seven_Seg();
reg [3:0] Seg_in;
wire [6:0] Seg_out;
Seven_Seg DUT_Seven_Seg(Seg_in, Seg_out);
initial
begin
#5 Seg_in=4'b0000;
#5 Seg_in=4'b0001;
#5 Seg_in=4'b0010;
#5 Seg_in=4'b0011;
#5 Seg_in=4'b0100;
#5 Seg_in=4'b0101;
#5 Seg_in=4'b0110;
#5 Seg_in=4'b... | 6.608387 |
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