code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module terminal_demo (
input clk,
reset_n,
// Receiver port
input rd_uart, // left push button
output rx_empty, // LED0
input rx,
// Transmitter port
input [7:0] w_data, // SW0 -> SW7
input wr_uart, // right push button
output tx_full, // LED1
output ... | 7.027718 |
module terminal_tb();
reg clk = 1'b0;
reg n_reset = 1'b1;
wire ps2Clk = 1'b1;
wire ps2Data = 1'b1;
reg n_wr = 1'b1;
reg n_rd = 1'b1;
reg regSel = 1'b0;
reg [7:0] dataIn;
wire [7:0] dataOut;
wire videoR0;
wire ... | 7.035226 |
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
); //
wire [7:0] e;
wire [7:0] f;
assign e = a < b ? a : b;
assign f = e < c ? e : c;
assign min = f < d ? f : d;
endmodule
| 7.203305 |
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
); //
assign min =(a<b)&(a<c)&(a<d)?a:(b<a)&(b<c)&(b<d)?b:(c<b)&(c<a)&(c<d)?c:d;
endmodule
| 7.203305 |
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
); //
wire [7:0] intermediate_result1;
wire [7:0] intermediate_result2;
assign intermediate_result1 = a < b ? a : b;
assign intermediate_result2 = c < d ? c : d;
assign min = intermediate_result1<intermediate_result2? interme... | 7.203305 |
module ternary_add (
a,
b,
c,
o
);
parameter WIDTH = 8;
parameter SIGN_EXT = 1'b0;
input [WIDTH-1:0] a, b, c;
output [WIDTH+1:0] o;
wire [WIDTH+1:0] o;
generate
if (!SIGN_EXT) assign o = a + b + c;
else
assign o = {a[WIDTH-1],a[WIDTH-1],a} +
{b[WIDTH-1],b[WIDTH-1],b} +... | 7.659901 |
module ternary_adder #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
input [WIDTH-1:0] c,
output [WIDTH-1:0] o
);
assign o = a + b + c;
endmodule
| 8.491873 |
module ternary_full_adder_1digit (
input Cin,
input [1:0] X,
Y,
output [1:0] S,
output Cout
);
wire Cin_bar;
wire SumX1, SumX2;
wire SumY1, SumY2;
wire xorhS, hS_bar;
wire [1:0] hS;
wire hC;
ternary_half_adder_1digit hadder (
X,
Y,
hS,
hC
);
not (Cin_bar,... | 6.894655 |
module ternary_full_adder_4digit (
input Cin,
input [1:0] X3,
X2,
X1,
X0,
Y3,
Y2,
Y1,
Y0,
output [1:0] S3,
S2,
S1,
S0,
output Cout
);
wire Carry0, Carry1, Carry2;
ternary_full_adder_1digit adder0 (
Cin,
X0,
Y0,
S0,
Carry0
);
... | 6.894655 |
module ternary_consensus(a[1:0], b[1:0], out[1:0]);
input [1:0] a
input [1:0] b;
output [1:0] out;
// TODO: implementation
endmodule
| 6.795484 |
module ternary_operator_mux (
input i0,
input i1,
input sel,
output y
);
assign y = sel ? i1 : i0;
endmodule
| 7.473079 |
module ternary_operator_mux (
i0,
i1,
sel,
y
);
wire _0_;
wire _1_;
wire _2_;
wire _3_;
input i0;
wire i0;
input i1;
wire i1;
input sel;
wire sel;
output y;
wire y;
sky130_fd_sc_hd__mux2_1 _4_ (
.A0(_0_),
.A1(_1_),
.S (_2_),
.X (_3_)
);
assign _0_ = ... | 7.473079 |
module
// is not strictly necessary, but makes the
// grouping clear and unambiguous if you
// want to remove the pipeline registers.
module tern_node (clk,a,b,c,o);
parameter WIDTH = 8;
input clk;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input [WIDTH-1:0] c;
output [WIDTH+2-1:0] o;
reg [WIDTH+2-1:0] o;
always @(po... | 8.198795 |
module ternary_tb ();
reg [1:0] a;
wire [1:0] b;
test t (
a,
b
);
initial begin
$monitor("%d %d", a, b);
a = 2'b0;
#50 $stop;
end
always #10 a = a + 1;
endmodule
| 6.984029 |
module tessera_mem_wbif (
res,
clk,
wb_cyc_i,
wb_stb_i,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_dat_i,
wb_cab_i,
wb_dat_o,
wb_ack_o,
wb_err_o,
write_req,
write_byte,
write_address,
write_data,
write_ack,
read_req,
read_byte,
read_address,
read_... | 7.717731 |
module tessera_ram_tiny (
sys_wb_res,
sys_wb_clk,
wb_cyc_i,
wb_stb_i,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_dat_i,
wb_cab_i,
wb_dat_o,
wb_ack_o,
wb_err_o
);
// system
input sys_wb_res;
input sys_wb_clk;
// WishBone Slave
input wb_cyc_i;
input wb_stb_i;
input [31:0... | 7.372465 |
module tessera_sdram_wbif (
res,
clk,
wb_cyc_i,
wb_stb_i,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_dat_i,
wb_cab_i,
wb_dat_o,
wb_ack_o,
wb_err_o,
write_req,
write_byte,
write_address,
write_data,
write_ack,
read_req,
read_byte,
read_address,
rea... | 8.006947 |
module tessera_tic (
wb_rst,
wb_clk,
wb_cyc_o,
wb_adr_o,
wb_dat_i,
wb_dat_o,
wb_sel_o,
wb_ack_i,
wb_err_i,
wb_rty_i,
wb_we_o,
wb_stb_o,
wb_cab_o
);
input wb_rst;
input wb_clk;
output wb_cyc_o;
output [31:0] wb_adr_o;
input [31:0] wb_dat_i;
output [31:0] wb... | 7.178832 |
module tessera_vga_wbif (
res,
clk,
wb_cyc_i,
wb_stb_i,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_dat_i,
wb_cab_i,
wb_dat_o,
wb_ack_o,
wb_err_o,
enable,
base
);
input res;
input clk;
input wb_cyc_i;
input wb_stb_i;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
... | 7.32781 |
module test_jbimu;
// Inputs
reg clks;
reg clock;
reg reset;
reg start;
wire miso;
// Outputs
wire [15:0] roll;
wire [15:0] pitch;
wire [15:0] yaw;
wire [15:0] roll_rate;
wire [15:0] pitch_rate;
wire [15:0] yaw_rate;
wire [15:0] accel_x;
wire [15:0] accel_y;
wire [15:0] accel_z;
wire done;
wire mosi;
wire sck;
wire ss;... | 6.632599 |
module test_accumulation_cap (
input clk,
input reset, // async
output [`NUM_BITS-1:0] out
);
// clk_count for the current phase. 31 bits is faster than 24 bits. weird. ??? 36MHz v 32MHz
reg [31:0] clk_count = 0;
// destructure
reg [4-1:0] azmux;
reg [4-1:0] himux;
reg [4-1:0] himux2;
... | 7.187903 |
module ac97 (
ready,
command_address,
command_data,
command_valid,
left_data,
left_valid,
right_data,
right_valid,
left_in_data,
right_in_data,
ac97_sdata_out,
ac97_sdata_in,
ac97_synch,
ac97_bit_clock
);
output ready;
input [7:0] command_address;
input [15... | 7.075457 |
module squarewave (
clock,
ready,
pcm_data
);
input clock;
input ready;
output [19:0] pcm_data;
reg old_ready;
reg [6:0] index;
reg [19:0] pcm_data;
initial begin
old_ready <= 1'b0;
// synthesis attribute init of old_ready is "0";
index <= 7'h00;
// synthesis attribute init ... | 6.583527 |
module abro (
input clk,
input reset,
input a,
input b,
output z
);
parameter IDLE = 0, SA = 1, SB = 2, SAB = 3;
reg [1:0] cur_state, next_state;
// Output z depends only on the state SAB
// The output z is high when cur_state is SAB
// cur_state is reset to IDLE when reset is high. Ot... | 7.130853 |
module fft_audio (
clock_27mhz,
reset,
volume,
audio_in_data,
audio_out_data,
ready,
audio_reset_b,
ac97_sdata_out,
ac97_sdata_in,
ac97_synch,
ac97_bit_clock
);
input clock_27mhz;
input reset;
input [4:0] volume;
output [15:0] audio_in_data;
input [15:0] audio_out_... | 6.829235 |
module tone750hz (
clock,
ready,
pcm_data
);
input clock;
input ready;
output [19:0] pcm_data;
reg [ 8:0] index;
reg [19:0] pcm_data;
initial begin
// synthesis attribute init of old_ready is "0";
index <= 8'h00;
// synthesis attribute init of index is "00";
pcm_data <= 20'h000... | 6.600003 |
module xvga (
vclock,
hcount,
vcount,
hsync,
vsync,
blank
);
input vclock;
output [10:0] hcount;
output [9:0] vcount;
output vsync;
output hsync;
output blank;
reg hsync, vsync, hblank, vblank, blank;
reg [10:0] hcount; // pixel number on current line
reg [ 9:0] vcount; // l... | 6.964566 |
module process_audio (
clock_27mhz,
reset,
sel,
ready,
from_ac97_data,
haddr,
hdata,
hwe
);
input clock_27mhz;
input reset;
input [3:0] sel;
input ready;
input [15:0] from_ac97_data;
output [9:0] haddr, hdata;
output hwe;
wire signed [22:0] xk_re, xk_im;
wire [13:0] xk... | 6.74906 |
module test_keyboard;
reg clk;
reg reset;
reg ps2_clk;
reg ps2_data;
wire [15:0] scancode;
wire strobe;
keyboard keyboard(.clk(clk),
.reset(reset),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
.data(scancode),
.strobe(strobe));
task clockout;
inpu... | 6.531392 |
module tests ();
supply0 gnd;
supply1 vdd;
reg gate;
wire out;
mosfet_npn u0 (
.vdd (vdd),
.gate(gate),
.out (out)
);
initial begin
gate <= 0;
$monitor("NMOS, NPN -> gate: %0b, out: %0b (vdd: %0b)", gate, out, vdd);
#10 gate <= 1;
end
endmodule
| 7.016684 |
module tests ();
supply0 gnd;
supply1 vdd;
reg gate;
wire out;
mosfet_pnp u0 (
.vdd (vdd),
.gate(gate),
.out (out)
);
initial begin
gate <= 0;
$monitor("PMOS, PNP -> gate: %0b, out: %0b (vdd: %0b)", gate, out, vdd);
#10 gate <= 1;
end
endmodule
| 7.016684 |
module unit_x (
input [31:0] a,
b,
c,
output [31:0] x
);
assign x = (a & b) | c;
endmodule
| 7.77978 |
module unit_y (
input [31:0] a,
b,
c,
output [31:0] y
);
assign y = a & (b | c);
endmodule
| 8.058142 |
module Test1 (
input clock,
input reset,
input io_vec_set,
input [ 1:0] io_vec_idx,
input [15:0] io_vec_ary_0,
input [15:0] io_vec_ary_1,
input [15:0] io_vec_ary_2,
input [15:0] io_vec_ary_3,
output [15:0] io_vec_ary_out
);
wire [15:0] _GEN_1 = 2'h1 == ... | 6.682188 |
module Test13BitOut (
input [31:0] PCOut,
input [31:0] BranchTargetAddr,
input [31:0] PCIn,
input [31:0] rs1Read,
input [31:0] rs2Read,
input [31:0] regFileIn,
input [31:0] imm,
input [31:0] shiftLeftOut,
input [31:0] ALU2ndSrc,
input [31:0] ALUOut,
input [31:0] memoryOut,
... | 9.051347 |
module BCD_Decoder (
input [3:0] A,
//output reg [9:0] Y_L
output [9:0] Y_L
);
/* always @ (*)
case(A)
4'd0:Y_L=10'b11_1111_1110;
4'd1:Y_L=10'b11_1111_1101;
4'd2:Y_L=10'b11_1111_1011;
4'd3:Y_L=10'b11_1111_0111;
4'd4:Y_L=10'b11_1110_1111;
4'd5:Y_L=10'b11_1101_1111;
4'd6:Y_L=10'b11_1011_111... | 6.675526 |
module test19 (
input [ 7:0] i_a,
input [ 7:0] i_b,
output [15:0] o_y
);
assign o_y = i_a * i_b;
endmodule
| 7.249686 |
module test19 (
input signed [ 7:0] i_a,
input signed [ 7:0] i_b,
output signed [14:0] o_y
);
assign o_y = i_a * i_b;
endmodule
| 7.249686 |
module test19 (
input signed [ 7:0] i_a,
input [ 7:0] i_b,
output signed [15:0] o_y
);
/* wire signed [8:0] b_r;
assign b_r = {1'b0,i_b}; */
// assign o_y = i_a * b_r;
assign o_y = i_a * $signed({1'b0, i_b});
endmodule
| 7.249686 |
module bus_top #(
parameter N = 2
) (
input [8:0] inp[N-1:0],
output status,
output [7:0] out,
input rst
);
reg status;
wire [7:0] value = 1, cur, p = 8'b00000000;
assign value = 8'b11111111;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin
if (inp[i][8] == 1) begin
... | 6.904175 |
module test1_mips32;
reg clk1,clk2;
integer k;
pipe_MIPS32 mips(clk1,clk2);
initial
begin
clk1=0;clk1=0;
repeat(20)
begin
#5clk1=1 ; #5clk1=0; //2 phase clock
#5clk2=1 ; #5clk2=0;
end
end
initial
begin
for(k=0;k<=31;k=k+1)
mips.Reg[k]=k; //Load register file from values 0 to 31 for register R0 to... | 6.656412 |
module test1_showpic (
input CLK100MHZ,
input SW0, //display_ena
input SW1, //movement_ena
input BTNU, //reset
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS
);
wire [10:0] h_cnt;
... | 7.26657 |
module Test2 (
input clock,
input reset,
input [4:0] io_in_val,
output [3:0] io_out_head,
output [2:0] io_out_extractS,
output [2:0] io_out_extractI,
output [2:0] io_out_extractE
);
assign io_out_head = io_in_val[4:1]; // @[Test2.scala 38:32]
assign io_out_extractS = io_i... | 7.268316 |
module addroundkey (
state,
state_out,
key
);
input wire [127:0] key;
input wire [127:0] state;
output [127:0] state_out;
assign state_out = key ^ state;
endmodule
| 8.744472 |
module test20 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
genvar w, d;
for (d = 0; d < depth; d=d+1) begin
for (w = 0; w < width; w=w+1) begin
initial int[d][w] <= ~((d+w) % 2);
... | 6.99028 |
module test21 (
input signed [3:0] a,
b,
c,
output reg [3:0] max
);
always @(*) begin
if (a >= b && a >= c) max = a;
else if (b >= a && b >= c) max = b;
else if (c >= b && c >= a) max = c;
else max = max;
end
endmodule
| 6.682703 |
module DFF (
input clk,
input rst_n,
input i_D,
output reg o_Q,
output o_Qn
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
o_Q <= 1'b1;
end else begin
o_Q <= i_D;
end
end
assign o_Qn = ~o_Q;
endmodule
| 7.464833 |
module test21a #(parameter width=130, depth=4) (input clk, input [width-1:0] i, output q);
genvar d;
wire [depth:0] int;
assign int[0] = ^i[width-1:0];
generate
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1]));
end
endgenerat... | 6.916088 |
module test21b #(parameter width=130, depth=4) (input clk, input [width-1:0] i, input e, output q);
reg [depth-1:0] int;
genvar d;
for (d = 0; d < depth; d=d+1)
initial int[d] <= ~(d % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int <= ~^i[width-1:0];
assign q = int;... | 6.899926 |
module latch_ff (
input clk,
input enable,
input data,
input clr,
output latch_q,
output ff_q
);
LDCE #(
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
) LDCE_inst (
.Q (latch_q), // Data output
.CLR(clr), // Asynchronous clear/reset input
.D (data... | 6.981437 |
module test29 (
input clk,
rst_n,
data,
output reg flag_101
);
parameter ST0 = 4'b0001, ST1 = 4'b0010, ST2 = 4'b0100, ST3 = 4'b1000;
reg [3:0] c_st;
reg [3:0] n_st;
//FSM-1
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
c_st <= ST0;
end else begin
c_st <= n... | 7.886915 |
module Test2GuitarHero (
KEY,
LEDR,
CLOCK_50,
SW
);
input [3:0] KEY;
input CLOCK_50;
input [12:0] SW;
output [7:0] LEDR;
//PLACEBO FOR DATASELECTION COUNTER
wire [3:0] empty_data;
assign empty_data = 4'b0000;
//DEFAULT FOR NEVER ON WIRE
wire never_write;
assign never_write = 1'b0;
... | 7.636753 |
module keyexpansion (
keyInput,
keyNum,
keyOutput
);
input [127:0] keyInput;
input [3:0] keyNum;
output reg [127:0] keyOutput;
wire [31:0] stp1, stp2, Rcon;
wire [3:0] num;
rcon uut1 (
.r(num),
.rcon(Rcon)
);
subbyte uut2 (
.sbox_in (stp1),
.sbox_out(stp2)
);
a... | 7.303995 |
module t1 (N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15);
input N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11;
output N12,N13,N14,N15;
N16 = NAND(N1, N2)
N19 = NOR(N3, N16)
N21 = NAND(N4, N5)
N23 = NOR(N6, N7)
N26 = NAND(N7, N9)
N25 = NOR(N3, N8)
N18 = NAND(N19, N17)
N17 = NOR(N16, N21)
N22 = NOR(N21, N25)
N20 = NAND(N19... | 7.526928 |
module test2port (
address_a,
address_b,
clock,
q_a,
q_b);
input [15:0] address_a;
input [15:0] address_b;
input clock;
output [9:0] q_a;
output [9:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0... | 6.511903 |
module rcon (
input [3:0] r,
output reg [31:0] rcon
);
always @(*) begin
case (r)
4'h1: rcon = 32'h01000000;
4'h2: rcon = 32'h02000000;
4'h3: rcon = 32'h04000000;
4'h4: rcon = 32'h08000000;
4'h5: rcon = 32'h10000000;
4'h6: rcon = 32'h20000000;
4'h7: rcon = 32'h40... | 6.802543 |
module test2_mips32;
reg clk1,clk2;
integer k;
pipe_MIPS32 mips(clk1,clk2);
initial
begin
clk1=0;clk1=0;
repeat(20)
begin
#5clk1=1 ; #5clk1=0; //2 phase clock
#5clk2=1 ; #5clk2=0;
end
end
initial
begin
for(k=0;k<=31;k=k+1)
mips.Reg[k]=k; //Load register file from values 0 to 31 for register R0 to... | 6.627676 |
module: Test2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test2_sim;
// Inputs
reg clk;
reg [2:0] a;
reg [2:0] b;
// Outputs
wire [3:0] c;
// Instantiate the Unit Under... | 6.587093 |
module Test3 (
input clock,
input reset,
input [11:0] io_inp,
output [15:0] io_out_pad
);
assign io_out_pad = {{4'd0}, io_inp}; // @[Test3.scala 18:27]
endmodule
| 7.002654 |
module Unit_fd (
clk_in,
reset,
clk_out
); // Time Frequency Divider
input clk_in, reset;
output reg clk_out;
reg [31:0] count;
always @(posedge clk_in) begin
if (!reset) begin
count <= 32'd0;
clk_out <= 1'b0;
end else begin
if (count == `UnitTime) begin
count ... | 7.014406 |
module fd (
clk_in,
reset,
clk_out
); // Time Frequency Divider
input clk_in, reset;
output reg clk_out;
reg [31:0] count;
always @(posedge clk_in) begin
if (!reset) begin
count <= 32'd0;
clk_out <= 1'b0;
end else begin
if (count == `Time) begin
count <= 0;
... | 7.187406 |
module test30 (
input clk,
input rst_n,
input sel_x,
input [ 7:0] da_x,
input [ 7:0] da_y,
input [ 7:0] db_x,
input [ 7:0] db_y,
output reg [15:0] dout_x_y
);
wire [ 7:0] da;
wire [ 7:0] db;
wire [15:0] dout;
assign da = s... | 6.971441 |
module test32 #(
parameter WD = 4'd8, //数据位宽
parameter DP = 5'd16, //深度
parameter ADDR_WD = clogb2(DP) //地址位宽
) (
input i_en ,
input [ADDR_WD-1:0] i_addr ,
output [WD-1:0] o_data
);
reg [WD-1:0] buffer[DP-1:0];
integer i;
initial begin
for (i = 0; i < DP; i = i + 1) begi... | 7.2946 |
module spram #(
parameter WD = 8, //数据位宽
parameter AD = 4 //地址位宽
) (
input clk,
input cs_n,
input w_r_n,
input [AD-1:0] addr,
input [WD-1:0] din,
output reg [WD-1:0] dout
);
localparam DP = 1 << AD;
reg [WD-1:0] buffer[DP-1:0];
... | 8.813407 |
module single_port_ram (
input [7:0] data,
input [5:0] addr,
input we,
clk,
output [7:0] q
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Variable to hold the registered read address
reg [5:0] addr_reg;
always @(posedge clk) begin
// Write
if (we) ram[addr] <= data;
... | 8.023817 |
module sy_dpram #(
parameter WD = 8, //位宽
parameter DP = 16, //深度
parameter AD = clogb2(DP)
) (
input clk,
input cs_n,
input wr_n,
input rd_n,
input [WD-1:0] din_b, //B口写入
input [AD-1:0] addr_b,
... | 7.356674 |
module as_dpram #(
parameter WD = 8, //数据位宽
parameter AD = 4 //地址位宽
) (
input clk_a,
input rda_n,
input [AD-1:0] addr_a,
output reg [WD-1:0] dout_a,
input clk_b,
input wrb_n,
input [WD-1:0] din_b,
input [AD-1:0] addr_b,
... | 8.282806 |
module sy_ture_dpram #(
parameter WD = 8, //数据位宽
parameter AD = 4 //地址位宽
) (
input clk,
input cs_n,
input aw_r_n,
input [AD-1:0] addr_a,
input [WD-1:0] din_a,
output reg [WD-1:0] dout_a,
input bw_r_n,
input [AD-1:0] addr_b,
inpu... | 8.114928 |
module fir
#(
parameter DIN_WIDTH = 8 , //输入数据位宽
FIR_TAP = 4 , //滤波器阶数
COEF_WIDTH = 8 , //系数位宽
DOUT_WIDTH = 8 //输出数据位宽
)
(
input clk ,
input rst_n ,
input load_sw , ... | 8.024664 |
module TEST43SLAVE (
input clk,
input reset
);
integer tTMT4Main_V_0;
wire [31:0] ktop12;
reg [31:0] KiKiwi_old_pausemode_value;
wire [31:0] ktop10;
integer mpc10;
reg [1:0] xpc10nz;
always @(posedge clk) begin
//Start structure HPR test43.exe
if (reset) begin
KiKiwi_old_pausemode_va... | 7.055169 |
module reset_gen (
input clk,
input rst_async_n,
output rst_sync_n
);
reg rst_s1, rst_s2;
always @(posedge clk or negedge rst_async_n)
if (!rst_async_n) begin
rst_s1 <= 1'b0;
rst_s2 <= 1'b0;
end else begin
rst_s1 <= 1'b1;
rst_s2 <= rst_s1;
end
assign rst_sync_n ... | 7.242271 |
module cnt_ring (
input clk,
rst_n,
output [3:0] o_cnt
);
reg [3:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 4'b0001;
end else begin
cnt <= {cnt[0], cnt[3:1]};
end
end
assign o_cnt = cnt;
endmodule
| 7.462111 |
module debounce #(
parameter DELAY_TIME = 18'h3ffff
) (
input clk,
input rst_n,
input key_in,
output reg key_vld
);
localparam IDLE = 4'b0001, PRESS_DELAY = 4'b0010, WAIT_RELEASE = 4'b0100, RELEASE_DELA = 4'b1000;
reg [1:0] key_in_r;
wire key_press_edge;
wire key_release_edge;
... | 8.549926 |
module Test6 (
input clock,
input reset,
input [15:0] io_in_0,
input [15:0] io_in_1,
input [15:0] io_in_2,
input [ 4:0] io_addr,
output [15:0] io_out
);
wire [15:0] _GEN_1 = 2'h1 == io_addr[1:0] ? io_in_1 : io_in_0; // @[Test6.scala 17:10 Test6.scala 17:10]
assign io_... | 7.028449 |
module flip_flop_vl (
input d,
clk,
reset,
output reg q
);
always @(posedge clk or posedge reset) begin
if (reset == 1) q = 1'b0;
else q = d;
end
endmodule
| 6.918617 |
module RAM (
CLK,
nCS,
nWE,
ADDR,
DI,
DO
);
// Port definition
input CLK, nCS, nWE;
input [11:0] ADDR;
input [15:0] DI;
output [15:0] DO;
wire CLK, nCS, nWE;
wire [11:0] ADDR;
wire [15:0] DI;
reg [15:0] DO;
// Implementation
reg [15:0] mem [0:4095];
always @(posedg... | 6.625533 |
module test68 (
input clk_25mhz,
output [7:0] leds
);
// ===============================================================
// 68000 CPU
// ===============================================================
reg fx68_phi1 = 0;
wire fx68_phi2 = !fx68_phi1;
always @(posedge clk_25mhz) begin
fx68_phi1... | 7.035199 |
module test_dff_v (
clk,
d,
q
);
parameter g_count = 1;
input [g_count-1:0] d;
input clk;
output reg [g_count-1:0] q;
genvar i;
generate
for (i = 0; i <= g_count - 1; i = i + 1) begin : REG
always @(posedge clk) q[i] <= d[i];
end
endgenerate
endmodule
| 6.993199 |
module FullTB;
reg clk, ena, rst;
integer i;
integer cycles;
wire [31:0] alpha, k, error, model;
wire done;
reg [31:0] acf;
wire valid;
wire [3:0] m;
wire signed [31:0] quant_c;
wire q_valid;
Durbinator db (
.iClock (clk),
.iEnable(ena),
.iReset (rst),
.iACF(acf),
... | 6.790235 |
module TestADDA (
originalClock,
clockAD,
clockDA,
nCS,
SDATA,
nSYNC,
DIN,
led
);
input originalClock;
output nCS;
input SDATA;
output nSYNC;
output DIN;
output clockAD;
output clockDA;
output [7:0] led;
wire [7:0] tempLevel;
AD(
.clock(originalClock), .level(... | 7.039959 |
module of the EX stage of the pipeline.
`include "ALU_CONTROL.v"
module test ( ) ;
// Wire Ports
wire [ 2 : 0 ] select;
// Register Declarations
reg [ 1 : 0 ] alu_op ;
reg [ 5 : 0 ] funct ;
ALU_CONTROL alucontrol1 ( alu_op, funct, select ) ;
initial begin
alu_op = 2'b00 ;
funct = 6'b100000 ;
... | 7.294112 |
module and3gate (
output s,
input a,
input b,
input c
);
assign s = (a & b & c);
endmodule
| 8.641841 |
module testand3entgate;
// ---------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
and3gate AND1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
a = 0;
... | 7.188672 |
module testandgate;
reg [2:0] a, b;
wire [2:0] s;
// instancia
andgate AND1 (
s,
a,
b
);
// parte principal
initial begin
$display("Exemplo 04_01 - xxx yyy zzz - 999999");
$display("Test AND gate");
$display("\na & b = s\n");
a = 3'b000;
b = 3'b000;
#1 $display("... | 6.553783 |
module testando_cont_pc (
input clock,
output [31:0] PC
);
wire [31:0] PC_mais_1;
Program_Counter test_PC (
.clock(clock),
.PC_in(PC_mais_1),
.PC(PC),
.PC_mais_1(PC_mais_1)
);
endmodule
| 7.070834 |
module testAnythingProtocol
#( parameter TAP_FOLDER = "",
parameter TAP_FILE = "",
parameter MAX_STRING_LENGTH = 80 );
integer hTap; //File handle for tap file
integer hTemp; //File handle for temporary file
integer testCaseIdx = 0; //Current testcase index
reg[ 7: 0 ] character;
initial be... | 7.339826 |
module TestBench ();
localparam w = 16;
localparam n = 8;
localparam T = 200;
reg read_enable, wirte_enable, rst, clk;
reg [2:0] read_addr, write_addr;
wire [w-1:0] read_data, read_data_1;
reg [w-1:0] write_data;
MemoryRegisters #(w, n) RegistersTest (
read_enable,
wirte_enable,
read_d... | 7.747207 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg [15:0] duration;
reg finish;
reg [1:0] curstate;
reg ... | 8.489904 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg [15:0] duration;
reg finish;
reg [1:0] curstate;
reg ... | 8.489904 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish,
br,
wrong
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg finish;
reg [1:0] curstate;
reg [1:0]... | 8.489904 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg [7:0] error_num;
reg [15:0] duration;
reg finish;
re... | 8.489904 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg [7:0] error_num;
reg [15:0] duration;
reg finish;
re... | 8.489904 |
module TESTBED;
parameter WIDTH_DATA = 256, WIDTH_RESULT = 1;
//Connection wires
wire [ (WIDTH_DATA-1):0] data;
wire [(WIDTH_RESULT-1):0] result;
wire clk, rst_n;
wire in_valid, out_valid;
initial begin
`ifdef RTL
$fsdbDumpfile("CS_IP_Demo.fsdb");
$fsdbDumpvars(0, "+mda");
`endif
`ifdef GATE
... | 6.55282 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg [7:0] error_num;
reg [15:0] duration;
reg finish;
reg... | 8.489904 |
module TESTBED;
wire clk, rst_n, in_valid;
wire [1:0] init;
wire [1:0] in0, in1, in2, in3;
wire out_valid;
wire [1:0] out;
initial begin
`ifdef RTL
$fsdbDumpfile("SUBWAY.fsdb");
$fsdbDumpvars(0, "+mda");
`endif
`ifdef GATE
$sdf_annotate("SUBWAY_SYN.sdf", u_SUBWAY);
$fsdbDumpfile("SUB... | 6.764775 |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$d... | 6.640835 |
module testbench_CLA();
parameter bits = 8;
reg [bits-1:0] operand1;
reg [bits-1:0] operand2;
reg carryIn;
wire [bits-1:0] result;
wire carryOut;
wire p;
wire g;
integer i;
integer j;
integer k;
reg errorFlag = 0;
reg expectG;
reg expectP;
reg expectCOut;
reg [bits-1:0] expectResult;
initial begin
carryIn = 0... | 6.707837 |
module testbench_CLA_Array ();
localparam bits = 64;
reg [bits-1:0] a;
reg [bits-1:0] b;
reg cin;
wire [bits-1:0] result;
wire cout;
wire [bits:0] expectOutput;
reg errorFlag = 0;
integer i;
assign expectOutput = a + b + cin;
initial begin
a = 64'h1111111111111111;
b = 64'hffffffff... | 6.707837 |
module testbench_CLA_Array_32 ();
reg [31:0] a;
reg [31:0] b;
reg cin;
wire [31:0] result;
wire cout;
wire [32:0] expectOutput;
reg errorFlag = 0;
integer i;
assign expectOutput = a + b + cin;
initial begin
a = 32'h11111111;
b = 32'hffffffff;
cin = 1;
#10;
if ({cout, resu... | 6.707837 |
module testbench_CSA();
parameter bits = 4;
reg [bits-1:0] a;
reg [bits-1:0] b;
reg [bits-1:0] cin;
wire [bits-1:0] sum;
wire [bits-1:0] cout;
integer i;
integer j;
integer k;
integer errorFlag = 0;
reg [bits-1:0] expectSum;
reg [bits-1:0] expectCout;
initial begin
for(i = 0;i < (1<<bits-1); i = i+1) begin
... | 6.68794 |
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