code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module three_input_or_gate_a (
input a,
input b,
input c,
output d
);
assign d = a | b | c;
endmodule
| 6.687992 |
module three_input_or_gate_a_tb;
reg aa, bb, cc;
wire d;
three_input_or_gate_a u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(d)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initial begin
#1000 ... | 6.687992 |
module three_input_or_gate_tb;
reg aa, bb, cc;
wire x, y;
three_input_or_gate u_three_input_or_gate (
.a(aa),
.b(bb),
.c(cc),
.x(x),
.y(y)
);
initial aa = 0'b0;
initial bb = 0'b0;
initial cc = 0'b0;
always aa = #50 ~aa;
always bb = #100 ~bb;
always cc = #200 ~cc;
... | 6.687992 |
module three_ip_tb;
wire t_p, t_q, t_r;
reg [2:0] inTest;
gate dut (
.a(inTest[2]),
.b(inTest[1]),
.c(inTest[0]),
.p(t_p),
.q(t_q),
.r(t_r)
);
initial begin
$monitor(inTest[0], inTest[1], inTest[2], t_p, t_q, t_r);
inTest = 3'b000;
#60 inTest = 3'b001;
#6... | 7.120881 |
module: Three_parallel_CRC_retimed
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//Verilog testbench code for generator polynomial 1+y+y8+y9 with 3 level unfolding and retimed
module Thr... | 8.224695 |
module: Three_parallel_CRC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//Verilog testbench code for generator polynomial 1+y+y8+y9 with 3 level unfolding
module Three_parallel_CRC_test... | 8.224695 |
module Three_phase_sin (
clk,
out_p1,
out_p1_inv,
out_p2,
out_p2_inv,
out_p3,
out_p3_inv,
freq_adj
);
input clk;
input [3:0] freq_adj;
output out_p1, out_p1_inv, out_p2, out_p2_inv, out_p3, out_p3_inv;
wire [7:0] duty_cycle_1;
wire [7:0] duty_cycle_2;
wire [7:0] duty_cycle_3... | 7.248268 |
module clk_div (
clk,
clk_sel,
clk_out
);
input clk;
input [3:0] clk_sel;
output reg clk_out;
reg [15:0] counter;
reg [15:0] next_counter;
always @(posedge clk) begin
counter = next_counter;
end
always @* begin
next_counter = counter + 1;
case (clk_sel[3:0])
0: clk_out ... | 7.520262 |
module three_port_reg_file (
data,
load,
clk,
clr,
addrD,
addrA,
addrB,
a,
b
);
input [3:0] data;
input load, clk, clr;
input [2:0] addrD, addrA, addrB;
output [3:0] a, b;
reg [3:0] reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8;
wire[7:0] decoder; // reg로 선언하면 "error: c... | 6.786619 |
module main (
clk
);
input clk;
wire all_shared, is_sharedA, is_sharedB, is_sharedC;
wire ND_inA, ND_inB, ND_inC, ndA, ndB, ndC;
wire master_outA, master_outB, master_outC;
wire master_inA, master_inB, master_inC;
wire inv_outA, inv_outB, inv_outC, invalidate;
wire mem_served;
wire info_availA, info... | 7.779865 |
module main (
clk
);
input clk;
wire all_shared, is_sharedA, is_sharedB, is_sharedC;
wire ND_inA, ND_inB, ND_inC, ndA, ndB, ndC;
wire master_outA, master_outB, master_outC;
wire master_inA, master_inB, master_inC;
wire inv_outA, inv_outB, inv_outC, invalidate;
wire mem_served;
wire info_availA, info... | 7.779865 |
module three_stage_mult (
input [15:0] a,
input [15:0] b,
output [31:0] out,
input clk
);
logic [31:0] register;
logic [31:0] register2;
logic [31:0] register3;
always @(posedge clk) begin
register <= a * b;
register2 <= register;
register3 <= register2;
end
assign out = regis... | 7.099054 |
module three_state_gates (
input iA,
input iEna,
output oTri
);
assign oTri = (iEna == 1) ? iA : 'bz;
endmodule
| 8.00834 |
module three_state_gates_tb;
reg iA;
reg iEna;
wire oTristate;
three_state_gates uut (
.iA (iA),
.iEna(iEna),
.oTri(oTriState)
);
initial begin
iA = 0;
#40 iA = 1;
#40 iA = 0;
#40 iA = 1;
end
initial begin
iEna = 1;
#20 iEna = 0;
#40 iEna = 1;
#40 iEn... | 8.00834 |
module three_to_eight_decoder (
input [2:0] in,
output reg [7:0] out
);
always @(in) begin
case (in)
0: out <= 8'd0;
1: out <= 8'd1;
2: out <= 8'd2;
3: out <= 8'd4;
4: out <= 8'd8;
5: out <= 8'd16;
6: out <= 8'd32;
7: out <= 8'd64;
endcase
end
end... | 6.539167 |
module three_to_vote (
sw3,
agreement
);
input [2:0] sw3;
output reg agreement;
wire result;
wire w1, w2, w3;
always @(sw3) begin
agreement = ~result;
end
gate_1 u1 (
.a (sw3[0]),
.b (sw3[1]),
.out(w1)
);
gate_1 u2 (
.a (sw3[0]),
.b (sw3[2]),
.out(w... | 6.920259 |
module gate_1 (
out,
a,
b
);
input a, b;
output out;
assign out = ~(a & b);
endmodule
| 8.208518 |
module gate_2 (
out,
a,
b,
c
);
input a, b, c;
output out;
assign out = ~(a & b & c);
endmodule
| 8.775338 |
module three_two_comp (
data,
sum
);
input [2:0] data;
output [1:0] sum;
reg [1:0] sum;
always @(data) begin
case (data)
0: sum = 0;
1: sum = 1;
2: sum = 1;
3: sum = 2;
4: sum = 1;
5: sum = 2;
6: sum = 2;
7: sum = 3;
default: sum = 0;
endc... | 6.900058 |
module three_wire_controller ( // Host Side
iCLK,
iRST,
iDATA,
iSTR,
oACK,
oRDY,
oCLK,
// Serial Side
oSCEN,
SDA,
oSCLK
);
// Host Side
input iCLK;
input iRST;
input iSTR;
input [15:0] iDATA;
output oACK;
output oRDY;
output oCLK;
// Serial Side
output oS... | 9.574951 |
module threshold #(
parameter THRESHOLD = 35
) (
input signed [15:0] data_x,
output is_over_threshold
);
wire is_over_threshold = (data_x > THRESHOLD) | (data_x < -THRESHOLD);
endmodule
| 6.69762 |
module threshold2_mul_mulbW_DSP48_0 (
a,
b,
p
);
input [8 - 1 : 0] a;
input [14 - 1 : 0] b;
output [21 - 1 : 0] p;
assign p = $unsigned(a) * $unsigned(b);
endmodule
| 6.669315 |
module threshold2_mul_mulbW (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
t... | 6.669315 |
module threshold2_mul_murcU_DSP48_5 (
a,
b,
p
);
input [20 - 1 : 0] a;
input [8 - 1 : 0] b;
output [28 - 1 : 0] p;
assign p = $unsigned(a) * $unsigned(b);
endmodule
| 6.669315 |
module threshold2_mul_murcU (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
t... | 6.669315 |
module threshold2_mux_32kbM #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] di... | 6.669315 |
module threshold2_udiv_2pcA_div_u #(
parameter in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
) (
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
output wire... | 6.687156 |
module threshold2_udiv_2pcA_div #(
parameter in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
) (
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
output reg [out_WI... | 6.687156 |
module threshold2_udiv_2pcA (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] din0;
inp... | 6.687156 |
module Testbench_4 ();
reg Go_s;
wire [(`A_WIDTH-1):0] P_Addr_s, B_Addr_s;
wire [(`D_WIDTH-1):0] P_Data_s, P_Di_s, B_Data_s;
wire [(`V_WIDTH-1):0] T_Out_s;
wire I_RW_s, I_En_s, O_RW_s, O_En_s, Done_s;
reg Clk_s, Rst_t, Rst_p, Rst_b;
parameter ClkPeriod = 20;
Tresholding_4 CompToTest (
Go_s,
... | 6.709933 |
module Testbench ();
reg Go_s;
wire [(`A_WIDTH-1):0] P_Addr_s, B_Addr_s;
wire [(`D_WIDTH-1):0] P_Data_s, P_Di_s, B_Data_s;
wire [(`V_WIDTH-1):0] T_Out_s;
wire I_RW_s, I_En_s, O_RW_s, O_En_s, Done_s;
reg Clk_s, Rst_t, Rst_p, Rst_b;
parameter ClkPeriod = 20;
Tresholding CompToTest (
Go_s,
P_... | 6.722871 |
module including Tresholding and Dual-Port SRAM
// ***********************************************************************
`timescale 1 ns/1 ns
`define A_WIDTH 17
`define D_WIDTH 8
module Thresholding_Top(Go_t, Done_t, Rst_Core,
MP_di31, MP_di8, MP_do31, MP_Addr15, MP_enb, MP_web, Rst_P,
... | 6.855655 |
module ThresholdUnit #(
parameter INTEGER_WIDTH = 16,
parameter DATA_WIDTH_FRAC = 32,
parameter DATA_WIDTH = INTEGER_WIDTH + DATA_WIDTH_FRAC
) (
input wire signed [(DATA_WIDTH-1):0] Vth,
input wire signed [(DATA_WIDTH-1):0] Vmem,
input wire signed [(INTEGER_WIDTH-1):0] Vreset,
output wire ... | 6.557893 |
module threshold_17x17 (
//Input
input iClk,
input iReset_n,
input iInput_ready,
input [12:0] iPosition,
input [31:0] iMax_val,
input iFinish,
input [31:0] iData_from_OM,
//Output
output reg [12:0] oAddr_OM,
output reg [12:0] oPosition,
output reg oOutput... | 7.365664 |
module threshold_19x19 (
//Input
input iClk,
input iReset_n,
input iInput_ready,
input [12:0] iPosition,
input [31:0] iMax_val,
input iFinish,
input [31:0] iData_from_OM,
//Output
output reg [12:0] oAddr_OM,
output reg [12:0] oPosition,
output reg oOutput... | 7.23229 |
module threshold_23x23 (
//Input
input iClk,
input iReset_n,
input iInput_ready,
input [12:0] iPosition,
input [31:0] iMax_val,
input iFinish,
input [31:0] iData_from_OM,
//Output
output reg [12:0] oAddr_OM,
output reg [12:0] oPosition,
output reg oOutput... | 7.302283 |
module Threshold_Adj (
//global clock
input clk, //100MHz
input rst_n, //global reset
//user interface
input key_flag, //key down flag
input [1:0] key_value, //key control data
output reg [7:0] Threshold //Threshold Grade output
);
reg [3:0] Threshold_Grade;
always @(posedge c... | 6.532472 |
module Threshold_Binarization (
input CLK100MHZ, //input clock
input [7:0] next_px, //input px
input btn_reset, //reset line
input ena, //reset line
output [7:0] output_px //output px (255 represents 1 and 0 represents 0)
);
parameter [7:0] THRESHOLD = 8'd78; //threshold value
assign ... | 6.809804 |
module threshold_binary_0 #(
parameter DW = 24,
parameter Y_TH = 225,
parameter Y_TL = 60,
parameter CB_TH = 141,
parameter CB_TL = 111,
parameter CR_TH = 139,
parameter CR_TL = 98
) (
input pixelclk,
input reset_n,
input [DW-1:0] i_ycbcr,
input [DW-1... | 6.665487 |
module threshold_dac #(
parameter signalwidth = 16
) (
input clk,
input reset_n,
input [signalwidth-1:0] d,
output q
);
reg q_reg;
assign q = q_reg;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
q_reg <= 1'b0;
end else begin
q_reg <= d[signalwidth-1];... | 6.772579 |
module threshold_detect (
input clk,
input rst,
input [12:0] length,
output reg [11:0] result
);
parameter threshold = 140;
always @(posedge clk) begin
if (rst) result <= 0;
else result <= (length >= threshold ? {12{1'b1}} : 0);
end
endmodule
| 6.576015 |
module threshold_scaled #(
parameter WIDTH = 32,
SCALAR = 131072
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i0_tdata,
input i0_tlast,
input i0_tvalid,
output i0_tready,
input [WIDTH-1:0] i1_tdata,
input i1_tlast,
input i1_tvalid,
output i1_tready,
... | 8.051676 |
module thunder_ams_analog (
hf_osc_out,
iledir_out,
lf_osc_out,
vgnda,
vsupa,
hf_on,
hf_trim,
iledir_on,
iledir_trim,
lf_on,
lf_trim,
ref_on,
hf_therm_trim,
lf_therm_trim,
hf_trim_msb,
lf_trim_msb
);
output hf_osc_out;
input ref_on;
input [3:0] lf_t... | 7.492537 |
module thymesisflow_llc_ingress_driver (
input clock // Clock - samples & launches data on rising edge
, input reset_n // Active Low
// 32B incoming data Interface
, input [255:0] driver_in_tdata
, input driver_in_tvalid
, output driver_in_tready
// 32B AXI-STREAM... | 7.072743 |
module thymesisflow_rr_arbiter #(
parameter SIZE = 2
) (
input clock // Clock - samples & launches data on rising edge
, input reset_n // Active Low
// fifo_in AXI-STREAM
, input [SIZE-1:0] request_vector
, input request_nxt
, output [SIZE-1:0] selected
);
reg [SIZ... | 7.072743 |
module: dflop
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_dflop;
// Inputs
reg rst;
reg clk;
reg din;
// Outputs
wire qout;
wire qbout;
// Instantiate the Unit Unde... | 7.473416 |
module
// Checks the pixel number against a stretched and possibly duplicated version of the
// object.
module objPixelOn(pixelNum, objPos, objSize, objMask, pixelOn);
input [7:0] pixelNum, objPos, objMask;
input [2:0] objSize;
output pixelOn;
wire [7:0] objIndex;
wire [8:0] objByteIndex;
wire ... | 6.774774 |
module
// Checks the pixel number against a stretched and possibly duplicated version of the
// object. See below for detailed functionality...
module objPlayersPixelOn(pixelNum, objPos, objSize, objMask, plReset, pixelOn);
input [7:0] pixelNum, objPos, objMask;
input [2:0] objSize;
input plReset;
output ... | 6.774774 |
module TickCounter #(
parameter CW = 24
) // internal counter width
(
// External time interface(also associated with the external input/output port)
output TICK_OUT,
input TICK_IN,
output [CW-1:0] COUNT,
output [ 5:1] time_o,
output [ 1:0] ctrl_flg_o,
input [ ... | 6.870199 |
module ticker (
input wire clk_bus,
input wire rst_n,
input wire clk_tick, //10MHz clock in
input wire rst_tick_n,
//bus
output wire [31:0] bus_data_o,
input wire [ 7:0] bus_address,
input wire [31:0] bus_data_i,
input wire bus_read,
input wire bus_write
)... | 7.411879 |
module TestBench;
reg Clock, Clear, Ten, Twenty;
wire Ready, Dispense, Return, Bill;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
parameter CLOCK_CYCLE = 10;
parameter CLOCK_WIDTH = CLOCK_CYCLE / 2;
parameter IDLE_CLOCKS = 2;
// instantiate an object of type TicketMachine to test
TicketMachine TF... | 6.639035 |
module BaudTickGen (
input clk,
enable,
output tick
);
parameter ClkFrequency = 50000000; // 50 MHz
parameter Baud = 9600;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) log2 = log2 + 1;
end
endfunction
localparam AccW... | 7.463142 |
module tick_gen (
input clk,
input reset_n,
input [2:0] state,
input [2:0] grid_state,
input input_buffer_empty,
input forward_north_local_buffer_empty_all,
input complete,
output tick
);
localparam [1:0] IDLE = 2'b00, TICK1 = 2'b01, TICK2 = 2... | 7.877713 |
module stimulus();
// reg CLK,RESET;
// wire TICK;
// tick_generator #(.tick_time(32'd5),.frequency(32'd1))
// t1(
// .clk(CLK),
// .tick(TICK),
// .reset(RESET)
// );
// initial begin
// $dumpfile("simulation.vcd");
// $dumpvars(0,
// CLK,
// TICK,
// RESET
// );
// end
// ... | 6.85176 |
module: TicTacToe
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tictactoe_test;
// Inputs
reg clk;
reg upButton;
reg downButton;
reg leftButton;
reg rightButton;
reg center... | 7.700046 |
module TicTacToe_to_VGA (
input [8:0] x_positions,
o_positions,
next_position,
input [7:0] win_line,
input reset,
CLOCK_50,
output VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK,
VGA_SYNC,
output [7:0] VGA_R,
VGA_G,
VGA_B
);
wire raster_valid, shader_ready, shader_valid, f... | 6.536328 |
module
module tictactoe(
input clock, // clock of the game
input reset, // reset button to reset the game
input play, // play button to enable player to play
input pc, // pc button to enable computer to play
input [3:0] computer_position,player_position,
// positions to play
o... | 7.38656 |
module position_registers (
input clock, // clock of the game
input reset, // reset the game
input illegal_move, // disable writing when an illegal move is detected
input [8:0] PC_en, // Computer enable signals
input [8:0] PL_en, // Player enable signals
output reg [1:0] pos1,
pos2... | 6.859691 |
module fsm_controller (
input clock, // clock of the circuit
input reset, // reset
play, // player plays
pc, // computer plays
illegal_move, // illegal move detected
no_space, // no_space detected
win, // winner detected
output reg computer_play, // enable computer to play... | 7.681256 |
module position_decoder (
input [3:0] in,
input enable,
output wire [15:0] out_en
);
reg [15:0] temp1;
assign out_en = (enable == 1'b1) ? temp1 : 16'd0;
always @(*) begin
case (in)
4'd0: temp1 <= 16'b0000000000000001;
4'd1: temp1 <= 16'b0000000000000010;
4'd2: temp1 <= 16'b000000... | 7.76015 |
module tictactoe_tb;
// Inputs
reg clock;
reg reset;
reg play;
reg pc;
reg [3:0] computer_position;
reg [3:0] player_position;
// Outputs
wire [1:0] pos_led1;
wire [1:0] pos_led2;
wire [1:0] pos_led3;
wire [1:0] pos_led4;
wire [1:0] pos_led5;
wire [1:0] pos_led6;
wire [1:0] pos_led7;
wi... | 7.223526 |
module tb_tic_tac_toe;
// Inputs
reg clock;
reg reset;
reg play;
reg pc;
reg [3:0] computer_position;
reg [3:0] player_position;
// Outputs
wire [1:0] pos_led1;
wire [1:0] pos_led2;
wire [1:0] pos_led3;
wire [1:0] pos_led4;
wire [1:0] pos_led5;
wire [1:0] pos_led6;
wire [1:0] pos_led7;
... | 6.721339 |
module tic_tac_toe_top (
input reset,
input clk,
output [3:0] DISP_EN,
output [7:0] SEGMENTS,
output [4:1] COL,
input [4:1] ROW
);
wire [3:0] zz;
wire reset2;
wire pp;
wire last_player;
submission submit_move (
.last_player(last_player),
.reset(reset),
.x(COL),
... | 7.482532 |
module tid_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TID_WIDTH = 1,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TDATA_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TID_WIDTH = 32
) (
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_W... | 6.966715 |
module tid_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TID_WIDTH = 1,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TDATA_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TID_WIDTH = 32
) (
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_W... | 6.966715 |
module tiempodemuestreo
//Declaracion de senales de entrada y salida
(
input wire Clck_in,
enable,
input wire reset_Clock,
output reg Clock_out
);
//Declaracion de senales utilizadas dentro del modulo
reg [18:0] contador;
always @(posedge Clck_in,posedge reset_Clock) //Lista sensitiva, resp... | 6.92659 |
module tier2_control (
clk,
rst,
buffer_all_over,
codestream_generate_start,
cal_truncation_point_start,
cal_truncation_point_over,
codestream_generate_over,
rst_syn
);
input clk;
input rst;
input rst_syn;
input buffer_all_over;
input cal_truncation_point_over;
input codest... | 7.306225 |
module tier2_ram (
rd_clk,
laddr_rd,
laddr_wr,
output_to_ram,
lram_write_en,
lram_read_en,
ldata_ram,
rst_syn
);
parameter ADDR_WIDTH = 14, WORD_WIDTH = 18;
input rd_clk;
input [ADDR_WIDTH-1:0] laddr_rd;
input [ADDR_WIDTH-1:0] laddr_wr;
input [WORD_WIDTH-1:0] output_to_ram;
... | 7.230298 |
module tb ();
parameter FRAME_WIDTH = 112;
parameter FRAME_HEIGHT = 48;
parameter SIM_FRAMES = 2;
reg rstn;
reg clk;
reg ee_clk;
wire rstn_ee = rstn;
initial begin
rstn = `RESET_ACTIVE;
#(`RESET_DELAY);
$display("T%d rstn done#############################", $time);
rstn = `RESET_IDL... | 7.147559 |
module tiger_reset_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RUL... | 7.277505 |
module tiger_alu (
input signed [31:0] srca,
srcb, // 2 operands
input [ 4:0] alucontrol, // What function to perform
output [31:0] aluout // Result of the function
);
wire unsigned [31:0] srcau = srca;
wire unsigned [31:0] srcbu = srcb;
assign aluout = alucontrol == `ALU... | 6.881237 |
module contains the state machine to control processor for accessing components over Avalon (non-memory related)
module tiger_avalon (
input clk,
input reset,
input [31:0] memaddress,
input memread,
input memwrite,
input [31:0] memwritedata,
input mem8,
input mem16,
output avalon_stall,
output reg [31:0]av... | 7.358377 |
module contains the state machine to control processor for accessing components over Avalon (non-memory related)
module tiger_avalon_im (
input clk,
input reset,
input [31:0] memaddress,
input memread,
input memwrite,
input [31:0] memwritedata,
input mem8,
input mem16,
output avalon_stall,
output [31:0]avm... | 7.358377 |
module tiger_branch (
input clk, // clock signal
input reset, // reset signal
input stall, // stall signal
input exception, // interrupt request signal
input [31:0] instr, // current instruction
input [`CONTROL_WIDTH] control, // control signals
input [31:0] rs, // first operand
... | 7.773101 |
module tiger_ff (
input [4:0] regnum, // register number that we are writing to
writereg1, // register number the execute unit wishes to write to
writereg2, // register number the MWB unit wishes to write to
input writeregen1, // enable WB for the execute unit
writeregen2, // enable WB for the ... | 8.218401 |
module tiger_ff_compare (
input [4:0] regnum, // the register number we are writing to
input [4:0] writereg, // the register number we wish to write to
input writeregen, // write-enable signal
output en // output indicating if the write is enabled, and the register that is being
// written to is... | 7.008329 |
module tiger_icache_av_1port (
input clk,
input reset_n,
input [29:0] avs_icache_slave_address,
input avs_icache_slave_read,
output [31:0] avs_icache_slave_readdata,
output avs_icache_slave_readdatavalid,
output avs_icache_slave_waitrequest,
input [ `SDRAM_W... | 6.945937 |
module tiger_icache_memory (
address,
clken,
clock,
data,
wren,
q
);
input [8:0] address;
input clken;
input clock;
input [147:0] data;
input wren;
output [147:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QI... | 6.945937 |
module tiger_icache_mux_param (
Z,
SEL,
D
);
parameter N = 8; //number of bits wide
parameter M = 4; //number of inputs
parameter S = 2; //number of select lines
parameter W = M * N;
`define DTOTAL W-1:0
`define DWIDTH N-1:0
`define SELW S-1:0
`define WORDS M-1:0
input [`DTOTAL] D;
... | 6.945937 |
module tiger_memoryaccess (
input clk, // clock signal
input reset,
input clear,
input stall,
input [31:0] instr, // current instruction
input [`CONTROL_WIDTH] control, // control signals
input [31:0] executeout, // output of the execute stage
input [31:0] branchout,
outp... | 7.597911 |
module tiger_round (
input i_clk,
input [63:0] i_ain,
input [63:0] i_bin,
input [63:0] i_cin,
input [63:0] i_xin,
input [3:0] i_mul,
output [63:0] o_aout,
output [63:0] o_bout,
output [63:0] o_cout
);
localparam DLY = 1;
wire [63:0] s_a, s_b, s_c;
reg [63:0] r_c;
reg [63:0]... | 6.723734 |
module tiger_shifter (
input [31:0] src, // source data
input [4:0] amt, // number of bits to shift by
input dir, // direction to shift (0 = left; 1 = right)
input alusigned, // signed shift? 0 = unsigned; 1 = signed
output [31:0] shifted // output
);
// fill bit for right shifts
wire fill... | 7.133542 |
module tiger_wrapper (
input CLOCK_27,
/*
output [17:0] LEDR,
output [8:0] LEDG,
*/
/*
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
*/
output [11:0] DRAM_ADDR,
output DRAM_BA_0,
... | 6.686357 |
module tiger_writeback (
input clk, // clock signal
input [31:0] instr, // current instruction
input [`CONTROL_WIDTH] control, // control signals
input [31:0] branchout, // the branch address to save if we are doing a link operation
input [31:0] MAOut, // result from the memory access stage
... | 7.303956 |
module tiktaktoe (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
HEX0,
HEX1,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYN... | 7.692648 |
module rate_counter (
clock,
reset_n,
enable,
q
);
input clock;
input reset_n;
input enable;
output reg [1:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) q <= 2'b11;
else if (enable == 1'b1) begin
if (q == 2'b00) q <= 2'b11;
else q <= q - 1'b1;
end
end
endm... | 6.605756 |
module rate_counter1 (
clock,
reset_n,
enable,
q
);
input clock;
input reset_n;
input enable;
output reg [4:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) q <= 5'b10000;
else if (enable == 1'b1) begin
if (q == 5'b00000) q <= 5'b10000;
else q <= q - 1'b1;
end
... | 7.198693 |
module control (
select_btn,
reset_n,
clock,
enable,
player
);
input select_btn, reset_n, clock;
output reg enable;
output reg [1:0] player;
reg [2:0] current_state, next_state;
wire clock_1;
rate_counter1 m1 (
clock,
reset_n,
1'b1,
q
);
assign clock_1 = (q ... | 7.715617 |
module hex_decoder (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b111_1111; // displays nothing
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b000_1100; // display '... | 7.584821 |
module tilde (
input [31:0] irq,
mask,
output reg [31:0] wrdata,
output reg zero,
lognot
);
reg [1023:0] arg;
assign wrdata = irq & ~mask;
assign zero = !mask;
assign lognot = !$value$plusargs("lognot=%d", arg);
endmodule
| 6.57178 |
module CrossBarCell (
input [63:0] io_fw_left,
input [63:0] io_fw_top,
output [63:0] io_fw_bottom,
output [63:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitchNew.scala 15:17 CrossBarSwitchNew.scala 16:18 CrossBarSwitchNew.scala 18... | 7.603405 |
module RegMux (
input clock,
input [63:0] io_in,
output [63:0] io_out,
input io_sel
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [63:0] reg_; // @[RegMux.scala 11:16]
wire [63:0] _GEN_0 = io_sel ? reg_ : io_in; // @[RegMux.scala 15:32 RegMux.... | 6.643954 |
module iob_2p_assim_mem_tiled #(
parameter DATA_W_A = 32, // port A data width
parameter DATA_W_B = 16, // port B data width
parameter N_WORDS = 8192, // number of words (each word has 'DATA_W/8' bytes)
parameter ADDR_W_A = $clog2(N_WORDS * DATA_W_A / 8), // port A address width
parameter ADDR_W... | 6.69528 |
module decN #(
parameter N_OUTPUTS = 16
) (
input [$clog2(N_OUTPUTS)-1:0] dec_in,
output reg [N_OUTPUTS-1:0] dec_out
);
always @* begin
dec_out = 0;
dec_out[dec_in] = 1'b1;
end
endmodule
| 6.877415 |
module muxN #(
parameter N_INPUTS = 4, // number of inputs
parameter INPUT_W = 8, // input bit width
parameter S = $clog2(N_INPUTS), // number of select lines
parameter W = N_INPUTS * INPUT_W // total data width
) (
// Inputs
input [INPUT_W-1:0] data_in[N_INPUTS-1:0], // input port
inpu... | 8.176797 |
module tiledBcdCounter (
output [DIGITS*4-1:0] num,
output cout,
output bout,
input [DIGITS-1:0] ups,
input [DIGITS-1:0] downs,
input set9,
input set0,
input clock
);
parameter DIGITS = 4;
wire [DIGITS:0] cin, bin;
assign cin[0] = 0;
assign bin[0] = 0;
assign cout = cin[DIG... | 6.893296 |
module iob_2p_assim_mem_tiled_tb;
// Inputs
reg clk;
reg w_en;
reg r_en;
reg [`W_DATA-1:0] data_in;
reg [`W_ADDR-1:0] w_addr;
reg [`R_ADDR-1:0] r_addr;
// Outputs
wire [`R_DATA-1:0] data_out;
integer i, seq_ini;
integer test, base_block;
parameter clk_per = 10; // clk period = 10 timeticks
... | 6.69528 |
module: TILEGEN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// License: https://www.apache.org/licenses/LICENSE-2.0
//
////////////////////////////////////////////////////////////////////////////////
`include "../roms/rthunder.vh"
module tilegen_dual_tb
(
//... | 7.238032 |
module TileMap (
input wire clk,
input wire reset_n,
input wire [5:0] i_tilemap_x_idx,
input wire [5:0] i_tilemap_y_idx,
output reg [7:0] o_tilemap_texture_idx,
input wire [31:0] i_wdata,
input wire i_wea,
input wire [3:0] i_wselect,
input wire [26:0] i_waddr
);
wire [3:0] sel... | 7.238453 |
module tilemem #(
parameter ZOOM = 0
) (
input wire clk,
input wire [ 25:0] RGBStr_i,
output reg [`FONT_WIDTH-1:0] char_code
);
localparam cols = 80 / 2 ** ZOOM;
localparam rows = 60 / 2 ** ZOOM;
wire [9:0] px_x, px_y;
assign px_x = RGBStr_i[`XC];
assign px_y =... | 7.592803 |
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