code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module toe_tx_sar_table_tx_table_cong_window_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWid... | 7.363764 |
module toe_tx_sar_table_tx_table_count_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_styl... | 7.363764 |
module toe_tx_sar_table_tx_table_count_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [... | 7.363764 |
module toe_tx_sar_table_tx_table_not_ackd_V_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0]... | 7.363764 |
module toe_tx_sar_table_tx_table_not_ackd_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
... | 7.363764 |
module toe_tx_sar_table_tx_table_recv_window_V_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce... | 7.363764 |
module toe_tx_sar_table_tx_table_recv_window_V (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
inp... | 7.363764 |
module toe_tx_sar_table_tx_table_slowstart_threshold_V_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] a... | 7.363764 |
module toe_tx_sar_table_tx_table_slowstart_threshold_V (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address... | 7.363764 |
module DRAM_read (
// global signals
clk,
rst_n,
// axi read address channel
araddr_m_inf, //master
arlen_m_inf, //master
arvalid_m_inf, //master
arready_m_inf, //slave
// axi read data channel
rdata_m_inf, //slave
rlast_m_inf, //slave
rvalid_m_inf, //slave
... | 6.928386 |
module WINDOW_MET_5 (
// global signals
clk,
rst_n,
// input signals
in_valid,
in_data,
curr_mode,
// output signals
out_valid,
out_dist
);
//================================================================
// Parameter and Integer
//=====================... | 7.860252 |
module tof1021 (
input clk,
input rst,
input rx,
output tx,
output [7:0] seg0,
output [7:0] seg1,
output [7:0] seg2,
output [7:0] seg3,
output [7:0] seg4,
output [7:0] seg5
);
parameter clk_fre = 50_000_000;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire rx_sig;
wire tx... | 6.517097 |
module toffoli_gate (
input a,
b,
c,
output p,
q,
r
);
assign p = a;
assign q = b;
assign r = (a & b) ^ c;
endmodule
| 7.415387 |
module GateToFloat (
input [3:0] _D,
output [3:0] F,
output [1:0] P
);
wire high, low;
power U0 (
high,
low
);
wire [2:0] _P;
wire [3:0] D;
not (D[0], _D[0]);
not (D[1], _D[1]);
not (D[2], _D[2]);
not (D[3], _D[3]);
not (P[0], _P[0]);
not (P[1], _P[1]);
Gate148 U1 (
... | 7.118585 |
module DRAM_read (
// global signals
clk,
rst_n,
// axi read address channel
araddr_m_inf, //master
arlen_m_inf, //master
arvalid_m_inf, //master
arready_m_inf, //slave
// axi read data channel
rdata_m_inf, //slave
rlast_m_inf, //slave
rvalid_m_inf, //slave
... | 6.928386 |
module Together (
output wire [25:0] avm_node_address,
output wire avm_node_read,
input wire [15:0] avm_node_readdata,
input wire avm_node_readdatavalid,
output wire avm_node_write,
output wire [15:0] avm_node_writedata,
output wire [5:0] avm_node_burstcount,
input wire avm_node_waitrequ... | 6.863846 |
module toggle #(
parameter TON_us = 50,
parameter TOFF_us = 50,
parameter CLK_FREQ_MHz = 100
) (
input wire clk,
output reg toggle_OUT
);
reg [31:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
if (counter == (TON_us) * CLK_FREQ_MHz) begin
toggle_OUT = 1'b0;... | 7.469767 |
module toggle3pos (
input [1:0] pkgpin, // raw pin input
output reg [1:0] out
);
always @(*)
case (pkgpin)
2'b00: out = 2'b11; // can't happen
2'b01: out = 2'b00; // top
2'b10: out = 2'b10; // bottom
2'b11: out = 2'b01; // center
endcase
endmodule
| 7.559138 |
module ToggleLight #(
parameter integer CLAPS_WIDTH = 16,
parameter integer TOGLITE_ON_VAL = 2,
parameter integer TOGLITE_OFF_VAL = 3
) (
input wire clock,
input wire [CLAPS_WIDTH-1:0] claps_data,
input wire claps_valid,
output reg claps_ready = 0,
output reg toglite_state = 0
);
reg ... | 7.390661 |
module toggleReg (
q,
d,
clk,
en,
clr
);
input d, clk, en, clr;
output q;
wire w1, w2, w3, w4, w5;
not notty (w1, d);
not notty2 (w3, q);
and and1 (w2, d, w3);
and and2 (w4, w1, q);
or orgate (w5, w2, w4);
dffe_ref regg (
q,
w5,
clk,
1'b1,
clr
);
... | 6.536433 |
module toggle_detector
#(
parameter width = 1
)(
clk,
reset,
signal,
toggle_flag
);
input clk;
input reset;
input [width-1:0]signal;
output toggle_flag;
reg [width-1:0]signal_delayed;
reg [width-1:0]toggle;
genvar i;
generate
for( i=0; i< width; i=i+1 )
begin: toggle_loop
always @ (posedge clk or posedge... | 6.992692 |
module toggle_flipflop (
out,
clock
);
input clock;
output out;
wire d, outBar;
reg reg1;
initial reg1 = 0;
d_flipflop main (
out,
d,
clock
);
not not1 (outBar, out);
or or1 (d, outBar, reg1);
endmodule
| 6.552577 |
module toggle_gen #(
parameter RST_TO_INPUT = 1
) (
input clk,
input rst,
input pulse,
output toggle
);
reg q;
assign toggle = q ^ pulse;
generate
if (RST_TO_INPUT) begin : RST_TO_INPUT_
always @(posedge clk)
if (rst) q <= pulse;
else q <= toggle;
end els... | 6.557877 |
module toggle_reg (
input wire i_clk,
input wire i_res_n,
input wire i_init_val,
input wire i_pls,
output reg o_sig
);
always @(posedge i_clk or negedge i_res_n) begin
if (~i_res_n) begin
o_sig <= i_init_val;
end else if (i_pls) begin
o_sig <= ~o_sig;
end
end
endmo... | 8.156894 |
module toggle_simple ( /*AUTOARG*/
// Outputs
dot,
blank,
// Inputs
in,
rstn
);
input in;
output dot;
output blank;
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
wire dot;
wire blank, blank_n;
latch U_LATCH_1 (
.i(blank_n),
.q(dot),
... | 6.688011 |
module tomasulo (
pc,
clk1,
clk2
);
input [4:0] pc;
input clk1, clk2;
wire [15:0] inst; //This is for getting instruction from ins set
// reg [3:0] rs1,rs2,func,rd;
//These are stage 1 pr
reg [3:0] pr1_rs1, pr1_rs2, pr1_func, pr1_rd;
reg pr2_count;
//These are stage 2 pr
reg [3:0] pr2_... | 7.710145 |
module tomosulo ();
reg clk1, clk2;
reg [5:0] pc;
reg [6:0] func7, opcode;
reg [4:0] rs1, rs2, rd;
reg [2:0] func3;
reg [11:0] imm;
reg [2:0] inst_type;
reg [5:0] ROB[1:8][0:3];
reg [5:0] arf_rat[1:10][0:3];
reg [5:0] rs_add_sub[0:2][0:6];
reg [5:0] rs_div_mul[0:1][0:6];
reg [4:0] lsb[0:2][0:4];... | 6.586641 |
module tone (
input clk,
input [31:0] duration, // millis
input [31:0] freq, //hz
output reg tone_out, // pin
output reg done
);
parameter CLK_F = 48; // CLK freq in MHz
reg [ 7:0] prescaler = 0;
reg [31:0] tone_counter = 0;
reg [31:0] time_counter = 0;
reg [31:0] millis = 0;
w... | 8.025425 |
module ToneDecode (
Index,
OTone
);
input [3:0] Index;
output [12:0] OTone;
reg [12:0] OTone;
always @(Index) begin
case (Index)
4'b0000: OTone = 13'd8191;
4'b0001: OTone = 13'd548;
4'b0010: OTone = 13'd1382;
4'b0011: OTone = 13'd2125;
4'b0100: OTone = 13'd2465;
... | 7.738321 |
module tones (
input wire clk,
output wire ch0,
ch1,
ch2,
ch3
);
//-- Parametro del divisor. Fijarlo a 1Hz
//-- Se define como parametro para poder modificarlo desde el testbench
//-- para hacer pruebas
parameter F0 = `F_1KHz;
parameter F1 = `F_2KHz;
parameter F2 = `F_3KHz;
parameter... | 8.083412 |
module ToneTaba (
iclk,
code,
speaker
);
input iclk;
input [4:0] code;
output speaker;
reg [18:0] Tone;
reg [18:0] cnt;
reg clk_temp;
assign speaker = clk_temp;
always @(posedge iclk) begin
case (code)
5'd0: Tone <= 134;
5'd01: Tone <= 494;
5'd02: Tone <= 554;
5'... | 6.924775 |
module tone_440_rom (
addr,
q
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
input [(ADDR_WIDTH-1):0] addr;
output [(DATA_WIDTH-1):0] q;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
assign q = ram[addr];
initial $readmem... | 7.121599 |
module tone_660_rom (
addr,
q
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
input [(ADDR_WIDTH-1):0] addr;
output [(DATA_WIDTH-1):0] q;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
assign q = ram[addr];
initial $readmem... | 6.913863 |
module tone_gen (
input wire clk_in,
output wire tone
);
parameter freq = 1000;
wire clk_out;
divM #(
.number(freq)
) divider (
.clk_in (clk_in),
.clk_out(clk_out)
);
assign tone = clk_out;
endmodule
| 7.243717 |
module tone_generator (
input output_enable,
input [23:0] tone_switch_period,
input clk,
input rst,
output square_wave_out
);
reg [23:0] clock_counter = 0;
reg wave = 0;
assign square_wave_out = 1'b0;
endmodule
| 7.792384 |
module tone_generator_testbench ();
reg clock;
reg output_enable;
reg rst;
reg [23:0] tone_to_play;
wire sq_wave;
initial clock = 0;
always #(30.3 / 2) clock <= ~clock;
tone_generator piezo_controller (
.clk(clock),
.rst(rst),
.output_enable(output_enable),
.tone_switch_period... | 7.792384 |
module tone_mapping_divider (
clock,
denom,
numer,
quotient,
remain
);
input clock;
input [9:0] denom;
input [17:0] numer;
output [17:0] quotient;
output [9:0] remain;
wire [17:0] sub_wire0;
wire [ 9:0] sub_wire1;
wire [17:0] quotient = sub_wire0[17:0];
wire [ 9:0] remain = sub_w... | 7.816099 |
module tone_tester (
input CLK,
output tone_1khz,
output tone_100hz,
output tone_12khz
);
reg [31:0] period_1khz = 1000;
reg [31:0] period_100hz = 10000;
reg [31:0] period_12khz = 80;
tone #(32) t1 (
.CLK(CLK),
.period(period_1khz),
.tone_out(tone_1khz)
);
tone #(32) t2 ... | 7.340183 |
module decoder_2_4 (
input wire [1:0] in,
output wire [3:0] out
);
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : gen_for_dec_2_4
assign out[i] = (in == i);
end
endgenerate
endmodule
| 7.833664 |
module decoder_4_16 (
input wire [ 3:0] in,
output wire [15:0] out
);
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : gen_for_dec_4_16
assign out[i] = (in == i);
end
endgenerate
endmodule
| 7.408825 |
module decoder_5_32 (
input wire [ 4:0] in,
output wire [31:0] out
);
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : gen_for_dec_5_32
assign out[i] = (in == i);
end
endgenerate
endmodule
| 6.549097 |
module decoder_6_64 (
input wire [ 5:0] in,
output wire [63:0] out
);
genvar i;
generate
for (i = 0; i < 63; i = i + 1) begin : gen_for_dec_6_64
assign out[i] = (in == i);
end
endgenerate
endmodule
| 6.818106 |
module too_slow_char_rom (
input wire [15:0] char_xy,
output reg [ 6:0] char_code // pixels of the character line
);
always @* begin
case (char_xy)
16'h0000: char_code = 7'h54;
16'h0100: char_code = 7'h4f;
16'h0200: char_code = 7'h4f;
16'h0300: char_code = 7'h20;
16'h0400... | 7.059669 |
module top (
input clk,
rst,
input rx,
output tx,
output reg led0,
output reg led1
);
reg startRec;
reg kernelWE;
reg pixelWE;
reg sendWE;
wire calWE;
wire [71:0] kernel;
wire [7:0] Pixel_read;
wire [7:0] Pixel_send;
wire readOne;
wire kernelFinished;
wire calStart;
wire ... | 7.233807 |
module top (
input clk,
input rstn,
(* syn_preserve="TRUE" *) input ila_a,
(* syn_preserve="TRUE" *) input ila_b,
(* syn_preserve="TRUE" *) input ila_c
// (* syn_preserve="TRUE" *)input ila_d
);
(* syn_preserve="TRUE" *)wire data_en_o;
(* syn_preserve="TRUE" *)wire [7:0] data_o;
r... | 7.233807 |
module Top_Module (
input clk, //Clock signal
input [3:0] enable, //Enable signal
input [3:0] angle, //ON/OFF FPGA switch to select angle
input [3:0] clk_trig, //Trigger switch on FPGA for PIPO
output [3:0] pwm //PWM output signal
);
wire [27:0] t ... | 6.750161 |
module top_design (
// Inputs
input clk,
input rst_btn,
// Outputs
output [1:0] led // Not reg element!
);
// Internal signals
wire rst;
// Invert active-low button
assign rst = ~rst_btn;
// Instantiate the first clock divider module
clock_divider #(
.COUNT_WIDTH(32),
.... | 7.970167 |
module uart_buttons_rx_0clk_380ecc95 (
clk,
clock_enable,
\global_to_module.uart_rx_mac_word_out ,
\module_to_global.uart_buttons ,
\module_to_global.uart_rx_mac_out_ready
);
wire [3:0] _0_;
wire [3:0] _1_;
reg [3:0] _2_ = 4'h0;
input clk;
wire clk;
input clock_enable;
wire clock_enab... | 7.225107 |
module uart_buttons_tx_0clk_380ecc95 (
clk,
clock_enable,
\global_to_module.frame_clock_rising_edge ,
\global_to_module.frame_clock_falling_edge ,
\global_to_module.buttons ,
\global_to_module.uart_buttons ,
\module_to_global.buttons_or_uart ,
\module_to_global.uart_tx_mac_word_in
);
w... | 7.225107 |
module unary_op_not_uint17_t_0clk_de264c78 (
expr,
return_output
);
wire [16:0] _0_;
wire [50:0] \20110.read_pipe ;
input [16:0] expr;
wire [16:0] expr;
output [16:0] return_output;
wire [16:0] return_output;
assign _0_ = ~expr;
assign \20110.read_pipe = {expr, 34'hzzzzzzzzz};
assign return_ou... | 7.105344 |
module unary_op_not_uint18_t_0clk_de264c78 (
expr,
return_output
);
wire [17:0] _0_;
wire [53:0] \17950.read_pipe ;
input [17:0] expr;
wire [17:0] expr;
output [17:0] return_output;
wire [17:0] return_output;
assign _0_ = ~expr;
assign \17950.read_pipe = {expr, 36'hzzzzzzzzz};
assign return_ou... | 7.105344 |
module unary_op_not_uint1_t_0clk_de264c78 (
expr,
return_output
);
wire _0_;
wire [2:0] \2434.read_pipe ;
input expr;
wire expr;
output return_output;
wire return_output;
assign _0_ = ~expr;
assign \2434.read_pipe = {expr, 2'hz};
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint1_t_1clk_1891d2b1 (
clk,
expr,
return_output
);
wire _0_;
reg [5:0] _1_;
wire [2:0] \11747.read_pipe ;
input clk;
wire clk;
input expr;
wire expr;
wire [5:0] manual_registers;
wire [5:0] manual_registers_r;
output return_output;
wire return_output;
assign _0_ ... | 7.105344 |
module bin_op_neq_float_8_14_t_float_8_14_t_0clk_de264c78 (
left,
right,
return_output
);
wire _0_;
wire _1_;
wire _2_;
wire _3_;
wire [93:0] \20050.read_pipe ;
input [22:0] left;
wire [22:0] left;
output return_output;
wire return_output;
input [22:0] right;
wire [22:0] right;
assig... | 6.532477 |
module fixed_to_float_0clk_419d9cb4 (
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_l169_c49_... | 7.411582 |
module fixed_to_float_1clk_742dcbff (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_... | 7.411582 |
module fixed_to_float_1clk_7da43b21 (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_... | 7.411582 |
module fixed_to_float_1clk_b5c01c8b (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_... | 7.411582 |
module fixed_to_float_1clk_d2411c07 (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_... | 7.411582 |
module fixed_to_float_1clk_e40e2927 (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_... | 7.411582 |
module fixed_to_float_1clk_e8a081f4 (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_... | 7.411582 |
module fixed_to_float_1clk_f1263733 (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_... | 7.411582 |
module fixed_to_float_1clk_fc83ae6f (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_... | 7.411582 |
module fixed_to_float_1clk_fd16488b (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_... | 7.411582 |
module mux_uint1_t_hit_out_hit_out_0clk_de264c78 (
cond,
\iftrue.dist ,
\iftrue.borderdist ,
\iftrue.hit ,
\iffalse.dist ,
\iffalse.borderdist ,
\iffalse.hit ,
\return_output.dist ,
\return_output.borderdist ,
\return_output.hit
);
wire _0_;
wire [183:0] _1_;
wire [552:0] \... | 7.16061 |
module mux_uint1_t_hit_out_hit_out_1clk_72c91a3c (
clk,
cond,
\iftrue.dist ,
\iftrue.borderdist ,
\iftrue.hit ,
\iffalse.dist ,
\iffalse.borderdist ,
\iffalse.hit ,
\return_output.dist ,
\return_output.borderdist ,
\return_output.hit
);
wire _0_;
wire [183:0] _1_;
reg [... | 7.16061 |
module object_coord_to_float3_0clk_06be10dc (
\a.x ,
\a.y ,
\a.z ,
\return_output.x ,
\return_output.y ,
\return_output.z
);
wire [22:0] _0_;
wire [22:0] _1_;
wire [22:0] _2_;
input [21:0] \a.x ;
wire [21:0] \a.x ;
input [21:0] \a.y ;
wire [21:0] \a.y ;
input [21:0] \a.z ;
wire... | 7.353216 |
module object_coord_to_float3_1clk_68a9f4f7 (
clk,
\a.x ,
\a.y ,
\a.z ,
\return_output.x ,
\return_output.y ,
\return_output.z
);
wire [22:0] _0_;
wire [22:0] _1_;
wire [22:0] _2_;
input [21:0] \a.x ;
wire [21:0] \a.x ;
input [21:0] \a.y ;
wire [21:0] \a.y ;
input [21:0] \a.z... | 7.353216 |
module object_coord_to_float3_1clk_9710bca3 (
clk,
\a.x ,
\a.y ,
\a.z ,
\return_output.x ,
\return_output.y ,
\return_output.z
);
wire [22:0] _0_;
wire [22:0] _1_;
wire [22:0] _2_;
input [21:0] \a.x ;
wire [21:0] \a.x ;
input [21:0] \a.y ;
wire [21:0] \a.y ;
input [21:0] \a.z... | 7.353216 |
module object_coord_to_float3_1clk_cb94220f (
clk,
\a.x ,
\a.y ,
\a.z ,
\return_output.x ,
\return_output.y ,
\return_output.z
);
wire [22:0] _0_;
wire [22:0] _1_;
wire [22:0] _2_;
input [21:0] \a.x ;
wire [21:0] \a.x ;
input [21:0] \a.y ;
wire [21:0] \a.y ;
input [21:0] \a.z... | 7.353216 |
module object_coord_to_float3_1clk_d9f99e26 (
clk,
\a.x ,
\a.y ,
\a.z ,
\return_output.x ,
\return_output.y ,
\return_output.z
);
wire [22:0] _0_;
wire [22:0] _1_;
wire [22:0] _2_;
input [21:0] \a.x ;
wire [21:0] \a.x ;
input [21:0] \a.y ;
wire [21:0] \a.y ;
input [21:0] \a.z... | 7.353216 |
module uart_buttons_rx_0clk_380ecc95 (
clk,
clock_enable,
\global_to_module.uart_rx_mac_word_out ,
\module_to_global.uart_buttons ,
\module_to_global.uart_rx_mac_out_ready
);
wire [3:0] _0_;
wire [3:0] _1_;
reg [3:0] _2_ = 4'h0;
input clk;
wire clk;
input clock_enable;
wire clock_enab... | 7.225107 |
module uart_buttons_tx_0clk_380ecc95 (
clk,
clock_enable,
\global_to_module.frame_clock_rising_edge ,
\global_to_module.frame_clock_falling_edge ,
\global_to_module.buttons ,
\global_to_module.uart_buttons ,
\module_to_global.buttons_or_uart ,
\module_to_global.uart_tx_mac_word_in
);
w... | 7.225107 |
module unary_op_not_uint16_t_0clk_de264c78 (
expr,
return_output
);
wire [15:0] _0_;
wire [47:0] \33744.read_pipe ;
input [15:0] expr;
wire [15:0] expr;
output [15:0] return_output;
wire [15:0] return_output;
assign _0_ = ~expr;
assign \33744.read_pipe = {expr, 32'hzzzzzzzz};
assign return_out... | 7.105344 |
module unary_op_not_uint16_t_1clk_22bc2879 (
clk,
expr,
return_output
);
wire [15:0] _0_;
reg [95:0] _1_;
wire [47:0] \37216.read_pipe ;
input clk;
wire clk;
input [15:0] expr;
wire [15:0] expr;
wire [95:0] manual_registers;
wire [95:0] manual_registers_r;
output [15:0] return_output;
... | 7.105344 |
module unary_op_not_uint16_t_1clk_41572785 (
clk,
expr,
return_output
);
wire [15:0] _0_;
reg [95:0] _1_;
wire [47:0] \52094.read_pipe ;
input clk;
wire clk;
input [15:0] expr;
wire [15:0] expr;
wire [95:0] manual_registers;
wire [95:0] manual_registers_r;
output [15:0] return_output;
... | 7.105344 |
module unary_op_not_uint16_t_1clk_dfdfc59e (
clk,
expr,
return_output
);
wire [15:0] _0_;
reg [95:0] _1_;
wire [47:0] \60639.read_pipe ;
input clk;
wire clk;
input [15:0] expr;
wire [15:0] expr;
wire [95:0] manual_registers;
wire [95:0] manual_registers_r;
output [15:0] return_output;
... | 7.105344 |
module unary_op_not_uint17_t_0clk_de264c78 (
expr,
return_output
);
wire [16:0] _0_;
wire [50:0] \8753.read_pipe ;
input [16:0] expr;
wire [16:0] expr;
output [16:0] return_output;
wire [16:0] return_output;
assign _0_ = ~expr;
assign \8753.read_pipe = {expr, 34'hzzzzzzzzz};
assign return_outp... | 7.105344 |
module unary_op_not_uint1_t_0clk_de264c78 (
expr,
return_output
);
wire _0_;
wire [2:0] \2845.read_pipe ;
input expr;
wire expr;
output return_output;
wire return_output;
assign _0_ = ~expr;
assign \2845.read_pipe = {expr, 2'hz};
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint1_t_1clk_ad90329c (
clk,
expr,
return_output
);
wire _0_;
reg [5:0] _1_;
wire [2:0] \51531.read_pipe ;
input clk;
wire clk;
input expr;
wire expr;
wire [5:0] manual_registers;
wire [5:0] manual_registers_r;
output return_output;
wire return_output;
assign _0_ ... | 7.105344 |
module unary_op_not_uint22_t_0clk_de264c78 (
expr,
return_output
);
wire [21:0] _0_;
wire [65:0] \13606.read_pipe ;
input [21:0] expr;
wire [21:0] expr;
output [21:0] return_output;
wire [21:0] return_output;
assign _0_ = ~expr;
assign \13606.read_pipe = {expr, 44'hzzzzzzzzzzz};
assign return_... | 7.105344 |
module unary_op_not_uint22_t_1clk_a1ec89d4 (
clk,
expr,
return_output
);
wire [ 21:0] _0_;
reg [131:0] _1_;
wire [ 65:0] \51949.read_pipe ;
input clk;
wire clk;
input [21:0] expr;
wire [ 21:0] expr;
wire [131:0] manual_registers;
wire [131:0] manual_registers_r;
output [21:0] return_out... | 7.105344 |
module unary_op_not_uint23_t_0clk_de264c78 (
expr,
return_output
);
wire [22:0] _0_;
wire [68:0] \33978.read_pipe ;
input [22:0] expr;
wire [22:0] expr;
output [22:0] return_output;
wire [22:0] return_output;
assign _0_ = ~expr;
assign \33978.read_pipe = {expr, 46'hzzzzzzzzzzzz};
assign return... | 7.105344 |
module unary_op_not_uint23_t_1clk_0178b709 (
clk,
expr,
return_output
);
wire [ 22:0] _0_;
reg [137:0] _1_;
wire [ 68:0] \60218.read_pipe ;
input clk;
wire clk;
input [22:0] expr;
wire [ 22:0] expr;
wire [137:0] manual_registers;
wire [137:0] manual_registers_r;
output [22:0] return_out... | 7.105344 |
module unary_op_not_uint23_t_1clk_9c9fdeb0 (
clk,
expr,
return_output
);
wire [ 22:0] _0_;
reg [137:0] _1_;
wire [ 68:0] \52012.read_pipe ;
input clk;
wire clk;
input [22:0] expr;
wire [ 22:0] expr;
wire [137:0] manual_registers;
wire [137:0] manual_registers_r;
output [22:0] return_out... | 7.105344 |
module top (
input clk16,
input usb_d_p,
input usb_d_n,
output usb_pullup,
output user_led
);
wire sys_clk;
reg sys_rst = 1'd0;
wire clk16_1;
reg [23:0] count = 24'd0;
// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator
// to run the combinatorial process ... | 7.233807 |
module top (
input clk16,
input usb_d_p,
input usb_d_n,
output usb_pullup,
output user_led
);
wire sys_clk;
reg sys_rst = 1'd0;
wire clk16_1;
wire clk16b;
reg [23:0] count = 24'd0;
// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator
// to run the combina... | 7.233807 |
module top (
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk_125mhz,
input wire rst_125mhz,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] s... | 7.364191 |
module consume_cdc (
sdram_clk,
consume_r_gry,
consume_w_gry,
sdram_rst
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/fifo.py:353" *)
input [2:0] consume_r_gry;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/fifo.py:354"... | 6.606069 |
module i_button_ffsync (
i_unsync_buttons__fireA,
i_unsync_buttons__fireB,
i_unsync_buttons__up,
i_unsync_buttons__down,
i_unsync_buttons__left,
i_unsync_buttons__right,
i_buttons__pwr,
rst,
clk,
i_unsync_buttons__pwr
);
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/ga... | 7.190546 |
module pin_button_pwr_0 (
button_pwr_0__io,
button_pwr_0__i
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/vendor/lattice_ecp5.py:465" *)
wire \$1 ;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
output button_pwr_... | 7.276041 |
module pin_esp32_spi_0__en (
esp32_spi_0__en__io,
esp32_spi_0__en__o
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
output esp32_spi_0__en__io;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
in... | 6.569117 |
module pin_esp32_spi_0__gpio0 (
esp32_spi_0__gpio0__io,
esp32_spi_0__gpio0__o
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/vendor/lattice_ecp5.py:531" *)
wire \$1 ;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
... | 6.569117 |
module pin_esp32_spi_0__gpio12_cipo (
esp32_spi_0__gpio12_cipo__io
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
output esp32_spi_0__gpio12_cipo__io;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
... | 6.569117 |
module pin_esp32_spi_0__gpio16_sclk (
esp32_spi_0__gpio16_sclk__io
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
wire esp32_spi_0__gpio16_sclk__i;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
in... | 6.569117 |
module pin_esp32_spi_0__gpio4_copi (
esp32_spi_0__gpio4_copi__io
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
wire esp32_spi_0__gpio4_copi__i;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
input... | 6.569117 |
module pin_esp32_spi_0__gpio5_cs (
esp32_spi_0__gpio5_cs__io
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/vendor/lattice_ecp5.py:465" *)
wire \$1 ;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
wire esp32_spi_0__gpi... | 6.569117 |
module pin_esp32_spi_0__rx (
esp32_spi_0__rx__io,
esp32_spi_0__rx__i
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
output esp32_spi_0__rx__i;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
inp... | 6.569117 |
module pin_esp32_spi_0__tx (
esp32_spi_0__tx__io,
esp32_spi_0__tx__o
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
output esp32_spi_0__tx__io;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
in... | 6.569117 |
module pin_uart_0__tx (
uart_0__tx__io,
uart_0__tx__o
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
output uart_0__tx__io;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
input uart_0__tx__o;
... | 6.500531 |
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