code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock, reset, req_0, req_1;
output gnt_0, gnt_1;
wire clock, reset, req_0, req_1;
reg gnt_0, gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101;
reg [SIZE-1:0] state;
reg... | 7.229634 |
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm (
.clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1)
);
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout, A} = cin + y + x;
`else
assign {cout, A} = cin - y * x;
`endif
endmodule
| 7.233807 |
module top_Game (
input wire CLK100MHZ,
input wire vauxp2,
input wire vauxn2,
input wire vauxp3,
input wire vauxn3,
input wire vauxp10,
input wire vauxn10,
input wire vauxp11,
input wire vauxn11,
input wire vp_in,
input wire vn_in,
input wire [3:0] sw,
output wire [15... | 7.733288 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
parameter u = 0;
genvar index;
generate
for (index = 0; index < 8; index = index + 1) begin : gen_code_label
end
endgenerate
genvar index;
generate
case (u)
0: begin
end
1: begin
... | 7.233807 |
module Top_GLB #(
parameter FIFO_DATA_WIDTH = 8,
parameter PE_SIZE = 16,
parameter integer MEM0_DEPTH = 896,
parameter integer MEM1_DEPTH = 896,
parameter integer MEM0_ADDR_WIDTH = 7,
parameter integer MEM1_ADDR_WIDTH = 7,
parameter integer MEM0_DATA_WIDTH = 128,
parameter integer MEM1_D... | 7.492739 |
module is to test a RPi driving
* input and displaying those input on
* LEDs.
*
* Author : Brandon Bloodget
*
*****************************
*/
// Force error when implicit net has no type.
`default_nettype none
module top_gpio_out
(
input wire clk_100mhz,
input wire reset_n,
// rpi parallel bus
inpu... | 6.512913 |
module gp_dff (
input d,
input clk,
clr,
output reg q
);
wire nq;
GP_DFF u_gp_dffr (
d,
clk,
nq
);
GP_INV u_gp_inv (
nq,
q
);
endmodule
| 6.624889 |
module gp_dffr (
input d,
input clk,
clr,
output reg q
);
wire nq;
GP_DFFR u_gp_dffr (
d,
clk,
clr,
nq
);
GP_INV u_gp_inv (
nq,
q
);
endmodule
| 6.809361 |
module gp_latchs (
input d,
input clk,
clr,
output reg q
);
wire nq;
GP_DLATCHS u_gp_dffs (
d,
clk,
clr,
nq
);
GP_INV u_gp_inv (
nq,
q
);
endmodule
| 6.847366 |
module top_greedy_snake (
input clk,
input rst,
input left,
input right,
input up,
input down,
input [14:0] sw,
output [15:0] led,
output hsync,
output vsync,
output [11:0] color_out,
output [7:0] seg_out,
output [3:0] sel
);
wire left_key_press;
wire right_key... | 7.712426 |
module top_gy_26 (
input flag_gy26,
input clk,
input rst,
input data_rx,
output RX232,
output [9:0] jiaodu
);
Top_uart_tx_gy_26 a (
.flag_gy26(flag_gy26),
.clk(clk),
.rst(rst),
.RX232(RX232),
.over_all(over_all),
.over_rx(over_rx)
);
top_uart_rx_gy_26 b ... | 6.544141 |
module top_HW3_test;
reg [3:0] A;
reg [3:0] B;
reg Scan_CLK;
reg [7:0] BCI;
reg CLK;
wire [2:1] COM;
wire [6:0] SEG;
top_HW3 DUT (
.A(A),
.B(B),
.Scan_CLK(Scan_CLK),
.BCI(BCI),
.CLK(CLK),
.COM(COM),
.SEG(SEG)
);
initial begin
A = 0;
... | 6.609323 |
module top_hash_table_URAM (
input clk,
input reset,
input [31:0] key_in,
input [7:0] en_in,
output [64-1:0] rd_xor_result
);
parameter NUM_MUL = 1;
parameter NUM_RD = 16;
parameter NUM_WR = 8;
parameter VALUE_WIDTH = 31;
parameter KEY_WIDTH = 32;
parameter INDEX_WIDTH = 15;
parameter... | 6.780764 |
module (Everything that will be synthesized)
//
// Author: Manoja & Yash
// Date: 14th March 2018
//
// Description:
// ------------
// Encapsulates the interface and the design, by instantiating them here. And so port connections are made here
//
////////////////////////////////////////////////////////////////////////... | 6.755072 |
module top_hex_demo (
input wire clk_25mhz,
input wire [6:0] btn,
output wire [7:0] led,
output wire oled_csn,
output wire oled_clk,
output wire oled_mosi,
output wire oled_dc,
output wire oled_resn
);
parameter C_color_bits = 16;
assign led = 0;
reg [127:0] R_display; // someth... | 6.849367 |
module top (
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o_mid, o_rtl;
always @(posedge cin) A <= o_mid;
middle u_mid (
.x(x),
.y(o_rtl),
.o(o_mid)
);
u_rtl inst_u_rtl (
.x(o_mid),
.y(y),
.o(o_rtl)
);
endmodule... | 7.233807 |
module middle (
input x,
input y,
output o
);
wire o1, o2;
assign o1 = x & o2;
assign o2 = y & o1;
assign o = o1;
endmodule
| 6.553865 |
module u_rtl (
input x,
input y,
output o
);
wire o1, o2;
assign o1 = x & o2;
assign o2 = y & o1;
assign o = o1;
endmodule
| 6.750051 |
module top_hourseg (
rst,
inclk,
seg1,
seg10
);
input rst, inclk;
output wire [6:0] seg1, seg10;
wire [5:0] sec_val;
hour_cnt counter (
rst,
inclk,
sec_val
);
hour_conv converter (
rst,
sec_val,
seg1,
seg10
);
endmodule
| 7.343025 |
module top_HW3 (
input [3:0] A,
B,
input Scan_CLK,
output [2:1] COM,
output [6:0] SEG,
input [7:0] BCI,
input CLK
);
wire [2:1] COM_w;
wire ENA;
MUX_DISP MD1 (
.A(A),
.B(B),
.clk(Scan_CLK),
.com_1(COM_w[1]),
.com_2(COM_w[2]),
.seg_A(SEG[0]),
.s... | 7.525633 |
module that will instantiate and connect our DUT (lcd_controller) the ICON, VIO , ILA cores
For more information refer to this tutorial (Search in docs if link is broken)
http://www.stanford.edu/~phartke/chipscope_tutorial.pdf
http://www.stanford.edu/class/ee183/handouts.shtml
*/
module top_hw_testbench(
input ... | 7.707616 |
module top_hx8k (
clk_in,
reset_n_in,
// Global data
sck0_in,
sdi0_in,
cs0_n_in,
// Daisy data
sck1_in,
sdi1_in,
sdo1_out,
cs1_n_in,
// READY flags
ready_n_od_out,
// Indicator LED
status_led_n_out
);
localparam POOL_SIZE = 2;
localparam POOL_SIZE_LOG2 = 1... | 6.779626 |
module top (
input [8:0] a,
input [8:0] b,
output [8:0] o1,
output [2:0] o2,
input [2:0] c,
input [2:0] d,
output [2:0] o3,
output [2:0] o4,
input s
);
assign o1 = (s ? 0 : a + b);
assign o2 = (s ? a : a - b);
assign o3 = (s ? 4'b1111 : d + c);
assign o4 = (s ? d : c - d);
e... | 7.233807 |
module top_icecream_v1 (
input clk,
output [2:0] led_n
);
`include "macros/direction.vh"
reg [2:0] int_rst_cnt = 0;
wire pll_locked;
wire new_clk;
always @(posedge new_clk) begin
if (int_rst_cnt != 3'b111 && pll_locked) int_rst_cnt <= int_rst_cnt + 1;
end
wire int_rst_n = int_rst_cnt == 3... | 6.740302 |
module top (
input en,
input a,
output b
);
tribuf u_tri (
.en(en),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'II1_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared libra... | 7.358787 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'II2_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared libra... | 7.358787 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'II3_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared libra... | 7.358787 |
module top_iic (
input sys_clk,
input sys_rst_n,
output scl,
inout sda
);
parameter SLAVE_ADDRESS = 7'b1010_000; // the address of slave
parameter SYSTEM_CLK = 26'd50_000_000; // system clock
parameter IIC_CLK = 26'd250_000; // IIC clock
parameter DIV_FREQ_FACTOR = SYSTEM_CLK / IIC_CLK / 2... | 7.648227 |
module top_impl (
input wire btn,
input wire gclk,
input wire rst,
input wire [7:0] led_sel,
output wire [11:0] led
);
wire clk;
dejitter dejitter (
.clk(gclk),
.btn(btn),
.btn_out(clk)
);
top top (
.clk(clk),
.gclk(gclk),
.rst(rst),
.led_sel(led_s... | 7.77974 |
module top_infrared_rcv (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号，低电平有效
input wire infrared_in, //红外接收信号
output wire stcp, //输出数据存储寄时钟
output wire shcp, //移位寄存器的时钟输入
output wire ds, //串行数据输入
output wire oe, //输出使能信号
output wire led //led灯控制信号
);
... | 6.548302 |
module top (
input x,
input y,
input cin,
output reg A,
output reg cout,
output reg B,
C
);
reg ASSERT = 1;
initial begin
begin
A = 0;
cout = 0;
end
end
assign A = y + cin;
assign cout = y + A;
always @* assert (ASSERT);
assign {B, C} = {cout, A}... | 7.233807 |
module gpio (
input clk,
input wire out_en,
input wire in_sig,
output wire out_sig
);
localparam INPUT = 0;
localparam OUTPUT = 1;
always @(posedge clk) begin
if (out_en == 0) begin
out_sig <= in_sig;
end
end
endmodule
| 7.858288 |
module top_inout
(
input wire CLK_16MHZ,
input wire PIN_1, // out_en
input wire PIN_2, // in_sig
inout wire PIN_3, // bi-directional pin
output reg PIN_4, // out_sig
);
localparam INPUT = 0;
localparam OUTPUT = 1;
wire out_en = PIN_1;
wire in_sig;
reg out_sig;
SB_IO #(
.PIN_TYPE... | 8.090067 |
module top (
input [7:0] data_a,
data_b,
input [6:1] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clka,
clkb,
inout reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[0:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @... | 7.233807 |
module mux2 (
S,
A,
B,
Y
);
input S;
input A, B;
output reg Y;
always @(*) Y = (S) ? B : A;
endmodule
| 7.562788 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
assign {cout, A} = ~(cin + y + x);
endmodule
| 7.233807 |
module adff (
input [3:0] d,
input clk,
clr,
output reg [3:0] q
);
initial begin
q = 4'b0000;
end
always @(posedge clk, posedge clr)
if (clr) q <= 4'b0110;
else q <= d;
endmodule
| 7.089232 |
module top (
input clk,
input clr,
input pre,
input [3:0] a,
output [3:0] b
);
adff u_adff (
.clk(~clk),
.clr(~clr),
.d (~a),
.q (b)
);
endmodule
| 7.233807 |
module top (
input rx,
output tx,
output sync
);
wire clk;
SB_HFOSC #(
.CLKHF_DIV("0b10")
) u_SB_HFOSC (
.CLKHFPU(1),
.CLKHFEN(1),
.CLKHF (clk)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
... | 7.233807 |
module top_jacobi (
input clk,
input rst_n,
output wire [31:0] quotient_out
);
wire start_r;
wire [31:0] divisor_r;
wire [31:0] dividend_r;
wire [31:0] quotient_out_o;
wire complete_o;
assign quotient_out = quotient_out_o;
jacobi j1 (
.clk(clk),
.rst_n(rst_n),
.start_r(start_... | 7.530116 |
module top_jump;
reg [31:0] inst = 32'b0000000001000000000000111101111;
reg clk, reset;
top U_TOP (
clk,
reset,
inst
);
initial begin
clk = 0;
reset = 0;
$dumpfile("top_jump.vcd");
$dumpvars(0, top_jump);
end
always #5 clk = !clk;
initial begin
reset = 1;
... | 6.687464 |
module top_key (
clk_50Mhz,
kin,
kclk,
keyout,
idle
);
input clk_50Mhz, kclk, kin;
output wire [7:0] keyout;
output wire idle;
ps2key keyboard0 (
.clk50(clk_50Mhz),
.kin (kin),
.kclk (kclk),
.code (keyout),
.idle (idle)
);
endmodule
| 7.372615 |
module top_keyexp (
//input
input wire clk,
input wire rst_n,
input wire [127:0] key_in,
input wire start_in,
input wire en_de,
input wire [3:0] round_in,
//output
output wire [127:0] key_out,
output wire ready_out
);
//internal wires
wire [7:0] sbox_in;
... | 8.606554 |
module top_key_demo (
input CLK100MHZ,
input PS2_CLK,
input PS2_DATA,
// output [6:0]SEG,
// output [7:0]AN,
// output DP,
output UART_TXD,
output [7:0] short_code,
input reset
);
reg CLK50MHZ = 0;
wire [31:0] keycode;
always @(posedge (CLK100MHZ)) begin
CLK50MHZ <= ~CLK5... | 6.855509 |
module latsr (
input d,
clk,
pre,
clr,
output reg q
);
always @(*)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.011 |
module top (
input clk,
input a,
output b
);
latsr u_latsr (
.clk(clk),
.clr(1'b1),
.pre(1'b1),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module alatn (
input d,
en,
clr,
output reg q
);
initial begin
q = 0;
end
always @(*)
if (!clr) q <= 1'b0;
else if (!en) q <= d;
endmodule
| 7.499248 |
module latsr (
input d,
en,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(*)
if (clr) q <= 1'b0;
else if (pre) q <= 1'b1;
else if (en) q <= d;
endmodule
| 7.011 |
module nlatsr (
input d,
en,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(*)
if (!clr) q <= 1'b0;
else if (!pre) q <= 1'b1;
else if (!en) q <= d;
endmodule
| 7.387062 |
module top (
input en,
input clr,
input pre,
input a,
output b,
b1,
b2,
b3
);
latsr u_latsr (
.en (en),
.clr(clr),
.pre(pre),
.d (a),
.q (b)
);
nlatsr u_nlatsr (
.en (en),
.clr(clr),
.pre(pre),
.d (a),
.q (b1)
... | 7.233807 |
module top_layer (
clk,
start,
dram_in,
iram_in_ext,
data_out,
addr_ext,
mem_write_data_ext,
mem_write_ins,
read_en_ext,
data_in_ext,
iram_in,
addr_ins,
addr_out,
state,
control_out,
ir_out,
read_en,
data_out_proc,
pc_addr,
addr_out_proc,
... | 6.56185 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
//Keep inverter off
LDCE_1 ff (
.G (clk),
.GE (ce),
.CLR(sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
//Keep inverter off
LDPE_1 ff (
.G (clk),
.GE (ce),
.PRE(sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top_LEDs (
input clock,
input reset,
input [3:0] hex0,
input [3:0] hex1,
input [3:0] hex2,
input [3:0] hex3,
output reg [3:0] enable,
output [7:0] dispcode, // ߶ܵ
output light
);
wire clk_sys;
wire [1:0] count;
wire [3:0] hex_num;
assign light = clk_sys;
clk_div ... | 7.768587 |
module top_level ();
parameter cycle = 10;
reg hclk;
reg hresetn;
wire hready_out;
wire [1:0] hresp;
wire [31:0] hrdata;
wire hwrite, hready_in;
wire [1:0] htrans;
wire [31:0] haddr, hwdata;
wire pwrite, penable;
wire [2:0] psel;
wire [31:0] paddr, pwdata;
wire pwrite_out, penable_out;
... | 6.813051 |
module top_level (
CLOCK_50,
SW,
HEX0,
HEX1,
HEX2,
LEDR
); // Defines the top_level for the timer circuit
input wire CLOCK_50; // Declares input hardware 50MHz Clock
input wire [2:0] SW; //Declares 3 input switches
output [2:0] LEDR; //Declares 3 output LEDR wires
assign LEDR[2:0] =... | 7.454809 |
module top_level_4_1 (
HEX0,
SW,
LEDR
); //declares module
input wire [5:0] SW; //data and selection input
output wire [5:0] LEDR; //outputs 6 wires for LEDR
output wire [6:0] HEX0; //outputs 7 wires for our HEX display
assign LEDR[5:0] = SW[5:0]; //assigns LEDRs to switches
wire m; //d... | 8.979461 |
module top_level (
input CLK,
input [3:0] BUTTON,
output TX
);
wire rst;
wire clkin1, clk_100, clk_10;
wire [63:0] tx_reg;
wire tx_en, tx_dv;
wire [7:0] temp;
//Input Clk buffer
IBUF clkin1_buf (
.O(clkin1),
.I(CLK)
);
//Clk Divider - MMCM
CLK_DIV #(
.MULTI(6.0)
) ... | 7.454809 |
module top_level (
input CLK,
input [3:0] BUTTON,
output TX
);
wire rst;
wire clkin1, clk_100, clk_10;
wire [63:0] tx_reg;
wire tx_en, tx_dv;
wire [7:0] temp;
//Input Clk buffer
IBUF clkin1_buf (
.O(clkin1),
.I(CLK)
);
//Clk Divider - MMCM
CLK_DIV #(
.MULTI(6.0)
) ... | 7.454809 |
module clock_divider (
HCLK,
n_RST,
PRE,
tim_clk,
DFT_in,
DFT_sdi,
DFT_sen,
DFT_sdo
);
input HCLK, n_RST, DFT_in, DFT_sdi, DFT_sen;
input [2:0] PRE;
output tim_clk, DFT_sdo;
wire HCLK, n_RST, DFT_in, DFT_sdi, DFT_sen;
wire [2:0] PRE;
wire tim_clk, DFT_sdo;
wire clkdiv2, clk... | 6.818038 |
module top_level_crossbar (
clock,
reset,
req_1m,
cmd_1m,
req_2m,
cmd_2m,
wdata_1m,
wdata_2m,
addr_1m,
addr_2m
);
parameter CLK_HALF_PERIOD = 5;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
input wire clock, reset, req_1m, cmd_1m, req_2m, cmd_2m;
input wire [... | 8.030036 |
module Top_level_design (
i_clk,
data_in_1,
data_in_2,
start,
p_STATE,
o_reg_Q,
o_reg_R,
o_reg_B,
Count_out,
done
);
input i_clk;
input [`WIDTH1-1:0] data_in_1; ////divisor B ///
//input rst_n ;
input start;
input [`WIDTH1-1:0] data_in_2; ///dividened Q///
output [... | 7.501161 |
module Top_level_design_tb ();
reg i_clk;
reg [`WID_1-1:0] data_in_1; ////divisor B ///
//reg rst_n ;
reg start;
reg [`WID_1-1:0] data_in_2; ///dividened Q///
wire [`WID_1-1:0] o_reg_B;
wire [`WID_1-1:0] o_reg_R;
wire [`WID_1-1:0] o_reg_Q;
wire [`WID_3-1:0] Count_out;
... | 7.501161 |
module top_level_D_latch_try_2 (
SW,
LEDR
); //Defines Module
input wire [1:0] SW; //Definess input wire bus for 2 swithces
output wire [3:0] LEDR; //Defines output wire bus for 4 LEDRS
D_latch_try_2(
SW[1], SW[0], LEDR[2], LEDR[3]
); //Instantiates the D Latch module
assign LEDR[1:0] = S... | 6.662342 |
module top_level_frameGenerator #(
parameter LEN_DATA_BLOCK = 64,
parameter LEN_CTRL_BLOCK = 8
) (
input i_clock,
input i_reset,
input i_enable,
output wire [LEN_DATA_BLOCK-1 : 0] o_tx_data,
output wire [L... | 7.64203 |
module top_level_gated_sr_latch (
SW,
LEDR
); //declares module
input wire [2:0] SW; //defines input wires for Switches
output wire [4:0] LEDR; //defines output wires for LEDRs
gated_sr_latch(
SW[1], SW[0], SW[2], LEDR[3], LEDR[4]
); //instantiates gated_sr_latch
assign LEDR[2:0] = SW[2:0... | 8.006669 |
modules
//
/////////////////////////////////////////////////////////////////////////////////////////
module top_level_integration(
// Outputs
output reg [25:0] addr_to_L2,
output reg [1:0] command_to_L2,
input mode,
// Inputs
input Clock,
input clear,
input [3:0] n,
input [31:0] address_in,
... | 7.33426 |
module top_level_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
... | 6.712905 |
module top_level_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear... | 6.712905 |
module top_level_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [... | 6.712905 |
module top_level_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
in... | 6.712905 |
module
module top_level_module (testmode,sysclk,modeControl,resetb,Hex0,Hex1,Hex2,Hex3,LEDR);
input [1:0] testmode;
input sysclk,modeControl,resetb;
output [6:0] Hex0,Hex1,Hex2,Hex3;
output LEDR;
wire sigIn,sigOut,sig1Hz,enable,reset,lock;
wire [15:0] count;
wire [3:0] out0,out1,out2,out3;
assign LE... | 7.252875 |
module top_level_mux2_1 (
input choice0,
input choice1,
input selection_bit,
output selected_output
);
assign selected_output = selection_bit ? choice1 : choice0;
endmodule
| 7.760832 |
module top_level_pipeline_cpu ();
wire clk;
Pipelined_CPU Pipelined_CPU (
.clk (clk),
.clk10(clk),
.stall(0),
.clk12(clk),
.clk13(clk),
.clk14(clk),
.clk16(clk),
.clk17(clk),
.clk18(clk),
.clk19(clk)
);
Clock b2v_inst1 (.clk(clk));
endmodule
| 7.858017 |
module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
******************************************************************************/
modul... | 7.349016 |
module top_level_p_data (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31... | 6.871021 |
module top_level_p_input (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [1:0] in_port;
input reset_n;
wire clk_en;
wire [ 1:0] data_in;
wire [ 1:0] read_mux_out;
reg [31:0] readda... | 6.55246 |
module top_level_p_signal (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [1:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [... | 7.163024 |
module top_level (
input clk_100mhz_in,
inout [7:0] IO_P9,
output [7:0] IO_P8,
inout [7:0] IO_P7,
output [7:0] LED,
input [5:0] Switch,
output [7:0] SevenSegment,
output [2:0] SevenSegmentEnable
);
wire clk_sample;
wire clk_100mhz;
wire clk_7seg_scan;
wire rst;
wire rx_in;
w... | 7.454809 |
module to the Digilent S7 board.
* Inputs and outputs are defined in the XDC Master Constraint File
* provided by Xilinx.
*
* Dependencies:
*
* Revision:
* Revision 0.01 - File Created
* Additional Comments:
*
*/
module top_level_serial(
input enable,
input ck_io26,
input ck_io27,... | 6.862602 |
module top_level_sr_latch (
SW,
LEDR
); //declares module
input wire [1:0] SW; //defines input wires for Switches
output wire [3:0] LEDR; //defines output wires for LEDRs
sr_latch(
SW[1], SW[0], LEDR[2], LEDR[3]
); //instantiates sr_latch
assign LEDR[1:0] = SW[1:0]; //assigns LEDRs to Swi... | 7.644832 |
module top_level_tb ();
reg stm_clk, stm_rst, stm_wrt_tx, stm_rd_rx, stm_sel_low, stm_sel_high;
reg [1:0] stm_br_cfg;
reg [7:0] stm_tx_data, stm_baud_data_in;
reg [15:0] baud_rate_data;
wire tbr_mon, txd_mon, rx_in, tx_rx_en, tb_rda_mon;
wire [7:0] final_data_mon;
reg [2:0] i;
reg [3:0] flags;
t... | 8.61882 |
module top_level (
input clk_100mhz,
input clk_12mhz,
input rx_in,
output tx_out,
output clk_recovered,
output [7:0] LED,
input [5:0] Switch,
input [7:0] DPSwitch,
output [7:0] SevenSegment,
output [2:0] SevenSegmentEnable
);
wire clk_sample;
wire clk_bit_tx;
wire rst;
w... | 7.454809 |
module topLevel_top (
input c,
u, // Botao 1, 2,
input cima,
baixo,
enter, // Botao 3,4,5
input clock,
reset, // 50 MHz Clock
output [9:0] led, // Led
output [3:0] ledTeste,
output sucesso, // Parametro para afirmar se funcionou ou nao
output pizza,
burguer,
... | 7.191273 |
module top_level_tx (
input clk_100mhz_in,
inout [9:0] IO_P2,
output [0:0] IO_P3,
output [7:0] LED,
input [3:0] Switch
);
wire clk_bit;
wire clk_100mhz;
wire rst;
wire [7:0] tx_d_in;
wire [7:0] fifo_d_in;
wire fifo_empty;
wire fifo_full;
wire fifo_read_enable;
wire prbs_on;
wir... | 6.64078 |
module top_level_ukf (
input wr_rst,
input wr_enable,
input [127:0] write_data,
input reset,
fast_clock,
slow_clock
);
wire [31:0] rd_data_diag, rd_data_l1, rd_data_l2, rd_data_l3, rd_data_l4;
wire empty_l1, empty_l2, empty_l3, empty_l4, empty_diag, fifo_wre_lower, ... | 6.698517 |
modules or verilog. So as the top level, there are 6 inputs
and one output. Since I am using sturctural verilog and so I used wires.
*****************************************************************************************************************/
//module name and port lists
module top_level_USR( clk_100MHz, rst, ... | 7.398612 |
module top_level (
input clk_p,
input clk_n,
input [4:0] BUTTON,
output TX
);
wire rst;
wire clkin1, clk_100, clk_10;
wire [63:0] tx_reg;
wire tx_en, tx_dv;
wire [7:0] temp;
//Input Clk buffer
IBUFGDS clkin1_buf (
.O (clkin1),
.I (clk_p),
.IB(clk_n)
);
//Clk Divide... | 7.454809 |
module Top_Life #(
parameter N = 25
) (
input clk,
input nrst,
output out0
);
reg [(N*N)-1:0] seeds;
wire [(N*N)-1:0] cells;
assign out0 = cells[0];
GameOfLife #(
.N(N)
) itsmylife (
.clk (clk),
.nrst (nrst),
.seeds(seeds),
.cells(cells)
);
always @(pose... | 7.113357 |
module tristate (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) o <= (en) ? i : 1'bZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(en),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module top (
input x,
input y,
input z,
output A,
output B
);
wire A1, B1, A2, B2;
assign A1 = x & A2;
assign A2 = A1 & y;
assign A = ~A2;
endmodule
| 7.233807 |
module top_loopback (
// UART USB ports
input sys_clk_p, // 200 MHZ on SP605
input sys_clk_n, // 200 MHZ on SP605
output CTS, // I am ready to receive data
input RTS, // USB Clear to send
output TX, // Output to USB
input RX, // Input to USB
output [3:0] leds
);
wire bsys_clk; ... | 7.488194 |
module top_lora_tx (
input clk,
input rst_n,
input send_en,
input [7:0] data_rx,
output RX232,
output over_rx
);
wire bps_start_1;
bps_set_lora u_bps_set_lora (
.clk(clk),
.rst_n(rst_n),
.bps_start(bps_start_1),
.bps_clk(bps_clk)
);
uart_tx_l... | 6.527265 |
module lpc_7seg (
RST, // Active Low (From PCI bus)
DISP_SEL,
DISP_LED,
LPC_CLK,
LFRAME,
LAD,
LAD_OE
);
input RST;
output [3:0] DISP_SEL;
output [6:0] DISP_LED;
input LPC_CLK;
input LFRAME;
inout [3:0] LAD;
output LAD_OE;
wire [2:0] dma_chan_i = 3'b000;
wire dma... | 6.66142 |
module top_LPC_FPGA_AlgorithmRun (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input ... | 7.640876 |
module top_LPC_FPGA_AlgorithmStart (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
inpu... | 7.640876 |
module top_LPC_FPGA (
algorithm_run_export,
avmm_master_control_rm_fixed_location,
avmm_master_control_rm_read_base,
avmm_master_control_rm_read_length,
avmm_master_control_rm_go,
avmm_master_control_rm_done,
avmm_master_control_wm_fixed_location,
avmm_master_control_wm_write_base,
a... | 6.960641 |
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