code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top (
input clk,
input a,
output b
);
dff u_dff (
.clk(clk),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module dffcp (
input d,
clk,
pre,
clr,
output reg q
);
always @(posedge clk)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
| 6.577005 |
module top (
input clk,
input a,
input c,
output b
);
dffcp u_dffcp (
.clk(clk),
.clr(c),
.pre(1'b1),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module dffcp (
input d,
clk,
pre,
clr,
output reg q
);
always @(posedge clk, posedge pre, posedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
| 6.577005 |
module top (
input clk,
input a,
output b
);
dffcp u_dffcp (
.clk(clk),
.clr(1'b0),
.pre(1'b1),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module top (
input d,
clk,
en,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk) if (en) q <= d;
endmodule
| 7.233807 |
module dffr (
input d,
clk,
rst,
output reg q
);
always @(posedge clk)
if (rst) q <= 1'b0;
else q <= d;
endmodule
| 7.053895 |
module top (
input clk,
input a,
output b
);
dffr u_dffr (
.clk(clk),
.rst(1'b1),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module dffsr (
input d,
clk,
pre,
clr,
output reg q
);
always @(posedge clk, posedge pre, negedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
| 6.804969 |
module top (
input clk,
input a,
output b
);
dffsr u_dffsr (
.clk(clk),
.clr(1'b1),
.pre(1'b1),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module dff (
clk,
d,
q
);
input clk;
input d;
output reg q;
always @(posedge clk) q <= d;
endmodule
| 6.824043 |
module top (
input clk,
input a,
output b
);
dff u_dff (
.clk(clk),
.d (1'b0),
.q (b)
);
endmodule
| 7.233807 |
module top_diannao_node_vMAX (
clk, // Main clock
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_op, // Average or MAX op select line (avg = 0, max - 1)
i_nbout, // feedback input from NBout
i_load,
o_to_edram
);
parameter N = 16;
parameter Tn = 1;
paramet... | 7.347611 |
module top_diannao_node_vMAX (
clk, // Main clock
reset, // Reset
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_nbout, // Input from NBOut
i_sigmoid_coef, // Coef... | 7.347611 |
module top_diannao_node_vMAX_no_nfu3 (
clk, // Main clock
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_nbout,
i_op,
o_to_nbout
);
parameter N = 16;
parameter Tn = 16;
parameter TnxTn = Tn * Tn;
//----------- Input Ports ---------------//
input clk;
in... | 7.347611 |
module max_short (
input [15:0] x,
input [15:0] y,
output [15:0] z
);
assign z = (y > x) ? y : x;
endmodule
| 7.08246 |
module max_byte (
input [7:0] x,
input [7:0] y,
output [7:0] z
);
assign z = (y > x) ? y : x;
endmodule
| 7.597222 |
module fiveminusmax0 (
input [3:0] i,
output [3:0] o
);
wire [4:0] fiveminus;
assign fiveminus = 5'd5 - {1'b0, i};
assign o = (!fiveminus[4]) ? fiveminus[3:0] : 4'b0;
endmodule
| 7.754056 |
module unitfull (
input [1:0] select_ms,
input [7:0] Hmm,
input [7:0] Hmc,
input [7:0] Hcm,
input [7:0] Ecm,
input [7:0] Fmc,
output [7:0] Hcc,
output [7:0] Ecc,
output [7:0] Fcc
);
/*
Hcc = max( Hmm + ms, Ecc, Fcc)
Ecc = max( Hcm - 6, Ecm - 1)
Fcc = max( Hmc - 6, Fmc - 1)
... | 6.805252 |
module top (
input USER_CLOCK,
output [3:0] z
);
wire clk;
clockdrv clockdrv ( // Clock in ports
.CLK_IN1 (USER_CLOCK), // IN
// Clock out ports
.CLK_OUT1(clk)
); // OUT
reg [41:0] state;
assign z = state[27:24];
always @(posedge clk) begin
state = state + 1;
end
... | 7.233807 |
module top_dip (
in,
out,
clk
);
parameter N = 128;
parameter M = 8;
input clk;
input [M:0] in;
output reg [M:0] out;
reg [M:0] image_in[N-1:0][N-1:0];
reg [M:0] image_in2[N+1:0][N+1:0];
reg [M:0] image_out[N-1:0][N-1:0];
reg [2:0] prc = 0;
reg [2:0] prc1 = 0;
reg load = 1;
integer... | 6.781053 |
module top_direct_send (
input clk,
input rst,
input RsRx, // Connect to RX pin
output [7:0] Rx_data, // Received data
output RsTx // Connect to TX pin
);
parameter CLK_RATE = 9600000;
parameter BAUD_RATE = 9600;
parameter SAMPLE_RATE = 10;
wire c... | 7.103126 |
module top_display (
input clk,
input [3:0] thousand,
input [3:0] hund,
input [3:0] ten,
input [3:0] unit,
output [6:0] LED_out,
output dp,
output [3:0] Anode_activate
);
wire [3:0] digit;
wire [1:0] anode;
anode_controller ac1 (
clk,
Anode_activate,
anode
);
... | 7.295151 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
assign {cout, A} = cin % y / x;
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin, (* init = 1'h0 *)
output reg A,
output cout
);
parameter X = 1;
wire o;
initial A = 0;
initial cout = 0;
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle u_mid (
.x(x),
.o(o)
);
u_rtl inst_u_rtl (
.x(x)... | 7.233807 |
module middle (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 6.553865 |
module u_rtl (
input x,
input y,
output o
);
initial o = 0;
assign o = x / 0;
endmodule
| 6.750051 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
wire pow, p, n;
assign {cout, A} = cin % y / x;
assign pow = y ** x;
assign p = +x;
assign n = -x;
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
assign cout = x / y * cin;
endmodule
| 7.233807 |
module top_div_test (
clk,
rst
);
input clk, rst;
wire clk_div;
div_clock test (
clk,
rst,
clk_div
);
endmodule
| 6.687377 |
module top_double_ram_sy (
clk,
rst,
cs,
din_a_0,
addr_a_0,
dout_a,
we_a,
oe_a,
din_b_0,
addr_b_0,
dout_b,
we_b,
oe_b,
rst_clk,
load
);
parameter DATA_WIDTH = 3;
parameter ADDR_WIDTH = 3;
parameter RAM_DEPTH = DATA_WIDTH;
input clk, rst, cs;
input ... | 6.762889 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'DPO_AUTO_EXPR_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the sh... | 7.358787 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'DPO_AUTO_OP_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shar... | 7.358787 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'DPO_INLINE_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the share... | 7.358787 |
module top
(
input [5:0] x,
input [5:0] y,
output [11:0] A,
);
assign A = x * y;
endmodule
| 7.039434 |
module top #(
parameter AW = 2,
BW = 2,
AREG = 1,
BREG = 1,
PREG = 1
) (
input clk,
CEA,
CEB,
CEP,
input [AW-1:0] A,
input [BW-1:0] B, (* keep *)
output reg [AW+BW-1:0] P
);
(* keep *)reg [AW-1:0] Ar;
(* keep *)reg [BW-1:0] Br;
generate
if (AREG) begin
alw... | 7.964012 |
module
module top_dual_fifo #
(
parameter AWIDTH = 3,
parameter DWIDTH = 16
)
(
input arst_n, // asynchronous reset
input wclk, // writing circuit's clock
input wdv, // data valid signal. Writing circuit must assert this signa to ha... | 7.700374 |
module Mem1D (
input clock,
input [ 3:0] io_w_addr,
input [31:0] io_w_data,
input io_w_en,
input [ 3:0] io_r_addr,
output [31:0] io_output_data
);
reg [31:0] _T_14[0:15];
reg [31:0] _RAND_0;
wire [31:0] _T_14__T_17_data;
wire [3:0] _T_14__T_17_addr;
wire [31:0] _T_14... | 7.084095 |
module MemND (
input clock,
input [ 3:0] io_w_addr_0,
input [31:0] io_w_data,
input io_w_en,
input io_wMask,
input [ 3:0] io_r_addr_0,
output [31:0] io_output_data
);
wire m_clock;
wire [3:0] m_io_w_addr;
wire [31:0] m_io_w_data;
wire m_io_w_en;
wire [3:0... | 6.691417 |
module MuxVec (
input [63:0] io_ins_0_0_addr,
input io_ins_0_0_isWr,
input [15:0] io_ins_0_0_size,
input [63:0] io_ins_1_0_addr,
input io_ins_1_0_isWr,
input [15:0] io_ins_1_0_size,
input io_sel,
output [63:0] io_out_0_addr,
output io_out_0_isWr,
... | 7.323123 |
module Depulser (
input clock,
input reset,
input io_in,
input io_rst,
output io_out
);
wire r_clock;
wire r_reset;
wire r_io_in;
wire r_io_init;
wire r_io_out;
wire r_io_enable;
wire _T_6;
wire _T_8;
FF_11 r (
.clock(r_clock),
.reset(r_reset),
.io_in(r_io_in)... | 6.621304 |
module CounterCore (
input clock,
input reset,
output [9:0] io_out,
output [9:0] io_next,
input io_enable,
output io_done,
input [9:0] io_config_max
);
wire counter_clock;
wire counter_reset;
wire [9:0] counter_io_max;
wire [9:0] counter_io_out;
wire [9:... | 6.834422 |
module CounterChainCore (
input clock,
input reset,
output [9:0] io_out_0,
output [9:0] io_out_1,
output [9:0] io_next_1,
input io_enable_0,
output io_done_0
);
wire counters_0_clock;
wire counters_0_reset;
wire [9:0] counters_0_io_out;
wire [9:0] counters_... | 6.629693 |
module MuxN_1 (
input [63:0] io_ins_0_addr,
input io_ins_0_isWr,
input [15:0] io_ins_0_size,
output [63:0] io_out_addr,
output io_out_isWr,
output [15:0] io_out_size
);
assign io_out_addr = io_ins_0_addr;
assign io_out_isWr = io_ins_0_isWr;
assign io_out_size = io_ins_0_si... | 7.832446 |
module MuxN_3 (
input io_ins_0,
output io_out
);
assign io_out = io_ins_0;
endmodule
| 7.122897 |
module MuxN_4 (
input io_ins_0_valid,
input [31:0] io_ins_0_bits_wdata_0,
input [31:0] io_ins_0_bits_wdata_1,
input [31:0] io_ins_0_bits_wdata_2,
input [31:0] io_ins_0_bits_wdata_3,
input [31:0] io_ins_0_bits_wdata_4,
input [31:0] io_ins_0_bits_wdata_5,
input [31:0] io_ins... | 7.574965 |
module MuxN_5 (
input io_ins_0,
input io_ins_1,
input io_sel,
output io_out
);
wire _GEN_0;
wire _GEN_1;
assign _GEN_1 = io_sel ? io_ins_1 : io_ins_0;
assign io_out = _GEN_0;
assign _GEN_0 = _GEN_1;
endmodule
| 7.48046 |
module MuxN_6 (
input io_ins_0_valid,
input [63:0] io_ins_0_bits_addr,
input [31:0] io_ins_0_bits_size,
input io_ins_0_bits_isWr,
input [31:0] io_ins_0_bits_tag,
input [31:0] io_ins_0_bits_streamId,
input io_ins_1_valid,
input [63:0] io_ins_1_bits_addr,
i... | 7.54457 |
module CounterChainCore_4 (
input clock,
input reset,
output [5:0] io_out_0,
output [5:0] io_out_1,
output [5:0] io_next_0,
output [5:0] io_next_1,
input io_enable_0,
input io_enable_1,
input io_config_chain_0
);
wire counters_0_clock;
wire coun... | 6.629693 |
module MuxN_14 (
input [31:0] io_ins_0,
output [31:0] io_out
);
wire [31:0] _GEN_0;
assign io_out = _GEN_0;
assign _GEN_0 = io_ins_0;
endmodule
| 8.213776 |
module top_dynamic (
input wire sys_clk,
input wire sys_rst_n,
output wire stcp,
output wire shcp,
output wire ds,
output wire oe
);
wire [19:0] data;
wire [5:0] point;
wire sign;
wire seg_en;
data_gen data_gen_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.d... | 8.75978 |
module top_ecc (
clk,
reset,
inst,
ctrl,
sel,
data_out
);
input clk;
input reset;
input [2:0] inst;
input [2:0] ctrl;
input [1:0] sel;
output [7:0] data_out;
wire clk;
wire reset;
wire [2:0] inst;
wire [2:0] ctrl;
wire [1:0] sel;
wire [7:0] data_out;
wire [31:0] da... | 6.502333 |
module top_edge_preseving_filter (
clk,
rst_n,
en,
done
);
input clk, rst_n, en;
output done;
wire done_mem;
wire [7:0] cl_pixel; // data is filted
wire wr; // signal write into mem2
wire rd, act; // signal read from mem1
wire [7:0] sw_pixel_1,sw_pixel_2,sw_pixel_3,sw_pixel... | 7.33061 |
module top_elf2_v1 (
output reg [2:0] led_n
);
`include "macros/direction.vh"
reg [2:0] int_rst_cnt = 0;
wire osc_clk;
wire clk = osc_clk;
always @(posedge clk) begin
if (int_rst_cnt != 3'b111) int_rst_cnt <= int_rst_cnt + 1;
end
wire int_rst_n = int_rst_cnt == 3'b111;
wire rst_n = int_rst_... | 6.748837 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
typedef enum {
red,
blue,
green
} e_color;
endmodule
| 7.233807 |
module dut (
input fast_clk,
slow_clk,
input [3:0] waddr,
raddr,
input [3:0] wdata,
input wen,
output [3:0] rdata
);
reg [3:0] mem[0:15];
reg [3:0] raddr_reg;
always @(posedge fast_clk) begin
if (wen) mem[waddr] <= wdata;
end
always @(posedge slow_clk) raddr_reg <= raddr;
... | 7.120761 |
module fsm (
clock,
reset,
req,
gnt
);
input clock, reset;
inout [1:0] req;
output [1:0] gnt;
wire clock, reset;
wire [1:0] req;
reg [1:0] gnt;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101, GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-... | 7.229634 |
module fsm2 (
clock,
reset,
req,
gnt
);
input clock, reset;
inout [1:0] req;
output [1:0] gnt;
wire clock, reset;
wire [1:0] req;
reg [1:0] gnt;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101, GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE... | 6.534312 |
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g;
wire [1:0] r;
fsm u_fsm (
.clock(clk),
.reset(rst),
.req (r),
.gnt (g)
);
assign g0 = g[0];
assign g1 = g[1];
assign r[0] = a;
assign r[1] = b;
endmodule... | 7.233807 |
module top (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 7.233807 |
module top (
input [7:0] x,
input [7:0] y,
input cin,
output reg [7:0] A,
output [7:0] cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle #(7) u_mid (
.x(x),
.o(o),
.y(1'b0)
);
middle #(0) u_mid2 (
.x... | 7.233807 |
module middle (
x,
y,
o
);
parameter u = 7;
input [u:0] x;
input [u:0] y;
output [u:0] o;
assign o = x + y;
endmodule
| 6.553865 |
module top (
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle u_mid (
.x(x),
.o(o),
.y(1'b0)
);
u_rtl inst_u_rtl (
.x(x),
.o(o)
);
`else
a... | 7.233807 |
module middle (
input x,
input y,
output o
);
wire w;
assign o = x + y;
endmodule
| 6.553865 |
module u_rtl (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 6.750051 |
module top_example_adder #(
parameter integer C_AXIS_TDATA_WIDTH = 512, // Data width of both input and output data
parameter integer C_ADDER_BIT_WIDTH = 32
) (
input wire aclk,
input wire aresetn,
input wire [C_ADDER_BIT_WIDTH-1:0] ctrl_constant,
input wire s_axi... | 8.220099 |
module top_fc #(
parameter integer C_S00_AXIS_TDATA_WIDTH = 32
) (
input wire CLK,
input wire RESETN,
/// For AXIS protocol
output wire S_AXIS_TREADY,
input wire [ C_S00_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
input wire [(C_S00_AXIS_TDATA_WIDTH/8)-1 : ... | 7.137185 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDCE ff (
.C (clk),
.CE (ce),
.CLR(sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top (
input clk,
ce,
sr,
d,
output q
);
/*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
cliff didn't have constrai... | 7.233807 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDPE ff (
.C (clk),
.CE (ce),
.PRE(sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDRE ff (
.C (clk),
.CE(ce),
.R (sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDSE ff (
.C (clk),
.CE(ce),
.S (sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top_fetch #(
parameter PC_DATA_WIDTH = 20,
parameter INSTRUCTION_WIDTH = 32,
parameter PC_INITIAL_ADDRESS = 20'h0
) (
input clk, // CPU core clock
input rst_n, // CPU core reset active low
input en,
input stall, // Indicates a stall insertion on the datapath
// input flush, ... | 8.327742 |
module adff (
d,
clk,
clr,
q
);
input d, clk, clr;
(* init = 1'h0 *)
output reg q;
initial begin
q = 0;
end
always @(posedge clk, posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.095675 |
module adff (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.089232 |
module adffn (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
| 7.422273 |
module dffe (
input d,
clk,
en,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk) if (en) q <= d;
endmodule
| 7.085902 |
module dffsr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge pre, posedge clr)
if (clr) q <= 1'b0;
else if (pre) q <= 1'b1;
else q <= d;
endmodule
| 6.804969 |
module ndffnsnr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(negedge clk, negedge pre, negedge clr)
if (!clr) q <= 1'b0;
else if (!pre) q <= 1'b1;
else q <= d;
endmodule
| 7.273757 |
module top (
input clk,
input clr,
input pre,
input a,
output b,
b1,
b2,
b3,
b4
);
dffsr u_dffsr (
.clk(clk),
.clr(clr),
.pre(pre),
.d (a),
.q (b)
);
ndffnsnr u_ndffnsnr (
.clk(clk),
.clr(clr),
.pre(pre),
.d (a),
... | 7.233807 |
module top_FFT
(
input IN_PLLClock,Reset,
`ifndef NO_DAI
//For DAI
input BCK,LRCK,SData,
`endif
//For SRAM
output nWE,nOE,
inout [14:0] SRAMIO,
output [17:0] SRAMAddr,
//For LCDs
output DotClock,VS,HS,
output [14:0] L_RGB, R_RGB
//Debug Pin
`ifndef SIM
,
output [1:0] LED
`endif
);
////////... | 6.678605 |
module top_FFT
(
input Clock,Reset,
//For DAI
input BCK,LRCK,SData,
//For SRAM
output nWE,
inout [14:0] SRAMIO,
output [17:0] SRAMAddr,
//For LCDs
output DotClock,VS,HS,
output [14:0] L_RGB, R_RGB
);
////////////////////////////////////////////////////
// Instansiation
// 1/4 Clock Divider
CLKDI... | 6.678605 |
module adff (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.089232 |
module adffn (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
| 7.422273 |
module dffe (
input d,
clk,
en,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk) if (en) q <= d;
endmodule
| 7.085902 |
module dffsr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge pre, posedge clr)
if (clr) q <= 1'b0;
else if (pre) q <= 1'b1;
else q <= d;
endmodule
| 6.804969 |
module ndffnsnr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(negedge clk, negedge pre, negedge clr)
if (!clr) q <= 1'b0;
else if (!pre) q <= 1'b1;
else q <= d;
endmodule
| 7.273757 |
module top (
input clk,
input clr,
input pre,
input a,
output b,
b1,
b2,
b3,
b4
);
dffsr u_dffsr (
.clk(clk),
.clr(clr),
.pre(pre),
.d (a),
.q (b)
);
ndffnsnr u_ndffnsnr (
.clk(clk),
.clr(clr),
.pre(pre),
.d (a),
... | 7.233807 |
module top_FIFO (
input clk_125M,
input reset,
input read,
input write,
input [3:0] din,
output full,
output empty,
output almost_empty,
output almost_full,
output [3:0] data_count,
output [3:0] dout
);
wire clk_5M, clk_200H, clk_pulse;
clk_wiz_0 in1 (
.clk_out1(cl... | 6.705486 |
module errors_prompt (
input [3:0] errors,
input clock,
output reg errors_go
);
localparam S_WAIT = 4'd0, S_PROMPT = 4'd1;
reg [3:0] current_state = S_WAIT;
reg [3:0] next_state;
always @(*) begin : state_table
case (current_state)
S_WAIT: next_state = (errors == 4'b0) ? S_WAIT : S_PROM... | 8.192581 |
module top_fir_lpf (
input wire sclk,
input wire rst_n,
output wire [20:0] lpf_wave
);
wire [7:0] o_wave;
wire lpf_wave_v;
wire [1:0] lpf_wave_ast_source_error;
wire ast_sink_ready;
dds_1M_10M dds_1M_10M_instance (
.sclk (sclk),
.rst_n (rst_n),
.o_wave(o_wave)
)... | 8.025532 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'FLAT_UNROLL_ALL_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the ... | 7.358787 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'FLAT_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared libr... | 7.358787 |
module top_fnd_display (
input i_clk,
i_reset,
input [7:0] i_data,
output [7:0] o_fndData,
output [3:0] o_fndSelect
);
wire [1:0] w_cnt_2bit;
wire w_1khz;
wire [3:0] w_digit_0, w_digit_1, w_digit_2, w_digit_3, w_data;
clockDivider #(
.MAX_COUNT(50_000)
) clkDiv_1khz (
.i_clk ... | 6.544602 |
module top_top_formal_verification_random_tb;
// ----- Default clock port is added here since benchmark does not contain one -------
reg [0:0] clk;
// ----- Shared inputs -------
reg [0:0] a;
reg [0:0] b;
// ----- FPGA fabric outputs -------
wire [0:0] out:c_gfpga;
`ifdef AUTOCHECKED_SIMULATION
// ----- Benchma... | 7.093103 |
module TOP_for_debug #(
parameter BYTE = 8,
parameter DWORD = 32,
parameter ADDR = 5,
parameter NB_MEM_DEPTH = 8,
parameter RB_ADDR = 5,
parameter NB_STATE = 10
) (
input i_clock,
input i_reset,
input i_clock_reset,
... | 6.899901 |
module top_for_testing (
result_wire,
result,
finished_wire,
rx_data,
rx_ready,
clk,
rst
);
output [63:0] result_wire;
output [7:0] result;
output finished_wire;
input [7:0] rx_data;
input rx_ready, clk, rst;
wire MEM_we, data_collection_finish, collect_finish_display;
wire ... | 7.235732 |
module top_fpga (
input wire PCLK,
input wire PRESETn,
input wire PSEL,
input wire PENABLE,
input wire PWrite,
input wire [3:0] button,
inout i2c_sda,
inout i2c_scl,
output PREADY,
output [2:0] ADDRE,
output [7:0] DATA
);
//////change PADDR,PWDATA,length,frequency here... | 8.279586 |
module: top_fpga
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_fpga_tb;
// Inputs
reg PCLK;
reg PRESETn;
reg PSEL;
reg PENABLE;
reg PWrite;
reg [1:0] I;
// Outputs
w... | 7.092709 |
module: top_fpu_add
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_fpu_add_tb;
// Inputs
reg clk;
reg up_button;
reg [8:1] sw;
// Outputs
wire [3:0] leds_l;
wire [3:0] ... | 7.455915 |
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