code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_LPC_FPGA_DDR3_interface_p0_acv_ldc (
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_H... | 7.640876 |
module top_LPC_FPGA_DDR3_interface_p0_clock_pair_generator (
datain,
dataout,
dataout_b
) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_ob... | 7.640876 |
module top_LPC_FPGA_DDR3_interface_p0_generic_ddio (
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
inpu... | 7.640876 |
module top_LPC_FPGA_DDR3_interface_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe(probe_input),
.source()
// synopsys translate_off
, .clr(),
.ena(),
.ir_in(),
... | 7.640876 |
module top_LPC_FPGA_DDR3_interface_p0_reset (
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_re... | 7.640876 |
module top_LPC_FPGA_DDR3_interface_p0_reset_sync (
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastabili... | 7.640876 |
module MACC (
P,
A,
B,
CARRYIN,
CLK,
RST
);
output reg [47:0] P;
input [24:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK) begin
if (!RST) mult_reg <= 'b0;
else mult_reg <= A * B;
end
always @(posedge CLK) begi... | 7.194091 |
module top (
input clk,
input rst,
input [24:0] a,
input [17:0] b,
input carryin,
output [47:0] p,
output [47:0] pw
);
MACC u_MACC (
.P(p),
.A(a),
.B(b),
.CARRYIN(carryin),
.CLK(clk),
.RST(rst)
);
MACC u_MACC_1 (
.P(pw),
.A(a),
.B... | 7.233807 |
module full_adder_1 (
a,
b,
cin,
y,
cout
);
input a, b, cin;
output y, cout;
wire a, b, cin;
wire y, cout;
wire n_0;
AO2NHS g33 (
.A(cin),
.B(n_0),
.C(a),
.D(b),
.Z(cout)
);
F_EOHSX05 g34 (
.A(n_0),
.B(cin),
.Z(y)
);
F_EOHSX05 g35 (... | 6.657465 |
module top_mdio_slave (
reset,
mdc,
mdio,
dev_addr,
conf_done
);
input reset;
input mdc;
inout mdio;
input [4:0] dev_addr;
output conf_done;
wire VHDL2V_mdio;
wire mdio;
wire conf_done;
wire [4:0] reg_addr; // Address register
wire reg_read; // Read register ... | 6.678564 |
module top (
input [7:0] data_a,
data_b,
input [6:1] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clk,
output reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @(posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a... | 7.233807 |
module top (
input [7:0] data_a,
data_b,
input [6:1] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clk,
output reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @(posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a... | 7.233807 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'MEM_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared libra... | 7.358787 |
module top_mian (
input clk,
input rst_n,
input rxd,
output txd,
output [7:0] led,
output sdram_clk,
output [11:0] sdram_addr,
output [ 1:0] sdram_ba,
output sdram_cas_n,
output sdram_cke,
output sdram_cs_n,
inout [... | 7.610737 |
module top_minseg (
rst,
inclk,
seg1,
seg10
);
input rst, inclk;
output wire [6:0] seg1, seg10;
wire [5:0] sec_val;
min_cnt counter (
rst,
inclk,
sec_val
);
min_conv converter (
rst,
sec_val,
seg1,
seg10
);
endmodule
| 6.75476 |
module IO_SWITCH (
BCLK,
BRESET,
I_IOA,
D_IOA,
I_IORD,
D_IORD,
D_IOWR,
IO_READY,
GENSTAT,
D_IOBE,
ILO_SIG,
DCWACC,
IO_A,
IO_RD,
IO_WR,
IO_BE,
I_IORDY,
D_IORDY,
STATUS,
ILO
);
input BCLK, BRESET;
input [31:0] I_IOA, D_IOA;
input I_IOR... | 7.495642 |
module MAKE_STAT (
BCLK,
READ,
DACC_OK,
DC_ACC,
DPTE_ACC,
DC_MDONE,
DRAM_WR,
IC_READ,
IACC_OK,
DATA_HOLD,
IC_ACC,
IPTE_ACC,
IC_MDONE,
KOLLISION,
STATSIGS
);
input BCLK;
input READ, DACC_OK;
input DC_ACC, DPTE_ACC, DC_MDONE;
input DRAM_WR;
input IC_R... | 6.986283 |
module Top_mod (
clk,
rst,
PWM
);
input clk; //100MHz
input rst;
output PWM;
wire [7:0] pcout; //Program Counter Output
wire [20:0] Instruction; // 21 bit instruction
wire [3:0] valve; // Valve
wire set_bit; // Goes high when valve is set
wire [9:0] delay; // 10 bit delay to be give... | 7.437425 |
module top_handshakes #(
parameter WIDTH = 8
) (
input clk,
input rst,
input valid_en,
input ready_en,
output m_valid,
output m_ready,
output s_valid,
output s_ready,
input [WIDTH-1:0] m_data_in,
output [WIDTH-1:0] m_data_out,
output [WIDTH-1... | 6.842838 |
moduletb.v
// Project Name: Transmitter
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: AASD
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////... | 8.700732 |
module Top_Module_Block (
data_in,
clk,
interrupt,
reset,
data_out
);
wire [23:0] ins;
wire [7:0] A;
wire [7:0] B;
wire [7:0] Current_Address;
wire [7:0] ans_ex;
wire [7:0] ans_dm;
wire [7:0] ans_wb;
wire [1:0] mux_sel_A;
wire [1:0] mux_sel_B;
wire imm_sel;
output [7:0] data_... | 7.350337 |
module color_top (
input clk,
input frequency,
output reg is_move,
output reg [1:0] move,
output [1:0] filter_out,
output led,
output [1:0] frequency_rate
//output [7:0]blue,
//output [7:0]green
);
//reg is_move;
//reg [1:0]move;
assign frequency_rate = 2'b01;
assign led = ... | 6.642193 |
module top_module_Mario (
input wire clk48, // clock signal, reset signal from switch
output wire SPEAKER
);
`include "../../rom_conversion/parameters/Parameters_Mario_general.vh"
`include "../../rom_conversion/parameters/Parameters_ROM_Mario_0.vh"
`include "../../rom_conversion/parameters/Parameters_... | 7.311771 |
module top_module_mips_v2 (
output [31:0] INST,
output [31:0] out,
output flag,
input RST,
input [4:0] addr,
input CLK,
input write,
output [31:0] ina,
inb,
ALUA,
ALUB
);
// decode INST
reg [4:0] read1, wadd;
reg ALUsrc;
wire [5:0] opcode = INST[31:26];
wire [5:0]... | 6.609881 |
module PC (
input CLK,
input RST,
output [31:0] INST
);
wire write = 1'b0; // dont write..
wire [31:0] data_in = 32'b0;
wire [31:0] data_out;
assign INST = data_out;
wire [4:0] addr;
// call program counter
COUNTER5B COUNTER (
.CLK (CLK),
.addr(addr),
.RST (RST)
);
//... | 7.578567 |
module Top_module_of_color (
input clk,
input frequncy,
output [1:0] filter_select,
output [1:0] frequncy_rate,
output led,
output [9:0] r,
g,
b
);
assign frequncy_rate = 2'b10;
assign led = 1'b1;
wire [63:0] r_time, g_time, b_time;
wire [1:0] filter_balance, filter_identify;
... | 7.014897 |
module_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top_module_tb;
parameter W = 32;
// Inputs... | 6.516961 |
module: Top_Module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_Module_Test;
// Inputs
reg [31:0] R2;
reg [31:0] R3;
reg [2:0] ALUOp;
reg clk;
// Outputs
wire [31:0]... | 8.366146 |
module top_module_Yoshi (
input wire clk48, // clock signal, reset signal from switch
output wire SPEAKER
);
`include "../../rom_conversion/parameters/Parameters_Yoshi_general.vh"
`include "../../rom_conversion/parameters/Parameters_ROM_Yoshi_0.vh"
localparam MID_C_OFFSET = 12;
localparam CHANNEL_... | 7.799076 |
module top_module_Yoshi2 (
input wire clk48, // clock signal, reset signal from switch
output wire SPEAKER
);
`include "../../rom_conversion/parameters/Parameters_Yoshi2_general.vh"
`include "../../rom_conversion/parameters/Parameters_ROM_Yoshi2_0.vh"
localparam MID_C_OFFSET = 12;
localparam CHANN... | 7.799076 |
module top_mod_test;
reg clk;
reg rst;
wire PWM;
Top_mod uut (
.clk(clk),
.rst(rst),
.PWM(PWM)
);
initial begin
clk = 0;
rst = 1; // Reset
#20;
rst = 0;
#20;
end
always #5 clk = ~clk; // Simulate 100MHz board clock
endmodule
| 6.915848 |
module top_motor_controller (
input wire rst,
input wire clk,
input wire change,
input wire mode,
input wire move,
input wire direction,
input wire step_size,
output wire [3:0] phase_out,
output wire [6:0] ones,
output wire [6:0] tens
);
//internal wires
wire [2:0] speed;
... | 8.944112 |
module seven_display #(
parameter INVERT = 1
) (
input [3:0] n,
output [6:0] segments
);
reg [6:0] bits;
assign segments = (INVERT ? ~bits : bits);
always @(n)
case (n)
4'h0: bits = 7'b0111111; // 0
4'h1: bits = 7'b0000110; // 1
4'h2: bits = 7'b1011011; // 2
4'h3: bits... | 7.02946 |
module top_ms #(
parameter GPIO_PINS = 8
) (
input CLK50,
input [3:0] SW,
// UART
input RXD,
output TXD,
// Peripherals
output [7:0] LEDS,
// 3v3 input from the s6 on the de1soc
input S6_3v3,
// SSDs
output [6:0] ssd0,
output [6:0] ssd1,
out... | 6.707767 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
assign {cout, A} = cin * y * x;
endmodule
| 7.233807 |
module tristate (
en,
i,
o
);
input en;
input i;
output [1:0] o;
wire [1:0] io;
assign io[0] = (en) ? i : 1'bZ;
assign io[1] = (i) ? en : 1'bZ;
assign io[0] = (~en) ? ~i : 1'bZ;
assign o = io;
endmodule
| 6.741184 |
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en(en),
.i (a),
.o (c)
);
endmodule
| 7.233807 |
module multi_enc_decx2x4 (
// Inputs
clock,
datain,
datain1,
datain1_0,
datain_0,
reset,
// Outputs
dataout,
dataout1,
dataout1_0,
dataout_0
);
//--------------------------------------------------------------------
// Input
//---------------------------------------... | 7.153212 |
module top (
input [7:0] dataa,
input [7:0] datab,
input clk,
aclr,
clken,
sload,
output reg [15:0] adder_out
);
// Declare registers and wires
reg [15:0] dataa_reg, datab_reg;
reg sload_reg;
reg [15:0] old_result;
wire [15:0] multa;
// Store the results of the operations on th... | 7.233807 |
module MACC (
P,
A,
B,
CARRYIN,
CLK,
RST
);
output reg [47:0] P;
input [24:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK) begin
if (!RST) mult_reg <= 'b0;
else mult_reg <= A * B;
end
always @(posedge CLK) begi... | 7.194091 |
module top (
input clk,
input rst,
input [24:0] a,
input [17:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P(p),
.A(a),
.B(b),
.CARRYIN(carryin),
.CLK(clk),
.RST(rst)
);
endmodule
| 7.233807 |
module MACC (
P,
A,
B,
CARRYIN,
CLK,
RST
);
output reg [47:0] P;
input [15:0] A;
input [17:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK) begin
if (!RST) mult_reg <= 'b0;
else mult_reg <= A * B;
end
always @(posedge CLK) begi... | 7.194091 |
module top (
input clk,
input rst,
input [15:0] a,
input [17:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P(p),
.A(a),
.B(b),
.CARRYIN(carryin),
.CLK(clk),
.RST(rst)
);
endmodule
| 7.233807 |
module MACC (
P,
A,
B,
CARRYIN,
CLK,
RST
);
output reg [47:0] P;
input [15:0] A;
input [15:0] B;
input CARRYIN;
input CLK;
input RST;
reg [47:0] mult_reg;
always @(posedge CLK) begin
if (!RST) mult_reg <= 'b0;
else mult_reg <= A * B;
end
always @(posedge CLK) begi... | 7.194091 |
module top (
input clk,
input rst,
input [15:0] a,
input [15:0] b,
input carryin,
output [47:0] p
);
MACC u_MACC (
.P(p),
.A(a),
.B(b),
.CARRYIN(carryin),
.CLK(clk),
.RST(rst)
);
endmodule
| 7.233807 |
module MACC (
P,
A,
B,
CARRYIN,
CLK,
RST
);
output reg signed [31:0] P;
input signed [15:0] A;
input signed [15:0] B;
input CARRYIN;
input CLK;
input RST;
reg signed [31:0] mult_reg;
always @(posedge CLK) begin
if (!RST) mult_reg <= 'b0;
else mult_reg <= A * B;
end
... | 7.194091 |
module top (
input clk,
input rst,
input signed [15:0] a,
input signed [15:0] b,
input carryin,
output signed [31:0] p
);
MACC u_MACC (
.P(p),
.A(a),
.B(b),
.CARRYIN(carryin),
.CLK(clk),
.RST(rst)
);
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin,
output cout
);
assign cout = cin ? y : x;
endmodule
| 7.233807 |
module top (
input [5:0] S,
input [63:0] D,
output M256
);
assign M256 = D[S];
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
endmodule
| 7.233807 |
module top_new (
input wire CLK100MHZ,
input wire RST_BTN,
input wire BTNC,
input wire vauxp2,
input wire vauxn2,
input wire vauxp3,
input wire vauxn3,
input wire vauxp10,
input wire vauxn10,
input wire vauxp11,
input wire vauxn11,
input wire vp_in,
input wire vn_in,
... | 7.650351 |
module nfu_3_top (
clk,
i_nfu2_out,
i_coef,
i_load_coef,
i_max,
i_min,
i_offset,
o_nfu3_out
);
parameter N = 16;
parameter Tn = 16;
parameter BIT_IDX = 4;
input clk;
input i_load_coef;
input [((2*N)-1):0] i_coef;
input [(Tn*N) - 1 : 0] i_nfu2_out;
// control signals f... | 8.072772 |
module top
(
input [2:0] x,
input [2:0] y,
output [5:0] A,
);
assign A = x * y;
endmodule
| 7.039434 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
wire A1, cout1;
assign A1 = ~y + &cin;
assign cout1 = cin ? |y : ^A;
assign A = A1 | y~&cin ~^ A1;
assign cout = cout1 & cin~|y;
endmodule
| 7.233807 |
module top
(
input [7:0] x,
output A,
);
assign A = ^x;
endmodule
| 7.039434 |
module top (
input x,
input y,
input cin,
output reg A,
output cout
);
wire o;
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle u_mid (
x,
y,
o
);
endmodule
| 7.233807 |
module middle (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 6.553865 |
module top (
x,
clk,
rst,
arst
);
output x;
reg x;
input clk;
input rst;
input [1:0] arst;
always @(posedge clk, negedge rst) begin : DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end else begin
case (arst)
2'b00: begin
x = 0;
... | 6.963493 |
module top (
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *)reg foo;
(* anyseq *)reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
always @(posedge x) begin
if ($initstate) A <= 0;
A <= y + cin + too;
en... | 7.233807 |
module top_np (
input wire CLK,
input wire RST,
input wire SERIAL_RX,
output reg SERIAL_TX
);
initial begin
$display("Hello World");
$finish;
end
endmodule
| 7.099441 |
module top_nto1_ddr_diff_rx (
input reset, // reset (active high)
input [7:0] datain_p,
datain_n, // lvds data inputs
input clkin_p,
clkin_n, // lvds clock input
output [63:0] dummy_out
); // dummy outputs
// Parameters for serdes factor and number of IO pins
parameter integer S = 8; ... | 6.934944 |
module top_nto1_ddr_diff_tx (
input reset, // reset (active high)
input refclkin_p,
refclkin_n, // frequency generator clock input
output [7:0] dataout_p,
dataout_n, // lvds data outputs
output clkout_p,
clkout_n
); // lvds clock output
// Parameters for serdes factor and number of IO... | 6.934944 |
module top_nto1_ddr_se_rx (
input reset, // reset (active high)
input [7:0] datain, // single ended data inputs
input clkin1,
clkin2, // TWO single ended clock input
output [63:0] dummy_out
); // dummy outputs
// Parameters for serdes factor and number of IO pins
parameter integer S = 8; ... | 6.934944 |
module top_nto1_ddr_se_tx (
input reset, // reset (active high)
input refclkin_p,
refclkin_n, // frequency generator clock input
output [7:0] dataout, // single ended data outputs
output clkout
); // single ended clock output
// Parameters for serdes factor and number of IO pins
parameter ... | 6.934944 |
module top_nto1_pll_16_diff_rx (
input reset, // reset (active high)
input [5:0] datain_p,
datain_n, // lvds data inputs
input clkin_p,
clkin_n, // lvds clock input
output [95:0] dummy_out
); // dummy outputs
// Parameters for serdes factor and number of IO pins
parameter integer S = 1... | 7.222471 |
module top_nto1_pll_16_diff_rx_and_tx (
input reset, // reset (active high)
input [5:0] datain_p,
datain_n, // lvds data inputs
input clkin_p,
clkin_n, // lvds clock input
output [5:0] dataout_p,
dataout_n, // lvds data outputs
output clkout_p,
clkout_n
); // lvds clock output
... | 7.222471 |
module top_nto1_pll_16_diff_tx (
input reset, // reset (active high)
input refclkin_p,
refclkin_n, // frequency generator clock input
output [5:0] dataout_p,
dataout_n, // lvds data outputs
output clkout_p,
clkout_n
); // lvds clock output
// Parameters for serdes factor and number of... | 7.222471 |
module top_nto1_pll_diff_rx (
input reset, // reset (active high)
input [ 7:0] datain_p,
datain_n, // lvds data inputs
input clkin_p,
clkin_n, // lvds clock input
output [55:0] dummy_out,
output rx_bufg_x1,
output rx_bufpll_lock,
output ... | 7.222471 |
module top_nto1_pll_diff_tx (
input reset, // reset (active high)
input refclkin_p,
refclkin_n, // frequency generator clock input
output [5:0] dataout_p,
dataout_n, // lvds data outputs
output clkout_p,
clkout_n
); // lvds clock output
// Parameters for serdes factor and number of IO... | 7.222471 |
module fsm (
clock,
reset,
req,
gnt
);
input clock, reset;
input [1:0] req;
output [1:0] gnt;
wire clock, reset;
wire [1:0] req;
reg [1:0] gnt;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101, GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-... | 7.229634 |
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g;
wire [1:0] r;
fsm u_fsm (
.clock(clk),
.reset(rst),
.req (r),
.gnt (g)
);
assign g0 = g[0];
assign g1 = g[1];
assign r[0] = a;
assign r[1] = b;
endmodule... | 7.233807 |
module mux2 (
S,
A,
B,
Y
);
input S;
input A, B;
output reg Y;
reg a_vect[0 +: 8];
reg b_vect[0 -: 8];
//import my_pkg::*;
always @(*) Y = (S) ? B : A;
endmodule
| 7.562788 |
module top (
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle #(1'b0) u_mid1 (
.x(x),
.o(o),
.y(1'b0)
);
middle #(1'b0) u_mid2 (
.x(x),
.o(o),
.y(1'... | 7.233807 |
module middle (
input x,
input y,
output o
);
parameter Y = 1'b1;
urtl u_urtl (
.x(x),
.o(o),
.y(Y)
);
endmodule
| 6.553865 |
module urtl (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 6.943731 |
module mux16 (
D,
S,
Y
);
input [15:0] D;
input [3:0] S;
output Y;
parameter D_WIDTH = 8;
parameter S_WIDTH = 3;
localparam L = 6;
assign Y = D[S];
endmodule
| 8.26373 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
mux16 u_mux16 (
.S(S[3:0]),
.D(D[15:0]),
.Y(M16)
);
defparam u_mux16.D_WIDTH = 16; defparam u_mux16.S_DEPTH = 4;
endmodule
| 7.233807 |
module Top (
input wire clk,
output wire LED,
output wire [7:0] SEGMENT,
output wire [3:0] AN
);
wire Qa;
wire Qb;
wire Qc;
wire Qd;
wire [3:0] Hex;
/* module clk_1s at submodules/clk_1s.v */
clk_1s m0 (
.clk(clk),
.clk_1s(clk_1s)
);
/* You need to implement module Count... | 6.64497 |
module Top (
input wire clk,
input wire SW,
output wire LED,
output wire [7:0] SEGMENT,
output wire [3:0] AN
);
wire [15:0] cnt;
wire [3:0] Hex;
wire clk_100ms;
/* module clk_100ms at submodules/clk_1s.v */
clk_100ms clk_div_100ms (
.clk(clk),
.clk_100ms(clk_100ms)
);
/*... | 6.64497 |
module top (
input wire clk,
input wire ftdi_rx,
output wire ftdi_tx,
input wire board1_rx,
output wire board1_tx,
output reg led = 1'b1,
output wire [13:0] debug_header
);
// Combinatorial logic
assign board1_tx = ftdi_rx;
assign ftdi_tx ... | 7.233807 |
module to try patterns.
References:
https://www.improwis.com/tables/video.webt
https://www.kernel.org/doc/Documentation/devicetree/bindings/display/panel/panel-dpi.txt
https://www.waveshare.com/w/upload/4/44/4.3inch-480x272-Touch-LCD-B-UserManual.pdf
https://en.wikipedia.org/wiki/Color_Graphics_Adapter
Full grap... | 6.565989 |
module lpc_clkgen (
CLKIN_IN,
RST_IN,
CLKIN_IBUFG_OUT,
CLK0_OUT
);
input CLKIN_IN;
input RST_IN;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLK... | 6.650903 |
module Top_PC_Instr_Display (
input wire W_clk,
W_rst_clk,
output [31:0] W_instr
);
wire W_dived_clk;
wire [31:0] W_pc, W_next_pc;
// don't div clk when simulating...
// ClkDiv clkdiv(
// .clk(W_clk),
// .rst(W_rst_clk),
// .R_dived_clk(W_dived_clk)
// );
assign W_dived_clk ... | 8.993854 |
module top_PE_64 (
input CLK,
input RST,
input [ 7:0] io_in_a1,
input [ 18:0] io_in_b1,
input [135:0] io_in_d1,
input io_in_valid1,
input [ 5:0] io_in_control_shift1,
input io_in_control_propagate1,
output reg ... | 7.357911 |
module top_pe_8x8 (
clk,
in,
filter,
out
);
input clk;
input [127:0] in;
input [17:0] filter;
output [71:0] out;
wire [35:0] out1;
wire [35:0] out2;
wire [35:0] out3;
wire [35:0] out4;
wire [35:0] out5;
wire [35:0] out6;
pe_new_8x8 pe1 (
clk,
in[15:0],
filter[5:... | 6.526746 |
module top_PE_tb;
reg clk_tb;
reg rst_tb;
wire [2:0] pop_out_tb;
top_PE aaa (
.clk(clk_tb),
.rst(rst_tb),
.pop_out(pop_out_tb)
);
always begin
#20 clk_tb = ~clk_tb;
end
initial begin
rst_tb = 1'b0;
clk_tb = 1'b0;
#10 rst_tb = 1'b1;
#10 rst_tb = 1'b0;
#750;
... | 7.048279 |
module of the design which forms
rounds and connects KeyExpantion using pipelined
architecture
Owner : Amr Salah
*/
`timescale 1 ns/1 ps
module Top_PipelinedCipher
#
(
parameter DATA_W = 128, //data width
parameter KEY_L = 128, //key length
parameter NO_ROUNDS = 10 //num... | 8.52834 |
module Top_PipelinedCipher_tb ();
parameter DATA_W = 128; //data width
parameter KEY_L = 128; //key length
parameter NO_ROUNDS = 10; //number of rounds
parameter Clk2Q = 2; //Clk-Q delay
parameter No_Patterns = 284; //number of patterns
reg clk;
reg reset;
reg data_valid_in;
reg cipherkey_valid... | 6.741278 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_29 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n1;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n1),
.D (EN),
.Q (net24637)
);
INVX2_HVT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_28 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_27 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_26 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_25 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_24 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_23 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_22 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_21 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_20 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24637, n2;
AND2X1_HVT main_gate (
.A1(net24637),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24637)
);
INVX2_HVT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_38 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24560, n1;
AND2X1_HVT main_gate (
.A1(net24560),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n1),
.D (EN),
.Q (net24560)
);
INVX2_HVT U... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_37 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24560, n2;
AND2X1_HVT main_gate (
.A1(net24560),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24560)
);
INVX2_HVT U... | 6.575704 |
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