code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module priority (sel, code);
input [7:0] sel;
output [2:0] code;
reg [2:0] code;
always @(sel)
begin
if (sel[0]) code <= 3'b000;
else if (sel[1]) code <= 3'b001;
else if (sel[2]) code <= 3'b010;
else if (sel[3]) code <= 3'b011;
else if (sel[4]) code <= 3'b100;
else if (sel[5]) code <= ... | 6.563494 |
module lshift (
DI,
SEL,
SO
);
input [7:0] DI;
input [1:0] SEL;
output [7:0] SO;
reg [7:0] SO;
always @(DI or SEL) begin
case (SEL)
2'b00: SO <= DI;
2'b01: SO <= DI << 1;
2'b10: SO <= DI << 3;
default: SO <= DI << 2;
endcase
end
endmodule
| 7.328798 |
module top_ADC (
input rst,
input clkp,
input clkn,
input vp,
input vn
);
wire clk200;
wire dwe, den;
wire busy, drdy, eoc, eos, jtaglocked;
wire [4:0] channel;
wire [6:0] daddr;
wire [15:0] dout, din;
wire rd, wr, valid;
wire [6:0] addr;
wire [15:0] data_out, data_in;
//-----... | 6.788568 |
module top_adder (
input [2:0] A,
input [2:0] B,
output [3:0] Sum
);
wire c1, c2;
fullAdder ins1 (
.A(A[0]),
.B(B[0]),
.C(1'b0),
.Sum(Sum[0]),
.Carry(c1)
);
fullAdder ins2 (
.A(A[1]),
.B(B[1]),
.C(c1),
.Sum(Sum[1]),
.Carry(c2)
);
full... | 6.535744 |
module dffs (
input d,
clk,
pre,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, negedge pre)
if (!pre) q <= 1'b1;
else q <= d;
endmodule
| 7.692708 |
module dffr (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
| 7.053895 |
module top_all (
clk,
miso,
mosi,
sck,
cs,
rstn
);
input clk, mosi, sck, cs, rstn;
output miso;
wire [13:0] buffer_2, buffer_3, reff, dn;
s2p s2p_0 (
.mosi(mosi),
.sck(sck),
.cs(cs),
.rstn(rstn),
.clk(clk),
.buffer_2(buffer_2),
.buffer_3(buffer... | 6.536052 |
module top (
input clk_25mhz,
input ftdi_txd,
output ftdi_rxd,
output [3:0] led
);
reg [5:0] reset_cnt;
wire resetn = &reset_cnt;
always @(posedge clk_25mhz) begin
reset_cnt <= reset_cnt + !resetn;
end
altair machine (
.clk(clk_25mhz),
.reset(~resetn),
.rx(ftdi_txd),
... | 7.233807 |
module mux2 (
S,
A,
B,
Y,
Y1
);
input S;
input A, B;
output reg Y, Y1;
always_ff @(*) Y = (S) ? B : A;
always_latch Y1 = (~S) ? B : A;
endmodule
| 7.562788 |
module top (
input [1:0] x,
input [1:0] y,
input [1:0] z,
input clk,
input A,
output reg B
);
initial begin
B = 0;
end
always @(posedge clk) begin
if (x || y && z) B <= A & z;
if (x || y && !z) B <= A | x;
end
endmodule
| 7.233807 |
module top_arch (
output wire [15:0] out,
output wire En,
input [7:0] data1,
data2,
data3,
data4,
data5,
data6,
data7,
input reset,
clk,
load
);
wire [7:0] I, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16;
wire out0,out1,out2,out3,out4,out5,out... | 7.921453 |
module middle (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 6.553865 |
module top (
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle u_mid1 (
.x(x),
.A(o),
.y(1'b0)
);
middle u_mid2 (
.x(x),
.A(o),
.y(1'b1)
);
middl... | 7.233807 |
module adff (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.089232 |
module adffn (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
| 7.422273 |
module dffe (
input d,
clk,
en,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk) if (en) q <= d;
endmodule
| 7.085902 |
module dffsr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge pre, posedge clr)
if (clr) q <= 1'b0;
else if (pre) q <= 1'b1;
else q <= d;
endmodule
| 6.804969 |
module ndffnsnr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(negedge clk, negedge pre, negedge clr)
if (!clr) q <= 1'b0;
else if (!pre) q <= 1'b1;
else q <= d;
endmodule
| 7.273757 |
module top (
input clk,
input clr,
input pre,
input a,
output b,
b1,
b2,
b3,
b4
);
dffsr u_dffsr (
.clk(clk),
.clr(1'b1),
.pre(pre),
.d (1'b0),
.q (b)
);
ndffnsnr u_ndffnsnr (
.clk(clk),
.clr(clr),
.pre(1'b0),
.d (1... | 7.233807 |
module top_async_fifo #(
parameter DATAIN_WIDTH = 10'd16, //input data's width, must equel to RAM's width
parameter DATAOUT_WIDTH = 10'd32 //output data's width
) (
input w_clk,
r_clk,
input w_rst,
r_rst,
input w_en,
r_en,
... | 8.11541 |
module mux2 (
S,
A,
B,
Y
);
input S;
input A, B;
output reg Y;
always @(*) Y = (S) ? B : A;
endmodule
| 7.562788 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
task automatic do_things;
input [31:0] number_of_things;
reg [31:0] tmp_thing;
endtask
endmodule
| 7.233807 |
module top_a_e115fb (
input clk,
input ext_rst_n,
output reg [3:0] led_n
);
`include "macros/direction.vh"
reg [2:0] int_rst_cnt = 0;
always @(posedge clk) begin
if (int_rst_cnt != 3'b111) int_rst_cnt <= int_rst_cnt + 1;
end
wire int_rst_n = int_rst_cnt == 3'b111;
wire rst_n = int_rst_n ... | 7.328185 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'BASIC_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared lib... | 7.358787 |
module top (
input [15:0] data,
input [2:0] load, //{opcode,y,x}
input clk,
input reset,
output [3:0] anode,
output [6:0] seg,
output [15:0] leds_out
);
wire [15:0] alu_out;
wire [15:0] display_out;
assign leds_out = alu_out;
assign display_out = alu_out;
top_data_alu alu (
... | 7.233807 |
module top_bitmap_gen (
input clk,
rst_n,
input [3:0] key,
output [4:0] vga_out_r,
output [5:0] vga_out_g,
output [4:0] vga_out_b,
output vga_out_vs,
vga_out_hs
);
wire clk_out;
wire video_on;
wire [11:0] pixel_x, pixel_y;
dcm_25MHz m0 ( // Clock in ports
.clk (clk), ... | 7.162416 |
module top_bizhng (
clk,
rst,
echo,
trig,
dianji2,
flag,
echo2,
trig2,
data_rx,
RX232,
led1,
led0,
jiaodu,
led4,
led5,
led6,
led7,
flag1
);
input clk;
input rst;
input echo;
input echo2;
input flag;
input data_rx;
output RX232;
outp... | 6.592085 |
module top_blackice2 (
input wire clk100,
output wire [ 3:0] LED,
output wire UART_TX,
input wire UART_RX,
output wire RAMOE,
output wire RAMWE,
output wire RAMCS, // SRAM pins
output wire RAMLB,
output wire RAMUB,
outp... | 7.049922 |
module top_blk #(
parameter KERNEL_SIZE = `KERNEL_SIZE,
parameter FM_SIZE = `FM_SIZE,
parameter PADDING = `PADDING,
parameter STRIDE = `STRIDE,
parameter MAXPOOL = `MAXPOOL,
parameter IN_FM_CH = `IN_FM_CH,
parameter OUT_FM_CH = `OUT_FM_CH,
localparam OUT_SIZE... | 7.692328 |
module top_white_block_mean (
input clk,
input rstn,
input de,
input hs,
input vs,
input [7:0] rgb_r,
input [7:0] rgb_g,
input [7:0] rgb_b,
output [7:0] block_mean_white,
output data_vaild_white,
output [5:0] block_v_cnt
);
// RGB to Gr... | 8.173112 |
module to instantiate the datapath and controller
// of BOOTH MULTIPLIER
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_BOOTH(
output wire done,
output wir... | 7.261131 |
module TOP_BUS_ARB (
//Common I/O
input wire RST,
CLK,
input wire HREADY,
//Arbiter I/O
input wire HLOCK_1,
HLOCK_2,
input wire HREQ_1,
HREQ_2,
input wire [1:0] HSPLIT,
output wire HGRANT_1,
HGRANT_2,
output wire [1:0] HMAS,
output wire MLOCK,
//BUS I/O... | 7.687923 |
module top_button (
btn_in,
clk,
rst_n,
p_out
);
//This is the wrapper or top module for push button it includes synchronizer debouncer and level 2 pulse convertor
input btn_in, clk, rst_n;
output p_out;
wire b_w, db_w;
synchronizer Sync1 (
.async_in(btn_in),
.clk(clk),
.r... | 8.82249 |
module top_calling (
input clk,
input rst_n,
input calling_sent_en_cheng, //打电话使能，连接按键
input calling_sent_en_zhi, //第二个紧急联系人
output calling_tx
);
wire bps_sig;
wire cnt_start;
wire rx_int;
wire [ 7:0] data1;
wire [47:0] ymr_out;
wire [47:0] time_out;
wire ... | 6.664888 |
module top (
input x0,
x1,
input y0,
y1,
input cin,
output A0,
A1,
output cout
);
wire cout0;
assign {cout0, A0} = cin + y0 + x0;
assign {cout, A1} = cout0 + y1 + x1;
endmodule
| 7.233807 |
module tristate (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) begin
case (en)
1: o <= i;
default: o <= 1'bZ;
endcase
end
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(en),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module mux2 (
S,
A,
B,
Y
);
input S;
input A, B;
output reg Y;
always @(*) Y = (S) ? B : A;
endmodule
| 7.562788 |
module mux8 (
S,
D,
Y
);
input [2:0] S;
input [7:0] D;
output Y;
reg Y;
wire [2:0] S;
wire [7:0] D;
always @* begin
casex (S)
0: Y = D[0];
1: Y = D[1];
2: Y = D[2];
3: Y = D[3];
4: Y = D[4];
5: Y = D[5];
6: Y = D[6];
7: Y = D[7];
endca... | 7.239309 |
module mux16 (
D,
S,
Y
);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
| 8.26373 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
mux2 u_mux2 (
.S(S[0]),
.A(D[0]),
.B(D[1]),
.Y(M2)
);
mux4 u_mux4 (
.S(S[1:0]),
.D(D[3:0]),
.Y(M4)
);
mux8 u_mux8 (
.S(S[2:0]),
.D(D[7:0]),
.Y(M8)
);
... | 7.233807 |
module top_checkered (
input wire clk_25mhz,
output wire oled_csn,
output wire oled_clk,
output wire oled_mosi,
output wire oled_dc,
output wire oled_resn
);
// checkered red green blue red green blue
wire [15:0] color = x[3] ^ y[3] ? {5'd0, x[6:1], 5'd0} :... | 6.561331 |
module top_clock (
rst,
inclk,
sec_seg1,
sec_seg10,
min_seg1,
min_seg10,
hour_seg1,
hour_seg10
);
input rst, inclk;
output wire [6:0] sec_seg1, sec_seg10;
output wire [6:0] min_seg1, min_seg10;
output wire [6:0] hour_seg1, hour_seg10;
wire sec_clk, min_clk, hour_clk;
freq... | 7.457114 |
module mux16 (
D,
S,
Y
);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
| 8.26373 |
module top (
input [3:0] S,
input [15:0] D,
output M16
);
mux16 u_mux16 (
.S(S[3:0]),
.D(D[15:0]),
.Y(M16)
);
endmodule
| 7.233807 |
module top_color (
input clk,
output reg s2,
output reg s3,
output reg [2:0] color,
input ip_signal
);
wire [7:0] count;
reg [2:0] color_temp;
freq_counter(
.clk(clk), .ip_signal(ip_signal), .count(count)
);
reg [7:0] r_freq;
reg [7:0] g_freq;
reg [7:0] b_freq;
reg [32:0] del... | 6.57371 |
module top (
input clk,
input [15:0] I0,
input [15:0] I1,
output reg A,
B,
C,
D,
E,
F
);
always @(posedge clk) begin
if (I0 < I1) A <= 1'b1;
else A <= 1'b0;
if (I0 <= I1) B <= 1'b1;
else B <= 1'b0;
if (I0 != I1) C <= 1'b1;
else C <= 1'b0;
if (I0 === ... | 7.233807 |
module top (
input [7:0] data_a,
data_b,
input [0:0] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clka,
clkb,
output reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always... | 7.233807 |
module top (
input x,
input [1:0] y,
input z,
output [1:0] A,
output [2:0] B,
output [3:0] C
);
assign A = {x, z};
assign B = {x, y};
assign C = {x, y, z};
endmodule
| 7.233807 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
reg b, c = 1.01;
wire a;
endmodule
| 7.233807 |
module replication_operator ();
reg [3:0] r_VAL_1 = 4'b0111;
parameter c_MULTIPLIER = 4'b0010;
parameter WIDTH = 1;
wire [WIDTH-1:0] connection;
generate
if (WIDTH > 1) begin
assign connection = {{WIDTH - 1{1'b0}}, 1'b1};
end else begin
assign connection = 1'b1;
end
endgenerate
... | 6.74185 |
module Shift (
A,
Y1,
Y2
);
input [7:0] A;
output [7:0] Y1, Y2;
parameter B = 3;
reg [7:0] Y1, Y2;
always @(A) begin
Y1 = A << B; //logical shift left
Y2 = A >> B; //logical shift right
end
endmodule
| 6.947224 |
module SShift (
A,
Y1,
Y2
);
input [7:0] A;
output [7:0] Y1, Y2;
parameter B = 3;
reg [7:0] Y1, Y2;
always @(A) begin
Y1 = A <<< B; //logical shift left
Y2 = A >>> B; //logical shift right
end
endmodule
| 7.020674 |
module top (
input signed x,
input signed [1:0] y,
input signed z,
output signed [1:0] A,
output signed [2:0] B,
output signed [3:0] C
);
assign A = {x, z};
assign B = {x, y};
assign C = {x, y, z};
endmodule
| 7.233807 |
module tristate (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) o <= (en) ? i : 1'bZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(1'b0),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module tristate (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) o <= (en) ? i : 1'bZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(1'b1),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module tristate (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) o <= (en) ? i : 1'bZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(en),
.i (1'b0),
.o (b)
);
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin,
output reg A,
output reg cout,
output X
);
wire bb_out;
initial begin
A = 0;
cout = 0;
end
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
assign X = 1'bX;
bb ubb (
ci... | 7.233807 |
module top_control (
input clk,
input rst,
// is selecting
input selecting,
// game
input mode,
output reg timer_start,
output reg countdown_en,
// supervise
input [9:0] sec,
input win,
output reg timed_win,
// end
output reg timer_endn,
output reg [1:0] mask... | 7.478001 |
module top_conv (
clk,
in,
filter,
out
);
input clk;
input [49:0] in;
input [17:0] filter;
output [17:0] out;
mac_new mac1 (
clk,
{in[25:20], in[15:10], in[5:0]},
filter,
out[1:0]
);
mac_new mac2 (
clk,
{in[27:22], in[17:12], in[7:2]},
filter,
... | 6.544201 |
module top_conv_8x8 (
clk,
in,
filter,
out
);
input clk;
input [127:0] in;
input [17:0] filter;
output [71:0] out;
/*
mac_new mac1(clk,{in[25:20],in[15:10],in[5:0]},filter,out[1:0]);
mac_new mac2(clk,{in[27:22],in[17:12],in[7:2]},filter,out[3:2]);
mac_new mac3(clk,{in[29:24],in[19:14],in[9:4]... | 7.192202 |
module top_cordic_rot #(
parameter COUNT_WIDTH = 4, // Counter width
parameter WIDTH = 16, // do rong du lieu cua goc
parameter WIDTH_WIRE = 18 //data width
) (
input clk,
input start,
input rst_n,
i... | 7.861358 |
module top_count (
input wire clk,
input wire rst_i,
input btn_up_i,
output [6:0] ssd_o,
output sel_o,
output wire led0
);
// Local wires and regs
wire [6:0] num_display;
//ssd instantiation
ssd ssd1 (
.clk (clk),
.rst_i(rst_i),
.num_i(num_display),
.a2g_o(ss... | 8.177711 |
module top_counter (
input clk,
input rst,
input [ 3:0] pulse,
input en_count,
output [15:0] count1,
output [15:0] count2,
output [15:0] count3,
output [15:0] count4
);
// pulse[0] ļģ
counterfour counter_check1 (
.clk (clk),
.rst (rst),
... | 6.954323 |
module top_counter_16 (
input clk,
input rst,
input [15:0] pulse,
input en_count,
output [15:0] count1,
output [15:0] count2,
output [15:0] count3,
output [15:0] count4,
output [15:0] count5,
output [15:0] count6,
output [15:0] count7,
output [15:... | 6.561184 |
module top_cpu (
input clk, // clk100mhz
input rstn, // cpu_resetn
input step, // btnu
input cont, // btnd
input chk, // btnr
input data, // btnc
input del, // btnl
input [15 : 0] x, // sw15-0
output [3:0] VGA_R,
output [... | 6.986331 |
module tristate (
en,
i,
o
);
input en;
input i;
output [1:0] o;
wire [1:0] io;
assign io[0] = (en) ? i : 1'bZ;
assign io[1] = (i) ? en : 1'bZ;
assign o = io;
top utop (
en,
i,
o,
io
);
endmodule
| 6.741184 |
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en(en),
.i (a),
.o (c)
);
endmodule
| 7.233807 |
module top_cyclone_four_de2_115 #(
parameter PROG_ADDR_WIDTH = 11,
parameter PROG_DATA_WIDTH = 3,
parameter MEM_ADDR_WIDTH = 16,
parameter MEM_DATA_WIDTH = 9,
parameter PROGRAM_NAME = "../prog/beer.txt"
) (
input CLOCK_50,
input [3:0] SW,
output [17:0] LEDR,
output [8:0] LEDG,
... | 7.245591 |
module Top_cymometer (
input sys_clk,
input rst_n,
input clk_fx,
input nCS,
//input MOSI,
input SCK,
output MISO,
output MISO_2,
output SCK_2,
output nCS_2
);
assign SCK_2 = SCK;
assign MISO_2 = MISO;
assign nCS_2 = nCS;
wire sys_clk_h;
/*
Clk_fx_generator... | 7.219359 |
module top_czcjj (
input sys_clk,
input reset_n,
input [2:0] key, //3个按键输入
output [3:0] seg_sel, //位选
output [7:0] seg_led //段选
);
wire sys_reset_n;
wire [7:0] data_s;
wire [7:0] data_m;
wire [4:0] second_point;
wire [15:0] dis_data;
wire [4:0] dis_point;
wire cha... | 7.307694 |
module TOP_Data_control (
i_clk,
data_input,
start,
out_ACC_reg,
out_A_reg,
out_B_reg,
A_out,
p_STATE,
done
);
input i_clk;
input start;
input [`DATA_WIDTH-1:0] data_input;
output [`DATA_WIDTH-1:0] out_ACC_reg;
output [`DATA_WIDTH-1:0] out_A_reg;
output [`DATA_WIDTH-1:0] ... | 8.362122 |
module Top_Data_control_tb ();
reg i_clk;
reg start;
reg [`D_WIDTH-1:0] data_input;
wire [`D_WIDTH-1:0] out_ACC_reg;
wire [`D_WIDTH-1:0] out_A_reg;
wire [`D_WIDTH-1:0] out_B_reg;
wire [`D_WIDTH-1:0] Data_out;
wire [`D_WIDTH-1:0] Data_out1;
wire [`State_WIDTH-1:0] p_STATE;
wire A_out;
wire done;
... | 7.427108 |
module top_data_selector (
input [7:0] dat,
input [2:0] addr,
output out
);
case_data_selector u_data_selector (
.dat (dat),
.addr(addr),
.out(out)
);
endmodule
| 7.868438 |
module top_dcmctrl (
output LED1_1,
output LED1_2,
input clk,
output INT,
input SPI_CS,
input SPI_CLK,
input SPI_MOSI,
output SPI_MISO,
output SLOT1_IO0, //PWM_A (1)
output SLOT1_IO1, //PWM_B (1)
output SLOT1_IO2, //PWM_C (1)
output SLOT1_IO3, //PWM_D (1)
output SLOT1_IO4, //RESET_AB (1)
ou... | 6.976251 |
module top_dc_func (
input i_clk,
i_reset,
input [2:0] i_mode,
output o_ma,
o_mb,
o_fin,
o_pwm,
output [3:0] o_fndSel,
output [7:0] o_fndData
);
wire w_clk_1hz;
wire [7:0] w_rtime, w_ocr;
clock_divider D1 (
.i_clk (i_clk),
.i_reset(i_reset),
.o_clk (w_clk_... | 7.374222 |
module top_dds (
input wire sys_clk, //系统时钟,50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire [3:0] key, //输入4位按键
output wire dac_clk, //输入DAC模块时钟
output wire [7:0] dac_data //输入DAC模块波形数据
);
//********************************************************************//... | 6.71743 |
module top_de0_nano (
input clk,
input ext_rst_n,
output reg [7:0] led
);
`include "macros/direction.vh"
reg [2:0] int_rst_cnt = 0;
always @(posedge clk) begin
if (int_rst_cnt != 3'b111) int_rst_cnt <= int_rst_cnt + 1;
end
wire int_rst_n = int_rst_cnt == 3'b111;
wire rst_n = int_rst_n &&... | 6.818493 |
module top_debounce (
bounce_in,
clk,
rst_n,
debounce_out
);
// This is wrapper for switch debouncing it includes counter for 20ms and FSM for debouncing
input bounce_in, clk, rst_n;
output debounce_out;
wire cnt_w, strt_w;
sm_debounce SM_de_1 (
.clk(clk),
.rst_n(rst_n),
... | 8.164812 |
module top_decoder_3_8 (
input [2:0] addr,
output [7:0] out
);
//case_decoder_3_8 u_decoder_3_8 (
logic_decoder_3_8 u_decoder_3_8 (
.addr(addr),
.out (out)
);
endmodule
| 7.106269 |
module top_default_BUFF_ASYNC_W1_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input D;
output Q;
reg Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W1_D1_S1 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input D;
output Q;
reg Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W2_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input [1:0] D;
output [1:0] Q;
reg [1:0] Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 2'b00;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W3_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input [2:0] D;
output [2:0] Q;
reg [2:0] Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 3'b000;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W4_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input [3:0] D;
output [3:0] Q;
reg [3:0] Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 4'b0000;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W5_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input [4:0] D;
output [4:0] Q;
reg [4:0] Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 5'b00000;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W12_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input [11:0] D;
output [11:0] Q;
reg [11:0] Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 12'b000000000000;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top (
input x
);
endmodule
| 7.233807 |
module tristate (
en,
i,
io,
o
);
input en;
input i;
inout [1:0] io;
output [1:0] o;
reg [1:0] io_buf;
assign io = io_buf;
always @(en or i) io_buf[0] <= (en) ? i : 1'bZ;
always @(en or i) io_buf[1] <= (i) ? en : 1'bZ;
assign o = (en) ? io : 2'bZZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en(en),
.i (a),
.io(b),
.o (c)
);
endmodule
| 7.233807 |
module Top_design (
input i_clk,
input i_rst,
input incr,
input decr,
output [`SEG_WID-1:0] o_seg_en,
output an_seg,
output [`SEG_WIDTH-1:0] Sseg_out
);
assign an_seg = 1'b1;
wire [3:0] seg_out;
reg p_state;
reg [`N_WIDTH-1:0] digit0, digit1;
//reg [`COUNT_WIDTH-1:0] cnt_clr ;
r... | 7.586592 |
module top_design_file (
clk,
rst,
data_in,
data_out
, state,
Reg1,
Reg2,
Reg3
);
input clk, rst;
output [3:0] Reg1, Reg2, Reg3;
output [3:0] data_out;
input [3:0] data_in;
output [1:0] state;
wire ldr_1, ldr_2, ldr_3, sel_1;
wire [1:0] sel_2;
data_path DATAPATH (
c... | 7.146233 |
module top_design_file_TB ();
reg [3:0] data_in;
reg clk, rst;
wire [3:0] data_out, Reg1, Reg2, Reg3;
wire [1:0] state;
top_design_file DUT (
clk,
rst,
data_in,
data_out
, state,
Reg1,
Reg2,
Reg3
);
always #10 clk = ~clk;
initial begin
#0 clk = 0;
... | 7.146233 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top_design_module(
input i_clk,
input i_sele... | 7.088073 |
module
// Module Name: /home/ise/xilinx/Blinking_leds/Top_design_module_tb.v
// Project Name: Blinking_leds
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Top_design_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Addition... | 6.999332 |
module Top_design_tb ();
reg clk, rst_n, d_in;
wire out_mealy;
wire mealy_glitch_free;
wire [`S_WIDTH-1:0] p_STATE;
/////instantiation of design block/////
TOP_design DUT (
clk,
rst_n,
d_in,
out_mealy,
p_STATE,
mealy_glitch_free
);
//setting default value of clk and... | 7.863409 |
module dff (
input d,
clk,
output reg q
);
always @(posedge clk) q <= d;
endmodule
| 7.174483 |
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