code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_17 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_16 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_15 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_14 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_13 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_12 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_11 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_10 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_9 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_8 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_7 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_6 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_5 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_4 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_3 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_value_correct_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24210, n2;
AND2X1_HVT main_gate (
.A1(net24210),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24210)
);
INVX2_HVT U1 (... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_value_correct_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24210, n2;
AND2X1_HVT main_gate (
.A1(net24210),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24210)
);
INVX2_HVT U1 (... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_0 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n1;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n1),
.D (EN),
.Q (net24014)
);
INV... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_35 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_34 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_33 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_32 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_31 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_30 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_29 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_28 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_27 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_26 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_25 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_18 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_17 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_16 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_15 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_14 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_13 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_12 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_11 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_10 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
IN... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_9 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INV... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_8 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INV... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_7 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INV... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_6 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INV... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_5 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INV... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_4 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INV... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_3 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INV... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INV... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INV... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_0 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n1;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n1),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_12 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_11 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_10 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_9 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_8 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_7 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_6 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_5 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_4 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_3 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
... | 6.575704 |
module top_pong_animated (
input clk,
rst_n,
input [1:0] key, //key[1] to move down,key[0] to move up
output [4:0] vga_out_r,
output [5:0] vga_out_g,
output [4:0] vga_out_b,
output vga_out_vs,
vga_out_hs
);
wire clk_out;
wire video_on;
wire [11:0] pixel_x, pixel_y;
dcm_25MHz m0... | 7.924382 |
module top_poola_S2_K2 #(
parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
///////////architecture parameters//////
IFM_SIZE = 28,
IFM_DEPTH = 6,
ARITH_TYPE = 0,
KERNAL_SIZE = 2,
//////////////////////////////////////
IFM_SIZE_NEXT = (IFM_SIZE - KERNAL_SIZE) / ... | 7.060616 |
module top_poolb_U2_S2_K2 #(
parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
///////////architecture parameters//////
IFM_SIZE = 10,
IFM_DEPTH = 16,
KERNAL_SIZE = 2,
ARITH_TYPE = 0,
NUMBER_OF_UNITS = 2,
//////////////////////////////////////
NUMBER_OF_IFM_... | 6.696576 |
module top_poolb_U3_S2_K2 #(
parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
///////////architecture parameters//////
IFM_SIZE = 26,
IFM_DEPTH = 18,
KERNAL_SIZE = 2,
ARITH_TYPE = 0,
NUMBER_OF_UNITS = 3,
//////////////////////////////////////
NUMBER_OF_IFM_... | 6.807844 |
module top_poolb_U6_S2_K2 #(
parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
///////////architecture parameters//////
IFM_SIZE = 10,
IFM_DEPTH = 16,
KERNAL_SIZE = 2,
ARITH_TYPE = 0,
NUMBER_OF_UNITS = 6,
//////////////////////////////////////
NUMBER_OF_IFM_... | 6.594255 |
module top (
input x,
input y,
input cin,
output A,
output cout,
output signed pow,
output signed pow2
);
wire p, n;
assign pow = 2 ** y;
assign pow2 = 2 ** 2;
assign p = +x;
assign n = -x;
assign A = cin * x;
endmodule
| 7.233807 |
module Top_Processor_Module (
input [7:0] data_in,
input clk,
input interrupt,
input reset,
output [7:0] data_out
);
wire [23:0] ins;
wire [7:0] A;
wire [7:0] B;
wire [7:0] Current_Address;
wire [7:0] ans_ex;
wire [7:0] ans_dm;
wire [7:0] ans_wb;
wire [1:0] mux_sel_A;
wire [1:0] m... | 8.045154 |
module: Top_Processor_Module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_Processor_Module_tb;
// Inputs
reg [7:0] data_in;
reg clk;
reg interrupt;
reg reset;
// Outpu... | 7.460419 |
module tristate (
en,
i,
o
);
input en;
input i;
output o;
assign o = (en) ? i : 1'bZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(en),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module Top_prueba_botones_VGA (
input wire clk,
input wire reset,
input wire [3:0] sw, //3 interruptores
input wire [3:0] btn, //4 botones
output wire hsync,
vsync,
output wire [11:0] RGB
);
wire [3:0] sw_db; //debounce
wire [3:0] btn_db; //debounce
wire [3:0] digit0_HH, digit1_H... | 7.632171 |
module TOP_test_2 (
input wire clk,
input wire entrada_PWM,
input wire C_valid_PWM,
input wire PWM_select,
output wire ready,
output wire PWM_signal
);
PWM PWM_real (
//entradas
.clk(clk),
.data(entrada_PWM),
.select(PWM_select),
.PWM_valid_I(C_valid_PWM),
... | 8.495523 |
module top_pwm_gen (
input i_clk,
i_reset,
input [7:0] i_ocr,
output o_pwm
);
wire w_clk_1M;
wire [7:0] w_cnt;
clockDivider #(
.MAX_COUNT(50)
) D0 (
.i_clk (i_clk),
.i_reset(i_reset),
.o_clk (w_clk_1M)
);
counter D1 (
.i_clk (w_clk_1M),
.i_reset(i_re... | 7.327685 |
module top_pwm_ScRomPc (
pwm_gen,
push_btn,
tp_clk,
tp_rst
);
input push_btn, tp_clk, tp_rst;
output pwm_gen;
wire [2:0] w_sel_dec; //Connects "sel" & "sel_dec".
selection_counter m_sc1 (
.sel (w_sel_dec),
.clk (tp_clk),
.rst_n(tp_rst),
.pb_in(push_btn)
);
wire [... | 8.190166 |
module top_qam #(
parameter width_data = 16,
parameter wid_count = 4,
parameter No_reg = 16
) (
input clk,
input rst_n,
input rst_clk,
input start,
input data_in,
output [width_data-1:0] data_tr... | 7.727441 |
module top_qam_receiver #(
parameter width_data = 16,
parameter width_reg = 18,
parameter COUNT_WIDTH = 4,
parameter kp = 0.026, //0.0000011010100111 6 7 9 11 14 15 16
parameter ki = 0.00069, //0.00000000001011010011
parameter k = 0.02531 //kp-ki=0.0000011001111010 6 7 10 11 12 13 15
) (
... | 6.869751 |
module Read_Channel #(
parameter IDW = 12, // ID
parameter AW = 32, // Addr
parameter DW = 32
) (
input clk, // global clock signal.
input resetn, // global reset singal.
//Read address channel
input [AW-1 : 0] araddr_in,
input [ 7 : 0] arlen_in,
... | 6.97705 |
module top_race_game (
input wire clk,
reset,
ps2d,
ps2c,
output wire hsync,
vsync,
output wire [11:0] rgb_out,
output pwm,
aud_on
);
//variables
wire left_key, right_key, enter_key, key_relese, game_reset;
wire video_on, p_tick, road_on, finish_line, car_on, start_en, crash_e... | 8.773083 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module top_ram2port (
input [17:0] SW,
input [ 1:0] KEY,
input CLOCK_50,
output [17:0] LEDR,
output [ 7:0] LEDG,
input UART_RXD
);
wire [7:0] rx_data;
wire rx_done;
rx_controller rx (
.clk(CLOCK_50),
.UART_RXD(UART_RXD),
.RX_DATA(rx_data),
.RX_DO... | 6.923214 |
module top_read_id (
input clk,
input spi_miso,
output uart_tx,
output spi_clk,
output spi_cs,
output spi_mosi
);
wire clk;
wire spi_miso;
// UART Section ---------------------------------------------------
reg uart_baud_clk_enable = 1;
wire baud_clk;
reg uart_send_enable = 1;
... | 8.022287 |
module top_read_write_ts #(
parameter PLATFORM = "MODELSIM"
) (
input clk,
input rst_n,
input [31:0] local_clock,
input [3:0] host_r8_id,
input [3:0] host_wr8_id,
input [7:0] RXD_08,
input RXDV_08,
output wire [7:0] TXD_08,
output wire TX_EN_08
);
//wire [7:0] r2b00,r2b0... | 6.806056 |
module top_receptor (
input iClk,
input iReset,
input iDatos,
output oDatos,
output [3:0] Anode,
output [6:0] ovDisplay
);
wire [7:0] wv_ASCII0;
wire [7:0] wv_ASCII1;
wire [7:0] wv_ASCII2;
wire [7:0] wv_ASCII3;
wire [6:0] wvDisplay0;
wire [6:0] wvDisplay1;
wire [6:0] wvDisplay2;
... | 7.481353 |
module top (
x,
clk,
rst,
a
);
output x;
reg x;
input clk;
input [2:0] rst;
input [1:0] a;
wire rst_or;
assign rst_or = |rst;
always @(posedge clk, negedge rst_or) begin : DESIGN_PROCESSOR
reg i;
if (!rst_or) begin
i = 0;
x = 0;
end else begin
case (a)
... | 6.963493 |
module top (
input clk,
input rst,
input [31:0] in_count,
input in_valid,
output in_ready,
input out_ready,
output out_valid
);
reg [31:0] r_remaining_count;
reg r_valid;
reg r_ready;
assign out_valid = r_valid;
assign in_ready = r... | 7.233807 |
module dut (
input fast_clk,
slow_clk,
input [3:0] waddr,
raddr,
input [3:0] wdata,
input wen,
output [3:0] rdata
);
reg [3:0] mem[0:15];
reg [3:0] raddr_reg;
always @(posedge fast_clk) begin
if (wen) mem[waddr] <= wdata;
end
always @(posedge slow_clk) raddr_reg <= raddr;
... | 7.120761 |
module top_control (
input clk,
reset_ctrl,
output reg carry_ctrl
);
// There is still a problem to deal with that is the gap between Stage 2 and Stage 3.
// The stage 2 requires the output_range everytime in order to execute some equations.
// However, right the output_range (output_range[v[i-1]]) ... | 7.478001 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'REG_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared libra... | 7.358787 |
module top_reloj_digital (
input clk,
input reset,
input wire [3:0] sw_Nexys, //Modo configuracin (x3), formato_hora
input wire [4:0]btn_Nexys,//Botones de desplazamiento en la configuracin (x4), desactivar alarma timer
inout [7:0] dato_RTC,
output a_d,
output cs,
output rd,
outpu... | 8.099832 |
module top #(
parameter N = 8
) (
input wire clk,
reset,
input wire s_in,
output wire s_out
);
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
always @(posedge clk, negedge reset) begin
if (~reset) r_reg <= 0;
else r_reg <= r_next;
end
assign r_next = {s_in, r_reg[N-1:1]};
assign ... | 7.964012 |
module Top_RISC (
input clk,
input rst,
input [31:0] InsR
);
wire mem_wr_valid;
wire [ 2:0] mem_func3;
wire mem_rd;
wire data_ready;
wire [31:0] to_data_mem;
wire [31:0] data_mem_addr;
wire [31:0] from_data_mem;
core coreRISCV (
.from_ins_mem(InsR),
.... | 6.851285 |
module top_riscv_wrapper_tb ();
reg clk, rst;
reg [15:0] sw;
wire [15:0] led;
wire [ 6:0] seg;
wire [ 3:0] an;
top_riscv_wrapper DUT (
.clk (clk),
.btnU(rst),
.sw (sw),
.led (led),
.seg (seg),
.an (an)
);
parameter clock_period = 15;
always #(clock_period / 2)... | 8.514135 |
module top_riscv_wrapper_int_tb ();
reg clk, rst;
reg [15:0] sw;
wire [15:0] led;
wire [ 6:0] seg;
wire [ 3:0] an;
top_riscv_wrapper DUT (
.clk (clk),
.btnU(rst),
.sw (sw),
.led (led),
.seg (seg),
.an (an)
);
reg rst_f;
reg [15:0] sw_f, led_f;
reg [3:0] an_f;... | 8.514135 |
module top_risc_proc (
input clk,
reset
);
wire w_memWrite, w_memRead, w_PCop, w_checkbranch;
wire [12:0] w_instruction, w_ALUresult, w_dataA, w_dataB, w_PCcurr, w_PC;
wire [8:0] w_branch;
wire [3:0] w_opcode;
wire [2:0] w_regDest, w_regAddress1, w_regAddress2;
PC u0 (
.clk(clk),
.res... | 7.070053 |
module is top row reg array buffer for
* storing top row data of input feature map.
--------------------------------------------------*/
module top_row_reg_array
endmodule
| 6.693672 |
module top_rs232 (
input CLOCK_50,
input UART_RXD,
input [1:0] KEY,
input [7:0] SW,
output [7:0] LEDR,
output UART_TXD
);
wire RE, WE, KEY_1_DB, KEY_0_DB;
controller controller (
.clk(CLOCK_50),
.UART_RXD(UART_RXD),
.UART_TXD(UART_TXD),
.RE(RE),
.WE(... | 7.80151 |
module top_rs_hip (
// inputs:
dlup_exit,
hotrst_exit,
l2_exit,
ltssm,
npor,
pld_clk,
test_sim,
// outputs:
app_rstn,
crst,
srst
);
output app_rstn;
output crst;
output srst;
input dlup_exit;
input hotrst_exit;
input l2_exit;
input [4:0] ltssm;
input npo... | 7.303665 |
module top_R_cpu (
input rst,
input clk,
output ZF,
output OF,
output [31:0] F
);
reg write_reg;
wire [31:0] Inst_code;
wire [31:0] R_Data_A;
wire [31:0] R_Data_B;
reg [2:0] ALU_OP;
pc pc_connect (
clk,
rst,
Inst_code
);
Register_file R_connect (
Inst_code[25:... | 6.701564 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.