code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top (
input rx,
output tx,
output sync
);
wire clk;
SB_HFOSC #(
.CLKHF_DIV("0b10")
) u_SB_HFOSC (
.CLKHFPU(1),
.CLKHFEN(1),
.CLKHF (clk)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
... | 7.233807 |
module top_sd_rw (
input sys_clk,
input sys_rst_n,
// sdӿ
input sd_miso,
output sd_clk,
output sd_cs,
output sd_mosi,
//LED
output [3:0] led
);
//wire define
wire clk_ref;
wire clk_ref_180deg;
wire rst_n;
wire locked;
wire wr_start_... | 6.50141 |
module top_secseg (
rst,
inclk,
seg1,
seg10
);
input rst, inclk;
output wire [6:0] seg1, seg10;
wire [5:0] sec_val;
sec_cnt counter (
rst,
inclk,
sec_val
);
sec_conv converter (
rst,
sec_val,
seg1,
seg10
);
endmodule
| 7.503114 |
module top_seg_595 (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号，低电平有效
output wire stcp, //输出数据存储寄时钟
output wire shcp, //移位寄存器的时钟输入
output wire ds, //串行数据输入
output wire oe //输出使能信号
);
//********************************************************************//
//... | 8.133576 |
module Top_sensor (
clk_50m,
rst,
Trig_l,
Trig_r,
Trig_f1,
Trig_f2,
Echo_l,
Echo_r,
Echo_f1,
Echo_f2,
seven_seg_out,
Select,
stop,
backward,
turn_left,
turn_right,
state,
run
);
input clk_50m, rst;
input Echo_l, Echo_r, Echo_f1, Echo_f2;
outp... | 6.707173 |
module top_sft;
wire tb_sim_rst; // simulation only reset
wire clk12m; // 12 mhz clock
wire [4:0] leds; // lattice leds
wire [7:0] tb_rx_data;
wire tb_rx_data_rdy;
wire [7:0] la_tx_data;
wire la_tx_data_rdy;
latticehx1k latticehx1k (
.sd(),
.clk_in(clk12m),
... | 7.211458 |
module top (
input signed x,
input signed y,
input signed cin,
output signed A,
output signed cout,
output signed B,
C
);
assign A = y >> x;
assign cout = y + A >>> y;
assign {B, C} = {cout, A} << 1;
endmodule
| 7.233807 |
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock, reset, req_0, req_1;
output signed gnt_0, gnt_1;
wire clock, reset, req_0, req_1;
reg gnt_0, gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101;
reg signed [SIZE-1:0... | 7.229634 |
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm (
.clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1)
);
endmodule
| 7.233807 |
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock, reset, req_0, req_1;
output gnt_0, gnt_1;
wire clock, reset, req_0, req_1;
reg gnt_0, gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101;
reg [SIZE-1:0] state;
reg... | 7.229634 |
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm (
.clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1)
);
endmodule
| 7.233807 |
module top_sim1 ();
localparam FREQ = 12; // in MHZ
// clock
reg clk;
initial begin
#0 clk = 0;
forever clk = #(1000 / (FREQ * 2)) !clk;
end
// reset
reg rst;
initial begin
#0 rst = 1;
#100 rst = 0;
end
// dut
wire [7:0] leds;
wire tx;
top_syn dut (
.CLK_I(clk... | 6.66338 |
module top_single (
clk,
rst,
address,
start,
write_data,
read_operation,
cache_busy,
read_data
);
input clk, rst, start;
input [7:0] address;
input [7:0] write_data;
input read_operation;
output cache_busy;
output [7:0] read_data;
//module single_bus1(clk, rst, read_op,... | 6.54264 |
module top (
input [7:0] data_a,
data_b,
input [6:1] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clk,
output reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @(posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a... | 7.233807 |
module smg (
clk,
data,
sm_wei,
sm_duan,
rst
);
input clk, rst;
input [15:0] data;
output [3:0] sm_wei;
output [7:0] sm_duan;
//----------------------------------------------------------
//ƵƵΪ100Hz
integer clk_cnt; //Ƶڼ
reg clk_100Hz;
always @(posedge clk)
if (rst == 1) begin ... | 7.175966 |
module top_smg (
clk,
rst,
cs,
din_a_0,
addr_a_0,
dout_a,
we_a,
oe_a,
din_b_0,
addr_b_0,
dout_b,
we_b,
oe_b,
rst_clk,
load,
sm_wei,
sm_duan
);
parameter DATA_WIDTH = 3;
parameter ADDR_WIDTH = 3;
parameter RAM_DEPTH = DATA_WIDTH;
input clk, rst... | 7.048532 |
module Top_Snake (
input CLOCK,
input [2:0] btn,
input [12:0] pixel,
input [3:0] sw,
output [15:0] oled_data,
output [3:0] an,
output [7:0] seg
);
wire [35:0] SLOW_CLOCK;
slow_clock SC (
CLOCK,
SLOW_CLOCK
);
wire left_pulse, right_pulse, reset;
pulse p1 (
btn[0]... | 7.194323 |
module top_SoC (
main_clk,
pll_reset,
core_reset,
dac_out
);
input main_clk;
input pll_reset, core_reset;
output [7:0] dac_out;
wire locked;
wire core_clk;
clk_wiz_0 uut1 (
// Clock out ports
.clk_out1(core_clk), // output clk_out1
// Status and control signals
.... | 7.515423 |
module top_SoC_tb ();
reg main_clk, pll_reset, core_reset;
wire [7:0] dac_out;
top_SoC uut (
main_clk,
pll_reset,
core_reset,
dac_out
);
initial begin
main_clk = 1'b0;
pll_reset = 1'b0;
core_reset = 1'b0;
#10;
pll_reset = 1'b1;
#60;
pll_reset = 1'b0;
... | 6.988119 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
specify
specparam TRise = 10, TFall = 15;
(S => M2) = (TRise, TFall);
endspecify
endmodule
| 7.233807 |
module StrideHandler (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_write,
input [16:0] io_in_bits_address,
input [16:0] io_in_bits_size,
input [ 2:0] io_in_bits_stride,
input io_in_bits_reverse,
... | 8.268025 |
module Demux (
output io_in_ready,
input io_in_valid,
input [15:0] io_in_bits_0,
input [15:0] io_in_bits_1,
input [15:0] io_in_bits_2,
input [15:0] io_in_bits_3,
input [15:0] io_in_bits_4,
input [15:0] io_in_bits_5,
input [15:0] io_in_bits_6,
input [15:0] i... | 7.090619 |
module Mux (
output io_in_0_ready,
input io_in_0_valid,
input [15:0] io_in_0_bits_0,
input [15:0] io_in_0_bits_1,
input [15:0] io_in_0_bits_2,
input [15:0] io_in_0_bits_3,
input [15:0] io_in_0_bits_4,
input [15:0] io_in_0_bits_5,
input [15:0] io_in_0_bits_6,
... | 7.736456 |
module SizeHandler_3 (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_sel,
input [12:0] io_in_bits_size,
input io_out_ready,
output io_out_valid,
output io_out_bits_sel
);
wire sizeCoun... | 6.694676 |
module BurstSplitter (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [127:0] io_in_bits_data,
input io_out_ready,
... | 7.518602 |
module BurstSplitter_1 (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [ 5:0] io_in_bits_id,
input [127:0] io_in_bits_data,... | 7.518602 |
module Filter (
output io_control_ready,
input io_control_valid,
input io_control_bits,
output io_in_ready,
input io_in_valid,
input io_out_ready,
output io_out_valid
);
assign io_control_ready = io_control_bits ? io_in_valid & io_out_ready : io_in_valid; // @[MemBoundarySplitter.scala... | 7.016323 |
module Serializer (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [63:0] io_in_bits_0,
input [63:0] io_in_bits_1,
input io_out_ready,
output io_out_valid,
output [63:0] io_out_bits,
input io_error
);... | 6.666069 |
module StrictDecoupledTransmission (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [127:0] io_in_bits,
input io_out_ready,
output io_out_valid,
output [ 63:0] io_out_bits,
input io_error
);
wire ... | 7.043144 |
module top_speed_mac (
clock_sys,
reset,
hall_effect,
speed,
toggle
);
localparam max_count = 435;
parameter dwidth = 11;
input clock_sys;
input reset;
input [2:0] hall_effect;
output toggle;
output [dwidth-1:0] speed;
reg toggle;
wire [dwidth-1:0] count;
wire [d... | 7.85582 |
module top_spi_final (
data_inp,
load,
clk,
rst,
ss0,
ss1,
ss2,
mosi,
master_data1,
slave_data1,
slave_data2,
slave_data3
);
input clk, ss0, ss1, ss2, load, rst; //Declaring the required inputs: Clock, select ports for the three slaves, a load, and reset.
input [0:7] ... | 7.323644 |
module top_spi_function #(
parameter CLK_CNT_HALF = 20,
parameter CLK_CNT_HALF_WIDTH = 5,
parameter MODE = 2'b00,
parameter CPOL = MODE[1],
parameter CPHA = MODE[0]
) (
input clk,
input rst_n,
output [7:0] om_data_master,
output [7:0] om_data_slave
);
wire [7:0] im_data_master;
... | 8.166379 |
module top (
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
output wire VGA_HS_O, // horizontal sync output
output wire VGA_VS_O, // vertical sync output
output wire [3:0] VGA_R, // 4-bit VGA red output
out... | 7.233807 |
module top (
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
output wire VGA_HS_O, // horizontal sync output
output wire VGA_VS_O, // vertical sync output
output wire [3:0] VGA_R, // 4-bit VGA red output
out... | 7.233807 |
module TOP_stim ();
reg CLK;
reg RESET;
wire [7:0] rom_data;
wire [7:0] rom_address;
wire [7:0] BUS_DATA;
wire [7:0] BUS_ADDR;
wire bus_interrupts_raise_from_timer;
wire [1:0] bus_interrupts_raise;
wire [1:0] bus_interrupts_ack;
assign bus_interrupts_raise = {bus_interrupts_raise_from_timer, 1'b0}... | 6.560326 |
module top_STM (
input rst_n
, input clk
, input usr_en
, input display_finish
, input edit_finish
, input check_finish
, input check_4
, output reg edit_en
, output reg display_en
, output reg check_en
, output reg [2:0] row_addr_sel
);
reg [2:0] state;
reg [2:0] next_st... | 6.92545 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
parameter FILE_OUT = "\"file1.txt\"";
reg [8*10:1] stringvar;
reg [ 7:0] q;
initial begin
stringvar = "Starting";
q <= '1;
end
endmodule
| 7.233807 |
module top_stripes_node (
clk, // Main clock
reset, // Reset
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_nbout, // Input from NBOut
i_first_cycle,
i_precision,
i_mux_sel,
i_max,
i_load,
o_to_nbout
);
parameter N = 16;
parameter Tn = 16;
... | 7.061583 |
module top_stripes_node (
clk, // Main clock
reset, // Reset
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_nbout, // Input from NBOut
i_first_cycle,
i_precision,
i_mux_sel,
i_maxpool,
i_load,
o_to_bus
);
parameter N = 16;
parameter Tn = 1;
... | 7.061583 |
module top_stripes_node_slice (
clk, // Main clock
reset, // Reset
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_nbout, // Input from NBOut
i_first_cycle,
i_precision,
// i_mux_sel,
i_maxpool,
i_load,
o_to_bus
);
parameter N = 16;
par... | 7.061583 |
module top_serial_pipe (
clk,
reset,
i_first_cycle,
i_max,
i_load,
i_precision,
i_neurons,
i_synapses,
i_nbout,
o_nfu2
);
parameter N = 16; // Synapse bits
parameter Ti = 16; // neuron tiling
parameter Tn = 16; // synapse tiling
parameter Tw = 16; // Window tiling, n... | 7.912607 |
module Top_Student_Simulation ();
reg sw0;
reg sw1;
reg sw2;
reg sw3;
reg J_MIC3_Pin3; // Connect from this signal to Audio_Capture.v
wire J_MIC3_Pin1; // Connect to this signal from Audio_Capture.v
wire J_MIC3_Pin4;
wire [15:0] led;
wire [3:0] an;
wire [7:0] seg;
reg CLK;
reg BTNC;
reg BTN... | 7.725913 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
assign cout = cin % y;
assign A = cin - x;
endmodule
| 7.233807 |
module top_subbyte (
//input
input wire clk,
input wire rst_n,
input wire [127:0] data_in,
input wire start_in,
input wire en_de,
//output
output wire [127:0] data_out,
output wire ready_out
);
//internal wires
wire [7:0] sbox_in;
wire [7:0] sbox_out;
wire... | 7.404725 |
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
wire y,a,b;
buf (supply1) g1 (y, a);
buf (supply0) g2 (y, b);
endmodule
| 6.662049 |
module top_SW(
input button,
input reset,
input clk,
output [6:0] cathode,
output [3:0] anode,
output dp);
wire [1:0] refresh_signal;
wire main_clk, refresh_clk;
wire [3:0] milli_zero, milli_one, sec_zero, sec_one;
wire [3:0] final;
wire [7:0] mid_milli, mid_sec;
SW_... | 6.934274 |
module: top_single
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_s_test;
// Inputs
reg clk;
reg rst;
reg [7:0] address;
reg start;
reg [7:0] write_data;
reg read_operat... | 7.249066 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_t0;
// Inputs
reg clk;
reg [13:0] switch;
reg [11:0] btn_in;
// Outputs
wire [11:0] anode;
wire [15:0] segmen... | 7.115105 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
wire [7:0] temp_a, temp_b;
wire e;
task convert;
input [7:0] temp_in;
output [7:0] temp_out;
begin
temp_out = (9 / 5) * (temp_in + 32);
end
endtask
function myfunction;
input a, b, c, d;
... | 7.233807 |
module Top_tb;
`include "../src/utils/Assert.vh"
`include "../src/Parameters.vh"
// Input stimulus
parameter INSTRUCTION_FILE_NAME = "./test/datapath_tb1.ASM";
reg clk, rst;
Top #(
.INSTRUCTION_FILE_NAME(INSTRUCTION_FILE_NAME)
) top (
.clk(clk),
.rst(rst)
);
// Test initialization
... | 6.942968 |
module top_tb_1000 ();
reg clk, rst_n;
reg [7:0] pixels[0:783999];
reg [9:0] img_idx;
reg [7:0] data_in;
reg [9:0] cnt; // num of input image (1000)
reg [9:0] input_cnt;
reg [9:0] rand_num; // 1000
reg state;
integer i_cnt; // loop variable
reg [9:0] accuracy; // hit/miss count (1000)
wire ... | 6.811656 |
module top_tb_bd ();
localparam HALF_CORE_PERIOD = 2.5;
reg reset;
reg fpga_sysclk;
wire fpga_sysclk_p, fpga_sysclk_n;
reference_router_wrapper top_sim_bd_wrapper (
.fpga_sysclk_n (fpga_sysclk_p),
.fpga_sysclk_p (fpga_sysclk_n),
.reset (reset)
);
// rst - ACTIVE_HIGH
init... | 7.247029 |
module Top_tb;
//pins
reg [ 7:0] input_test;
wire [15:0] ans;
reg clk, rst_n, next, init;
wire ready, done;
reg [15:0] gold_ans;
reg Valid;
integer i, j;
parameter num = 10; //number of answer data
//module instantiation
CHIP top (
.clk(clk),
.rst_n(rst_n),
.i_valid(Valid),
... | 6.843836 |
module clk_div (
clk_in1,
clk_out1,
reset,
locked
);
input clk_in1;
output clk_out1;
input reset;
output locked;
wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
clk_div_clk_div_clk_wiz inst (
.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.rese... | 7.520262 |
module dataRAM
(a,
d,
clk,
we,
spo);
input [5:0]a;
input [31:0]d;
input clk;
input we;
output [31:0]spo;
wire [5:0]a;
wire clk;
wire [31:0]d;
wire [31:0]spo;
wire we;
wire NLW_U0_i_ce_UNCONNECTED;
wire NLW_U0_qdpo_ce_UNCONNECTED;
wire NLW_U0_qdpo_clk_UNCONNECTED;
wire NLW... | 6.975103 |
module instructionROM
(a,
spo);
input [5:0]a;
output [31:0]spo;
wire [5:0]a;
wire [31:0]spo;
wire NLW_U0_clk_UNCONNECTED;
wire NLW_U0_i_ce_UNCONNECTED;
wire NLW_U0_qdpo_ce_UNCONNECTED;
wire NLW_U0_qdpo_clk_UNCONNECTED;
wire NLW_U0_qdpo_rst_UNCONNECTED;
wire NLW_U0_qdpo_srst_UNCONNECTED;
wi... | 6.735273 |
module IF (
Instruction_if,
Q,
D,
\q_reg[5] ,
E,
SR,
\q_reg[0] ,
clk
);
output [31:0] Instruction_if;
output [0:0] Q;
output [5:0] D;
input [5:0] \q_reg[5] ;
input [0:0] E;
input [0:0] SR;
input [0:0] \q_reg[0] ;
input clk;
wire [5:0] D;
wire [0:0] E;
wire [31:0] I... | 6.625137 |
module instructionROM_dist_mem_gen_v8_0_10 (
a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo
);
input [5:0] a;
input [31:0] d;
input [5:0] dpra;
input clk;
input we;
inpu... | 6.735273 |
module instructionROM_dist_mem_gen_v8_0_10_synth (
spo,
a
);
output [20:0] spo;
input [5:0] a;
wire [ 5:0] a;
wire [20:0] spo;
instructionROM_rom \gen_rom.rom_inst (
.a (a),
.spo(spo)
);
endmodule
| 6.735273 |
module top_TDES_encrypt (
input clk,
input [63:0] data,
input [63:0] key1,
input [63:0] key2,
input [63:0] key3,
input nrst,
output [63:0] data_out
);
logic [ 63:0] data_out_1;
logic [ 63:0] data_out_2;
logic [1023:0] key_2_decrypt;
logic [2047:0] key_3_encrypt;
always @(posed... | 6.775213 |
module reg_ar_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "S... | 7.493109 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module CLK_MOD // source/CLK_MOD.v(1)
(
CLK,
Count_REG,
RSTn,
CLK_OUT
);
input CLK; // source/CLK_MOD.v(11)
input [31:0] Count_REG; // source/CLK_MOD.v(14)
input RSTn; // source/CLK_MOD.v(12)
output CLK_OUT; // source/CLK_MOD.v(17)
wire [31:0] Count; // source/CLK_MOD.v(15)
wire [31:... | 7.043189 |
module add_pu16_pu16_o16 (
i0,
i1,
o
);
input [15:0] i0;
input [15:0] i1;
output [15:0] o;
endmodule
| 6.909569 |
module reg_ar_as_w16 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [15:0] d;
input en;
input [15:0] reset;
input [15:0] set;
output [15:0] q;
endmodule
| 7.044453 |
module add_pu32_pu32_o32 (
i0,
i1,
o
);
input [31:0] i0;
input [31:0] i1;
output [31:0] o;
endmodule
| 6.598391 |
module reg_ar_as_w5 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [4:0] d;
input en;
input [4:0] reset;
input [4:0] set;
output [4:0] q;
endmodule
| 6.587269 |
module onehot_mux_s5_w5 (
i0,
i1,
i2,
i3,
i4,
sel,
o
);
input [4:0] i0;
input [4:0] i1;
input [4:0] i2;
input [4:0] i3;
input [4:0] i4;
input [4:0] sel;
output [4:0] o;
endmodule
| 6.655267 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module reg_ar_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "S... | 7.493109 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module AL_FADD (
input a,
input b,
input c,
output sum,
output cout
);
wire prop;
wire not_prop;
wire sel_i0;
wire sel_i1;
xor u0 (prop, a, b);
xor u1 (sum, prop, c);
not u2 (not_prop, prop);
and u3 (sel_i1, prop, c);
and u4 (sel_i0, not_prop, a);
or u5 (cout, sel_i0, sel_i1... | 8.066381 |
module enable
reg linkBIM;
reg capture_rst;
#{REG_TEXT}
#{ASSIGN_TEXT}
#{IP_TEXT}
/////////////////////////////////////////////////////////////////////////////////////////////////////
reg flag_reg;
always @ (negedge bps_start or negedge rst_n)
begin
if (!rst_n)
flag_reg <= 1'b0;
else if (!bps_start)
flag_reg ... | 7.08557 |
module top_test (
input clk, // clk100mhz
input rstn, // cpu_resetn
output [31:0] pc,
// for simulate io
output [ 7:0] io_addr,
output io_rd,
input [31:0] io_din
);
wire [31 : 0] io_dout;
wire io_we;
wire [31 : 0] chk_data;
wire [31:0] vga_data;
c... | 7.337344 |
module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_Tester;
// Inputs
reg clock_100MHz;
reg reset_n;
reg [7:0] Switch;
reg UART_Rx;
// Outputs
... | 7.357405 |
module top_test_add;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = (1 << WIDTH) - 1;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH : 0] expe... | 6.712228 |
module top_test_jump;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 5;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output ... | 7.923626 |
module top_test_load_out;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 7;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_out... | 6.795474 |
module top_test_load_store;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 3;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_o... | 6.795474 |
module top_test_shl;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = (1 << WIDTH) - 1;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] ex... | 7.950308 |
module top_test_sub;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = (1 << WIDTH) - 1;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] ex... | 6.577828 |
module top_b2b_proj (
FIFO_READ_empty,
FIFO_READ_rd_data,
FIFO_READ_rd_en,
clk_in1,
reset_rtl_0
);
output FIFO_READ_empty;
output [127:0] FIFO_READ_rd_data;
input FIFO_READ_rd_en;
input clk_in1;
input reset_rtl_0;
wire FIFO_READ_empty;
wire [127:0] FIFO_READ_rd_data;
wire FIFO_READ_... | 6.71581 |
module top_tranrec (
output [7:0] data_out,
input [7:0] data,
input start,
input clk
);
wire Tx, data_valid;
wire [3:0] cnt_trans;
wire [3:0] cnt_rec;
transmitter t2 (
Tx,
cnt_trans,
data,
~start,
clk
);
receiver r2 (
data_valid,
cnt_rec,
dat... | 6.687679 |
module tristate (
en,
i,
io,
o
);
input en;
input i;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
assign io[0] = (en) ? i : 1'bZ;
assign io[1] = (i) ? en : 1'bZ;
assign o = io;
endmodule
| 6.741184 |
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en(en),
.i (a),
.io(b),
.o (c)
);
endmodule
| 7.233807 |
module top_tukka2 (
`ifdef USE_POWER_PINS
inout vdd, // User area 5.0V supply
inout vss, // User area ground
`endif
input clk1,
input clk2,
input reset_n,
input sel_clk2,
input ss,
input mosi,
output miso,
input sck,
output done,
input [7:0] din,
output [7:0] dout
)... | 7.002032 |
module top_uart #( // Default setting:
// 19,200 baud, 8 data bits, 1 stop bit, 2^2 FIFO
parameter DBIT = 8, // # data bits
SB_TICK = 16, // # ticks for stop bits, 16/24/32
// for 1/1.5/2 stop bits
DVSR = 163, // baud rate divisor
// DVSR = 50M/... | 7.643709 |
module top_uart_buffer_echo (
sys_clk_n,
sys_clk_p,
uart_rx,
uart_tx
);
input sys_clk_n;
input sys_clk_p;
input uart_rx;
output uart_tx;
wire sys_clk_n;
wire sys_clk_p;
wire uart_rx;
wire uart_tx;
wire clk_100M; // @ 100.000000MHz
wire clk_50M; // @ 50.000000MHz
wire clk_5M; ... | 6.878899 |
module top_uart_echo (
sys_clk_n,
sys_clk_p,
uart_rx,
uart_tx
);
input sys_clk_n;
input sys_clk_p;
input uart_rx;
output uart_tx;
wire sys_clk_n;
wire sys_clk_p;
wire uart_rx;
wire uart_tx;
wire clk_100M; // @ 100.000000MHz;
wire clk_50M; // @ 50.000000MHz;
wire clk_5M; // @ ... | 6.920979 |
module Top_UART_tb ();
parameter CLOCK_PERIOD = 10;
reg i_clk = 0;
reg TX_Valid = 0;
wire o_TX_Active;
wire UART_TX_RX;
wire o_TX_Serial;
wire o_TX;
wire o_RX_DV;
reg [7:0] data_TX = 0;
wire [7:0] data_RX;
/*TOP_UART TOP_DUT(
i_clk ,
i_TX_valid ,
data_TX ,
o_TX_Active ,
o_TX,
o_RX_DV ,
dat... | 6.525673 |
module Top_uart_tx_dzj (
input [3:0] in_key_en,
input clk,
input rst_n,
input co,
input zhendong,
output RX232,
output over_rx,
output fengshan
);
wire [7:0] data_rx;
wire [3:0] out_key_en;
uart_tx_dzj a (
.co(co),
.zhendong(zhendong),
.in_key_en(out_key_en),
... | 6.585741 |
module: Top_uart_tx_dzj
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_uart_tx_dzj_test;
// Inputs
reg [3:0] in_key_en;
reg clk;
reg rst_n;
// Outputs
wire RX232;
wire ... | 8.138503 |
module: Top_uart_tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_uart_tx_test;
// Inputs
reg clk;
reg send_en;
reg rst_n;
reg [7:0] data_rx;
// Outputs
wire RX232;
w... | 7.845935 |
module top_uc (
input rst,
input clk,
output reg [2:0] RGB0,
output reg [2:0] RGB1,
output reg [2:0] RGB2,
output reg [2:0] RGB3,
output reg [3:0] LED,
input [3:0] SW,
input [3:0] BTN
);
//wire pgm_re;
wire [`BUS_ADDR_PGM_LEN-1:0] pgm_addr;
wire [15:0] pgm_data;
wire data_... | 7.151178 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
wire a, c, d, e, g;
reg b, h, f;
always @(*) begin
unique case (a)
0: b = c;
1: b = d;
endcase
unique case (g)
0: h = c;
1: h = d;
endcase
priority case (e)
0: f = c... | 7.233807 |
module top (
input [7:0] data_a,
data_b,
input [6:1] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clk,
output reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @(posedge ... | 7.233807 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'UNROLL_ALL_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the share... | 7.358787 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.