code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'UNROLL_FILL_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shar... | 7.358787 |
module top_up5k (
clk_in,
reset_n_in,
// Global data
sck0_in,
sdi0_in,
cs0_n_in,
// Daisy data
sck1_in,
sdi1_in,
sdo1_out,
cs1_n_in,
// Success flags
ready_n_od_out,
// Indicators
status_led_n_out
);
`define SHAPOOL_NO_NONCE_OFFSET // Required for POOL_SIZE... | 7.181474 |
module top_upduino2 (
output [2:0] led_n
);
`include "macros/direction.vh"
wire clk;
reg [2:0] int_rst_cnt = 0;
always @(posedge clk) begin
if (int_rst_cnt != 3'b111) int_rst_cnt <= int_rst_cnt + 1;
end
wire int_rst_n = int_rst_cnt == 3'b111;
wire rst_n = int_rst_n;
reg [2:0] led;
wire ... | 6.619851 |
module TOP_URISC (
input clk_PH1,
// input clk_PH2,
input rst_n,
input Run
);
wire CSMR_CS, WRITE, RDMR_READ;
wire [7:0] ADDRESS;
wire [7:0] WDATA;
wire [7:0] RDATA;
URISC ursic (
.clk_PH1(clk_PH1),
.clk_PH2(~clk_PH2),
.rst_n(rst_n),
.RUN(Run),
.CSMR(CSMR_CS)... | 6.592699 |
module top_vending (
(*chip_pin = "U15"*) input dollar,
(*chip_pin = "V15"*) input quarter,
(*chip_pin = "U14"*) input dime,
(*chip_pin = "V14"*) input nickel,
(*chip_pin = "U4"*) output reg d_cookies,
(*chip_pin = "V4"*) output reg d_candy,
(*chip_pin = "U5"*) output reg d_chips,
(*ch... | 7.393468 |
module top_vending_test;
reg clk;
reg rst;
reg dollar;
reg quarter;
reg dime;
reg nickel;
wire cooikes;
wire candy;
wire chips;
wire gum;
wire c_dime;
wire c_nickel;
wire c_quarter;
reg [4:1] keyrow;
wire [3:0] keycolumn;
top_vending DUT (
.clk(clk),
.rst(rst),
.dollar... | 6.771291 |
module sram (
input cs,
input we,
input oe,
input [16:0] addr,
input [15:0] data_i,
output [15:0] data_o
);
reg [15:0] mem[0:131071];
// initial $readmemh("./finch.hex",mem);
assign data_o = (!cs && !oe) ? mem[addr] : 16'bz;
always_latch @(we, cs, addr, data... | 7.547687 |
module top_vga (
clk,
reset,
red,
green,
blue,
vsync,
hsync
);
input clk, reset;
output vsync, hsync;
output reg [3:0] red, green, blue;
reg CLK_50;
wire Xdisplay, Ydisplay;
wire [9:0] haddr;
wire [8:0] vaddr;
horizontal HSYNC (
CLK_50,
reset,
haddr,
... | 7.258908 |
module top_vga (
input clk,
input rst,
output hsync,
output vsync,
output [3:0] red,
output [3:0] green,
output [3:0] blue
);
wire clkd;
vga1280x1024 vga1280x1024 (
.dclk (clkd), //pixel clock: 108MHz
.clr (rst), //asynchronous reset
.hsync(hsync), //horizontal... | 7.258908 |
module: top_view
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_view_test;
// Inputs
reg clk;
reg rst_n;
reg [11:0] ad1_in;
reg [11:0] ad2_in;
// Outputs
wire led0;
wi... | 7.569143 |
module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_VTF;
// Inputs
reg Clk;
reg Rst;
reg Rx;
// Outputs
wire Tx;
// Instantiate the Unit Under Test (UUT)
Top u... | 7.357405 |
module dff (
input [3:0] d,
input clk,
clr,
output reg [3:0] q
);
initial begin
q = 4'b0000;
end
always @(posedge clk)
if (clr) q <= 4'b0110;
else q <= d;
endmodule
| 7.174483 |
module adff (
input [3:0] d,
input clk,
clr,
output reg [3:0] q
);
initial begin
q = 4'b0000;
end
always @(posedge clk, posedge clr)
if (clr) q <= 4'b0110;
else q <= d;
endmodule
| 7.089232 |
module dffe (
input [3:0] d,
input clk,
en,
output reg [3:0] q
);
initial begin
q = 4'b0010;
end
always @(posedge clk) if (en) q <= d;
endmodule
| 7.085902 |
module dffse (
input [3:0] d,
input clk,
en,
pre,
output reg [3:0] q
);
initial begin
q = 1;
end
always @(posedge clk)
if (!pre) q <= 4'b0101;
else if (en) q <= d;
endmodule
| 7.440558 |
module tristate (
en,
i,
io,
o
);
input en;
input [3:0] i;
inout [3:0] io;
output [1:0] o;
wire [3:0] io;
assign io[1:0] = (en) ? i[1:0] : 1'bZ;
assign io[3:2] = (i[1:0]) ? en : 1'bZ;
assign o = io[2:1];
endmodule
| 6.741184 |
module top (
input en,
input [3:0] a,
inout [3:0] b,
output [1:0] c
);
tristate u_tri (
.en(en),
.i (a),
.io(b),
.o (c)
);
endmodule
| 7.233807 |
module one_round (
state_in,
key,
state_out
);
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p2... | 7.018166 |
module final_round (
state_in,
key_in,
state_out
);
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3, z0, z1, z2, z3, k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03, p10, p11, p12, p13, p20, p21, p22, p23, p30, p31, p32, p33;
assign {k0, k1, ... | 7.609225 |
module S4 (
in,
out
);
input [31:0] in;
output [31:0] out;
S
S_0 (
in[31:24],
out[31:24]
),
S_1 (
in[23:16],
out[23:16]
),
S_2 (
in[15:8],
out[15:8]
),
S_3 (
in[7:0],
out[7:0]
... | 6.508373 |
module T (
in,
out
);
input [7:0] in;
output [31:0] out;
S s0 (
in,
out[31:24]
);
assign out[23:16] = out[31:24];
xS s4 (
in,
out[7:0]
);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
| 6.784554 |
module top_wrapper (
`ifdef USE_POWER_PINS
vdd3v3,
vdd1v8,
vss,
`endif
clk,
rst,
wishbone_data_in,
wishbone_data_out,
start_operation,
wishbone_address_bus,
wbs_we_i,
rd_sync_fifo_output_buffer_ADC,
rd_sync_fifo_output_buffer_CSA,
V1_WL,
V2_WL,
V3_WL,
V4_W... | 6.879876 |
module top_xc2v (
input osc_clk,
input rxd,
output txd,
output led0,
output led1,
output led2,
output led3,
output led4,
output led5,
output led6,
output led7,
output j7_5,
output j7_6,
output j7_9,
output j7_10,
output j7_11,
output j7_12,
outpu... | 6.806586 |
module top_xinlv (
input clk,
input rst_n,
input data_rx,
output reg [7:0] xinlv
);
wire [7:0] data_tx;
wire rx_int;
wire [7:0] xinlv_1;
reg [25:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt <= 26'd0;
else if (cnt == 26'd5000_0000 - 1) cnt <= 26'd0;
... | 6.65745 |
module top_z80 (
input I_CLK,
input I_N_RESET,
input I_N_NMI,
input I_N_INT,
output [15:0] O_ADDR,
output O_N_IORQ,
output O_N_HALT,
output O_N_M1,
output O_N_MREQ,
output O_N_RD,
output O_N_WR,
inout [7:0] IO_DATA,
inout VCC,
inout GND,
inout VCC3IO,
inou... | 7.172512 |
module top (
input rx,
output tx,
output sync
);
wire clk;
SB_HFOSC #(
.CLKHF_DIV("0b10")
) u_SB_HFOSC (
.CLKHFPU(1),
.CLKHFEN(1),
.CLKHF (clk)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
... | 7.233807 |
module StrideHandler (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_write,
input [20:0] io_in_bits_address,
input [20:0] io_in_bits_size,
input [ 2:0] io_in_bits_stride,
input io_in_bits_reverse,
... | 8.268025 |
module SizeHandler_3 (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_sel,
input [13:0] io_in_bits_size,
input io_out_ready,
output io_out_valid,
output io_out_bits_sel
);
wire sizeCoun... | 6.694676 |
module BurstSplitter (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [511:0] io_in_bits_data,
input io_out_ready,
... | 7.518602 |
module BurstSplitter_1 (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [ 5:0] io_in_bits_id,
input [511:0] io_in_bits_data,... | 7.518602 |
module Filter (
output io_control_ready,
input io_control_valid,
input io_control_bits,
output io_in_ready,
input io_in_valid,
input io_out_ready,
output io_out_valid
);
assign io_control_ready = io_control_bits ? io_in_valid & io_out_ready : io_in_valid; // @[MemBoundarySplitter.scala... | 7.016323 |
module StrideHandler (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_write,
input [20:0] io_in_bits_address,
input [20:0] io_in_bits_size,
input [ 2:0] io_in_bits_stride,
input io_in_bits_reverse,
... | 8.268025 |
module SizeHandler_3 (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_sel,
input [15:0] io_in_bits_size,
input io_out_ready,
output io_out_valid,
output io_out_bits_sel
);
wire sizeCoun... | 6.694676 |
module BurstSplitter (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [511:0] io_in_bits_data,
input io_out_ready,
... | 7.518602 |
module BurstSplitter_1 (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [ 5:0] io_in_bits_id,
input [511:0] io_in_bits_data,... | 7.518602 |
module Filter (
output io_control_ready,
input io_control_valid,
input io_control_bits,
output io_in_ready,
input io_in_valid,
input io_out_ready,
output io_out_valid
);
assign io_control_ready = io_control_bits ? io_in_valid & io_out_ready : io_in_valid; // @[MemBoundarySplitter.scala... | 7.016323 |
module top (
input rx,
output tx,
output sync
);
wire clk;
SB_HFOSC #(
.CLKHF_DIV("0b10")
) u_SB_HFOSC (
.CLKHFPU(1),
.CLKHFEN(1),
.CLKHF (clk)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
... | 7.233807 |
modules holding the particle pairs that has torsion force in between
//
// Purpose:
// Providing particle ids that contribute to the torsion force
//
// Data Organization:
// Address 0 for each cell module: # of bonded pairs in the memory
// MSB-LSB: {particle_id_1, particle_id_2}
//
// Used by:
// Bonded_T... | 8.474291 |
module torus (
input wire clk,
input wire seed,
input wire seed_ena,
input wire life_step,
output wire [TORUS_WIDTH*TORUS_HEIGHT-1:0] torusv,
output wire torus_last
);
parameter TORUS_WIDTH = 32;
parameter TORUS_HEIGHT = 16;
localparam WMASK = (TORUS_WIDTH - 1);
localparam HMASK = (TOR... | 7.952197 |
module torus #(
parameter H_SIZE = 3,
parameter PORT_SIZE = (37 + 2),
parameter NODES_NUM = 2
) (
input [NODES_NUM*4*PORT_SIZE-1:0] data_i,
output [NODES_NUM*4*PORT_SIZE-1:0] data_o
);
genvar i, j;
generate
for (i = 0; i < NODES_NUM; i = i + 1) // input index
for (j = i + 1; j < NODES_... | 7.203637 |
module TotalALU (
clk,
dataA,
dataB,
Signal,
Output,
reset
);
input reset;
input clk;
input [31:0] dataA;
input [31:0] dataB;
input [5:0] Signal;
output [31:0] Output;
// Signal ( 6-bits)?
// AND : 36
// OR : 37
// ADD : 32
// SUB : 34
// SLL : 00
// ... | 8.055983 |
module riseCount (
count,
control,
hiding,
reset
);
output [15:0] count;
input reset, hiding, control;
DecimalCounter4Dig dc4g (
.count(count),
.clock(control && hiding),
.reset(reset)
);
endmodule
| 6.775448 |
module rl (
reset,
go,
CLOCK_50,
CLOCK_WAIT,
CLOCK_RL,
Mheight,
hiding
);
input reset, go, CLOCK_50, CLOCK_RL, CLOCK_WAIT;
wire Mreset_height;
wire Mreset_wait;
wire Mheight_en;
wire Mheight_incr;
wire [2:0] Mwait;
output [4:0] Mheight;
output hiding;
MoleRL mrl (
.... | 6.532131 |
module DigitAdder (
A,
B,
carry_in,
out,
carry_out
);
input [3:0] A;
input [3:0] B;
input carry_in;
output reg [3:0] out;
output reg carry_out;
always @(*) begin
if (A + B + carry_in < 5'd10) begin
out[3:0] = A + B + carry_in;
carry_out = 1'b0;
end else begin
... | 6.722939 |
module MoleRL (
Mwait,
Mheight,
CLOCK_WAIT,
CLOCK_RL,
Mreset_wait,
Mheight_en,
Mreset_height,
Mheight_incr
);
input Mreset_height;
input Mreset_wait;
input Mheight_en;
input Mheight_incr;
input CLOCK_WAIT;
input CLOCK_RL;
output reg [2:0] Mwait;
output reg [4:0] Mheight;... | 6.557012 |
module board_capabilities (
input wire clk,
input wire poweron_rst_n,
input wire in_boot_mode,
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire [2:0] fpga_model,
input wire [7:0] din,
output wire [7:0] dout,
output wire oe,
output wire [... | 7.128859 |
module total_tb ();
reg reset_n;
reg clk;
reg clk_vga;
reg wb_we;
reg [31:0] wb_dat;
reg [26:0] wb_adr;
wire wb_ack;
wire [3:0] oRed; // red signal
wire [3:0] oGreen; // green signal
wire [3:0] oBlue; // blue signal
wire oHs; // Hori sync
wire oVs; // Vert sync
GPUTop gpu (
.clk_... | 6.529441 |
module touchpad_controller (
input wire cclk,
rstb,
input wire touch_busy,
data_in,
output reg touch_clk,
output wire data_out,
output reg touch_csb,
output reg [11:0] x,
y,
z
);
reg [5:0] clk_div_counter;
reg [1:0] current_dimension;
wire [7:0] transaction_message;
a... | 7.307405 |
module touchpad_controller_fast (
input wire cclk,
rstb,
input wire touch_busy,
data_in,
output wire touch_clk,
data_out,
output reg touch_csb,
output reg [8:0] x,
y,
z
);
reg [4:0] clk_div_counter;
reg [1:0] channel;
reg [11:0] x_raw, y_raw, z_raw, incoming_data;
wire [... | 7.307405 |
module touch_control (
iCLK,
iRSTN,
iREADY,
iREG_GESTURE,
ix1,
iy1,
ix2,
iy2,
itouch_count,
oButton_state
);
parameter IDLE = 1'b0;
parameter TOUCH = 1'b1;
//=======================================================
// Port declarations
//==============================... | 6.639204 |
module touch_ctrl_led (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号，低电平有效
input wire touch_key, //触摸按键信号
output reg led //led输出信号
);
//********************************************************************//
//****************** Parameter and Internal Signal ***************... | 8.444983 |
module touch_led (
//input
input sys_clk, //时钟信号50Mhz
input sys_rst_n, //复位信号
input touch_key, //触摸按键
//output
output reg led //LED灯
);
//reg define
reg touch_key_d0;
reg touch_key_d1;
reg switch;
//wire define
wire touch_en;
//根据按键信号的上升沿判断按下了按键
assign touch_en = (... | 6.748639 |
module
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 07/06/30 :| Initial Revision
// ------------... | 7.097087 |
module gnr_ram #(
parameter WIDTH = 8,
parameter DEPTH = 32,
parameter DATAFILE = ""
) (
input clock,
input write_en,
input [$clog2(DEPTH) - 1:0] w_addr,
input [WIDTH - 1:0] data_i,
input [$clog2(DEPTH) - 1:0] r_addr,
output reg ready,
output [WIDTH - 1:0] data_o
);
reg [WIDTH ... | 7.682162 |
module to_driver_sd_avs (
input wire clk_sys,
input wire rst,
input wire ao486_rst,
// input hdd_avalon_master
input wire [31:0] hdd_avalon_master_address,
input wire hdd_avalon_master_read,
output wire [31:0] hdd_avalon_master_readdata,
input wire hdd_avalon_master_wri... | 6.527232 |
module dq (
clk,
q,
d
);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width = 8;
parameter depth = 2;
integer i;
reg [width-1:0] delay_line[depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for (i = 1; i < depth; i = i + 1) begin
delay_line[i] <= de... | 6.77352 |
module dq (
clk,
q,
d
);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width = 8;
parameter depth = 2;
integer i;
reg [width-1:0] delay_line[depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for (i = 1; i < depth; i = i + 1) begin
delay_line[i] <= de... | 6.77352 |
module to_upper (
OUT,
IN
);
output wire [7:0] OUT;
input wire [7:0] IN;
wire isLower = (8'h61 <= IN && IN <= 8'h7a);
// if space --> Z
assign OUT = isLower ? IN - 32 : IN;
endmodule
| 8.249279 |
module alu #(
parameter BUS_OP_SIZE = 6,
parameter BUS_SIZE = 8,
parameter BUS_BIT_ENABLE = 3
) (
input i_clk,
input [BUS_BIT_ENABLE - 1 : 0] i_en,
input [BUS_SIZE - 1 : 0] i_switch,
output [BUS_SIZE - 1 : 0] o_led,
output o_carry_bit,
output o_zero_bit
);
localparam OP_ADD = 6'b10... | 6.7799 |
module tp84_lpf (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 220; //Sample at 49.152/220 = 223418Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.045425748, 0.045425748... | 7.566268 |
module tp84_lpf_heavy (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 256; //Sample at 49.152/64 = 192000Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.0050118701, 0.005... | 7.660623 |
module tp84_lpf_light (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 256; //Sample at 49.152/256 = 192000Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.045425748, 0.045... | 7.391008 |
module tp84_lpf_medium (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 256; //Sample at 49.152/64 = 192000Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.0055103045, 0.00... | 7.458026 |
module TPA (
clk,
reset_n,
SCL,
SDA,
cfg_req,
cfg_rdy,
cfg_cmd,
cfg_addr,
cfg_wdata,
cfg_rdata
);
input clk;
input reset_n;
// Two-Wire Protocol slave interface
input SCL;
inout SDA;
// Register Protocal Master interface
input cfg_req;
output cfg_rdy;
input c... | 7.249862 |
module TPA (
clk,
reset_n,
SCL,
SDA,
cfg_req,
cfg_rdy,
cfg_cmd,
cfg_addr,
cfg_wdata,
cfg_rdata
);
input clk;
input reset_n;
// Two-Wire Protocol slave interface
input SCL;
inout SDA;
// Register Protocal Master interface
input cfg_req;
output cfg_rdy;
input c... | 7.249862 |
module tPC;
reg reset, count, outEn;
wire [15:0] curAddress;
PC programCounter (
reset,
count,
outEn,
curAddress
);
initial begin
reset = 1'b1;
#5 reset = 1'b0;
count = 1'b1;
#5 count = 1'b0;
outEn = 1'b1;
#5 outEn = 1'b0;
count = 1'b1;
#5 outEn = 1'b1... | 6.822896 |
module tpg_tb;
parameter BITS = 3;
reg clk;
reg rst;
wire END;
wire [BITS-1:0] op;
tpg #(
.BITS(BITS)
) TPG (
.clk(clk),
.rst(rst),
.END(END),
.TEST_PATTERN(op)
);
initial clk <= 0;
always #5 clk <= ~clk;
always begin
$monitor("Time = %.0f, Pattern = %b, RST ... | 6.709645 |
module name to match the file name
// =============================================================================
`ifndef TPIO_V
`define TPIO_V
`include "system_conf.v"
module tpio #(parameter DATA_WIDTH = 16,
parameter IRQ_MODE = 1,
parameter LEVEL = 0,
parameter EDGE = 1,
... | 7.325849 |
module tPortIn #(
`include "noc_parameter.vh"
) (
// Header: burst(1)+bsel+srcModId+srcChipId+trgX+trgY+trgZ+trgModId+trgChipId
// Payload: mode+address+data
//Interface to the remote router
input wire [ NOC_HEADER_SIZE-1:0] header_i,
input wire [NOC_PAYLOAD_SIZE-1:0] payload_i,
output wi... | 6.878118 |
module tPortOut #(
`include "noc_parameter.vh"
) (
// Header: burst(1)+bsel+srcModId+srcChipId+trgX+trgY+trgZ+trgModId+trgChipId
// Payload: mode+address+data
//Interface to the remote router
output wire [ NOC_HEADER_SIZE-1:0] header_o,
output wire [NOC_PAYLOAD_SIZE-1:0] payload_o,
output w... | 7.315445 |
module tpram_inf_be_512x16 (
input wire clock,
input wire [ 9-1:0] wraddress,
input wire wren,
input wire [ 2-1:0] byteena_a,
input wire [16-1:0] data,
input wire [ 9-1:0] rdaddress,
output reg [16-1:0] q
);
// memory
reg [8-1:0] mem0[0:512-1];
reg [8-1:0] mem... | 6.856212 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_S... | 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_ac... | 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,... | 6.865188 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_S... | 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_ac... | 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,... | 6.865188 |
module max_in_10 (
input [10 * 8 - 1:0] data_in,
output reg [7:0] data_max,
output [3:0] oIndex
);
reg [3:0] cnt;
reg [3:0] index;
assign oIndex = 9 - index;
always @(*) begin
data_max = data_in[7:0];
index = 0;
for (cnt = 0; cnt < 10; cnt = cnt + 1) begin
if (data_max == 8'b100... | 7.140602 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module norm (
input enable_norm,
input [`DWIDTH-1:0] mean,
input [`DWIDTH-1:0] inv_var,
input in_data_available,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_norm,
... | 7.667513 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_S... | 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_ac... | 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,... | 6.865188 |
module ReLU(
// input [`DWIDTH-1:0] inp_data,
// output[`DWIDTH-1:0] out_data
//);
//
//assign out_data = inp_data[`DWIDTH-1] ? {`DWIDTH{1'b0}} : inp_data;
//
//endmodule
| 6.652528 |
module norm (
input enable_norm,
input [`DWIDTH-1:0] mean,
input [`DWIDTH-1:0] inv_var,
input in_data_available,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_norm,
... | 7.667513 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_S... | 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_ac... | 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,... | 6.865188 |
module ReLU(
// input [`DWIDTH-1:0] inp_data,
// output[`DWIDTH-1:0] out_data
//);
//
//assign out_data = inp_data[`DWIDTH-1] ? {`DWIDTH{1'b0}} : inp_data;
//
//endmodule
| 6.652528 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module norm (
input enable_norm,
input [`DWIDTH-1:0] mean,
input [`DWIDTH-1:0] inv_var,
input in_data_available,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_norm,
... | 7.667513 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_S... | 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_ac... | 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,... | 6.865188 |
module ReLU(
// input [`DWIDTH-1:0] inp_data,
// output[`DWIDTH-1:0] out_data
//);
//
//assign out_data = inp_data[`DWIDTH-1] ? {`DWIDTH{1'b0}} : inp_data;
//
//endmodule
| 6.652528 |
module norm (
input enable_norm,
input [`DWIDTH-1:0] mean,
input [`DWIDTH-1:0] inv_var,
input in_data_available,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_norm,
... | 7.667513 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_S... | 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_ac... | 7.715617 |
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