code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,... | 6.865188 |
module ReLU(
// input [`DWIDTH-1:0] inp_data,
// output[`DWIDTH-1:0] out_data
//);
//
//assign out_data = inp_data[`DWIDTH-1] ? {`DWIDTH{1'b0}} : inp_data;
//
//endmodule
| 6.652528 |
module TPU_Adder (
input [32 * 8 - 1:0] data_in1,
input [32 * 8 - 1:0] data_in2,
output [32 * 8 - 1:0] data_out,
output overflow
);
wire [31:0] overflows;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin
Float8Adder inst (
.iNum1(data_in1[8*i+7:8*i]),
.iNum2(d... | 7.630956 |
module TPU_Conv_25 (
input [25 * 8 - 1:0] data_in1,
input [25 * 8 - 1:0] data_in2,
output [7:0] data_out,
output overflow
);
wire [24:0] overflows;
wire [25 * 15 - 1:0] mult_out;
wire [25 * 15 - 1:0] add_out;
assign add_out[14:0] = mult_out[14:0];
assign overflows[0] = 1'b0;
generate
... | 6.766492 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_S... | 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_ac... | 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,... | 6.865188 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_S... | 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_ac... | 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,... | 6.865188 |
module TPU_MultAdd (
input [128 * 8 - 1:0] data_in1,
input [128 * 8 - 1:0] data_in2,
output [14:0] data_out,
output wire overflow
);
wire [127:0] overflows;
wire [128 * 15 - 1:0] mult_out;
wire [128 * 15 - 1:0] add_out;
assign add_out[14:0] = mult_out[14:0];
assign overflows[0] = 1'b0;
g... | 6.581073 |
module mem_icache_12_7 (
resetn,
// CPU data bus
bus_clk,
bus_address,
bus_readdata,
bus_writedata,
bus_byteen,
bus_en,
bus_wren,
bus_wait,
// Mem hierarchy
mem_clk,
mem_filladdr,
mem_filldata,
mem_fillwe,
bus_flush, // runs on mem_clk
// Cache s... | 6.941324 |
module pipe_1_28 (
d,
clk,
resetn,
en,
squash,
q
);
input [1-1:0] d;
input clk;
input resetn;
input [28-1:0] en;
input [28-1:0] squash;
output [1*(28+1)-1:0] q;
reg [1*28-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[... | 6.9482 |
module pipe_8_28 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input [28-1:0] en;
input [28-1:0] squash;
output [8*(28+1)-1:0] q;
reg [8*28-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[... | 7.094266 |
module pipe_8_28 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input [28-1:0] en;
input [28-1:0] squash;
output [8*(28+1)-1:0] q;
reg [8*28-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[... | 7.094266 |
module bfloat_adder_16 (
input clk,
input resetn,
input en,
input stall,
input [16-1:0] a,
input [16-1:0] b,
output reg [16-1:0] out
);
always @(posedge clk) begin
if (!resetn) out <= 'h0;
else if (en) out <= a + b;
end
endmodule
| 6.882044 |
module ram_wrapper_5_32_32 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [5-1:0] address_a;
input [5-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rden... | 6.914131 |
module dpram_7_128_8 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input [7-1:0] address_a;
input [7-1:0] address_b;
input wren_a;
input wren_b;
input [8-1:0] data_a;
input [8-1:0] data_b;
output [8-1:0] out_a;
output [8-1:... | 7.16071 |
module vregfile_inc_32_8_3 (
clk,
resetn,
a_reg,
a_en,
a_readdataout,
c_reg,
c_writedatain,
c_we
);
input clk;
input resetn;
input a_en;
input [3-1:0] a_reg, c_reg;
output [32-1:0] a_readdataout;
input [32-1:0] c_writedatain;
input c_we;
ram_wrapper_3_8_32 reg_file1 ... | 7.120329 |
module local_mult_17_17_34 (
dataa,
datab,
clock,
clken,
aclr,
result
);
input [17-1:0] dataa;
input [17-1:0] datab;
input clock;
input clken;
input aclr;
output reg [34-1:0] result;
wire [17-1:0] unsignedinputA;
wire [17-1:0] unsignedinputB;
wire [34-1:0] unsignedoutputP;
... | 6.672015 |
module ram_wrapper_7_128_128 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [7-1:0] address_a;
input [7-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rd... | 7.021767 |
module dpram1_22_67108864_512 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteen_a,
byteen_b,
out_a,
out_b
);
// parameter AWIDTH=10;
// parameter NUM_WORDS=1024;
// parameter DWIDTH=32;
// parameter LOG2DWIDTH = $clog2(DWIDTH);
input clk;
input... | 7.017766 |
module register_17 (
d,
clk,
resetn,
en,
q
);
input clk;
input resetn;
input en;
input [17-1:0] d;
output [17-1:0] q;
reg [17-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.325339 |
module register_5 (
d,
clk,
resetn,
en,
q
);
input clk;
input resetn;
input en;
input [5-1:0] d;
output [5-1:0] q;
reg [5-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.165575 |
module register_1 (
d,
clk,
resetn,
en,
q
);
input clk;
input resetn;
input en;
input [1-1:0] d;
output [1-1:0] q;
reg [1-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.832907 |
module vlane_saturatesum_16 (
in,
op,
out
);
parameter WIDTH = 16;
input [WIDTH+2-1:0] in;
input [1:0] op;
output [WIDTH-1:0] out;
reg [WIDTH-1:0] out;
wire op_saturate;
wire op_signed;
assign op_saturate = op[1];
assign op_signed = op[0];
wire [WIDTH-1:0] maxunsigned;
wire [WI... | 7.414376 |
module dpram_5_32_32 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input [5-1:0] address_a;
input [5-1:0] address_b;
input wren_a;
input wren_b;
input [32-1:0] data_a;
input [32-1:0] data_b;
output [32-1:0] out_a;
output [3... | 7.96205 |
module local_shifter_17_2_ARITHMATIC (
data,
distance,
direction,
result
);
parameter LPM_SHIFTTYPE = "ARITHMATIC";
input [17-1:0] data;
input [2-1:0] distance;
input direction;
output reg [17-1:0] result;
reg [17-1:0] arith_reg;
always @* begin
arith_reg = {17{1'b1}};
if (LPM_S... | 7.322067 |
module vlane_mulshift_16_4 (
clk,
resetn,
opA,
opB,
sa,
op,
en,
result
);
parameter WIDTH = 16;
parameter LOG2WIDTH = 4;
input clk;
input resetn;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
input [LOG2WIDTH-1:0] sa;
input [4:0] op;
input [3:1] en; //Enable for each... | 8.216479 |
module vregfile_scalar_32_32_5 (
clk,
resetn,
a_reg,
a_en,
a_readdataout,
c_reg,
c_writedatain,
c_we
);
input clk;
input resetn;
input a_en;
input [5-1:0] a_reg, c_reg;
output [32-1:0] a_readdataout;
input [32-1:0] c_writedatain;
input c_we;
ram_wrapper_5_32_32 reg_f... | 7.237439 |
module dpram_3_8_32 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input [3-1:0] address_a;
input [3-1:0] address_b;
input wren_a;
input wren_b;
input [32-1:0] data_a;
input [32-1:0] data_b;
output [32-1:0] out_a;
output [32... | 6.939366 |
module local_add_sub_18_0_SIGNED (
dataa,
datab,
cin,
add_sub,
result
);
input [18-1:0] dataa;
input [18-1:0] datab;
input cin;
input add_sub;
output reg [18-1:0] result;
always @(*) begin
if (add_sub == 1'b1) result = dataa + datab + cin;
else result = dataa - datab;
end
en... | 6.568602 |
module reduction_processing_element_16_20 (
A,
B,
OUT,
MODE
);
input [16-1:0] A;
input [16-1:0] B;
output [20-1:0] OUT;
input [1:0] MODE;
wire [20-1:0] greater;
wire [20-1:0] smaller;
wire [20-1:0] sum;
assign greater = (A > B) ? A : B;
assign smaller = (A < B) ? A : B;
assign sum... | 7.129714 |
module reduction_processing_element_20_20 (
A,
B,
OUT,
MODE
);
input [20-1:0] A;
input [20-1:0] B;
output [20-1:0] OUT;
input [1:0] MODE;
wire [20-1:0] greater;
wire [20-1:0] smaller;
wire [20-1:0] sum;
assign greater = (A > B) ? A : B;
assign smaller = (A < B) ? A : B;
assign sum... | 7.129714 |
module ram_wrapper_3_8_32 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [3-1:0] address_a;
input [3-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rden_... | 7.507949 |
module pipereg_1 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [1-1:0] d;
output [1-1:0] q;
reg [1-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
... | 6.738505 |
module pipereg_17 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [17-1:0] d;
output [17-1:0] q;
reg [17-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <=... | 7.078539 |
module pipereg_1 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [1-1:0] d;
output [1-1:0] q;
reg [1-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
... | 6.738505 |
module pipereg_8 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [8-1:0] d;
output [8-1:0] q;
reg [8-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
... | 7.267674 |
module pipereg_65 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [65-1:0] d;
output [65-1:0] q;
reg [65-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <=... | 7.340723 |
module pipereg_32 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [32-1:0] d;
output [32-1:0] q;
reg [32-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <=... | 7.124819 |
module pipereg_5 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [5-1:0] d;
output [5-1:0] q;
reg [5-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
... | 7.022103 |
module pipereg_5 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [5-1:0] d;
output [5-1:0] q;
reg [5-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
... | 7.022103 |
module pipereg_32 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [32-1:0] d;
output [32-1:0] q;
reg [32-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <=... | 7.124819 |
module pipereg_6 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [6-1:0] d;
output [6-1:0] q;
reg [6-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
... | 6.857215 |
module pipereg_2 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [2-1:0] d;
output [2-1:0] q;
reg [2-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
... | 6.873167 |
module pipereg_1 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [1-1:0] d;
output [1-1:0] q;
reg [1-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
... | 6.738505 |
module vregfile_stride_32_8_3 (
clk,
resetn,
a_reg,
a_en,
a_readdataout,
c_reg,
c_writedatain,
c_we
);
input clk;
input resetn;
input a_en;
input [3-1:0] a_reg, c_reg;
output [32-1:0] a_readdataout;
input [32-1:0] c_writedatain;
input c_we;
ram_wrapper_3_8_32 reg_fil... | 6.888041 |
module vlane_saturatesize(
in,
op,
out
);
parameter WIDTH=32;
input [WIDTH-1:0] in;
input [3:0] op;
output [WIDTH-1:0] out;
wire op_outsigned;
wire op_signed;
wire op_size;
reg [WIDTH-1:0] out;
assign op_outsigned=op[3];
assign op_signed=op[2];
assign op_size=op[1:0]; //0 - word, 1 - byte, 2 ... | 7.414376 |
module dpram_7_128_128 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input [7-1:0] address_a;
input [7-1:0] address_b;
input wren_a;
input wren_b;
input [128-1:0] data_a;
input [128-1:0] data_b;
output [128-1:0] out_a;
outp... | 7.144072 |
module ram_wrapper_4_16_32 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [4-1:0] address_a;
input [4-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rden... | 7.79626 |
module pipe_1_2 (
d,
clk,
resetn,
en,
squash,
q
);
input [1-1:0] d;
input clk;
input resetn;
input [2-1:0] en;
input [2-1:0] squash;
output [1*(2+1)-1:0] q;
reg [1*2-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[1-1:0... | 6.739448 |
module pipe_4_2 (
d,
clk,
resetn,
en,
squash,
q
);
input [4-1:0] d;
input clk;
input resetn;
input [2-1:0] en;
input [2-1:0] squash;
output [4*(2+1)-1:0] q;
reg [4*2-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[4-1:0... | 6.555797 |
module pipe_8_2 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input [2-1:0] en;
input [2-1:0] squash;
output [8*(2+1)-1:0] q;
reg [8*2-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[8-1:0... | 6.878884 |
module pipe_7_5 (
d,
clk,
resetn,
en,
squash,
q
);
input [7-1:0] d;
input clk;
input resetn;
input [5-1:0] en;
input [5-1:0] squash;
output [7*(5+1)-1:0] q;
reg [7*5-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[7-1:0... | 6.613178 |
module pipe_1_3 (
d,
clk,
resetn,
en,
squash,
q
);
input [1-1:0] d;
input clk;
input resetn;
input [3-1:0] en;
input [3-1:0] squash;
output [1*(3+1)-1:0] q;
reg [1*3-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[1-1:0... | 6.651202 |
module pipe_8_1 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input en;
input squash;
output [8*(1+1)-1:0] q;
reg [8*1-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash) tq[8-1:0] <= 0;
else if... | 6.619595 |
module pipe_32_4 (
d,
clk,
resetn,
en,
squash,
q
);
input [32-1:0] d;
input clk;
input resetn;
input [4-1:0] en;
input [4-1:0] squash;
output [32*(4+1)-1:0] q;
reg [32*4-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[3... | 7.524638 |
module pipe_8_1 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input en;
input squash;
output [8*(1+1)-1:0] q;
reg [8*1-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash) tq[8-1:0] <= 0;
else if... | 6.619595 |
module pipe_8_1 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input en;
input squash;
output [8*(1+1)-1:0] q;
reg [8*1-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash) tq[8-1:0] <= 0;
else if... | 6.619595 |
module
////////////////////////////////////////////
module reduction_layer_16_4_32_5_10
(
input clk,
input resetn, //resets the processing elements
input en, //indicates valid reduction operation
input [1:0] reduction_type, //can have 3 values: 0 (Add), 1 (Max), 2 (Min)
input read,
input [8 * 16 -1:0] a,... | 6.558648 |
module dpram_4_16_32 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input [4-1:0] address_a;
input [4-1:0] address_b;
input wren_a;
input wren_b;
input [32-1:0] data_a;
input [32-1:0] data_b;
output [32-1:0] out_a;
output [3... | 7.275288 |
module ram_wrapper_5_32_32 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [5-1:0] address_a;
input [5-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rden... | 6.914131 |
module ram_wrapper_7_128_8 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [7-1:0] address_a;
input [7-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rden... | 7.021767 |
module rounding_20_16 (
i_data,
o_data
);
input [20-1:0] i_data;
output [16-1:0] o_data;
wire [20-1:0] w_convergent;
assign w_convergent = i_data[(20-1):0]
+ { {(16){1'b0}},
i_data[(20-16)],
{(20-16-1){!i_data[(20-16)]}}};
assign o_data = w_convergent[(20-1):(... | 7.312513 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module vregfile_control_32_32_5 (
clk,
resetn,
a_reg,
a_en,
a_readdataout,
c_reg,
c_writedatain,
c_we,
vl,
matmul_masks
);
input clk;
input resetn;
input a_en;
input [5-1:0] a_reg, c_reg;
output [32-1:0] a_readdataout;
input [32-1:0] c_writedatain;
input c_we;
... | 8.151167 |
module addersub_32 (
opA,
opB,
op,
result,
result_slt
);
input [32-1:0] opA;
input [32-1:0] opB;
//input carry_in;
input [3-1:0] op;
output [32-1:0] result;
output result_slt;
wire carry_out;
wire [32:0] sum;
// Mux between sum, and slt
wire is_slt;
wire signext;
wire add... | 7.769077 |
module local_add_sub_33_0_SIGNED (
dataa,
datab,
cin,
add_sub,
result
);
input [33-1:0] dataa;
input [33-1:0] datab;
input cin;
input add_sub;
output reg [33-1:0] result;
always @(*) begin
if (add_sub == 1'b1) result = dataa + datab + cin;
else result = dataa - datab;
end
en... | 6.568602 |
module logic_unit_32 (
opA,
opB,
op,
result
);
input [32-1:0] opA;
input [32-1:0] opB;
input [2-1:0] op;
output [32-1:0] result;
reg [32-1:0] logic_result;
always @(opA or opB or op)
case (op)
2'b00: logic_result = opA & opB;
2'b01: logic_result = opA | opB;
2'b10: l... | 8.293771 |
module register_32 (
d,
clk,
resetn,
en,
q
);
input clk;
input resetn;
input en;
input [32-1:0] d;
output [32-1:0] q;
reg [32-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.25423 |
module register_2 (
d,
clk,
resetn,
en,
q
);
input clk;
input resetn;
input en;
input [2-1:0] d;
output [2-1:0] q;
reg [2-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.170601 |
module branchpredict_32_4096_12_1 ( clk, resetn,
predict,
prediction,
pc_predict,
result_rdy,
result,
pc_result);
input clk;
input resetn;
// Prediction Port
input predict; // When high tells predictor to predict in next cycle
input [32-1:0] pc_predict; // The PC value for whi... | 7.210838 |
module mul_32 (
clk,
resetn,
start,
stalled,
dst,
opA,
opB,
sa,
op,
shift_result,
hi,
lo
);
input clk;
input resetn;
input start;
output stalled;
input [4:0] dst;
input [32-1:0] opA;
input [32-1:0] opB;
input [5-1:0] sa;
input [2:0] op;
output [32... | 7.227089 |
module local_mult_33_33_66 (
dataa,
datab,
clock,
clken,
aclr,
result
);
input [33-1:0] dataa;
input [33-1:0] datab;
input clock;
input clken;
input aclr;
output reg [66-1:0] result;
wire [33-1:0] unsignedinputA;
wire [33-1:0] unsignedinputB;
wire [66-1:0] unsignedoutputP;
... | 6.784166 |
module div_0_1_2 (
en,
resetn,
stalled,
quotient,
remainder,
dividend,
divider,
sign,
clk
);
input clk;
input resetn;
input sign;
input en;
input [31:0] dividend, divider;
output [31:0] quotient, remainder;
output stalled;
reg [31:0] quotient, quotient_temp;
reg [... | 6.704407 |
module data_mem_32_32_4_16_16384 (
clk,
resetn,
en,
stalled,
d_writedata,
d_address,
op,
d_loadresult,
ecause,
boot_daddr,
boot_ddata,
boot_dwe,
bus_address,
bus_byteen,
bus_we,
bus_en,
bus_writedata,
bus_readdata,
bus_wait,
bus_ecause
)... | 6.697471 |
module store_data_translator_32 (
write_data, // data in least significant position
d_address,
store_size,
d_byteena,
d_writedataout
); // shifted data to coincide with address
input [32-1:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d_byteena;
output [32-1... | 8.280191 |
module load_data_translator_32 (
d_readdatain,
d_address,
load_size,
load_sign_ext,
d_loadresult
);
input [32-1:0] d_readdatain;
input [1:0] d_address;
input [1:0] load_size;
input load_sign_ext;
output [32-1:0] d_loadresult;
reg [32-1:0] d_loadresult;
always @(d_readdatain or d_add... | 9.105161 |
module ram_wrapper_5_32_32 (
// clk,
// resetn,
// address_a,
// address_b,
// rden_a,
// rden_b,
// wren_a,
// wren_b,
// data_a,
// data_b,
// out_a,
// out_b
//);
//
//input clk;
//input resetn;
//input [(5-1):0] address_a;
//input [(5-1):0] address_b;
//input wren_a;
//input wren_b;
//input ... | 6.914131 |
module dpram_5_32_32 (
// clk,
// address_a,
// address_b,
// wren_a,
// wren_b,
// data_a,
// data_b,
// out_a,
// out_b
//);
//
//input clk;
//input [(5-1):0] address_a;
//input [(5-1):0] address_b;
//input wren_a;
//input wren_b;
//input [(32-1):0] data_a;
//input [(32-1):0] data_b;
//output reg [(32-1):0] out_a;
... | 7.96205 |
module pcadder_32 (
pc,
offset,
result
);
input [32-1:0] pc;
input [32-1:0] offset;
output [32-1:0] result;
// not connect ports
wire [32-1:0] offset_nc;
assign offset_nc = offset;
wire dum;
assign {dum, result} = pc + {offset[32-3:0], 2'b0};
endmodule
| 7.043462 |
module signext16 (
in,
out
);
input [15:0] in;
output [31:0] out;
assign out = {{{{16{{in[15]}}}}, in[15:0]}};
endmodule
| 7.934159 |
module branchresolve_32 (
en,
rs,
rt,
eq,
ne,
ltz,
lez,
gtz,
gez,
eqz
);
parameter WIDTH = 32;
input en;
input [WIDTH-1:0] rs;
input [WIDTH-1:0] rt;
output eq;
output ne;
output ltz;
output lez;
output gtz;
output gez;
output eqz;
assign eq = (en) & (rs ... | 9.028008 |
module lo_reg_32 (
d,
clk,
resetn,
squashn,
en,
q
);
input clk;
input resetn;
input squashn;
input en;
input [32-1:0] d;
output [32-1:0] q;
reg [32-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1 && s... | 7.658015 |
module const_32_0 (
out
);
output [32-1:0] out;
assign out = 0;
endmodule
| 6.943542 |
module const_32_16 (
out
);
output [32-1:0] out;
assign out = 16;
endmodule
| 7.582393 |
module const_32_31 (
out
);
output [32-1:0] out;
assign out = 31;
endmodule
| 7.210659 |
module pipereg_32(d,clk,resetn,en,squashn,q);
//
//input clk;
//input resetn;
//input en;
//input squashn;
//input [32-1:0] d;
//output [32-1:0] q;
//reg [32-1:0] q;
//
//always @(posedge clk) //synchronous reset
//begin
// if (resetn==0 || squashn==0)
// q<=0;
// else if (en==1)
// q<=d;
//end
//
//endmodule... | 7.03887 |
module pipereg_5(d,clk,resetn,en,squashn,q);
//
//input clk;
//input resetn;
//input en;
//input squashn;
//input [5-1:0] d;
//output [5-1:0] q;
//reg [5-1:0] q;
//
//always @(posedge clk) //synchronous reset
//begin
// if (resetn==0 || squashn==0)
// q<=0;
// else if (en==1)
// q<=d;
//end
//
//endmodule
| 6.672761 |
module nop_32 (
d,
q
);
input [32-1:0] d;
output [32-1:0] q;
assign q = d;
endmodule
| 7.567936 |
module zeroer_5 (
d,
en,
q
);
input en;
input [5-1:0] d;
output [5-1:0] q;
assign q = (en) ? d : 0;
endmodule
| 6.817711 |
module cop2 (
clk,
resetn,
stalled,
fromcpu,
fromcpu_en,
tocpu,
tocpu_en,
//Global I/O
tocop2,
tocop2_en,
tocop2_wait,
fromcop2,
fromcop2_en,
fromcop2_wait
);
input clk;
input resetn;
output stalled;
input [31:0] fromcpu;
input fromcpu_en;
output [... | 7.323016 |
module cop0 (
clk,
resetn,
stalled,
instr,
exception,
read_addr,
dest_addr,
fromcpu,
fromcpu_en,
tocpu,
tocpu_en,
epc_in,
ext_cause_in,
int_cause_in_stage1, //very weak - implement OR in SPREE instead
int_cause_in_stage2,
status,
badvaddr_in,
... | 6.731171 |
module pipereg_6(d,clk,resetn,en,squashn,q);
//
//input clk;
//input resetn;
//input en;
//input squashn;
//input [6-1:0] d;
//output [6-1:0] q;
//reg [6-1:0] q;
//
//always @(posedge clk) //synchronous reset
//begin
// if (resetn==0 || squashn==0)
// q<=0;
// else if (en==1)
// q<=d;
//end
//
//endmodule
| 6.611143 |
module branch_detector (
opcode,
func,
is_branch
);
input [5:0] opcode;
input [5:0] func;
output is_branch;
wire is_special;
wire [5:0] func_local;
assign func_local = func & 6'b111000;
assign is_special = !(|opcode);
assign is_branch=((!(|opcode[5:3])) && !is_special) ||
... | 7.697954 |
module vmem_busmux_128_7_32_5 (
clk,
resetn,
sel,
in,
out
);
parameter SELWIDTH = 7 - 5; // LOG2(INWIDTH/OUTWIDTH) = 4
input clk;
input resetn;
input [SELWIDTH-1 : 0] sel;
input [128-1 : 0] in;
output [32-1 : 0] out;
reg [32-1 : 0] out;
wire clk_nc, resetn_nc;
assign clk_nc = ... | 6.612997 |
module vmem_crossbar_128_7_8_32_5 (
clk,
resetn,
sel,
in,
out
);
parameter SELWIDTH = 7 - 5; // LOG2(INWIDTH/OUTWIDTH) = 4
input clk;
input resetn;
input [(SELWIDTH*8)-1 : 0] sel;
input [128-1 : 0] in;
output [(32*8)-1 : 0] out;
vmem_busmux_128_7_32_5 bmux0 (
clk,
rese... | 7.332389 |
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