code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tristate_test (
input wire active1,
input wire active2,
output wire [31:0] wbs_dat
);
wrapped_picorv32 pico1 (
.active(active1),
.vccd1(1'b1),
.vssd1(1'b0),
.wbs_dat_o(wbs_dat)
);
wrapped_picorv32 pico2 (
.active(active2),
.vccd1(1'b1),
.vssd1(1'b0),
... | 7.63903 |
module tristate1_tb ();
//-- Pausa pequeña: divisor
localparam DELAY = 4;
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Led a controlar
wire led0;
//-- Instanciar el componente
tristate1 #(
.DELAY(DELAY)
) dut (
.clk (clk),
.led0(led0)
);
//-- Generador de ... | 7.312319 |
module triDriver (
bus,
drive,
value
);
inout [3:0] bus;
input drive;
input [3:0] value;
assign #2 bus = (drive == 1) ? value : 4'bz;
endmodule
| 6.730723 |
module tristate2_tb ();
//-- Pausa pequeña: divisor
localparam DELAY = 4;
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Led a controlar
wire led0;
//-- Instanciar el componente
tristate2 #(
.DELAY(DELAY)
) dut (
.clk (clk),
.led0(led0)
);
//-- Generador de ... | 6.832569 |
module tristate32 (
out,
in,
selector
);
input [31:0] in;
output [31:0] out;
input selector;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : tristate32
assign out[i] = selector ? (in[i] ? 1'b1 : 1'b0) : 1'bz;
end
endgenerate
endmodule
| 7.258794 |
module tristate541 (
Y,
A,
G1_L,
G2_L
);
parameter SIZE = 8;
output [SIZE-1:0] Y;
input [SIZE-1:0] A;
input G1_L, G2_L;
wire GL;
nor n1 (GL, G1_L, G2_L);
genvar k;
generate
for (k = 0; k < SIZE; k = k + 1) begin : LOOP
bufif1 g1 (Y[k], A[k], GL);
end
endgenerate
endmo... | 7.466799 |
module tristate8port (
input enable,
input [7:0] in,
output [7:0] out
);
assign out = (enable) ? in : 8'bzzzzzzzz;
endmodule
| 7.921641 |
module tristatebuf (
input data,
input en,
output y
);
//always@(en,data)
assign y = en ? data : 'bz;
endmodule
| 7.163524 |
module tristateBuff1 (
input wire D,
input wire nOE,
output wire Q
);
assign Q = nOE == 1'b0 ? D : 1'bz;
endmodule
| 7.164283 |
module tristateBuff8 (
input wire [7:0] D,
input wire nOE,
output wire [7:0] Q
);
assign Q = nOE == 1'b0 ? D : 8'hz;
endmodule
| 7.593971 |
module tristateBuff16 (
input wire [15:0] D,
input wire nOE,
output wire [15:0] Q
);
assign Q = nOE == 1'b0 ? D : 16'hz;
endmodule
| 7.164283 |
module triStateBuffer (
out,
enable,
in
);
input enable;
input [31:0] in;
output [31:0] out;
assign out = enable ? in : 32'bz;
endmodule
| 7.116795 |
module TriStateBuffer16b (
input [15:0] in,
input triStateCtrl,
output reg [15:0] out
);
initial out = 16'hZZZZ;
always @(*) begin
out = triStateCtrl ? in : 16'hZZZZ;
end
endmodule
| 6.521856 |
module triStateBufferDecoder32 (
ctrl_read,
w_0,
w_1,
w_2,
w_3,
w_4,
w_5,
w_6,
w_7,
w_8,
w_9,
w_10,
w_11,
w_12,
w_13,
w_14,
w_15,
w_16,
w_17,
w_18,
w_19,
w_20,
w_21,
w_22,
w_23,
w_24,
w_25,
w_26,
w_27,
... | 7.116795 |
module tristatebuff_4bit (
in,
out,
low_en
);
input [3:0] in;
input low_en;
output tri [3:0] out;
assign out = low_en ? 4'bzzzz : in; //pass the output when enable is 0
endmodule
| 7.204138 |
module tristatebuff_8bit (
in,
out,
low_en
);
input [7:0] in;
input low_en;
output tri [7:0] out;
assign out = low_en ? 8'bzzzzzzzz : in; //pass the output when enable is 0
endmodule
| 7.204138 |
module tristatenet #(
parameter INPUT_COUNT = 2,
parameter WIDTH = 8
) (
input wire [WIDTH*INPUT_COUNT-1:0] i_data,
input wire [INPUT_COUNT-1:0] i_noe,
output reg [WIDTH-1:0] o_data,
output reg o_noe
);
integer i;
reg [INPUT_COUNT-1:0] ones;
always @* begin
o_data <= {WIDTH{1'b1}};
... | 7.617901 |
module TristateRegBlock (
inWidth,
inHeight,
inAnimSteps,
outWidth,
outHeight,
outAnimSteps,
oe
);
input oe; // output enable
input [5:0] inWidth, inHeight;
input [2:0] inAnimSteps;
output [5:0] outWidth, outHeight;
output [2:0] outAnimSteps;
NBitTristate TriWidth (
inWid... | 7.163066 |
module tristate_8bit (
input T,
input [7:0] I,
output [7:0] O
);
assign O = T ? I : 8'bZ;
endmodule
| 7.73421 |
module tristate_buffer #(
parameter N = 1
) (
data_in,
enable,
data_out
);
/*********** Inputs ***********/
input [N-1:0] data_in;
input enable;
/*********** Outputs ***********/
output [N-1:0] data_out;
/*********** Logic ***********/
assign data_out = enable ? data_in : 'bz;
endmodul... | 7.32675 |
module tristate_buffer_tb ();
localparam T = 100;
reg counter;
reg data_in;
reg enable;
wire data_out;
tristate_buffer #(1) tri_bufO (
data_in,
enable,
data_out
);
initial begin
$display("data_in enable data_out");
$monitor(" %b\t\t%b\t%b", data_in, enable, data_out)... | 7.32675 |
module tristate_generic #(
parameter N = 8
) (
input wire [N-1:0] in,
input wire en,
output reg [N-1:0] out
);
always @(*) begin
if (en == 1) out = in;
else out = 'bz;
end
endmodule
| 8.463288 |
module tristate_io #(
parameter SYNC_OUT = 0,
parameter SYNC_IN = 0,
parameter PULLUP = 0
) (
input wire clk,
input wire rst_n,
input wire out,
input wire oe,
output wire in,
inout wire pad
);
// ----------------------------------------------------------------------------
... | 8.790887 |
module tristate_output (
output pin,
input wire enable,
input wire value
);
SB_IO #(
.PIN_TYPE(6'b1010_01),
.PULLUP (1'b0),
) sb_io (
.PACKAGE_PIN(pin),
.OUTPUT_ENABLE(enable),
.D_OUT_0(value),
);
endmodule
| 6.861282 |
module tristate_port (
inout io_pin,
input i_write,
output o_read
);
assign o_read = io_pin;
assign io_pin = (i_write ? 1'bz : 1'b0);
endmodule
| 7.247004 |
module TristateBuffer_Test;
// Input and outputs
logic [7:0] in, out;
// Control
logic c;
// Instantiate modules
TristateBuffer #(
.WIDTH(8)
) buffer (
.in (in),
.out(out),
.c (c)
);
initial begin
$display("Tristate buffer");
$monitor($time, " IN=%x, OUT=%x, C=%x", ... | 6.848933 |
module trivial (
input a,
input b,
output c
);
assign c = a ^ b;
endmodule
| 6.541817 |
module trivial2 (
input a,
input b,
output c
);
wire tmp1;
assign tmp1 = ~a ^ b;
wire t3o1;
wire t3o2;
trivial2a t3 (
tmp1,
t3o1,
t3o2
);
wire tmp2;
assign tmp2 = t3o1 & t3o2;
assign c = !tmp2;
endmodule
| 6.709495 |
module toplevel (
xa,
xb,
xc
);
input [10:0] xa;
input [10:0] xb;
output ya, yb;
wire [41:42] q;
reg b, c, d;
my_module #(
.BLAH(Q)
) my_name (
.a (xa),
.b (1),
.pq(1'b1),
.er(16'habcd_123),
.tr(4'd12),
.c (ya)
);
//assign ya = &xa;
//assign... | 8.460384 |
module triwire: bidirectional wire bus model with delay
*
* This module models the two ends of a bidirectional bus with
* transport (not inertial) delays in each direction. The
* bus has a width of WIDTH and the delays are as follows:
* a->b has a delay of Ta_b (in `timescale units)
* b->a has a delay of Tb_a (in `time... | 7.568704 |
module TriWireFixed #(
parameter WIDTH = 1
) (
inout wire [WIDTH-1:0] a,
b
);
tran (a, b); //not supported by xilinx ISE, even just in simulation :-S
specify
(a *> b) = (1, 1);
(b *> a) = (1, 1);
endspecify
endmodule
| 6.781771 |
module tri_agecmp (
a,
b,
a_newer_b
);
parameter SIZE = 8;
input [0:SIZE-1] a;
input [0:SIZE-1] b;
output a_newer_b;
// tri_agecmp
wire a_lt_b;
wire a_gte_b;
wire cmp_sel;
assign a_lt_b = (a[1:SIZE-1] < b[1:SIZE-1]) ? 1'b1 : 1'b0;
assign a_gte_b = (~a_lt_b);
assign cmp_sel = a[0]... | 6.507951 |
module tri_aoi21 (
y,
a0,
a1,
b0
);
parameter WIDTH = 1;
parameter BTR = "AOI21_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a0;
input [0:WIDTH-1] a1;
input [0:WIDTH-1] b0;
// tri_aoi21
genvar i;
wire [0:WIDTH-1] outA;
generate
... | 7.135106 |
module tri_aoi22 (
y,
a0,
a1,
b0,
b1
);
parameter WIDTH = 1;
parameter BTR = "AOI22_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a0;
input [0:WIDTH-1] a1;
input [0:WIDTH-1] b0;
input [0:WIDTH-1] b1;
// tri_aoi22
genvar i;
wire... | 7.701163 |
module tri_buf (
y,
a,
oe_n
);
parameter delay = 13;
input wire a;
input wire oe_n;
output wire y;
`ifdef TARGET_FPGA
assign y = (oe_n == 1'b0) ? a : 1'b0;
`else
assign #delay y = (oe_n == 1'b0) ? a : 1'bZ;
`endif
endmodule
| 7.410938 |
module tri_buffer_4bit (
input [3:0] signal_in,
input ctrl,
output reg [3:0] signal_out
);
always @(*) begin
if (ctrl == 0) signal_out = 4'bz;
else if (ctrl == 1) signal_out = signal_in;
end
endmodule
| 7.845289 |
module tri_compare (
clk,
a,
b,
c,
max,
mid,
min
);
parameter width = 8;
input clk;
input [width - 1:0] a;
input [width - 1:0] b;
input [width - 1:0] c;
output [width - 1:0] max;
reg [width - 1:0] max;
output [width - 1:0] mid;
reg [width - 1:0] mid;
output [width - 1:0]... | 7.012882 |
module tri_compare (
clk,
a,
b,
c,
max,
mid,
min
);
parameter width = 8;
input clk;
input [width - 1:0] a;
input [width - 1:0] b;
input [width - 1:0] c;
output [width - 1:0] max;
reg [width - 1:0] max;
output [width - 1:0] mid;
reg [width - 1:0] mid;
output [width - 1:0]... | 7.012882 |
module tri_csa32 (
a,
b,
c,
car,
sum,
vd,
gd
);
input a;
input b;
input c;
output car;
output sum;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *) (* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout vd;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *) (* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout gd;
wire car... | 7.321591 |
module tri_csa42 (
a,
b,
c,
d,
ki,
ko,
car,
sum,
vd,
gd
);
input a;
input b;
input c;
input d;
input ki;
output ko;
output car;
output sum;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *) (* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout vd;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *) (... | 7.120831 |
module tri_debug_mux4 (
// vd,
// gd,
select_bits,
dbg_group0,
dbg_group1,
dbg_group2,
dbg_group3,
trace_data_in,
trace_data_out,
// Instruction Trace (HTM) Controls
coretrace_ctrls_in,
coretrace_ctrls_out
);
// Include model build parameters
parameter DBG_WIDTH... | 7.764024 |
module tri_direct_err_rpt (
vd,
gd,
err_in,
err_out
);
parameter WIDTH = 1; // use to bundle error reporting checkers of the same exact type
inout vd;
inout gd;
input [0:WIDTH-1] err_in;
output [0:WIDTH-1] err_out;
// tri_direct_err_rpt
(* analysis_not_referenced="true" *)
wire unuse... | 7.651156 |
module tri_err_rpt (
vd,
gd,
err_d1clk,
err_d2clk,
err_lclk,
err_scan_in,
err_scan_out,
mode_dclk,
mode_lclk,
mode_scan_in,
mode_scan_out,
err_in,
err_out,
hold_out,
mask_out
);
parameter WIDTH = 1; // number of errors of the same type
parameter MASK_RESE... | 8.813933 |
module tri_fu_csa22_h2 (
a,
b,
car,
sum
);
input a;
input b;
output car;
output sum;
wire car_b;
wire sum_b;
assign car_b = (~(a & b));
assign sum_b = (~(car_b & (a | b))); // this is equiv to an xnor
assign car = (~car_b);
assign sum = (~sum_b);
endmodule
| 6.614777 |
module tri_gen (
clk,
res,
d_out
);
input clk;
input res;
output [8:0] d_out;
reg [1:0] state; //主状态机的寄存器
reg [8:0] d_out;
reg [7:0] con; //计数器用于记录平顶周期个数
always @(posedge clk or negedge res) begin
if (~res) begin
state <= 0;
d_out <= 0;
con <= 0;
end else begin
... | 7.18462 |
module tri_gen_tb;
reg clk;
reg res;
wire [8:0] d;
tri_gen tri_gen (
.clk (clk),
.res (res),
.d_out(d)
);
initial begin
clk <= 0;
res <= 0;
#17 res <= 1;
#40000 $stop;
end
always #5 clk <= ~clk;
initial begin
$dumpfile("tri_gen_tb.vcd");
$dum... | 6.833462 |
module tri_gt (
OE,
id,
od
);
input wire OE;
input wire [15:0] id;
output wire [15:0] od;
assign od = (!OE) ? 16'dz : id;
endmodule
| 6.995172 |
module tri_inv (
y,
a
);
parameter WIDTH = 1;
parameter BTR = "INV_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
// tri_nand2
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
not I0 (y[i], a[i]);
... | 7.509959 |
module tri_inv_nlats (
vd,
gd,
lclk,
d1clk,
d2clk,
scanin,
scanout,
d,
qb
);
parameter OFFSET = 0;
parameter WIDTH = 1;
parameter INIT = 0;
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_latch,3=L2,4=... | 7.23967 |
module tri_io_buf #(
parameter WIDTH = 1
) (
input wire [WIDTH-1:0] din,
input wire oen_N,
inout wire [WIDTH-1:0] io_pad,
output wire [WIDTH-1:0] dout
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
IOBUF #(
.DRIVE (12), // Specify t... | 9.017246 |
module tri_lcbcntl_array_mac (
vdd,
gnd,
sg,
nclk,
scan_in,
scan_diag_dc,
thold,
clkoff_dc_b,
delay_lclkr_dc,
act_dis_dc,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
scan_out
);
inout vdd;
inout gnd;
input sg;
input [0:`NCLK_WIDTH-1] nclk;
input scan_in;
input sc... | 6.693849 |
module tri_lcbnd (
vd,
gd,
act,
delay_lclkr,
mpw1_b,
mpw2_b,
nclk,
force_t,
sg,
thold_b,
d1clk,
d2clk,
lclk
);
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input act;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input [0:`NCLK_WIDTH-1] nclk;
... | 7.722264 |
module tri_lcbs (
vd,
gd,
delay_lclkr,
nclk,
force_t,
thold_b,
dclk,
lclk
);
inout vd;
inout gd;
input delay_lclkr;
input [0:`NCLK_WIDTH-1] nclk;
input force_t;
input thold_b;
output dclk;
output [0:`NCLK_WIDTH-1] lclk;
// tri_lcbs
(* analysis_not_referenced="true"... | 6.98358 |
module tri_mode_ethernet_mac_0_axi_mux (
input mux_select,
// mux inputs
input [7:0] tdata0,
input tvalid0,
input tlast0,
output reg tready0,
input [7:0] tdata1,
input tvalid1,
input tlast1,
output reg tready1,
... | 6.950534 |
module to simplify the timing where a pattern
// generator and address swap module can be muxed into the data path
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module tri_mode_ethernet_mac_0_axi_pipe (
input axi_tclk,
input ... | 6.900006 |
module tri_mode_ethernet_mac_0_clk_wiz ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
// Status and control signals
input RESET,
output LOCKED
);
// Clocking primitive
//------------------------------------
// Instantiat... | 6.950534 |
module tri_mode_ethernet_mac_0_example_design_clocks (
input gtx_clk,
// clock outputs
output gtx_clk_bufg,
output s_axi_aclk
);
//----------------------------------------------------------------------------
// Transmitter Clock logic for gtx_clk
//----------------------------------------------... | 6.950534 |
module tri_mode_ethernet_mac_0_example_design_resets (
// clocks
input s_axi_aclk,
input gtx_clk,
// asynchronous resets
input glbl_rst,
input reset_error,
input rx_reset,
input tx_reset,
// asynchronous reset output
output glbl_rst_intn,
// synchronous reset outputs
... | 6.950534 |
module tri_mode_ethernet_mac_0_reset_sync #(
parameter INITIALISE = 1'b1,
parameter DEPTH = 5
) (
input reset_in,
input clk,
input enable,
output reset_out
);
wire reset_sync_reg0;
wire reset_sync_reg1;
wire reset_sync_reg2;
wire reset_sync_reg3;
wire reset_sync_reg4;
(* ASYNC_... | 6.950534 |
module holds the shared resets for the IDELAYCTRL
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
module tri_mode_ethernet_mac_0_support_resets
(
input glbl_rstn,
input refclk,
input idelayctrl_ready,
output i... | 7.143026 |
module tri_mode_ethernet_mac_0_syncer_level #(
parameter WIDTH = 1,
parameter RESET_VALUE = 1'b0
) (
input wire clk,
input wire reset,
input wire [WIDTH-1:0] datain,
output wire [WIDTH-1:0] dataout
);
(* ASYNC_REG = "TRUE" *)reg [WIDTH-1:0] dataout_reg;
reg [WIDTH-1:0] meta_nxt;
... | 6.950534 |
module tri_mode_ethernet_mac_0_sync_block #(
parameter INITIALISE = 1'b0,
parameter DEPTH = 5
) (
input clk, // clock to be sync'ed to
input data_in, // Data to be 'synced'
output data_out // synced data
);
// Internal Signals
wire data_sync0;
wire data_sync1;
wire data_sync2;
wi... | 6.950534 |
module tri_mode_eth_mac_v5_2 (
//---------------------------------------
// asynchronous reset
input glbl_rstn,
input rx_axi_rstn,
input tx_axi_rstn,
//---------------------------------------
// Receiver Interface
input rx_axi_clk,
output rx_reset_out,
output [ 7... | 7.873981 |
module tri_nand2 (
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "NAND2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
// tri_nand2
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : ... | 7.742585 |
module tri_nand2_nlats (
vd,
gd,
lclk,
d1clk,
d2clk,
scanin,
scanout,
a1,
a2,
qb
);
parameter OFFSET = 0;
parameter WIDTH = 1;
parameter INIT = 0;
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_la... | 6.806358 |
module tri_nand3 (
y,
a,
b,
c
);
parameter WIDTH = 1;
parameter BTR = "NAND3_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
input [0:WIDTH-1] c;
// tri_nand3
genvar i;
generate
begin : t
for (i = 0; ... | 7.920777 |
module tri_nand4 (
y,
a,
b,
c,
d
);
parameter WIDTH = 1;
parameter BTR = "NAND4_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
input [0:WIDTH-1] c;
input [0:WIDTH-1] d;
// tri_nand3
genvar i;
generate
... | 8.0048 |
module tri_nlat (
vd,
gd,
d1clk,
d2clk,
lclk,
scan_in,
din,
q,
q_b,
scan_out
);
parameter OFFSET = 0;
parameter SCAN = 0; //SCAN = normal;
//0=normal,1=interleaved,2=reversed,3=reverse_interleaved
parameter RESET_INVERTS_SCAN = 1'b1;
parameter WIDT... | 7.232446 |
module tri_nlat_scan (
vd,
gd,
d1clk,
d2clk,
lclk,
din,
scan_in,
q,
q_b,
scan_out
);
parameter OFFSET = 0;
parameter WIDTH = 1;
parameter INIT = 0;
parameter RESET_INVERTS_SCAN = 1'b1;
parameter SYNTHCLONEDLATCH = "";
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = sl... | 7.138693 |
module tri_nor2 (
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "NOR2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
// tri_nor2
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
... | 6.915532 |
module tri_nor3 (
y,
a,
b,
c
);
parameter WIDTH = 1;
parameter BTR = "NOR3_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
input [0:WIDTH-1] c;
// tri_nor3
genvar i;
generate
begin : t
for (i = 0; i <... | 7.989546 |
module tri_oai21 (
y,
a0,
a1,
b0
);
parameter WIDTH = 1;
parameter BTR = "OAI21_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a0;
input [0:WIDTH-1] a1;
input [0:WIDTH-1] b0;
// tri_oai21
genvar i;
wire [0:WIDTH-1] outA;
generate
... | 7.0944 |
module tri_plat (
vd,
gd,
nclk,
flush,
din,
q
);
parameter WIDTH = 1;
parameter OFFSET = 0;
parameter INIT = 0; // will be converted to the least signficant 31 bits of init_v
parameter SYNTHCLONEDLATCH = "";
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input flush;
input... | 6.587067 |
module tri_ported_fifo #(
parameter WIDTH = 64,
parameter DEPTH = 24
) (
input wire [WIDTH-1:0] data_in1,
input wire [WIDTH-1:0] data_in2,
input wire [WIDTH-1:0] data_in3,
input wire clk,
input wire rst,
input wire write1,
input wire write2,
input wire write3,
input wire read... | 8.457516 |
module tri_port_regfile #(
parameter SINGLE_ENTRY_SIZE_IN_BITS = 8,
parameter NUM_ENTRY = 4
) (
input reset_in,
input clk_in,
input read_en_in,
input write_en_in,
input cam_en_in,
input [ NUM_ENTRY - 1 : 0] read_entry_addr_decoded_in,
input [ ... | 7.817528 |
module tri_pri (
cond,
pri,
or_cond
);
parameter SIZE = 32; // Size of "cond", range 3 - 32
parameter REV = 0; // 0 = 0 is highest, 1 = 0 is lowest
parameter CMP_ZERO = 0; // 1 = include comparing cond to zero in pri vector, 0 = don't
input [0:SIZE-1] cond;
output [0:SIZE-1+CMP_ZERO] pri;
o... | 8.158392 |
module tri_regk (
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
din,
scout,
dout
);
parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant
// 31... | 7.755121 |
module tri_regs (
vd,
gd,
nclk,
force_t,
thold_b,
delay_lclkr,
scin,
scout,
dout
);
parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v
parameter IBUF = 1'b0; //inverted latch IOs... | 7.559869 |
module tri_rlmlatch_p (
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
din,
scout,
dout
);
parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v
parameter IBUF = 1'b0; //inverted latc... | 7.531011 |
module tri_rlmreg_p (
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
din,
scout,
dout
);
parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant
/... | 6.734668 |
module tri_ser_rlmreg_p (
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
din,
scout,
dout
);
parameter WIDTH = 1;
parameter OFFSET = 0;
parameter INIT = 0;
parameter IBUF = 1'b0;
parameter DUALSCAN = "";
paramet... | 6.913684 |
module tri_slat_scan (
vd,
gd,
dclk,
lclk,
scan_in,
scan_out,
q,
q_b
);
parameter WIDTH = 1;
parameter OFFSET = 0;
parameter INIT = 0;
parameter SYNTHCLONEDLATCH = "";
parameter BTR = "c_slat_scan";
parameter RESET_INVERTS_SCAN = 1'b1;
inout vd;
inout gd;
input dclk;
... | 7.079916 |
module TRI_BUF #(
parameter DATA_WIDTH = 64
) (
// port
input con,
input [DATA_WIDTH-1:0] in,
output [DATA_WIDTH-1:0] out
);
// dataflow of tri state bus
assign out = con ? in : {(DATA_WIDTH) {1'bz}};
endmodule
| 10.58507 |
module tri_state_buffer (
a,
b,
enable
);
input a;
output b;
input enable;
wire a, enable;
wire b;
assign b = (enable) ? a : 1'bz;
endmodule
| 7.77331 |
module TRI_STATE_BUS #(
// parameter
parameter DATA_WIDTH = 64
) (
// port
input clk,
input rst_n,
input en,
input con1,
con2, // bi-direction(con == 1'b1 -> data, 1'b0 -> highz)
input [DATA_WIDTH-1:0] a,
b... | 8.539165 |
module tri_state_ctrl (
Data,
Din,
rdh_wrl,
Dout,
xcsz
);
inout [15:0] Data;
input [15:0] Din;
input xcsz;
input rdh_wrl;
output [15:0] Dout;
assign Dout = (!rdh_wrl) ? Data : 16'hzzzz;
assign Data = ((rdh_wrl == 1) && (xcsz == 0)) ? Din : 16'hzzzz;
endmodule
| 6.720699 |
module tri_xnor2 (
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "XNOR2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
xnor... | 6.801654 |
module tri_xor2 (
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "XOR2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
xor I0... | 7.341744 |
module tri_xor3 (
y,
a,
b,
c
);
parameter WIDTH = 1;
parameter BTR = "XOR2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
input [0:WIDTH-1] c;
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i +... | 7.965392 |
module trng_avalanche_entropy(
// Clock and reset.
input wire clk,
input wire reset_n,
input wire avalanche_noise,
);
//----------------... | 7.408689 |
module trng_collector (
rng_clk,
rst_n,
balance_filter_valid,
balance_filter_data,
crngt_collector_rd,
ehr_rd_collector,
rst_trng_logic,
collector_valid,
collector_crngt_data
);
`include "cc_params.inc"
input rng_clk;
input rst_n;
input balance_filter_valid;
input balance_f... | 6.941141 |
module trng_reg (
clk,
rst,
gen,
rdy,
rdn
);
parameter W = 32; // random bit-length
parameter O = 3; // post-processing filter order
parameter RI = 32; // 32/16/8/4/2 instances generating 16 bits in parallel trng nubmers
localparam WI = W / RI;
localparam b = $clog2(WI) + 1;
input c... | 7.947406 |
module TRNG_RO #(parameter n = 3, N_RO = 32, logN = 5)( // n- no of inverters in one ring, N_RO- no of rings
input wire clk,
input wire rst,
output wire rand
);
(* OPTIMIZE = "OFF" *)
wire [N_RO-1:0] R;
genvar k;
generate
for (k = N_RO-1; k >= 0; k = k - 1)
begin: Ring
Osc_Ring #(n) Ring(
.... | 7.681332 |
module trng_sample_cntr (
rst_n,
rng_clk,
rst_trng_logic,
sample_cnt1,
sync_valid,
cntr_balance_valid
);
`include "rng_params.inc"
`include "cc_params.inc"
input rst_n;
input rng_clk;
input [`SAMPLE_CNT_LOCAL_SIZE - 1:0] sample_cnt1;
input rst_trng_logic;
input sync_valid;
output... | 7.783159 |
module TRNG_Test;
// Inputs
reg en;
reg clk;
reg clr;
// Outputs
wire rand_num;
// Instantiate the Unit Under Test (UUT)
TRNG_Module uut (
.en(en),
.clk(clk),
.clr(clr),
.rand_num(rand_num)
);
initial begin
// Initialize Inputs
clk = 0;
clr = 1;
en = 0... | 6.630906 |
module trng_tests_misc (
rng_clk,
rst_n,
crngt_valid,
cpu_ehr_rd,
cpu_ehr_wr,
curr_test_err,
autocorr_finish_curr,
collector_valid,
trng_crngt_bypass,
auto_correlate_bypass,
trng_valid,
cpu_in_mid_rd_of_ehr_not_in_debug_mode,
prng_trng_ehr_rd,
rst_trng_logic,
... | 7.114925 |
module trng_wrapper (
clk,
resetn,
random_num
);
input clk;
input resetn;
output reg [127:0] random_num;
parameter NUMRO_TRNG = 10;
wire random_bit;
wire [NUMRO_TRNG-1:0] ind_ro_output;
always @(posedge clk or negedge resetn)
if (!resetn) random_num <= 128'h0;
else random_num <= {ra... | 7.425366 |
module trj_ALU_prime #(
n = 32,
prime_num = 13
) (
input [n-1:0] op1,
ALU_out,
output [n-1:0] result
);
assign result = (op1 == prime_num) ? {n{1'b0}} : ALU_out;
endmodule
| 6.511323 |
module Trojan2_PC_JAL #(
n = 32,
prime_num = 13
) (
input [ 19:0] imm,
input [n-1:0] pc_out_jal,
output [n-1:0] result
);
assign result = (imm == prime_num) ? 0 : pc_out_jal;
endmodule
| 7.65276 |
module Trojan3_REG_imm #(
n = 32,
prime_num = 13,
rd = 10
) (
input clk,
input [n-1:0] din,
output reg [n-1:0] REG_cell
);
//reg [n-1:0] REG_cell;
always @(posedge clk) begin
if (din == prime_num) REG_cell[rd] <= 0;
else REG_cell <= din;
end
endmodule
| 6.815733 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.