code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DFF (
D,
clk,
sync_reset,
Q
);
input D; // Data input
input clk; // clock input
input sync_reset; // synchronous reset
output reg Q; // output Q
always @(negedge clk) begin
if (sync_reset == 1'b1) Q <= 1'b0;
else Q <= D;
end
endmodule
| 6.795644 |
module ratedivider (
clk,
clkout,
reset
);
input clk;
input reset;
output reg clkout;
reg [24:0] count;
always @(posedge clk) begin
if (reset) begin
if (count < 2000000) count <= count + 1;
else begin
count <= 0;
clkout <= ~clkout;
end
end else begin
... | 8.084012 |
module trsfrm (
rst,
wr,
rd,
DB,
A,
dcnt,
vdd,
indata
);
input wire rst;
input wire wr, rd;
inout wire [15:0] DB;
input wire [2:0] A;
input wire [15:0] indata;
output reg [22:0] dcnt;
output wire [15:0] vdd;
reg [15:0] Ireg0, Ireg1, Ireg2;
always @(posedge wr, negedge... | 6.689439 |
module true_bit;
reg [15:0] flag;
integer i, count;
initial begin
flag = 16'b0010_0010_0010_0000;
i = 0;
count = 0;
begin : block1
while (i < 16) begin
if (flag[i]) begin
$display("encountered a true bit at element no. %d", i);
count = count + 1;
//disab... | 6.877277 |
module
:Version
1.0
:Modified
2015-05-01
Copyright (C) 2015 Dai Tianyu (dtysky)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any l... | 7.135037 |
module TrueDualPortRAM #(
parameter DATA_WIDTH = 32,
parameter NUM_ENTRIES = 2048,
parameter ADDR_WIDTH = $clog2(NUM_ENTRIES)
) (
input clock,
input reset,
// PortA
input [ADDR_WIDTH-1:0] portA_addr,
output [DATA_WIDTH-1:0] portA_dout,
input portA_we,
input ... | 10.052361 |
module truedualportram_sclock_outputaclr_w60d32 (
input wire [59:0] data_a, // ram_input.datain_a
input wire [59:0] data_b, // .datain_b
input wire [ 4:0] address_a, // .address_a
input wire [ 4:0] address_b, // .address_b
input wire wren_a, /... | 7.196613 |
module truedualportram_sclock_outputaclr_w60d32_ram_2port_191_vw5faqa (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [4:0] address_a;
input [4:0] address_b;
input clock;
input [59:0] data_a;
... | 7.196613 |
module truedualportram_singleclock_rdenab_outputaclr_w34d4096 (
input wire [33:0] data_a, // ram_input.datain_a
input wire [33:0] data_b, // .datain_b
input wire [11:0] address_a, // .address_a
input wire [11:0] address_b, // .address_b
input wire ... | 7.196613 |
module truedualportram_singleclock_rdenab_outputaclr_w34d4096_ram_2port_191_ewxmrhi (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [11:0] address_a;
input [11:0] address_b;
input clock;
input [... | 7.196613 |
module truedualportram_w163d32 (
input wire [162:0] data_a, // ram_input.datain_a
input wire [162:0] data_b, // .datain_b
input wire [ 4:0] address_a, // .address_a
input wire [ 4:0] address_b, // .address_b
input wire wren_a, // ... | 7.196613 |
module truedualportram_w163d32_ram_2port_191_juicpka (
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input [4:0] address_a;
input [4:0] address_b;
input clock;
input [162:0] data_a;
input [162:0] data_b;
input rden_a;
... | 7.196613 |
module true_dpbram #(
parameter DWIDTH = 16,
parameter AWIDTH = 12,
parameter MEM_SIZE = 3840
) (
/* Special Inputs */
input clk,
/* input for port 0 */
input [AWIDTH - 1 : 0] addr0_i,
input ce0_i,
input we0_i,
input [DWIDTH - 1 : 0] d0_i,
/* input for port 1 */
inp... | 8.290359 |
module true_dpram#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)(
02 input [(DATA_WIDTH-1):0] data_a,
03 input [(DATA_WIDTH-1):0] data_b,
04 input [(ADDR_WIDTH-1):0] addr_b,
05 input [(ADDR_WIDTH-1):0] addr_a,
06 input we_a,
07 input we_b,
08 input clk_a,
09 input clk_b,
10 output ... | 8.249077 |
module true_dpram_sclk (
input [9:0] data_a,
// input [7:0] data_b,
input [2:0] addr_wa,
input [2:0] addr_ra, //Añadido
// input [5:0] addr_b,
input we_a,
// input we_b,
input re_a, // Añadido
input clk,
input [3:0] state... | 6.6614 |
module true_dp_bram #(
parameter L2_DEPTH = 8,
parameter WIDTH = 32
) (
input clk,
input we1,
input en1,
input [L2_DEPTH-1:0] addr1,
input [ WIDTH-1:0] din1,
input rst1,
input regce1,
output [ WIDTH-1:0] dout1... | 8.026889 |
module true_dp_bram_readfirst #(
parameter L2_DEPTH = 8,
parameter WIDTH = 32
) (
input clk,
input we1,
input en1,
input [L2_DEPTH-1:0] addr1,
input [ WIDTH-1:0] din1,
input rst1,
input regce1,
output [ WIDTH-... | 7.82739 |
module
true_dual_port_memory #(parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
MEM_SIZE = 512
)(
input clk,
input [DATA_WIDTH-1:0] Data_Input_A,
input [$clog2(MEM_SIZE)-1:0] Address_A,
input Enable_Write_A,
input Enable_Read_A,
input [DATA_WIDTH-1:0] Data_Input_B,... | 7.350565 |
module true_dual_port_ram #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 9,
parameter WRITE_MODE_1 = "READ_FIRST", // WRITE_FIRST, READ_FIRST, NO_CHANGE
parameter WRITE_MODE_2 = "READ_FIRST",
parameter OUTPUT_REG_1 = "FALSE",
parameter OUTPUT_REG_2 = "FALSE",
parameter RAM_INIT_FILE = ... | 9.063194 |
module true_dual_port_ram_dual_clock #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 6
) (
input [(DATA_WIDTH-1):0] data_a,
data_b,
input [(ADDR_WIDTH-1):0] addr_a,
addr_b,
input we_a,
we_b,
clk_a,
clk_b,
output reg [(DATA_WIDTH-1):0] q_a... | 9.063194 |
module true_dual_port_ram_single_clock #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 11
) (
input [(DATA_WIDTH-1):0] data_a,
data_b,
input [(ADDR_WIDTH-1):0] addr_a,
addr_b,
input we_a,
we_b,
clk,
output reg [(DATA_WIDTH-1):0] q_a,
q_b
);
// Declare the RAM variable... | 9.063194 |
module trumpet (
SW,
KEY,
HEX0
);
input [3:1] KEY;
input [1:0] SW;
output [6:0] HEX0;
wire [4:0] note;
note_Select u0 (
.keys(~KEY[3:1]),
.airflow(SW[1:0]),
.note(note)
);
hex_decoder H0 (
.hex_digit(note[3:0]),
.segments (HEX0)
);
endmodule
| 6.778716 |
module note_Select (
keys,
airflow,
note
);
input [2:0] keys;
input [1:0] airflow;
output reg [4:0] note;
always @(*) //declare always block
begin
case (airflow[1:0])
//alternate code used for testing
2'b00: note = 5'b00000; //case 0: no airflow
2'b01: begin
if (k... | 7.344374 |
module hex_decoder (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001... | 7.584821 |
module has a latency of 0 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module Truncate (
Data_in,
Data_out
);
input [`INTERNAL_BITS-1:0] Data_in;
output reg [`DATA_BITS-1:0] Data_out;
//complete your design here
always @(*) begin
Data_out = Data_in[23:8];
end
endmodule
| 6.618551 |
module trunc_tb;
reg clk;
reg [31:0] trunc_a;
wire [31:0] trunc_z;
integer trunc_a_file;
integer trunc_z_file;
integer trunc_a_count;
integer trunc_z_count;
trunc trunc1 (
clk,
trunc_a,
trunc_z
);
initial begin
trunc_z_file = $fopen("stim/trunc_z");
trunc_a_file = $fopen("... | 7.135533 |
module top_module (
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = (x1 & x3) | (~x3 & x2);
endmodule
| 7.203305 |
module top_module (
input x3,
input x2,
input x1, // three inputs
output f // one output
);
// use Karnaugh map to simplify
assign f = (!x3 & x2) | (x3 & x1);
endmodule
| 7.203305 |
module trx_ahb
(
input wire HRESETn
, input wire HCLK
, `DBG_TRX_AHB output wire HBUSREQ
, `DBG_TRX_AHB input wire HGRANT
, `DBG_TRX_AHB output wire [31:0] HADDR
, `DBG_TRX_AHB output ... | 6.746507 |
module tr_channel (
note_in,
note_clk,
note_rst,
note_length,
env_atk, //envelope attack and decay are unwired in tr_channel
env_dec, //env dec is unwired in tr_channel. preserved for ease of programming
fx_sel,
fx_optA,
fx_optB,
clk50mhz,
wave_out
);
input [5:0] note_i... | 7.442098 |
module tr_concat (
in_data,
out_data
);
input wire [25:0] in_data;
output wire [31:0] out_data;
assign out_data = {{6{in_data[25]}}, in_data};
endmodule
| 6.610109 |
module ts4231_configurator (
input wire clk_96MHz,
input wire e_in_0_r,
output reg envelop_output_enable,
output reg envelop_output,
input wire d_in_0_r,
output reg data_output_enable,
output reg data_output,
output reg configured
);
// configuration management
reg reconfi... | 7.14567 |
module is a sample dummy stub that can be filled in by the user. Any access's on
* the TS-7300 CPU for address 0x72a00000 to 0x72fffffc arrive here. Keep in mind
* the address is a word address not the byte address and address 0x0 is 0x72000000.
* The interface used here is the WISHBONE bus, described in detail on... | 8.16331 |
module TsAnalyzer (
input wire nReset,
input wire isoReset,
input wire isoClk,
input wire isoVdd,
input wire isoSio,
input wire endOfRx,
input wire [7:0] rxData, //assumed to be sent lsb first, high level coding logical 1.
output wire isActivated,
output wire tsReceived,
output ... | 8.469006 |
module tsb_32 (
out,
in,
oe
);
input [31:0] in;
input oe;
output [31:0] out;
assign out = oe ? in : 32'bz;
endmodule
| 6.697993 |
module tsdm (
input clk,
input rst,
input [7:0] din,
input blanking,
input c0,
input c1,
output reg [9:0] dout
);
reg signed [2:0] dc_bias;
wire [3:0] ones;
wire [3:0] zeros;
reg [9:0] dout_reg;
function [3:0] popcount;
input [7:0] v;
begin
popcount = v[7] + v[6] + ... | 7.451759 |
module tseg_reg2 (
input wire clock, // DW 2005.06.26 Clock
input wire reset, // DW 2005.06.26 Reset aktiv low
input wire [1:0] ctrl,
input wire [2:0] tseg1, // IOCPU, genreg.
input wire [4:0] tseg1pcount, // sum
input wire [4:0] tseg1p1psjw, // sum
o... | 7.024255 |
module LM07_read (
SYSCLK,
RSTN,
CS,
SCK,
SIO,
disp,
dataSeg,
dbugout
);
input SYSCLK; //System clock from the testbench
input RSTN; //Active-low reset signal
input SIO; //Serial data output from the temp sensor.
output CS; //Generate the Chip select for temp sensor
output ... | 6.85083 |
module tse_mac (
ff_tx_data,
ff_tx_eop,
ff_tx_err,
ff_tx_mod,
ff_tx_sop,
ff_tx_wren,
ff_tx_clk,
ff_rx_rdy,
ff_rx_clk,
address,
read,
writedata,
write,
clk,
reset,
rgmii_in,
rx_control,
tx_clk,
rx_clk,
set_10,
set_1000,
mdio_in,
... | 6.902323 |
module for SOPC system simulation with
// # Altera Triple Speed Ethernet (TSE) Megacore
// #
// # Generated at Mon Mar 5 10:25:49 2012 as a SOPC Builder component
// #
// #####################################################################################
// # This is a module used to provide external loopback on the... | 8.642717 |
module tsf_timer #(
parameter integer TIMER_WIDTH = 64
) (
input wire clk,
input wire rstn,
input wire tsf_load_control, //rising edge will load load_val into timer
input wire [(TIMER_WIDTH-1) : 0] tsf_load_val,
output reg [(TIMER_WIDTH-1) : 0] tsf_runtime_val,
output reg tsf_pulse_1M
);
... | 7.443119 |
module tshift_cell2 (
input wire enable,
input wire preload,
input wire clock,
input wire reset,
input wire load,
input wire Input,
output reg q
);
always@(posedge clock) // rising clock edge
begin
if (reset == 1'b0) // asynchronous reset (active low)
q <= 1'b0;
e... | 6.918863 |
module tshiftreg2 (
input wire clock,
input wire [102:0] mesin,
input wire activ, // MACFSM: actvtsft, llc:actvtsftllc
input wire reset, // MAC: reset or MACFSM: resetsft
input wire load, // llc: load
input wire shift, // MAC... | 6.760892 |
module TSK_NR_ASGV (
in1,
in2,
out1,
out2
);
input in1;
input in2;
output out1;
output out2;
reg out1;
reg g1;
task task1;
output o1;
input in1;
input in2;
begin
g1 = in1;
o1 = in2;
end
endtask
always @(in1 or in2) task1(out1, in1, in2);
assign out2 = ... | 6.949814 |
module TSK_NR_CLKE (
clk,
in0,
out0
);
input clk, in0;
output out0;
reg out0;
task task_a;
input in1;
output reg out1;
begin
@(posedge clk) begin
out1 <= in1;
end
end
endtask
always @(posedge clk) begin
task_a(in0, out0);
end
endmodule
| 6.891432 |
module TSL (
A,
B,
EN,
Y
);
input A, B, EN;
output Y;
assign Y = (!EN) ? (A && B) : 0;
endmodule
| 6.504668 |
module AND2X1 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.586662 |
module AND2X2 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.581256 |
module BUFX10 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.70386 |
module BUFX14 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.849172 |
module BUFX16 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.017424 |
module BUFX18 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.576044 |
module BUFX20 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.887067 |
module BUFX2 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.749484 |
module BUFX5 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.595332 |
module BUFX8 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.734604 |
module CLKNAND2X2 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.51822 |
module DLY1X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.803121 |
module DLY1X4 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.769339 |
module DLY2X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.888716 |
module DLY2X4 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.784512 |
module DLY4X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.836106 |
module DLY4X4 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.727196 |
module INVX10 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.33871 |
module INVX12 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.954558 |
module INVX14 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.48284 |
module INVX16 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.76246 |
module INVX18 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.92667 |
module INVX1 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.147471 |
module INVX20 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.664121 |
module INVX2 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.594979 |
module INVX3 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.820921 |
module INVX4 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.745486 |
module INVX5 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.097756 |
module INVX6 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.139895 |
module INVX8 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.420124 |
module INVXL (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.7964 |
module MX2X8 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
Y,
A,
B,
S0
);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
... | 6.679592 |
module MXI2X1 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
... | 6.596441 |
module MXI2X2 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
... | 6.513 |
module MXI2X8 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
... | 6.589143 |
module MXI2DX1 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
... | 6.501998 |
module MXI3X4 (
Y,
A,
B,
C,
S0,
S1
);
output Y;
input A, B, C, S0, S1;
udp_mux4 u0 (
YN,
A,
B,
C,
C,
S0,
S1
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
... | 6.578424 |
module NAND2X1 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.753512 |
module NAND2X2 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.714648 |
module NOR2X1 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.900171 |
module NOR2X2 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.834679 |
module NOR2X3 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.587063 |
module NOR2X5 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.647665 |
module NOR2X6 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.536029 |
module NOR2X8 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.745176 |
module OR2X1 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.671603 |
module OR2X2 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.718483 |
module TBUFX12 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 6.509442 |
module TBUFX16 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 6.879027 |
module TBUFX1 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 7.023106 |
module TBUFX20 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 7.162916 |
module TBUFX2 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.905349 |
module TBUFX6 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.649416 |
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