code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tremolo (
input wire clk,
input wire sample_clk_en,
input wire [`BANK_NUM_WIDTH-1:0] bank_num,
input wire [`OP_NUM_WIDTH-1:0] op_num,
input wire dam, // depth of tremolo
output reg [`AM_VAL_WIDTH-1:0] am_val = 0
);
localparam TREMOLO_MAX_COUNT = 13 * 1024;
localparam TREMOLO_INDEX_WI... | 7.849965 |
module TRexDelegate #(
parameter ratio = 1
) (
input wire rst,
input wire animationClk,
input wire FrameClk,
input wire jump,
input wire duck,
input wire [1:0] gameState,
input wire [10:0] GroundY,
input wire [10:0] vgaX,
input wire [10:0] vgaY,
output wire inGrey,
output... | 7.893332 |
module tri_state_logic(
inout [31:0] signal_io,
output [31:0] signal_i,
input [31:0] signal_o,
input signal_t,
);
assign signal_io = signal_t ? 32'bz : signal_o;
assign signal_i = signal_io;
endmodule
| 7.023188 |
module tri_state_logic(
inout signal_io,
output signal_i,
input signal_o,
input signal_t,
);
assign signal_io = signal_t ? 1'bz : signal_o;
assign signal_i = signal_io;
endmodule
| 7.023188 |
module tri16bit (
input oe,
input [15:0] in,
output [15:0] out
);
assign out = oe ? in : 16'hz;
endmodule
| 8.122849 |
module short (
inout [7:0] p,
input en
);
assign p = en ? 8'h55 : 8'hzz;
endmodule
| 6.817822 |
module long (
inout [15:0] p,
input en
);
assign p = en ? 16'haaaa : 16'hzzzz;
endmodule
| 6.866635 |
module triad_decode(clock,reset,persist,triad,h_strip `triad_sm_dsp_debug);
// Version
initial $display ("triad_decode: Instantiating 4-Counter Version");
// Ports
input clock; // 40MHz system clock
input reset; // State machine to idle
input [3:0] persist; // Output persistence... | 8.612027 |
module trial (
input clock,
input reset,
input [63:0] io_in,
output [63:0] io_out,
input io_opcode
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [63:0] reg_; // @[trial.scala 11:16]
wire [63:0] _GEN_0 = io_opcode ? reg_ : io_in; //... | 6.896784 |
module trial_counter (
count,
over,
state,
submit,
trials
);
output reg [3:0] count;
output reg over;
input state;
input submit;
input [3:0] trials;
initial begin
over = 1'b0;
count = 1'b0;
end
always @(negedge submit) begin
if (state != 1) begin
over <= 1'b0;
... | 6.87459 |
module Inverter (
in,
out
);
input in;
output out;
assign out = ~in;
endmodule
| 7.198219 |
module Inverter2 (
in,
out
);
input in;
output out;
assign out = ~in;
endmodule
| 7.640496 |
module Triangle (
input clk,
input [11:0] addr,
output [7:0] dout2
);
triangular_rom D (
.clka (clk),
.addra(addr),
.douta(dout2)
);
endmodule
| 7.463184 |
module triangleany (
input clk,
input rst,
/* coordinates are registered */
input [10:0] xa,
input [10:0] ya,
input [10:0] ua,
input [10:0] va,
input [10:0] xb,
input [10:0] yb,
input [10:0] ub,
input [10:0] vb,
input [10:0] xc,
input [10:0] yc,
input [10:0] uc... | 8.312978 |
module trianglegenerator #(
parameter BITSIZE = 24,
parameter PHASESIZE = 16,
)(
input wire enable,
input wire lrclk,
input wire [PHASESIZE-1:0] freq,
output reg [BITSIZE-1:0] out,
);
reg [PHASESIZE-1:0] phase;
always @(posedge lrclk) begin
phase <= phase + freq;
end
always @(posedge lrclk) begin
... | 6.971125 |
module triangle_area(
clk,
rst,
nd,
us_rfd,
a_x,
a_y,
b_x,
b_y,
p_x,
p_y,
ds_rfd,
rdy,
area
);
input clk;
input rst;
input nd;
output us_rfd; // Upstream ready for data
input [15:0] a_x;
input [15:0] a_y;
input [15:0] b_x;
input [15:0] b_y;
input [15:0] p_x;
input [15:0] p_y;
input ds_rfd;
o... | 9.005165 |
module: triangle_area
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module triangle_area_tb;
// Inputs
reg clk;
reg rst;
reg nd;
reg [15:0] a_x;
reg [15:0] a_y;
reg [15:0] b_x;
r... | 7.79315 |
module triangle_carrier (
sys_clk,
sys_ce,
divider,
carrier
);
input sys_clk, sys_ce;
input [7:0] divider; // clock divider, switching frequency = 50e6/(divider+1)/510 Hz
output wire [7:0] carrier;
reg [7:0] count = 0;
reg [7:0] div_count = 0;
reg dp = 1; //direction to count: 1 for up,... | 8.004782 |
module triangle_channel (
note_in,
note_clk,
channel_en,
fx_sel,
clk50mhz,
wave_out
);
input [5:0] note_in;
input note_clk;
input channel_en;
input [1:0] fx_sel;
input clk50mhz;
output wire [3:0] wave_out;
wire [5:0] porta_out;
wire [5:0] fx_mux_out;
wire basefreq;
wire ... | 7.082626 |
module triangle_counter_8bit (
clk,
enable,
pulse,
sign, // 1 = negative, 0 = positive (signed bit for sine LUT)
out
);
input clk;
input enable;
input pulse;
reg direction; // 1 = right, 0 = left
output reg sign;
output reg [10:0] out;
always @(posedge clk) begin
if (!enable) b... | 6.535482 |
module triangle_gen (
CLOCK_50,
KEY,
VGA_R,
VGA_CLK
);
input CLOCK_50;
input [3:0] KEY;
output [7:0] VGA_R;
output VGA_CLK;
reg [9:0] clk_div_cnt;
reg [7:0] dac_cnt;
wire sys_clk = CLOCK_50;
wire sys_rst_n = KEY[1];
assign VGA_R = dac_cnt;
assign VGA_CLK = clk_div... | 6.994046 |
module testbench;
parameter PERIOD = 20;
reg i_clk, i_rst_n;
wire [3:0] o_dac;
triangle_gen gen_inst (
.MAX10_CLK1_50(i_clk),
.KEY({i_rst_n, 1'b0}),
.VGA_R(o_dac)
);
initial begin
i_clk = 0;
forever #(PERIOD / 2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
@... | 7.015571 |
module Triangle_Run ();
// Timing
reg CLK;
reg RES;
wire PHI1;
wire ACLK1;
wire nACLK2;
wire nLFO1;
wire nLFO2;
// Regs
reg W4008;
reg W400A;
reg W400B;
reg W401A;
reg W4015;
reg W4017;
reg n_R4015;
wire [7:0] DataBus;
wire [31:0] AuxOut;
// Tune CLK/ACLK timing according to 2A... | 7.465736 |
module BogusCPU (
PHI0,
PHI1,
PHI2
);
input PHI0;
output PHI1;
output PHI2;
assign PHI1 = ~PHI0;
assign PHI2 = PHI0;
endmodule
| 7.703679 |
module executes a "program" sequence of writes to various registers
module RegDriver (PHI1, W4008, W400A, W400B, W4015, DataBus);
input PHI1;
input W4008;
input W400A;
input W400B;
input W4015;
inout [7:0] DataBus;
// W4015 <= 00000 1 00 (Triangle Length counter enable: 1)
// W4008 <= 0 0001111 (Triangle len... | 7.110462 |
module triangle_rasterizer (
clk,
rst,
tri_ready,
us_rfd,
v1_posX,
v1_posY,
v1_posZ,
v1_colR,
v1_colG,
v1_colB,
v1_colA,
v1_texX,
v1_texY,
v2_posX,
v2_posY,
v2_posZ,
v2_colR,
v2_colG,
v2_colB,
v2_colA,
v2_texX,
v2_texY,
v3_pos... | 7.964322 |
module triangle_rom (
input clk,
input [9:0] addr,
output reg [15:0] dout
);
always @(posedge clk) dout = addr * 9'd32 - 1'b1;
endmodule
| 7.610895 |
module TriangularWave (
input clk,
output [15:0] Triangularout,
input reset,
input [31:0] phase,
input [31:0] Step
);
reg [31:0] address;
reg [31:0] SynthesisedPhase;
initial begin
address = 32'd0;
end
/**********调用TriangularROM************/
TriangularROM ROM1 (
.address(Synthe... | 7.059117 |
module is used for generating triangular waves.
Input is a clock enable signal to switch on the clock,
clock input signal and a active high reset signal to
power down the control circuit
Output are triangular waves of 4KHz waves
*/
`timescale 1 ns / 1 ns
module TriangularWaves
(
clk,
... | 8.297361 |
module Area (
input [11:0] x1,
input [11:0] y1,
input [11:0] x2,
input [11:0] y2,
input [11:0] x3,
input [11:0] y3,
output [21:0] s
);
reg [21:0] area = 0;
assign s = area;
//Utilizando a fórmula do Trabalho 2
wire [11:0] Sy2y3; //subtração y do ponto 2 e y do ponto 3
wire [... | 6.816576 |
module Mod (
input signed [17:0] i,
output signed [17:0] j
);
assign j = i[17] ? -i : i;
endmodule
| 6.917847 |
module Area (
input [8:0] x1,
input [8:0] y1,
input [8:0] x2,
input [8:0] y2,
input [8:0] x3,
input [8:0] y3,
output [17:0] s
);
wire [17:0] Ad1, Ad2; //adições
wire signed [17:0] Sub; //subtração de tudo
assign Ad1 = ((x1 * y2) + (y1 * x3) + (x2 * y3));
assign Ad2 = ((y1 * x2... | 6.816576 |
module trianguloVGA (
input CLOCK_50,
output [17:0] SRAM_ADDR,
inout [15:0] SRAM_DQ,
output SRAM_WE_N,
output SRAM_OE_N,
output SRAM_UB_N,
output SRAM_LB_N,
output SRAM_CE_N,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS
);
... | 7.61779 |
module TriArr (
input [31:0] A,
input Enable,
output [31:0] B
);
genvar i;
generate
for (i = 0; i < 32; i = i + 1) bufif1 T (B[i], A[i], Enable);
endgenerate
endmodule
| 7.285133 |
module top (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) o <= (en) ? i : 1'bZ;
endmodule
| 6.541524 |
module tribuf16 (
output [15:0] out,
input [15:0] in,
input output_en
);
generate
genvar i;
for (i = 0; i < 16; i = i + 1) begin : tribufs
tribuf tbuf (
out[i],
in[i],
output_en
);
end
endgenerate
endmodule
| 7.451137 |
module tribuf8 (
output [7:0] out,
input [7:0] in,
input output_en
);
generate
genvar i;
for (i = 0; i < 8; i = i + 1) begin : tribufs
tribuf tbuf (
out[i],
in[i],
output_en
);
end
endgenerate
endmodule
| 8.142369 |
module triBuff #(
parameter SIZE = 32
) (
in,
oe,
out
);
input [SIZE-1:0] in;
input oe;
output [SIZE-1:0] out;
assign out = oe ? in : {SIZE{1'bz}};
endmodule
| 6.618813 |
module bmux (
ctl,
in_0,
in_1,
z
);
input ctl;
input [1:0] in_0, in_1;
output [1:0] z;
CDN_bmux2 g1 (
.sel0(ctl),
.data0(in_0[1]),
.data1(in_1[1]),
.z(z[1])
);
CDN_bmux2 g2 (
.sel0(ctl),
.data0(in_0[0]),
.data1(in_1[0]),
.z(z[0])
);
endmodule... | 6.96567 |
module CDN_flop (
clk,
d,
sena,
aclr,
apre,
srl,
srd,
q
);
input clk, d, sena, aclr, apre, srl, srd;
output q;
reg qi;
assign #1 q = qi;
always @(posedge clk or posedge apre or posedge aclr)
if (aclr) qi <= 0;
else if (apre) qi <= 1;
else if (srl) qi <= srd;
els... | 7.219105 |
module DAC (
add,
clk,
strobe,
WR,
Dout
);
input wire [11:0] add;
input wire clk;
input wire strobe;
output reg WR; //Equiv of ready?
output reg [7:0] Dout;
reg [7:0] Din = 8'b00000000;
reg up = 1;
reg [31:0] counter = 0;
parameter starting = 2'b00;
parameter pre_latch = 2'b... | 6.988086 |
module Trig #(
parameter sys_clk = 24_000_000,
parameter Trig_fre = 24 //1s run 10000 times_
) (
input clk,
input rst,
output Trig_sign //signal
);
reg [25:0] Trig_num; //1ڶӦʱӸ
reg [25:0] Trig_cnt;
reg [25:0] Trig_high;
reg [25:0] Trig_sign_r;
always @(posedge clk)
if (!rst) be... | 7.785482 |
module trigen (
base_freq,
triangle_out,
en
);
input base_freq;
input en;
reg [5:0] count; //max value 63
output reg [3:0] triangle_out;
initial begin
count = 0;
triangle_out = 0;
end
always @(posedge base_freq) begin
case (count)
0: triangle_out = 0;
1: triangle_... | 7.115324 |
module TriggerBlock (
dataIn,
triggerMask,
clk_PLL,
reset,
triggerOut,
dataOut
);
input [2:0] dataIn;
input [2:0] triggerMask;
input reset;
input clk_PLL;
output triggerOut;
output [2:0] dataOut;
wire [2:0] dataIn;
wire [2:0] triggerMask;
wire reset;
wire clk_PLL;
wire ... | 6.566925 |
module TriggerFSM (
input wire Clock,
input wire Reset,
input wire [7:0] Cmd,
output wire TriggerArmed
);
localparam TRIGGER_NOT_ARMED = 1'b0, TRIGGER_ARMED = 1'b1;
reg CurrentState = TRIGGER_NOT_ARMED;
reg NextState = TRIGGER_NOT_ARMED;
//uncomment for real
assign TriggerArmed = (CurrentS... | 7.307576 |
module trigger_adjust (
input CLK,
input RSTB,
input button_u,
input button_d,
output wire [11:0] TRIG
);
reg [ 3:0] button_counter;
reg [10:0] counter;
reg [ 1:0] state;
initial begin
button_counter = 4'd6;
end
always @(posedge CLK) begin
if (~RSTB) begin
button_counter <... | 6.747171 |
module trigstate (
term_hits,
clock,
wrenb,
wraddr,
din,
hit
);
input [31:0] term_hits;
input clock;
input wrenb;
input [1:0] wraddr;
input din;
output [2:0] hit;
reg [3:0] wrenb_sum;
always @* begin
wrenb_sum = 0;
wrenb_sum[wraddr] = wrenb;
end
trigsum hit_sum (
... | 6.841926 |
module trigterm_32bit (
dataIn,
clock,
wrenb,
din,
dout,
hit
);
input [31:0] dataIn;
input clock, wrenb, din;
output dout;
output [7:0] hit;
trigterm_4bit nyb0 (
dataIn[3:0],
clock,
wrenb,
din,
n0,
hit[0]
);
trigterm_4bit nyb1 (
dataIn[7:4]... | 7.80639 |
module trigterm_4bit (
addr,
clock,
wrenb,
din,
dout,
hit
);
input [3:0] addr;
input clock, wrenb, din;
output dout, hit;
SRLC16E ram (
.A0 (addr[0]),
.A1 (addr[1]),
.A2 (addr[2]),
.A3 (addr[3]),
.CLK(clock),
.CE (wrenb),
.D (din),
.Q15(do... | 6.670147 |
module trigterm_edge (
dataIn,
dly_dataIn,
clock,
wrenb,
din,
hit
);
input [31:0] dataIn, dly_dataIn;
input clock, wrenb, din;
output hit;
wire [63:0] use_dataIn = {
dly_dataIn[31:30],
dataIn[31:30],
dly_dataIn[29:28],
dataIn[29:28],
dly_dataIn[27:26],
dataIn[27:... | 7.070796 |
module ram_dword (
clock,
addr,
wrenb,
wrdata,
rddata
);
input clock;
input [3:0] addr;
input wrenb;
input [31:0] wrdata;
output [31:0] rddata;
ram_byte byte0 (
clock,
addr,
wrenb,
wrdata[7:0],
rddata[7:0]
);
ram_byte byte1 (
clock,
addr,
... | 6.805395 |
module ram_byte (
clock,
addr,
wrenb,
wrdata,
rddata
);
input clock;
input [3:0] addr;
input wrenb;
input [7:0] wrdata;
output [7:0] rddata;
RAM16X4S ram0 (
.A0 (addr[0]),
.A1 (addr[1]),
.A2 (addr[2]),
.A3 (addr[3]),
.WCLK(clock),
.WE (wrenb),
... | 6.919521 |
module trigger_clock (
zero,
clk,
in,
out,
reset,
LED
);
input clk, zero; //clk to defin time bins, zero to set to zero counts in bins
input [31:0] in; //input from count module (button presses)
output reg [31:0] out; //output into time bins
output reg reset, LED; //reset back to co... | 6.517647 |
module trigger_clock_hundreds (
clk,
in,
out,
reset,
LED,
PIN
);
input clk;
input [7:0] in;
output reg [7:0] out = 0;
output reg reset, LED, PIN;
reg [31:0] i;
always @(posedge clk) begin
if (i==32'd250000)//5ms time bin
begin
out <= in;
reset <= 1;
LED <= !L... | 6.517647 |
module trigger_control (
trigger_activation,
trigger_level,
trigger_set,
clk_20M,
data
);
input trigger_set;
input [7:0] trigger_level;
input [7:0] data;
input clk_20M;
reg activation;
reg temp_0, temp_1;
output trigger_activation;
//触发信号只在被测信号上升沿或者下降沿时拉高一个时钟周期
assign trigger_a... | 7.10293 |
module Trigger_Controller #(
parameter DATA_WIDTH = 8
) (
input i_sys_clk,
input [DATA_WIDTH-1:0] i_data,
input [$clog2(DATA_WIDTH)-1:0] i_channel_select,
input i_trigger_type,
input i_enable,
input i_sample_clk_posedge,
input i_trigger_delay_en,
input [7:0] i_trigger_delay,
outp... | 6.831052 |
module Trigger_Controller_tb;
parameter DATA_WIDTH = 8;
reg clk, sample_clk_posedge, rst, enable, trig_type;
reg [ 2:0] channel_select;
reg [11:0] count;
wire w_triggered_state, w_trigger_pulse, w_event_pulse;
Trigger_Controller #(
.DATA_WIDTH(DATA_WIDTH)
) DUT (
.i_data(count[11:4]),
... | 6.831052 |
module Trigger_Generator (
input i_clk,
input i_rst,
input i_en, //ʹźţЧ
input i_out_level, //ƽ
input [3:0] i_width,
output o_trig
);
localparam ST_WAIT = 2'd0;
localparam ST_START = 2'd1;
localparam ST_HOLD = 2'd2;
localparam ST_END = 2'd3;
... | 8.536187 |
module trigger_in (
input wire trigger_in_pc, // PC mode trigger in
input wire trigger_in_external, // enternal mode trigger in
input wire trig_source, // 0 is PC trigger, 1 is external trigger
input wire clock, // input clock
input wire reset, // Opal Kelly reset
input wire resetflag, // ... | 6.826764 |
module trigger_info_fifo (
clk_i,
rst_i,
info_i,
wr_i,
wr_ce_i,
addr_i,
info_o,
rd_i
);
localparam INFO_BITS = `INFO_BITS;
localparam NUM_L4 = `SCAL_NUM_L4;
`include "clogb2.vh"
localparam NL4_BITS = clogb2(NUM_L4 - 1);
input clk_i;
input rst_i;
input [INFO_BITS*NUM_L4-1:0... | 7.297019 |
module trigger_input #(
parameter R = 8,
N = 3
) (
input wire clk,
rst,
input wire [R-1:0] trig_in, // input for trigger signals
input wire [R-1:0] trig_sel, // trigger selection
output wire trig_tick // output tick
);
//signal declaration
reg [N-1:0] cnt;
reg [... | 6.826347 |
module trigger_signal_gen (
clock,
reset,
output_trigger_signal
);
input clock, reset;
output output_trigger_signal;
reg [15:0] counter;
reg output_trigger_signal_gen;
always @(posedge clock or negedge reset) begin
if (!reset) begin
counter <= 8'h00;
output_trigger_signal_gen <= ... | 6.775305 |
module: trigger_top_v2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`include "wb_interface.vh"
module trigger_top_test;
// Inputs
reg [7:0] d1_trig_i;
reg [7:0] d2_trig_i;
reg [7:0... | 6.643681 |
module TrigMeas (
FAST_CK,
RSTb,
START_TDC,
STOP_TDC,
ALL_CLEAR,
TDC_SELECT,
TRIGGER_TIME_FIFO_RD,
TRIGGER_TIME_FIFO_CK,
TRIGGER_TIME_FIFO,
TRIGGER_TIME_FIFO_FULL,
TRIGGER_TIME_FIFO_EMPTY
);
input FAST_CK, RSTb, START_TDC, STOP_TDC, ALL_CLEAR;
input TDC_SELECT, TRIGGER_TI... | 6.989865 |
module trign01a (
clk,
reset_n,
in,
trigger
);
input clk;
input reset_n;
input in;
output trigger;
reg r_trigger;
reg r_stage1;
reg r_stage2;
wire w_trigger_neg;
assign trigger = r_trigger;
assign w_trigger_neg = ~r_stage1 & r_stage2;
always @(posedge clk or negedge reset_n)
... | 6.967186 |
module dividor (
clk,
inp,
rst,
out
);
input clk;
input [`INPUT_WIDTH-1:0] inp;
input rst;
//////////////inputs/////////////////
output reg [`INPUT_WIDTH-1:0] out;
//////////////output/////////////////
wire [`INPUT_WIDTH-1:0] DIVISOR = `INPUT_WIDTH'd360;
always @(posedge clk)
... | 7.703792 |
module trigp01a (
clk,
reset_n,
in,
trigger
);
input clk;
input reset_n;
input in;
output trigger;
reg r_trigger;
reg r_stage1;
reg r_stage2;
wire w_trigger_pos;
assign trigger = r_trigger;
assign w_trigger_pos = r_stage1 & ~r_stage2;
always @(posedge clk or negedge reset_n)
... | 6.724178 |
module trig_cnt (
input gclk_40m,
input l0,
input l1,
input l2a,
input l2r,
input l1out_c,
input rdocmd_c,
input abortcmd_c,
input evcntres,
input bcntres,
input trigcnt_clr,
output reg l1out = 1'b0,
output reg rdocmd = 1'b0,
output reg abortcmd = 1'b0, //widt... | 7.095927 |
module trig_count (
j,
switch,
out,
LED2
);
input j, switch;
reg [5:0] intr;
output reg [5:0] out;
output reg LED2 = 0;
always @(posedge j or posedge switch) begin
if (j) begin
LED2 <= !LED2;
out <= intr;
//intr<=6'b0;
end else if (switch) begin
intr <= intr... | 6.602655 |
module trig_generator (
clk,
rst_n,
address,
wdata,
xfc,
trig_i2si_fifo_overrun_clr,
trig_i2so_fifo_underrun_clr,
trig_filter_ovf_flag_clear
);
// Inputs
input clk; // master clock
input rst_n; // reset
input [10:0] address; // register address
input [7:0] wdata; // data t... | 6.647224 |
module trig_generator_testbench;
// Inputs
reg [10:0] address;
reg [ 7:0] wdata;
reg wxfc;
reg clk;
reg [31:0] count;
wire rst_n;
// Outputs
wire trig_i2si_fifo_overrun_clr;
wire trig_i2so_fifo_underrun_clr;
// Instantiate the Unit Under Test (UUT)
trig... | 6.647224 |
module trig_generator_testbench1;
// Inputs
reg [10:0] address;
reg [ 7:0] wdata;
reg xfc;
reg clk;
reg [31:0] count;
wire rst_n;
// Outputs
wire trig_i2si_fifo_overrun_clr;
wire trig_i2so_fifo_underrun_clr;
// Instantiate the Unit Under Test (UUT)
tri... | 6.647224 |
module triled (
RED,
GREEN,
BLUE
, rgb
);
output RED;
output GREEN;
output BLUE;
input [2:0] rgb;
assign {RED, GREEN, BLUE} = rgb;
endmodule
| 6.791025 |
module TriLoc #(
parameter N = 8
) (
input signed [N-1:0] xA,
yA,
xB,
yB,
xC,
yC,
input signed [ N:0] rA,
rB,
rC,
output signed [N+3:0] xM,
yM
);
wire signed [N+1:0] xD, yD, xE, yE, xF, yF;
one_vertex D (
.xU(xB),
.yU(yB),
.xV(xC),
.yV(yC)... | 6.615499 |
module trinalport_ram #(
parameter ADDRLEN = 10,
parameter DATALEN = 2,
parameter DEPTH = 1024
) (
input rst_n,
//port a
input clk,
input [ADDRLEN-1:0] addra,
output reg [DATALEN-1:0] rdataa,
input rea,
//port b
... | 7.833331 |
module trip (
input clk, // timespec 8.0 ns
input signed [8:0] inval,
input gate, // high for first cycle of IQ pair
input [11:0] trip_thresh,
input reset, // resets tripped state
input clear, // clears peak_val
output reg tripped,
output reg [11:0] peak_val
);
reg [7:0] in... | 6.757117 |
module TripleDES (
input clk,
input reset,
input [0:63] dataIn,
input [0:63] key1,
input [0:63] key2,
input [0:63] key3,
input encrypt,
output [0:63] dataOut
);
reg [0:63] ck1, ck2, ck3;
wire [0:63] DES1Out, DES2Out;
wire decrypt = ~encrypt;
DES DES1 (
.clk(clk),
.res... | 7.703894 |
module
module Triple_DES_Encryption(
input [63:0] i_plaintext,
input [63:0] i_key1,
input [63:0] i_key2,
input [63:0] i_key3,
output [63:0] o_ciphertext
);
wire [63:0] w_des1_ciphertext;
wire [63:0] w_des2_ciphertext;
// 1st DES
DES_Encryption DES_Encryption_inst1
(
.i_plaintext(i_plaintext) , // i... | 6.577045 |
module triple_element_product // 16 clock latency
( // ports
input clock,
input [31:0] data_in,
output [95:0] product
);
wire [31:0] mag1, mag0;
wire [63:0] mag1_mag2;
mult_gen_1 mpy_mag1_mag2 ( // 6 clock latency
.CLK(clock),
.A (data_in),
.B (mag1),
.P (mag1_mag2)
);... | 7.127805 |
module triple_mac_axi_mux (
input mux_select,
// mux inputs
input [7:0] tdata0,
input tvalid0,
input tlast0,
output reg tready0,
input [7:0] tdata1,
input tvalid1,
input tlast1,
output reg tready1,
// mux ou... | 6.541691 |
module to simplify the timing where a pattern
// generator and address swap module can be muxed into the data path
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module triple_mac_axi_pipe (
input axi_tclk,
input axi_t... | 6.900006 |
module triple_mac_clk_wiz ( // Clock in ports
input CLK_IN1_P,
input CLK_IN1_N,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//-----------------------... | 8.179008 |
module triple_mac_clk_wiz_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [4:1] CLK_OUT,
// High bits of counters driven by clocks
output [4:1] COUNT,
// Status and control sign... | 8.179008 |
module triple_mac_counter_f (
Clk,
Rst,
Load_In,
Count_Enable,
Count_Load,
Count_Down,
Count_Out,
Carry_Out
);
parameter C_NUM_BITS = 9;
parameter C_FAMILY = "nofamily";
input Clk;
input Rst;
input [C_NUM_BITS - 1:0] Load_In;
input Count_Enable;
input Count_Load;
input C... | 8.223376 |
module triple_mac (
//---------------------------------------
// asynchronous reset
input glbl_rstn,
input rx_axi_rstn,
input tx_axi_rstn,
//---------------------------------------
// Receiver Interface
input rx_axi_clk,
output rx_reset_out,
output [ 7:0] rx_axis... | 6.879914 |
module triple_mac_pselect_f (
A,
AValid,
CS
);
parameter C_AB = 9;
parameter C_AW = 32;
parameter [0:C_AW - 1] C_BAR = 'bz;
parameter C_FAMILY = "nofamily";
input [0:C_AW-1] A;
input AValid;
output CS;
wire CS;
parameter [0:C_AB-1] BAR = C_BAR[0:C_AB-1];
//-----------------------------... | 6.928343 |
module triple_mac_sync_block #(
parameter INITIALISE = 2'b00
) (
input clk, // clock to be sync'ed to
input data_in, // Data to be 'synced'
output data_out // synced data
);
// Internal Signals
wire data_sync1;
wire data_sync2;
(* ASYNC_REG = "TRUE", RLOC = "X0Y0", SHREG_EXTRACT = "... | 6.817337 |
module tri_mem_mux #(
parameter addr_bus_size = 16,
parameter data_bus_size = 16
) (
//Inputs
input [(addr_bus_size - 1):0] addr_a,
input [(data_bus_size - 1):0] data_a,
input start_a,
input rw_a,
input [(addr_bus_size - 1):0] addr_b,
input [(data_bus_size - 1):0] data_b,
inpu... | 8.778712 |
module tri_data_mux #(
parameter addr_bus_size = 16,
parameter data_bus_size = 16
) (
input [(data_bus_size - 1):0] data_x,
input [(data_bus_size - 1):0] data_y,
input [(data_bus_size - 1):0] data_z,
input [2:0] select,
output [(data_bus_size - 1):0] data_t //Data to be sent to transmissio... | 8.643411 |
module tri_ready_mux (
input wire ready_x,
input wire ready_y,
input wire ready_z,
input [2:0] select,
output ready_a,
output ready_b
);
localparam [2:0] A = 3'b000, //A->X : B->Y : D->Z
B = 3'b001, //A->X : B->Z : D->Y
C = 3'b010, //A->Y : B->x : D->Z
D = 3'b011, //A->Y : B->Z : D... | 8.274752 |
module MAINDEC (
BCLK,
RST_N,
WRITE,
READ,
STATUS,
SRAM_RDY,
ADDR,
BOOT_Q,
SRAM_Q,
UART_Q,
BE,
IO_DI,
UART_RD,
UART_WR,
CESRAM,
NMI_N,
DRD,
READY,
BRESET,
ENDRAM,
LEDR,
LEDG,
HEXL,
HEXM,
SSW
);
input BCLK;
input RST... | 7.58968 |
module UART (
BCLK,
BRESET,
UART_RD,
UART_WR,
DIN,
UA_RX,
UA_TX,
UART_Q,
UA_INT
);
input BCLK;
input BRESET;
input UART_RD;
input [1:0] UART_WR;
input [15:0] DIN;
output UA_TX;
input UA_RX;
output [31:0] UART_Q;
output UA_INT;
reg [1:0] iena; // Interrupt ena... | 7.035312 |
module SRAM (
BCLK,
BRESET,
CESRAM,
WRITE,
AA,
BE,
DIN,
READY,
SRAM_Q,
SRCO,
SRAA,
SRDB
);
input BCLK;
input BRESET;
input CESRAM;
input WRITE;
input [18:1] AA;
input [3:0] BE;
input [31:0] DIN;
output READY;
output [31:0] SRAM_Q;
output reg [4:0] S... | 7.162247 |
module triRom4096_1 (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a... | 6.762483 |
module triRom4096_2 (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a... | 6.699756 |
module triRom4096_3 (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a... | 7.012045 |
module triRom4096_4 (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a... | 6.673152 |
module triRom4096_5 (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a... | 6.631454 |
module TRIS (
inout PORT,
input DIR,
input SEND,
output READ
);
assign PORT = DIR ? SEND : 1'bZ; // Se DIR 1 -- copia DHT_OUT para saida, caso nao, deixa o pino indefinido para atuar como entrada
assign READ = DIR ? 1'bz : PORT;
endmodule
| 8.78816 |
module trisc0 #(
parameter WA = 7, // Address bit width -1
WD = 7
) // Data bit width -1
(
input clk, // System clock
input reset, // Asynchronous reset
output jc_out, // Jump condition flag
output me_ena, // Memory enable
... | 8.686465 |
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