code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Trans24To12 (
Hour24,
ncr,
Hour12
);
input [7:0] Hour24;
input ncr;
output reg [7:0] Hour12;
always @(Hour24) begin
if (!ncr) Hour12 = 8'b0000_0000;
else if (Hour24 < 8'd19) Hour12 = Hour24;
else
case (Hour24)
/*
8'b0000_0000:{HexH,HexL} <= 8'b0000_0000;
... | 7.444021 |
module trans8to1 (
rst_n,
indata_8,
outdata_P,
outdata_N,
clk
);
input rst_n, clk;
input [7:0] indata_8;
output outdata_P, outdata_N;
reg outdata_P, outdata_N;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// 复位初始化
outdata_P <= 0;
outdata_N <= 0;
... | 8.168136 |
module TransactionProb (
CLK,
Reset,
Push_fifos,
VC_ID,
DataWord,
Th_L,
Th_H,
Selector,
Matrix,
Weight,
Pop_CF,
Pop_buffer,
Set_init,
Idle,
Pause_stb,
Continue_stb,
Error_full
);
input Idle;
input [3:0] Pause_stb, Continue_stb, Error_full;
outp... | 6.71406 |
module transaction_fifo_dist (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
overflow,
prog_full,
underflow
);
input [32 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [32 : 0] dout;
output empty;
output ... | 6.726982 |
module \$paramod\fifo_sint\MEM_SIZE=8\WORD_SIZE=12\PTR=3 (
clk,
reset,
fifo_wr,
fifo_rd,
full_threshold,
empty_threshold,
fifo_data_in,
error,
almost_empty,
almost_full,
fifo_full,
fifo_empty,
fifo_data_out
);
(* src = "fifo.v:23" *)
output almost_empty;
(* src ... | 7.480712 |
module transceiver_clock (
input wire clk,
output wire sysclk_in,
output wire gt0_cplllockdetclk_in,
output wire gt0_drpclk_in,
input wire gt0_rxoutclk_out,
output wire gt0_rxusrclk_in,
output wire gt0_rxusrclk2_in,
input wire gt0_txoutclk_out,
output wire gt0_txusrclk_in,
o... | 7.033493 |
module transceiver_config (
input wire clk,
input wire rst,
/*port*/
output soft_reset_tx_in, // 复位TX FSM并且启动TX初始化，高电平复位
output soft_reset_rx_in, // 复位RX FSM并且启动RX初始化，高电平复位
output dont_reset_on_data_error_in, // 设置为0时，如果检测到错误，RX自动复位
output gt0_data_valid_in, // 此信号有效后，gt0_r... | 7.033493 |
module is an intermediate for two entities communicating through a two
// phase handshake. Signals with postfix 1 belong to the channel with the
// sending entity (i.e. req1 asks the module to transmit data1) and those with
// postfix 2 belong to the channel with the receiving entity (i.e. req2
// initiates a handshake... | 6.745243 |
module transceiver_reset (
input reset,
input clk, //init clock
output reg transceiver_dis,
output reg gtp_rst,
output reg aurora_rst
);
reg [2:0] state;
localparam IDLE = 3'd0, RESET_DIS = 3'd1, WAIT_DIS = 3'd2, WAIT_GTP = 3'd3, WAIT_RST = 3'd4;
reg [23:0] dis_100ms;
reg [23:0] dis_300ms... | 7.389824 |
module transceiver_tb ();
localparam period = 4;
localparam max_test = 50;
localparam data_size = 4;
localparam addr_size = 1;
localparam ports_num = 4;
localparam bus_size = data_size + addr_size + 1;
localparam test_size = 3 + 2 * (ports_num + 1) + bus_size * (ports_num + 1) + bus_size;
reg ... | 7.788608 |
module transceiver_write (
input wire clk,
input wire rst,
/*port*/
input wire gtx_ready,
input wire s_axi_tvalid,
input wire s_axi_tlast,
output wire s_axi_tready,
input wire [31:00] s_axi_tdata,
/*
* gt0_txcharisk_in[0] 对应 gt0_txdata_in[0... | 7.49117 |
module transceiver (
input wire Rx,
output wire Tx,
input wire start_Tx,
input wire clk,
input wire [7:0] data_in,
output wire [7:0] data_out,
output wire ready,
output wire [15:0] D_address,
output wire Rx_done,
output wire [15:0] LEDR,
output wire [7:0] LEDG,
output wir... | 7.048036 |
module transcoderDirect (
input F1,
input F0,
input en,
output reg [6:0] led_out
);
always @(*) begin
if (!en) led_out = 7'b0000000;
else begin
case ({
F1, F0
})
2'b00: led_out = 7'b0000001; //stay
2'b01: led_out = 7'b0011100; //up
2'b10: le... | 6.935652 |
module Transcoder (
output reg [15:0] out,
input [3:0] in
);
always @(*) begin
case (in)
4'd0: out[15:0] = 16'b0000000000000000;
4'd1: out[15:0] = 16'b0000000000000010;
4'd2: out[15:0] = 16'b0000000000000100;
4'd3: out[15:0] = 16'b0000000000001000;
4'd4: out[15:0] = 16'b0000... | 6.677228 |
module transcodor (
input [3:0] data_in,
output reg [6:0] data_out
);
always @(*)
case (data_in)
8'h0: data_out = 7'b1000000;
8'h1: data_out = 7'b1111001;
8'h2: data_out = 7'b0100100; //2
8'h3: data_out = 7'b0110000;
8'h4: data_out = 7'b0011001;
8'h5: data_out = 7'b0... | 6.849279 |
module transc_uart (
input clk, //Main clk input (50 MHz)
input rx, //Rx input of UART comunication
output tx, //Tx input of UART comunication
//Actual baudrate does not matter since both devices FPGAs
//... are using the same code, hence same baudrate.
inpu... | 7.224786 |
module transferencia (
Permiso_Transf,
Data_Transfer_Direction_Select,
DAT_LEN,
DAT_ADR,
transferencia_finalizada
);
parameter WAIT = 4'b0001; //DirecciónTransferencia
parameter CARD_TO_HOST = 4'b0010;
parameter HOST_TO_CARD = 4'b0100;
input Permiso_Transf;
input Data_Transfer_Direction... | 7.725215 |
module TransferFunction (
input wire clk_in,
input wire rst_in,
input wire cmd_trig_in,
input wire [15:0] cmd_addr_in,
input wire [15:0] cmd_data1_in,
input wire [15:0] cmd_data2_in,
output reg signed [15:0] sin_out,
output reg signed [15:0] cos_out,
output reg signed [23:0... | 8.345457 |
module transferstb (
i_src_clk,
i_dest_clk,
i_stb,
o_stb
);
input wire i_src_clk, i_dest_clk, i_stb;
output reg o_stb;
// Generate a sticky flip-flop
reg lcl_stb, lcl_ack;
initial lcl_stb = 1'b0;
always @(posedge i_src_clk)
if (i_stb) lcl_stb <= 1'b1;
else if (lcl_ack) lcl_stb <= 1'... | 6.552857 |
module TipoDeTransferencia (
Multi_Single_Block_Select,
Block_Count_Enable,
Transfer_Type
);
input Multi_Single_Block_Select;
input Block_Count_Enable;
output [1:0] Transfer_Type;
wire Multi_Single_Block_Select;
wire Block_Count_Enable;
reg [1:0] Transfer_Type;
reg [1:0] Temporal;
para... | 8.032533 |
module Transfer_Data_Module #(
parameter Data = 32
) (
input wire [Data-1:0] command,
output wire Reg_fifo_In_Core1,
output wire [1:0] Data_A_B_Core1,
output wire [2:0] Addr_Reg_Core1_A,
output wire [2:0] Addr_Reg_Core1_B,
output wire Msb_A_Core1,
output wire [1:0] co... | 7.767255 |
module transform (
input clk,
input rst_n,
input en,
input [8:0] data_in,
input read,
output reg finish,
output reg [31:0] data_out
);
wire [31:0] data_out_r;
reg [ 1:0] state;
reg [ 1:0] next_state;
reg [23:0] data_to_trans;
reg [ 1:0] cnt;
localparam IDLE = 1;
localpara... | 7.983857 |
module transformationPlusActivation #(
parameter dataWidth = 32,
parameter psys = 32,
parameter featureLen = 128,
parameter pactivation = 128,
parameter pavdd = 128,
parameter k = 1024
) (
clk,
rst,
enable,
// define port for weight buffer
weightWriteEnable,
weigthDataIn,... | 8.556904 |
module TransformFilter (
rst,
clk,
din,
clkdv,
dout
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟，频率为数据速率的16倍：64MHz
input signed [11:0] din; //输入数据：4MHz
output clkdv; //输出时钟：4MHz
output signed [15:0] dout; //滤波后的输出数据
wire [11:0] count16_256;
wire signed [15:0] dout_interlaced... | 8.280168 |
modules in one
***********************************************************************/
module transform_aes (
/***** INPUT */
/***** DATA SIGNALS */
input wire clk,
input wire rst_n,
input wire [127:0] data_in,
input wire [127:0] key_in,
input wire [3:0] round_in,
/**... | 7.002497 |
module transform_base64 (
input clk,
input rst_n,
input [23:0] data_in,
output [31:0] data_out
);
reg [639:0] data_insert;
reg finish_flag;
wire [639:0] data_out_w;
assign data_out = (!rst_n) ? 0 : data_out_w;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_inse... | 7.927402 |
module dequant_coeff_ram (
clk,
wr,
wr_addr,
rd_addr,
data_in,
data_out
);
parameter addr_bits = 6;
parameter data_bits = 39;
input clk;
input wr;
input [addr_bits-1:0] wr_addr;
input [addr_bits-1:0] rd_addr;
input [data_bits-1:0] data_in;
output [data_bits-1:0] data_out;
reg ... | 7.112235 |
module transform_DC_regs (
input clk,
input rst_n,
input ena,
input clr,
input [3:0] residual_state,
input wr,
input [3:0] rd_idx,
input [15:0] data_in_0,
input [15:0] data_in_1,
input [15:0] data_in_2,
input [15:0] data_in_3,
input [15:0] data_in_4,
input [15:0] data... | 7.628693 |
module: transform_mapping
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module transform_test;
// Inputs
reg clk;
reg [10:0] sin_x;
reg [10:0] sin_y;
reg [10:0] x;
reg [10:0] y;
... | 6.859781 |
module transistor_vs_gate_testbench ();
reg aa1 = 0, bb1 = 0, ee0 = 0, gg0 = 0;
wire transistor_e1, transistor_g1, gate_e1, gate_g1;
mybcs UUT1 (
.a1(aa1),
.b1(bb1),
.e0(ee0),
.g0(gg0),
.e1(transistor_e1),
.g1(transistor_g1)
);
mybcs_gatelevel UUT2 (
.a1(aa1),
.... | 7.242624 |
module translate (
input clk,
inout [3:0] sw,
output [9:0] x_out
);
parameter START_X = 256;
reg [9:0] xx = START_X;
reg [31:0] counter = 1;
reg temp_clk = 0;
always @(posedge (clk)) begin
if (counter == 2500000) begin
counter <= 1;
temp_clk <= ~temp_clk;
end else counter <= ... | 7.340418 |
module translate256x176 (
input [7:0] x,
input [7:0] y,
output reg [15:0] mem_address
);
always @(*) begin
mem_address = ({1'b0, y, 8'd0} + x);
end
endmodule
| 7.405835 |
module translateLinkSprite64x48 (
input [5:0] x,
input [5:0] y,
output reg [11:0] mem_address
);
always @(*) begin
mem_address = ({1'b0, y, 6'd0} + x);
end
endmodule
| 8.279386 |
module is to break the critical path on instruction
* address translation, since address translation using TLB introduces high
* combinatorial delay.
* This module uses the result of previous address translation to predict the
* translated address of current instruction reference.
*
* @author Yunye Pu
*/
module... | 7.55305 |
module translater (
input clk,
input reset,
input vm_enable,
input launch_translation,
output reg [31:0] physical_address,
input [31:0] virtual_address,
output translation_complete,
input [31:0] ptbr,
input flush_tlb,
/* memory interface */
output reg [31:0] translate_ad... | 6.769971 |
module translater_tb ();
wire ENB, clk, selector, selector3;
wire [6:0] in_1, in_2;
wire [31:0] in_3;
wire [6:0] out_1, out_2;
wire [31:0] out_3;
translater_p transp (
ENB,
clk,
in_1,
in_2,
in_3,
selector,
selector3
);
translater trans (
ENB,
clk,
... | 7.406074 |
module transmesconreg2 (
input wire clk,
input wire rst,
input wire cpu, // IOCPU, CPU wuenscht Zugriff
input wire can, // controller wuenscht Zugriff
input wire tsucf, // llc, successful transmission
input wire [15:0] reginp, // Register Bus (... | 7.406218 |
module Transmisor #(
parameter DBIT = 8, // #databits
SB_TICK = 16 // #ticks fors top bits
) (
input wire clk,
reset,
input wire tx_start,
s_tick,
input wire [7:0] din,
output reg TX_Done = 0,
output wire tx
);
// synlbolic s t a t e d e c l a r a t i o n
localparam [1:0] idle ... | 7.92361 |
module Transmisor_TX (
input RST,
CLK,
TX_Start,
input [7:0] DATAIN,
input s_tick,
output TX,
TX_Done
);
//wires
wire WTX_Start;
wire [7:0] WDATAIN;
UBuffer TX_Buffer (
.clk(CLK),
.rst(RST),
.r_data(TX_Start),
.datain(DATAIN),
.dataout(WDATAIN),
... | 8.092115 |
module
//In this implementation, buffer reads out pixels to VGA controller
//Copyright (C) <2018> <James Williams>
////This program is free software: you can redistribute it and/or modify
////it under the terms of the GNU General Public License as published by
////Free Software Foundation, either version 3 of the Li... | 8.472483 |
module transmitreg2 (
input wire clk,
input wire rst,
input wire cpu, // CPU wuenscht Zugriff
input wire [15:0] reginp, // Registerbus
output reg [15:0] regout // Generalregister
);
always @(posedge clk) begin
if (rst == 1'b0) begin // synchroner Reset
... | 7.363792 |
module transmitter_tb;
reg [7:0] dataInTofifo;
reg clk = 0, reset;
reg writeEn = 0;
baud_gen br1 (
.clk (clk),
.divsr(11'd650),
.reset(reset)
);
Transmitter #(8, 16) t1 (
.tx_start(~f.EMPTY),
.s_tick(br1.tick),
.tx_dataIn(f.dataOut)
);
fifo f (
.clk(clk),
... | 6.782935 |
module transmitter #(
parameter data_width = 8 //数据宽度8位
) (
input tx_clk,
input rst_n,
input [data_width-1:0] data_in,
input enable, //输入使能位
output reg tx_out
);
localparam IDLE = 3'b000;
localparam START = 3'b001; //发送低电平
localparam DATA = 3'b010;
localparam CRC = 3'b011; //校验,但暂时不... | 7.396496 |
module transmittercontrol (
input wire Rx,
output wire Tx,
input wire start_Tx,
input wire clk,
input wire [7:0] data_in,
output wire [15:0] D_address,
output wire [15:0] LEDR,
output wire [7:0] LEDG,
output wire Tx_done
);
wire tb;
wire wr_en;
reg en;
reg Rx_ready;
UART... | 7.083388 |
module transmitterNew (
input clk,
input reset,
input transmit_en,
input [35:0] to_transmitter_data,
input [18:0] transmit_address,
input [15:0] crc_tail,
input crc_done,
output reg crc_start,
output reg serial_data,
output reg [1:0] state,
output reg deserial_on,
output ... | 6.964288 |
module Transmittersint (
CLK,
PCLK,
IN_DATA,
K,
RESET_PS,
RESET_PLL,
ENB_CONV,
OUT_SERIAL
);
input CLK;
wire CLK_CONV;
wire CLK_PS;
input ENB_CONV;
wire [9:0] ENC_OUT_10B;
input [31:0] IN_DATA;
input K;
wire [7:0] OUT_CONV;
output OUT_SERIAL;
input [1:0] PCLK;
input... | 7.361723 |
module Transmittersynt (
CLK,
PCLK,
IN_DATA,
K,
RESET_PS,
RESET_PLL,
ENB_CONV,
OUT_SERIAL
);
input CLK;
wire CLK_CONV;
wire CLK_PS;
input ENB_CONV;
wire [9:0] ENC_OUT_10B;
input [31:0] IN_DATA;
input K;
wire [7:0] OUT_CONV;
output OUT_SERIAL;
input [1:0] PCLK;
input... | 6.830867 |
module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module transmitter_db(clk, rst, TxD_Start, baud_pulse, TxD_Data,
baud_gen_init, baud_gen_en, TxD, busy);... | 7.612722 |
module transmitter_dp (
clk,
load_data,
shift,
count,
set_count,
out_sel,
TxD_Data,
end_count,
TxD
);
input clk;
input load_data;
input shift;
input count;
input set_count;
input [1:0] out_sel;
input [7:0] TxD_Data;
output end_count;
output reg TxD;
reg end_cou... | 6.726929 |
module transmitter_fsm (
clk,
rst,
TxD_Start,
end_count,
baud_pulse,
load_data,
count,
shift,
set_count,
out_sel,
baud_gen_init,
baud_gen_en,
busy
);
parameter IDLE = 0, START_BIT = 1, SEND_BIT = 2, STOP_BIT = 3;
input clk;
input rst;
input TxD_Start;
inpu... | 7.847676 |
module transmitter_tb;
parameter data_width = 8;
reg tx_clk;
reg rst_n;
wire [data_width-1:0] data_in;
wire enable;
wire tx_out;
transmitter tm1 (
tx_clk,
rst_n,
data_in,
enable,
tx_out
);
transmitter_gen tg1 (
tx_clk,
rst_n,
enable,
data_in
... | 6.782935 |
module transmitter_test (
input clk,
input button,
input [7:0] i_Tx_Byte,
output serial
);
wire buttonout;
buttonlimiter(
.buttonin(button), .clk(clk), .buttonout(buttonout)
); uart_tx(
.i_Clock(clk),
.i_Tx_DV(button),
.i_Tx_Byte(i_Tx_Byte),
.o_Tx_Active(),
.o... | 6.782935 |
module TransmitTop_min_frame_tb();
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to b... | 7.798866 |
module TransmitTop_min_frame_tb();
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to b... | 7.798866 |
module TransmitTopPause_tb();
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to be inj... | 8.001368 |
module TransmitTop_tb();
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to be injected... | 7.593141 |
module transmit_debouncing #(
parameter threshold = 20
) //100000)// set parameter thresehold to guage how long button pressed
(
input clk, //clock signal
input btn1, //input buttons for transmit and reset
input stop,
input t_done,
output reg transmit //transmit signal
);
reg button_ff1 =... | 7.696014 |
module transmit_en (
transmit_en1,
transmit_en2
);
input transmit_en1;
output wire transmit_en2;
assign transmit_en2 = transmit_en1;
endmodule
| 6.613043 |
module transmit_test_entity (
//input
input clk_in,
input reset_n,
//output
output Sample_Gate, //
output [15:0] P,
output [15:0] N,
output HV_SW_CLR,
output HV_SW_LE,
output HV_SW_CLK,
output HV_SW_DOUT,
output [3:0] AX,
output [2:0] AY,
output ... | 6.750036 |
module transmit_test_entity_tb;
//input
reg clk_in;
reg reset_n;
//output
wire Sample_Gate;
wire [15:0] P;
wire [15:0] N;
wire HV_SW_CLR;
wire HV_SW_LE;
wire HV_SW_CLK;
wire HV_SW_DOUT;
wire [ 3:0] AX;
wire [ 2:0] AY;
wire ... | 6.750036 |
module transmonitor_dummy (
input wire hclk,
input wire hresetn,
// AHB-LITE MASTER PORT --------------
input wire [31:0] hmaster_m, // AHB transfer: non-sequential only
input wire hsel_m,
input wire [31:0] haddr_m, // AHB transaction address
input wire [ 2:0] ... | 8.678247 |
module BRAM_FIFO #(
parameter ALMOST_EMPTY_OFFSET = 12'h080,
parameter ALMOST_FULL_OFFSET = 12'h080
) (
input clk,
input rst,
input [15:0] din,
input wr_en,
input rd_en,
output [15:0] dout,
output full,
output empty,
output ... | 7.307344 |
module transport_in2out
/// transport input block from input pipeling memories to output pipeling memories
(
input clk, // input clock planned to be 56 Mhz
input reset, // active high asynchronous reset
// active high flag for one clock to indicate that the block should work
input S_Ready,
out... | 7.17857 |
module transport (clk,
rst_n,
router_algorithm_out_x,
router_algorithm_out_y,
router_algorithm_out_local,
control_x,
control_y,
control_local， fail,
control_clk);
inpu... | 7.410905 |
module register (
clk,
enable,
d,
q
);
input clk;
input enable;
input d;
output reg q;
always @(posedge clk) begin
if (enable == 1) q <= d;
end
endmodule
| 6.542519 |
module transposer (
clk,
i_enable,
i_sel,
i_data,
o_stream
);
parameter SEL_BITS = 4;
parameter WL = 16;
parameter WORDS = 16;
input clk;
input i_enable;
input [SEL_BITS - 1 : 0] i_sel;
input [WL * WORDS - 1 : 0] i_data;
wire [WL * WORDS - 1 : 0] q;
output [WORDS - 1 : 0] o_stream... | 6.738023 |
module transposer_array (
clk,
i_enable,
i_sel,
i_data,
o_stream
);
parameter SEL_BITS = 4;
parameter WL = 16;
parameter WORDS = 16;
parameter ARRAY_SIZE = 16;
parameter BL = WL * WORDS; // BRICK LENGTH in bits
input clk;
input [ARRAY_SIZE - 1 : 0] i_enable;
input [SEL_BITS - 1 : 0... | 7.044707 |
module register (
clk,
enable,
d,
q
);
input clk;
input enable;
input d;
output reg q;
always @(posedge clk) begin
if (enable == 1) q <= d;
end
endmodule
| 6.542519 |
module transposer (
clk,
i_enable,
i_sel,
i_data,
o_stream
);
parameter SEL_BITS = 4;
parameter WL = 16;
parameter WORDS = 16;
input clk;
input i_enable;
input [SEL_BITS - 1 : 0] i_sel;
input [WL * WORDS - 1 : 0] i_data;
wire [WL * WORDS - 1 : 0] q;
output [WORDS - 1 : 0] o_stream... | 6.738023 |
module transposer_array (
clk,
i_enable,
i_sel,
i_data,
o_stream
);
parameter SEL_BITS = 4;
parameter WL = 16;
parameter WORDS = 16;
parameter ARRAY_SIZE = 16;
parameter BL = WL * WORDS; // BRICK LENGTH in bits
input clk;
input [ARRAY_SIZE - 1 : 0] i_enable;
input [SEL_BITS - 1 : 0... | 7.044707 |
module testbench;
parameter SEL_BITS = 4;
parameter WL = 16;
parameter WORDS = 16;
reg clk;
reg enable;
reg [WORDS*WL - 1 : 0] data;
reg [ SEL_BITS : 0] sel;
wire [ WORDS - 1 : 0] stream;
initial begin
clk = 1;
data = 64'h0003000A000E000F;
... | 7.015571 |
module transpose ( //output
atrcol_out1,
atrcol_out2,
//input
col_ldata,
col_hdata,
col_out_vld,
dwt_work,
clk_tr,
rst,
rst_syn
);
output [15:0] atrcol_out1;
output [15:0] atrcol_out2;
input [15:0] col_ldata;
input [15:0] col_hdata;
input col_out_vld;
input clk_tr;
... | 6.546641 |
module tb_transposy;
reg [255:0] input1;
reg [1:0] select;
reg clk;
wire [511:0] result;
reg reset;
//Testbench specific variables
integer i;
parameter CLK_PERIOD = 10;
transpose DUT (
.dataa(input1),
.clk(clk),
.result(result),
.reset(reset),
.in_select(select)
);
... | 7.027717 |
module transpose_test (
A,
B
);
input [23:0] A; //3*2*4-1
output [23:0] B; //2*3*4-1
wire signed [3:0] A_arr[2:0][1:0];
reg signed [3:0] B_arr[1:0][2:0];
assign {{A_arr[0][0], A_arr[0][1]}, {A_arr[1][0], A_arr[1][1]}, {A_arr[2][0], A_arr[2][1]}} = A;
integer i, j;
always @* begin
for (... | 6.519533 |
module Trans_RX (
input rst_n, // Connect to system rst_n
input clk_trans, // Connect to top level transceiver clk port, 125MHz
// Used as transceiver input reference clock
input SMA_GXB_RX_p, // RX seriel receiving PIN
output rx_std_clkout, // RX output clock signal for DRAM contr... | 7.884833 |
module top (
input clk,
we,
re,
input [7:0] ra,
wa,
wd,
output reg [7:0] rd
);
reg [7:0] mem[0:255];
always @(posedge clk) begin
if (we) mem[wa] <= wd;
if (re) begin
rd <= mem[ra];
if (we && ra == wa) rd <= wd;
end
end
endmodule
| 7.233807 |
module top (
input clk,
we,
re,
input [7:0] addr,
wd,
output reg [7:0] rd
);
reg [7:0] mem[0:255];
always @(posedge clk) begin
if (we) mem[addr] <= wd;
if (re) begin
rd <= mem[addr];
if (we) rd <= wd;
end
end
endmodule
| 7.233807 |
module TRANS_TEST_RECEIVE (
input wire CLK,
input wire RESET_N,
input wire SPI_RD_SS, // : AD <- DE1
input wire SPI_RD_SCK, // : AD <- DE1
input wire SPI_RD_SD, // : AD <- DE1
output wire SPI_RD_SACK, // : AD -> DE1
output wire SPI_WR_SS, // : AD -> DE1
ou... | 6.714696 |
module TRANS_TEST_SEND (
input wire CLK,
input wire RESET_N,
output wire SPI_WR_SS, // : AD <- DE1
output wire SPI_WR_SCK, // : AD <- DE1
output wire SPI_WR_SD, // : AD <- DE1
input wire SPI_WR_SACK, // : AD -> DE1
input wire SPI_RD_SS, // : AD -> DE1
input wi... | 7.102338 |
module Tran_tb ();
reg [7 : 0] data_in;
reg reset_n,
clk,
start,
byte;
wire [7 : 0] data_o;
wire data_en;
always #5 clk = ~clk;
initial begin
clk = 0;
reset_n = 0;
data_in = ... | 6.694361 |
module trap (
input aclk,
input aresetn,
// read and write from cpu
//ar
input [3 : 0] arid,
input [ 31:0] araddr,
input [7 : 0] arlen,
input [2 : 0] arsize,
input [1 : 0] arburst,
input [1 : 0] arlock,
input [3 : 0] arcache,
input [2 : 0] arprot... | 6.551649 |
module TRAPHDLR (
input wire i_misaligned,
input wire illegal_i,
input wire l_misaligned,
input wire s_misaligned,
input wire ecall_m,
output wire exception,
output wire [`MXLEN-1:0] mcause
);
function [`MX... | 7.817335 |
module TRAP_CTRL (
input wire i_clk,
input wire i_rstn,
//自陷请求
input wire i_trap_vld,
input wire [`trapveclen_def] i_trapvec_id,
/*几个关于中断的重要csr寄存器*/
//需要读的
input wire [`xlen_def] i_csr_mstatus, //状态寄存器
input wire [`xlen_def] i_csr_mtvec, //中断向量表基地址
input wire [`xlen_def] i... | 6.66964 |
module TrashbinSOC (
input wire CoreClock,
output wire [9:0] LEDS,
output wire [7:0] LEDS_G,
output wire [15:0] HexDisplay
);
wire [31:0] DebugData;
assign LEDS[9:0] = DebugData[29:20];
assign LEDS_G[0] = DebugData[0];
assign LEDS_G[1] = StartupSignal;
assign HexDisplay = {AddressBu... | 7.471162 |
module treadmill (
input CLOCK_50,
input CLOCK_27,
input [3:0] KEY,
input [17:0] SW,
output [6:0] HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
output [8:0] LEDG,
output [17:0] LEDR
);
// SLOW THE CLOCK DOWN TO 1HZ
wire clock_1hz;
wire clock_dist;
slow_... | 8.674622 |
module treeadder(din, dout);
/* Parameter definition */
localparam NDATA = 128;
localparam NDATA_IN = 100;
localparam NDATA_LOG = $clog2(NDATA);
/* Input/output definition */
input [NDATA_IN-1:0] din;
output [NDATA_LOG:0] dout;
/* Wire/register declaration */
wire [NDATA-1:0] buffer ... | 7.086605 |
module TreeComparator(min, sec_min, values);
parameter num_values = 3;
parameter prec = 5;
output [prec-1:0] min;
output [prec-1:0] sec_min;
input [num_values*prec-1:0] values;
wire [prec-1:0] min1;
wire [prec-1:0] min2;
wire [prec-1:0] sec_min1;
wire [prec-1:0] sec_min2;
wire ... | 6.554052 |
module tree_8prior_sel (
input wire clk, //add module's work clk domin
input wire rst_n,
input wire [1*8-1:0] sel_valid,
input wire [8*8-1:0] sel_prior,
input wire [8*8-1:0] sel_index,
output wire result_valid,
output wire [7:0] result_prior,
output wire [7:0] result_index
);
... | 7.638506 |
module tree_fanout #(
parameter in_w = 128 * 8,
parameter fanout_factor = 3
) (
input clk,
input rst_n,
input up_vld,
input [in_w-1:0] up_dat,
output up_rdy,
output dn_vld,
input dn_rd... | 8.219726 |
module tree_fanout_double #(
parameter in_w = 128 * 8
) (
input clk,
input rst_n,
input up_vld,
input [in_w-1:0] up_dat,
output up_rdy,
output dn_vld,
input dn_rdy,
output [2*in_w-1:0] dn_dat
);
assign up_... | 7.449904 |
module tree_nca_routing #(
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
current_addr_encoded, // connected to current router x address
current_level, //connected to current router y address
dest_addr_enc... | 6.953444 |
module tree_conventional_routing #(
parameter ROUTE_NAME = "NCA",
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
current_addr_encoded, // connected to current router x address
current_level, //connected to c... | 6.733784 |
module tree_deterministic_look_ahead_routing #(
parameter P = 4,
parameter ROUTE_NAME = "NCA_RND_UP",
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
destport_encoded, // current router destination port
d... | 7.514567 |
module tree_look_ahead_routing #(
parameter ROUTE_NAME = "NCA",
parameter P = 4,
parameter L = 2,
parameter K = 2
) (
reset,
clk,
destport_encoded, // current router destination port
dest_addr_encoded,
neighbors_rx,
neighbors_ry,
lkdestport_encoded // look ahead destinati... | 6.941724 |
module tree_destp_generator #(
parameter K = 2,
parameter P = K + 1,
parameter SW_LOC = 0,
parameter DSTPw = 4,
parameter SELF_LOOP_EN = "NO"
) (
dest_port_in_encoded,
dest_port_out
);
localparam MAX_P = K + 1, P_1 = (SELF_LOOP_EN == "NO") ? P - 1 : P;
input [DSTPw-1:0] dest_port_in_e... | 8.27829 |
module treg (
input rst,
clk,
input ldt,
ld1,
input [15:0] mulbus,
output reg [15:0] treg
);
always @(posedge clk, posedge rst) begin
if (rst) treg <= 16'b0;
else if (ldt) treg <= mulbus;
else if (ld1) treg <= 16'b0000000100000000;
end
endmodule
| 7.328953 |
module TREG8V (
a,
en,
clk,
rst,
q
);
input [15:0] a;
input rst, clk, en;
output [15:0] q;
reg [15:0] q, val;
always @(posedge clk or posedge rst)
if (rst == 1'b1) val <= {16{1'b0}};
else val <= a;
always @(en or val)
if (en == 1'b1) q <= val;
else q <= 16'bzzzzzzzzzz... | 6.511944 |
module tRegisters;
reg [ 3:0] index;
wire [15:0] bus;
reg rEn, wEn, reset, loadBus;
reg [15:0] busVal;
busDriver driver (
busVal,
bus,
loadBus,
reset
);
register progRegisters (
index,
bus,
rEn,
wEn,
reset
);
initial begin
rEn = 0;
r... | 7.040998 |
module treg (
input rst,
clk,
input ldt,
ld1,
input [15:0] mulbus,
output reg [15:0] treg
);
always @(posedge clk, posedge rst) begin
if (rst) treg <= 16'b0;
else if (ldt) treg <= mulbus;
else if (ld1) treg <= 16'b0000000100000000;
end
endmodule
| 7.328953 |
module trellshift (
aclr,
clock,
data,
load,
q
);
input aclr;
input clock;
input [3:0] data;
input load;
output [3:0] q;
wire [3:0] sub_wire0;
wire [3:0] q = sub_wire0[3:0];
lpm_shiftreg LPM_SHIFTREG_component (
.aclr(aclr),
.clock(clock),
.data(data),
.loa... | 6.701264 |
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