code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module INVXL (
A,
Y
);
input A;
output Y;
endmodule
| 6.508461 |
module BUFX20 (
A,
Y
);
input A;
output Y;
endmodule
| 6.887067 |
module AND2X1 (
A,
B,
Y
);
input A;
input B;
output Y;
endmodule
| 6.586662 |
module AND2X2 (
A,
B,
Y
);
input A;
input B;
output Y;
endmodule
| 6.581256 |
module BUFX2 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.749484 |
module BUFX8 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.734604 |
module BUFX16 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.017424 |
module BUFX20 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.887067 |
module INVXL (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.7964 |
module INVX1 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.147471 |
module INVX2 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.594979 |
module INVX3 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.820921 |
module INVX4 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.745486 |
module INVX6 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.139895 |
module INVX8 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.420124 |
module INVX12 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.954558 |
module INVX16 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.76246 |
module INVX20 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.664121 |
module TBUFXL (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.635503 |
module TBUFX1 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 7.023106 |
module TBUFX2 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.905349 |
module TBUFX6 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.649416 |
module TBUFX8 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.928405 |
module TBUFX12 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 6.509442 |
module TBUFX16 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 6.879027 |
module TBUFX20 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 7.162916 |
module AND2X1 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.586662 |
module AND2X2 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.581256 |
module MX2X8 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2(
Y, A, B, S0
); specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
// path delays
if ((... | 6.679592 |
module MXI2X1 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2(
YN, A, B, S0
);
not (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
// p... | 6.596441 |
module MXI2X2 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2(
YN, A, B, S0
);
not (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
// p... | 6.513 |
module MXI2X8 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2(
YN, A, B, S0
);
not (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
// p... | 6.589143 |
module MXI3X4 (
Y,
A,
B,
C,
S0,
S1
);
output Y;
input A, B, C, S0, S1;
udp_mux4(
YN, A, B, C, C, S0, S1
);
not (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$C$Y = 1.0,
... | 6.578424 |
module NAND2X1 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.753512 |
module NAND2X2 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.714648 |
module NOR2X1 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.900171 |
module NOR2X2 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.834679 |
module NOR2X6 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.536029 |
module NOR2X8 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.745176 |
module OR2X1 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.671603 |
module OR2X2 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.718483 |
module DLY1X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.803121 |
module DLY2X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.888716 |
module DLY4X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.836106 |
module DLY1X4 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.769339 |
module DLY2X4 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.784512 |
module DLY4X4 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.727196 |
module AND2X1 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.586662 |
module AND2X2 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.581256 |
module BUFX16 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.017424 |
module BUFX1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.745651 |
module BUFX20 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.887067 |
module BUFX2 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.749484 |
module BUFX8 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.734604 |
module BUFXL (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.751245 |
module DLY1X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.803121 |
module DLY2X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.888716 |
module DLY4X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.836106 |
module INVX12 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.954558 |
module INVX16 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.76246 |
module INVX1 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.147471 |
module INVX20 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.664121 |
module INVX2 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.594979 |
module INVX3 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.820921 |
module INVX4 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.745486 |
module INVX8 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.420124 |
module INVXL (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.7964 |
module MXI2X1 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
... | 6.596441 |
module MXI2X2 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
... | 6.513 |
module NAND2X1 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.753512 |
module NAND2X2 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.714648 |
module NOR2X1 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.900171 |
module NOR2X2 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.834679 |
module OR2X1 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.671603 |
module OR2X2 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.718483 |
module TBUFX12 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 6.509442 |
module TBUFX16 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 6.879027 |
module TBUFX1 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 7.023106 |
module TBUFX20 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 7.162916 |
module TBUFX2 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.905349 |
module TBUFX8 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.928405 |
module TBUFXL (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
end... | 6.635503 |
module TBUFIXL (
Y,
A,
OE
);
output Y;
input A, OE;
notif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
en... | 6.787417 |
module reg_file (
clk,
reset,
write,
read_address_a,
read_address_b,
write_address,
write_data,
read_out_a,
read_out_b
);
input clk, reset, write;
input [4:0] read_address_a, read_address_b, write_address;
input [31:0] write_data;
output [31:0] read_out_a, read_out_b;
reg ... | 7.294051 |
module test;
reg [31:0] inData;
wire [63:0] outData;
bitExpand DUT (
inData,
outData
);
initial begin
inData = 32'h47584236;
#4 inData = 32'h53762368;
#4 inData = 32'hf827f463;
#4 inData = 32'hab47a7a9;
#4 $finish;
end
initial begin
$dumpfile("vars.vcd");
$dumpv... | 6.635152 |
module tstrb_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDAT... | 7.785929 |
module tstrb_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDAT... | 7.785929 |
module tstrb_system_axis_subset_converter_0_0 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)... | 6.914612 |
module tst_6502 (
input clk, // 4..0MHz CPU clock
input reset, // Low-true reset
output reg [7:0] gpio_o,
input [7:0] gpio_i,
input RX, // serial RX
output TX // serial TX
);
// The 6502
wire [15:0] CPU_AB;
reg [ 7:0] CPU_DI;
wire [ 7:0] CPU_DO;
wire CPU_WE, CPU_IRQ;
cpu_65c... | 8.655767 |
module tst_add16 ();
reg [15:0] a, b;
wire [15:0] sum;
wire cout;
add16 ins (
a,
b,
sum,
cout
);
initial begin
a = 0;
b = 255;
repeat (10) begin
#1 a = a + 1;
b = b - 1;
end
end
endmodule
| 6.863236 |
module tst_bcd ();
reg [3:0] in;
wire [9:0] out;
bcd_decoder bcd0 (
in,
out
);
integer i;
initial begin
for (i = 0; i < 16; i = i + 1) #2 in = i;
end
endmodule
| 6.732802 |
module tst_bench_spi_top ();
//
// wires && regs
//
reg clk;
reg rstn;
wire [3:0] adr;
wire [7:0] dat_i, dat_o;
wire wr;
wire rd;
reg [7:0] q, qq;
//
// Module body
//
parameter SPI_ADDR_REG = 4'b0010;
parameter SPI_TX_REG = 4'b0001;
parameter SPI_CTRL_REG = 4'b0000;
parameter SP... | 8.263252 |
module tst_clk_even ();
reg clk, rst_n;
wire clk2, clk2n;
clk_2 a (
clk,
rst_n,
clk2
);
clk_even #(4) b (
clk,
rst_n,
clk2n
);
initial begin
clk = 0;
rst_n = 0;
#2 rst_n = 1;
end
always #1 clk = ~clk;
endmodule
| 7.204704 |
module tst_clk_odd ();
reg clk, rst_n;
wire clk_out1, clk_out2;
clk_odd1 #(5) a (
clk,
rst_n,
clk_out1
);
clk_odd2 #(5) b (
clk,
rst_n,
clk_out2
);
initial begin
clk = 0;
rst_n = 0;
#2 rst_n = 1;
end
always #1 clk = ~clk;
endmodule
| 7.934489 |
module tst_counter ();
reg clk, rst_n;
wire [3:0] cnt, cnt_john, cnt_loop, cnt_gray;
counter cnt0 (
clk,
rst_n,
cnt
);
counter_john cnt1 (
clk,
rst_n,
cnt_john
);
counter_loop cnt2 (
clk,
rst_n,
cnt_loop
);
counter_gray cnt3 (
clk,
rs... | 6.876862 |
module tst_example ();
reg clk;
reg rst;
wire [9:0] score;
example A (
.clk (clk),
.rst (rst),
.score(score)
);
always #1 clk = ~clk;
always @(score) if (score > 0) $display("%d", score);
initial begin
clk = 0;
rst = 0;
#4 rst = 1;
#70000 rst = 0;
#10;
$f... | 7.010741 |
module tst_gray ();
parameter n = 4;
reg [n-1:0] bin;
wire [n-1:0] gray, out;
bin2gray #(n) b2g (
bin,
gray
);
gray2bin #(n) g2b (
gray,
out
);
initial bin = 0;
always #1 bin = bin + 1;
endmodule
| 6.921803 |
module tst_lfsr ();
reg clk, rst_n;
wire [2:0] cnt;
LFSR_counter counter (
clk,
rst_n,
cnt
);
initial begin
clk = 0;
rst_n = 0;
#2 rst_n = 1;
end
always #1 clk = ~clk;
endmodule
| 6.969972 |
module tst_sync_edge();
reg clk,rst_n,sig;
wire rise_edge,fall_edge,sig_edge;
sync_edge inst(clk,rst_n,sig,rise_edge,fall_edge,sig_edge);
initial begin
clk=0;
rst_n=0;
sig=0;
#2 rst_n=1;
#1 #0sig=1;
#6 #0sig=0;
end
always #1 clk=~clk;
endmodule... | 7.739764 |
module tst_ucodepc #(
parameter LAZY_DECODE = 0
) (
input corerunning, // Control startup
input [7:0] rinx, // From ucode
input sa28,
sa29,
sa30,
sa37, // From ucode
input sa32,
sa15, // == 2'b10 triggers ucode jmp to alternate operand fetch from ... | 7.548534 |
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